MEN Mikro F50C Manual
Contents
1. HERE SEE dar M 22 2 4 3 Thermal Considerations and Conduction Cooling 23 2 5 BUS 25 25 1 Host to PClL Bridge hn meme REESE 25 2 5 2 Local PCI Buses oc rr REESE 25 2 5 9 Local PCI Express Connections 25 2 6 Memoty e m ere ERRARE Re EE the meee 26 2 0 1 DRAM System Memory 26 202 PRAM Susu apasi E ER OE 26 26 3 eludet mobi thane 26 208 JBOODUPIashr A r E 26 2 6 5 Solid State Flash 26 2 7 Mass Storage Serial SATA SSD 27 2 8 USB eh T ORIG DIA DRE 28 2 8 1 Front Panel Connection seeni dere auca 28 2 82 Rear I O Connection CompactPCI PlusIO 28 2 9 Ethernet Interfaces isse em ee sons Rn e REFER 29 EUER 29 2 02 T0Base bee e RR eR eG eer ERREUR 29 2 03 s 00BaSe T ossi ndr bte 30 204 HNOO00BAS T sia sqan paqaq 30 2 10 CompactPCI Intetface u erp om dede nm RE em E 31 DAN Rear auci un bh rego 31 2 11 1 User Defined I O from Onboard FPGA 32 2 11 2 Standard and Possible Pin Assignments 33 3 MENMON Loss tevpbbs e v bbb See E bs ei ET 37 A General uso t mee m pee FREE 37 Ol State o2. 49 MENMON Controller Logical Units 50 MENMON Device Logical Units DLUNs 50 MENMON F50C system parameters Autodetected parameters 51 MENMON F50C system parameters Production data 52 MENMON F50C system parameters MENMON persistent parameters asc esse Sale oA edi pasas 53 MENMON F50C system parameters VxWorks bootline patamelers q uuu ses eese AUS qup aho Bad PER edP Tp Ss 55 Reset causes through system parameter rststat 35 MENMON Command reference uu uyu das ces ed hes 56 Memory processor VIEW 58 Address mapping For PCL iie m gins pa wayua TOES 58 Dedicated interrupt line assignment 59 Interrupt numbering assigned by 59 SMB 59 Onboard PCT deviees sho ch ERRORS T d E 60 16 Getting Started 1 Getting Started This chapter gives an overview of the board and some hints for first installation in a system 1 1 Maps of the Board Figure 1 Map of the board front panel view UART to USB MEN Mikro Elektronik GmbH 17 20 050 00 E2 2011 06 16 _ Started Figure 2 Map of the board top view Hexagonal wedge lock screw E wegswk i UART to USB ai J1 CompactPCI E wedge l
3. OIEF FFFF 1MB Text Reloc 0000 01 1 FFFF 1128 Stack 01 2 0000 0174 FFFF 128 Stack for user programs and operating system boot Ox 01 5 0000 FFFF 1640 Heap 0000 FFFF 164 Not touched for OS post mor tem buffer i e VxWorks WindView or MDIS debugs requires ECC to be turned off 0x 0200 0000 End of RAM Free or download area 3 6 2 2 Boot Flash Memory Table 18 MENMON Boot Flash memory map Flash Offset CPU Address Size Description 00 0000 FFOO 0000 14 MB Available to user 128 KB DE 0000 FFDE 0000 128 KB System parameter section in boot Flash if useflpar system parameter is set to 1 EO 0000 FFEO 0000 1 Secondary MENMON FO 0000 FFFO 0000 1 MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 16 3 6 3 MENMON BIOS Logical Units The following table shows fixed assigned CLUNs other CLUNs are used dynamically Table 19 MENMON Controller Logical Units CLUNs CLUN HE Description 0x02 ETHERO Ethernet 0 0 0x03 ETHER1 Ethernet 1 LAN 1 0x04 ETHER2 Ethernet 2 LAN 2 0x06 USB USB controller 0x08 UART to USB COM MPC854X DUART channel 0 0x0A TOUCH Reserved for touch console 0x10 SATAO SATA port 0 routed to SSD Flash
4. 0 11 SATA1 SATA port 1 0x12 SATA2 SATA port 2 0x20 CONSOLE1 FPGA controlled rear COM1 0x21 CONSOLE2 FPGA controlled rear COM2 0x22 CONSOLES FPGA controlled rear COMS 0x23 CONSOLE4 FPGA controlled rear COM4 All other devices dynamically detected PCI FPGA devices 0x40 Telnet console 0x41 HTTP monitor console Table 20 MENMON Device Logical Units DLUNS CLUN DLUN dios None Description 0x06 0x00 USB USB controller 0x10 0x00 SATAO Disk at SATA port 0 onboard SSD Flash 0x11 0x00 SATA1 Disk at SATA port 1 0x12 0x00 SATA2 Disk at SATA port 2 1 The actual disks can be selected through command USBDP see also page 57 MEN Mikro Elektronik GmbH 20F050C00 2011 06 16 3 6 4 System Parameters System parameters are parameters stored in EEPROM Some parameters are automatically detected by MENMON such as CPU type and frequency The parameters can be modified through the EE xxx command via the command line 3 6 4 1 Physical Storage of Parameters Most parameters are stored in the 1024 byte serial EEPROM on the F50C If required you can configure MENMON to store some strings in boot Flash rather than in EEPROM 3 6 42 Start up with Faulty EEPROM If a faulty EEPROM is detected i e the checksum of the EEPROM section is wrong the system parameters will use defaults The behavior is the same if the EEPROM is blank The default baud rate is 9600 3 6 4 3 F50C S
5. 5 1 Literature and Web Resources F50C data sheet with up to date information and documentation www men de products 02F050C html 3U conduction cooled rack data sheet www men de products 0701 0054 html 5 1 1 PowerPC MPC8548 MPC8548E PowerQUICC II Integrated Processor Family Reference Manual MPC8548ERM 2007 Freescale Semiconductor Inc www freescale com 5 1 2 SATA Serial ATA International Organization SATA IO www serialata org 5 1 3 USB Universal Serial Bus Specification Revision 1 0 1996 Compaq Digital Equip ment Corporation IBM PC Company Intel Microsoft NEC Northern Telecom www usb org 5 1 4 Ethernet ANSI IEEE 802 3 1996 Information Technology Telecommunications and Information Exchange between Systems Local and Metropolitan Area Net works Specific Requirements Part 3 Carrier Sense Multiple Access with Col lision Detection CSMA CD Access Method and Physical Layer Specifications 1996 IEEE www ieee org Charles Spurgeon s Ethernet Web Site Extensive information about Ethernet IEEE 802 3 local area network LAN technology www ethermanage com ethernet InterOperability Laboratory University of New Hampshire This page covers general Ethernet technology www iol unh edu services testing ethernet training MEN Mikro Elektronik GmbH 61 20F050C00 E2 2011 06 16 Appendix 5 1 5 CompactPCl e CompactPCI Specification PICMG 2 0 R3 0 1999 PCI Industrial Computer
6. If you want to accelerate file transfer you can select a higher baud rate in MENMON and then set the terminal emulation program accordingly MEN Mikro Elektronik GmbH 42 20F050C00 E2 2011 06 16 3 5 Diagnostic Tests 3 5 1 Ethernet Table 10 MENMON Diagnostic tests Ethernet Test Name Description Availability ETHERO Ethernet 0 1 2 LAN 0 1 2 internal Always ETHER1 loopback test except ETHER with an ETHER2 Groups POST AUTO 8543 processor ETHERO_X Ethernet 0 1 2 LAN 0 1 2 external Always ETHER1 X loopback test except ETHER with an ETHER2 X Groups NONAUTO ENDLESS MPC8543 processor 3 5 1 1 Ethernet Internal Loopback Test The test configures the network interface for loopback mode on PHY verifies that the interface s ROM has a good checksum verifies that the MAC address is valid not OXFFFFFF sends 10 frames with 0x400 bytes payload each verifies that frames are correctly received on the same interface If the network interface to test is the currently activated interface for the MENMON network stack the interface is detached from the network stack during test and reactivated after test Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Does not check Connection between PHY and physical connector Interrupt line All LAN speeds MEN Mikro Elektronik GmbH 43 20 050 00 E2 2011 06
7. It has an MEN CCA frame around a standard 3U CompactPCI card The CCA frame is a heat sink assembly with wedge locks that meets thermal requirements Please note that if you use any other heat sink assembly than the CCA frame supplied by MEN or no heat sink at all warranty on functionality and reliability of the F50C may cease If you have any questions or problems regarding thermal behavior please contact MEN The Basics of Conduction Cooling Conduction cooling is actually no cooling it is a way to transfer energy from electronic components to a position which can be cooled Aluminum or copper for instance can be used to connect the hot spots of the electronics to the outside of the housing Outside airflow must be guaranteed by forced air flow It is also possible to spread the heat to an even larger surface e g by coupling the chassis wall to a metal wall of a vehicle How the F50C is Cooled The F50C has a large CCA frame enclosing the board with a cover at the top side and a plate at the bottom side of the board Both parts have thermal interfaces to key components Heat is diverted from the components to the CCA frame cover and bottom plate and on to its wedge locks at the card s sides The F50C uses two five section wedge type locking devices wedge locks as expanders Five section expanders spread the expansion forces evenly over the board and create an efficient thermal transfer path from the board s thermal interfaces to
8. PING host lt opts gt Network connectivity test RELOC Relocate MM to RAM RST Cause an instant system reset RTC xxx lt arg gt Real time clock commands lt addr gt Single step user program SERDL passwd Update Flash using YModem protocol SETUP Open interactive Setup menu UNZIP src size lt opt gt lt dest gt lt size gt Unzip memory zipped by gzip USB lt bus gt Init USB controller and devices on a USB bus USBT lt bus gt lt p1 gt lt p5 gt Shows the USB device tree USBDP lt bus p1 p5 gt d lt x gt Display modify USB device path MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 16 Organization the Board Organization of the Board To install software on the board or to develop low level software it is essential to be familiar with the board s address and interrupt organization 4 1 Memory Mappings Table 27 Memory map processor view CPU Address Range Size Description 0x 0000 0000 End of RAM 512 1024 SDRAM 2048 MB Ox 8000 0000 DFFF FFFF 1536 PCle Memory Space Ox E000 0000 E7FF FFFF 128 MB Memory Space Ox E800 0000 EFFF FFFF 128 MB PCI2 Memory Space Ox F000 0000 F00F 0000 128 MB CCSR Ox F200 0000 F200 3FFF Config PLD Ox F300 0000 F301 FFFF FRAM opt Ox F400 0000 F41F FFFF SRAM Ox FBOO 000
9. in out This user manual describes the hardware functions of the board connection of peripheral devices and integration into a system It also provides additional information for special applications and configurations of the board The manual does not include detailed information on individual components data sheets etc A list of literature is given in the appendix History Issue Comments Date E1 First issue 2009 11 20 E2 Corrected standard rear I O configuration SATA 2011 06 16 GPIO COM interfaces SSD support Conventions This sign marks important notes or warnings concerning proper functionality of the product described in this document You should read them in any case Folder file and function names are printed in italics Bold type is used for emphasis A monospaced font type is used for hexadecimal numbers listings C function descriptions or wherever appropriate Hexadecimal numbers are preceded by Ox Hyperlinks are printed in blue color The globe will show you where hyperlinks lead directly to the Internet so you can look for the latest information online Signal names followed by or preceded by a slash indicate that this signal is either active low or that it becomes active at a falling edge Signal directions in signal mnemonics tables generally refer to the corresponding board or component in meaning to the board or component out meaning coming from it Ver
10. Check if secondary MENMON valid DegradedStartup E Secondary MENMON not valid or abort pin set 4 StartupPrologue N Determine clocks controller init SYSPARAM init Check for D pressed Parse SO DIMM SPD Init DRAM Check for d pressed Quick DRAM test Init early MMBIOS dev BEND D or d pressed DRAM not working DRAM ok 1 Relocating Y Secondary MENMON valid MainState Full Mode NE y A FullStartup Init heap in DRAM StartupPrologue MainState MEN Mikro Elektronik GmbH 20F050C00 E2 2011 06 16 MENMON Secondary MENMON Figure 5 MENMON State diagram state MENMON Main State P x Init e 5 Init on chip MMBIOS devs PCI autoconfig RTC init FPGA load Init further MMBIOS devs Check for user abort SETUP User abort gt No user intervention v Screen Menu do start network servers or degraded mode Screen oriented Main menu Selftest User abort or s pressed Perform self tests Check for user abort Touch pressed outside setup A elf test error and stignfault false TouchCalib No user intervention do touch calibration Auto Update Check N do check for u
11. Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 MEN Mikro Elektronik GmbH 20F050C00 2011 06 15 Processor core options on 5 22 Pin assignment of USB front panel 28 Signal mnemonics of USB front panel connector 28 Assignment of 16Z034_GPIO controllers 32 Pin assignment of rear I O connector J2 standard board version 33 Pin assignment of rear I O connector J2 I O options Ethernet USB SATA coneishie penio ier wd did me tutes ee Shade S ptis 34 Pin assignment of rear I O connector J2 I O options maximum FPGA Skee 35 Signal mnemonics of rear I O connector 2 36 MENMON Program update files and locations 41 MENMON Diagnostic tests Ethernet 43 MENMON Diagnostic tests SDRAM SRAM and FRAM 44 MENMON Diagnostic tests EEPROM 45 MENMON Diagnostic tests 5 46 MENMON Diagnostic tests hardware monitor 46 MENMON Diagnostic tests RTC 47 MENMON System parameters for console selection and COMMPUTANONY s uoi ea 48 MENMON Address map full featured 49 MENMON Boot Flash memory map
12. coi tie EE TN EORR POR EBEN S 38 3 2 Interacting with MENMON eee 40 3 2 1 Entering the Setup Menu Command Line 40 3 3 Configuring MENMON for Automatic Boot 40 MEN Mikro Elektronik GmbH 13 20 050 00 E2 2011 06 16 Contents 3 4 Updating Boot Flash senses 204 RR cia aaa SIR RR e gee 41 3 4 1 Update via the Serial Console using SERDL 41 3 4 2 Update from Network using 41 3 4 3 Update via Program Update Menu 41 3 4 4 Automatic Update Check 41 3 4 5 Updating MENMON 42 2 Diagnose overdose e Peppe pao 43 43 3 52 SDRAM SRAM FRAM 44 399 EEPROM dua ede 45 354 RR Pp RRAS 46 355 Hardware Monitor Test og ses eet Decem eee repr ond 46 35 0 DR RPG Pa PETER eee esas ee 47 3 6 MENMON Configuration and Organization 48 48 3 6 2 MENMON Memory 49 3 6 3 MENMON BIOS Logical Units 50 3 6 4 System Parameters see rem 51 3 7 MENMON Commands PRESE RE 56 4 Organization of the Board 58 4 1 Memory Mappings ser Ret aq Ie Rem Ree 58 42 Inte
13. does not make use of all the possible FPGA I O pins Of 46 I O pins that may be used here only 34 pins are used by the standard GPIO and COM IP cores Cf Chapter 2 11 1 1 Standard Factory FPGA Configuration on page 32 and Table 7 Pin assignment of rear I O connector J2 options maximum FPGA control on page 35 MEN Mikro Elektronik GmbH 20F050C00 2011 06 16 Functional Description The following table shows all options for non FPGA controlled interfaces For this reason only those pins are marked light green for FPGA I O that cannot be used for other functions See Table 7 Pin assignment of rear I O connector J2 options maximum FPGA control on page 35 for the assignment of the maximum number of FPGA controlled pins Table 6 Pin assignment of rear I O connector J2 I O options Ethernet USB SATA F E D C B A 7 22 GND GAO 1 GA4 GND 21 GND GND CLK6 GND 20 GND GND CLK5 GND 19 GND GND GND 18 GND GND FEDCBAZ 17 GND GND DE 16 GND GND 15 GND GND BB 14 GND GND EIE EB 13 GND GND EIE 12 GND GND EIE Bg 11 GND GND 10 GND GND BE 9 GND GND 8 GND SATA2 RX GND oo 7 GND 5 2 SATA2_TX GND BH 6 GND SATA1 RX SATA2 TX GND 5 GND SATA1 RX SATA1_TX GND 4 SATA1 TX E GND 3 GND GNT4 REQ4 GNT3 GND 2 GND
14. for informa tion on feasibility You can find more information on our web page User in FPGA FPGA Capabilities FPGA Altera Arria GX AGX35C 33 520 logic elements 1 348 416 total memory bits Connected to CPU via PCI Express x1 link Connection Available pin count 64 pins Functions available via rear I O J2 connector MEN Mikro Elektronik GmbH 9 20F050C00 E2 2011 06 16 Product Safety Product Safety A Electrostatic Discharge ESD Computer boards and components contain electrostatic sensitive devices Electrostatic discharge ESD can damage components To protect the board and other components against damage from static electricity you should follow some precautions whenever you work on your computer Power down and unplug your computer system when working on the inside Hold components by the edges and try not to touch the IC chips leads or cir cuitry Use a grounded wrist strap before handling computer components Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system Store the board only in its original ESD protected packaging Retain the original packaging in case you need to return the board to MEN for repair MEN Mikro Elektronik GmbH 10 20F050C00 E2 2011 06 16 About this Document About this Document italics bold monospace hyperlink lt x IRQst IRQ
15. the chassis wall of the board rack The energy transferred to the chassis wall can now be diverted by convection with the help of the chassis cooling fins 1 Conduction Cooled Assembly MEN Mikro Elektronik GmbH 23 20F050C00 E2 2011 06 16 Functional Description Figure 3 Conduction cooling thermal interfaces horizontal front view of CCA rack Chassis wall with cooling fins AA Airflow Card guides 9 HP CCA frame front panel top cover e Wedge lock to chassis Air flow AA CCA frame Ejector handle bottom plate MEN Mikro Elektronik GmbH 24 20F050C00 E2 2011 06 16 Functional Description 2 5 Bus Structure 2 5 1 Host to PCI Bridge The integrated host to PCI bridge is used as host bridge and memory controller for the PowerPC processor transactions of the PowerPC to the PCI bus are controlled by the host bridge The FRAM SRAM and boot Flash are connected to the local memory bus of the integrated host to PCI bridge The PCI interface is PCI bus Rev 2 2 compliant and supports all bus commands and transactions Master and target operations are possible Only big endian operation is supported 2 5 2 Local PCI Buses Two local PCI buses are controlled by the integrated host to PCI bridge One is connected to the PCI to USB bridge and runs at 33 MHz The other connects the PCI to SATA bridge and operates at 66 MHz Board versions with the MPC8543 process
16. 0 FBFF FFFF 16 MB PCIe ISA Space Ox 0000 7FFF 32 KB PCI I O Space Ox FF00 0000 FFFF FFFF 16 MB Flash Table 28 Address mapping for PCI CPU Address Range Interface Mapped to PCI Space Description 8000 0000 9FFF FFFF 0x 8000 0000 9FFF FFFF PCle memory space MEM prefetchable BARS Ox A000 0000 DFFF FFFF PCle Ox A000 0000 DFFF FFFF PCle memory space MEM non prefetchable BARs Ox E000 0000 E7FF FFFF Ox E000 0000 E7FF FFFF PCI1 memory space MEM Ox E700 0000 EFFF FFFF Ox E700 0000 EFFF FFFF PCI2 memory space MEM Ox FBOO 0000 FBFE FFFF PCle Ox 0000 0000 00FE FFFF PCle ISA memory ISA Ox FBFF 8000 FBFF FFFF PCle Ox 0000 7FFF I O PCle I O space Ox 0000 7FFF Ox 8000 FFFF I O I O space 1 not available for MPC8543 MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 16 Organization the Board 4 2 Interrupt Handling Interrupt handling is done via the 12 external interrupt lines of the CPU IRQ 11 0 While the IRQ lines 8 to 10 are used as PCI interrupt lines see Table 30 Interrupt numbering assigned by MENMON on page 59 the Ethernet function unit interrupt is routed to a dedicated interrupt line The mapping is as follows Table 29 Dedicated interrupt line assignment 854 IRQ Input Function IR
17. 16 3 5 1 2 Ethernet External Loopback Test This test is the same as the Ethernet Internal Loopback Test but requires an external loopback connector Before sending frames the link state is monitored If it is not ok within 2 seconds the test fails Note A loopback connector makes a connection between the following pins of the 8 pin Ethernet connector 1 3 2 6 4 7 5 8 Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Connection between PHY and physical connector Does not check nterrupt line All LAN speeds 3 5 2 SDRAM SRAM and FRAM Table 11 MENMON Diagnostic tests SDRAM SRAM and FRAM Test Name Description Availability SDRAM Quick SDRAM connection test Always Groups POST AUTO SDRAM X Full SDRAM test Always Groups NONAUTO ENDLESS SRAM Quick SRAM test F50C is known to have Groups POST AUTO SRAM SRAM X Full SRAM test Groups NONAUTO ENDLESS FRAM Quick FRAM test F50C is known to have Groups POST AUTO FRAM FRAM X Full FRAM test Groups NONAUTO ENDLESS MEN Mikro Elektronik GmbH 44 20 050 00 E2 2011 06 16 3 5 2 1 Quick RAM Test This quick test checks most of the connections to the RAM chips but does not test all RAM cells It executes very quickly within milliseconds This test is non destructive saves restores original RAM content Checks address lines
18. 2 bits cbr baud Baudrate of all UART consoles dec 9600 Yes Read write con0 con3 CLUN of console 0 3 hex see Chap OxFF auto No Read write ter 3 6 1 Consoles on page 48 eccsth ECC single bit error threshold 32 No Read write ecl CLUN of attached network interface OxFF No Read write hex gcon CLUN of graphics screen hex see OxFF auto No Read write Chapter 3 6 1 Consoles on page 48 hdp HTTP server TCP port decimal 1 No Read write kerpar Linux Kernel Parameters 399 chars Empty string No Read write max Part of VxWorks bootline if usefl 0 400 chars max if useflpar 1 Idlogodis Disable load of boot logo bool 0 No Read write mmstartup Start up string Empty string No Read write startup 256 chars max if 0 512 chars max if useflpar 1 nobanner Disable ASCII banner on start up 0 No Read write noecc Do not use ECC even if board supports 0 No Read write it bool nspeed0 1 3 Speed setting for Ethernet interface AUTO Yes Read write 0 3 Possible values AUTO 10HD 10FD 100HD 100FD 1000 Stdis Disable POST bool 0 No Read write stdis XXX Disable POST test with name XXX 0 No Read write bool stdis ether Internal ETHERO 1 2 loop back stdis fram FRAM test stdis sram SRAM test stdis touch Touch controller test stignfault Ignore POST failure continue boot 1 No Read write bool stwait Time in 1 10 seconds to stay at least 30 No Read write SELFTEST state decimal 0 C
19. 2011 06 16 Functional Description 2 9 3 100Base T The 100Base T networking standard supports data transfer rates up to 100 Mbits s 100Base T is actually based on the older Ethernet standard Because it is 10 times faster than Ethernet it is often referred to as Fast Ethernet Officially the 100Base T standard is IEEE 802 3u There are several different cabling schemes that can be used with 100Base T e g 100Base TX with two pairs of high quality twisted pair wires 2 9 4 1000Base T 1000Base T is a specification for Gigabit Ethernet over copper wire IEEE 802 3ab The standard defines 1 Gbit s data transfer over distances of up to 100 meters using four pairs of CAT 5 balanced copper cabling and a 5 level coding scheme Because many companies already use CAT 5 cabling 1000Base T can be easily implemented Other 1000Base T benefits include compatibility with existing network protocols 1 IPX AppleTalk existing applications Network Operating Systems network management platforms and applications MEN Mikro Elektronik GmbH 30 20 050 00 E2 2011 06 16 Functional Description 2 10 CompactPCI Interface The F50C is a 3U CompactPCI system slot board It implements a 32 bit PCI interface to the CompactPCI backplane which uses a 3 3 V signaling voltage It also tolerates 5 V The CompactPCI bus connects to the MPC8548 MPC8543 processor via a PCI Express x1 link and a PCIe to PCI bridge The pin assignment
20. 20F050CO00 E2 2011 06 16 F50C Conduction Cooled CompactPCI MPC8548 CPU User Manual mikro elektronik gmbh n rnberg F50C Conduction Cooled 3U MPC8548 CPU Board F50C Conduction Cooled 3U CompactPCI MPC8548 CPU Board The F50C is a versatile rugged PowerPC based single board computer for embedded applications with conduction cooling It is controlled by an MPC8548 or optionally an MPC8543 PowerPC CPU alternatively with encryption unit with clock frequencies between 800 MHz and 1 5 GHz The SBC is equipped with ECC controlled soldered on DDR2 RAM for data storage with up to 16 GB of solid state Flash disk for program storage as well as industrial FRAM and SRAM The CPU card provides up to three Gigabit Ethernet channels four USB ports up to two SATA interfaces and up to 64 user definable I O lines controlled by its onboard FPGA These interfaces can be combined in many variations and are all available at the rear using the board s J2 connector For first operation and service purposes the board also includes a UART to USB port accessible at the front panel The F50C is based on a standard 3BU CompactPCI card that is embedded into a dedicated CCA frame for conduction cooling conduction cooled assembly The 9 HP assembly can be used with MEN s conduction cooled subrack It is designed for operation in a 40 to 85 environment For
21. 5 1A approx Mechanical Specifications Dimensions CompactPCI 3U board embedded in MEN standard 3U CCA frame For use with MEN s conduction cooled subrack 0701 0054 Front panel 9HP with cut out for USB Weight 620g Environmental Specifications Temperature range operation 40 85 Tcase screened 0 60 Tcase screened with 16 GB SSD Flash disk Convection cooled variety F50P also available Temperature range storage 40 85 Relative humidity operation max 9596 non condensing Relative humidity storage max 9596 non condensing Altitude 300m to 3 000m Shock 15g 11ms Bump 10g 16ms Vibration sinusoidal 1g 10 150Hz Conformal coating on request MTBF 150 290h 40 C according to IEC TR 62380 RDF 2000 Safety PCB manufactured with a flammability rating of 94V 0 by UL recognized manu facturers EMC Tested according to EN 55022 radio disturbance IEC1000 4 2 ESD and IEC1000 4 4 burst BIOS MENMON MEN Mikro Elektronik GmbH 5 20F050C00 E2 2011 06 16 Technical Data Software Support Linux VxWorks QNX on request support of the FPU is currently not provided by QNX INTEGRITY Green Hills Software OS 9 on request For more information on supported operating system versions and drivers see online data sheet amp MEN Mikro Elektronik GmbH 6 20F050C00 2011 06 16 Block Diagram Boot Flash FRAM S
22. B 1 in 5 V power supply Input for client port USB 1 GND Digital ground USB USB in out USB lines differential pair 2 8 2 Rear I O Connection CompactPCI PluslO Up to four USB interfaces are accessible via rear I O in compliance with the PICMG 2 30 CompactPCI PlusIO standard See Chapter 2 11 Rear I O on page 31 for J2 rear I O pin assignments MEN Mikro Elektronik GmbH 28 20F050C00 E2 2011 06 16 PP Functional Description 2 9 Ethernet Interfaces The F50C has up to three Ethernet interfaces controlled by the CPU All channels support up to 1000 Mbits s and full duplex operation All three Ethernet channels are available at the J2 rear I O connector See Chapter 2 11 Rear I O on page 31 for J2 rear I O pin assignments Please note that LAN 2 is not available on board versions with the MPC8543 processor The unique MAC address is set at the factory and should not be changed Any attempt to change this address may create node or bus contention and thereby render the board inoperable The MAC addresses on F50C are LAN 0 0x 00 CO 3A 87 xx xx LAN I 0x 00 CO 3A 88 xx xx 2 0x 00 CO 3A 89 xx xx where 00 CO 3A is the MEN vendor code 87 88 and 89 are the MEN product codes and xx 15 the hexadecimal serial number of the product which depends on your board e g 00 2A for serial number 000042 2 9 1 General Ethernet is a local area network LAN protocol tha
23. ENMON s integrated Flash update functions allow you to do updates yourself However you need to take care and follow the instructions given here Otherwise you may make your board inoperable In any case read the following instructions carefully Please be aware that you do MENMON updates at your own risk After an incorrect update your CPU board may not be able to boot Do the following to update MENMON Unzip the downloaded file e g 14xm50 00_01_02 zip into a temporary direc tory Power on your F50C K Connect a terminal emulation program with the UART to USB port of your F50C and set the terminal emulation program to 9600 baud 8 data bits 1 stop bit no parity no handshaking if you haven t changed the target baud rate on your own Reset the F50C through software e g reboot command under VxWorks Press ESC immediately after resetting the F50C In your terminal emulation program you should see the gt prompt Enter SERDL MENMON to update the secondary MENMON You should now see a C character appear every 3 seconds In your terminal emulation program start YModem download of file 14xm50 00 01 02 smm for example with Windows Hyperterm select Trans fer Send File with protocol YModem When the download is completed reset the F50C 1 You can change the baud rate at runtime using command cons baud See Table 26 MENMON Command reference page 56
24. I PlusIO standard See Chapter 2 11 Rear I O on page 31 for J2 rear I O pin assignments MEN Mikro Elektronik GmbH 27 20F050C00 E2 2011 06 16 Functional Description 2 8 USB Interfaces The F50C provides four USB 2 0 host ports with OHCI EHCI implementation and one USB client port The client port UART to USB USB 1 is led to the front panel Up to four host ports are available via rear I O on connector J2 The host ports are controlled via PCI to USB bridges from the PowerPC processor while the client port is driven by a UART to USB converter The UART to USB interface supports data rates up to 115 2 kbits s It has no handshake lines In connection with USB to UART driver software it can be used as a COM interface and is supported by MENMON as a console device 2 8 1 Front Panel Connection The client port UART to USB USB 1 is accessible at the front panel for first operation and service purposes It is not available during normal operation of the board inside a closed conduction cooled rack Connector types 4 pin USB Series A receptacle according to Universal Serial Bus Specification Revision 1 0 Mating connector 4 pin USB Series A plug according to Universal Serial Bus Specification Revi sion 1 0 Table 2 Pin assignment of USB front panel connector 1 45V 2 USB D 3 USB 4 GND Table 3 Signal mnemonics of USB front panel connector Signal Direction Function 5 US
25. QO Ethernet Table 30 Interrupt numbering assigned by MENMON IRQ PCI oe Function MENON IRQO PCle_INTA OxFO IRQ1 PCle_INTB FPGA OxF1 IRQ2 PCle INTC OxF2 IRQ3 PCle_INTD OxF3 IRQ8 PCI_INTA SATA 0x8 IRQ9 PCI INTB 1st USB Controller 0x9 USBO 2 IRQ10 PCI INTC 2nd USB Controller USB3 4 5 4 3 SMB Devices Table 31 SMB devices Bus Address Function 0x0 Ox5E LM81 hardware monitor 2 Real time clock 0xA8 CPU EEPROM 0 2 Clock generator 0 1 OxAC ID EEPROM MEN Mikro Elektronik GmbH 59 20F050C00 E2 2011 06 16 Organization the Board 4 4 Onboard PCI Devices Table 32 Onboard PCI devices Interface Bus Device Vendor ID Device ID Function Interrupt PCI 0x00 0x00 0x1057 0x0013 PCI host bridge in MPC854X 0x10 0x1095 0x3114 SATA PCI_INTA IRQ8 PCI2 0x01 0x00 0x1057 0x0013 PCI host bridge in MPC854X 0x11 0x1033 0x0035 1st USB Controller USB0 2 PCI_INTB IRQ9 0x12 USB Controller USB3 4 5 PCI INTC IRQ10 PCle 0x02 0x00 0 1957 0x0013 PCle bridge in MPC854X 0x03 0x00 0 1208 0 0404 PCIe switch for CompactPCI 0x04 0x01 0 1208 0 0404 bus 0x02 0x03 0x05 0 00 0x1A88 0 4045 FPGA if implemented PCle INTB IRQ 1 0x06 0x00 0 1208 0 1 10 PCIe bridge CompactPCI bus MEN Mikro Elektronik GmbH 60 20 050 00 E2 2011 06 16 Appendix 5 Appendix
26. RAM EEPROM RTC lt gt Front connector Rear I O connector PowerPC 8548 Options MPC8543 Ethernet Q 10 100 1000Base T Ethernet 0 1 2 3 10 100 1000Base T 8 Ethernet Ethernet AE fas only with USB i r 8548 0 1 2 14 UART to USB lt P gt client UART and or to64 PCl to USB 7 user defined I O _ 4 ports K from FPGA MPC8543 PCI to SATA MPC8548 3 ports o 55 5 5 a 1 5 T 14 GPIOs E 9 standard example id FPGA i up to 64 user I O lines 4 5 Z Id standard example CZ Option Busless SDRAM The F50C provides great flexibility for routing functions to rear I O Additional Please refer to Configuration for more information MEN Mikro Elektronik GmbH 7 20F050C00 E2 2011 06 16 Configuration Options Configuration Options CPU Several PowerQUICC III types with different clock frequencies MPC8548 or MPC8548E GHz 1 2 GHz 1 33 GHz or 1 5 GHz MPC8543 or MPC8543E 800 MHz or 1 GHz Memory e System RAM 512MB I GBor2 GB With or without ECC Flash Disk 2GB 4GB 8 GBor 16 GB Please note that the 16 GB Flash disk component only supports a temperature range of 0 60 C FRAM OKBor 128 KB Additional SDRAM 0 MB or 32 MB With FPGA See Interf
27. REQ3 GNT2 SYSEN GND 1 GND REQ2 GNT1 REQ1 GND MEN Mikro Elektronik GmbH 34 20 050 00 E2 2011 06 16 Functional Description Table 7 Pin assignment of rear I O connector J2 I O options maximum FPGA control F E D C B A 2 22 GND GA1 GA2 GA4 GND 21 GND GND CLK6 GND 20 GND GND CLK5 GND 19 GND GND GND GND 18 GND GND PTT 17 GND GND 16 GND GND 15 GND GND 14 GND GND 13 GND GND 12 GND GND 11 GND GND 10 GND GND 9 GND GND 8 GND GND 7 GND GND 6 GND GND 5 GND GND 4 GND GND 3 GND GNT3 GND 2 GND SYSEN GND 1 GND REQ14 GND MEN Mikro Elektronik GmbH 35 20 050 00 E2 2011 06 16 Functional Description Table 8 Signal mnemonics of rear I O connector J2 SATA1_RX SATA1_RX Signal Direction Function Power GND Ground VIO in 3 3 V V I O supply voltage 3 3V in 3 3V supply voltage optional 5V in 5V supply voltage optional CompactPCI CLK 6 1 out Clocks 1 to 6 GA 4 0 in Geographic addressing signals 0 to 4 GNT 6 1 out Grant 1 to 6 REQ 6 1 in Request 1 to 6 SYSEN in System slot identification Differential SATA receive lines port 1 SATA1_TX SATA1_TX out Differential SATA transmit lines port 1 SATA2_RX SATA2_RX Differential SATA receive lines port 2 SATA2_TX SATA2_TX Differential SATA transmit l
28. Serial are registered trademarks of the PCI Industrial Computer Manufacturers Group COM Express is a trademark of PCI Industrial Computer Manufacturers Group OS 9 OS 9000 and SoftStax are registered trademarks of RadiSys Microware Communications Software Division Inc FasTrak and Hawk are trademarks of RadiSys Microware Communications Software Division Inc RadiSys is a registered trademark of RadiSys Corporation PCI Express and PCIe are registered trademarks of PCI SIG QNX is a registered trademark of QNX Ltd Tornado and VxWorks are registered trademarks of Wind River Systems Inc All other products or services mentioned in this publication are identified by the trademarks service marks or product names as designated by the companies who market those products The trademarks and registered trademarks are held by the companies producing them Inquiries concerning such trademarks should be made directly to those companies All other brand or product names are trademarks or registered trademarks of their respective holders Information in this document has been carefully checked and is believed to be accurate as of the date of publication however no responsibility is assumed for inaccuracies MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability function or d
29. ace Configuration Matrix showing possible I O combinations Ethernet Upto three channels at rear Only two channels total with MPC8543 SATA Upto two channels at rear Up to 64 user defined I O lines With optional FPGA Reduces number of Ethernet SATA channels Cooling concept Convection cooled variety F50P also available for up to 40 85 C Please note that some of these options may only be available for large volumes Please ask our sales staff for more information MEN Mikro Elektronik GmbH 8 20F050C00 E2 2011 06 16 Interface Configuration Matrix FPGA I O pins No FPGA 23 34 45 56 27 38 49 60 31 42 53 64 Front 1 UART to USB client service port Rear I O 3 ETH 3 ETH 2 ETH 1 ETH 3 ETH 2 ETH 1 ETH 2 ETH 1 ETH 2 SATA 2 SATA 2SATA 2SATA 2SATA 1SATA 1 SATA 1 SATA 1 SATA 4 USB Form factor 9 HP The standard configuration is highlighted in bold blue in the table rear Ethernet interfaces include 2 LED signals each These could also be used for other FPGA functions instead if no LEDs and more I O pins are needed lt For available standard configurations see online data sheet FPGA Flexible Configuration This MEN board offers the possibility to add customized I O functionality in FPGA t depends on the board type pin counts and number of logic elements which IP cores make sense and or can be implemented Please contact MEN
30. ck RQ signals Partition table or file system on disk 3 5 5 Hardware Monitor Test Table 14 MENMON Diagnostic tests hardware monitor Test Name Description Availability LM81 LM81 basic access test Always Groups POST AUTO MEN Mikro Elektronik GmbH 46 20 050 00 E2 2011 06 16 3 5 6 Table 15 MENMON Diagnostic tests Test Name Description Availability RTC Quick presence test of RTC Always Groups POST AUTO RTC X Extended test of RTC Always Groups NONAUTO ENDLESS 3 5 6 1 RTC Test This is a quick presence test of the real time clock RTC and is executed on POST Checks Presence of RTC PC access Does not check If RTC is running RTC backup voltage 3 5 6 2 Extended RTC Test Checks Presence e g PC access is running Does not check RTC backup voltage MEN Mikro Elektronik GmbH 47 20 050 00 E2 2011 06 16 3 6 3 6 1 Consoles MENMON Configuration and Organization MENMON You can select the active consoles by means of system parameters and configure the console through parameters ecl gcon and tdp MENMON commands CONS xxx also give access to the console settings see Chapter 3 7 MENMON Commands page 56 Table 16 MENMON System parameters for console selection and configuration Parameter m User alias Descript
31. convection cooling the F50P model is also available which comes with a tailor made heat sink for extended temperatures The large FPGA on the F50C allows to add additional user defined functions such as graphics touch serial interfaces fieldbus controllers binary I O etc for the needs of the individual application in an extremely flexible way Before boot up of the system the FPGA is loaded from boot Flash Updates of the FPGA contents can be made inside the boot Flash during operation Equipped with a PCI bridge chip the F50C offers a full CompactPCI interface system slot functionality for reliable system expansion Apart from that the F50C can also be used as a busless stand alone board with power supply from the backplane The soldered components on the F50C withstand shock and vibration and the board design is optimized for conformal coating The F50C comes with MENMON support This firmware BIOS can be used for bootstrapping operating systems from disk Flash or network for hardware testing or for debugging applications without running any operating system MEN Mikro Elektronik GmbH 2 20F050C00 E2 2011 06 16 Technical Data Technical Data CPU PowerPC PowerQUICC MPC8548 MPC8548E MPC8543 or MPC8543E 800MHz up to 1 5GHz Please see Configuration Options for available standard versions e500 PowerPC core with MMU and double precision embedded scalar and vector floating point APU Integ
32. data lines Byte enable signals ndirectly checks clock and other control signals Does not check SDRAM cells Burst mode 3 5 2 2 Extended RAM Test This full featured memory test allows to test all RAM cells Depending on the size of the SDRAM this test can take up to one minute It tests 8 16 or 32 bit access each with random pattern and single and burst access On each pass this test first fills the entire memory starting with the lowest address with the selected pattern using the selected access mode and then verifies the entire block This test is destructive Checks All address lines All data lines All control signals All SDRAM cells 3 5 3 EEPROM Table 12 MENMON Diagnostic tests EEPROM Test Name Description Availability EEPROM access Magic nibble check Always Groups POST AUTO ENDLESS This test reads the first EEPROM cell over SMB and checks if bits 3 0 of this cell contain the magic nibble MEN Mikro Elektronik GmbH 45 20 050 00 E2 2011 06 16 3 5 4 USB Table 13 MENMON Diagnostic tests USB Test Name Description Availability USBO USB5 USB device access sector 0 Always access Groups NONAUTO ENDLESS The test performs a sector 0 read from the Flash disk without verifying the content of the sector Checks e USB control lines Data Data Basic USB transfer Does not che
33. esign MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document Copyright 2011 MEN Mikro Elektronik GmbH rights reserved S Please recycle Germany France USA MEN Mikro Elektronik GmbH MEN Mikro Elektronik SA MEN Micro Inc Neuwieder Stra e 5 7 18 rue Ren Cassin 24 North Main Street 90411 Nuremberg ZA de la Chatelaine Ambler PA 19002 Phone 49 911 99 33 5 0 74240 Gaillard Phone 215 542 9575 Fax 49 911 99 33 5 901 Phone 33 0 450 955 312 Fax 215 542 9577 E mail info men de Fax 33 0 450 955 211 E mail sales menmicro com www men de E mail info men france fr www menmicro com www men france fr MEN Mikro Elektronik GmbH 12 20F050C00 E2 2011 06 16 Contents Contents 1 Getting Started us oso a coder Sv mae tono m me E 17 LE Boatd auia 17 1 2 Integrating the Board into a System 19 1 3 Installing Operating System Software 20 1 4 Installing Driver 20 2 Functional Description e rr re o 21 2 Power ana db Rd SR ORC 21 2 2 Board Supervisi n ne A qaqaqa 21 2 3 Real lime Clock 21 24 Processor ee ee 22 24
34. h a password in the serial download function of MENMON cf Chapter 3 4 1 Update via the Serial Console using SERDL on page 41 2 6 5 Solid State Flash Disk The board includes up to 16 GB soldered NAND Flash disk A solid state disk SSD is data storage device that uses solid state memory to store persistent data An SSD behaves like a conventional hard disk drive On F50C it has a PATA interface connected to a SATA to PATA bridge and controlled by one SATA channel See also Chapter 2 7 Mass Storage Serial ATA SATA SSD on page 27 With no moving parts a solid state disk is more robust effectively eliminating the risk of mechanical failure and usually enjoys reduced seek time and latency by removing mechanical delays associated with a conventional hard disk drive MEN Mikro Elektronik GmbH 26 20F050C00 E2 2011 06 16 Functional Description 2 7 Mass Storage Serial ATA SATA SSD The F50C provides three serial ATA channels through a PCI to SATA converter that is connected to the PowerPC processor via a dedicated 66 MHz PCI bus On board versions with the MPC8543 processor PCI to SATA shares one 33 MHz PCI bus with PCI to USB The SATA interfaces support 1 5 Gbits s One SATA channel is used for the SSD solid state Flash disk See also Chapter 2 6 5 Solid State Flash Disk on page 26 The other two SATA channels are led to the rear I O J2 connector The pin assignment is in compliance with the PICMG 2 30 CompactPC
35. holds the CPU in reset condition until all supply voltages are within their nominal values In addition the board contains a PLD watchdog that must be triggered After configuration the CPU serves the PLD watchdog The watchdog timeout is automatically set to 1 12 s after the first trigger pulse by the CPU The watchdog can be enabled or disabled through MENMON and can be triggered by a software application This function is normally supported by the board support package see BSP documentation Another watchdog device on the board has to be triggered by the FPGA and asserts a reset if the FPGA fails 2 3 Real Time Clock The board includes an RA8581 real time clock Interrupt generation of the RTC is not supported For data retention during power off the RTC is supplied by a GoldCap A control flag indicates a back up power fail condition In this case the contents of the RTC cannot be expected to be valid A message will be displayed on the MENMON console in this case MEN Mikro Elektronik GmbH 21 20F050C00 E2 2011 06 16 Functional Description 2 4 The board is equipped with the MPC8548 or MPC8543 processor which includes a 32 bit PowerPC e500 core the integrated host to PCI bridge Ethernet controllers and UARTs Processor Core 2 4 1 The MPC8548 3 family of processors integrates an e500v2 processor core built on Power Architecture technology with system logic required for networking telecommunications and wireles
36. ines port 2 GPIO GPIO1_ 6 0 GPIO2_ 6 0 in out GPIO pins 2 x 7 lines on controllers 1 FPGA and 2 COM1 4 COM 2 1 _CTS in Clear to send COM1 COM2 FPGA COM 2 1 _ DCD in Data carrier detected COM1 COM2 COM 2 1 _DSR in Data set ready COM1 COM2 COM 2 1 _DTR out Data terminal ready COM1 COM2 COM 2 1 _Ri in Ring indicator COM1 COM2 COM 2 1 _ RTS out Request to send COM1 COM2 COM 4 1 _ RXD in Receive data COM 4 1 _TXD out Transmit data MEN Mikro Elektronik GmbH 20F050C00 2011 06 16 3 3 1 MENMON is the CPU board firmware that is invoked when the system is powered on The basic tasks of MENMON are Initialize the CPU and its peripherals PCI PCle auto configuration Perform self test Provide debug diagnostic features on MENMON command line Interaction with the user via touch panel TFT display if supported through FPGA Boot operating system Update firmware or operating system The following description only includes board specific features For a general description and in depth details on MENMON please refer to the MENMON 2nd Edition User Manual MEN Mikro Elektronik GmbH 37 20F050C00 E2 2011 06 16 3 1 1 Figure 4 State diagram Degraded Mode Full Mode State Diagram 5 Degraded Mode Earlylnit do CPU early init
37. ion Default Access cbr baud Baud rate of all UART consoles 9600 Read write decimal default 9600 baud 8n1 con0 con3 CLUN of console 0 3 con0 08 UART Read write CLUN 0x00 disable to USB COM CLUN 0xFF Autoselect next avail con1 00 none able console con2 00 none con0 is implicitly the debug console con3 00 none ecl CLUN of attached network interface 0xF F Read write hex CLUN 0x00 none CLUN 0xFF first available Ether net gcon CLUN of graphics device to display 0xFF AUTO Read write boot logo CLUN 0x00 disable CLUN 0xFF Autoselect first avail able graphics console hap HTTP server TCP port decimal 1 Read write 0 don t start telnet server 1 use default port 23 else TCP port for telnet server tdp Telnet server TCP port decimal 1 Read write 0 don t start HTTP server 1 use default port 80 else TCP port for HTTP server MEN Mikro Elektronik GmbH 48 20F050C00 E2 2011 06 16 3 6 2 3 6 2 1 MENMON Memory Address Mapping Table 17 MENMON Address map full featured mode Address Space Size Description Ox 0000 0000 0000 1400 5KB Exception vectors 0000 3000 0000 3FFF 14 MENMON parameter string Ox 0000 4200 0000 42FF 256 bytes VxWorks bootline Ox 0000 4300 OOFF FFFF Nearly Free 16 MB Ox 0100 0000 O1DF FFFF 2MB Heap2 Ox 0000
38. ist also using the H command Table 26 MENMON Command reference Command Description lt gt val Display modify registers in debugger model ACT lt addr gt lt size gt Execute a HWACT script ARP Dump network stack ARP table B DC no lt addr gt Set display clear breakpoints BIOS DBG lt gt net cons lt clun gt Set MENMON BIOS or network debug level set debug console BO lt addr gt lt opts gt Call OS bootstrapper BOOTP lt opts gt Obtain IP config via BOOTP C BWLLNAX lt addr gt lt val gt Change memory CHAM lt clun gt Dump FPGA Chameleon table CONS Show active consoles CONS ACT lt clun1 gt lt clun2 gt Test console configuration CONS BAUD lt baud gt Change baud rate instantly without storing CONS GX clun Test graphics console D lt addr gt lt cnt gt Dump memory DBOOT clun lt dlun gt lt opts gt Boot from disk DCACHE OFF ON Enable disable data cache DIAG lt which gt VTF Run diagnostic tests DSKRD lt args gt Read blocks from RAW disk DSKWR lt args gt Write blocks to RAW disk EE xxx lt arg gt Persistent system parameter commands EER xxx lt arg gt Raw serial EEPROM commands ERASE lt D gt lt O gt lt S gt Erase Flash sectors fr
39. max Empty string No Read write bootdev VxWorks boot device name Empty string No Read write e netip IP address subnet mask e g Empty string No Read write 192 1 1 28 00 9 netgw IP address of default gateway Empty string No Read write h nethost Host IP address used when booting Empty string No Read write over NBOOT TFTP hostname VxWorks name of boot host Empty string No Read write Access the IP address part of No Read write parameter netsm Access the subnet mask part of netip No Read write parameter procnum VxWorks processor number decimal 0 No Read write S VxWorks start up script Empty string No Read write tn netname Host name of this machine Empty string No Read write unitnum VxWorks boot device unit number deci 0 No Read write 3 6 4 4 Reset Cause Parameter rststat The following rststat values are possible When MENMON starts up it determines the reset cause and sets system parameter rststat accordingly Table 25 MENMON Reset causes through system parameter rststat rststat Value Description pwon Power On swrst Board was reset by software by means of the board s reset con troller wdog Board was reset by watchdog timer unit MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 16 3 7 Commands The following table gives all MENMON commands that can be entered on the F50C MENMON prompt You can call this l
40. me through MENMON system parameter stwait see stwait 3 3 Configuring MENMON for Automatic Boot You can configure how MENMON boots the operating system either through the Setup Menu or through the command line In the Basic Setup Menu you can select the boot sequence for the bootable devices on the F50C The selected sequence is stored in system parameter mmstartup as a string of MENMON commands For example if the user selects Int CF Ether None the mmstartup string will be set to DBOOT 0 NBOOT TFTP You can view and modify this string directly using the Expert Setup Menu option Startup string or through the command line command EE MMSTARTUP See also MENMON 2nd Edition User Manual for further details MEN Mikro Elektronik GmbH 40 20F050C00 E2 2011 06 16 3 4 Updating Boot Flash 3 4 1 Update via the Serial Console using SERDL You can use command SERDL to update program data using the serial console The following table shows the F50C locations Table 9 MENMON Program update files and locations File Name Password for Extension Typical File Name SERDL Location SMM 14XM50 00 01 02 5 Secondary MENMON F000 Starting at sector xxx in boot Flash Exx MYFILE E00 Starting at byte xx in EEPROM 3 4 2 Update from Network using NDL You can use the network download command NDL to download the update files fr
41. mmst Status of diagnostic tests as a string Yes Read only 0 1 2 MAC address of Ethernet interface x Yes Read only 0 n Format e g 00112233445566 Set automatically according to serial number of the board pciclkhz PCI bus clock frequency system input Yes Read only clock decimal Hz rststat Reset status code as a string see Yes Read only Chapter 3 6 4 4 Reset Cause eter rststat on page 55 usbdp USB boot device path in format Yes Read only gt 186 port no last port no e g 00 gt 02 gt 01 for USB bus 0 port no 1 2 port no 2 1 1 If implemented Table 22 MENMON F50C system parameters Production data Parameter Parameter User alias Description Standard Default String Access brd Board name Yes Read only brdmod Board model mm Yes Read only brdrev Board revision xx yy zz Yes Read only prodat Board production date MM DD YYYY Yes Read only repdat Board last repair date MM DD YYYY Yes Read only sernbr Board serial number Yes Read only MEN Mikro Elektronik GmbH S ll 52 20F050C00 E2 2011 06 16 Table 23 MENMON F50C system parameters persistent parameters MENMON Parameter rr Parameter User alias Description Standard Default String Access bsadr bs Bootstrapper address Used when 0 No Read write command was called without argu ments hexadecimal 3
42. ns User defined I O FPGA controlled Up to 64 I O lines Connection via rear I O J2 Standard version provides 4 UARTs and 16 GPIO lines See Interface Configuration Matrix showing possible I O combinations Rear I O Four USB 2 0 Up to three 1000Base T Ethernet Up to two SATA Up to 64 I O lines FPGA controlled Reduces Ethernet SATA interfaces See Interface Configuration Matrix showing possible I O combinations FPGA Standard factory FPGA configuration Main bus interface 162043 SDRAM Additional SDRAM controller 32 MB 1672034 GPIO GPIO controller rear I O 14 lines 2 IP cores 162125 UART UART controller controls rear I O COM1 4 The FPGA offers the possibility to add customized I O functionality See FPGA Miscellaneous Real time clock with GoldCap backup Temperature sensor power supervision and watchdog CompactPCI Bus Compliance with CompactPCI Core Specification PICMG 2 0 R3 0 System slot 32 bit 32 MHz PCIeG to PCI bridge e V I O 3 3V 5 tolerant MEN Mikro Elektronik GmbH 4 20F050C00 E2 2011 06 16 Technical Data Busless Operation Board can be supplied with 5V 3 3V and 12V from backplane all other volt ages are generated on the board Backplane J1 connector used only for power supply Electrical Specifications Supply voltage power consumption 5V 3 5 800mA approx 3 3V 3 5 350mA approx 12 5
43. nst all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that MEN was negligent regarding the design or manufacture of the part Unless agreed otherwise the products of MEN Mikro Elektronik are not suited for use in nuclear reactors or for application in medical appliances used for therapeutical purposes Application of MEN products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product ESM ESMini MDIS MDIS4 MDISS5TM MENMON M Module M Modules SA Adapter SA Adapters UBox USM and the MBIOS logo are trademarks of MEN Mikro Elektronik GmbH PC MIP is a registered trademark of MEN Micro Inc and SBS Technologies Inc MEN Mikro Elektronik ESMexpress MIPIOS and the MEN logo are registered trademarks of MEN Mikro Elektronik GmbH Altera Arria Avalon Cyclone Nios and Quartus are registered trademarks of Altera Corp Freescale and PowerQUICC are trademarks of Freescale Semiconductor Inc PowerPC is a registered trademark of IBM Corp Green Hills and INTEGRITY are registered trademarks of Green Hills Software Inc CompactPCI CompactPCI Express CompactPCI PlusIO and CompactPCI
44. ock screw MEN Mikro Elektronik GmbH 18 207050000 2011 06 16 Getting Started 12 Integrating the Board into a System The F50C must be inserted into a system rack with conduction cooling that supports the frame format e g MEN s 0701 0054 rack You can use the following check list when installing the board in a system for the first time and with minimum configuration Power down the system Remove all boards from the CompactPCI system Insert the F50C into the system slot of your CompactPCI system making sure that the CompactPCI connectors are properly aligned Note The system slot of every CompactPCI system is marked by a A triangle on the backplane and or at the front panel It also has red guide rails Use a 2 5 mm hexagon torque wrench to fasten the two wedge locks in the rack You need to apply a turning moment torque of 0 8 Nm Note For first installation and or configuration you can also temporarily oper ate the card without a CompactPCI bus In this case you only need to connect a suitable power supply to the CompactPCI J1 connector You should generally use a host computer for first operation typically under Linux or Windows Install USB to UART driver on your host computer You can use a Windows driver provided by MEN article number 13T005 70 third party or go to the FTDI web site www ftdichip com FTDrivers htm and download a driver there Connect your host compute
45. of connector J1 as defined in the CompactPCI specification will not be repeated here 2 11 Rear I O The F50C provides great flexibility for routing functions to rear I O An onboard FPGA allows to implement customized functions on rear I O connector J2 of the board with a total available pin count of 64 pins Different combinations of interfaces controlled by the CPU and the FPGA are possible The four USB ports are always routed to the J2 connector The Interface Configuration Matrix shows an overview of all varieties that are pos sible Chapter 2 11 2 Standard and Possible Pin Assignments on page 33 gives the standard pin assignment along with possible signal routings In any case please contact our sales team for specially configured board versions This chapter only summarizes the board s options MEN Mikro Elektronik GmbH 31 20F050C00 E2 2011 06 16 d Functional Description 2 11 1 User Defined I O from Onboard FPGA The F50C provides an onboard FPGA The component is a powerful Altera Arria GX AGX35C device and is connected to the CPU via a fast serial PCI Express x1 link It permits to configure the board s rear I O according to your needs without any hardware modifications With regard to the FPGA resources such as available logic elements or pins it is not possible to grant all possible combinations of FPGA IP cores You can find an overview and descriptions of all available FPGA IP co
46. om to val Fill memory byte GO lt addr gt Jump to user program H Print help HELP I lt D gt List board information ICACHE OFF ON Enable disable instruction cache IOI Scan for BIOS devices LM81 Show current voltage and temperature values LOGO Display MENMON start up text screen LS lt clun gt lt dlun gt lt opts gt List files partitions on device MEN Mikro Elektronik GmbH 20F050C00 E2 2011 06 16 Command Description MC lt addr1 gt addr2 cnt Compare memory lt clun gt lt reg gt lt val gt Ethernet register command MO lt from gt lt to gt lt cnt gt Move copy memory MS lt from gt lt to gt lt val gt Search pattern in memory MT lt opts gt lt start gt lt end gt lt runs gt Memory test NBOOT lt opts gt Boot from network NDL lt opts gt Update Flash from network NETSTAT Show current state of networking parameters PCI probe dev lt addr gt bus lt func gt val PCI config register change PCID dev lt bus gt lt func gt PCI config register dump PCIR List PCI resources PCI VPD lt devNo gt lt busNo gt lt capld gt PCI Vital Product Data dump PFLASH lt D gt lt O gt lt S gt lt A gt Program Flash PGM XXX args Media copy tool
47. om a TFTP server in network The file name extensions locations and passwords are the same as for the SERDL command 3 4 3 Update via Program Update Menu MENMON scans an external medium connected to the first USB port USBO for files named 74XM50 SMM The Program Update Menu will then give a list of all files on this medium conforming with this name pattern for selection 3 4 4 Automatic Update Check MENMON s automatic update check looks for some special files on an external medium connected to the first USB port USBO However the F50C implementation does not support program update here but can boot from the external medium The file that is searched for has a name stored in system parameter bf or bootfile or if this is empty BOOTFILE this file is found it is assumed that the external medium is supposed to be booted from To allow MENMON to locate this file it must be in the root directory of a DOS FS This works on unpartitioned media or on drives with one partition MENMON does not automatically start the boot but presents the following menu to the user Detected an update capable external medium gt Ignore continue boot Boot from external medium If there is no user input for 5 seconds after the menu appears booting continues MEN Mikro Elektronik GmbH 41 20 050 00 E2 2011 06 16 3 4 5 Updating MENMON Code Updates of MENMON available for download from website M
48. ontinue as soon as POST has fin ished tdp Telnet server TCP port decimal 1 No Read write MEN Mikro ElektronikGmbH 53 20F050C00 E2 2011 06 16 Parameter m Parameter User alias Description Standard Default String Access tries Number of network tries 20 No Read write tto Minimum timeout between network 0 No Read write retries decimal in seconds 00 15 User parameters hex 16 bits 0x0000 Read write updcdis Disable auto update check bool 0 No Read write Store kerpar and mmstartup parameters 0 No Read write in boot Flash rather than in EEPROM bool vmode Vesa Video Mode for graphics console 0x0101 No Read write hex wat Time after which watchdog timer shall 0 disabled No Read write reset the system after MENMON has passed control to operating system decimal in 1 10 s If 0 MENMON disables the watchdog timer before starting the operating sys tem Note The F50C watchdog supports only the following values 0 Disable watchdog timer 11 Short time out 1 12 seconds 260 Long time out 26 0 seconds 1 If FRAM is implemented 2 If SRAM is implemented MEN Mikro Elektronik GmbH 54 20 050 00 E2 2011 06 16 Table 24 MENMON F50C system parameters VxWorks bootline parameters MENMON mal Description Standard Default iin Posed 8 bf bootfile Boot file name 127 chars
49. or only have one local PCI bus operating at 33 MHz The I O voltage is fixed to 3 3V The data width is 32 bits 2 5 3 Local PCI Express Connections A PCI Express x1 link connects the PowerPC processor with the CompactPCI bus via a PCIe to PCI bridge and with the FPGA MEN Mikro Elektronik GmbH 25 20 050 00 E2 2011 06 16 Functional Description 2 6 Memory 2 6 1 DRAM System Memory The board provides up to 2 GB onboard soldered DDR2 double data rate SDRAM on nine memory components incl ECC The memory bus is 72 bits wide and operates at up to 300 MHz physical depending on the processor type Depending on the board version the SDRAM may have ECC error correcting code ECC memory provides greater data accuracy and system uptime by protecting against soft errors in computer memory 2 6 2 FRAM The board has up to 128 KB non volatile FRAM memory connected to the local bus of the CPU The FRAM does not need a back up voltage for data retention 2 6 3 SRAM The board has up to 2 MB non volatile SRAM memory connected to the local bus of the CPU For data retention during power off the SRAM is supplied with a back up voltage by a GoldCap 2 6 4 Boot Flash The board has 16 MB of onboard Flash It is controlled by the CPU Flash memory contains the boot software for the MENMON operating system bootstrapper and application software The MENMON sectors are software protected against illegal write transactions throug
50. pdate media Execute Auto update dialog when suitable medium found Leave dialog after 5 ids Y Y Booting MenmonCli Execute mmstartup string mmstartup empty Jump to bootstrapper User abort or Boot failure entry start network servers do process command line No user intervention MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 16 3 2 Interacting with To interact with MENMON you can use the following consoles UART to USB COM via UART to USB interface Rear I O COMI 4 FPGA controlled Touch panel TFT interface if present Telnet via network connection HTTP monpage via network connection The default setting of the COM ports is 9600 baud 8 data bits no parity and one stop bit 3 2 1 Entering the Setup Menu Command Line During normal boot you can abort the booting process in different ways during the self test depending on your console With a touch panel press the Setup button to enter the Setup Menu With a text console press the s key to enter the Setup Menu With a text console press ESC to enter the command line By default the self test is not left until 3 seconds have elapsed measured from the beginning of the self test even if the actual test has finished earlier to give the user a chance to abort booting and enter the Setup Menu You can modify the self test wait ti
51. perating System Software The board supports Linux VxWorks and INTEGRITY By default no operating system is installed on the board Please refer to the respective manufacturers documentation on how to install operating system software You can find any software available on MEN s website d 1 4 Installing Driver Software For a detailed description on how to install driver software please refer to the respective documentation You can find any driver software available for download on MEN s website MEN Mikro Elektronik GmbH 20 20F050C00 E2 2011 06 16 Functional Description 2 Functional Description The following describes the individual functions of the board and their configuration on the board There is no detailed description of the individual controller chips and the CPU They can be obtained from the data sheets or data books of the semiconductor manufacturer concerned Chapter 5 1 Literature and Web Resources on page 61 2 1 Power Supply The board is supplied CompactPCI connector J1 with 5 V 43 3 V and 12 V AII other required voltages are generated on the board The F50C may also be operated as a stand alone card without the bus In this case power is also supplied via the J1 connector Three voltages are needed 5 V 43 3 V and 12 V 2 2 Board Supervision The board features a temperature sensor and voltage monitor A voltage monitor supervises all used voltages and
52. r to the front panel USB 1 port of the F50C UART to USB interface To do this you need a suitable USB cable type A to A Power up the system Start up a terminal program on your host computer e g HyperTerm under Win dows and open a terminal connection Set your terminal connection to the following protocol 9600 baud data transmission rate 8 data bits 1 stop bit No parity MEN Mikro Elektronik GmbH 19 20F050C00 E2 2011 06 16 Getting Started When the terminal connection is made press Enter Now you can use the MEN MON BIOS firmware see detailed description in Chapter 3 MENMON on page 37 If you enter command LOGO on the MENMON prompt the terminal dis plays a message similar to the following Secondary MENMON for MEN MPC8548 Family XM50 1 7 c 2007 2008 MEN Mikro Elektronik GmbH Nuremberg MENMON 2nd Edition Created Jun 12 2008 10 45 08 CPU Board XM50 03 CPU MPC8548 Serial Number 4 CPU MEM 1386 198 MHz HW Revision 00 00 00 CIE 396 50 MHz PCII PCI2 32Bit 66MHz 32Bit 33MHz PCIe x4 DDR2 SDRAM 512 MB ECC on 3 0 3 8 FRAM SRAM 128 2048 kB Produced FLASH 16 MB Last epa s Reset Cause Power On Carrier Board F503 00 Rev 00 01 00 Serial 3 Note Don t power off the F50C now otherwise the USB to UART interface on the host computer will be disconnected Observe the installation instructions for the respective software 1 3 Installing O
53. rated Northbridge and Southbridge Memory e 2x32KB L1 data and instruction cache 512KB 256KB L2 cache integrated in MPC8548 MPC8543 Up to 2GB SDRAM system memory Soldered DDR2 with or without ECC Up to 300 MHz memory bus frequency depending on CPU e Up to 16GB soldered Flash disk SSD solid state disk Up to 32MB additional DDR2 SDRAM FPGA controlled e g for video data 16MB boot Flash 2MB non volatile SRAM With GoldCap backup 128KB non volatile FRAM Serial EEPROM 4kbits for factory settings Mass Storage Parallel IDE PATA Upto 16GB soldered ATA Flash disk SSD solid state disk Serial ATA SATA Up to two ports via rear I O J2 Transfer rates up to 150MB s 1 5 Gbits s Via PCI to SATA bridge See Interface Configuration Matrix showing possible I O combinations USB host Four USB 2 0 host ports Via rear I O J2 OHCI and EHCI implementation Data rates up to 480Mbits s MEN Mikro Elektronik GmbH 3 20F050C00 E2 2011 06 16 rrt Technical Data USB client One USB client port on series A connector at front panel Via UART to USB converter For first operation and service Data rates up to 115 2kbits s 16 byte transmit receive buffer Handshake lines none Ethernet Up to three 10 100 1000Base T Ethernet channels with MPC8548 E two channels with MPC8543 E Via rear I O J2 See Interface Configuration Matrix showing possible I O combinatio
54. res on MEN s website Table 7 Pin assignment of rear I O connector J2 options maximum FPGA control on page 35 gives the I O pins available for custom FPGA functions 64 pins 2 11 1 1 Standard Factory FPGA Configuration In addition to basic IP cores needed for the FPGA internal infrastructure the following IP cores are implemented in the standard model 16Z043_SDRAM Additional SDRAM controller 32 MB 167034 GPIO controller 14 lines 2 IP cores e 167125 UART UART controller controls rear COM1 4 You can find more information on the SDRAM IP core in the 162043 SDRAM data sheet on MEN s website You can find more information on the GPIO IP core in the 162034 GPIO data sheet on MEN s website You can find more information on the UART IP core in the 162125 UART data sheet on MEN s website Please see MEN s website for up to date driver software and documentation Accessing the GPIO Pins You can control the I O lines using MDIS4 driver software available from MEN By default the GPIOs are configured as inputs This configuration can be changed through the driver software The following table gives the assignment of the GPIO controllers implemented in the F50C s FPGA to their function on the board Normally you can identify the controllers by their instance numbers in your operating system Table 4 Assignment of 162034 GPIO controllers Instance Function 0 GPIO 1 lines O
55. rrupt Handling DUREE ege onek 59 43 SMB Devices dees RR RI RU IRR E EET E 59 4 4 Onboard PGI DeVIC6S epo ent eben dub seipsis 60 S Appendix 61 5 1 Literature and Web Resources 1 0 0 0 asa saa se eese 61 Sul sinha 61 5029 EET 61 Sko 61 SU 61 Sls 62 5 2 Finding out Board s Article Number Revision and Serial Number62 MEN Mikro Elektronik GmbH 14 20 050 2011 06 16 Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 15 Map of the board front panel view 17 Map of the board top VIeW u esset ee mb eh bere bes 18 Conduction cooling thermal interfaces horizontal front view of CCA e dunia iow Sve suwa ia aca aoa 24 MENMON State diagram Degraded Mode Full Mode 38 MENMON State diagram main state 39 Label giving the board s article number revision and serial number 62 Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22
56. s Manufacturers Group PICMG www picmg org PCI Local Bus Specification Revision 2 2 1995 PCI Special Interest Group P O Box 14070 Portland OR 97214 USA WWW pcisig com CompactPCI PlusIO Specification PICMG 2 30 R1 0 2009 PCI Industrial Computers Manufacturers Group PICMG www picmg org Introduction to CompactPCI PlusIO on Wikipedia en wikipedia org wiki CompactPCI_PlusIO 5 2 Finding out the Board s Article Number Revision and Serial Number MEN user documentation may describe several different models and or hardware revisions of the F50C You can find information on the article number the board revision and the serial number on two labels attached to the board Article number Gives the board s family and model This is also MEN s order ing number To be complete it must have 9 characters Revision number Gives the hardware revision of the board Serial number Unique identification assigned during production If you need support you should communicate these numbers to MEN Figure 6 Label giving the board s article number revision and serial number Complete article number Article No L 02F050C00 Serial No 000001 Rev 00 00 00 Revision number Serial number man MEN Mikro Elektronik GmbH 62 20F050C00 E2 2011 06 16
57. s infrastructure applications The MPC8548 3 is a member of the PowerQUICC III family of devices that combine system level support for industry standard interfaces with processors that implement the embedded category of the Power Architecture technology General The MPC8548 3 offers a double precision floating point auxiliary processing unit APU up to 512 KB of level 2 cache up to four integrated 10 100 1Gbits s enhanced three speed Ethernet controllers with TCP IP acceleration and classification capabilities a DDR DDR2 SDRAM memory controller a programmable interrupt controller two PC controllers a four channel DMA controller a general purpose I O port and dual universal asynchronous receiver transmitters DUART The MPC8548 3 is available with MPC8548 3E or without an integrated security engine with XOR acceleration Table 1 Processor core options on F50C Processor Type Core Frequency L2 Cache Encryption Unit Ethernet Ports MPC8548 1 GHz 1 2 GHz 1 33 GHz or 512 KB No 3 15 GHz MPC8548E 1 GHz 1 2 GHz 1 33 GHz 512 KB Yes 3 15 GHz MPC8543 800 MHz or 1 GHz 256 KB No MPC8543E 800 MHz or 1 GHz 256 KB Yes MEN Mikro Elektronik GmbH 20 050 00 E2 2011 06 16 Functional Description 2 4 2 Thermal Considerations and Conduction Cooling The F50C generates around 17 W of power dissipation when operated at 1 33 GHz The board was specially designed for conduction cooled systems
58. t uses a bus or star topology and supports data transfer rates of 100 Mbits s and more The Ethernet specification served as the basis for the IEEE 802 3 standard which specifies the physical and lower software layers Ethernet is one of the most widely implemented LAN standards Ethernet networks provide high speed data exchange in areas that require economical connection to a local communication medium carrying bursty traffic at high peak data rates A classic Ethernet system consists of a backbone cable and connecting hardware e g transceivers which links the controllers of the individual stations via transceiver transmitter receiver cables to this backbone cable and thus permits communication between the stations 2 9 2 10Base T 10Base T is one of several adaptations of the Ethernet IEEE 802 3 standard for Local Area Networks LANs The 10Base T standard also called Twisted Pair Ethernet uses a twisted pair cable with maximum lengths of 100 meters The cable is thinner and more flexible than the coaxial cable used for the 10Base 2 or 10Base 5 standards Since it is also cheaper it is the preferable solution for cost sensitive applications Cables in the 10Base T system connect with RJ45 connectors star topology is common with 12 or more computers connected directly to a hub or concentrator The 10Base T system operates at 10 Mbits s and uses baseband transmission methods MEN Mikro Elektronik GmbH 29 20F050C00 E2
59. tical lines on the outer margin signal technical changes to the previous issue of the document MEN Mikro Elektronik GmbH 11 20F050C00 E2 2011 06 16 About this Document Legal Information MEN Mikro Elektronik reserves the right to make changes without further notice to any products herein MEN makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does MEN assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts MEN does not convey any license under its patent rights nor the rights of others Unless agreed otherwise MEN products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the MEN product could create a situation where personal injury or death may occur Should Buyer purchase or use MEN products for any such unintended or unauthorized application Buyer shall indemnify and hold MEN and its officers employees subsidiaries affiliates and distributors harmless agai
60. to 6 bits 0 6 GPIO 2 lines O to 6 bits 0 6 MEN Mikro Elektronik GmbH 32 20F050C00 E2 2011 06 16 2 11 2 Functional Description Table 5 Pin assignment of rear I O connector J2 standard board version Standard and Possible Pin Assignments F E D B A 7 22 GND GAO GAT GA2 GA3 GA4 GND 21 GND GND CLK6 GND 20 GND GND CLK5 GND 19 GND GND GND 18 GND GND m 17 CE GND 16 GND GND 220 15 GND COM2_RI GND 14 GND GPIO2 0 COM2 DTR amp COM1_RI GND EBB 13 GPIO2 6 GPIO 6 DSR amp COM1 DTR4 GND 12 GPIO2 5 GPIO1 5 GPIO1 0 COM2 DCD4 COM1 DSR amp GND HH 11 GND 2 GPlO1 4 2_ DCD GND 10 2 3 GPIO1 3 CTS amp 1 RTS4 GND 9 2 2 GPIO1 2 COM2_TXD COM1 CTS GND 8 GND SATA2 GPIO1 1 RXD TXD GND 7 GND 5 2 RX SATA2_TX 4 TXD COM1_RXD GND EBB 6 GND SATA1 RX SATA2_TX COM3_TXD GND naa 5 GND SATA1_RX SATA1_TX COM3_RXD GND 4 GND GPIO2 1 SATA1_TX B3 VIO GND GND GNT4 REQ4 GNT3 GND 2 GND REQ3 GNT2 SYSEN CLK3 GND 1 GND REQ2 GNT1 REQ1 GND GND Please note that the standard configuration
61. ystem Parameters Note Parameters marked by Yes in section Parameter String are part of the MENMON parameter string Table 21 F50C system parameters Autodetected parameters Parameter oer Parameter User alias Description Standard Default String Access ccbclkhz CCB clock frequency decimal Hz Yes Read only clun MENMON controller unit number that Yes Read only MENMON used as the boot device hexadecimal cons Selected console Set to name of first Yes Read only selected console cpu CPU type as ASCII string e g Yes Read only MPC8548E cpuclkhz CPU core clock frequency decimal Hz Yes Read only dlun MENMON device unit number that Yes Read only MENMON used as the boot device hexadecimal flashO Flash size decimal kilobytes Yes Read only fram0 FRAM size decimal kilobytes Yes Read only immr Physical address of CCSR register Yes Read only block memO RAM size decimal kilobytes Yes Read only mem1 Size of SRAM decimal kilobytes Yes Read only memclkhz Memory clock frequency decimal Hz Yes Read only MEN Mikro Elektronik GmbH 51 20 050 00 E2 2011 06 16 Parameter is Parameter User alias Description Standard Default String Access mm Info whether primary or secondary Yes Read only MENMON has been used for booting either smm or
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