PCA9605 Simple 2-wire bus buffer
Contents
1. PCA9605 9 1 Bidirectional data buffer The bidirectional data buffer will determine which side has first fallen below Viock and give that side of the buffer control over the direction of the buffer For the purpose of this one LOW going pulse that side now becomes the input be it SDA_IN or SDA_OUT When the input side falls to near Vi it will begin to drive the output side of the buffer LOW It will continue to hold the output low until the input exceeds Vi at which point the output is released and will rise as fast as it is permitted by the load and pull up to which it is attached Assuming of course that the output is not otherwise held LOW by some other device on the bus on that side of the buffer When the input side again exceeds Vuniock it will release its control of the buffer direction At this point if the output side was being held LOW lt Vuniock by another device it will immediately gain control and now become the input What was the input will now become the output and the process will repeat as above but in the opposite direction All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 7 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer This means that as direction control2. ae PCA9605 BUS Simple 2 wire bus buffer Rev 1 28 February 2011 Product data sheet 1 General description The PCA9605 is a monolithic CMOS integrated circuit for bus buffering in applications including I C bus SMBus DDC PMBus and other systems based on similar principles The buffer extends the bus load limit by buffering both the SCL and SDA lines allowing the maximum permissible bus capacitance on both sides of the buffer The PCA9605 includes a unidirectional buffer for the clock signal and a bidirectional buffer for the data signal Slave devices which employ clock stretching are therefore not supported In its most basic implementation the buffer will allow an extended number of slave devices to be attached to one or more master devices In this case all master devices would be positioned on the Sxx_IN side of the PCA9605 The direction pin DIR further enhances this function by allowing the unidirectional clock signal to be reversed thus allowing master devices on both sides of the buffer The enable EN function allows sections of the bus to be isolated Individual parts of the system can be brought on line successively This means a controlled start up using a diverse range of components operating speeds and loads is easily achieved 2 Features and benefits E Simple impedance isolating buffer for 2 wire buses E 30 mA maximum static open drain pull down capability suppo
3. 0 ese e eee eee eee 2 6 Pinning information 00ee ee eee 3 6 1 PINNING ze orth decked dpsed nee Oe ed Vere dala ere 3 6 2 Pin description 50 e0 e eee 3 7 Functional description 0 0005 3 7 1 Vpp Vss Supply pins 3 7 2 SCL_IN SCL_OUT clock signal inputs outputs 2 2 eee eee ee 3 7 3 SDA_IN SDA_OUT data signal inputs outputs 2 2 eee 4 7 4 Enable EN activate buffer operations 4 7 5 Direction DIR clock buffer direction control 4 8 Limiting values 000 e eee eee eee 5 9 CharacteristicS 00 c cece ee 5 9 1 Bidirectional data buffer 7 9 2 Operating conditions n easan aana 9 10 Application information 10 10 1 Design considerations 10 11 Package outline 00 e eee eee 14 12 Handling information 00 00005 16 13 Soldering of SMD packages 16 13 1 Introduction to soldering 16 13 2 Wave and reflow soldering 16 13 3 Wave soldering 20 eee eee 17 13 4 Reflow soldering 0 e ee eee 17 14 Abbreviations 00 00 cee eee eee 18 15 References 0 0 0 cece eee eee 18 16 Revision history 00 eee e eens 19 17 Legal information 00 eee eeeee 20 17 1 Data sheet status 00 20 17 2 Definitions 20000 eee eee 20 17 3 Disc
4. All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 15 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 12 Handling information CAUTION A SEN This device is sensitive to ElectroStatic Discharge ESD Observe precautions for handling electrostatic sensitive devices Such precautions are described in the ANSI ESD S20 20 IEC ST 61340 5 JESD625 A or equivalent standards 13 Soldering of SMD packages 13 1 13 2 PCA9605 This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in whi
5. Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT96 1 076E03 MS 012 E40 99 42 27 03 02 18 Fig 19 Package outline SOT96 1 SO8 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved PCA9605 Product data sheet Rev 1 28 February 2011 14 of 22 NXP Semiconductors PCA9605 TSSOP8 plastic thin shrink small outline package 8 leads body width 3 mm DIMENSIONS mm are the original dimensions Simple 2 wire bus buffer SOT505 1 lt _ gt detail X UNIT A max A1 A2 Ag bp c D E2 mm 1 1 0 15 0 05 0 95 0 80 0 45 0 25 0 28 0 15 3 1 3 1 2 9 2 9 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT505 1 ES 03 02 18 Fig 20 Package outline STO505 1 TSSOP8 PCA9605
6. The master can control the enable EN signals such that each bus section can be independently activated This allows for slaves sharing the same address to be placed on different bus sections and thus uniquely addressed The enable pin EN can similarly be used to interface buses of different operating frequencies When certain bus sections are enabled the system frequency may be limited by a bus section having a slave device specified only to 400 kHz Fast mode When that bus section is disabled the slow slave is isolated and the remaining bus can be run at 1 MHz Fast mode Plus PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 10 of 22 NXP Semiconductors PCA9605 PCA9605 Simple 2 wire bus buffer BUS MASTER 2 1 1 kQ 1 1 KQ d A Oa 2 Nn gt MASTER SLAVE U4 up to 400 pF load PCA9525 or 4 nF load if only PCA9605 s used R1 and R2 110 Q VDD SCLIN SCL OUT SDAIN SDA_OUT ai PCA9525 gt SCL VDD SCLIN SCL OUT SDAIN SDA_OUT a PCA9605 up to 4 nF load PCA9605 Fig 14 PCA9605 typical buffer application R5 110 Q R4 110 Q gt SDA gt SCL gt SDA 002aaf342 Figure 15 show
7. NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or PCA9605 All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeg
8. and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s 18 Contact information Simple 2 wire bus buffer own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 17 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 21 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 19 Contents 1 General description 0 0ee00s 1 2 Features and benefits 00 00eees 1 3 Applications 0 0 00 00 cece ee eee 2 4 Ordering information 0 0 0005 2 5 Block diagram
9. as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wave Solder bath specifications including temperature and impurities Reflow soldering Key characteristics in reflow soldering are e Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures See Figure 21 than a SnPb process thus reducing the process window e Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board e Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 5 and 6 Table 5 SnPb eutectic process from J STD 020C Package thickness mm Package reflow temperature C Volume mm lt 350 350 lt 2 5 235 220 22 5 220 220 Table 6 Lead free process from J STD 020C Package thickness mm Package reflow temperature C Volume mm lt 350 35
10. by isolating the load capacitance of each branch Figure 17 and Figure 18 show alternate forms of bus multiplexing with the latter being an excellent way to eliminate the requirement for a master to dedicate pins to enabling multiple PCA9605 devices R3 R4 1 1 KQ 1 1 KQ Vec VoD SCL ISCLIN SCL_OUT gt SCL SCO lt gt SDA SDAIN SDA_OUT gt SDA SD0 gt SC1 gt L_ inti SD1 Using the PCA9525 up to 400 pF may be SC2 gt connected to each BUS MASTER EN PCA9605 A0 SD2 and every bus 0 through bus 3 gt A1 SC3 j gt A2 SD3 gt U3 002aaf362 Fig 16 PCA9605 multiplexer isolation application PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 12 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer Fig 17 PCA9605 bus multiplexer application driven from a simple logic device 5V VDD SCL_IN SCL_OUT gt SCL SDAIN SDA_OUT J gt SDA EN PCA9525 DIR isolated bus with 400 pF load capacitance 74LS137 VDD SCLIN SCL_OUT SDAIN SDA_OUT EN PCA9605 DIR 3 to 8 demultiplexer SCL SDA isolated bus with 4 nF load capacitance 002aaf345 Fig 18
11. case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 20 of 22 NXP Semiconductors PCA9605 Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications
12. 0 Fast rising SDA_xx input side 002aaf338 PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 8 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer Figure 11 shows that by choosing an appropriate value of pull up resistance or adding additional load capacitance if that is preferred the rate of rise of both input and output can be matched and the glitch on the rising edge eliminated Tek oh El Ready CH1 1 00VBy CH2 1 00VBy M 500ns CH3 1 00VEy CH4 1 00VBy 002aaf339 Fig 11 Matched input and output rise times 9 2 Operating conditions PCA9605 A full byte transaction is shown in Figure 12 SDA_IN and SDA_OUT are shown at the top of the image and SCL_IN and SCL_OUT are shown at the bottom The START condition address bits read write bit acknowledge bit and STOP condition can all be clearly seen E Ready LLL RE CH1 1 00VR CH2 1 00VEy M 5 00us CH3 1 00VBy CH4 1 00VBy 002aaf340 Fig 12 Full 400 kHz I2C bus address byte transaction All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 9 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 10 Application information 10 1 Design considerat
13. 0 to 2000 gt 2000 lt 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautions as indicated on the packing must be respected at all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 21 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 17 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer temperature MSL Moisture Sensitivity Level Fig 21 Temperature profiles for large and small components maximum peak temperature MSL limit damage level minimum peak temperature minimum soldering temperature peak temperature time 001aac844 For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description 14 Abbreviations 15 References Table 7 Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DDC Data Display Channel Fm Fast mode Plus 2C bus Inter Integrated Circuit bus VO Input Output IC Integrated Circuit PMBus Power Management Bus SCL Serial Clock Line SDA Serial Data Line SMBus System Management Bus PCA9605 1 _UM10204 I2C bus specification and user manual Rev 03 19 June 2007 NXP B V www nxp com documents user_manual
14. PCA9605 bus multiplexer application driven from an I2C bus I O expander 3 3 V Rt R2 1 1 kQ 1 1 kQ VDD SCL lt t t gt SCL_IN SCL OUT SCL SDA lt gt SDA_IN SDA OUT SDA gt EN pCAg525 isolated bus with 400 pF load capacitance 100 gt SCL 101 U1 102 3 3 V 12C bus 103 T I O expander PCA9536 DD gt SCL_IN SCL_OUT J gt SCL isolated bus with 4 nF load capacitance 002aat346 PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 13 of 22 PCA9605 NXP Semiconductors Simple 2 wire bus buffer 11 Package outline SO8 plastic small outline package 8 leads body width 3 9 mm SOT96 1 A2 ri lt a detail X 2 5 las i scale DIMENSIONS inch dimensions are derived from the original mm dimensions A 1 2 max DO E He UNIT Ai A2 Ag bp 5 0 4 0 6 2 48 3 8 en 5 8 0 20 0 16 0 19 0 15 0 25 0 19 0 0100 0 0075 1 75 inches Notes 1 Plastic or metal protrusions of 0 15 mm 0 006 inch maximum per side are not included 2
15. UM10204 pdf 2 System Management Bus SMBus Specification Version 2 0 August 3 2000 SBS Implementers Forum All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 18 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 16 Revision history Table 8 Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9Q605 v 1 20110228 Product data sheet PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 19 of 22 NXP Semiconductors PCA9605 17 Legal information Simple 2 wire bus buffer 17 1 Data sheet status Document status I 2 Product status 3 Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may
16. ch the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following e Through hole components e Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are e Board specifications including the board finish solder masks and vias e Package footprints including solder thieves and orientation e The moisture sensitivity level of the packages e Package placement e Inspection and repair e Lead free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 16 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 13 3 Wave soldering 13 4 PCA9605 Key characteristics in wave soldering are e Process issues such
17. ge lo 30 mA lo 100 uA Pins SDA_IN SDA_OUT Viock direction lock voltage Vpp 2 7 V Vpp 5 5 V Vunlock direction unlock voltage Vpp 2 7 V Vpp 5 5 V quiescent Vpp Vien 5 5 V SCL_IN SDA_IN 800 kHz Vi2c bus Voo or GND LOW level Viec bus lt VIL 2 2 2 2 2 2 2 2 2 2 PCA9605 All information provided in this document is subject to legal disclaimers Min 2 7 1 2 2 0 80 200 30 2 0 4 8 Max 5 5 1 Vpp 0 3 0 4 0 5 1 300 1 3 3 0 NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 lt lt lt lt NXP Semiconductors PCA9605 Simple 2 wire bus buffer Table 4 Characteristics continued Tamb 40 C to 85 C voltages are specified with respect to ground Vss Vpp 5 5 V unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Enable EN Vinven enable threshold voltage EN active Vpp 2 7 V 2 0 V EN active Vpp 5 5 V 4 8 V Vindis disable threshold voltage EN standby Vpp 2 7 V 0 9 V EN standby Vpp 5 5 V 2 1 V Vhys hysteresis voltage Vpp 2 7 V 100 mV Vpop 5 5 V 200 mV lo input leakage current Vien VoD 0 1 uA Direction DIR Viair direction input voltage direction SCL_OUT to SCL_IN Vpp 2 7 V 2 0 V Vpp 5 5 V 4 8 V direction SCL_IN to SCL_OUT Vpop 2 7 V 0 9 V Vpp 5 5 V 2 1 V Vhys hysteresis voltage V
18. have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 17 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer function
19. ions Figure 13 shows a typical data transfer through the PCA9605 The PCA9605 has excellent application to extending loads and providing interfaces to connectors on high speed microprocessor cards PCA9605 can operate well in excess of the Fast mode 400 kHz C bus specification Ref 1 and is compatible with the Fast mode Plus specification Rise times are determined simply by the side of the buffer with the slowest RC time constant 1 l w 1 1 1 1 1 1 1 1 1 1 1 I l e i 1 z SDA i 7 AO A1 A2 i AS 7 pa A5 A6 Ww ACK A fi data l K master master master _ master f master master master master slave ai LS i l Zea purpose of bit address bit 5 SDA direction STOP device asserting data line master slave hand over pulses upon change Sequence of device asserting the data line Sequence master side of PCA9525 PCA9605 slave side of PCA9525 PCA9605 002aaf341 Remark Input to output delay exaggerated for clarity Fig 13 Typical communication sequence through the PCA9605 Figure 14 shows a typical application for the PCA9605 In most applications there will be a single master on the Sxx_IN side of the buffer One or more PCA9605s can be connected to this master giving multiple isolated bus sections on which the slaves are located Each bus section can have the maximum permissible load capacitance and this capacitance will not influence any other bus section
20. is handed from one side of the buffer to the other a voltage spike of about Vuniock volts will appear on the side that was the input and became the output Figure 9 shows clock and data being buffered through the PCA9605 Channel 3 shows the SDA_IN port with direction hand over spike upper left corner The level of the SDA_OUT port channel 4 can be seen to increase as it goes from being held LOW by the buffer to being held LOW by another device on the bus Of course the information on the SDA line is only latched into an 1 C bus device on a clock edge The spike on the data line does not occur at a time when data is being latched and thus the set up and hold conditions are still met for a valid 1 C bus transaction Figure 9 also shows a glitch occurring on the SDA_OUT port upper right corner A more drastic example is shown in Figure 10 In this case the side acting as the input SDA_OUT is more lightly loaded than the side acting as the output SDA_IN It therefore rises quickly to Vuniock level before the SDA_IN has been able to exceed Vi Direction control briefly reverses and SDA_OUT gets pulled back LOW again until SDA_IN has exceeded Vi Tek wl be E Ready 2 CH1 1 00VEy CH2 1 00VEy M 500ns CH3 1 00VBy CH4 1 00VBy 002aaf337 Fig 9 Hand over spikes on the data bus Tek od Lis By Ready Ar CH1 1 00VEy CH2 1 00VEy M 500ns CH3 1 00VBy CH4 1 00VEy Fig 1
21. ith its register contents During these times the controlling input side will have to rise back above the unlock voltage Vunlock before it releases the lock which then allows the output side to gain control and pull what was the input side LOW again This will cause a pulse on the input side which can be quite a long duration in high capacitance buses However this pulse will not interfere with the actual data transmission as it should not occur during times of clock line transition during normal 1 C bus and SMBus protocols and thus data signal set up time requirements are still met Ports are open drain type and require external pull up resistors 7 4 Enable EN activate buffer operations The active HIGH enable input EN can be used to disable the buffer for the purpose of isolating sections of the bus The IC should only be disabled when the bus is idle This prevents truncation of commands which may confuse other devices on the bus Enable EN may also be used to progressively activate sections of the bus during system start up Bus sections slow to respond on power up can be kept isolated from the main system to avoid interference and collisions The pin must be externally driven to a valid state 7 5 Direction DIR clock buffer direction control The direction input DIR is used to change the signal direction of the SCL ports When the DIR pin is logic LOW the clock signal inpu
22. l information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 2 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 6 Pinning information 7 Functional 6 1 Pinning EN V el a EN O VDD SCL_OUT SDA_OUT SCL_OUT SDA_OUT PCA9605D 7 PCA9605DP 3 SCL_IN 6 SDA_IN SCL_IN SDA_IN Vss DIR Vss DIR 002aaf357 002aaf358 Fig 2 Pin configuration for S08 Fig 3 Pin configuration for TSSOP8 6 2 Pin description Table 2 Pin description Symbol Pin Description EN 1 enable SCL_OUT 2 clock buffer slave side SCL_IN 3 clock buffer master side Vss 4 supply ground DIR 5 clock direction SDA_IN 6 data buffer master side SDA_OUT 7 data buffer slave side Vpp 8 positive supply description PCA9605 7 1 7 2 Refer to Figure 1 Block diagram of PCA9605 Vpp Vss supply pins The power supply voltage for the PCA9605 may be any voltage in the range 2 7 V to 5 5 V The IC supply must be common with the supply for the bus Hysteresis on the ports is a percentage of the IC s power supply hence noise margin considerations should be taken into account when selecting an operating voltage SCL_IN SCL_OUT clock signal inputs outputs The clock signal buffer is unidirectional although the direction may be reversed under control of the direction pin DIR In normal bu
23. laimers 000200 cee eee eee 20 17 4 Trademarks 000202 00 eee eee ee 21 18 Contact information 0 0006 21 19 Contents siccce ccc int eee tees nee ae 22 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2011 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 28 February 2011 Document identifier PCA9605
24. pop 2 7 V 100 mV Vpop 5 5 V 200 mV lo input leakage current Voir Vpp 0 1 uA Timing characteristics Figure 4 ta delay time Rpy 200 Q 0l 70 ns tr fall time Rpy 200 Q 0l 16 ns 1 Guaranteed by design not subject to test 2 Supply voltage dependent refer to graphs Figure 5 through Figure 8 for typical trend PCA9605 A Vi2C bus Sxx_IN Sxx_OUT time 002aaf332 Fig 4 Timing diagram All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 6 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer 5 002aaf333 4000 002aaf334 Vi Vi hys V V 4 800 3 600 Viock 2 400 VIH 1 200 ed a VIL 0 0 2 3 4 5 6 2 3 4 5 6 Vpp V Voo V Tamb 25 C Fig 5 Typical input levels versus supply voltage Fig 6 Typical Vi Vi_ hysteresis versus supply voltage 100 002aaf359 300 002aaf360 VoL mV VoL 80 mV 200 60 40 100 20 Vpp 5 5V 27V 0 0 0 0 5 1 0 1 5 2 0 25 50 0 50 100 150 Rey kQ Tamb C Tamb 25 C lo 30 mA Fig 7 Typical LOW level output voltage versus Fig 8 Typical LOW level output voltage versus pull up resistance ambient temperature
25. rts a wide range of bus standards Works with 2C bus Standard mode Fast mode Fast mode Plus SMBus standard and high power mode and PMBus Fast switching times allow operation in excess of 1 MHz Enable allows bus segments to be disconnected Hysteresis on inputs provides noise immunity Operating voltages from 2 7 V to 5 5 V Very low supply current Uncomplicated characteristics suitable for quick implementation in most common 2 wire bus applications NXP Semiconductors PCA9605 Simple 2 wire bus buffer 3 Applications Electronic signs and displays Lighting control including architectural and stage lighting Game consoles boxes Gaming machine networks Building automation TV projector monitor interconnection DDC Power management systems Desktop and portable computers Security systems Interfacing standard 3 mA C bus parts to a 30 mA Fm bus 4 Ordering information Table 1 Ordering information Type number Topside Package mark Name Description Version PCA9605D PCA9605 SO8 plastic small outline package 8 leads body width 3 9 mm SOT96 1 PCA9605DP 9605 TSSOP8 plastic thin shrink small outline package 8 leads body width 3 mm SOT505 1 5 Block diagram 2 7Vto5 5V R1 R3 R4 enable SDA SDA SCL direction SCL 002aaf356 Fig 1 Block diagram of PCA9605 PCA9605 Al
26. s and qualities beyond those described in the Product data sheet 17 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use
27. s operations for example the I2C bus the master device generates a unidirectional clock signal to the slave For lowest cost the PCA9605 combines unidirectional buffering of the clock signal with a bidirectional buffer for the data signal Clock stretching is therefore not supported and slave devices that may require clock stretching must be accommodated by the master adopting an appropriate All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 3 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer clocking when communicating with them The buffer includes hysteresis to ensure clean switching signals are output especially with slow rise times on high capacitively loaded buses Output ports are open drain type and require external pull up resistors 7 3 SDA_IN SDA_OUT data signal inputs outputs The data signal buffer is bidirectional The port SDA_IN SDA_OUT which first falls below the lock voltage Viock will take control of the buffer direction and lock out signals coming from the opposite side As the input signal continues to fall it will then drive the output side LOW Again hysteresis is applied to the buffer to minimize the effects of noise At some points during the communication the data direction will reverse e g when the slave transmits an acknowledge ACK or responds w
28. s the PCA9605 used with masters on both sides of the buffer More than one master may be used on the Sxx_IN side of the IC However to locate a master on the Sxx_OUT side and have that master be able to communicate with devices on the Sxx_IN side it must either have direct control over the direction pin DIR of the PCA9605 or it must request another controlling master to change the direction In Figure 15 U4 uses an IRQ to signal to U2 that requests a direction change Once in control it could alternatively use the bus to signal release of control All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 11 of 22 NXP Semiconductors PCA9605 Simple 2 wire bus buffer R1 R2 R3 R4 VDD ejst sct ourj i gt SCL SDA_IN SDA OUT gt SDA BUS MASTER 1EN pcage0s gt DIR a L1 Q O A Ut aBS d 3 S master U4 requests SCL MASTER Nn gt direction change from MASTER master U2 using IRQ U4 SLAVE U3 002aaf361 Fig 15 PCA9605 with masters on both sides of buffer Multiplexers such as the PCA9544A are simple analog switches which provide no capacitive load isolation between connected branches Figure 16 shows the PCA9605 enhancing an l C bus multiplexer application
29. t is SCL_IN and the buffered output is SCL_OUT When the DIR pin is logic HIGH the clock signal input is SCL_OUT and the buffered output is SCL_IN The pin must be externally driven to a valid state PCA9605 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 1 28 February 2011 4 of 22 NXP Semiconductors PCA9605 8 Limiting values Simple 2 wire bus buffer Table 3 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Vpop supply voltage Vi voltage on any other pin lyo input output current Pitot total power dissipation Tstg storage temperature Tamb ambient temperature Max 7 Vpp 0 5 50 300 125 85 1 Voltages are specified with respect to pin 4 Vss 9 Characteristics Table 4 Characteristics Tamb 40 C to 85 C voltages are specified with respect to ground Vss Vpp 5 5 V unless otherwise specified Symbol Parameter Conditions Power supply Vpp supply voltage operating Ipp supply current Vpp 5 5 V Buffer ports SDA_IN SCL_IN SDA_OUT SCL_OUT Vi2c bus 12C bus voltage Vit LOW level input voltage Vpn 2 7 V Vpp 5 5 V Vin HIGH level input voltage Vpp 2 7 V Vpp 5 5 V Vinys hysteresis of input voltage Vpop 2 7 V Vpp 5 5 V Iu input leakage current lovsink output sink current VoL LOW level output volta
30. uards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In
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