AN10835 - NXP Semiconductors
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1. 16 below AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 11 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort instruction fetch memory fault 0x0000 0010 Data Abort data access memory fault 0x0000 0014 Reserved 0x0000 0018 IRQ 0x0000 001C FIQ Fig 15 ARM exception vector locations Mode Activation Usage Boot Hardware The Boot Loader always executes after any reset The Boot ROM Loader activation by interrupt vectors are mapped to the bottom of memory to allow mode any Reset handling exceptions and using interrupts during the Boot Loading process A sector of the Flash memory the Boot Flash is available to hold part of the Boot Code User Software Activated by the Boot Loader when a valid User Program Signature is Flash activation by recognized in memory and Boot Loader operation is not forced mode boot code Interrupt vectors are not re mapped and are found in the bottom of the Flash memory UserRAM Software Activated by a User Program as desired Interrupt vectors are mode activation by _re mapped to the bottom of the Static RAM user program User Software Activated by a User Program as desired Interrupt vectors are External activation by re mapped to external memory bank OL Memory user co2. EEPROM 24LC64 can be used on the MCB2300 board to test the 12C interface and protocol As shown in Fig 26 the 24LC64 works as an I2C slave with address of OXAO NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 17 of 21 NXP Semiconductors AN1 0835 AN10835_1 4 2 4 LPC2000 secondary bootloader for code update using IAP Note The SDA and SCL bus requires a pull up resistor to Vec typical 10 kQ for 100 kHz 2 kQ for 400 kHz The application code needs to be already programmed into EEPROM By typing command prog lt starting address gt the user application code will be copied from EEPROM via I2C interface onto internal flash at the address specified in the prog command Then input run lt starting address gt which should jump to the application 3 3V AO Vcc A we H GND 1K 1K A2 SCL P0 28 Vss SDA l P0 27 GND Fig 26 24LC64 circuit Code update via SD MMC The SD MMC bootloader utilizes a FAT file system so that the user can just copy the binary application code onto a SD Card from a workstation and then flash the application from the SD MMC interface Using this bootloader the user can list separate files located on the SD card and flash the microcontroller with the name specified See Fig 27 NXP B V 2009 All rights reserved Application
3. if EndSecNum lt StartSecNum return IAP STA INVALD PARAM command 0 IAP CMD EraseSec command 1 StartSecNum command 2 EndSecNum command 3 IAP_CLK 1000 iap entry command result return result 0 Fig 7 Erase sector 2 2 4 4 Program sector During this stage the data will be programmed from on chip RAM to Flash Note 1 Data can only be programmed from on chip SRAM to on chip Flash 2 The address in on chip Flash should be on a 256 byte boundary AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 7 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP 3 On chip RAM should be located on the local bus which means neither USB SRAM nor Ethernet SRAM can be used 4 Number of programmed bytes each time should be 256 512 1024 or 4096 Felele Function Name IAP CopyRAMToFlash Parameters unsigned long dst Destination Flash address should be a 256 byte boundary unsigned long src Source RAM address should be a word boundary unsigned long number 256 512 1024 4096 Return unsigned long Status Code Description This command is used to program the flash memory x zklelkooeoooookkk unsigned long IAP_CopyRAMToFlash unsigned long dst unsigned long sre unsigned long number command 0 IAP_CMD_CopyRAMToF lash command 1 dst command 2 sre command 3
4. internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 5 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof AN10835_1 Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications
5. 1 The FlashMagic tool is available for free at http www nxp com redirect flashmagictool com Software setup Keil uVision3 and Flashmagic are used to edit compile link debug and download the code Tera term or other tools is used for serial communication between PC terminal and MCB2300 and configured at 115200 baud 8 bits no parity 1 stop bit XON XOFF Because the IAP routines are run in thumb code the bootloaders need to have ARM Thumb interworking enabled Fig 21 shows the configuration in Keil uVision3 IDE Options for Target MCB2300_BL_CAN Device Target Output Listing User C C Asm Linker Debug Preprocessor Symbols Define Undefine gasse Code Generati vV Enable ARM Thumb Interworking Optimization Level3 03 v I Strict ANSI C I Enum Container always I Optimize for Time Plain Char is Signed Split Load and Store Multiple I Read Only Position Inde One ELF Section per Function J Read Write Position Indi Fig 21 Enable ARM Thumb interworking in KEIL uVsion3 IDE Start the demo The reason for having four different bootloaders instead of just one bootloader is to minimize the size of the secondary bootloader itself The smaller the bootloader the more flash is available for the user application At power on or reset a menu will be displayed in the Tera Term if properly configured Most of the functions listed in menu are same With these functions
6. 32 update_base_addr UNS_32 src_app_can_ptr src_app_can_ptr UN5_32 app_src_addr app_size_byte src_app_can_ptr 5 Number of bytes to copy if app_size_byte OxFFFFFFFF printft nNo user program size information n return 0 If no user program size information if app_size_ byte OxE1400000 Unknown size NOP instruction printf nUnknow size use default value Ox x n NAX_USER_PROG_53Z app_size byte MAX USER_PROG 32 Fig 20 Retrieve user application size in secondary bootloader NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 14 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP 4 Demo description AN10835_1 4 1 4 1 1 4 2 Demo setup Hardware setup This demo is tested on the KEIL MCB2300 evaluation board version 4 7 For more information about MCB2300 please refer to http www nxp com redirect keil com mcb2300 No other special hardware is needed except a RS 232 cable Standard USB A B cable for power and an EEPROM with IC interface if using the I C bootloader The RS 232 cable is for the connection between the PC and MCB2300 on COM1 The ULINK ME JTAG module can be used to program the bootloader onto the board Optionally the FlashMagic tool can be used to program the bootloader using the RS 232 cable connected onto UARTO COMO UART1 COM1 Setting 115200 baud 8N
7. 3xx devices containing 128 256 and 512 kB of flash respectively For other LPC2000 devices please refer to the user manual AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 3 of 21 NXP Semiconductors AN10835 AN10835_1 2 2 2 2 1 2 2 2 2 2 3 LPC2000 secondary bootloader for code update using IAP Sector Number 0 olulol ols wln a 9 10 0x0A 11 0x0B 12 0x0C 13 0x0D 14 0X0E 15 0x0F 16 0x10 17 0x11 18 0x12 19 0x13 20 0x14 21 0x15 22 0x16 23 0x17 24 0x18 25 0x19 26 0x1A 27 0x1B Sector Size kB CEGE ae Address Range 0X0000 0000 0Xx0000 1000 0x0000 2000 00000 3000 0x0000 4000 0X0000 5000 0X0000 6000 0x0000 7000 0x0000 8000 0x0001 0000 0x0001 8000 0x0002 0000 0x0002 8000 0x0003 0000 0x0003 8000 0x0004 0000 0x0004 8000 OX0005 7FFF 0x0005 8000 0x0006 0000 0x0006 8000 0x0007 0000 0x0007 8000 0x0007 9000 OX0007 AFFF 0X0007 BFFF 0x0007 C000 0x0007 D000 0x0005 0000 0x0007 A000 0x0007 B000 0x0000 OFFF 0x0000 1FFF 0X0000 2FFF 0X0000 3FFF 0X0000 4FFF 0x0000 SFFF 0X0000 6FFF 0x0000 7FFF 0X0000 FFFF 0X0001 7FFF 0x0001 FFFF 0x0002 7FFF 0X0002 FFFF 0X0003 7FFF 0x0003 FFFF 0X0004 7FFF 0X0004 FFFF Ox0005 FFFF Ox0006 7FFF OX0006 FFFF 0x0007 7FFF 0x0007 8FFF 0Xx0007 SFFF 0X0007 CFFF 0x0007 DFFF 128 kB Part x os
8. AN10835 LPC2000 secondary bootloader for code update using IAP Rev 01 26 May 2009 Application note Document information Info Content Keywords LPC2000 Secondary bootloader IAP Code update Abstract This application note describes the design and implementation of a secondary bootloader which can update the user application code in on chip flash via UART with 1K XMODEM protocol SD MMC with file system EEPROM with I2C interface and CAN interface using IAP In Application Programming founded by Philips NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP Revision history Rev Date Description 01 20090526 Initial version Contact information For additional information please visit http Avww nxp com For sales office addresses please send an email to salesaddresses nxp com AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 2 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP 1 Introduction In most LPC2000 devices the primary bootloader is the firmware which resides in the Boot Block and is executed every time the part is powered on or reset The secondary bootloader in this document refers to a user defined application that provides the user with an option to update the code or execute the previously programmed code In Application Programming IAP executes erase and write
9. LDR PC IRQ_Addr LDR Pc PC 0x0120 Vector from VicVectAddr LDR PC FIQ Addr Reset_Addr DCD Reset_Handler Undef_Addr DCD Undef_Handler SwI_Addr DCD SUI_Handler PAbt_Addr DCD Pabt_Handler DAbt_Addr DCD Dabt_Handler DCD o Reserved Address IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ Handler Copy Exception Vectors to Internal RAM IF PRR AM INTVEC ADR R8 Vectors Source LDR R9 RAN_BASE Destination LDMIA R8 RO R7 Load Vectors STMIA R9 RO R7 Store Vectors LDMIA R8 RO R7 Load Handler Addresses STMIA R9 RO R7 Store Handler Addresses ENDIF Fig 17 Vector table re mapping in user application file pc2300 s 3 2 3 User application size One key parameter needed to update the user application is the size of the application itself When loading the user application from the SD MMC or UART interface the end and the size of the binary file can be easily determined CAN and 1 C only handles the physical data transfers from the interface onto on chip memory Without an additional protocol loading the application via CAN or I C requires prior knowledge of the application size before it can be programmed into flash The following figures show how to record the image size NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 13 of 21 NXP Semiconductors AN1 0835 AN10835_1 LPC2000 secondary bootloader for code updat
10. OCIO sieneen enina 7 2 2 4 4 Program sector eeeeeoeeeeeeeeeeeeeeerenrreerrreene neee 7 2 2 4 5 Verify data cececcccceeceeeeeeenneeeeeeeeeeesneeeeeeeees 8 2 2 4 6 Interrupts during IAP eeren 8 2 2 4 7 RAMused by IAP command handler 9 2 2 4 8 Running the user application eee 9 3 Secondary bootloader and user application 10 3 1 Secondary bootloader cceescceeesseeeeeteeees 10 3 1 1 Bootloader Features and Constraints 10 3 2 User applicatiOM si esiisa 10 32 1 Memory MAP isic e ccc csaeecacetes eagtepes cciepeseeedeaseabiasas 10 3 2 2 Interrupt vector table re mapping eee 11 3 2 3 User application size 0 ee eeeeeeeeeeeeeeeneeeeeeeee 13 4 Demo description ececceeeeeeesneeeeeeeeeneeeees 15 4 1 Demo SOT pos cis soreer krakou iae Ei Ee a 15 4 1 1 Hardware setup eeeeeesrssserresrireerrresrrrrssrrnees 15 4 1 2 Software setup 0 00 eeeeeeeeeeeeeeeeeeeeeeeeeteneeteaeeeaes 15 4 2 Start the CEMO ecccecceeeceeseeeeeeeeeeeeeeeneeeeteeeeneees 15 4 2 1 Code update via UART eeeeeeeeeeeeteeteteeenees 16 4 2 2 Code update via CAN eeeeeeeteeeeeeeeeeeteeeeeees 17 4 2 3 Code update via 12C ee eceeeeeeteeeteeeteneeeneee 17 4 2 4 Code update via SD MMC eee eeeeeteeeeeeeeeee 18 5 Legal information csssseesseeeeseseeeesseeneeneee 20 5 1 DePiINItIONS 2 00 2 eee eeeeeeeee cece eeeeeeneeeeeeeeeeeeeeteeeeeeeeete
11. an execute the application by modifying the PC register by pointing it to the starting address of the application code define AP_ADDR 0x8000 where the user app located typedef void FP void 7 run the user application from pre specified address void Run_Application FP fp fp FP AP_ADDR fp 0 Fig 11 run the user application AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 9 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP 3 Secondary bootloader and user application AN10835_1 3 1 Secondary bootloader 3 1 1 After power on or reset the secondary bootloader will always run and display a menu on a PC terminal window e g Teraterm With this menu the user can erase or program the internal flash Depending on the bootloader selected the application code can be programmed using one of the four different interfaces UART SD Card I C or CAN The secondary bootloader resides in sectors starting at 0 and must not overlap the user application code 0x40008000 0x40008000 0x20 0x0 0x40000000 On chip Flash On chip RAM LPC2378 Fig 12 Bootloader memory map Bootloader Features and Constraints The UART SD MMC I C and CAN bootloaders function as a reference to allow the user to customize it to their particular needs The bootloaders at their current state have the followi
12. and therefore such inclusion and or use is for the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities 5 3 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 20 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP 6 Contents 1 Introduction s ssssssssseunsennnnennnnnnnunnennnnnnnnnnnnnnnnnnnnnnn 3 2 LPC2000 Flash Programming s cssessseeeee 3 2 1 Sector AESCHIPtION ceeeeeeeeeeeeeeeeneeeeeeetteeeeeeeeee 3 2 2 In Application Programming IAP nsee 4 2 2 1 IAP introductio crease 4 2 2 2 JAP application ciiisean 4 2 2 3 IAP COMMANASG ccceeeeeeeeteeeeeeeeeeeeeeteeeeeeeees 4 224 Using WAP cocccsceccassteessned scussses vices sirane ni ann 5 2 2 4 1 Define system parameters eeren 6 2 2 4 2 Select sector 0 eeeeeeseeeeeeeeeneeeeeeeteseeetsaeeeeees 6 224 3 Erase S
13. ation note Rev 01 26 May 2009 6 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP eeek Function Name IAP PrepareSec Parameters unsigned long StartSecNum Start Sector Number unsigned long EndSecNum End Sector Number Return unsigned long Status Code x Description This command must be executed before executing Copy RAM to Flash or Erase Sector s command zelek unsigned long IAP PrepareSec unsigned long StartSecNum unsigned long EndSecNum if EndSecNum lt StartSecNum return IAP STA INVALD PARAM command 0 IAP CMD PrepareSec command 1 StartSecNum command 2 EndSecNum iap_entry command result return result 0 Fig 6 Select sector 2 2 4 3 Erase sector Like other Flash implementations the LPC2000 on chip should be erased before programming However if the target sector is already erased it is not necessary to erase the sector again More than one sector can be erased at a time ekeeke ekeeke Function Name IAP EraseSec Parameters unsigned long StartSecNum Start Sector Number unsigned long EndSecNum End Sector Number Return unsigned long Status Code x Description This command is used to erase a sector or multiple sectors of on chip Flash memory x elelelekklklkilklkklkkkkkkkkkkkkk unsigned long IAP EraseSec unsigned long StartSecNum unsigned long EndSecNum
14. ble Refer to section 3 2 2 Fig 14 shows the memory configuration for the user application in Keil s uVision 3 IDE The on chip RAM is from 0x40000040 instead of 0x40000000 Options for Target MCB2300 FLASH S9 Device Target Output Listing User C C Asm Linker Debug Utiities NXP founded by Philips LPC2378 Code Generation Xtal MHz ARM Mode zi Operating system RTX Kemel I Use Cross Module Optimization Use MicroLIB F Bi r Read Only Memory Areas Read Write Memory Areas default off chip Start Size Startup default off chip Start Size Noli F ROMI c F RAMI ie a i ee a is ee a ia Fi onvs ff a 2c a orrehip on chip IRom1 0x10000 0x60000 G CF imami 040000040 08000 M ROMS P c RAMZ r Fig 14 Memory configuration for User application in Keil uVision 3 By changing the IROM1 Start address in uVision the user can change the starting location at which the application will be stored Note that it is important not to use a starting address that is located in a sector that contains the secondary bootloader 3 2 2 Interrupt vector table re mapping Because of the location of the interrupt vectors on the ARM7 processor at addresses 0x0000 0000 through 0x0000 001C as shown in Fig 15 below a small portion of the Boot ROM and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Fig
15. ctors from 9 to 9 Cmd gt blkehk 3 Sectors from 9 to 9 are blank Cmd gt ff Fig 22 Secondary bootloader menu 4 2 1 Code update via UART Type command prog lt starting address gt and then send a binary file using 1K XMODEM protocol See Fig 23 Then input run lt starting address gt which should jump to the application Note The address should be the same with the entry point of the binary file AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 16 of 21 NXP Semiconductors AN1 0835 AN10835_1 LPC2000 secondary bootloader for code update using IAP Tera Term COM1 VT Tera Term XMODEM Send AG Edit Setup Control Window Help Look in je HEXSBIN file e ef New connection At N fe E binky7 bin E binky22 bin ae aa Log loader via XMODEM 9 blinky7 hex blinky22 hex Send file t function E blinky9 bin 9 blinkyR7L19 hex Ze uot loader info blinky9 hex blinkyR21L19 hex Ch direct XMODEM gt Recei lark SS blinky21 bin gt blinkyR22L19 hex change directory amp MOD Receive ani blinky21 hex 5 peace oe zwom gt Print Alt P i he FLASH B Plus address default 0x10000 Disconnect Quick VAN gt ile and program to addr 7 E Atro laoor app address default 0x10000 Filename blinky9 bin oe a displays this help Heessenerneeessssersesee
16. de mode Fig 16 LPC2300 Memory mapping modes The portion of memory that is re mapped allows for interrupt processing in different modes and includes the interrupt vector area 32 bytes as well as an additional 32 bytes a total of 64 bytes to facilitate branching to interrupt handlers at distant physical addresses The remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F The interrupt vectors of the secondary bootloader occupies the physical address from 0x0000 0000 through 0x0000 003F in on chip flash thus the interrupt vectors for the user application has to be re mapped to the bottom of the on chip SRAM using User RAM Mode Before entering the main application the user should copy the 64 bytes 32 bytes interrupt vector and 32 bytes additional bytes into the bottom of the on chip RAM and set the mapping mode to User RAM Mode Fig 17 shows how to copy the 64 bytes of interrupt vectors from on chip flash to the bottom of on chip RAM AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 12 of 21 NXP Semiconductors AN1 0835 AN10835_1 LPC2000 secondary bootloader for code update using IAP Area Definition and Entry Point Startup Code must be linked first at Address at which it expects to run AREA RESET CODE READONLY ARM Vectors LDR PC Reset_Addr LDR Pc Undef_Addr LDR PC SWI_Addr LDR PC Pabt_Addr LDR PC Dabt_Addr NOP
17. e using IAP AREA RESET CODE READONLY ARN IF DEF 51ZE_INT_INFO IMPORT Image ER_IROM1 RO Length IMPORT Image RWU_IRAM1 RW Length ELIF DEF SIZE_EXT_INFO IMPORT Image ER_ROM1 RO Length IMPORT Image RW_RAM1 RW Length ENDIF Exception Vectors Mapped to Address 0 Absolute addressing mode must be used Dummy Handlers are implemented as infinite loops which can be modified EXPORT Vectors Vectors LDR PC Reset_Addr LDR PC Undef_Addr LDR Pc SWI_Addr LDR Pc PaAbt_Addr LDR Pc Dabt Addr Reserved vector is used for image size information IF DEF 5IZE_INT_INFO DCD Image ER_IROM1 RO Length Image RWJ_IRAM1 RW Length ELIF DEF 51ZE_EXT_INFO DCD Image ER_ROM1 RO Length Image RW_RAM1 RW Length LDR PC IRQ Addr LDR PC PC 0x0120 Vector from VicVectAddr LDR PC FIQ Addr Fig 18 Record user application image size in lpc2300 s Options for Target MCB2300 FLASH S9 Device Taraet Output Listing User C C Asm Linker Debug Utilities Conditional Assembly Control Symbols a SESE De fre REMAP RAM_MODE RAM_INTVEC SIZE_INT_INFO Undetine Language Code Generation Enable ARM Thumb Interworking I Split Load and Store Multiple TM Raadin Pasitinn Indanandant Fig 19 Control symbols definition for lpc2300 s in user application UNS_32 CAN Update UN5_32 app_src_addr UN5_
18. gt e f gt e os gt f oe gt e gt e oe 256 kB Part x xix x xix x xix a aa 2 2 512 kB Part x x x x x xef gt gt gt gt gt e gt e gt e gt e xe gt e gt e gt e gt e gt e gt e f gt e gt e gt e f gt e gt e gt e f gt e Fig 1 Sectors in LPC2300 devices In Application Programming IAP IAP introduction A boot code 8 kB in size is programmed into the on chip flash after factory The boot code controls initial operation after reset and also provides the means to accomplish programming of the flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the Flash memory by the application program in a running system In Application Programming IAP executes erase and write operations on the on chip flash memory as directed by the end user application code IAP application Using IAP users can update the application code by various communication interfaces such as UART USB or Ethernet Flash sectors that aren t used for the secondary bootloader or the user application may be used as non volatile data storage While the application is running the user can update some portion of the code using IAP commands which we call online code updates It is not necessary to power off or even to remove the chip from the board to have it serviced by some commercial pr
19. ite operations When the user application code starts executing the interrupt vectors from the user flash area are active AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 8 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP The user should either disable interrupts or ensure that the user s interrupt vectors reside and are active in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts __swi 0x00 void SwiHandlel int Handle Hdefine IRQDisable SwiHandlel 0 Hdefine IRQEnable SwiHandlel 1 prepare and erase the sectors with index from start to end if successful return TRUE elsewise FALSE BYTE IAP_PrepareErase Sector DWORD start DWORD end DWORD IAP status BYTE result FALSE IRQDisable IAP _status IAP PrepareSec start end if IAP status IAP STA CMD SUCCESS IAP _status IAP EraseSec start end if IAP status IAP STA CMD SUCCESS result TRUE IRQEnab le return result Fig 10 Interrupt handle during IAP 2 2 4 7 RAM used by IAP command handler Flash programming commands use the top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 bytes for LPC2300 and grows downwards 2 2 4 8 Running the user application After loading the application the user c
20. ng design constraints and features e The bootloader s default user application code starting address is 0x10000 e The bootloader will always wait for user input before continuing on into the application code The bootloader has no knowledge whether user code is present or where it is located at in flash The SD MMC bootloader requires a SD Card to be inserted for proper operation The SD MMC bootloader allows the user to select which binary file should be flashed onto the microcontroller If the application code utilizes interrupts it needs to maintain its own interrupt vector table in SRAM see section 3 2 2 The user application s starting address can be changed at compile time however it must match the address at which the code is to be programmed using the bootloader 3 2 User application 3 2 1 Memory map The user application is located in different sectors along with the secondary bootloader and consumes the on chip RAM starting from 0x40000000 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 10 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP 0x40000000 0x40 0x40000000 On chip Flash On chip RAM LPC2378 0x0 Fig 13 User application memory map If the user application utilizes interrupts the first 64 bytes 0x40 at the bottom of the on chip RAM should be used as the interrupt vector ta
21. note Rev 01 26 May 2009 18 of 21 NXP Semiconductors AN10835 LPC2000 secondary bootloader for code update using IAP Fig 27 Code update via SD MMC Tera Term COM1 VT File Edit Setup Control Window Help LPC2000 Bootloader via SD MMC AO GOMES TUU ikli nY eae ee ge ne INFO display the bootloader info READID read part ID DIR mask displays a list of files in SD MMC BLECHK fromLidx to_idx check if flash sectors are blank ERASE from_idx to_idx erase flash sectors RUN nnn Run application in internal FLASH nnmn app address default 0x10000 PROG fname bin nnnn Program flash using a BIN file nnnn app address default 0x10000 HELP or displays this help Laana E S A EE S s O Cmd gt dir File System Directory BLINK Y BIN 5 652 09 01 2009 17 41 BLINKY9 BIN 5 652 09 01 2009 17 42 BLINKY22 BIN 5 652 09 01 2009 17 42 3 File s 16 956 bytes Cmd gt prog blinkyS bin Ox10000 Programming blinky3 bin to Ox10000 5652 bytes programmed Cmd gt run 0x10000 Run applicaiton at O0x10000 AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 19 of 21 NXP Semiconductors AN10835 LPC2000 secondary boot loader for code update using IAP 5 Legal information 5 1 Definitions Draft The document is a draft version only The content is still under
22. number command 4 IAP CLK 1000 Feclk in KHz iap_entry command result return result 0 Fig 8 Program sector 2 2 4 5 Verify data With this function user does not have to write their own code to compare the data in RAM and Flash Note Source address destination address and number of bytes should be a word boundary or a multiple of 4 eelloo Function Name IAP Compare Parameters unsigned long dst Destination Flash address unsigned long src Source RAM address unsigned long number Should be in mutilple of 4 Return unsigned long Status Code Description This command is used to compary the memory contents at two locations NOTE Compary result may not be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes can be re mapped to RAM Jebbicbsobebebeisooisiobioleistbioiotieloiosobieisiobooleoisioloissoieiststooiotsiooloiotooleiotototoieiotototoiototok unsigned long IAP Compare unsigned long dst unsigned long src unsigned long number unsigned long offset command 0 IAP_CMD_ Compare command 1 dst command 2 src command 3 number iap_entry command result if result 0 IAP_STA_COMPARE_ERROR xoffset result 1 return result 0 Fig 9 Verify data 2 2 4 6 Interrupts during IAP The on chip flash memory is not accessible during erase wr
23. odes are listed in Fig 3 IAP Command Command Code Prepare sector s for write operation 5019 Copy RAM to flash 5149 Erase sector s 5210 Blank check sector s 5340 Read Part ID 5449 Read Boot code version 5549 Compare 5610 Reinvoke ISP 5710 Fig 3 IAP command summary For detailed information please refer to the LPC2000 user manual 2 2 4 Using IAP Fig 4 shows the necessary steps to perform the flash programming using IAP AN10835_1 NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 5 of 21 AN10835 LPC2000 secondary bootloader for code update using IAP NXP Semiconductors Define system parameter y Select sector y Erase sector Y Select sector y Program sector y Verify data Fig 4 Flash programming steps 2 2 4 1 Define system parameters Some constants such as system clock IAP entry point input and output buffers should be defined before an IAP call define IAP CLK Feclk define IAP LOCATION Ox7FFFFFF1 define iap entry a b void IAP_LOCATION a b unsigned long command 5 0 0 0 0 0 unsigned long result 3 0 0 0 Fig 5 Define system parameter 2 2 4 2 Select sector The sectors have to be selected before any erase or programming operation More than one sector can be selected NXP B V 2009 All rights reserved AN10835_1 Applic
24. ogramming tools Having the device work as data storage PCB costs and sizes can be reduced Caution is however advised in handling data storage sectors Since sectors functioning as data storage can be erased no application code should be contained in these sectors Frequent erasing and programming will reduce the flash s lifecycle The LPC2000 provides a minimum of 10 000 write erase cycles and 10 years of data retention IAP commands For in application programming the IAP routine should be called using a word sized pointer that has been loaded into register rO which is pointing to memory on chip RAM NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 4 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP containing the command code and its parameters Register r1 contains the results of the IAP command returned by a pointer pointing to a table The user can reuse the command table for the results by passing the same pointers into registers r0 and r1 Ensure that the results table is large enough to store all the results coming from the IAP command issued Refer to Fig 2 COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n command parameter table ARM REGISTER ro ARM REGISTER r1 STATUS CODE RESULT 1 RESULT 2 RESULT n command result table Fig 2 IAP parameter passing The IAP commands and c
25. operations on the on chip flash memory as directed by the end user application code Code update is a typical application of IAP This document describes four secondary bootloaders using different interfaces UART using the 1K XMODEM protocol SD MMC using a FAT file system I2C interfaced to EEPROM and CAN 2 LPC2000 flash programming 2 1 Sector description The IAP commands operate on a sector by sector basis This means that in order to make any modifications even if it is just one byte in a particular sector the entire sector must be erased The user application and the secondary bootloader share the same on chip flash space This means that the user s application code should not be placed inside any of the sectors on which the bootloader resides Therefore the application should be erased and programmed in sectors separate from the bootloader IAP ISP and RealMonitor routines are located in the primary bootloader Boot block The boot block is present at addresses 0x0007 E000 to 0x0007 FFFF 8 kB in all devices Depending on the device not all of the flash is available to the user This is the case if the part contains 512 kB of flash Rather than having 512 kB available the user will only have 504 kB available for the application In devices that have less than 512 kB flash available please refer to the respective user manuals Fig 1 indicates the correspondence between sector numbers and memory addresses for LPC2
26. s 20 5 2 Disclaimer S insorite ienne 20 5 3 Trademarks cccccceeeceeeeeeeeeeeeeenneeeeeeeeeeenseeeees 20 6 COMPOS se seisceceeseee cee ster inie ein enasi evened enters 21 Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information founded by NXP B V 2009 All rights reserved For more information please visit http www nxp com For sales office addresses email to salesaddresses nxp com Date of release 26 May 2009 Document identifier AN10835_1
27. sse N EA KERE Files of type fj i Cancel Cmd gt prog Ox10000 Help Application address 0x10000 r Option Please transfer a BIN file via 1K XMODEM Checksum CAC ceececeececeececeececeececeeced l Fig 23 Update via 1K XMODEM 4 2 2 Code update via CAN To simplify the test of the CAN interface and protocol CAN1 will act as transmitter and CAN2 as receiver on the MCB2300 board Since CAN transceivers are already integrated in MCB2300 the user only needs to connect pins 2 and 7 directly together to both CANs as shown in Fig 24 1 y 3 4 5 1 2 3 4 5 o o o o o o o o o 6 T 8 E 6 7 8 9 o o o o P o o CAN2 CAN1 Fig 24 CAN port connection The user application is linked at address of 0x70000 but is programmed at address 0x60000 Afterwards type prog 0x60000 0x70000 This causes the user application code to be copied from address 0x60000 onto address 0x70000 via the CAN interface Cmd gt prog 0x60000 0x70000 Start to update app at 0x70000 copyied from Ox60000 via CAN App size 5652 bytes iap progrom number 6 1024 bytes once Prepare and erase sector 21 Program at addr Ox70000 Program at addr 0x70400 program at addr 0x70800 program at addr 0x70c00 Program at addr 0x71000 program at addr 0x71400 6144 bytes programmed Cmd gt run 0x70000 Bun applicaiton at Ox70000 Fig 25 Code update via CAN 4 2 3 Code update via 12C An additional
28. the user can erase or program the flash with the application code using a specific interface NXP B V 2009 All rights reserved Application note Rev 01 26 May 2009 15 of 21 NXP Semiconductors AN1 0835 LPC2000 secondary bootloader for code update using IAP Throughout this section lt starting address gt refers to the actual address which should be entered into the serial terminal For example if you want to use address 0x10000 and the command is shown as prog lt starting address gt then the user should type prog 0x10000 Tera Term COM1 VT File Edit Setup Control Window Help LPC2000 Bootloader via XMODEM command PUNCH ON saan paneer eatS INFO display the bootloader info READID read part ID BLKCHK from_idx to_idx check if flash sectors are blank ERASE from_idx to_idx erase flash sectors Run application in internal FLASH RUN addr addr app address default 0x10000 PROG addr Dowload BIN file and program to addr addr app address default 0x10000 HELP or displays this help t iCmd gt info Boot loader Entry 0x0 Size Ox2eb0 bytes 11952 Sectors 0 to 2 Yersion Jan 20 2009 iCmd gt readid Part ID 0x1700fd25 Offset of the first non blank word location is 0x0 Cmd gt erase 9 Erased se
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