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1. So 999099999 19 L7 L5 13 118116114112 LICALILI LIC TL IET is L6 14 12 117115113111 89990690 CB4 t t mmm 20 95 8 Figure 16 Location of Connectors on the phyCORE Development Board HD200 PHYTEC Messtechnik GmbH 2006 L 658e_5 79 phyCORE LPC2292 94 Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals 80 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 2 2 Jumpers on phyCORE Carrier Board HD200 Peripheral components of the phyCORE Carrier Board HD200 can be connected to the signals of the phyCORE LPC2292 94 by setting the applicable jumpers The Carrier Board s peripheral components are configured for use with the phyCORE LPC2292 94 by means of insertable jumpers If no jumpers are set no signals connect to the DB 9 connectors the c
2. uz ve L Lus ud Figure 22 Location of Components at U12 and U13 for Power Supply to External Subassemblies PHYTEC Messtechnik GmbH 2006 1 658 5 91 phyCORE LPC2292 94 The components at U12 and U13 guarantee electronic protection against overvoltage and excessive current draw at pin 6 of PIA in particular Load detection and controlled voltage supply switch on In order to ensure clear detection of the switch on condition the connected device should cause a current draw of at least 10 mA at pin 6 The controlled voltage supply switch on prevents voltage drop off on the phyCORE Carrier Board HD200 Overvoltage Protection If the voltage at pin 6 exceeds the limiting value that can be provided by the phyCORE Carrier Board HD200 the voltage at pin 6 will be switched off immediately This prevents damage to the phyCORE Carrier Board HD200 as well as connected modules and expansion boards Overload Protection If the current draw at pin 6 exceeds the limiting value of approximately 150 mA the voltage at pin 6 will be switched off immediately This prevents damage to the phyCORE Carrier Board HD200 and its power adapter caused by current overload This configuration option provides the following possibility Jumper Setting Description JP24 2 3 Electronically protected 5 V at pin 6 for supply of external devices connected to PIA Table 53
3. 9 1 MAC Address The MAC Media Access Control address is a unique identification code of computer hardware operating within a LAN Local Area Network When connecting the hardware to the Internet the assigned IP number is mapped to the MAC address via a conversion table The MAC addresses are administered in a central location in order to ensure the uniqueness of these numbers PHYTEC has purchased a pool of such MAC addresses and each one of our Ethernet based Single Board Computers gets one of these addresses The MAC address of your phyCORE LPC2292 94 is printed on a barcode sticker attached to the module The MAC address is provided as a 12 digit hexadecimal value In addition the MAC address is also programmed into the Ethernet controller EEPROM 0500 at the time of delivery This allows immediate start up of the module and its Ethernet hardware Following a hardware reset the MAC address is automatically loaded from the EEPROM into the Ethernet controller refer to section 9 2 60 PHYTEC Messtechnik GmbH 2006 1 658 5 LAN9ICIII Ethernet Controller 0501 9 2 Ethernet EEPROM U500 The EEPROM connected to the Ethernet controller can be used to store specific confguration data that are automatically loaded into the LAN9ICI11 following a hardware reset The EEPROM be programmed on board via the Ethernet controller Please refer to the SMSC LAN9ICIII Ethernet controller datasheet for details The
4. 29 J300 Flash Ready Busy Configuration 30 J301 J302 Flash Write Protection Configuration 3l J400 J401 SRAM Access 32 J402 SRAM Supply Voltage Configuration 32 J503 Ethernet Chip Select Signal Configuration 33 J501 Ethernet Interrupt Signal Configuration 33 J503 Ethernet Ready Signal Configuration 34 J504 Ethernet LAN IRQ Pull up Configuration 34 J505 J506 J507 Ethernet EEPROM Configuration 34 J508 Ethernet EEPROM Enable Configuration 35 1509 Ethernet nLNK Pin Configuration 35 J600 7601 CAN Transceiver 36 1616 CAN Transceiver Supply Configuration 37 1602 J603 J604 and J605 CAN Interface Configuration 38 J606 EEPROM Write Protection eene 38 J607 Watchdog Configuration sese 39 1608 J609 J610 Interface Configuration 40 J611 7612 J613 J614 SPI Interface Signal Configuration 40 1615 Level Configuration 41 7616 J617 CAN Transceiver VCC at Pin 5 42 J618 VDD V3V3 Supply 43 J619 J620 SPI Master Slave Selection
5. 85 Pin Assignment of the DB 9 Socket as First RS 232 Front VIEW EES E AEE arih 89 Location of Components at U12 and U13 for Power Supply to External 5 91 PHYTEC Messtechnik GmbH 2006 1 658 5 Contents Figure 23 Pin Assignment of the DB 9 Socket P1B as Second RS 232 Front View ccccccccsesececseseseseseseseseseseseees 93 Figure 24 Pin Assignment of the DB 9 Plug P2A CAN Transceiver on phyCORE LPC2292 94 Front View 95 Figure 25 Pin Assignment of the DB 9 Plug P2A CAN Transceiver on Carrier TTE NORRIS 96 Figure 26 Pin Assignment of the DB 9 Plug P2A CAN Transceiver on Carrier Board with Galvanic Separation 99 Figure 27 Pin Assignment of the DB 9 Plug P2B CAN Transceiver phyCORE LPC2292 94 Front 101 Figure 28 Pin Assignment of the DB 9 Plug P2B CAN Transceiver on Carrier VEN 102 Figure 29 Pin Assignment of the DB 9 Plug P2B CAN Transceiver on Carrier Board with Galvanic Separation 105 Figure 30 Pin Assignment Scheme of the Expansion Bus 109 Figure 31 Pin Assignment Scheme of the Patch Field 109 Figure 32 Connecting 052401 Silicon Seria
6. 41 CAN 36 56 d 37 CANDHI 37 37 anne 37 CANH een 56 BAR es 56 CANRX 56 CANTI ee 56 Carrier Board Connectors and JWINPETS i aede ka 79 CEKIN adit cot 46 COM Poft 55 Concept of the Carrier Board 77 Connector 119 28 29 Debug Interface nase 65 debugCORE LPC2292 94 69 Dimensions 74 IDS 240 se 118 E EEPROM Serial 57 EEPROM Write Protection 38 EN nn 1 Ert ate nasse 67 Ethernet ea 59 Ethernet Controller 33 Ethernet EEPROM 61 Ethernet Chip Select 23 Ethernet EEPROM 34 Ethernet EEPROM Enable 35 Ethernet Interrupt Signal 33 Ethernet LAN IRQ 34 Ethernet nLNK 35 Ethernet Ready Signal 34 were 45 Expansion Bus 108 F FS AUIS ae 4 First CAN Interface 95 First Serial Interface 89 Flash Write Protection 3l Flash Memory 58 uere mete 28 Functional Components on the phyCORE Carrier Board 84 H Humidity serre teet bet 74 I 40
7. 87 JP41 phyCROE LPC2292 94 Boot Memory Cone IEdE dtl t RS edid n 88 Jumper Configuration for the First RS 232 Interface 89 Improper Jumper Settings for DB 9 Socket P1A as First RS 232 ES 90 JP24 Power Supply to External Devices Connected to PiLA on the Carrier Board ei aa 92 Jumper Configuration of the DB 9 Socket PIB SECOURS 32 see 93 Improper Jumper Settings for DB 9 Socket PIB SECOUBS 232 94 PHYTEC Messtechnik GmbH 2006 L 658e 5 phyCORE LPC2292 94 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the 1 2292 94 95 Jumper Configuration for CAN Plug P2A using the Transceiver on the Carrier Board 200 96 Improper Jumper Settings for the CAN Plug P2A CAN Transceiver on the Carrier 97 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Carrier Board with Galvanic Separation 98 JP39 CAN Bus Voltage Supply Reduction 99 Improper Jumper Settings for the CAN Plug P2A CAN Transceiver on Carrier Board with Galvanic Separation 100 Jumper Configuration for CAN Plug P2B using the CAN
8. 124 PHYTEC Me technik GmbH 2006 L 658e 5 Component Placement Diagram 19 Component Placement Diagram X0 p 8 ar J300 1 1 R30 5 E I R30 RN200 El J401 J205 6 E2400 J402 8 gt eo gt e 7 t R202 J207 65 0303 R200 C206 1 Lu CB633 J612 X613 ZI J614 5S 711 501 Cres S 200 201 600 J601 J615 J202 CB 33 Xi 501 C500 Figure 36 phyCORE LPC2292 94 Component Placement Top View PHYTEC Messtechnik GmbH 2006 1 658 5 125 phyCORE LPC2292 94 CB620 I RN502 C3 RN503 8615 5 E J620 p 1619 R622 I 1 R621 2 RN500 R506 a R502 505 RN600 8616 RN700 C211 R213 r op oe em C212 R700 R211 R212 Figure 37 phyCORE LPC2292 94 Component Placement Bottom View 126 PHYTEC Me technik GmbH 2006 L 658e_5 Index Index 1 10 100 Mbps Ethernet 59 10Base T Interface 61 A A D Converter 26 B BAT 118 Battery 63 Battery Connector 118 Block Diagram 6 Boot Memory Configuration 88 C CAN 56 CAN 37 56 CAN Level
9. Pe Wd EG phyCORE LPC2292 94 Hardware Manual Edition July 2006 A product of a PHYTEC Technology Holding company phyCORE LPC2292 94 In this manual are descriptions for copyrighted products that are not explicitly indicated as such The absence of the trademark and copyright symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is believed to be entirely reliable However PHYTEC Messtechnik GmbH assumes responsibility for any inaccuracies PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2006 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including those of translation reprint broa
10. PHYTEC Messtechnik GmbH 2006 1 658 5 127 phyCORE LPC2292 94 ISP Command ISP Mod nen as ee 41 JONG essen 36 42 42 TOT acts Duet aa aga 43 43 43 62 S OR PATI 44 J622 ne 44 Please 45 45 002 NS 67 see 107 TP ED sense 118 107 JPA lp 88 JTAG Interface 65 JTAG Emulator Adapter 67 Jumper Configuration 81 Jumper Settings 24 L EAN SERO sack 33 I NN CRY nasse 33 LAN9 ICII I na 33 59 DEED D3 ren 107 M MAC Address 60 ee 21 Operating Temperature 74 Operating Voltage 74 P ei 33 POST 44 Pateh Field sea 108 62 23125 nod ore 56 phyCORE connector 9 12 Physical Dimensions 73 PHYTEC Me technik GmbH 2006 1 658 5 Pin Assignment 108 SRAM Supply Voltage 32 Pin Description 9 Storage Temperature 74 16 System Configuration 47 PIOS ae 95 T Plus eus 101 Power Consumption 74 Technical Specifications 73 Power 1 84 6250 33 000 37 56 Power Supply to External Devices via Soc
11. 019 19 19 6 P020 4A 4A 29A P021 24C 24C 8B P022 25C 25C 8D P027 AINO 50C 50C 17A P028 AIN1 49C 49C 16F P029 AIN2 48D 48D 16B P030 AIN3 48C 48C 16 Table 72 Pin Assignment Port PO for the phyCORE LPC2292 94 Carrier Board Expansion Board 1 Check configuration of Jumper J200 on the phyCORE LPC2292 94 refer to section 3 1 2 Check configuration of Jumper J202 on the phyCORE LPC2292 94 refer to section 3 1 PHYTEC Messtechnik GmbH 2006 1 658 5 113 phyCORE LPC2292 94 Signal phyCORE Module Expansion Bus Patch Field P1 16 25D 25D 8F P1 17 TRACEPKT1 26D 26D 9E P1 18 TRACEPKT2 29C 29C 10 P1 19 TRACEPKT3 30C 30C 10E P1 20 TRACES YNC 30D 30D 10B P1 21 PIPESTATO 31D 31D 11A P1 22 PIPESTAT1 41 41 14 P1 23 PIPESTAT2 41D 41D 14E P1 24 TRACECLK 42D 42D 14B P1 25 EXTINO 43C 43C 14F P1 26 RTCK 37D 37D 12F P1 27 TDO 38D 38D 13E P1 28 TDI 38C 38C 13A P1 29 TCK 40C 40C 13D P1 30 TMS 40D 40D 13F P1 31 TRST 39C 39C 13B Table 73 Pin Assignment Port for the phyCORE LPC2292 94 Carrier Board Expansion Board 114 PHYTEC Me technik GmbH 2006 L 658e 5 phyCORE LPC2292 94 on the phyCORE Carrier Board Signal phyCORE
12. 43 J621 WDI Signal Source osito ec teal ERE 44 J622 RESET Signal SOUICE ci deter eer et re et o 45 PHYTEC Messtechnik GmbH 2006 L 658e 5 Contents Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 J800 1801 ETM OCDS Connector Configuration DCNME023 Only 45 C210 CLKIN Configuration ein 46 System Startup Configuration Boot Device Selection 47 System Startup Configuration Debug Trace Port 48 CS Signal Bank Address Ranges and Configuration Registers ue ctn e berto pec toes 50 Memory Device Options for U607 57 Memory Area Ethernet Controller 60 ITAGAand TRACEM 0488 67 debugCORE LPC2292 94 DIP Switch S800 70 ETM OCDS Connector at X800 een 71 LAN Connector at X500 eese 72 Improper Jumper Setting for JP30 33 the Carrier Board 83 JP9 JP16 Configuration of the Main Supply Voltages VEC RR es 84 JP9 JP16 Improper Jumper Settings for the Main S pply Voltages een ee 85 JP28 Configuration of the Boot Button 86 JP28 Configuration of a Permanent ISP Mode Start
13. J612 613 Q 614 J502 fl 1 J509 12 508 4507 oO os 4501 J503 J505 J504 I ES X701 Figure 6 Location of the Jumpers Top View PHYTEC Messtechnik GmbH 2006 1 658 5 17 phyCORE LPC2292 94 Figure 7 Location of the Jumpers Bottom View 18 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers The jumpers J solder jumper have the following functions Default Setting Alternative Setting J200 1 2 P08 as TxD1 with RS 232 2 3 P08 of the uC available as level available at X700C23 standard I O or TxD1 with TTL level at pin X700C23 201 1 2 as TxDO with 5 232 2 3 of uC available as level available at X700D23 standard I O or TxDO with TTL level at pin X700D23 202 1 2 P09 as RADI with 5 232 2 3 P09 of the uC available as level available at X700C21 standard I O or RxD1 with TTL level at pin X700C21 203 1 2 P01 RxDO with RS 232 2 3 P01 of the uC available as level available at X700D22 standard I O or RxDO with TTL level at pin X700D22 J204 1 4 2 VDD V3V3 as reference 2 3 Reference voltage for internal voltage for CPU internal A D converter can be supplied A D converter via pin X700D50 J205 closed CSO connected with CSFO open CSO of the controller only if CPLD U202 is not connected with CPLD U202 populated CPLD generates CSFO CSF1 signals J206 closed CS1 connected wit
14. 565 e 0x8400 0000 free usable memory area at CS3 0x8300 0000 optional Ethernet device at CS2 0x8200 0000 Up to 8MB ext RAM at CS1 0x8100 0000 Up to 16MB ext FLASH at CSO 0x8000 0000 remapped Boot Block 0x4000 1FFF 16kB On Chip Static RAM 0x4000 0000 optional 128kB On Chip Non Volatile Memory 0x0002 0000 optional 128kB On Chip Non Volatile Memory 0x0000 0000 0x0004 0000 Figure 8 phyCORE LPC2292 94 Memory Model The following formula is used to calculate the timing settings for any access on the external asynchronous bus Standard read access WSTI gt tram 201 t 2 Standart write access WST2 gt twnrre tcyc 5 ns where fmax tram Memory acces time read of external memory Twr rE memory access time write of external memory PHYTEC Messtechnik GmbH 2006 1 658 5 51 phyCORE LPC2292 94 Please refer to the corresponding controller data sheet and application notes from Philips for more details on bus timing configuration The following section contains two examples of the controller s configuration registers These examples match the needs of most standard applications for the phyCORE LPC2292 94 Example a Module Configuration e Flash access time 90 ns e SRAM access time 10 ns without PLD BCFGO Register Configuration Value 0x02000 28A3 IDCY 3 gt Aidle cycle WSTI 3 gt 8 CCLK cycles RBLE 0 gt byte
15. JP24 Power Supply to External Devices Connected to on the Carrier Board 92 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 3 6 Second Serial Interface at Socket PIB Socket is the upper socket of the double DB 9 connector at P1B is connected via jumpers to the second serial interface of the phyCORE LPC2292 94 The following description is based on a module configuration that utilizes the on board RS 232 transceivers for the second serial interface refer to section 3 1 Jumper Setting Description JP1 closed Pin 2 of DB 9 socket PIB connected with RS 232 signal TxD1_RS232 of the phyCORE LPC2292 94 JP2 open Pin 9 of DB 9 socket P1B not connected JP3 open Pin 7 of DB 9 socket P1B not connected JP4 open Pin 4 of DB 9 socket P1B not connected JP5 open Pin 6 of DB 9 socket P1B not connected JP6 open Pin 8 of DB 9 socket P1B not connected JP7 open Pin 1 of DB 9 socket P1B not connected JP8 closed Pin 3 of DB 9 socket P1B connected with RS 232 signal RxD1_RS232 of the phyCORE LPC2292 94 Table 54 Jumper Configuration of the DB 9 Socket Second RS 232 1 2 2 Pin 2 TxD1 3 1 3 RxDI 5 5 Pin 5 GND Figure 23 Pin Assignment of the DB 9 Socket as Second RS 232 Front View 1 Check configuration of Jumper J200 on the phyCORE LPC2292 refer to section 3 1 2 Check configuration of Jum
16. 20B 21B DO DS Data line of the microcontroller 22B 28B 30B D6 D8 D11 31B 32B 37B D13 D14 D16 38B 40B 41B D18 D21 D23 42B 43B 45B D24 D26 D29 o Low active Byte Lane Select signal Bank1 Freely programmable PLD signal may be used as additional Chip Select signal 50B Pin Row X700C 1C 2C Voltage input 3 3 VDC 3C 7C 12C 17C GND Ground 0 V 22C 27C 32C 37C 4C 5C VDD V5VO Voltage input 5 VDC 6C VBAT I Battery input for back up of RTC and optional buffering of RAM 8C N C Not connected 9C BOOT I Boot input of the phyCORE module switches controller into boot mode during reset 10C RESET output of the phyCORE LPC2292 94 11C FS2 VO Freely programmable PLD signal may be used as additional Chip Select signal 13C P010 Port P010 of the microcontroller see data sheet 14 P012 I O Port PO12 of the microcontroller see data sheet 15C P013 Port P013 of the microcontroller see data sheet 16C P018 Port P018 of the microcontroller see data sheet PHYTEC Messtechnik GmbH 2006 1 658 5 13 phyCORE LPC2292 94 Pin Number Signal Description Pin Row 700 18C CAN_H2 IO Differential CANH line of second CAN transceiver alternative P024 if J603 populated
17. 27B 36F A23 28A 28A 37A Table 70 Pin Assignment Address Bus for the phyCORE LPC2292 94 Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2006 1 658 5 111 phyCORE LPC2292 94 Signal phyCORE Module Expansion Bus Patch Field CSO 5A 5A 29E CS1 5 5 29 CS2 6A 6A 29D CS3 6B 6B 29F 0 35 35 9 1 35 35 39B FS2 11C 11C 4 FS3 43D 43D 15 FS4 44C 44C 15C FS5 45C 45C 15E BLSO 34A 34A 39A BLS1 33B 33B 38F BLS2 36A 36A 39D BLS3 36B 36B 39F OE 7B 7B 30A WE 8A 8A 30E RESIN 10D 10D 3F RESET 10C 10C 3D BOOT 9C 9C 3B PWROFF 20C 20C 7A INT RTC 33D 33D Table 71 Pin Assignment Address Control Bust for the phyCORE LPC2292 94 Carrier Board Expansion Board 112 PHYTEC Me technik GmbH 2006 L 658e 5 phyCORE LPC2292 94 on the phyCORE Carrier Board Signal phyCORE Module Expansion Bus Patch Field TxDO 17D 17D 6C P01 RxDO 16D 16D 6A P02 47 47 43E 48 48 43 P04 48B 48B 43F POS 49A 49A 44A P06 50 50 44 P07 50B 50B 44B P08 TxD1 11D 11D 4A P09 RxD1 12D2 12D 4B P010 13C 13C 4 P011 13D 13D 5A P012 14C 14C 5 P013 15C 15C 5E P014 IRQ1 3A 3A 28B P015 IRQ2 3B 3B 28F P016 IRQO 2B 2B 28E P017 15D 15D 5B P018 16C 16C
18. 2A 7A 12 17 4C 7C 8C 22A 27A 32A 22A 27A 32A 9C 12C 13C 37A 42A 47A 37A 42A 47A 14C 17C 18C 4B 9B 14B 19B 52 57 62 19 22 23 24B 29B 34B 39 67 72 77 24 27 29 4 49B 9B 14B 19B 30C 31C 34C 3C 7C 12C 17C 24B 29B 34B 35C 36C 39C 22C 27C 32C 37C 39B 44B 49B 40C 41C 44C 3D 9D 14D 19D 54B 59B 64B 45C 46C 49C 24D 29D 34D 39D 69B 74B 79B 50C 51C 54C 3C 7C 12C 17C 4D 5D 6D 9D 22C 27C 32C 10D 11D 14D 37C 42C 47C 15D 16D 9D 52C 57C 62C 20D 21D 24D 67C 72C 77 25D 26D 28D 3D 9D 14D 19D 31D 32D 33D 24D 29D 34D 36D 37D 38D 39D 42D 47D 41D 42D 43D 52D 57D 62D 46D 47D 48D 67D 72D 77D 51D 52D 53D 1E 2E 1F Table 75 Pin Assignment Power Supply for the phy CORE LPC2292 94 Carrier Board Expansion Board 116 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board Signal phyCORE Module Expansion Bus Patch Field NC 8C 50A 51A 53A 18A 19A 20A 4D 5D 7D 54A 55A 56A 21A 22A 23 58A 59A 60A 24A 25A 26A 61A 63A 64A 27A 45A 46A 65A 66A 68A ATA 48A 49A 69 70A 71A 50A 51A 52A 73A 74A 75 53A 54A 76A 78A 79A 17B 18B 19B 80A 20B 21B 22B 51B 53B 54B 23B 24B 25B 55B 56B 58B 26B 27B 45B 59B 60B 61B 46B 47B 48B
19. 63B 64B 65B 49B 50B 51B 66B 68B 69B 52B 53B 54B 70B 71B 73B 20C 21C 25C 74B 75B 76B 26C 47C 48C 78B 79B 80B 52C 53C 51C 53C 54C 17D 18D 22D 55C 56C 58C 23D 27D 44D 59C 60C 61C 45D 49D 50D 63C 64C 65C 54D 66C 68C 69C 18E 19E 20 70C 71C 73C 21E 228 23E 74C 75C 76C 24 25E 26E 78C 79C 80C 27E 45E 46E 4D 5D 7D 8D 4 48E 49E 51D 53D 54D 50E 51E 52E 55D 56D 58D 53E 54E 59D 60D 61D 17F 18F 19F 63D 64D 65D 20F 21F 22F 66D 68D 69D 23F 24F 25F 70D 71D 73D 26F 27F 44F 74D 75D 76D ASF 46F 47F 78D 79D 80D 48F 49F 50F 51F 52F 5 54 Table 76 Unused Pins on the phy CORE LPC2292 94 Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2006 L 658e 5 117 phyCORE LPC2292 94 16 3 12 Battery Connector BAT1 The mounting space see PCB stencil is provided for connection of battery that buffers the the phyCORE LPC2292 94 In the event of a VCC operating voltage failure the RTC is automatically supplied with power from the connected battery There is also the option of buffering the SRAMs with an external battery This optional setting is configured with Jumper J25 see section 3 11 In most cases an SRAM buffer is not recommended since the SRAM devices draw their operating current from VBAT during runtime of the module and therefore cause rapid battery discharge It is the u
20. Board These signals in turn are routed in a similar manner to the patch field on an optional expansion board that mounts to the Carrier Board at X2 Please note that depending on the design and size of the expansion board only a portion of the entire patch field is utilized under certain circumstances When this is the case certain signals described in the following section will not be available on the expansion board However the pin assignment scheme remains consistent A two dimensional numbering matrix similar to the one used for the pin layout of the phyCORE connector is provided to identify signals on the Expansion Bus connector X2 on the Carrier Board as well as the patch field 108 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board However the numbering scheme for Expansion Bus connector and patch field matrices differs from that of the phyCORE connector as shown in the following two figures ABCDEF o o 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 Figure 3l Pin Assignment Scheme ofthe Patch Field PHYTEC Messtechnik GmbH 2006 1 658 5 109 phyCORE LPC2292 94 The pin assignment on the phyCORE LPC2292 94 in conjunction with the Expansion Bus X2 on the Carrier Board and t
21. Carrier Board derived from external source CAN bus via on board voltage regulator JP29 closed Supply voltage for on board voltage regulator from pin 9 of DB 9 connector P2A JP39 see Table 60 CAN bus supply voltage reduction for CAN circuitry Table 64 Improper Jumper Settings for the Plug P2B CAN Transceiver on the Carrier Board PHYTEC Messtechnik GmbH 2006 L 658e 5 103 phyCORE LPC2292 94 3 The CAN transceiver is not populating the phyCORE LPC2292 94 and Jumpers J603 and J605 are closed CAN signals generated by the CAN transceiver U3 on the Carrier Board extend to connector P2B with galvanic separation This configuration requires connection of an external CAN supply voltage of 7 to 13 V The external power supply must be only connected to either P2A or P2B Jumper Setting Description JP33 243 Pin 2 of DB 9 plug P2B connected with CAN L2 from CAN transceiver U3 on the Carrier Board JP34 142 Pin 7 of DB 9 plug P2B connected with CAN H2 from CAN transceiver U3 on the Carrier Board JP14 244 Input at opto coupler U6 on the Carrier Board connected to H2 TD2 of the phy CORE LPC2292 94 JP15 244 Output at opto coupler U7 on the Carrier Board phyCORE LPC2292 94 connected to CAN_L2 RD2 of the JP13 1 2 Supply voltage for CAN transceiver and opto coupler on the Carrier Board derived from external source CAN bus via on board voltage regulator JP18 open CAN t
22. Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Block Diagram 2292 94 6 Top View of the phyCORE LPC2292 94 7 Bottom View of the _ 2292 8 Pinout of the phyCORE Connector Top View with Cross SELLON Insel 11 Numbering of the Jumper Pads n 17 Location of the Jumpers Top View 17 Location of the Jumpers Bottom View 18 phyCORE LPC2292 94 Memory Model 51 Ethernet Connection to LPC2292 94 Controller 59 JTAG Interface View EIER na 65 JTAG Interface Bottom 66 debugCORE LPC2292 94 Top 69 debugCORE LPC2292 94 Bottom 70 Physical 73 Modular Development and Expansion Board Concept with the phy CORE L PC2292 94 co tte a 78 Location of Connectors on the phyCORE Development Board HD200 reed 79 Numbering of Jumper Pads eee a 81 Location of the Jumpers View of the Component Side 81 Default Jumper Settings of the phyCORE Development Board HD200 with phyCORE LPC2292 94 82 Connecting the Supply Voltage at
23. Ground potential of the phyCORE LPC2292 94 circuitry needs to be connected to the applicable Ground pin on the COM port as well One of the microcontroller s on chip UARTs UARTO does not support handshake signal communication However depending on user needs handshake communication can be software emulated using port pins on the microcontroller The controllers second UART UARTI supports standard modem signals However these signals are not converted to RS 232 signal level on the phyCORE LPC2292 94 All modem signals are routed to the phyCORE connector at X700 In order to support handshake communication with RS 232 signal level an external RS 232 transceiver is required The applicable circuirty needs to be added by the user PHYTEC Messtechnik GmbH 2006 L 658e 5 55 phyCORE LPC2292 94 6 2 CAN Interface The phyCORE LPC2292 94 is designed to house two CAN transceivers at U605 and U606 either PCA82C251 or TLE6250V33 The CAN bus transceiver devices support signal conversion of the CAN transmit CANTx and receive CANRx lines The CAN transceiver supports up to 110 nodes on a single CAN bus Data transmission occurs with differential signals between CANH and CANL A Ground connection between nodes on a CAN bus is not required yet is recommended to better protect the network from electromagnetic interference EMI In order to ensure proper message transmission via the CAN bus a 120 Ohm termination resistor must be
24. I O Port 020 of the microcontroller see data sheet alternative external interrupt 3 input 5A CSO Chip Select 0 6A CS2 Select 2 8A O WR signal of the microcontroller 9A 10A 11A Al A2 A4 Address line of the microcontroller 13A 14A 15A A7 A9 A10 16A 18A A12 A15 24 25 17 18 26 28 20 23 19 20 21 D1 D2 D4 Data line of the microcontroller 23A 29A 30A D7 D9 D10 31A 38 DI2 D15 D17 39 40A 41A 119 D20 D22 43A 44 45A 025 D27 D28 46A D30 34A BLSO Low active Byte Lane Select signal Bank0 35A FSO VO Freely programmable PLD signal may be used as additional Chip Select signal 36A BLS2 Low active Byte Lane Select signal Bank 48A 49A P05 Port 0 of the microcontroller 50A P06 see corresponding Data Sheet 12 PHYTEC Messtechnik GmbH 2006 1 658 5 Pin Description UO PinRowX700B MCKO ka CLKOUT system clock output only available if 1B E Jumper J207 15 populated 2B P016 Port 016 of the microcontroller see data sheet P015 Port 015 of the microcontroller see data sheet BRUN NI 24B 29B 34B 39 44 49 58 CS 1 6B 0653 ChipSelect 3 y O BOE 0 Output enable signal of the microcontroller 8B 10B 11B Address line of the microcontroller 12B 13B 15B 16B 17B 23B 25B 26B 27B 18B
25. Module Expansion Bus Patch Field CAN HI 21D 21D 7D CAN 11 20D 20D TE CAN_H2 18C 18C 6E CAN_L2 18D 18D 6B P0 0 17D 17D 6C RxDO P0 1 16D 16D 6A TxD1 P0 8 23C 1 23C 8A RxD1 P0 9 21C2 21 7 RxDO ext 22D 22D TF TxDO ext 23D 23D SE RADI ext 21C 21C 7B TxD1 ext 23C 23C 8A SCL 31 31 10 SDA 32D 32D 11C SCLKO 28D 28D 10A MISOO 27D 27D 9B MOSIO 28C 28C 9F PCSO 26C 26C 9A LAN LED A 33C 33C LAN_LED_B 34C 34C 11F LAN_TPI 35C 35C 12A LAN_TPI 35D 35D 12E LAN_TPO 36C 36C 12B LAN_TPO 36D 36D 12D RTCK P126 37D 37D 12F TDO P127 38D 38D 12E TDI P128 38C 38C 13A TCK P129 40C 40C 13D TMS P130 40D 40D 13F TRST P131 39C 39C 13B WDI 8D 8D 3A TMS_PLD 46C 46C 15F TDI_PLD 45D 45D 15B TCK_PLD 46D 46D 16A TDO_PLD 47D 47D 16C Table 74 Pin Assignment Interface Signals for the phyCORE LPC2292 94 Carrier Board Expansion Board 1 Check configuration of Jumper J200 on the phyCORE LPC2292 94 refer to section 3 1 2 Check configuration of Jumper J202 on the phyCORE LPC2292 94 refer to section 3 1 PHYTEC Messtechnik GmbH 2006 1 658 5 115 phyCORE LPC2292 94 Signal phyCORE Module Expansion Bus Patch Field VCC 1C 2C 1D 2D 1C 2C 1D 2D 1A 1C VCC2 4C 5C 4C 5C 2A IB CLKIN 1A 1A 28A MCKO 1B 1B 28C VPD 6D 6D 2D VBAT 6C 6C 2B ADVREF 50D 50D 17E VAGND 42C 47C 42C 47C connected to GND 44D 49D 44D 49D GND 2A 7A 12A 17
26. be closed Table 6 J205 J206 Chip Select Configuration 3 5 J207 MCKO Signal This jumper can be used to connect the master clock output signal MCKO to Molex pin X700B1 for use in external application circuitry The following configurations are possible X700B 1 Flash Memory Size J207 signal not routed to Molex open connector pin signals routed to Molex pin closed Default setting Table 7 J207 MCKO Signal Configuration 1 possible if minimum configuration of the phyCORE LPC2292 is used CPLD not populated PHYTEC Messtechnik GmbH 2006 1 658 5 27 phyCORE LPC2292 94 3 6 J208 J209 Flash Size Configuration The phyCORE LPC2292 94 can be populated with three different Flash memory sizes per shape U300 thru U303 The size of the device must be configured to ensure linear addressing of the entire Flash bank Jumpers J208 and J209 are used to select the size of the memory device The on board CPLD reads the signal level on the applicable input pins and configures the individual Chip Select signals for the Flash devices accordingly Note Jumpers J208 and J209 are configured at time of delivery of the phyCORE LPC2292 94 according to the choosen memory configuration Therefor these jumpers must not be altered by the user The following configurations are possible Flash Memory Size J208 J209 1 MByte per shape open open 2 MBy
27. drain capability Default setting Table 33 J622 RESET Signal Source 3 25 J800 J801 ETM OCDS Connector Configuration Only with debugCORE LPC2292 94 Jumper J800 and J801 are used to route certain signals to the ETM OCDS connector at X800 This connector is only available on the debugCORE LPC2292 94 Configuration of these jumpers greatly depends on the characteristics of the emulator that connects to the debugCORE module refer to the emulator User s Manual for details The following configurations are possible ETM OCDS Connector Configuration J800 J801 Pin 1 on ETM OCDS connector RESET open 2 not connected depends on emulator Pin 1 on ETM OCDS connector carries closed module s RESET signal Vsupply and VTREF on the ETM OCDS 1 2 connector are supplied via VDD_V3V3 Vsupply and VTREF are connected to GND 2 3 Default setting Table 34 J800 7801 ETM OCDS Connector Configuration DCM 023 only PHYTEC Messtechnik GmbH 2006 1 658 5 45 phyCORE LPC2292 94 3 26 C210 CLKIN Configuration Capacitor C210 is used to input an external clock signal In default settings the on board quartz oscillator is used for generating the microcontroller s clock speed C210 not populated As an alternative an external clock signal can be connected to the controller pin XIN via phyCORE connector pin X700A1 This requires removal of the on board quartz oscillator and popul
28. e up to 6 freely programmable Chip Select signals from on board CPLD device requires changing the default CPLD code e one operating voltage for core amp peripherals 3 3 V typ lt 280 mA with maximum circuitry installed at 60 MHz CPU frequency e controller 1 8 V core voltage generated on board e additional 5V operating voltage for CAN transceivers typ 12 mA e support of LPC2292 2294 single chip mode e support of ETM debug interface only on debugCORE version 1 Please contact PHYTEC if you have questions about changing the CPLD code PHYTEC Messtechnik GmbH 2006 L 658e 5 5 phyCORE LPC2292 94 1 1 Block Diagram PHILIPS RAM FLASH Ethernet opt LPC2292 94 1MB 8MB 2MB 16MB j DO 31 D a t a Ae Ss t1 A0 A23 Adar RxDO TxDO TxDO os RxD1 TxD1 Transceiver PXD TxD1 JTAG JTAG bus CAN2 CAN CAN2H CAN2L Transceiver opt CAN Interface CAN CAN CANIH CANIL 12C i Transceiver digital O ports Reset sp SPI bus JTAG ETM Connector EEPROM Figure 1 Block Diagram phyCORE LPC2292 94 5 lt DO 6 PHYTEC Messtechnik GmbH 2006 1 658 5 Introduction 1 2 View of the phyCORE LPC2292 94 4 0300 uso1 U302 U303 0400 0401 0402 0403 s X701 Figure 2 View of the phyCORE LPC2292 94 PHYTEC Messtechnik GmbH 2006 L 6
29. for on board voltage regulator from pin 9 of DB 9 plug P2A JP39 see Table 60 CAN bus supply voltage reduction for CAN circuitry Table 59 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Carrier Board with Galvanic Separation 1 Please make sure the CAN transceiver on the phyCORE LPC2292 94 is not populated and Jumpers J602 and J604 are closed refer to section 3 14 for details 98 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board CAN Bus Voltage Supply Reduction via JP39 Depending on the voltage level that is supplied over the CAN bus at P2A P2B VCAN_INI JP39 must be configured in order to routed the applicable voltage to the CAN voltage regulator at U8 on the Carrier Board VCAN_IN JP39 7 18 1 2 18 V 23 V 2 3 23 V 28 V open Table 60 JP39 CAN Bus Voltage Supply Reduction Pin 9 Pin 3 VCAN Pin 7 _ 1 galvanically separated Pin 2 galvanically separated Pin 6 VCAN OV I CO o 5 4 3 2 1 Figure 26 Pin Assignment of the DB 9 Plug P2A CAN Transceiver on Carrier Board with Galvanic Separation PHYTEC Messtechnik GmbH 2006 1 658 5 99 phyCORE LPC2292 94 Caution When using the DB 9 plug P2A as CAN interface and the CAN transceiver on the Carrier Board with galvanic separation the following jumper settings are not functional and could da
30. from the populated Flash devices can be connected with port 017 on the LPC2292 94 controller using Jumper J300 Refer to the applicable Flash device Data Sheet User s Manual for more information about this feature The following configurations are possible Flash banks U300 U301 and U302 U303 P017 not available as standard I O at Molex pin X700D15 Flash Ready Busy Configuration J300 Ready Busy outputs of both Flash banks U300 U301 open and U302 U303 disconnected from P017 of the uC P017 available as standard I O at Molex pin X700D15 P017 used to supervise the Ready Busy outputs of both closed Default setting Table 10 7300 Flash Ready Busy Configuration 30 PHYTEC Messtechnik GmbH 2006 L 658e 5 Jumpers 3 9 J301 J302 Flash Write Protection Configuration Jumpers J301 and J302 are used to protect the contents of Flash banks U300 U301 and U302 U303 from unauthorized or unintentional erasure By closing jumpers J301 and J302 the hardware mechanism is activated for write protection of the individual Flash banks This feature is not supported by all the Flash devices that could be populated on the module For more detailed information about the write protection function refer to the Data Sheet User s Manual of the Flash device in question The following configurations are possible Flash Write Protection J301 J302 Flash bank U300 U301 without hardware open don t c
31. is available I O pin at X700A48 as standard I O pin at X700A48 22 PHYTEC Messtechnik GmbH 2006 L 658e_5 Jumpers Default Setting Alternative Setting J610 closed 0604 SCL signal open RTC SCL signal not connected connected to port P02 of the to the uC on the module uC PO2 is then no longer external connection required at available as standard I O pin pin X700C31 P02 is available at X700A47 as standard I O pin at X700A47 J611 closed EEPROM 0607 PCSO open EEPROM 80 signal not signal connected to port P10 connected to the uC on the of the uC P10 is then no module external connection longer available as standard required at pin X700C26 P10 VO pin at X700B50 is available as standard I O pin at X700C13 J612 closed EEPROM U607 MISOO open EEPROM MISOO signal not signal connected to port POS connected to the uC on the of the uC POS is then no module external connection longer available as standard required at pin X700D27 P05 pin at X700A49 is available as standard I O pin at X700A49 7613 closed EEPROM 0607 MOSIO open EEPROM MOSIO signal not signal connected to port P06 connected to the uC on the of the uC P06 is then no module external connection longer available as standard required at pin X700C28 P06 pin at X700A50 is available as standard I O pin at X700A50 J614 closed EEPROM 0607 SCLKO open EEPROM SCLKO signal not signal connecte
32. partitioned device WST2 5 gt 8 cycles BUSERR 0 gt not relevant WPERR 0 gt write protection error WP 0 gt bank not write protected BM 0 gt no burst ROM bank MW 2 gt 32 bit wide bus AT 0 gt always write O to this field Register Configuration Value 0x02000 0403 IDCY 3 gt 414 cycle WSTI 0 gt 3 cycles RBLE 1 gt byte partitioned device WST2 0 gt only for read access BUSERR 0 gt not relevant WPERR 0 gt write protection error WP 0 gt bank not write protected BM 0 gt burst rom bank MW 2 gt 32 bit wide bus AT 0 gt always write 0 to this field 52 PHYTEC Messtechnik GmbH 2006 1 658 5 Memory Models Example b Module Configuration e Flash access time 90 ns e SRAM access time 70 ns e Ethernet access time 25 ns BCFGO Register Configuration Value 0 02000 28A3 IDCY 3 gt 41 cycle WSTI 5 gt 8 cycles RBLE 0 gt Onon byte partitioned device WST2 5 gt 8 cycles BUSERR 0 gt relevant WPERR 0 gt write protection error WP 0 gt bank not write protected BM 0 gt burst ROM bank MW 2 gt 32 bit wide bus AT 0 gt always write 0 to this field Register Configuration Value 0x02000 2483 IDCY 3 gt A idle cycle WSTI 4 gt 7CCLK cycles RBLE 1 gt byte partitioned device WST2 4 gt 7 CCLK cycles BUSERR 0 gt not relevant WPERR 0
33. port P0 0 of the microcontroller 18D CAN_L2 VO Differential CANL line of the 2nd CAN transceiver alternativ 23 if J605 populated and U606 not populated 20D CAN_LI IO Differential CANL line of the first CAN transceiver alternativ P025 if J604 populated 17605 not populated 21D CAN HI VO Differential CANH line of the first CAN transceiver alternativ TD1 if J602 populated and U605 not populated 22D RxDO ext I Input of the first serial interface RS 232 level 23D TxDO ext Output of the first serial interface RS 232 level 25D P116 VO Port P116 of the microcontroller see data sheet 26D P117 VO Port P117 of the microcontroller see data sheet 27D MISOO Master In Slave Out for EEPROM 28D SCLKO VO Clock input SPI interface for EEPROM 30D P120 VO Port P120 of the microcontroller see data sheet alternative TRACESYNC of TRACE port 31D P121 VO Port P121 of the microcontroller see data sheet alternative PIPESTATO of TRACE port 32D SDA VO data line for 33D INT RTC interrupt output from RTC 35D LAN_TPI I Positive Rx input of the Ethernet interface 36D LAN_TPO Positive Tx output of the Ethernet interface 37D P126 VO Port P126 of the microcontroller see data sheet RTCK alternative RTCK of the JTAG interface 38D P127 VO Port P127 of the microcontroller see data sheet TDO alternative Data output JTAG interface 40D P130 VO Port P130 of the microcontroller see data sheet TMS
34. the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds PHYTEC Messtechnik GmbH 2006 1 658 5 75 phyCORE LPC2292 94 76 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 The phyCORE LPC2292 94 on the phyCORE Carrier Board HD200 PHYTEC Carrier Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start up and subsequent communication to and programming of applicable PHYTEC Single Board Computer SBC modules Carrier Boards are designed for evaluation testing and prototyping of PHYTEC Single Board Computers in labratory environments prior to their use in customer designed applications 16 1 Concept of the phyCORE Carrier Board HD200 The phyCORE Carrier Board HD200 provides a flexible development platform enabling quick and easy start up and subsequent programming of the phyCORE LPC2292 94 Single Board Computer module The Carrier Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation This modular development platform concept is depicted in Figure 15 and includes the following components e
35. the internal structure of the Flash device as during the Flash internal programming process the reading of data from Flash is not possible Hence for Flash programming program exe cution must be transferred out of Flash such as into von Neumann RAM This usually equals the interruption of a normal program execution cycle If the phyCORE LPC2292 94 is populated with multiple Flash devices on the available Flash banks it is possible to store application data in a Flash area which is physically seperated from the Flash area that contains program code As of the printing of this manual Flash devices generally have a life expectancy of at least 100 000 erase program cycles 58 PHYTEC Messtechnik GmbH 2006 1 658 5 LAN9ICIII Ethernet Controller 0501 9 LAN91C111 Ethernet Controller 0501 Connection of the phyCORE LPC2292 to the world wide web or a local network is possible with the on board SMSC LANOICIII 10 100 Mbps Ethernet controller populating the module at U501 This Ethernet controller features an integrated PHY layer Thus the external components required to connect the phyCORE LPC2292 to a LAN are limited to the transformer the RJ45 socket and a few discrete components The Ethernet chip is supported by a wide range of operating systems such as Linux etc phyCORE LPC229x External LPC229x DATA 4 c DO D31 J 4 gt ADDRESS 2 15 10 100Mbps
36. the write protection function 38 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers 3 16 1607 Watchdog Configuration The phyCORE LPC2292 94 supports a processor independent MAX6301 watchdog device which can be configured with the help of Jumper J607 This jumper configures various watchdog operating modes with preconfigured settings or using a controller port pin to change the mode The following configurations are possible Watchdog 7607 MAX6301 configured for extended mode see IC data open sheet for details WDS pin via pull up resistor disables watchdog due to floating WDI signal Additional logic ICs monitor the level of these BOOT closed DEBUG and RESET signals If one of the signals has a low level then the WDT is disabled allowing unlimited use of the phyCORE module Following RESET without active low signals BOOT and DEBUG the WDT is always enabled if Jumper J607 is closed Default setting Table 25 7607 Watchdog Configuration PHYTEC Messtechnik GmbH 2006 1 658 5 39 phyCORE LPC2292 94 3 17 J608 J609 J610 Interface Jumpers J608 J609 and J610 are provided to connect the controller s interface to the on board RTC and the phyCORE connector The signals SDA and SCL are available at pins X700C31 and X700D32 if Jumpers J609 and J610 are closed Jumper J608 connects the RTC interrupt output to port 015 If all 3 jumpers remain open the corres
37. voltage regulator from pin 9 of DB 9 connector P2A JP39 see Table 60 CAN bus supply voltage reduction for CAN circuitry Table 58 Improper Jumper Settings for the CAN Plug P2A CAN Transceiver on the Carrier Board PHYTEC Messtechnik GmbH 2006 L 658e 5 97 phyCORE LPC2292 94 3 The CAN transceiver is not populated on the phyCORE LPC2292 94 and Jumpers J602 and J604 are closed CAN signals generated by the CAN transceiver U2 on the Carrier Board extend to connector P2A with galvanic separation This configuration requires connection of an external CAN supply voltage of 7 to 13 V The external power supply must be only connected to either P2A or P2B Jumper Setting Description JP31 1 2 Pin 2 of DB 9 plug P2A connected with CAN L1 from CAN transceiver U2 on the Carrier Board JP32 1 2 Pin 7 of DB 9 plug P2A connected with _ 1 from CAN transceiver U2 on the Carrier Board 2 4 Input at opto coupler U4 the Carrier Board connected to CAN HI TDI of the phyCORE LPC2292 94 JP12 2 4 Output at opto coupler U5 the Carrier Board connected to CAN_L1 RD1 of the phyCORE LPC2292 94 JP13 1 2 Supply voltage for CAN transceiver and opto coupler on the Carrier Board derived from external source CAN bus via on board voltage regulator JP18 open CAN transceiver and opto coupler on the Carrier Board disconnected from local GND potential JP29 closed Supply voltage
38. 006 1 658 5 101 phyCORE LPC2292 94 2 No CAN transceiver is populating the phyCORE LPC2292 94 and Jumpers J603 and J605 are closed CAN signals generated by the CAN transceiver U3 on the Carrier Board extending to connector P2B without galvanic seperation Jumper Setting Description JP33 2 3 Pin 2 of the DB 9 plug P2B is connected to CAN_L2 of CAN transceiver U3 of the Carrier Board HD200 JP34 1 2 Pin7 ofthe DB 9 plug P2B is connected to CAN_H2 of CAN transceiver U3 of the Carrier Board HD200 JP14 244 Input at opto coupler U6 on the Carrier Board connected to H2 TD2 of the phyCORE LPC2292 94 JP15 244 Output at opto coupler U7 on the Carrier Board connected to CAN L2 RD2 of the phyCORE LPC2292 94 JP13 closed transceiver and opto coupler on the Carrier Board connected with 5 V supply voltage JP18 closed GND potential at CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP29 open No power supply via CAN bus JP39 open No power supply via CAN bus Table 63 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board HD200 5 9 4 8 Pin 3 GND Carrier Board Ground 3 7 Pin 7 2 not galvanically separated 2 Pin 2 CAN_L2 not galvanically separated 6 Pin 6 GND Carrier Board Ground 1 Figure 28 Pin Assignment of DB 9 Plug P2B CAN Transceiver on Carrier Board 1 Please make sure the CAN transceiver on the ph
39. 11 TDO JTAG signal test data out 12 V TREF Can be connected to VCC 3 3 V or GND via Jumper J801 default VCC I3 RTCK JTAG signal returned test clock output 14 Vsupply Can be connected to VCC 3 3 V or GND via Jumper J801 default VCC 15 TCK JTAG signal test clock 16 18 20 22 GND Ground 17 TMS JTAG signal test mode select 19 TDI JTAG signal test data in 21 TRST JTAG signal test reset 23 25 27 29 N C Not connected 31 33 35 37 24 TRACEPKT3 Trace packet signal 3 26 2 Trace packet signal 2 28 TRACEPKTI Trace packet signal 1 30 TRACEPKTO Trace packet signal 0 32 TRACESYNC Trace synchronization signal 34 PIPESTAT2 Pipe Line status signal 2 36 PIPESTATI Pipe Line status signal 1 38 PIPESTATO Pipe Line status signal 0 Table 43 ETM OCDS Connector at X800 PHYTEC Messtechnik GmbH 2006 1 658 5 71 phyCORE LPC2292 94 The pinout of the 24 pin MII 0 64 mm pitch connector at X500 is described below Pin Number Signal Description 1 20 21 VCC 3 3 V supply voltage 2 LAN_MDI MII management data input 3 LAN_MDO MII management data output 4 LAN_MCLK MII management clock 5 LAN_RXD3 Received data nibble from MII PHY input 6 LAN_RXD2 Received data nibble from MII PHY input 7 LAN RXDI Received data nibble from MII PHY input 8 LAN RXDO Received data nibble from MII PHY input 9 LAN RX DV Envelope of da
40. 2 VCCRAM derived from VBAT 243 Default setting Table 13 J402 SRAM Supply Voltage Configuration 32 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers 3 12 J500 through J509 Ethernet Controller SMSC LAN91C111Configuration As an option a LAN9IC111 Ethernet controller from SMSC can populate the phyCORE LPC2292 94 at 0501 If the Ethernet controller populates the phyCORE module one of two possible Chip Select signals for controlling access to the LAN91C111 can be selected using Jumper J502 Jumper J501 selects which of the microcontroller interrupts connects with the interrupt output LAN_IRQ of the Ethernet controller The LAN_IRQ signal can be connected to a 10k pull up resistor with the help of Jumper J504 Connection of the LAN91C111 controller s Ready LAN_RDY signal to port pin 018 is established by closing Jumper J503 The following configurations are possible CS Signal Configuration J502 CS2 from the uC selects Ethernet controller 1 2 CS3 from the uC selects Ethernet controller 2 3 Default setting Table 14 J503 Ethernet Chip Select Signal Configuration Interrupt of the Ethernet Controller J501 connects to EINTO P016 of the microcontroller 1 2 connects to EINT1 P014 of the microcontroller 2 3 not connected to the microcontroller open Default setting Table 15 J501 Ethernet Interrupt Signal Configuration PHYTEC Mes
41. 200 is the fact that resistor R203 on the phyCORE LPC2292 94 has been removed In combination with Jumper JP41 left open a high level will be detected by the CPU at data line D26 which then causes instructions to be fetched from the controller internal Flash Boot from on board Flash 32 bit data bus width connected to Chip Select CSO If R203 is not installed on the phyCORE LPC2292 94 closing Jumper JP41 on the Carrier Board allows code execution from the on board Flash connected to the LPC2292 94 via CSO This will result in a low signal level at data line D26 during a reset cycle If the controller reads a low level at D26 it will execute code from the external Flash device connected to CSO Jumper Setting Description JP41 open Code execution from internal Flash Only applicable if R203 on the phyCORE module is not installed closed Code execution from external Flash connected to 50 Only applicable if R203 on the phyCORE module is not installed Table 50 JP41 phyCROE LPC2292 94 Boot Memory Configuration le Note R203 is populated on the standard version of the phyCORE LPC2294 SBC module 88 PHYTEC Me technik GmbH 2006 1 658 5 phyCORE LPC2292 94 on the phyCORE Carrier Board 16 3 4 First Serial Interface at Socket P1A Socket is the lower socket of the double DB 9 connector at Pl PIA is connected via jumpers to the first serial interface of the phyCORE LPC2
42. 292 94 Jumper Setting Description JP20 closed Pin 2 of DB 9 socket connected with RS 232 signal TxDO of the phyCORE LPC2292 94 JP21 open Pin 9 of DB 9 socket P1A not connected JP22 open Pin 7 of DB 9 socket P1A not connected JP23 open Pin 4 of DB 9 socket not connected JP24 open Pin 6 of DB 9 socket P1A not connected JP25 open Pin 8 of DB 9 socket P1A not connected JP26 open Pin 1 of DB 9 socket P1A not connected JP27 closed Pin 3 of DB 9 socket P1A connected with RS 232 signal 0 from the phyCORE LPC2292 94 Table 51 Jumper Configuration for the First RS 232 Interface 1 6 2 2 TxDO 2 1 Pin 3 RxDO 8 4 5 9 5 GND Figure 21 Pin Assignment of the DB 9 Socket PIA as First RS 232 Front View PHYTEC Messtechnik GmbH 2006 1 658 5 89 phyCORE LPC2292 94 Caution When using the DB 9 socket PIA as RS 232 interface on the phyCORE LPC2292 94 the following jumper settings are not functional and could damage the module Jumper Setting Description JP20 open Pin 2 of DB 9 socket P1A not connected no connection to TxDO signal from phyCORE LPC2292 94 JP21 closed Pin 9 of DB 9 socket connected with port P1 20 from phyCORE LPC2292 94 JP22 1 2 Pin 7 of DB 9 socket connected with port P1 17 from phyCORE LPC2292 94 JP23 52 Pin 4 of DB 9 socket P1A connected with MISOO signal from phyCORE LPC2292
43. 2A Plug P2A is the lower plug of the double DB 9 connector at P2 P2A is connected to the first CAN interface CANI of the phyCORE LPC2292 94 via jumpers Depending on the configuration of the CAN transceivers and their power supply the following three configurations are possible 1 CAN transceiver populating the phyCORE LPC2292 94 is populated and the CAN signals from the module extend directly to plug P2A Jumper Setting Description JP31 2 3 Pin 2 of the DB 9 plug P2A is connected to CAN L1 from on board transceiver the phyCORE module JP32 243 Pin 7 of the DB 9 plug P2A is connected to CAN from on board transceiver on the phyCORE module Input at opto coupler U4 on the phyCORE Carrier Board HD200 open JP12 open Output at opto coupler U5 on the phyCORE Carrier Board HD200 open JP13 open No supply voltage to CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP18 open No GND potential at CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP29 open No power supply via CAN bus JP39 open No power supply via CAN bus Table 56 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the phyCORE LPC2292 94 Pin 3 GND Carrier Board Ground Pin 7 CAN HI not galvanically separated Pin 2 CAN 11 not galvanically separated Pin 6 GND Carrier Board Ground N o A WN AN oy o Figure 24 Pin Assignment of the DB 9 Plug
44. 58e 5 7 phyCORE LPC2292 94 Figure 3 Bottom View of the phyCORE LPC2292 8 PHYTEC Messtechnik GmbH 2006 L 658e 5 Pin Description 2 Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals As Figure 4 indicates all controller signals extend to surface mount technology SMT connectors 0 635 mm lining two sides of the module referred to as phyCORE connector This allows the phyCORE LPC2292 94 to be plugged into any target application like a big chip A new numbering scheme for the pins on the phyCORE connector has been introduced with the phyCORE specifications This enables quick and easy identification of desired pins and minimizes errors when matching pins on the phyCORE module with the phyCORE connector on the appropriate PHYTEC Carrier Board or in user target circuitry The numbering scheme for the phyCORE connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number Pin 1A for example is always located in the upper left hand corner of the matr
45. 605 connected with uC port P025 only if CAN transceiver and available as CAN TTL U605 populates the signal an X700D20 for module connection to external CAN transceiver only in connection with unpopulated 0605 J605 open CAN_L2 signal generated closed CAN L2 signal directly by CAN transceiver U606 connected with uC port P023 only if CAN transceiver and available as CAN TTL U606 populates the signal an X700D18 for module connection to external CAN transceiver only in connection with unpopulated U606 J606 open SPI EEPROM not write closed SPI EEPROM write protected protected WP input tied to GND J607 open MAX6301 configured for closed MAX6301 is disabled if the extended mode see IC data or DEBUG signals are sheet for details WDS pin active Otherwise the WDT is via pull up resistor to VCC active following a RESET if WDI is floating the Please refer to the MAX6301 processor independend datasheet for further WDT is disabled information J608 closed output from open RTC interrupt not connected to RTC U604 connected to the uC P015 is available as port P015 of the uC 015 standard I O pin at X700B3 is then no longer available as standard I O pin at X700B3 J609 closed RTC 0604 SDA signal open RTC SDA signal not connected connected to port of to the uC on the module the uC is then no external connection required at longer available as standard pin X700D32
46. 94 JP24 152 Pin 6 of DB 9 socket connected with SCLKO signal from phyCORE LPC2292 94 PES Pin 6 of DB 9 socket connected with VOUT from Carrier Board HD200 JP25 Closed Pin 8 of DB 9 socket connected with port P1 16 from phyCORE LPC2292 94 JP26 closed Pin of DB 9 socket connected with port P1 21 from phyCORE LPC2292 94 JP27 open Pin 3 of DB 9 socket not connected no connection to RxDO signal from phyCORE LPC2292 94 Table 52 Improper Jumper Settings for DB 9 Socket as First RS 232 If an RS 232 cable is connected to PIA the voltage level on the RS 232 lines could destroy the phyCORE LPC2292 94 90 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 3 5 Power Supply to External Devices via Socket P1A The phyCORE Carrier Board HD200 can be populated by additional components that provide a supply voltage of 5 V at pin6 of DB 9 socket PIA This allows for easy and secure supply of external devices connected to This power supply option especially supports connectivity to analog and digital modems Such modem devices enable global communication of the phyCORE LPC2292 94 over the Internet or a direct dial connection The following figure shows the location of these components on the Carrier Board PHYTEC Messtechnik GmbH PCB 1179 6
47. 94 ISP Mode In order to start the ISP command handler on the LPC2292 94 port P0 14 of the microcontroller must be connected to a low signal level at the time the reset signal changes from its active to the inactive state This is achieved by applying a high level signal at pin X1C9 BOOT of the phyCORE LPC2292 94 A transistor circuitry connects P0 14 to GND as long as the BOOT pin is high An on board pull up resistor R213 ensures a high level at PO 14 if the BOOT signal is not active This BOOT signal can be generated by a push button temporary signal or jumper setting permanent signal on the phyCORE Developent Board HD200 refer to section 16 3 2 for more details 48 PHYTEC Messtechnik GmbH 2006 L 658e 5 Memory Models 5 Memory Models The Philips LPC2292 94 controller provides up to four Chip Select signals for easy selection of external peripherals or memory banks Depending on the number of memory devices installed on the phyCORE LPC2292 94 as well as the availability of the optional Ethernet controller up to three Chip Select signals are used internally 50 selects the two Flash banks installed on U300 U303 with either 1 MByte 2 MByte or 4 MByte devices in CBGA 48 packaging per shape The total amount of Flash memory is 2 MByte in the minimum configuration of the module and 16 if the maximum configuration is used The external data memory consists of the two RAM banks at U400 U403 These sp
48. ANITx CAN2Rx and 2 signals is also available at the phyCORE connector X700 This requires both removal of the on board CAN transceiver devices and closing Jumpers J602 J603 J604 and J605 PHYTEC Messtechnik GmbH 2006 L 658e 5 37 phyCORE LPC2292 94 The following configurations are possible First CAN Interface J602 J604 at X700D21 open open CAN 11 at X700D20 CANI Rxat X700D21 closed closed CANI Tx at X700D20 Second CAN Interface J603 J604 CAN H2 at X700C18 open open CAN L2 at X700D18 CANO2 Rx at X700C18 closed closed CAN2 Tx at X700D18 Default setting Table 23 J602 7603 J604 and 7605 CAN Interface Configuration 3 15 J606 Write Protection of SPI EEPROM Various types of SPI EEPROM devices can populate space U607 Some of these devices provide a write protection function Closing Jumper J606 connects pin 3 of the serial EEPROM with GND and thus activates write protection The following configurations are possible Write Protection EEPROM J606 Write protection of EEPROM deactivated open Write protection of EEPROM activated closed Default setting Table 24 J606 EEPROM Write Protection 1 Should only be used if CAN transceivers U605 and U606 are populated Note Should only be used if CAN transceivers U605 and U606 are NOT populated Refer to the corresponding EEPROM Data Sheet for more information on
49. B6 open CS2 and CS3 freely available at Molex pins X700A6 and 6 J503 open P018 from the uC freely closed P018 used to supervise the available at X700C16 Ready signal on the on SMSC LAN91C111 P018 is then no longer available at Molex pin X700C16 20 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers Default Setting Alternative Setting J504 open LAN_IRQ signal not closed LAN_IRQ signal is connected to connected to an additional an additional 10k pull up resistor 10k pull up resistor to to VDD_V3V3 VDD_V3V3 J505 open IOS2 signal on SMSC LAN closed 1052 signal on SMSC LAN 91C111 connected with 91C111 connected to GND See internal pull up to LAN91CI11 data sheet for more VDD_V3V3 configuration details via predefined EEPROM contents J506 open IOS1 signal on SMSC LAN closed 10501 signal on SMSC LAN 91C111 connected with 91C111 connected to GND See internal pull up to LAN9ICI11 data sheet for more VDD_V3V3 configuration details via predefined EEPROM contents J507 open IOSO signal on SMSC LAN closed 1050 signal on SMSC LAN 91C111 connected with 91C111 connected to GND See internal pull up to LAN91CI11 data sheet for more VDD V3V3 configuration details via predefined EEPROM contents J508 open ENEEP signal on SMSC closed signal on SMSC LAN LAN 91C111 connected 91C111 connected to GND See with internal pull up to LAN9ICI11 data sheet for more VDD_V3V3 configu
50. CB revision 1179 6 the phyCORE Carrier Board HD200 features 4 solder jumper J1 J4 that allow signal routing for GPIO37 GPIO40 to different connectors the Ethernet interface X7 or the Expansion Bus X2 The standard configuration of the phyCORE LPC2292 94 provides Ethernet signals on these pins As a result the default configuration of Jumpers J1 J4 will route the signals to Ethernet interface connector X7 Changing this jumper default configuration allows use of the signals on the Expansion Bus in combination with a phyCORE module lacking the Ethernet controller Jumper Setting Description J1 J4 1 2 Signals GPIO37 GPIO40 configured as Ethernet signals routed to X7 J1 J4 2 3 Signals GPIO37 GPIO40 routed to Expansion Bus Default setting Table 79 Solder Jumpers 74 Configuration Ethernet Interface BAM AE 5 J4 J2 PHYTEC Messtechnik GmbH PCB 1179 6 Figure 35 Location of Solder Jumpers J1 J4 and Ethernet Interface Connector X7 122 PHYTEC Me technik GmbH 2006 L 658e_5 Revision History 18 Revision History me Version numbers Changes in this manual 24 Mar 2004 Manual L 658e 0 PCM DCM 023 PCB 1228 0 PCM 997 V2 PCB 1179 5 17 Jun 2004 Manual L 658e 1 PCM DCM 023 1231 0 1228 0 PCM 997 V2 1179 5 13 Sep 2004 Manual L 658e 2 PCM
51. CONTROL CS2 ETHERNET U500 SPI EEPROM Figure 9 Ethernet Connection to LPC2292 94 Controller The Ethernet controller is connected to the data bus with a 32 bit width and can be configured via Jumpers J501 J502 and J503 Jumper J501 is used to connect the interrupt signal of the LAN91C111 with a corresponding input on the LPC2292 94 processor The interrupt is being used as active high edge triggered The CS signal for the LAN91C111 Ethernet controller at U501 can be connected to the LPC2292 processor s CS2 or CS3 signal using Jumper J502 The Ethernet controller s offset of 0x300 has to be noted when accessing the chip PHYTEC Messtechnik GmbH 2006 L 658e 5 59 phyCORE LPC2292 94 The Ethernet controller provides a READY output that can be connected to the 018 input of the controller using Jumper J503 It is also possible to combine various signal sources externally if multiple components need to use the processors P018 input for READY indication Refer to section 3 12 for more details on applicable jumper settings and configuration options The physical memory area for the Ethernet chip is defined in the following table An offset of 0x300 has to be added to the address of CS2 if Jumper J502 is closed at position 1 2 for accessing the 91 11 Ethernet Start Address CS2 OFFSET 0x8200 0000 0x0000 0300 0x8200 0300 Table 40 Memory Area Ethernet Controller
52. D1 with RS 232 levels 1 2 1 2 P08 and 09 I O pin or TxD1 and 2 3 2 3 RxD1 as interface signals with TTL level Default setting Table 3 J200 J202 Second Serial Interface Configuration 3 2 J201 J203 First Serial Interface Jumper J201 and J203 connect the signals of the first synchronous asynchronous serial interface to the on board RS 232 transceiver The interface signals are then available with RS 232 level at the phyCORE connector pins X700D22 0 and X700D23 If the jumpers are opened the applicable controller pins POO and POI can be used with their alternative functions or the serial interface signals are available with their TTL level at phyCORE connector pins X700D17 and X700D16 If the jumpers are closed we recommend not to use the interface signals with their TTL level as this will cause damage to the on board components The following configurations are possible Signal Configuration J201 J203 TxDO RxD0 with RS 232 level at 1 2 1 2 X700D22 and X700D23 RxDO with TTL level or as 2 3 2 3 pin at X700D22 and X700D23 POO and 01 as I O pin or TxDO and open open RxD0 interface signals with TTL level at X700D16 and X700D17 Default setting Table 4 J201 J203 First Serial Interface Configuration PHYTEC Messtechnik GmbH 2006 1 658 5 25 phyCORE LPC2292 94 3 3 J204 A D Converter The integrated analog digital
53. DCM 023 1231 0 1228 0 PCM 997 V2 1179 5 11 Oct 2005 Manual L 658e 3 PCM DCM 023 1231 0 1228 0 PCM 997 V2 PCB 1179 5 14 Dec 2005 Manual L 658e 4 PCM DCM 023 1231 0 1228 0 PCM 997 V2 1179 5 25 Jul 2006 Manual L 658e 5 PCM 023 1231 1 PCM 997 V3 1179 6 First draft Preliminary documentation Describes the debugCORE LPC2292 94 only Description and module images changed to match the phyCORE LPC2292 94 Pinout changes PLD JTAG signals routed to Molex connector see section 2 Pin Description Jumpers J619 J620 and J621 added J607 changed to 2 pad jumper Paragraphs added to section 5 Memory Models Section 4 2 Starting the LPC2292 94 ISP Mode added In section 13 debugCORE LPC2292 94 3 25 ETM OCDS Connector at X800 and 3 12 LAN MII Connector at X500 pinout added Section 6 3 2 Starting the ISP Command Handler added Section 19 Component Placement Diagram added Table 73 Signal P1 27 TDO Patch Field corrected Table 71 Signal BLS1 added New section for RTC added see Real Time Clock RTC 8564 U604 New images for PCB revision 1231 1 and PCM 997 V3 PCB revision 1179 6 New solder jumpers for Ethernet interface configuration in section 17 added New PCM 997 V3 PCB revision 1179 6 supports 100 Mbit s Ethernet transmission PHYTEC Messtechnik GmbH 2006 1 658 5 123 phyCORE LPC2292 94
54. Device Type Size Component Manufacturer EEPROM 1 kByte 1024 8 AT25080 Atmel EEPROM 2 kByte 2048 8 AT25160 Atmel EEPROM 4 kByte 4096 8 AT25320 Atmel EEPROM 8 kByte 8192 8 AT25640 Atmel Table 39 Memory Device Options for U607 Various available EEPROM types provide a write protection function Jumper J606 is used to activate this function If this jumper is closed then pin 3 of the serial EEPROM is connected to GND Refer to section 3 15 for details on jumper settings for J606 l Refer to the corresponding EEPROM Data Sheet for more information on the write protection function PHYTEC Messtechnik GmbH 2006 1 658 5 57 phyCORE LPC2292 94 8 On Board Flash Memory U300 U303 Use of Flash as non volatile memory on the phyCORE LPC2292 94 provides an easily reprogrammable means of code storage The following Flash devices can be used on the phyCORE LPC2292 94 29LV800B with 1 16 kByte 2 8 kByte 1 32 kByte 15 64 kByte 29LV160B with 1 16 kByte 2 8 kByte 1 32 kByte 31 64 kByte 29LV320B with 8 8 kByte 63 64 kByte 29DL800B with 4 8 kByte 2 16Kbyte 2 32 kByte 14 64kByte and all other pin and function compatible Flash devices available on the market These Flash devices are programmable with 3 3 V No dedicated programming voltage is required Use of a Flash device as the only code memory results in no or only a limited usability of the Flash memory as non volatile memory for data This is due to
55. H 2006 1 658 5 43 phyCORE LPC2292 94 3 23 J621 WDI Signal Source Jumper J621 configures the source of the signal connected to the WDI input on the external Watchdog timer WDT Jumper J621 connects microcontroller port P021 to the WDI input signal which allows software controlled WDT activation The following configurations are possible input signal Additional peripheral components can be controlled by the WDI P021 signal at Molex pin X700D8 WDI Signal Source J621 WDI signal on WDT MAX6301 is not open controlled by the microcontroller if the WDT is used then the WDI signal needs to be controlled via Molex pin X700D8 Microcontroller port P021 controls the WDI closed Default setting Table 32 J621 WDI Signal Source 3 24 J622 RESET Signal Source Jumper J622 configures the source of the high active RESET signal Closing Jumper J622 requires Q601 to not be populated connects the output of U601 TLC7701 with the RESET signal which allows push pull generation of the high active RESET signal 44 PHYTEC Messtechnik GmbH 2006 L 658e 5 Jumpers The following configurations are possible RESET Signal Source J622 FET transistor Q601 has to be populated and open signal generation of the high active RESET signal is done through Q601 with open drain capability Q601 is not populated and signal generation for closed the high active RESET signal is done by U601 without open
56. MAC address is pre programmed into the EEPROM U500 at time of delivery refer to section 9 1 9 3 10 100Base T Interface The phyCORE LPC2292 94 has been designed exclusively for operation in 10 100Base T networks The 10 100Base T interface with its signals LAN LEDA and LAN LEDB extends to phyCORE connector X1 The MII interface of the LAN91C111 is not available on the phyCORE connector However these signals are routed to an optional connector X500 that populates the debugCORE LPC2292 variant Additional external circuitry is required to connect the module to an existing 10 100Base T network It should be noted that the 3 3 V version of the LANOICIII controller is used on the phyCORE LPC2292 94 Please refer to the SMSC Ethernet controller datasheet for details on the external circuitry design This circuitry is also available from PHYTEC on an Ethernet adapter module order code EAD 003 refer to section 17 PHYTEC Messtechnik GmbH 2006 1 658 5 61 phyCORE LPC2292 94 10 Real Time Clock RTC 8564 0604 For real time or time driven applications the phyCORE LPC2292 94 is equipped with a RTC 8564 Real Time Clock at U604 This RTC device provides the following features Serial input output bus address OxA2 e Power consumption Bus active 400 kHz 1 mA Bus inactive CLKOUT inactive lt 1 Clock function with four year calendar Century bit for year 2000 compliance Universal timer with alarm and over
57. P2 P2B is connected to the second CAN interface CAN2 of the phyCORE LPC2292 94 via jumpers Depending on the configuration of the CAN transceivers and their power supply the following three configurations are possible 1 CAN transceiver populating the phyCORE LPC2292 94 and the CAN signals from the module extend directly to plug P2B Jumper Setting Description JP33 2 4 Pin 2 of the DB 9 plug P2B is connected to CAN_L2 from on board transceiver on the phyCORE module JP34 2 3 Pin 7 of the DB 9 plug P2B is connected to CAN_H2 from on board transceiver on the phyCORE module JP14 open Input at opto coupler U6 on the phyCORE Carrier Board HD200 open JP15 open Output at opto coupler 07 on the phyCORE Carrier Board HD200 open JP13 open CAN transceiver and opto coupler on the Carrier Board disconnected from supply voltage JP18 open No GND potential at CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP29 open No power supply via CAN bus JP39 open No power supply via CAN bus Table 62 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the phyCORE LPC2292 94 5 9 8 Pin 3 GND Carrier Board Ground 3 7 Pin 7 CAN_H2 not galvanically separated 2 Pin 2 CAN_L2 not galvanically separated 6 Pin 6 GND Carrier Board Ground Figure 27 Pin Assignment of the DB 9 Plug P2B CAN Transceiver on phyCORE LPC2292 94 Front View PHYTEC Messtechnik GmbH 2
58. P2A CAN Transceiver on phyCORE LPC2292 94 Front View PHYTEC Messtechnik GmbH 2006 L 658e 5 95 phyCORE LPC2292 94 2 No CAN transceiver is populating the phyCORE LPC2292 94 and Jumpers J602 and J604 are closed CAN signals generated by the CAN transceiver U2 on the Carrier Board extending to connector P2A without galvanic seperation Jumper Setting Description JP31 1 2 Pin 2 of the DB 9 plug P2A is connected to CAN L1 from transceiver on the Carrier Board HD200 JP32 142 Pin 7 of the DB 9 plug P2A is connected to from transceiver on the Carrier Board HD200 2 4 Input at opto coupler U4 on the phyCORE Carrier Board HD200 connected with CAN HI TDI of the phyCORE LPC2292 94 JP12 244 Output at opto coupler U5 on the phyCORE Carrier Board HD200 connected with CAN LI RDI of the phyCORE LPC2292 94 JP13 2 3 Supply voltage to CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP18 1 2 GND potential at CAN transceiver and opto coupler on the phyCORE Carrier Board HD200 JP29 open No power supply via CAN bus JP39 open No power supply via CAN bus Table 57 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Carrier Board HD200 5 9 4 3 8 Pin 3 GND Carrier Board Ground 7 Pin 7 CAN not galvanically separated 2 Pin 2 CAN 11 not galvanically separated 1 6 6 GND Carrier Board Ground Figure 25 Pin Assignment of the DB 9 P
59. The actual Carrier Board 1 which offers all essential components and connectors for start up including a power socket enabling connection to an external power adapter 2 and serial interfaces 3 of the SBC module at DB 9 connectors depending on the module up to two RS 232 interfaces and up to two RS 485 or CAN interfaces e All of the signals from the SBC module mounted on the Carrier Board extend to two mating receptacle connectors A strict 1 1 signal assignment is consequently maintained from the phyCORE connectors on the module to these expansion con nectors Accordingly the pin assignment of the expansion bus 4 depends entirely on the pinout of the SBC module mounted on the Carrier Board PHYTEC Messtechnik GmbH 2006 L 658e_5 771 phyCORE LPC2292 94 e As the physical layout of the expansion bus is standardized across all applicable PHYTEC Carrier Boards we are able to offer various expansion boards 5 that attach to the Carrier Board at the expansion bus connectors These modular expansion boards offer supplemental I O functions 6 as well as peripheral support devices for specific functions offered by the controller populating the SBC module 9 mounted on the Carrier Board e All controller and on board signals provided by the SBC module mounted on the Carrier Board are broken out 1 1 to the expansion board by means of its patch field 7 The required connections between SBC module Carrier Board and the expans
60. Transceiver on the 1 2292 94 101 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board 200 102 Improper Jumper Settings for the CAN Plug P2B CAN Transceiver on the Carrier 103 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board with Galvanic SeparatlOD epe e ears inv tee etes 104 Improper Jumper Settings for the CAN Plug P2B CAN Transceiver on Carrier Board with Galvanic Separation 106 JP17 Configuration of the Programmable LED D3 107 JP40 Configuration of User Button S3 107 Pin Assignment Data Bus for the phyCORE LPC2292 94 Carrier Board Expansion Board 110 Pin Assignment Address Bus for the phyCORE LPC2292 94 Carrier Board Expansion Board dae Ga PAG 111 Pin Assignment Address Control Bust for the phyCORE LPC2292 94 Carrier Board Expansion BOAR sesa sesi BER 112 Pin Assignment Port PO for the phyCORE LPC2292 94 Carrier Board Expansion Board 113 PHYTEC Messtechnik GmbH 2006 L 658e 5 Contents Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Pin Assignment Port P1 for the phyCORE LPC2292 94 Carrier Board Expansi
61. View PHYTEC Messtechnik GmbH 2006 L 658e 5 69 phyCORE LPC2292 94 Figure 13 debugCORE LPC2292 94 Bottom View A DIP switch has been added to the configuration resistors already present on the phyCORE module to enable easier configuration of the controller s debug interface When using the DIP switch for configuration resistors R205 and R206 must be removed DIP switch S800 on the debugCORE LPC2292 94 has the following configuration options DIP Switch Open OFF Closed ON 1 Normal operation of the Boot mode always enabled LPC2292 94 2 Port pins P116 P125 Port pins P116 P125 function as standard I O function as Trace port port 3 Port pins P126 P131 Port pins P126 P131 function as standard function as debug interface port 4 reserved reseverd Table 42 debugCORE LPC2292 94 DIP Switch 5800 70 PHYTEC Me technik GmbH 2006 1 658 5 debug 2292 94 The pinout of the 38 pin 0 64 mm pitch Embedded Trace Macrocell ETM and OCDS MICTOR connector at X800 is described below Pin Number Signal Description 1 RESET Low active reset signal Can connected by closing Jumper J800 default open 2 3 4 N C Not connected 5 GND Ground 6 TRACECLK Clock signal for trace port 7 8 N C Not connected 9 RESET Low active reset signal 10 EXTINO External trigger input
62. aces can house memory devices of 512 kByte 1 MByte or 2 MByte in an TBGA 48 package CS1 selects the RAM banks 0400 U403 Access to the optional Ethernet controller at U501 can be established via CS2 or CS3 configurable with Jumper J502 The default configuration allows access via CS2 J502 closed at 1 2 PHYTEC Messtechnik GmbH 2006 1 658 5 49 phyCORE LPC2292 94 Configuration of the LPC2292 94 controller s Chip Select signals is only possible in a restricted matter This is due to hardware defined address ranges for the individual CS signals Only bus access time and access type can be coinfigured with the bus configuration registers to BCFG3 The following table shows the predefined address ranges for the individual CS signals banks and the corresponding bus configuration registers Bank Address Range Configuration Register 0 8000 0000 80FF FFFF BCFGO 1 8100 0000 81FF FFFF BCFGI 2 8200 0000 82FF FFFF BCFG2 3 8300 0000 83FF FFFF BCFG3 Table 38 CS Signal Bank Address Ranges and Configuration Registers The following image depicts the default memory model on the Philips LPC2292 94 microcontroller showing internal and external address spaces of the controller This memory model also applies to the phyCORE LPC2292 94 module 50 PHYTEC Messtechnik GmbH 2006 1 658 5 Memory Models OxFFFF FFFF AHP Peripherals OxF000 0000 VPB Peripherals
63. al GPIOO JP17 closed A low level at port pin PO 8 causes the LED to illuminate LED D3 remains off when writing a high level to 0 8 Jumper Setting Description JP17 closed Port pin 0 8 GPIOO of the LPC2292 94 controls LED D3 on the Carrier Board Table 67 JP17 Configuration of the Programmable LED D3 16 3 10 User Push Button S3 The phyCORE Carrier Board HD200 starting with PCB revision 1179 6 offers a push button at S3 for user implementations Jumper JP40 connects this push button to port pin P015 X700B3 BUS4 or P020 X700A4 BUS5 of the phyCORE LPC2292 94 If the push button is pressed the corresponding port pin will read a low level on this input A 4 7 kOhm pull up resistor ensure a high level at this line when the button is not activated Jumper Setting Description JP40 1 2 Port pin 0 20 BUSS of the LPC2292 94 connected to push button 53 on the Carrier Board 2 3 Port pin P0 15 BUSA of the LPC2292 94 connected to push button 53 on the Carrier Board open Push button 53 on the Carrier Board not connected Table 68 JP40 Configuration of User Button S3 PHYTEC Messtechnik GmbH 2006 1 658 5 107 phyCORE LPC2292 94 16 3 11 Pin Assignment Summary of the phyCORE the Expansion Bus and the Patch Field As described in section 16 1 all signals from the phyCORE LPC2292 94 extend in a strict 1 1 assignment to the Expansion Bus connector X2 on the Carrier
64. alternative JTAG interface select input 41D P123 VO Port P123 of the microcontroller see data sheet alternative PIPESTAT2 of TRACE port 42D P124 VO Port P124 of the microcontroller see data sheet alternative TRACECLK of TRACE port PHYTEC Messtechnik GmbH 2006 1 658 5 15 phyCORE LPC2292 94 Pin Number Signal VO Description Pin Row X700D 43D FS3 VO Freely programmable PLD signal may be used as additional Chip Select signal 45D TDI_PLD I JTAG Scan Chain TDI signal from the PLD 46D TCK_PLD I JTAG Scan Chain TCK signal from the PLD 47D TDO_PLD O JTAG Scan Chain TDO signal from the PLD 44D 49D VAGND Analog Ground 48D P029 VO Port P029 of the microcontroller see data sheet 50D ADVREF I Reference voltage input for A D converter Table 1 Pinout of the phyCORE Connector 16 PHYTEC Messtechnik GmbH 2006 L 658e 5 Jumpers 3 Jumpers For configuration purposes the phyCORE LPC2292 94 has 51 solder jumpers some of which have been installed prior to delivery Figure 5 illustrates the numbering of the jumper pads while Figure 6 and Figure 7 indicate the location of the jumpers on the board With the exception of J619 J620 and J22 all other solder jumpers are located at the top side microcontroller side of the module 1 loot 2 1 4 loo gt 2 3 2 e g J400 401 e g J200 J201 e g J205 J206 Figure 5 Numbering of the Jumper Pads coms
65. and 0606 not populated 19C P019 VO Port P019 of the microcontroller see data sheet 20C PWROFF I PWROFF signal low level on this pin disables the power supply of the module 21C ext I Input of the second serial interface of the phyCORE LPC2292 94 RS 232 level 23C TxD1_ext Output of the second serial interface of the phyCORE LPC2292 94 RS 232 level 24C P021 VO Port P021 of the microcontroller see data sheet 25C P022 VO Port P022 of the microcontroller see data sheet 26C PCSO SPI Chip Select 0 for EEPROM U607 28C MOSIO Master Out Slave In for EEPROM 0607 29C P118 Port P118 of the microcontroller see data sheet 30C P119 VO Port P119 of the microcontroller see data sheet 31C SCL clock line for RTC 33C LAN_LED_A LINK LED output for Ethernet interface 34C LAN_LED_B LAN LED output for Ethernet interface 35C LAN_TPI I Negative Rx input of the Ethernet interface 36C LAN_TPO Negative Tx output of the Ethernet interface 38C P128 Port P128 of the microcontroller see data sheet TDI I alternative data input JTAG interface 39C P131 Port P131 of the microcontroller see data sheet TRST I alternative reset input JTAG interface 40C P129 Port P129 of the microcontroller see data sheet TCK I alternative clock input JTAG interface 41 P122 Port P122 of the microcontroller alternative PIPESTATI of TRACE port 42C 47C AGND Analog Groun
66. ansceivers U605 and U606 In order to ensure proper CAN_High and CAN_Low voltage levels the applicable CAN transceiver must be supplied with the required voltage level at pin 3 The following configurations are possible CAN Transceiver Supply Configuration J615 Pin 3 on CAN transceivers U605 and U606 connected 1 2 to 5 V supply voltage VDD V5VO use only with TLE6250V33 devices Pin 3 on CAN transceivers U605 and U606 not 2 3 connected to 3 3 supply voltage VDD_V3V3 use only with other CAN transceivers Default setting Table 28 J615 CAN Level Configuration PHYTEC Messtechnik GmbH 2006 1 658 5 4 phyCORE LPC2292 94 3 20 616 J617 CAN Transceiver VCC Pin 5 These jumpers are used to connect the 3 3 V main supply voltage to pin 5 on the TLE6250V33 CAN transceivers at U605 J616 and U606 J617 If other CAN transceiver devices are used on the phyCORE LPC2292 94 these jumpers must remain open The following configurations are possible CAN Transceiver VCC Pin 5 J616 J617 Pin 5 on CAN transceivers U605 connected closed to 3 3 supply voltage use only with TLE6250V33 devices Pin 5 on CAN transceivers U605 not open connected to 3 3 V supply voltage use only with other CAN transceivers devices Pin 5 on CAN transceivers U606 connected closed to 3 3 V supply voltage use only with TLE6250V33 devices Pin 5 on CAN transceivers U606 not open connected to 3 3 V su
67. are write protection Flash bank U300 U301 with hardware closed don t care write protection Flash bank U302 U303 without hardware don t care open write protection Flash bank U302 U303 with hardware don t care closed write protection Default setting Table 11 7301 J302 Flash Write Protection Configuration PHYTEC Messtechnik GmbH 2006 L 658e 5 31 phyCORE LPC2292 94 3 10 J400 J401 SRAM Configuration Jumpers J400 and J401 are required for configuring the SRAM signals BLSO through BLS3 This configures the controller access to the various SRAM types that can be populated on the phyCORE LPC2292 94 since these can have various data bus configurations The following configurations are possible Signal Configuration J400 J401 BLSO and BLS1 signals configured for p accessing fast SRAMs BLS2 and BLS3 signals configured for 3 4 4 3 4 4 accessing fast SRAMs i e 10 ns BLSO and BLS1 signals configured for 1 3 1 3 accessing standard SRAMs BLS2 and BLS3 signals configured for 2 4 2 4 accessing standard SRAMs i e 55 ns Default setting Table 12 J400 7401 SRAM Access Configuration 311 J402 SRAM Supply Voltage The SRAMs 0400 0403 can operate with or without a battery buffer Jumper J402 is used to set the supply voltage for the SRAM The following configurations are possible SRAM 0400 0403 Supply Voltage J402 VCCRAM derived from VDD V3V3
68. ating C210 with a 100 50 capacitor Note Because of the oscillator properties C210 should not be closed when using the on board quartz oscillator This can have a negative effect on the stability of the quartz oscillation If an external clock input via X700A1 is required the on board quartz oscillator must be removed The following configurations are possible CLKIN Configuration C210 Using the on board crystal XT1 open Supply via external clock signal at phyCORE 100p 50V capacitor connector pin X700A1 mounted Default setting Table 35 C210 CLKIN Configuration 46 PHYTEC Messtechnik GmbH 2006 1 658 5 System Configuration 4 System Configuration Although most features of the Philips LPC2292 94 microcontroller are configured and or programmed during the initialization routine other features which impact program execution must be configured prior to initialization via pin termination 4 1 System Startup Configuration Following a hardware reset certain port pins are latched by the controller to configure chip level features The desired port pins can be connected to a weak pull down resistor resulting in logical 0 or by leaving the connections open resulting in logical 1 Internal pull up resistors ensure a high level if the pin is left unconnected 4 7 kQ pull down resistors are recommended although the resistor value is also dependent upon the external circuitry connecte
69. cal appliances or as dedicated Evaluation Boards 1 for use as a test and prototype platform for hardware software development in laboratory environments Caution PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC Messtechnik GmbH 2006 1 658 5 1 phyCORE LPC2292 94 PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE LPC2292 94
70. connected to each end of the CAN bus For larger CAN bus systems an external opto coupler should be implemented to galvanically separate the CAN transceiver and the phyCORE LPC2292 94 This requires removal of the on board CAN transceivers and routing the CANTx and CANRx lines to the phyCORE connector X700 by closing Jumpers J602 J603 J604 and J605 For connection of the CANTx and CANR x lines to an external transceiver we recommend using a Hewlett Packard HCPLO6xx or Toshiba TLP113 fast opto coupler Parameters for configuring a proper CAN bus system can be found in the DS102 norms from the CiA CAN in Automation User and Manufacturer s Interest Group l CAN in Automation Founded in March 1992 CiA provides technical product and marketing information with the aim of fostering Controller Area Network s image and providing a path for future developments of the CAN protocol 56 PHYTEC Messtechnik GmbH 2006 L 658e_5 Serial EEPROM 7 Serial EEPROM U607 The phyCORE LPC2292 94 is populated with a non volatile memory with a serial interface SPI interface to store configuration data According to the memory configuration of the module an EEPROM 1 to 8 kByte can be mounted at U607 A description of the SPI protocol can be found in the applicable EEPROM Data Sheet Table 39 gives an overview of the memory components that can be used at U607 at the time of printing of this manual
71. converter on the phyCORE LPC2292 94 requires an upper and lower reference voltage V connected at pin 14 of the microcontroller The reference voltage source can be selected using Jumper J204 The following configurations are possible Reference Voltage Configuration J204 apvrer derived from main supply voltage VDD_V3V3 Dx external A D reference voltage source 243 V at X700D50 Default setting Table 5 J204 A D Converter Reference Voltage 3 4 J205 J206 Chip Select Configuration If the phyCORE LPC2292 94 is delivered with the minimum memory configuration then the CPLD device is not required In this case Jumper J205 and J206 must be closed in order to connect the Chip Select signals for Flash and SRAM with the corresponding controller signals These jumpers remain open on all other memory configuration varaints of the phyCORE LPC2292 94 since the required Chip Select signals for Flash and SRAM must be decodede by the CPLD at U202 in order to ensure correct memory addressing 26 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers The following configurations are possible connected to uC CSO and CS1 Chip Select for Flash and RAM J205 J206 Chip Selects for Flash and RAM decoded open open by the CPLD Chip Selects for Flash and RAM directly closed closed Note If minimum configuration of the phyCORE LPC2292 94 is used these jumpers must
72. cted with CAN_L2 RD2 from the phyCORE LPC2292 94 JP34 2 3 Pin 7 at P2B is connected with CAN_H2 TD2 from the phyCORE LPC2292 94 JP14 1 2 Input at opto coupler U6 on the Carrier Board is connected to P1 21 of the phyCORE LPC2292 94 2 3 Input at opto coupler U6 on the Carrier Board is connected to A23 of the phyCORE LPC2292 94 open Input at opto coupler U6 on the Carrier Board not connected JP15 1 2 Output at opto coupler U7 on the Carrier Board is connected to P1 20 of the phyCORE LPC2292 94 2 3 Output at opto coupler U7 on the Carrier Board is connected to A20 of the phyCORE LPC2292 94 open Output at opto coupler U7 on the Carrier Board not connected JP13 PIS Supply voltage for CAN transceiver and opto coupler derived from local supply circuitry on the phyCORE Carrier Board HD200 JP18 closed CAN transceiver and opto coupler on the Carrier Board connected with local GND potential JP29 open No power supply via CAN bus JP39 Table 60 Incorrect CAN bus supply voltage reduction for CAN circuitry Table 66 Improper Jumper Settings for the CAN Plug P2B CAN Transceiver on Carrier Board with Galvanic Separation 106 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 3 9 Programmable LED D3 The phyCORE Carrier Board HD200 offers a programmable LED at D3 for user implementations This LED can be connected to port pin 0 8 TxD1 of the phyCORE LPC2292 94 which is available via sign
73. d of the microcontroller 43C P125 Port P125 of the microcontroller alternative EXTINO of TRACE port 44C 45C FS4 FS5 Freely programmable PLD signal may be used as additional Chip Select signal 46C TMS_PLD I JTAG Scan Chain TMS Signal from the PLD 48C 49C P030 P028 Port PO of the microcontroller 50 P027 alternative analog inputs AINO AINI AIN3 14 PHYTEC Messtechnik GmbH 2006 L 658e 5 Pin Description Pin Row X700D 1D 2D VCC Voltage input 3 3 VDC 9D 14D 19D GND Ground 0 V 24D 29D 34D 39D 4D 5D 7D NC Not connected These contacts should remain unconnected on the target hardware side 6D VPD Output of back up voltage supply for buffering of external components 8D WDI I MAX6301 Watchdog input 10D RESIN I RESET input of the phyCORE LPC2292 94 11D TxD1 Output of the second serial interface TTL level alternative port 8 of the microcontroller 12D RxDI I Input of the second serial interface TTL level alternative port PO9 of the microcontroller 13D P011 VO Port PO11 of the microcontroller see data sheet 15D P017 Port P017 of the microcontroller see data sheet 16D RxDO I Input of the first serial interface TTL level alternative port 1 of the microcontroller 17D TxDO Output of the first serial interface TTL level alternative
74. d to port P04 connected to the uC on the of the uC P04 is then no module external connection longer available as standard required at pin X700D28 P04 VO pin at X700B48 is available as standard I O pin at X700B48 7615 1 2 Supply voltage for 2 3 Supply voltage for transceivers U605 and U606 transceivers U605 and U606 TLE6250V33 from VCC2 connected to VDD_V3V3 5 V 3 3 V J616 closed Pin 5 transceivers open Pin 5 on CAN transceivers U605 U605 connected to 3 3 V not connected to 3 3 V supply supply voltage use only voltage use only with other with TLE6250V33 devices CAN transceivers devices J617 closed Pin 5 on CAN transceivers open Pin 5 on CAN transceivers U606 U606 connected to 3 3 V not connected to 3 3 V supply supply voltage use only voltage use only with other with TLE6250V33 devices CAN transceivers J618 open VDD_V3V3 supply voltage closed VDD_V3V3 supply voltage is switched via FET Q600A directly derived from VCC PHYTEC Messtechnik GmbH 2006 L 658e 5 23 phyCORE LPC2292 94 Default Setting Alternative Setting J619 open SPIO is operated in master closed SPIO is operated in slave mode mode J620 open SPII is operated in master closed 5 is operated in slave mode mode J621 open P021 is available as closed signal is generated via standard I O pin at port P021 X700C24 J622 open RESET signal generated clos
75. d to the port pins in question Table 36 and Table 37 show the individual port pins used for system startup configuration the corresponding pull down resistor and the location of the signals on the phyCORE connector Boot Device Selection Configuration D26 BOOTO via D27 BOOTI via R203 X700B43 R204 X700A44 CSO configured for populated unpopulated 32 bit memory BOOTO 0 1 CSO configured for 16 unpopulated populated bit memory BOOTO 1 BOOTI o CSO configured for 8 populated populated bit memory BOOT0 0 BOOTI 0 Internal Flash access unpopulated unpopulated 1 1 36 System Startup Configuration Boot Device Selection Default system startup configuration on the phyCORE LPC2292 94 PHYTEC Messtechnik GmbH 2006 L 658e 5 47 phyCORE LPC2292 94 Debug Trace Port Configuration Configuration R205 for P120 R206 for P126 X700D30 X700D37 P1 16 through P1 25 populated don t care function as TRACE port P1 16 through P1 25 unpopulated don t care function as port pins P1 26 through P1 31 don t care populated function as Debug port P1 26 through P1 31 don t care unpopulated function as port Table 37 System Startup Configuration Debug Trace Port Default system startup configuration on the phyCORE LPC2292 94 Default system startup configuration with debugCORE LPC2292 94 4 2 Starting the LPC2292
76. dcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH EUROPE NORTH AMERICA Address PHYTEC Technologie Holding AG PHYTEC America LLC Robert Koch Str 39 203 Parfitt Way SW Suite G100 D 55129 Mainz Bainbridge Island WA 98110 GERMANY USA Ordering 49 800 0749832 1 800 278 9913 Information order phytec de sales phytec com Technical 49 6131 9221 31 1 800 278 9913 Support support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 Web Site http www phytec de http www phytec com 5 Edition July 2006 PHYTEC Messtechnik GmbH 2006 1 658 5 Contents Prei te NR 1 1 Introduction sisi sass vehe eii EY ka here E sesoses REDE 3 LL Block Dig csse er een 6 1 2 View of the 2292 94 7 2 Pin TCS CTA COM 9 17 3 1 7200 7202 Second Serial Interface 24 3 2 J201 J203 First Serial Intertace ehe 25 3 3 J204 A D Convert asien 26 3 4 J205 J206 Chip Select 26 3 5 4207 MCKO SH RE 21 3 6 J208 J209 Flash Size 28 3 7 J210 J211 RAM Size Confi
77. e increased pin package allows dedication of approximately 20 of all pin header connectors on the phyCORE boards to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD components and laser drilled Microvias are used on the boards providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design The phyCORE LPC2292 94 is a subminiature 60 x 53 mm insert ready Single Board Computer populated with the Philips LPC2292 94 microcontroller Its universal design enables its insertion in a wide range of embedded applications All controller signals and ports extend from the controller to high density pitch 0 635 mm connectors aligning two sides of the board allowing it to be plugged like a big chip into a target application PHYTEC Messtechnik GmbH 2006 L 658e 5 3 phyCORE LPC2292 94 Precise specifications for the controller populating the board can be found in the applicable controller User s Manual or Data Sheet The descriptions in this manual are based on the Philips LPC2292 94 No description of compatible microcontroller derivative functions is included as such functions are no
78. ed RESET signal generated through Q601 open drain through U601 push pull Additional jumper settings only applicable when using the debugCORE LPC2292 2294 J800 open Pin 1 on ETM OCDS closed Pin 1 on ETM OCDS connector RESET not connector carries module s connected RESET signal J801 1 2 Vsupply and VTREF on the 2 3 Vsupply and VTREF are ETM OCDS connector are connected to GND supplied via VDD_V3V3 Configuration depends on Configuration depends on Emulator requirements refer to Emulator requirements applicable data sheets refer to applicable data sheets Table 2 Jumper Settings 3 1 J200 J202 Second Serial Interface Jumpers J200 and J202 are used to route the signals of the second synchronous asynchronous serial interface via the RS 232 transceiver to the phyCORE connector pins X700C21 RxD1 and X700C23 TxD1 If the jumpers are closed in position 2 3 then the applicable controller pins P08 and 09 can be used with their alternative functions or the serial interface signals are available with their TTL level at phyCORE connector pins X700C21 and X700C23 If the jumpers are closed at position 1 2 we recommend not to use the interface signals with their TTL level as this will cause damage to the on board components 24 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers The following configurations are possible Signal Configuration J200 J202 TxD1 and Rx
79. en Flash bank U302 U303 not closed Flash banks U302 U303 is write write protected protected J400 1 2 BLSO and BLS1 signals 1 3 BLSO and BLS1 signals 3 4 configured for accessing fast 2 4 configured for accessing SRAM devices standard SRAM devices J401 1 2 BLS2 and BLS3 signals 1 3 BLS2 and BLS3 signals 3 4 configured for accessing fast 2 4 configured for accessing SRAM devices standard SRAM devices J402 1 2 VCCRAM connected with open No power supply for RAM VDD_V3V3 devices 2 3 connected with VBAT for external supply via battery J500 1 2 EEPROM U500 ORG 2 3 EEPROM U500 ORG pin connected with VDD_V3V3 connected with GND internal internal EEPROM EEPROM organization organization configured to configured to 8 16 J501 1 2 High active interrupt output 2 3 High active interrupt output from SMSC LAN91C111 from SMSC LAN91C111 chip chip connected to EINTO connected PA014 on 016 on the uC P016 is the uC PO14 is then no longer then no longer available as available as standard I O pin at standard I O pin at X700B2 X700A3 open Interrupt signals or standard I O pins freely available at Molex pins X700B2 and X700A3 J502 1 2 CS2 from the uC connected 2 3 CS3 from the uC connected with Chip Select signal on with Chip Select signal on SMSC LAN91C111 chip SMSC 91 111 chip CS3 CS2 is then no longer is then no longer available at available at X700A6 X700
80. epending on the specific configuration of the phyCORE LPC2292 94 module alternative jumper settings can be used These jumper settings are different from the factory default settings as shown in Figure 19 and enable alternative or additional functions on the phyCORE Carrier Board HD200 depending on user needs 16 3 1 Power Supply at X1 Caution Do not use a laboratory adapter to supply power to the Carrier Board Power spikes during power on could destroy the phyCORE module mounted on the Carrier Board Do not change modules or jumper settings while the Carrier Board is supplied with power Permissible input voltage 5 VDC regulated The required current load capacity of the power supply depends on the specific configuration of the phyCORE LPC2292 94 mounted on the Carrier Board as well as whether an optional expansion board is connected to the Carrier Board An adapter with a minimum supply of 500 mA is recommended Jumper Setting Description JP9 1 2 3 3 V primary main supply voltage to the phyCORE LPC2292 94 JP16 2 3 5 V as secondary main supply voltage to the phyCORE LPC2292 94 Table 46 JP9 JP16 Configuration of the Main Supply Voltages VCC VCC2 84 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board Polarity 5 VDC Center Hole gt 500 mA 3 5 VA GND Figure 20 Connecting the Supply Voltage at Caution When us
81. er Settings 83 16 3 Functional Components on the phyCORE Carrier Board D200 ua 84 16 3 1 Power Supply at aan 84 16 3 2 Starting the ISP Command 86 16 3 3 phyCROE LPC2292 4 Boot Memory Configuration 88 16 3 4 First Serial Interface at Socket P14A 89 16 3 5 Power Supply to External Devices via Socket 91 16 3 6 Second Serial Interface at Socket PIB 93 16 3 7 First CAN Interface at Plug 2 95 16 3 8 Second CAN Interface at Plug 2 101 16 3 9 Programmable LED tenerte otn 107 16 3 10 User Push Button S3 varie ea 107 16 3 11 Pin Assignment Summary of the phyCORE the Expansion Bus and the Patch Field 108 16 3 12 Battery Connector ek 118 16 3 13 052401 Silicon Serial Number 118 16 3 14 Pin Header Connector 119 PHYTEC Messtechnik GmbH 2006 L 658e 5 Contents 93 0 ces eaaa o dried 121 18 Revision History u ana aaa 123 19 Component Placement Diagram 000oo000000000000000000 00000000000000 00000000 125 deeem E E 127 PHYTEC Messtechnik GmbH 2006 L 658e 5 phyCORE LPC2292 94 Index of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
82. flow indication 24 hour format Automatic word address incrementing Programmable alarm timer and interrupt functions The Real Time Clock is programmed via the bus address OxA2 Since the LPC2292 94 is equipped with an internal controller the protocol is processed very effective without extensive processor action The Real Time Clock also provides an interrupt output that extends to the IRQRTC signal X1D33 An interrupt occurs in the event of a clock alarm timer alarm timer overflow and event counter alarm It has to be cleared by software With the interrupt function the Real Time Clock can be utilized in various applications If the RTC interrupt is to be used as a software interrupt via a corresponding interrupt input of the processor the signal must be connected externally with a processor interrupt input For more information on the features of the RTC 8564 refer to the corresponding Data Sheet Note After connection of the supply voltage the Real Time Clock generates no interrupt The RTC must first be initialized see RTC Data Sheet for more information 62 PHYTEC Messtechnik GmbH 2006 1 658 5 Battery Buffer 11 Battery Buffer The connection of a battery buffer is not essential to the functioning of the phyCORE LPC2292 94 However this battery buffer embodies an economical and practical means of storing data in the SRAM devices It is necessary to preserve data fro
83. g interface STAG connector X701 on the phyCORE module Figure 10 JTAG Interface Top View PHYTEC Messtechnik GmbH 2006 L 658e 5 65 phyCORE LPC2292 94 0 Figure 11 JTAG Interface Bottom View Pin 1 of the JTAG concector X701 is marked by a black pad on the connector side of the PCB The JTAG interface of the phyCORE LPC2292 94 can operate in various modes On board configuration resistors select if the corresponding port pins function as JTAG interface or as standard I O port In addition to the standard JTAG port the phyCORE LPC2292 94 also features a TRACE port which is also configured on board resistors Refer to section 13 for details 66 PHYTEC Messtechnik GmbH 2006 L 658e 5 Debug Interface The following configuration options are available R205 R206 JTAG ETM Interface Function unpopulated populated Port pins P1 26 P1 31 function as JTAG ICE interface populated unpopulated Port pins P1 16 P1 25 function as ETM TRACE port unpolulated unpopulated Port pins P1 16 P1 31 available as standard I O port populated populated Port pins P1 16 P1 31 function as JTAG and ETM TRACE port Table 41 and TRACE Modes Note The JTAG connector X701 only populates phyCORE LPC2292 94 modules with order code PCM 023 D This version of the phyCORE module is included in all Rapid Development Kits order code KPCM 023 JTAG connector X701 is n
84. ge Power consumption 3 3 V 300 mA typical VCC2 5 0 V 12 mA typical 60 mm x 53 mm approximately 25 g with all optional components mounted on the circuit board 40 C to 90 C standard 0 C to 70 C extended 40 C to 85 C 95 r F not condensed VCC 3 3 5 VCC2 5 V 5 VBAT 3 V 20 Conditions 3 3 V VBAT 0 V 2 MByte fast SRAM 4 MByte Flash 10 MHz quartz 60 Mhz CPU frequency at 20 C These specifications describe the standard configuration of the phyCORE LPC2292 94 as of the printing of this manual Please note that the module storage temperature is only 0 C to 70 C if a battery buffer is used for the RAM devices 74 PHYTEC Me technik GmbH 2006 1 658 5 Hints for Handling 15 Hints for Handling the phyCORE LPC2292 94 The address and data bus on the module is not buffered To connect external components to the data address bus as well as the control lines RD WR an external buffer i e 74AHCT245 between the modul and the peripheral components should be installed The data bus DO 31 port 0 should be connected with a 100 kQ pull up resistor against VCC Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering Overheating
85. gt write protection error WP 0 gt bank not write protected BM 0 gt burst ROM bank MW 2 gt 32 bit wide bus AT 0 gt J always write 0 to this field PHYTEC Messtechnik GmbH 2006 1 658 5 53 phyCORE LPC2292 94 BCFG2 Register Configuration Value 0x02000 0C23 IDCY 3 gt Aidle cycle WSTI 1 gt 4CCLK cycles RBLE 1 gt byte partitioned device WST2 1 gt 4CCLK cycles BUSERR 0 gt not relevant WPERR 0 gt write protection error WP 0 gt bank not write protected BM 0 gt no burst ROM bank MW 2 gt 32 bit wide bus AT 0 gt J always write 0 to this field 54 PHYTEC Messtechnik GmbH 2006 1 658 5 Serial Interfaces 6 Serial Interfaces 6 1 RS 232 Interfaces One RS 232 transceiver is populating the phyCORE LPC2292 94 at U200 This device converts the signal levels for e POI RxDO and POO TxDO frist serial interface e P09 RxD1 and P08 TxD1 second serial interface The ports listed above can also be used alternatively as standard I Os as interface signals with TTL level or in their alternative function on the phyCORE connector X700 For this Jumpers J201 and J203 as well as J200 and J202 must be closed at position 2 3 All RS 232 interfaces enable connection of the module to a COM port on a host PC In this instance the RxD line of the transceiver is connected to the TxD line of the COM port while the TxD line is connected to the RxD line of the COM port The
86. guration 29 3 8 1300 Flash Ready Busy Configuration 30 3 9 J301 J302 Flash Write Protection Configuration 31 3 10 J400 J401 SRAM Configuration eene 32 3 11 3402 SRAM Supply 32 3 12 J500 through J509 Ethernet Controller SMSC LEANOICILICODPBSULFALUOL ei 33 3 13 1600 7601 7616 CAN Transceiver Configuration 36 3 14 7602 1603 1604 1605 CAN 31 3 15 1606 Write Protection of SPI EEPROM 38 3 16 1607 Watchdog 39 3 17 1608 7609 1610 Interface 40 3 18 7611 7612 7613 J614 SPIO Interface 40 3 19 1615 Bus Level Configuration esee 41 3 20 7616 J617 CAN Transceiver VCC Pin 5 42 3 21 1618 VDD_V3V3 Supply 43 3 22 J619 J620 SPI Master Slave 43 3 23 J621 WDE Signal SOURCE ie Ere nitas ona etes 44 3 24 J622 RESET Signal SOULQO AG eno 44 3 25 J800 J801 ETM OCDS Connector Configuration Only with 1 2292 94 45 3 26 C210 CLKIN Configuration aaa 46 4 System Configuration 47 4 1 Syste
87. h CSRO open 51 of the controller only if CPLD U202 is not connected with CPLD U202 populated CPLD generates CSRO CSR1 signals J207 open MCKO signal not routed to closed signals routed to Molex Molex connector pin pin X700B1 J208 open Flash configuration input 1 closed Flash configuration input 1 of of CPLD U202 connected to the CPLD connected to GND via 10k pull up J209 open Flash configuration input 2 closed Flash configuration input 2 of of CPLD U202 connected to the CPLD connected to GND via 10k pull up J210 open RAM configuration input 1 closed RAM configuration input 1 of of CPLD U202 connected to the CPLD connected to GND via 10k pull up J211 open configuration input closed RAM configuration input 2 2 of CPLD 0202 ofthe CPLD connected to connected to VCC via GND 10k pull up Applies to standard modules without optional features minimal memory configuration 2 Default on all other configuration options of the phyCORE LPC2292 94 PHYTEC Messtechnik GmbH 2006 L 658e 5 19 phyCORE LPC2292 94 Default Setting Alternative Setting J300 open P017 of the uC available as closed P017 used to supervise the standard I O at Molex pin Ready Busy outputs of both X700D15 Flash banks U300 U301 and U302 U303 J301 open Flash bank U300 U301 not closed Flash banks U300 U301 is write write protected protected J302 op
88. he patch field on an expansion board is as follows Signal phyCORE Module Expansion Bus Patch Field DO 18B 18B 33F D1 19A 19A 34A D2 20A 20A 34E D3 20B 20B 34B D4 21A 21A 34D D5 21B 21B 34F D6 22B 22B 35A D7 23A 23A 35E D8 28B 28B 37C D9 29A 29A 37E D10 30A 30A 37B D11 30B 30B 37F D12 31A 31A 38A D13 31B 31B 38C D14 32B 32B 38E D15 33A 33A 38B D16 37B 37B 40A D17 38A 38A 40E D18 38B 38B 40B D19 39A 39A 40D D20 40A 40A 40F D21 40B 40B 41 D22 41A 41A 41E D23 41B 41B 41B D24 42B 42B 41F D25 43A 43A 42A D26 43B 43B 42C D27 44A 44A 42E D28 45A 45A 42B D29 45B 45B 42F D30 46A 46A 43A D31 46B 46B 43C Table 69 Pin Assignment Data Bus for the phyCORE LPC2292 94 Carrier Board Expansion Board 110 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board Signal phyCORE Module Expansion Bus Patch Field AO 8B 8B 30B Al 9A 9A 30D A2 10A 10A 30F A3 10B 10B 31A 4 31E 5 31 12 12 31F 7 13A 13A 32A A8 13B 13B 32 9 14 14 32 10 15 15 32 All 15B 15B 32F 12 16 16 33A A13 16B 16B 33C A14 17B 17B 33E A15 18A 18A 33B 16 23B 23B 35B 17 24 24 35D 18 25 25 35 19 25 25 36A A20 26A 26A 36E A21 26B 26B 36B A22 27B
89. in Description The following figure Figure 4 illustrates the numbered matrix system It shows a phyCORE LPC2292 94 with SMT phyCORE connectors on its underside defined as dotted lines mounted on a Carrier Board In order to facilitate understanding of the pin assignment scheme the diagram presents a crossview of the phyCORE module showing these phyCORE connectors mounted on the underside of the module s PCB Figure 4 Pinout of the phyCORE Connector Top View with Cross Section Insert Many of the controller port pins accessible at the connectors along the edges of the board have been assigned alternate functions that can be activated via software PHYTEC Messtechnik GmbH 2006 1 658 5 11 phyCORE LPC2292 94 Table 1 provides an overview of the pinout of the phyCORE connector as well as descriptions of possible alternative functions Please refer to the Philips phyCORE LPC2292 94 User s Manual Data Sheet for details on the functions and features of controller signals and port pins Pin Number Signal I O Description Pin Row X700A 1A CLKIN I Optional external clock generator only in if capacitor C210 is populated 2A 7A 12A 17A GND Ground 0 V 22A 27A 32A 37A 42A 47A 3A P014 I O Port 014 of the microcontroller see data sheet alternative external interrupt 1 input 4A P020
90. ing this function the following jumper settings are not allowed Jumper Setting Description JP9 2 3 5 V as primary main supply voltage for the phyCORE LPC2292 94 open phyCORE LPC2292 94 not connected to primary main supply voltage JP16 1 2 3 3 V as secondary main supply voltage for the phyCORE LPC2292 94 open phyCORE LPC2292 94 not connected to secondary main supply voltage NOTE This setting is correct if the module in its minimum configuration without on board CAN transceivers is used Table 47 JP9 JP16 Improper Jumper Settings for the Main Supply Voltages Setting Jumper JP9 to position 2 3 configures a primary main power supply to the phyCORE LPC2292 94 of 5 V which could destroy the module Setting Jumper JP16 to position 1 2 configures a secondary main power supply to the phyCORE LPC2292 94 of 3 3 V which also can damage the module If Jumper JP9 and JP16 remain open no primary and secondary main power supply is connected to the phyCORE LPC2292 94 These jumper settings should therefore not be used PHYTEC Messtechnik GmbH 2006 L 658e 5 85 phyCORE LPC2292 94 16 3 2 Starting the ISP Command Handler The Philips LPC229x microcontroller family contains an on chip boot loader that provides both In System ISP and In Application programming IAP interfaces The loader can execute an ISP command handler or the user application The combination of this ISP handler and the corres
91. internal open pull up to VDD_V3V3 configuration via predefined EEPROM contents ENEEP signal on LAN 91C111 connected to GND closed see data sheet for details Default setting Table 19 J508 Ethernet EEPROM Enable Configuration Jumper J509 configures the general purpose input port of the LAN91C111 Ethernet controller that is used to convey the LINK status EPHSR bit 14 This LINK_ON bit is typically used for link test See the LAN91CI11 data sheet for details Default setting Table 20 J509 Ethernet nLNK Pin Configuration Ethernet EEPROM Enable Configuration J509 LAN 91C111 nLNK pin tied to GND LINK ON bit in closed the EPH status register is set to 1 LAN 91C111 nLNK pin not connected LINK ON bit in open the EPH status register is set to 0 PHYTEC Messtechnik GmbH 2006 1 658 5 35 phyCORE LPC2292 94 3 13 600 J601 7616 CAN Transceiver Configuration The three Jumpers J600 J601 and J616 are used to configure both CAN transceivers U605 and U606 If the Jumpers J600 and J601 are placed in the corresponding position the CAN transceivers can be switched into power down mode via controller port pins P019 and P020 The following configurations are possible CAN Transceiver Activation J600 J601 CAN transceiver U605 always active 1 2 don t care CAN transceiver U605 mode is 2 3 don t care controlled via port P020 on the LPC2292 94 microcontroller CAN
92. ion board are made using patch cables 8 included with the expansion board Figure 15 illustrates the modular development platform concept Figure 15 Modular Development and Expansion Board Concept with the phyCORE LPC2292 94 The following sections contain specific information relevant to the operation of the phyCORE LPC2292 94 mounted on the phyCORE Carrier Board HD200 For a general description of the Carrier Board please refer to the corresponding Carrier Board Hardware Manual 78 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 2 Carrier Board HD200 Connectors and Jumpers 16 2 1 Connectors As shown in Figure 16 the following connectors are available on the phyCORE Carrier Board HD200 X1 X2 P1 P2 X4 X5 X6 X7 U9 U 10 BATI low voltage socket for power supply connectivity mating receptacle for expansion board connectivity dual DB 9 sockets for serial RS 232 interface connectivity dual DB 9 connectors for CAN or RS 485 interface connectivity voltage supply for external devices and subassemblies GND connector for connection of GND signal of measuring devices such as an oscilliscope phyCORE connector enabling mounting of applicable phyCORE modules interface for Ethernet transformer module EAD 003 space for an optional silicon serial number chip receptacle for an optional battery zur
93. is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports all common 8 and 16 bit as well as selected 32 bit controllers in two ways 1 as the basis for Rapid Development Kits which serve as a reference and evaluation platform 2 as insert ready fully functional micro mini and phyCORE OEM modules which can be embedded directly into the user s peripheral hardware design PHYTEC microcontroller modules allow engineers to shorten development horizons reduce design costs and speed project concepts from design to market 2 PHYTEC Messtechnik GmbH 2006 1 658 5 Introduction 1 Introduction The phyCORE LPC2292 94 belongs to PHYTEC s phyCORE Single Board Computer module family The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology Like its mini micro and nanoMODUL predecessors the phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments As independent research indicates that approximately 70 of all EMI Electro Magnetic Interference problems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package Th
94. ix The pin numbering values increase moving down on the board Lettering of the pin connector rows progresses alphabetically from left to right refer to Figure 4 PHYTEC Messtechnik GmbH 2006 L 658e 5 9 phyCORE LPC2292 94 The numbered matrix can be aligned with the phyCORE LPC2292 94 viewed from above phyCORE connector pointing down or with the socket of the corresponding phyCORE Carrier Board user target circuitry The upper left hand corner of the numbered matrix pin 1A is thus covered with the corner of the phyCORE LPC2292 94 marked with a white triangle The numbering scheme is always in relation to the PCB as viewed from above even if all connector contacts extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyCORE connector as well as mating connectors on the phyCORE Carrier Board or target hardware thereby considerably reducing the risk of pin identification errors Since the pins are exactly defined according to the numbered matrix previously described the phyCORE connector is usually assigned a single designator for its position X1 for example In this manner the phyCORE connector comprises a single logical unit regardless of the fact that it could consist of more than one physical socketed connector The location of row 1 on the board is marked by a white triangle on the PCB to allow easy identification 10 PHYTEC Messtechnik GmbH 2006 1 658 5 P
95. ket 91 55 R nasser 58 Polens 88 58 RAM Size ann 29 58 Real Time Clock 62 123 ISOS tei rn EMT 58 Reference Voltage EENT tee 26 sti ism 61 Reset 81 UDUT Eee 59 RS 232 Interface s 55 ater o Deal 62 123 RS 232 Transceiver 55 VOUS 56 PUT U ous eh 62 63 UG ort e e e bad 56 RTC Interrupt D ALE E 62 c 57 UART on chip 55 5 UARIQ ee 55 Delta 40 oia 55 SDA 40 User Push Button S3 107 Second CAN Interface 101 V Second Serial Interface 93 Serial Interface 1 25 26 Serial Interface 2 24 MB AT 63 Serial Interfaces 55 43 Silicon Serial Number 118 63 SMSC LANO9IC111 33 W SMT Connector 9 Socket First RS 232 89 Watchdoe unseres 39 Socket PIB Second RS 232 93 WIR Aeee e 44 1 EE 43 Weight nenne 74 SPI Interface 40 57 X SPI MAST secet terrre 43 SB A Sud NE 43 TOL Eam E 65 PHYTEC Messtechnik GmbH 2006 L 658e 5 129 phyCORE LPC2292 94 130 PHYTEC Me technik GmbH 2006 L 658e 5 Sugge
96. l Number 119 Figure 33 Pin Assignment of 052401 Silicon Serial Number 119 Figure 34 Ethernet Transformer Module Connector 121 Figure 35 Location of Solder Jumpers J1 J4 and Ethernet Interface M sU arat 122 Figure 36 phyCORE LPC2292 94 Component Placement TOP E 125 Figure 37 phyCORE LPC2292 94 Component Placement Bottom View usato te e 126 Index of Tables Table 1 Pinout of the phyCORE Connector 16 Table2 Jumper Setngs 24 Table 3 J200 J202 Second Serial Interface Configuration 25 Table 4 201 J203 First Serial Interface Configuration 25 PHYTEC Messtechnik GmbH 2006 L 658e 5 phyCORE LPC2292 94 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 1204 A D Converter Reference Voltage 26 J205 7206 Chip Select 27 J207 MCKO Signal Configuration esses 27 J208 7209 Flash Memory Size Configuration 28 J210 J211 RAM Memory Size Configuration
97. llowing table contains improper jumper settings for operation of the phyCORE LPC2292 94 on phyCORE Development Board HD200 Functions configured by these settings are not supported by the phyCORE module No RS 485 interface DB 9 plug P2B on the Carrier Board can be configured as RS 485 interface as an alternative to the second CAN interface The phyCORE LPC2292 94 does not support an RS 485 interface For this reason the corresponding jumper settings should never be used Jumper Setting Description JP30 closed TxD signal for second serial interface routed to pin 8 on the DB 9 plug P2B JP33 RxD signal for second serial interface routed to pin 2 on the DB 9 plug P2B Table 45 Improper Jumper Setting for JP30 33 the Carrier Board Reference Voltage Source for A D Converter Pins X1C42 X1C47 X1D44 and X1D49 VAGND of the phyCORE LPC2292 94 are solely connected with the phyCORE Carrier Board HD200 GND potential This makes a separate supply with an alternative VAGND potential impossible Free definition of the VAGND potential is however available in a customer application board PHYTEC Messtechnik GmbH 2006 1 658 5 83 phyCORE LPC2292 94 16 3 Functional Components on the phyCORE Carrier Board HD200 This section describes the functional components of the phyCORE Carrier Board HD200 supported by the phyCORE LPC2292 94 and appropriate jumper settings to activate these components D
98. lug P2A CAN Transceiver on Carrier Board 1 Please make sure the CAN transceiver on the phyCORE LPC2292 94 is not populated and Jumpers J602 and J604 are closed refer to section 3 14 for details 96 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board Caution When using the DB 9 connector P2A as CAN interface and the CAN transceiver on the Carrier Board the following jumper settings are not functional and could damage the module Jumper Setting Description JP31 2 3 phyCORE LPC2292 94 Pin 2 of DB 9 plug P2A connected with RD1 of the JP32 2 3 Pin 7 of DB 9 plug P2A connected with TD1 of the phyCORE LPC2292 94 1 2 Input at opto coupler U4 on the Carrier Board is connected to SCLKO of the phyCORE LPC2292 94 2 3 Input at opto coupler U4 on the Carrier Board is connected to A22 of the phyCORE LPC2292 94 open Input at opto coupler U4 on the Carrier Board not connected JP12 1 2 Output at opto coupler US on the Carrier Board is connected to MISOO of the phyCORE LPC2292 94 2 3 Output at opto coupler US on the Carrier Board is connected to A21 of the phyCORE LPC2292 94 open Output at opto coupler U5 on the Carrier Board not connected JP13 Lee Supply voltage for CAN transceiver and opto coupler on the Carrier Board derived from external source CAN bus via on board voltage regulator JP29 closed Supply voltage for on board
99. m Startup 47 4 2 Starting the LPC2292 94 ISP 48 5 Memory Mod lS issssssssessosssssssnssesessssesssssssossssosssssssosssssassssssisssssssss s 49 PHYTEC Messtechnik GmbH 2006 1 658 5 phyCORE LPC2292 94 6 Serial aaa 55 289 232 Interfaces aka wa sa 55 8 2 Interface anne 56 Serial EEPROM U607 uns 57 On Board Flash Memory 0300 0303 58 LAN 91C111 Ethernet Controller U501 59 91 MAC A TN 60 9 2 Ethernet EEPROM 0500 sse 61 9 3 10 100Base T Interface an 61 Real Time Clock 8564 U604 62 Battery Buffer 63 Debus Interface X701 eset Rae dera a race dee naeh 65 debugsCORE LPC2292 94 una 69 Technical Specifications ana 73 Hints for Handling the 1 2292 94 75 The phyCORE LPC2292 94 on the phyCORE Carrier Board HD200 nenne 77 16 1 Concept of the phyCORE Carrier Board 200 77 16 2 Carrier Board HD200 Connectors and Jumpers 79 162 1 COMME 79 16 2 2 Jumpers on the phyCORE Carrier Board HD200 81 16 2 3 Unsupported Features and Improper Jump
100. m the Real Time Clock of the phyCORE LPC2292 94 in case of a power failure The VBAT input at pin X700C6 of the board is provided for connecting the external battery The negative polarity pin on the battery must be connected to GND on the phyCORE LPC2292 94 As of the printing of this manual a lithium battery is recommended as it offers relatively high capacity at low discharge In the event of a power failure at VCC the RTC will be buffered by a connected battery via VBAT The RTC is generally supplied via VPD in order to preserve data by means of the battery back up in the absence of a power supply via VCC The battery supply for the SRAM devices is configured with Jumper J402 refer to section 3 11 If the SRAM battery supply is enabled the user must ensure that the battery is capable of supplying both SRAM and RTC at runtime of the module Power consumption depends on the installed components and memory size see section 14 Technical Specifications PHYTEC Messtechnik GmbH 2006 L 658e 5 63 phyCORE LPC2292 94 64 PHYTEC Messtechnik GmbH 2006 L 658e 5 Debug Interface 12 Debug Interface X701 The phyCORE LPC2292 94 is equipped with a JTAG interface for downloading program code into the external Flash or for debugging programs in the external SRAM The JTAG interface extends out to 2mm pitch pin header rows X701 on the controller side of the module Figure 10 and Figure 11 show the position of the debu
101. ma nently connected to VCC via a pull up resistor This pulls port pin P0 14 to low level via on board circuitry which then starts the ISP mode This spares pushing the Boot button during a hardware reset power on Caution In this configuration a regular reset hence normal start of your application is not possible The microcontroller will always enter ISP mode after reset Jumper Setting Description JP28 4 6 Boot input connected permanently with VCC via pull up resistor The ISP command handler is always started with reset or with connection of the power supply Table 49 28 Configuration of a Permanent ISP Mode Start PHYTEC Messtechnik GmbH 2006 1 658 5 87 phyCORE LPC2292 94 16 3 3 phyCROE LPC2292 4 Boot Memory Configuration Jumper JP41 can be used to select the boot memory device from which the LPC2294 controller fetches instructions If the phyCORE LPC2292 94 is populated with on board Flash and pull down resistor R203 is not installed the following boot options are available on the SBC module refer to section 4 1 for more information on boot memory selection options and phyCORE SBC default configuration 1 Boot from controller internal Flash Starting code stored in the controller internal Flash on the phyCORE LPC2292 94 is possible by changing the boot configuration during startup An important requirement for this boot option in combination with the phyCORE Carrier Board HD
102. mage the module Jumper Setting Description JP31 Pea Pin 2 of DB 9 plug P2A connected with RD1 of the phyCORE LPC2292 94 JP32 2 3 Pin 7 of DB 9 plug P2A connected with TD1 of the phyCORE LPC2292 94 1 2 Input at opto coupler U4 on the Carrier Board is connected to SCLKO of the phyCORE LPC2292 94 2 3 Input at opto coupler U4 on the Carrier Board is connected to A22 of the phyCORE LPC2292 94 open Input at opto coupler U4 on the Carrier Board not connected JP12 1 2 Output at opto coupler US on the Carrier Board 15 connected to MISOO of the phyCORE LPC2292 94 2 3 Output at opto coupler US on the Carrier Board 15 connected to A21 of the phyCORE LPC2292 94 open Output at opto coupler U5 on the Carrier Board not connected JP13 Hope Supply voltage for CAN transceiver and opto coupler derived from local supply circuitry on the phyCORE Carrier Board HD200 JP18 closed CAN transceiver and opto coupler on the Carrier Board connected with local GND potential JP29 open No power supply via CAN bus JP39 see Table 60 Incorrect CAN bus supply voltage reduction for CAN circuitry Table 61 Improper Jumper Settings for the CAN Plug P2A CAN Transceiver on Carrier Board with Galvanic Separation 100 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 3 8 Second CAN Interface at Plug P2B Plug P2B is the upper plug of the double DB 9 connector at
103. on 114 Pin Assignment Interface Signals for the phyCORE LPC2292 94 Carrier Board Expansion Board 115 Pin Assignment Power Supply for the phyCORE LPC2292 94 Carrier Board Expansion BO AEC 116 Unused Pins on the phyCORE LPC2292 94 Carrier Board Expansion 22 222 022 117 JP19 Jumper Configuration for Silicon Serial Chipset 118 Ethernet Transformer Connector Pinout 121 Solder Jumpers J1 4 Configuration Ethernet Interface 122 PHYTEC Messtechnik GmbH 2006 L 658e 5 phyCORE LPC2292 94 PHYTEC Messtechnik GmbH 2006 1 658 5 Preface Preface This phyCORE LPC2292 94 Hardware Manual describes the board s design and functions Precise specifications for the Philips LPC2292 94 microcontroller can be found in the enclosed microcontroller Data Sheet User s Manual If software is included please also refer to additional documentation for this software In this hardware manual and in the attached schematics low active signals are denoted by a in front of the signal name 1 RD A 0 indicates a logic zero or low level signal while a 1 represents a logic one or high level signal Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE LPC2292 94 PHYTEC Single Board Computers henceforth products are designed for installation in electri
104. ontrol and display units and the CAN transceivers The Reset input on the phyCORE LPC2292 94 directly connects to the Reset button S2 Figure 17 illustrates the numbering of the jumper pads while Figure 18 indicates the location of the jumpers on the Carrier Board z B JP28 z B JP23 z B JP24 Figure 17 Numbering of Jumper Pads Figure 18 Location of the Jumpers View of the Component Side PHYTEC Messtechnik GmbH 2006 1 658 5 8l phyCORE LPC2292 94 Figure 19 shows the factory default jumper settings for operation of phyCORE Carrier Board HD200 with the standard phyCORE LPC2292 94 standard LPC2292 controller use of first and second RS 232 and CAN interfaces and LED D3 on the Carrier Board Jumper settings for other functional configurations of the phyCORE LPC2292 94 module mounted on the Carrier Board are described in section 16 3 PHYTEC Messtechnik GmbH PCB 1179 6 Figure 19 Default Jumper Settings of the phyCORE Development Board HD200 with phy CORE LPC2292 94 82 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 2 3 Unsupported Features and Improper Jumper Settings The fo
105. ot populated on phyCORE modules with order code PCM 014 that are intended for OEM implementation However all JTAG signals are also accessible at the phyCORE connector X1 Molex connectors We recommend integration of a standard 2 54 mm pitch pin header connector in the user target circuitry to allow easy program updates via the JTAG interface See Table 74 for details on the JTAG signal pin assignment PHYTEC offers a JTAG Emulator adapter order code JA 002 for connecting the phyCORE LPC2292 94 to a standard emulator The JTAG Emulator adapter extends the signals of the module s JTAG connector to a standard ARM connector with 2 54 mm pin pitch The JA 002 therefore functions as an adapter for connecting the module s non ARM compatible JTAG connector X701 to standard Emulator connectors PHYTEC Messtechnik GmbH 2006 L 658e 5 67 phyCORE LPC2292 94 68 PHYTEC Messtechnik GmbH 2006 L 658e 5 debug CORE LPC2292 94 13 debugCORE LPC2292 94 The debugCORE LPC2292 94 is a special debugging version of the phyCORE LPC2292 94 module The debugCORE differs from its phyCORE counterpart in that an additional debug interface and corresponding circuitry has been added On the debugCORE LPC2292 94 there is also the possibility of connecting the MII interface of LAN91C111 Ethernet controller The following images depict the debugCORE LPC2292 94 with the debugCORE specific expansion Figure 12 debugCORE LPC2292 94 Top
106. per J202 on the phyCORE LPC2292 refer to section 3 1 PHYTEC Messtechnik GmbH 2006 1 658 5 93 phyCORE LPC2292 94 Caution When using the DB 9 socket PIB with the configuration of the phyCORE LPC2292 94 as described above the following jumper settings are not functional and could damage the module Jumper Setting Description JP1 open Pin 2 of DB 9 socket P1B not connected no connection to TxD1 signal from phyCORE LPC2292 94 JP2 closed Pin 9 of DB 9 socket P1B connected with port P1 18 from phyCORE LPC2292 94 JP3 closed Pin 7 of DB 9 socket P1B connected with port P0 22 from phyCORE LPC2292 94 JP4 closed Pin 4 of DB 9 socket P1B connected with port PCSO from phyCORE LPC2292 94 JP5 closed Pin 6 of DB 9 socket P1B connected with MOSIO signal from phyCORE LPC2292 94 JP6 closed Pin 8 of DB 9 socket P1B connected with port PO 21 from phyCORE LPC2292 94 JP7 closed Pin 1 of DB 9 socket P1B connected with port P1 19 from phyCORE LPC2292 94 JP8 open Pin 3 of DB 9 socket P1B not connected no connection to RADI ext signal from phyCORE LPC2292 94 Table 55 Improper Jumper Settings for DB 9 Socket Second RS 232 If an RS 232 cable is connected to P1B by mistake the voltage level on the RS 232 lines could destroy the phyCORE LPC2292 94 94 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 16 3 7 First CAN Interface at Plug P
107. ponding LPC2000 Flash Utility software installed on the PC allows for on chip Flash programming with application code via an RS 232 interface In order to start the ISP command handler on the phyCORE LPC2292 94 port P0 14 of the microcontroller must be connected to a low signal level at the time the Reset signal changes from its active to the inactive state This is achieved by applying a high level signal at pin X700C9 BOOT of the phyCORE LPC2292 94 A transistor circuitry connects P0 14 to GND as long as the BOOT pin is high An on board pull up resistor R213 ensures a high level at P0 14 if the BOOT signal is not active Refer to the Philips LPC229x User Manual section 20 for more details The phyCORE Carrier Board HD200 provides two different options to activate the ISP mode 1 The Boot button S_1 can be connected to VCC via Jumper JP28 which is located next to the Boot and Reset buttons at S_1 and S_2 This configuration enables start up of the ISP command handler if the Boot button is pressed during a hardware reset power on Jumper Setting Description JP28 6 8 Boot button in conjunction with Reset button or and connection of the power supply starts the ISP mode on 3 4 the LPC2292 94 Table 48 28 Configuration of the Boot Button 86 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 2 The Boot input of the phyCORE LPC2292 94 can also be per
108. ponding controller signals are available as standard I O pins at X700B47 X700A48 and X700B3 The following configurations are possible Signal Configuration J608 J609 J610 Port pins P02 P03 P015 closed closed closed configured as interface signals Port pins P02 P03 P015 available open open open as standard I O pins Default setting Table 26 7608 J609 J610 Interface Configuration 3 18 J611 7612 J613 J614 SPIO Interface Jumpers J611 through J614 connect the SPIO interface signals of the microcontroller to the on board SPI bus The on board EEPROM U607 is connected to the SPI bus If the jumpers remain open then the applicable controller pins P04 P05 P06 and P10 can be used with their alternative functions at phyCORE connector pins X700B48 X700A49 X700A50 and X700C13 The SPI interface signals are available at X700C26 X700C28 X700D27 and X700D28 The following configurations are possible Function J611 J612 7613 764 on board SPIO bus connected closed closed closed closed SCLKO PCSO MISOO MOSIO on board SPIO bus disconnected open open open open Default setting Table 27 J611 J612 J613 J614 SPI Interface Signal Configuration 40 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers 3 19 J615 CAN Bus Level Configuration Jumper J615 is used for configuration of the CAN level power supply on the CAN tr
109. pply voltage use only with other CAN transceivers devices Default setting Table 29 J616 J617 CAN Transceiver VCC at Pin 5 42 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers 3 21 J618 VDD V3V3 Supply Control Jumper J618 can be used to directly connect the VDD_3V3V on board main supply voltage with the external VCC voltage In normal operation the FET switch Q600A controls the VDD_3V3V connection to VCC Jumper J618 should remain open The following configurations are possible VDD_V3V3 Supply Control J618 VDD_V3V3 supply voltage is switched via open FET Q600A VDD_V3V3 supply voltage directly derived closed from VCC Default setting Table 30 J l8 VDD_V3V3 Supply Control 3 22 J619 J620 SPI Master Slave Selection Jumpers J619 and J620 are used to configure the SPI interface mode If both jumpers remain open then both SPI interfaces operate in Master mode The SPI interfaces will operate in Slave mode if the corresponding jumpers are closed The following configurations are possible SPI Master Slave Mode Selection J619 J620 SPIO operates in Master mode after RESET open SPIO operates in Slave mode after RESET closed SPII operates in Master mode after RESET open SPII operates in Slave mode after RESET closed Default setting Table 31 J619 J620 SPI Master Slave Selection PHYTEC Messtechnik Gmb
110. ransceiver and opto coupler on the Carrier Board disconnected from local GND potential JP29 closed Supply voltage for on board voltage regulator from pin 9 of DB 9 plug P2A JP39 see Table 60 CAN bus supply voltage reduction for CAN circuitry Table 65 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board with Galvanic Separation 1 Please make sure the CAN transceiver on the phyCORE LPC2292 94 is not populated and Jumpers J603 and J605 are closed refer to section 3 14 for details 104 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board 5 4 9 Pin 9 8 3 7 Pin 3 Pin 7 2 6 Pin 2 1 Pin 6 VCAN 1 galvanically separated 1 galvanically separated VCAN Figure 29 Pin Assignment of the DB 9 Plug P2B CAN Transceiver on Carrier Board with Galvanic Separation PHYTEC Messtechnik GmbH 2006 1 658 5 105 phyCORE LPC2292 94 Caution When using the DB 9 plug P2B as second CAN interface and the CAN transceiver on the Carrier Board with galvanic separation the following jumper settings are not functional and could damage the module Jumper Setting Description JP30 closed Pin 8 at P2B is connected with TxD1_ext from the phyCORE LPC2292 94 JP33 1 2 Pin 2 at P2B is connected with RxD1_ext from the phyCORE LPC2292 94 2 4 Pin 2 at P2B is conne
111. ration details via predefined EEPROM contents J509 closed LAN 91C111 nLNK pin tied open LAN 91C111 nLNK pin not to GND LINK_ON bit in connected LINK_ON bit in the the EPH status register is set EPH status register is set to 0 to 1 J600 1 2 P020 on the uC freely 243 P020 used for enabling resp available as standard I O at disabling the CAN transceiver Molex pin X700A4 U605 connected to INH J601 1 2 P019 on the uC freely 243 P019 used for enabling resp available as standard I O at disabling the CAN transceiver Molex pin X700C19 U606 connected to INH input J602 open CAN signal generated closed signal directly by CAN transceiver U605 connected with uC port TD1 and only if CAN transceiver U605 populates the module available as CAN TTL signal an X700D21 for connection to external CAN transceiver only in connection with unpopulated U605 PHYTEC Messtechnik GmbH 2006 L 658e 5 21 phyCORE LPC2292 94 Default Setting Alternative Setting J603 open 2 signal generated closed 2 signal directly by CAN transceiver U606 connected with uC port P024 only if CAN transceiver and available as CAN TTL U606 populates the signal an X700C18 for module connection to external CAN transceiver only in connection with unpopulated 0606 J604 open CAN_LI signal generated closed CAN_LI signal directly by CAN transceiver U
112. ser s responsibility to ensure sufficient SRAM power supply during runtime The optional battery required for the RTC buffering refer to section 10 is available through PHYTEC order code BL 011 16 3 13 DS2401 Silicon Serial Number Communication to a DS2401 Silicon Serial Number can be imple mented in various software applications for the definition of a node address or as copy protection in networked applications The DS2401 can be soldered on space U10 or U9 on the Carrier Board depending on the type of device packaging being used The Silicon Serial Number Chip mounted on the phyCORE Carrier Board HD200 can be connected to port pin 9 of the LPC2292 94 available at GPIO1 JP19 closed Jumper Setting Description JP19 closed Port pin P0 9 GPIO1 of the LPC2292 94 is used to access the Silicon Serial Number Table 77 JP19 Jumper Configuration for Silicon Serial Number Chip 118 PHYTEC Me technik GmbH 2006 L 658e 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board not connected NUMPORT Port P0 9 JP19 Figure 32 Connecting the 052401 Silicon Serial Number ph NET Nummernehip Bottom View Wu 24 Pin Description Pin 1 Ground Pin 2 Data Pin 3 No Connect Pin Assignment Figure 33 Pin Assignment of the DS2401 Silicon Serial Number 16 3 14 Pin Header Connector X4 The pin header X4 on the Carrier Board enables connec
113. stechnik GmbH 2006 L 658e_5 33 phyCORE LPC2292 94 Ethernet Controller Ready Signal J503 not connected to the LPC2292 94 P018 available as open standard I O pin connects to PO18 of the microcontroller closed Default setting Table 16 J503 Ethernet Ready Signal Configuration LAN_IRQ Pull up Configuration J504 LAN_IRQ signal not connected to an additional 10k open pull up resistor to VDD_V3V3 LAN_IRQ signal is connected to an additional 10k pull closed up resistor to VDD_V3V3 Default setting Table 17 J504 Ethernet LAN IRQ Pull up Configuration The LAN91C111 Ethernet controller provides 4 configuration inputs IOSO IOS2 and ENEEP to enable access to the serial EEPROM and use predefined EEPROM configurations The corresponding Jumpers J505 J507 and J508 connect these inputs to GND level when closed LAN91C111 Configuration J505 J506 J507 1052 IOS1 1050 IOSx signal LAN 91C111 connected open open with internal pull up to VDD_V3V3 configuration via predefined EEPROM contents IOSx signal on LAN 91C111 connected closed closed closed to GND see data sheet for details Default setting Table 18 1505 J506 J507 Ethernet EEPROM Configuration 34 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers Ethernet EEPROM Enable Configuration J508 ENEEP signal on LAN 91C111 connected with
114. stions for Improvement Document phyCORE LPC2292 94 Document number L 658e_5 July 2006 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 Me technikGmbH 2006 1 658 5 Published by L Me technik GmbH 2006 Ordering No L 658e_5 Printed in Germany
115. t relevant for the basic functioning of the phyCORE LPC2292 94 The phyCORE LPC2292 94 offers the following features subminiature Single Board Computer 60x 53 mm achieved through modern SMD technology populated with the Philips LPC2292 94 microcontroller TQPF 144 packaging improved interference safety achieved through multi layer PCB technology and dedicated Ground pins controller signals and ports extend to two 100 pin high density 0 635 mm Molex connectors aligning two sides of the board enabling it to be plugged like a big chip into target application 32 bit demultiplexed bus mode max 60 MHz clock frequency ca 50 ns instruction cycle extern ca 10 ns internal Flash 1 5 Gbyte external address space 2 MByte up to 16 MByte on board Flash on board Flash programming no dedicated Flash programming voltage required through use of 3 3 V Flash devices 1 MByte up to 8 MByte RAM on board max 1 MByte at 0 wait states up to two CAN transceivers Infineon TLE6250V33 RS 232 transceiver for two serial interfaces optional SMSC 91C111 Ethernet controller with EEPROM 2 kByte up to 8 kByte SPI EEPROM Real Time Clock with internal quartz can be battery buffered up to two free microcontroller Chip Select signals if optional Ethernet controller is not populated Please contact PHYTEC for more information about additional module configurations PHYTEC Messtechnik GmbH 2006 L 658e 5 Introduction
116. ta valid reception MII PHY input 10 LAN RX ER Code error detection by PHY input 11 LAN RX25 Receive clock input from MII PHY 12 LAN TX25 Transmit clock input from MII PHY 13 LAN TXEN Output to MII PHY 14 LAN TXDO Transmit data nibble to MII PHY output 15 LAN TXDI Transmit data nibble to MII PHY output 16 LAN TXD2 Transmit data nibble to MII PHY output 17 LAN TXD3 Transmit data nibble to MII PHY output 18 LAN COL Collision detect input from MII PHY 19 LAN CRS Envelope of packet reception from PHY 22 23 24 GND Ground Table 44 LAN MII Connector at X500 72 PHYTEC Me technik GmbH 2006 1 658 5 Technical Specifications 14 Technical Specifications The physical dimensions of the phyCORE LPC2292 94 are represented in Figure 14 The module s profile is 7 2 mm thick with a maximum component height of 2 6mm on the bottom connector side of the PCB and approximately 3 0 mm on the top microcontroller side The board itself is approximately 1 6 mm thick ka 4760 mm 60 00 mm 6 04 mm 92 70 mm c N xt 00 90 mm 2 0 90 mm 3 00 mm 46 48 mm Zz 00 0mm 0 70 mm 0 2 70 mm Figure 14 Physical Dimensions PHYTEC Messtechnik GmbH 2006 L 658e_5 73 phyCORE LPC2292 94 Additional specifications Dimensions Weight Storage temperature Operating temperature e Humidity Operating volta
117. te per shape closed open 4 MByte per shape open closed Not permitted closed closed Default setting Table 8 J208 J209 Flash Memory Size Configuration 28 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers 3 7 J210 J211 RAM Size Configuration The phyCORE LPC2292 94 can be populated with three different RAM memory sizes per shape U400 thru U403 The size of the device must be configured to ensure linear addressing of the entire RAM bank Jumpers J210 and J211 are used to select the size of the memory device The on board CPLD reads the signal level on the applicable input pins and configures the individual Chip Select signals for the RAM devices accordingly Note Jumpers J210 and J211 are configured at time of delivery of the phyCORE LPC2292 94 according to the choosen memory configuration Therefor these jumpers must not be altered by the user The following configurations are possible RAM Memory Size J210 J211 512 kByte per shape open open 1 MByte per shape closed open 2 MByte per shape open closed Not permitted closed closed Default setting Table 9 J210 J211 RAM Memory Size Configuration PHYTEC Messtechnik GmbH 2006 L 658e_5 29 phyCORE LPC2292 94 3 8 J300 Flash Ready Busy Configuration The state of the Flash device can be queried during a programming cycle by using the Flash s Ready Busy signal To accomplish this the Ready Busy signal
118. tion of an optional modem power supply Connector X4 supplies 5 V at pin 1 and provides the phyCORE Carrier Board HD200 GND potential at pin 2 The maximum current draw depends on the power adapter used We recommend the use of modems with less than 250 mA current draw PHYTEC Messtechnik GmbH 2006 1 658 5 119 phyCORE LPC2292 94 120 PHYTEC Me technik GmbH 2006 L 658e 5 Ethernet Port 17 Ethernet Port The phyCORE Carrier Board HD200 provides a 10 pin header connector at X7 for mounting the PHYTEC Ethernet transformer module The optional add on module is available through PHYTEC order code EAD 003 This allows for direct connection of the phyCORE LPC2292 94 with populated Ethernet controller mounted on a Carrier Board HD200 to 10 100Base T network Figure 34 Ethernet Transformer Module Connector The pinout for the Ethernet transformer connector is shown below Pin Function Note 1 ETH_LanLED Make sure JP37 on the Carrier Board is closed at position 1 2 2 LinkLED Make sure JP38 on the Carrier Board is closed at position 1 2 3 VCC 4 ETH_TxD 5 ETH_TxD 6 GND 7 ETH_RxD 8 ETH_RxD 9 GND 10 VCC Table 78 Ethernet Transformer Connector Pinout 1 Note New PCM 997 V3 PCB revision 1179 6 supports 100 Mbit s Ethernet transmission PHYTEC Messtechnik GmbH 2006 1 658 5 121 phyCORE LPC2292 94 Starting with P
119. transceiver U606 always active don t care 1 2 CAN transceiver U605 mode is don t care 2 3 controlled via port P019 on the LPC2292 94 microcontroller Default setting Table 21 J600 J601 CAN Transceiver Activation Jumper J616 is used to supply power to the CAN transceivers U605 and U606 Routing the VDD_V3V3 supply voltage to pin 5 of the relevant CAN transceiver is only required if the TLE 6250V3V3 populates the phyCORE module If the Philips 82C251 CAN transceiver is populated the jumper must be open 36 PHYTEC Messtechnik GmbH 2006 1 658 5 Jumpers The following configurations are possible connected to 3 3 V supply voltage VDD_V3V3 use only with 82C251 devices CAN Transceiver Supply Configuration J616 Pin 5 on CAN transceivers U605 and U606 connected closed to 3 3 V supply voltage VDD_V3V3 use only with TLE6250V33 devices Pin 5 on CAN transceivers U605 and U606 not open Default setting Table 22 7616 CAN Transceiver Supply Configuration 3 14 J602 J603 7604 J605 CAN Interfaces Two CAN interfaces are provided by the phyCORE LPC2292 94 The CAN signals extend to the two TLE6250V33 CAN transceivers at U605 and U606 The CAN transceivers generate the corresponding CAN CAN L1 CAN H2 and CAN L2 signals These signals can be directly connected to a CAN dual wire bus In order to use external opto isolated transceivers direct access to the CANIRx C
120. yCORE LPC2292 94 is not populated and Jumpers J603 and J605 are closed refer to section 3 14 for details 102 PHYTEC Me technik GmbH 2006 1 658 5 The phyCORE LPC2292 94 on the phyCORE Carrier Board Caution When using the DB 9 connector P2B as second CAN interface and the CAN transceiver on the Carrier Board the following jumper settings are not functional and could damage the module Jumper Setting Description JP30 closed Pin 8 at P2B is connected with TxD1_ext from the phyCORE LPC2292 94 JP33 1 2 Pin 2 at P2B is connected with RxD1_ext from the phyCORE LPC2292 94 2 4 Pin 2 at P2B is connected with CAN_L2 RD2 from the on board CAN transceiver on the phyCORE LPC2292 94 JP34 2 3 Pin 7 at P2B is connected with CAN_H2 TD2 from the on board CAN transceiver on the phyCORE LPC2292 94 JP14 1 2 Input at opto coupler U6 the Carrier Board is connected to P1 21 of the phyCORE LPC2292 94 243 Input at opto coupler U6 on the Carrier Board is connected to A23 of the phyCORE LPC2292 94 open Input at opto coupler U6 on the Carrier Board not connected JP15 1 2 Output at opto coupler U7 on the Carrier Board is connected to P1 20 of the phyCORE LPC2292 94 2 3 Output at opto coupler U7 on the Carrier Board is connected to A20 of the phyCORE LPC2292 94 open Output at opto coupler U7 on the Carrier Board not connected JP13 1222 Supply voltage for CAN transceiver and opto coupler on the

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