The key component of 8072
Contents
1. Offset Read BASE Offset Address Write BASE Offset Address 0 Clear interrupt input 0 ClrO N A 1 Clear interrupt input 1 Clrl N A 2 Clear interrupt input 2 Clr2 N A 3 Clear interrupt input 3 Clr3 N A 4 Clear interrupt input 4 Clr4 N A 5 Clear interrupt input 5 Clr5 N A 6 Clear interrupt input 6 Clr6 N A 7 Clear interrupt input 7 Clr7 N A 8 Read Rising Enable Register Set Rising Enable Register Er7 Er6 Er5 Er4 Er3 Er2 Er1 Er0 Er7 Er6 ErS Er4 Er3 Er2 Er1 Er0 D7 Er7 DO Er0 D7 Er7 DO Er0 9 Read Falling Enable Register Set Falling Enable Register Ef7 Ef6 Ef5 Ef4 Ef3 Ef2 Ef1 Ef0 Ef7 Ef60 Ef5 Ef4 Ef3 Ef2 Ef1 EfO D7 Ef7 DO Ef0 D7 Ef7 DO Ef0 OX0A Read Global Interrupt Status Gi Force Interrupt to LOW state about DO Gi 0 1uS ClrGi Ox0B Read Rising Interrupt Status N A Qr7 Qr6 Qr5 Qr4 Qr3 Qr2 Qr1 Qr0 Ox0C Read Falling Interrupt Status N A Qf7 Qf6 Qf5 Qf4 Qf3 Qf2 Qf1 Qf0 Ox0D Read Digital Input N A D17 D16 D15 D14 D13 D12 D11 Di0 The BASE address for the 8000 series is as follows Slot0 BASE 0x80 Slotl BASE 0xA0 Slot2 BASE 0xC0 Slot3 BASE 0xE0 Slot4 BASE 0x140 Slot5 BASE 0x160 Slot6 BASE 0x180 Slot7 BASE 0x1a0 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 1 5 Isolated or TTL Input The input signal can be either isolated or TTL input as follows E i 8048 8 ch interrupt JP1 JP8 in the DOWN position will select the isolated input 12. main c gt main program eo JSRI c gt designed for slotO and slot1 e ISR2 c gt designed for slot0 slot1 slot2 slot3 The user can modify ISR1 c ISR2 c to fit any special requirements 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 18 2 2 Demo1 Step 1 set JP1 to be either isolated or TTL input Step 2 install the I 8048 to the first slot slotO Step 3 apply the input signal to In0 In0 for isolated input or In0 TTL GND for non isolated input Step 4 download demol exe to the I 8048 Step 5 for rising edge testing press 1 for falling edge testing press 2 for rising and falling edge testing press 3 The following diagram shows that no I 8048 was detected in slot0 lease install one 8648 in Slot an not find a 8648 in SlotB The following diagram shows the rising edge test press 1 i 8666 gt demo1 Please install one 8648 in Slot This demo program is designed for channel_ Please select the active mode for channel_ lt i rising 2 falling 3 rising amp falling others disable gt gt 1 rising 0 0 0 0 a Ds Os Us 1 5 B A A A A A A A A A i 2 2 2 2 ee ee Se Oe ee ee TA TL Seegeeaeoooooeoeeoa00d MONO A AY ASA ooo oo oo TIME A Seegeeoeoooooeoogod Seegeeooooooeooo i s tee SS ee Se ee ee oa oo o is IA E A eS A Seegegeaeaoooooeeoa0g0o Sei See SOR OW oe TA A sao ooo o io IC A TO E AC A ooo ooo o is INIA MR O ST A 500005000 JC es
3. 8 The TTL input block diagram is as follows JP1 JP8 in the UP position will select the TTL input 1 8 JP1 Select Input 0 JP2 Select Input 1 O JP3 Select Input 2 JP4 Select Input 3 JPS Select Input 4 P7 Select Input6 JP8 Select Input 7 Isolated input default TTL input I 8048 Hardware User s Manual Aug 2004 Rev 1 0 7 1 6 BIOS Update The I 8048 is supported by MiniOS7 8K040330 IMG 2004 03 30 or later The BIOS can be updated as follows Step 1 upload 8K040330 IMG Step 2 type bios1 then press enter 1 8 666 gt i 8666 gt upload Press ALT_E to download filet Input filename 8k646336 img Load file 8k646336 img crc 47B3 66661 Send file info total 256 blocks Block 256 Transfer time is 6 953606 seconds CRC16 6B43 4 666 FFFE 7188 i 8666 gt bios1 MiniOs for 8666 Ver 2 606 661 date 63 36 2004 Checking CRC 16 0K Write to Flash memory please wait about 18 secs After update finished the system will auto reboot If it take too long please reset by power On Off i 8666 gt Step 3 double check entering the diag exe command i 8000 gt i 8666 gt diag Init pin is Open Sram 128K Flash Memory 256K Manufacturer C2 MKIC gt ID B lt size 256K gt Protect mode x8600006 EEPROM is 24LC16 CPU Am188ES 1 reset by WDT is OK number 4 8048 A du 1 8048 Hardware User s Manual Aug 2
4. be divided into two groups groupl and group2 Group is from slot0 to slot3 and these interrupts are connected to the CPU s int0 to 3 respectively Group2 is from slot4 to slot7 and these interrupts are connected to the NMI of the CPU The I 8048 can only be installed in slot0 slot3 Demo programs to 6 below are designed for Group1 Refer to these demo programs for additional coding information The sample libraries are as follows O srl c in demol 3 and 4 is designed for slot0 only O sr2 c in demo is designed for slot1 only O isr3 c in demo is designed for slot0 and slotl e isr4 c in demo6 is designed for slot0 1 2 and 3 New 8000L lib 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 13 1 10 Clear Interrupt Referring to Section 1 2 the interrupt signal will be latched until a clear interrupt signal is active Refer to Section 1 4 for the addresses of clear interrupt signals The global interrupt Gi is shared by all eight signals If any single interrupt does not clear to LOW then all interrupts will be blocked and the CPU will not be able to receive any further interrupts That is to say the programmer should ensure that the code clears the interrupt and make sure that the global interrupt Gi is LOW in normal conditions The global interrupt Gi can be read back from BASE 0x0A Writing to BASE 0x0D will force the Gi to LOW for about 0 1uS The Gi will return to its previous st
5. s Manual Aug 2004 Rev 1 0 2 1 1 Pin Assignment for the l 8048 The pin assignment for the I 8048 is as follows 8048 DODDDDDDODDODODODDDODDODD Pin 1 TTL GND ground for non isolated input signals Pin 2 N A Pins 3 18 8 channel digital input Pins 19 and 20 isolated power supply 5V 200mA max 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 3 1 2 1 8048 Block Diagram The signal flow block diagram is as follows Falling D flipflop i 8048 8 ch interrupt 1 Rising D flipflop A TTL GND In0 In0 Inl Inl In2 In2 In3 In3 In4 isi In4 i In5 In5 i In6 In6 In7 In7 Falling 2 D flipflop Interrupt CPU 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 4 1 3 8000 Interrupt Block Diagram The 8000 series interrupt system block diagram is as follows Slot0 s Int Slot1 s Int Slot2 s Int Slot3 s Int D filpflo Slot4 s int pee IntCir4 gt Cik Q Slot5 s int lintCir5 It is difficult for the interrupt mechanism of the I 8048 and the CPU s NMI to work together properly so the I 8048 must be installed in slot0 slot1 slot2 or slot3 only 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 5 1 4 1 8048 I O Control Register The I O control registers are as follows
6. 004 Rev 1 0 8 1 7 Digital Input amp LED The LED to Digital Input mapping is as follows power LED DJ i 8048 HOOUUUUU When all the pins are open all LEDs will be ON for both isolated or TTL input The high low status of the digital input is as follows JPn selected isolated input Digital Input LED Input is OPEN High OFF Input is 3 5 30V Low ON Input is 0 1V High OFF NOTE when applying an isolated HIGH voltage the digital input will be LOW JPn selected TTL input Digital Input LED Input is OPEN High OFF Input is 2 5V High OFF Input is 0 0 8V Low ON NOTE when applying a TTL HIGH voltage the digital input will be HIGH 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 9 Referring to Section 1 4 the address of digital input is BASE 0x0D so the DIAG command can be used to determine the I 8048 and INP commands to read the digital input as follows i 8666 gt diag Init pin is Open Sram 128K Flash Memory 256K Manufacturer C2 lt MXIC gt ID B lt size 256K gt Protect id 1515151515 EEPROM is 24LC16 Am188ES 1 reset by WDT ASCKEY is OK Slot number 4 44 HHH HHH HHH E a t i 80 gt inp 8d port 668D data 29 i 860 gt inp 8d port 668D data D7 i 8000 gt In this example there is one I 8048 module installed in the first slot slot0 the address of the digital input 0x80 0x0d 0x8D The first re
7. 1 8048 Hardware User s Manual Warranty All products manufactured by ICP DAS are warranted against defective materials for a period of one year from the date of delivery to the original purchaser Warning ICP DAS assumes no liability for damages consequent to the use of this product ICP DAS reserves the right to change this manual at any time without notice The information furnished by ICP DAS is believed to be accurate and reliable However no responsibility is assumed by ICP DAS for its use nor for any infringements of patents or other rights of third parties resulting from its use Copyright Copyright 2004 by ICP DAS All rights are reserved Trademark The names used for identification only maybe registered trademarks of their respective companies 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 1 1 General Introduction The I 8048 module is an 8 channel digital input module designed for interrupt applications The key features of the I 8048 are as follows 1 Input Signal isolated or non isolated TTL jumper selectable 2 Logic high level Isolated 4 30V recommended limit impedance when using 12 24V input Non isolated TTL 2 5V 3 Logic low level Isolated 0 1V Non isolated TTL 0 0 8V Isolated voltage 2000V Built in isolated power supply 5V 200mA max Rising Falling edge interrupt programmable Must be installed in slot0 slot1 slot2 or slot3 A ES 1 8048 Hardware User
8. 8 for rising edge testing press 1 for falling edge testing press 2 for rising and falling edge testing press 3 The testing diagram is similar to Section 2 2 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 21 2 4 Demo3 Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 set JP1 and JP2 to be either isolated or TTL input install the I 8048 to the second slot slot1 apply the input signal to In0 In0 In1 In1 for isolated input or In0 In1 TTL GND for non isolated input download demo3 exe to the I 8048 channel0 setting for rising edge testing press 1 for falling edge testing press 2 for rising and falling edge testing press 3 channel setting for rising edge testing press 1 for falling edge testing press 2 for rising and falling edge testing press 3 Note the settings for channel0 and channell can be different The testing results diagram is similar to Section 2 2 I 8048 Hardware User s Manual Aug 2004 Rev 1 0 22 2 5 Demo4 Step 1 set JP1 JP8 to be either isolated or TTL input Step 2 install the I 8048 to the second slot slot1 Step 3 apply input signals to In In for isolated input or In TTL GND for non isolated input Step 4 download demo4 exe to the I 8048 Note the demo will enable both rising falling edges of all channels The testing results diagram is similar to Section 2 2 2 6 Demo5 This demo is similar to demo4 c except t
9. Return probe High Voltage probe Figure Block Diagram I 8048 Hardware User s Manual Aug 2004 Rev 1 0 15 1 12 ESD Test Walking across an insulated floor surface can cause a person to become electrostatically charged and over a period of time it is possible for the human body to be charged to a capacity of several kilovolts The TRANSIENT 2000 Tester can simulate the transients of human body electrostatic discharge ESD and was used to simulate ESD in order to test the I 8048 First the ESD test file ESDTest exe was downloaded to an I 8411 module and executed The EUT Equipment Under Test is the I 8048 If static electricity causes a shock to the I 8048 module the test program will display an error message on the PC monitor There are two types of ESD test The first is to test the connection shock at 4K V ten times and the second is to test the air shock at 8K V ten times Both tests were performed on the same terminal There are 20 metal points on the module that can be touched and each one was tested in turn In all cases the testing program returned negative results showing that there were no adverse effects to either the I 8411 Embedded Controller or the I 8048 module so the I 8048 ESD test proved to be very successful Shock Running status 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 16 2 Demo Programs 1 demol e The I 8048 is installed in the first slot
10. SE 8 and BASE 9 can enable a rising and falling edge interrupt Some code examples are as follows Write to Write to Operation BASE 8 BASE 9 0 0 Disable all interrupts 1 0 Enable rising edge interrupt of channel_0 0 1 Enable falling edge interrupt of channel_0 1 1 Enable rising and falling edge interrupt of channel_0 2 0 Enable rising edge interrupt of channel_1 0 2 Enable falling edge interrupt of channel_1 2 2 Enable rising and falling edge interrupt of channel_1 4 4 Enable rising and falling edge interrupt of channel_2 8 8 Enable rising and falling edge interrupt of channel_3 0x10 0x10 Enable rising and falling edge interrupt of channel_4 0x20 0x20 Enable rising and falling edge interrupt of channel_5 0x40 0x40 Enable rising and falling edge interrupt of channel_6 0x80 0x80 Enable rising and falling edge interrupt of channel_7 Enable rising edge interrupt of channel_1 to 3 and OxOF OxFO gt falling edge interrupt of channel_ 4 to 7 Enable rising edge interrupt of channel_4 to 7 and OxFO OxOF falling edge of channel_ 0 to 3 OxFF 0 Enable rising edge interrupt of channel_1 to 7 0 OxFF Enable falling edge interrupt of channel_1 to 7 OxFF OxFF Enable rising and falling edge interrupt of channel_1 to 7 I 8048 Hardware User s Manual Aug 2004 Rev 1 0 12 1 9 ISR for Slot0 3 Referring to Section 1 3 the interrupt systems of the 8000 series can
11. ading of this digital input is 0x29 and the second reading is 0xD7 The following example shows two I 8048 modules installed in the first and second slots i 8666 gt diag Init pin is Open Sram 128K Flash Memory 256K Manufacturer C2 MRIC gt ID BA lt size 256K gt Protect ii 1515151515 EEPROM is 24LC16 CCPU Am188ES 1 Power ON reset OK 8048 8048 HN IA port 4B8D data 29 i 88BB gt inp ad port BBAD data 8F i 8000 gt 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 10 1 8 Enable Rising Falling Interrupt The digital input signals determined in Section 1 7 can be programmed to interrupt the CPU when their states are changed The possible types are as follows Digital Input Interrupt CPU a a Rising Edge Interrupt Digital Input Interrupt CPU Ooo Falling Edge Interrupt Digital Input Interrupt CPU o Both Edge Interrupt NOTE when referring to Section 1 7 applying isolated HIGH voltage and TTL HIGH voltage the digital input will be different That is to say their rising edge and falling edge are also different The user should be certain of whether the interrupt is rising or falling edge before starting to code the ISR program I 8048 Hardware User s Manual Aug 2004 Rev 1 0 11 Referring to Section 1 4 writing to BASE 8 can enable a rising edge interrupt and writing to BASE 9 will enable a falling edge interrupt Writing to both BA
12. ate after writing This mechanism will ensure that the I 8048 works properly in a shared interrupt system The only way to clear the Gi is to clear all the Qfn and Qrn values listed in Section 1 2 Reading from BASE n will clear both Qfn and Qrn values Refer to Demol Demo6 for more coding examples Notes 1 If any Qfn or Qrn value is HIGH the Gi will be HIGH to block all further interrupts All Qrn values can be read from BASE 0x0B All Qfn values can be read from BASE 0x0C The Gi can be read from BASE 0x0D Reading from BASE n will clear both Qrn and Qfn values to LOW Writing to BASE 0x0D will force the Gi to LOW for about 0 1uS Oy Se ek I 8048 Hardware User s Manual Aug 2004 Rev 1 0 14 1 11 Isolation Voltage Test ICP DAS has a strict and detailed endurance test for withstanding a voltage of 2000V for Smin which was used with the I 8048 As shown in the figure below two cables are connected to the isolation and non isolation input terminals of the Voltage Endurance Tester 1 7122 and the connected with the I 8048 Two types of test modes can be set on the I 7122 The first is a Breakdown test and the second is an Arc test Once the cables are connected the test can be started The voltage endurance test is performed for five minutes and once the success of the test has been determined the test is repeated for verification This test proves that the I 8048 has very high voltage endurance performance
13. es es ee A A Ye ooo ooo oo SQeeeqeeaooooegeqgoge0dS see es es es es ee ss 5000000000000 sys ee ee ee ee A Seeaqeeooooooeeegogo0 see es ee ee ee ee ee ee 5000000000000 p p p p p Jud Jud Jud Jud Jud Jud Jud p Jud Jud Jud Ju MAA SS Soo ooo od 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 19 The following diagram shows the falling edge test press 2 ia oa E al a E el m g E el o i 1 a AAA es hs A A es es A a AAAS SSN A oS e T Ce y h 6 4 4 k E h h E A G G O GOG ene n A n en e n foo an n k O h E k h k k h h G h G G GOG ene n n n en foo n t y y E A A y B G G G G G G GG ss o k h OO D o D a a a a a a a a foo oo g k h h k h h k k h k G G G G GOG MA de a ll paj pa el jo Jl Jo EE EE EE ENE EE EM EE EM EE EE HE HUE EM HUE EM UU T o o a a a a a a a a foo oo g LL EAKA ALLEA AEA K 4 T o o a a a a a a aa a oo oo g LL OOO a o E m l e T Il E EN 2 4 m e m e La m amp e 4 sr fai falling 3 oe o E pa E EN Ey o T E o El a a pH E a a pil a Sees eee Soararn LL ee LRT ooo ooo ooo ooo LO A A A A A A E CO E CO O A E LO AA o CE AE A OR ORR Pi eS a E E Fa a 5 a pa T a Z fap Al a a Al E 1 5 p a i a a ca Al Please Cl rising gt 2 The follo
14. hat there are two I 8048 modules installed in slot0O and slotl respectively 2 7 Demo6 This demo is similar to demo4 c except that there are four I 8048 modules installed in slot0 slot1 slot3 and slot4 respectively 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 23
15. slotO e Only channel_0 is enabled e Enter 0 1 2 or 3 to select the active rising falling edge 2 demo2 e The I 8048 is installed in the second slot slot e Only channel_0 is enabled e Enter 0 1 2 or 3 to select the active rising falling edge 3 demo3 e The J 8048 is installed in the first slot slotO e Channel_O and channel_1 are enabled e Enter 0 1 2 or 3 to select the active rising falling edge 4 demo4 e The I 8048 is installed in the first slot slotO e All channels and both rising falling edge are enabled 5 demo5 e One I 8048 is installed in the first slot slotO e Another I 8048 is installed in the second slot slot1 e All channels and both rising falling edge are enabled 6 demo6 e Four I 8048 modules are installed in slot0 1 2 and 3 e All channels and both rising falling edge are enabled I 8048 Hardware User s Manual Aug 2004 Rev 1 0 17 2 1 Library Files eo 8048 readme txt gt read this file first o 8048 lib 8000_2L lib gt 8000 series library file large model e 8048 lib 8000 H gt 8000_2L lib declaration file Oo 8048 lib 8K040330 IMG gt MiniOS7 image dated 2004 03 30 e 8048 EsdTest gt ESD testing program eo 8048 Demol gt demol Oo aiii nin o 8048 Demo6 gt demo6 The following files can be found in the demo directory O readme txt gt read this file first e demon exe gt execution file that can be download to the 8000 series module n 1 2 3 4 5 6
16. wing diagram shows the test for both rising falling edges press 3 channel_8 channel_ a ey lt c n A i pa lt 4 rl 13 he da n o a pan o E u rl phar select the active mode for others disable gt DONNA AAA AAA pg pen pg pg pg pd pd pg pd pd pd pd p p p pg p pad pad LR 8 OA amp amp amp amp amp amp amp amp amp HH H HR HR HK SSA ooo oo LOA OA OO amp amp amp amp amp amp amp A amp AAA Segeegooeoeooeoeoeeeoood 4 E A 4 4 2 4 4 4 E A A A 4 A A A 4 ooo ooo SSA ooo oo ol LL A A A A A A A A A SSA o ooo A LARA OEA AA OA AA AAA AAA 5000000000000 E A E A A 4 2 6 4 4 4 4 4 4 4 4 amp 4 4 5500000000000 000 SSSssssssssssssssss LL A A A AA A SAS o oo NCAA AAA AAA AA AA 5000000000000 E 4 8 46 2 A 2 4 A 2 8 6 2 6 8 A Q9SSSSSSSSSSSSSsssSsS Al DOI 60 5 4 AR 0 A AAA AA lll dar tarda qa aa Ador de de e oe a a ASA AAA ir ABO DDD A ml ll el ml AN ECC O AC A ee ee ee rising amp falling 3 ng 2 falling daing amp tatting 20 1 8048 Hardware User s Manual Aug 2004 Rev 1 0 2 3 Demo2 Step 1 Step 2 Step 3 Step 4 Step 5 set JP1 to be either isolated or TTL input install the I 8048 to the second slot slot1 apply the input signal to In0 InO for isolated input or In0 TTL GND for non isolated input download demo2 exe to the I 804
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