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1. REQUEST BUS PIPELINE Y BUS GRANT y E ASSERT ADDRESS ACKNOWLEDGE ees RETURN DATA MASTER y ASSERT TRANSFER ACKNOWLEDGE ASSERT BUS BUSY a Tae ASSERT TRANSFER ADDRESS LS ACKNOWLEDGE ASSERT ADDRESS y ALREADY ACKNOWLEDGE DRIVE ADDRESS ASSERTED AND ATTRIBUTES Y y Hat dee leie de il ee ie Ae a en 1 1 EE EEN y RECEIVE DATA MPC500 RD CYC FLOW Figure 4 1 Flow Diagram of a Single Read Cycle Figure 4 2 is a simplified timing diagram of a read cycle MOTOROLA EXTERNAL BUS INTERFACE SIU 4 4 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc wor LY LI LILI LILI LI UU Ld BR EQUEST BUS amp RECEIVE GRANT BB BEGIN DRIVING ADDRESS AND ASSERT TS ADDR amp PIPELINED ADDRESS ATTRIBUTES WR TS AACK RECEIVE AACK COULD STOP DRIVING ADDRESS HERE pata WAIT ONE CLOCK DATA RETURN FOR THE READ TA MPC500 RD CYC TIM Figure 4 2 Example of a Read Cycle 4 3 2 Write Cycle Flow Figure 4 3 is a flow diagram of a single write cycle on the external bus SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 5 Go to www freescale com Freescale Semiconductor Inc MASTER IS BUS GRANTED REQUEST BUS BUS GRANT RECEIVED BUS BEIN
2. 2 PIPE DEPTH 0 1 2 2 MPC500 PIPED BUS TIM Figure 4 4 Example of Pipelined Bus Figure 4 5 illustrates a write access followed by two read accesses on the external bus oan TS wi D R2 WR WI HI R2 a 9 i gt AACK WI HI TA WI R1 R2 CE1 R1 OE1 R1 CE2 WI R2 OE2 R2 WE2 WI ADDR PHASE Wi R1 R2 DATA PHASE Wi R1 R2 EBI PIPE DEPTH 0 1 1 2 2 1 2 1 1 1 MPC500 EBUS WR2RD TIM Figure 4 5 Write Followed by Two Reads on the E Bus Using Chip Selects SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More information On This Product 4 7 Go to www freescale com Freescale Semiconductor Inc 4 5 Bus Cycle Phases The following paragraphs describe the three bus cycle phases arbitration phase ad dress phase and data phase Note that there is no separate arbitration for the address and data buses 4 5 1 Arbitration Phase The SIU supports multiple masters but is optimized for single master systems Each master must have bus request bus grant and bus busy signals Arbitration signals of the masters feed into a central arbiter for arbitration Before the SIU can start an external cycle it must have a qualified bus grant A qual ified bus gran
3. eecceeeeeeeeeeeeeeeeeeeeneeees 7 7 7 5 2 Software Watchdog Control Register Timing Count 0 eeee 7 7 7 5 3 Software Watchdog Register iiaicciccel cccseseewsdctticsetavn ih wentedsceeeeeveeceew cts 7 8 SECTION 8 RESET OPERATION 8 1 ROSEr SOURCES EE 8 1 8 2 e 8 2 8 2 1 External Reset Request FIOW EE 8 2 8 2 2 Internal Reset Request FIOW ee 8 4 SIU MOTOROLA REFERENCE MANUAL For More Information On This Product wil Go to www freescale com Preeaglt sptentier me Continued Paragraph Title Page 8 2 3 Reset Behavior for Different Clock Modes eeeeeeeeeeeeeeeeeeees 8 6 8 3 Configuration During Reset E 8 7 8 3 1 Data Bus Configuration Mode EEN 8 7 8 3 2 Internal Default Mode sssessenccncceceeeeeeeeeeeeeeeeeeeeeseeeeeeeessnee 8 8 8 3 3 Data Bus Reset Configuration Word cc cceeeeeeeeeeeeeeeeeeeeeeeeneeees 8 8 8 4 Poweron ROSO ebe EE 8 10 SECTION 9 GENERAL PURPOSE UO 9 1 Geleet EE 9 1 9 2 EE EE 9 2 9 3 PORTS E and Bsa ee 9 3 9 4 Ports e dK an D NEE 9 4 9 5 Port Replacement Unit PRU Mode 9 5 SECTION 10 INTERRUPT CONTROLLER AND PORT Q 10 1 Interrupt Controller Operation ceceeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeseeeeeeneeeees 10 1 10 2 Interrupt SOUICOS ee ee ee 10 2 10 2 1 External Interrupt Requests a 10 5 10 2 2 Periodic Interrupt Timer Interrupts AAA 10 5 10 2 3 On Chip Peripheral IMB2 Interrupt Requests seeeeeeeeee
4. cceeeceeeeeeeeeeeeeeeeeeeeeeeeeeees 7 2 8 1 External Reset Request Flow EE 8 3 8 2 Internal Reset Request FIOW EEN 8 5 10 1 Interrupt Structure Block Diagram AEN 10 2 10 2 Interrupt Controller Block Diagram ccccccccceeeeeeeeeeeeeeeeeeeeteeeeeeneeees 10 3 10 3 Port Q IRQ Functional Block Diagoram 10 4 10 4 Time Multiplexing Protocol For IRQ PINS cecceeeeeeeeeeeeeeeeeeeeeeeeneeees 10 5 SIU MOTOROLA REFERENCE MANUAL ix For More Information On This Product Go to www freescale com We Gd alen gi Figure Su i Page MOTOROLA SIU x For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semigenquctor Inc Table Title 1 1 SIU Address Map EE 1 2 POUPAGGRGSS E 2 1 EBI Pin EENEG eege ait hee hn il etal 2 2 Byte Enable Encodings AAA 2 3 Address Type Definitions c 0acuien ncaa 3 1 SIUMCR RT le EE 3 2 MEMMAP Bit SettiNg Sinnani 3 3 PCUMCR Bit Settings EE 3 4 Internal Memory Array Block Mapping cceeeeeeeeeeeeeeeeeees 3 5 Memory Accesses in Case of Memory Mapping Conflicts 4 1 EBI Signal Descriptions AEN 4 2 Address Type ee ne EE 4 3 Byte Eelere Egeter dEr 4 4 Signals Driven at Start of Address Phase 4 5 Burst Access Address VWrappimg 4 6 SPECADDR Ed EE 4 7 SPECMASK Bit Settings ENEE 4 8 Example Speculative Mask Values n00nnn0n00000eneneeeeeennnnnnnennno 4 9 EBI Read and Write Access to 16 Bit Portes 4 10 Cyc
5. Chip Select Function Alternate Pin Function in Chip Select Mode Function CS5 ADDRS5 PA5 Can be CE WE or OE of EPROMs or SRAMs CS6 ADDR6 PA6__ Can be WE or OE of EPROMs or SRAMs CS7 ADDR7 PA7_ Can be WE or OE of EPROMs or SRAMs CS8 ADDR8 PBO_ Can be WE or OE of EPROMs or SRAMs CS9 ADDR9 PB1 Can be WE or OE of EPROMs or SRAMs CS10 ADDR10 PB2 Can be WE or OE of EPROMs or SRAMs CSTT ADDR11 PB3 Can be WE or OE of EPROMs or SRAMs NOTE During the first two clock cycles of power on reset the state of the pins listed in Table 5 1 is unknown When a chip select is configured as a chip enable of a memory or I O device the MCU asserts the chip select when it drives the address onto the external bus For non pipe lineable devices the CE is asserted until the access is completed For pipelineable de vices when CE is asserted the device should clock in the address at the rising edge of the clock Note that devices that the chip select unit regards as pipelineable are al ways synchronous The WE signal is used during write accesses When a chip select is configured as a write enable signal of a memory or I O device the MCU asserts the chip select as it drives data onto the external bus to signal the external device to strobe in the data For synchronous devices if WE is asserted the device should clock in the data at the rising edge of the clock The OE signal is used during read accesses When the MCU asser
6. 4 13 Show Cycles 4 18 Internal bus cycles that are echoed on the external bus are referred to as show cycles By providing access to bus cycles that are not visible externally during normal opera tion show cycles allow a development support system to trace the flow of a program The LSHOW field in the SIUMCR can be programmed to cause the EBI to echo certain or all internal L bus cycles on the external bus Likewise the ISCTL field in the ICTRL register instruction bus control register SPR 148 in the RCPU can be programmed to cause the EBI to echo certain or all internal l bus cycles on the external bus The l bus show cycles are always address only cycles They do not wait for the inter nal transaction to complete L bus show cycles have both address and data and ap pear on the external bus after the internal cycle is completed Aborted L bus cycles do not result in a show cycle The load store unit of the proces sor may abort the cycle when the previous cycle terminates with a transfer error or when an exception occurs during the current cycle MOTOROLA EXTERNAL BUS INTERFACE SIU For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Aborted I bus cycles do result in a show cycle The processor may abort an I bus cy cle when it encounters a branch it aborts the fetch just starting on a wrong path In addition the processor aborts the cycle on a cache hit
7. IS LOO LOL RST H NO NOTE INT_RST IS EITHER LOO OR LOL OR JTAG OR SWDOG TIMER OR CHECKSTOP RESET REQUEST y RESET CLOCKS AND PLL REQUEST THE INTERNAL BUSES WAIT FOR 32 CLOCKS OR EBI IDLE INDICATION IS CNT 32 OR EBI IDLE ASSERT RESETOUT AND INTERNAL RESETS START THE COUNTER WAIT FOR CNT 15 AND WAIT FOR PLL TO LOCK THIS STATE DEPENDS ON PLL MODE ican CONFIG IS CNT 15 OR PLL LOCKED RELEASE RESETOUT AND INTERNAL RESET START THE COUNTER CONTINUE REQUESTING BUSES NO RELEASE BUS REQUESTS AND GO TO IDLE MPC500 IN RESET FLOW Figure 8 2 Internal Reset Request Flow SIU REFERENCE MANUAL RESET OPERATION For More Information On This Product MOTOROLA 8 5 Go to www freescale com Freescale Semiconductor Inc The SIU enters internal reset flow when an internal reset request is issued due to one of the following causes loss of clock loss of PLL lock software watchdog time out entry into checkstop state or assertion of a JTAG reset request If the source of reset is either loss of oscillator or loss of clock the SIU resets the clocks and the PLL imme diately For other reset sources the SIU does not reset the clocks or the PLL When the internal reset request signal is asserted the SIU attempts to complete the current tra
8. Bit s Name Description 21 22 BYTE Byte enable This field applies to pins configured as WEs only Specifies for which of the four bytes in a word the WE is asserted If the region can always be written in 32 bit quantity this field can be programmed to any value 00 Byte enable 0 01 Byte enable 1 10 Byte enable 2 11 Byte enable 3 Refer to 5 12 2 Byte Enable Control for more information 23 25 REGION Memory region only applicable when pin is configured to be a WE or OE pin These bits indicate the memory region with which the pin is associated 000 CSBOOT 001 CST 010 CS2 011 CS3 100 CS4 101 CS5 110 Reserved 111 Reserved Refer to 5 5 Chip Select Regions for more information 26 27 _ Reserved 28 31 ITYPE Interface type Indicates the type of memory or peripheral device being controlled Refer to 5 13 Interface Types for details 5 5 Chip Select Regions The SIU supports an address space of 4 gigabytes 277 bytes This space can be di vided into regions Each region can be occupied by one or more chips depending on the output width of each chip Each chip select pin that is programmed as a chip enable defines a separate region Only the CSBOOT and CS 1 5 pins can serve as chip enables All chips within a re gion have a common chip enable signal Each chip select that can be programmed as a chip enable has an associated base address register
9. TA 2 10 4 2 4 9 5 15 delay 5 9 5 15 TADLY 5 9 5 15 TBS 6 16 TEA 2 11 4 2 4 9 4 16 7 5 cycles 4 16 Time base 6 13 clock source 6 16 Time out period PIT 7 3 Transfer acknowledge See TA Transfer error acknowledge See TEA Transfer start See TS TS 2 6 4 1 4 8 UL Unimplemented internal memory accesses 3 7 AN VCO 6 7 VDDKAP1 6 3 SIU REFERENCE MANUAL Vppsn 6 3 VF 2 12 VFLS 2 13 Vsssn 6 3 VSYNC 4 17 IA Wake up request 6 13 6 18 Watchpoint signals See WP WE 5 1 WP 2 13 5 9 5 14 WR 2 5 4 1 4 8 Write cycle 4 5 Write enable See WE Write protection 5 9 5 14 Write read signal See WR WUR 6 13 6 18 X XFCN 2 15 6 3 XFCP 2 15 6 3 XTAL 2 14 6 3 INDEX For More Information On This Product Go to www freescale com MOTOROLA l 5 Freescale Semiconductor Inc MOTOROLA INDEX SIU l 6 For More information On This Product REFERENCE MANUAL Go to www freescale com
10. Reserved 17 21 LBUSOL Interrupt request level for L bus IRQO interrupts 22 26 LBUS1L Interrupt request level for L bus IRQ1 interrupts 27 31 PITIRQL Interrupt request level for PIT interrupts 10 4 Port Q When not used as interrupt inputs the IRQ 0 7 PQ 0 7 pins can be used for digital I O The following registers control port Q operation e Port Q Pin Assignment Register PQPAR allows the user to configure each pin as a digital input digital output edge or level sensitive interrupt request to the CPU or edge or level sensitive interrupt request to the interrupt controller e Port Q Edge Detect Data Register PQEDGDAT contains the following fields Port Q Data Field PQ 0 7 Monitors or controls the state of port Q pins depending on the encoding for each pin in the PQPAR Port Q Edge Detect Status Field PQE 0 7 Monitors when the proper tran sition occurs on a port Q or interrupt request pin 10 4 1 Port Q Edge Detect Data Register The port Q edge detect data register PQEDGDAT consists of the port Q edge detect status PQE 0 7 field and the port Q data PQ 0 7 field Port Q edge status PQE bits indicate when the proper transition has occurred on a port Q pin Each pin can be configured as an interrupt input or as general purpose I O If the pin is configured in the PQPAR as an edge sensitive interrupt request pin then the PQE bit acts as a status bit t
11. aaanssnononnoonnnnnnnnnnnnno 5 26 5 16 3 Synchronous Interface with Asynchronous OE ITYPE 2 5 26 5 16 4 Synchronous Interface With Early Synchronous OE ITYPE 8 5 27 5 16 5 Synchronous Interface With Synchronous OE and Early Overlap ITYPE 9 5 28 5 16 6 Synchronous Burst Interface Auen 5 29 5 17 SUSE e Elle ie KEE 5 32 5 18 Chip Select Reset Operation EE 5 33 SECTION 6 CLOCK SUBMODULE 6 1 Signal Descriptions EE 6 3 6 2 Clock Power Supplies cccccccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeesaaees 6 3 6 3 System Clock Sources ee 6 4 6 4 Phase Locked Loop ircen anem aeaaaee ari aena ie benevonceanetinccdyvencunetanee cs 6 4 6 4 1 Grystal Osellato EE 6 5 6 4 2 Phase Detector ett 6 6 6 4 3 Charge Pump and Loop Filter unn 6 6 6 4 4 NO EE 6 7 6 4 5 Multiplication Factor Divider 0 cccecceeeeeeeeeeeneeeeeeeeeeeeneeeeeeeeeeeeaaees 6 7 6 4 6 Glock Delay tere enee ege 6 7 6 5 CLROUTBrEquency ee de EE 6 8 6 5 1 Multiplication Factor MF Bits c ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenees 6 8 6 5 2 RFD 0 3 Reduced Frequency Divider sssssssneenessennnnnneeerrrnrnesernee 6 9 6 6 Low Power lee 6 11 MOTOROLA SIU VI For More information On This Product REFERENCE MANUAL Go to www freescale com Preeamglepterpgtie Ier Continued Paragraph Title Page 6 6 1 eigene 6 11 6 6 2 lte lee 6 11 6 6 3 lee MOG EN 6 11 6 6 4 Sleep Mode anirnar E aE Ee NE d 6 11 6 6 5 Exiti
12. 2 2 9 1 Interrupt Requests IRQ 0 7 Input only Module ER State Meaning Asserted Indicates an external interrupt is being request ed with a request level corresponding to the IRQ number of the pin Negated Indicates no external interrupt when the indicat ed level is being requested 2 2 9 2 Port Q PQ 0 7 Input Output Module PCU State Meaning Asserted Negated Indicates the logic level of the data be ing transmitted Timing Comments __Assertion Negation Accesses to port Q require two clock cycles SIU SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product 2 17 Go to www freescale com Freescale Semiconductor Inc MOTOROLA SIGNAL DESCRIPTIONS SIU 2 18 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 3 MODULE CONFIGURATION This section describes several registers that are used to configure the SIU and PCU modules These registers include the following e The SIU module configuration register SIUMCR configures various aspects of SIU operation e The memory mapping register MEMMAP enables and sets the base address of the L bus and I bus internal memory blocks e The PCU module configuration register PCUMCR configures various aspects of PCU operation The following subsections describe these registers and discuss some of the issues in system configuration 3 1 SIU Module Configuration Re
13. M S Continuously running clock All signals driven on the E bus must be syn chronized to the rising edge of this clock Table 4 2 Address Type Encodings ATO AT1 Address Space 0 0 User data space 0 1 User instruction space 1 0 Supervisor data space 1 1 Supervisor instruction space Table 4 3 Byte Enable Encodings Byte Enable Use During 32 Bit Port Access Use During 16 Bit Port Access BEO Byte Enable for DATA 0 7 Byte Enable for DATA 0 7 BET Byte Enable for DATA 8 15 Byte Enable for DATA 8 15 BE2 Byte Enable for DATA 16 23 ADDR30 BE3 Byte Enable for DATA 24 31 0 Operand size is word 1 Operand size is byte or half word 4 3 Basic Bus Cycle The basic external bus cycle consists of two phases the address phase and the data phase If the external bus is not available when the SIU is ready to start an external cycle a bus arbitration phase is also required External bus cycles can be single or multiple burst data cycles Burst cycles normally have four data words associated with the cycle Refer to 4 6 Burst Cycles for infor mation on burst cycles SIU REFERENCE MANUAL EXTERNAL BUS INTERFACE For More Information On This Product Go to www freescale com MOTOROLA 4 3 Freescale Semiconductor Inc 4 3 1 Read Cycle Flow Figure 4 1 is a flow diagram of a single read cycle on the external bus MASTER SLAVE Y RECEIVE ADDRESS IS BUS GRANTED CAN SLAVE
14. Note that I bus show cycles are not burst A show cycle involves transfer start TS address ADDR cycle type CT address type AT burst BURST and read write WR pins The data phase of an L bus show cycle looks like a write cycle going out on the external bus The address and data phases of a show cycle last one clock cycle each No termination is needed for either phase as all show cycles are automatically terminated inside the SIU For the L bus show cycles bus show cycles are address only the data phase always follows the address phase by one clock cycle The L bus show cycle does not start until the inter nal cycle completes This allows all show cycles to complete in two clock cycles Show cycles require several holding registers in the SIU to hold address and data of an L bus cycle and address of an I bus cycle until the E bus is available and the show cycle is run When these holding registers are full the internal bus or buses are held up by the SIU while it waits for the show cycle to complete During cross bus accesses the show cycle is associated with the bus initiating the transaction For example if bus show cycles are enabled and L bus show cycles are disabled then an instruction fetch from L RAM will show up as an address only I bus show cycle and an L bus access to I memory would not have a show cycle Refer to the RCPU Reference Manual RCPURM AD for more information on show cycles and how they are use
15. The TADLY field in the option registers for CSBOOT and CS 1 5 indicates the number of wait states for the chip select logic to insert before returning TA If this field is en coded for zero wait states TA is asserted one clock cycle after TS is asserted An en coding of one wait state means that TA is asserted two clock cycles after TS and so on Up to seven wait states are allowed The encodings are shown in Table 5 7 Table 5 7 TADLY and Wait State Control TADLY Wait States 0b000 0 0b001 0b010 0b011 0b101 0b110 0b111 1 2 3 0b100 4 5 6 7 Note this field is used only when the chip select logic returns the handshaking signals ACKEN 1 Note that the user does not program the number of wait states prior to AACK assertion The chip select logic uses the following scheme to determine when to assert AACK e If the region is an asynchronous type AACK is asserted at the end of access to the region e If the region is pipelineable and the region is not busy with a pending access AACK is asserted after the address is latched by the region i e at the next rising clock edge e If the region is pipelineable and the region is busy with a pending access AACK is asserted for the next access to the region at the end of the pending access to the region e when TA is asserted for that access SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 15 Go to w
16. miss a complete regular bus cycle is generated SIU System interface unit Slave The device addressed by a master device The slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure Snooping Monitoring addresses driven by a bus master to detect the need for coherency actions Speculative access An access that the MCU performs out of order that it might otherwise not perform such as executing an instruction following a conditional branch Split transaction A bus transaction that couples the address and data phase of the bus cycle together as a single event Supervisor mode The privileged operation state of the RCPU In supervisor mode software can access all control registers and can access the supervisor memory space among other privileged operations User mode The unprivileged operating state of the RCPU In user mode software can only access certain control registers and can only access user memory space No privileged operations can be performed Watchpoint An event that when detected is reported but does not change the timing of the machine MOTOROLA For More Information On This Product G 3 Go to www freescale com Freescale Semiconductor Inc MOTOROLA SIU G4 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SUMMARY OF CHANGES This is
17. software needs to ensure that the code is accessible elsewhere For example if the processor is config uring the CSBOOT registers and simultaneously executing instructions out of the boot region software can re locate the necessary code to the instruction cache internal SRAM or to another external region such as external SRAM before modifying the chip select control registers Table 5 2 Chip Select Module Address Map Access Address Register 0x8007 FDOO 0x8007 FD90 RESERVED 0x8007 FD94 CS11 OPTION REGISTER CSOR11 0x8007 FD98 RESERVED 0x8007 FD9C 0x8007 FDAO CS10 OPTION REGISTER CSOR10 RESERVED 0x8007 FDA4 CS9 OPTION REGISTER CSOR39 0x8007 FDA8 RESERVED 0x8007 FDAC S8 OPTION REGISTER CSOR8 0x8007 FDBO RESERVED 0x8007 FDB4 0x8007 FDB8 S7 OPTION REGISTER CSOR7 RESERVED 0x8007 FDBC 0x8007 FDCO 0x8007 FDC4 0x8007 FDC8 0x8007 FDCC 0x8007 FDDO 0x8007 FDD4 0x8007 FDD8 0x8007 FDDC 0x8007 FDEO CS6 OPTION REGISTER CSOR6 CS5 BASE ADDRESS REGISTER 5 CSBAR5 CS5 OPTION REGISTER CSOR5 CS4 BASE ADDRESS REGISTER CSBAR4 CS4 OPTION REGISTER CSOR4 CS3 BASE ADDRESS REGISTER CSBAR3 CS3 OPTION REGISTER 3 CSOR3 CS2 BASE ADDRESS REGISTER 2 CSBAR2 CS2 OPTION REGISTER 2 CSOR2 CS1 BASE ADDRESS REGISTER CSBAR1 0x8007 FDE4 0x8007 FDE8 CST OPTION REGISTER CSOR1 RESERVED 0x8007 FDE
18. transfer start and the BURST signal to indicate a burst transfer If the slave can per form burst transfers it negates the burst inhibit signal BI If the slave does not support burst transfers it asserts BI An example of a burst read on the external bus is shown in Figure 4 6 MOTOROLA EXTERNAL BUS INTERFACE SIU 4 10 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CLKOUT ADDR A lt PIPELINED ADDRESS s pe E smst L mm A D1 gt lt D2 gt lt D3 gt lt DO gt WAIT STATE 4 ey Ww i Se LAST DATA BDIP NEXT Ti d Ze ADDR DATA MPC500 BRST RD TIM Figure 4 6 External Burst Read Cycle 4 6 1 Termination of Burst Cycles During the data phase of a burst read cycle the master receives data from the ad dressed slave The EBI asserts the BDIP signal at the beginning of a burst data phase and negates BDIP during the last beat of a burst The slave device stops driving new data after it receives the negation of BDIP at the rising edge of the clock The EBI can terminate a burst cycle early by asserting the BDIP pin Early termination is used for a word aligned not double word aligned burst to a small port The LST bit in the SIU module configuration register SIUMCR determines the timing used for the BDIP pin If LST is cleared t
19. 1 Enable bus monitor MOTOROLA SYSTEM PROTECTION SIU 7 6 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 7 7 BMCR Bit Settings Continued Bit s Name Description 6 7 BMT Bus monitor timing These bits select the time out period in system clocks for the bus monitor 00 256 system clocks 01 64 system clocks 10 32 system clocks 11 16 system clocks 8 31 Reserved 7 5 Software Watchdog The software watchdog monitors the software interfaces of the system and requires the software to take periodic action in order to ensure that the program is executing properly To protect against software error the following service must be executed on a regular basis 1 Write 0x556C to the SWSR 2 Write OxAA39 to the SWSR This sequence clears the watchdog timer and the timing process begins again If this periodic servicing does not occur the software watchdog issues a reset Any number of instructions may occur between the two writes to the SWSR If any val ue other than 0x556C or OxAA39 is written to the SWSR however the entire se quence must start over 7 5 1 Software Watchdog Service Register A write of 0x556C followed by a write of OxAA39 to the software watchdog service reg ister SWSR causes the software watchdog register to be reloaded with the value in the software watchdog timing count SWTC
20. Cycle type Address attribute BURST Burst Address attribute TS is a control signal that is valid for only one clock cycle at the start of the address phase The address attributes listed in Table 4 4 are updated at the start of the ad dress phase and are maintained until the start of the next address phase MOTOROLA EXTERNAL BUS INTERFACE SIU 4 8 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc The address phase is the period of time from the assertion of TS until the address phase is terminated by one of the following signals e Address acknowledge AACK e Address retry ARETRY e Transfer error acknowledge TEA If the external memory is under chip select control and the chip selects are enabled to return handshakes then the chip selects normally generate AACK internally Howev er if the external AACK pin is asserted before the chip select module generates the signal the chip select module accepts the external pin information and does not gen erate the AACK signal internally Burst inhibit BI is sampled when AACK is asserted BI is asserted by the slave to in dicate to the SIU that the addressed device does not have burst capability Refer to 4 6 2 Burst Inhibit Cycles for more information ARETRY and TEA can also be used to terminate the address phase Refer to 4 10 Ad dress Retry and 4 11 Transfer Error Acknowledge Cycles for more information
21. Figure 5 9 and Figure 5 10 illustrate reads and writes for devices with this type of in terface CLKOUT _ L E ADDR OVERLAP ACCESS WR CLOCK IN ADDRESS FOR READ CE ENABLE DATA OUTPUT OE ASYNCHRONOUS UNDEFINED AACK DONT CARE MPC500 SYNC R ASYNC OE TIM Figure 5 9 Synchronous Read with Asynchronous OE Zero Wait States MOTOROLA CHIP SELECTS SIU 5 26 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CLKOUT ADDR 4 Al x OVERLAP ACCESS CR IN ADDRESS FOR WRITE CLOCK IN DATA FOR WRITE J UNDEFINED OE o E OR DON T CARE MPC500 SYNC WR TIM Figure 5 10 Synchronous Write Zero Wait States 5 16 4 Synchronous Interface With Early Synchronous OE ITYPE 3 Devices with ITYPE 3 have a synchronous interface with a synchronous output en able OE is asserted at the earliest one clock cycle after CE The synchronous OE should be sampled by the external device using the rising edge of its clock signal For read accesses the early OE signal allows the responding device to prepare for the next data cycle If OE is asserted the device can prepare to drive the next data or re fill its internal data queue If OE is not asserted the device can place the data lines in a high impedance stat
22. In this case maximum CLKOUT frequency i e CLKOUT frequency when the RFD field is cleared is equal to one half the oscillator frequency In this mode the oscillator source must have a 50 duty cycle In each clock mode except 1 1 mode CLKOUT frequency can be reduced by program ming the RFD field to a non zero value Refer to 6 5 CLKOUT Frequency Control for details If Vpbpsn 0 and MODCLK 0 then the CPU clocks are configured in special test mode In this mode the PLL and most of the clock generation circuitry are bypassed This mode is intended for factory test only CAUTION When the clock is in PLL bypass mode or special test mode setting the LOLRE bit in the SCCR generates a loss of lock reset request since the PLL is off The LOLRE bit must not be set when the clock is in PLL bypass or special test mode 6 4 Phase Locked Loop The phase locked loop PLL is a frequency synthesis PLL that can multiply the refer ence clock frequency by a factor from 4 to 11 provided the system clock CLKOUT frequency when RFD 0b000 remains within the specified limits With a reference fre quency of 4 MHz the PLL can synthesize frequencies from 16 MHz to 44 MHz MOTOROLA CLOCK SUBMODULE SIU 6 4 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc The output of the PLL can be divided down to reduce the system frequency with the reduced frequency divider RFD The RFD
23. this pin should be pulled to ground through a resistor Refer to 8 3 Configuration Dur ing Reset for more information Timing Comments Refer to the RCPU Reference Manual RCPURM AD for detailed timing information 2 2 4 4 Instruction Fetch Visibility Signals VF 0 2 Output only Module Development support State Meaning Asserted Negated Denote the last fetched instruction or the number of instructions that were flushed from the in struction queue Refer to the RCPU Reference Manual MOTOROLA SIGNAL DESCRIPTIONS SIU 2 12 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc ROPURM AD for details Timing Comments __Assertion Negation Transitions may occur every clock cy cle This signal is not synchronous with bus cycles Refer to the RCPU Reference Manual RCPURM AD for more in formation on these signals 2 2 4 5 Instruction Flush Count VFLS 0 1 Output only Module Development support State Meaning Asserted Negated Denote the number of instructions that are flushed from the history buffer during the current clock cycle These signals also provide the freeze indication Re fer to the RCPU Reference Manual RCPURM AD for de tails Timing Comments __Assertion Negation Transitions may occur every clock cy cle This signal is not synchronous with bus cycles Refer to the RCPU Reference Manual RCPURM AD for more in formation on these signals 2
24. 0 1 Map Address types These address attribute signals define addressed space as user or supervisor data or instruction Refer to Table 4 2 for encod ings These signals have the same timing as ADDR 0 29 CT 0 3 Map Cycle type signals These address attribute signals indicate what type of bus cycle the bus master is initiating Used for development support Refer to Table 4 10 for encodings BURST M gt S Burst cycle This address attribute indicates that the transfer is a burst transfer If a burst access is burst inhibited by the slave the BURST pin is driven during each single beat decomposed cycle AACK S M Address acknowledge When asserted indicates the slave has received the address from the bus master This signal terminates the address phase of a bus cycle When the bus master receives this signal from the slave the master can initiate another address transfer This signal must be asserted at the same time or prior to TA assertion ARETRY S A M Address retry This is an address phase termination signal It is de signed to resolve deadlock cases on hierarchical bus structures or for error correcting memories ARETRY assertion overrides AACK asser tion and causes the SIU to re arbitrate and to re run the bus cycle BI S M Burst inhibit When asserted indicates the slave does not support burst mode Sampled at same time as AACK If BI is asserted the SIU trans fers the burst data in multiple cycles and increments the address for
25. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED SIU RESET OPERATION MOTOROLA REFERENCE MANUAL For More information On This Product 8 1 Go to www freescale com Freescale Semiconductor Inc Table 8 1 Reset Status Register Bit Settings Description If set source of reset is the external RESET input pin This pin should be asserted whenever VDD is below VDD yin If set source of reset is a loss of oscillator The clock module asserts loss of oscillator reset when the MCU is in low power mode 3 or no clock signal is present on the EXTAL pin If the clock module detects a loss of oscillator condition erroneous external bus operation will occur if syn chronous external devices use the MCU input clock Erroneous operation can also occur if de vices with a PLL use the MCU CLKOUT signal This source of reset is masked by the loss of oscillator reset enable LOORE bit in the system clock control register SCCR If set the cause of reset is the loss of PLL lock The clock module asserts loss of lock reset when the PLL detects a loss of lock and the loss of lock reset enable bit is set in the system clock con trol register SCCR If the PLL detects a loss of lock condition erroneous external bus operation will occur if synchronous external devices use the MCU input clock Erroneous operation can also occur if devices with a PLL use the MCU CLKOUT signal This source of reset is masked by the loss of lock reset enabl
26. 2 1 1 Fe eet BA sett 2 2 1 2 BUS Grant E EE 2 2 1 3 Bus Busy BB ike cathe uate te Ae teeta cee Sauer eee 2 2 1 4 Cancel Reservation CR cccccceseeeeeeeeeeeeeeeeneeeeeeeeee 2 2 2 Address Phase Signals AEN 2 2 2 1 Address ERR RE RK E 2 2 2 2 Write Read ANS egEe Eeer 2 2 2 3 Burst Indicator BURST eeeeeeeeeeeeeeeeeeeeeeteeeeeeeeeeeeees 2 2 2 4 Byte Enables BE 0 3 2 0 20 anand deene Nees 2 2 2 5 Transter Start E E WEE 2 2 2 6 Address Acknowledge AACK ceeeeeeeeseeeeeeeetees 2 2 2 7 Burst Inhibit BI NEE 2 2 2 8 Address Retry ARETRY en 2 2 2 9 Address Type AT 0 1 e ececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 2 2 2 10 Cycle Types CT 0 3 ee 2 2 3 Dat amp Phase Signals pececncveets cms ovsdvucdeateceecirestss EE eiin 2 2 3 1 Data Bus DATA 0 31 Seeerei ees 2 2 3 2 Burst Data in Progress BDIP ecceeeseeeeeeeeeeeeees 2 2 3 3 Transfer Acknowledge TA EE 2 2 3 4 Transfer Error Acknowledge TEA sseesesssssssseeeeseeeee 2 2 3 5 Data Strobe UE st esegeuk rage gege ebe egegeg 2 2 4 Development Support Signals ccccecceeceeeeeeeeeeeeeteeeees SIU REFERENCE MANUAL For More Information On This Product Go to www freescale com Page MOTOROLA iil Freegale sepies me Continued Paragraph Title Page 2 2 4 1 Development Port Serial Data Out DSDO eee 2 11 2 2 4 2 Development Port Serial Data In DSDI eee eee 2 12 2 2 4 3 D
27. 4 5 3 Data Phase If the pipe depth before a cycle starts is zero or would have gone to zero if the new cycle had not started then the data phase always starts one clock cycle after the ad dress phase starts If there is a previous data phase in progress one clock after an ad dress phase starts then the data phase for that address phase starts as soon as the previous data phase completes The data phase completes when it is terminated by TA or TEA If the cycle is a burst cycle then multiple TA assertions are required to ter minate the data phase During the data phase the following signals are used e DATA 0 31 e Burst data in progress BDIP The data phase can be terminated with either of the following signals e Transfer acknowledge TA e Transfer error acknowledge TEA AACK and TA are required for every cycle If under some error condition the slave asserts TA but not an AACK the SIU does not recover from this error condition If the external memory is under chip select control and the chip selects are pro grammed to return handshakes ACKEN 1 in the chip select option registers then the chip selects return TA unless the external TA pin is asserted first In that case the chip select module accepts the external pin information and does not generate TA in ternally A bus timer or system address protection mechanism can assert transfer error ac knowledge TEA to terminate the data phase when a bus error condition
28. 5 are involved in the sub block protection scheme These are the chip selects with address decoding logic i e they can act as chip enables MOTOROLA CHIP SELECTS SIU 5 12 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 5 6 2 Programming the Sub Block Option Register When the SBLK bit in CSOR1 CSOR3 or CSOR5 is set the corresponding address block defined by the BA and BSIZE fields is designated a sub block Table 5 6 indi cates the main block to which the sub block is assigned When the SBLK bit in one of these registers is set the following fields in the sub block option register must be programmed to the same values as in the option register for the corresponding main block ITYPE ACKEN TADLY and PS If there is a discrep ancy in the encoding of any of these bits in the two option registers the chip select unit uses the bits that are set in either register i e it performs a logical OR on the associ ated bits in the two registers When the SBLK bit in CSOR1 CSOR38 or CSOR5 is set the corresponding chip se lect pin cannot act as a CE pin since its decoder is used for multi level protection The pin however can still be configured by programming the PCON field to function as an OE WE or non chip select pin If the pin is configured as a WE or OE it can be assigned to any region not just the region associated with the sub block The CSB
29. 6 0110 64 0 250M 0 313M 0 375M 0 438M 0 500M 0 563M 0 625M 0 688 M 7 0111 128 0 125M 0 156M 0 188M 0 219M 0 250M 0 281M 0 313M 0 344M 1000 256 62 500K 78 125K 93 750K 0 109M 0 125M 0 141M 0 156M 0 172M 1001 512 31 250K 39 063K 46 875K 54 688K 62 500 K 70 313K 78 125K 85 938 K 10 1010 1024 15 625K 19 531 K 23 438K 27 344K 31 250K 35 156 K 39 063K 42 969 K 11 1010 1024 15 625K 19 531 K 23 438K 27 344K 31 250K 35 156 K 39 063K 42 969 K 12 1010 1024 15 625K 19 531 K 23 438K 27 344K 31 250K 35 156 K 39 063K 42 969 K 13 1010 1024 15 625K 19 531 K 23 438K 27 344K 31 250K 35 156 K 39 063K 42 969 K 14 1010 1024 15 625K 19 531 K 23 438K 27 344K 31 250K 35 156 K 39 063K 42 969 K 15 1010 1024 15 625K 19 531 K 23 438K 27 344K 31 250K 35 156 K 39 063K 42 969 K NOTES 1 Default setting Whenever clock reset is asserted the MF bits are set to 0x2 multiply by six and the RFD bits are set to 0x3 divide by eight These values program the PLL to generate the default system frequency of 3 MHz when a 4 MHz crystal is used 6 5 1 Multiplication Factor MF Bits The MF bits determine the operating frequency of the PLL The 4 MHz crystal refer ence frequency is multiplied by an integer from 4 to 11 depending on the value of the ME bits resulting in a PLL
30. Also as serted at the end of a show cycle 4 mi gt MOTOROLA EXTERNAL BUS INTERFACE SIU 4 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 4 1 EBI Signal Descriptions Continued Mnemonic Direction Description Arbitration BR M gt A When asserted indicates the potential bus master is requesting the bus Each master has its own bus request signal BG A gt M Bus grant When asserted by bus arbiter the bus is granted to the bus master Each master has its own bus grant signal BB M gt M A Bus busy Asserted by current bus master to indicate the bus is currently in use Prospective new master should wait until the current master ne gates this signal Miscellaneous CR X gt M Cancel reservation Each PowerPC CPU has its own CR signal This signal shows the status of any outstanding reservation on the external bus When asserted CR indicates that there is no outstanding reserva tion This is a level signal RESET Source M This input only signal resets the entire MCU While RESET is asserted the MCU asserts the RESETOUT signal RESETOUT Mos Reset output This output only signal indicates that the MCU is in reset When asserted instructs all devices monitoring this signal to reset all parts within themselves that can be reset by software CLKOUT Source
31. INTERFACE ADDRESS MUX CROSS BUS ARB amp CNTL ADDRESS DECODE BUS ADDR f BUS BIU HDATA SUBBUS INTERFACE BUS MONITOR CLOCKS POWER PC TIMER amp DECREMENTER MPC500 SIU BLOCK Figure 1 2 SIU Block Diagram 1 3 SIU Address Map Table 1 1 is an address map of the SIU registers An entry of S in the Access column indicates that the register is accessible in supervisor mode only S U indicates that the register can be programmed to the desired privilege level Test indicates that the register is accessible in test mode only SIU OVERVIEW MOTOROLA REFERENCE MANUAL For More Information On This Product 1 3 Go to www freescale com Freescale Semiconductor Inc Table 1 1 SIU Address Map Access Address Register S 0x8007 FC00 SIU MODULE CONFIGURATION REGISTER SIUMCR Test 0x8007 FC04 SIU TEST REGISTER 1 SIUTEST1 0x8007 FC08 0x8007 FC1C 0x8007 FC20 RESERVED MEMORY MAPPING MEMMAP 0x8007 FC24 SPECULATIVE ADDRESS REGISTER SPECADDR 0x8007 FC28 SPECULATIVE MASK REGISTER SPECMASK 0x8007 FC2C TERMINATION STATUS REGISTER TERMSTAT 0x8007 FC30 0x8007 FC3C RESERVED 0x8007 FC40 PERIODIC INTERRUPT CONTROL AND STATUS REGISTER PIC SR 0x8007 FC44 PERIODIC INTERRUPT TIMER REGISTER PIT 0x8007 FC48 0x8007 FC4C BUS MONITOR CONTROL REGISTER BMCR RESET STATU
32. In addition the CSBOOT sub block circuit has a base address reg ister The base address register specifies the base address of the memory or periph eral controlled by the chip select The base address and block size together determine the range of addresses con trolled by a chip select Block size is the extent of the address block above the base address Block size is specified in the BSIZE field of the chip select option register The BA base address field in the chip select base address register contains the high order bits bits O through 19 of the address block to which the associated chip select responds Register bit 0 corresponds to ADDRO register bit 19 corresponds to ADDR 19 The BSIZE field determines how many of these bits are actually compared For the smallest block size encoding 4 Kbytes bits 0 through 19 are compared with ADDR 0 19 For larger block sizes not all of these bits are compared Table 5 5 shows the block size and address lines compared for each BSIZE encoding MOTOROLA CHIP SELECTS SIU 5 10 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 5 Block Size Encoding BSIZE Field Block Size Address Lines Compared Binary Bytes 0000 Invalid Chip select is not asserted until BSIZE field is assigned a nonzero value 0001 4K ADDR 0 19 0010 8K ADDR 0 18 0011 16K ADDR 0 17 0100 32 K A
33. a programmable phase locked loop The PLL is pro grammable in integer multiples of 4 MHz to generate operating frequencies of 16 MHz to 44 MHz These frequencies can be divided by powers of two to generate other fre quencies If the crystal ceases to function the loss of oscillator LOO bit is set and the PLL is forced to operate in the self clocked mode SCM This mode provides a system clock frequency of approximately 4 MHz The exact frequency depends on the voltage and temperature of the CPU but is optimized for nominal operating conditions The PLL can be bypassed by grounding the Vppsn pin Note that in this case the input frequency needs to be twice the desired operating system frequency With Vppsn grounded the multiplication factor MF bits in the system clock control register SC CR no longer have any effect on the system frequency but the reduced frequency RFD bits and the low power mode LPM bits do have an effect Three different low power modes are available to minimize standby power usage Nor mal operation or one of the three low power modes is selected by programming the LPM bits in the SCCR The clock submodule also provides a clock source for the PowerPC time base and decrementer The oscillator time base and decrementer are powered from the keep alive power supply VDDKAP1 This allows the time base to continue incrementing even when the main power to the MCU is off While the power is off the decrementer al
34. and PM2 and DDM2 bits may not be implemented On these systems the PMPA2 bit may still be active but may select between two non port M pin functions Refer to the user s man ual for the microcontroller of interest for details The bits in DDRM control the direction of the port M pin drivers when the pins are con figured as I O pins Setting a bit in this register to one configures the corresponding pin as an output clearing the bit configures the pin as an input MOTOROLA GENERAL PURPOSE I O SIU 9 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc PMPAR Port M Pin Assignment Register 0x8007 FC64 0 1 2 3 4 5 6 T 8 9 10 11 12 13 14 15 PMPAO PMPA1 PMPA2 PMPA3 PMPA4 PMPA5 PMPA6 PMPA7 RESERVED RESET R R i i S x 0 0 0 0 0 0 0 0 Reset value depends on the value of the data bus configuration word at reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 On some SIU members the PM2 signal and PM2 and DDM2 bits may not be implemented On these systems the PMPA2 bit may still be active but may select between two non port M pin functions Refer to the user s man ual for the microcontroller of interest for details The bits in PMPAR control the function of the associated pins Setting a bit in this reg ister to one configures the corresponding pin as a bus
35. consecutive accesses to different regions 5 15 1 Pipelined Accesses to the Same Region The chip select unit overlaps consecutive accesses to the same region provided the following conditions are met e The second access is a read e The region is pipelineable as determined by its ITYPE e The TA signal is generated by the chip select logic ACKEN 1 When these conditions are met the address and CE assertion for the second access can overlap the data phase of the first access Figure 5 5 illustrates the concept of overlapped accesses to the same region Note that the diagram cannot be assumed to be accurate in timing CLKOUT ADDR lt At READ gt lt A2 OVERLAP gt CE 2ND ADDRESS OVERLAP WITH 1ST DATA OE 1ST ADDRESS LATCHED Figure 5 5 Overlapped Accesses to the Same Region NOTE If the region is programmed to return its own handshaking signals ACKEN 0 the chip select logic does not know whether the device has an address latch hence whether the device is programmable MOTOROLA CHIP SELECTS SIU 5 22 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc The chip select control logic takes this into account and asserts the CE of the second access only after AACK has been asserted for the first access 5 15 2 Pipelined Accesses to Different Regions The chip select unit su
36. delay is incurred All changes in frequency are synchronized to the next falling edge of the cur rent system clock Table 6 6 summarizes the possible values for the RFD bits Table 6 6 Reduced Frequency Divider Bits RFD Field Divider Binary 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 1024 1100 1024 1101 1024 1110 1024 1111 1024 These bits can be read at any time They should be written only when the system PLL lock status bit SPLS is set Writing the RFD bits especially to 0x0 when the PLL is not locked can cause the clock frequency to surpass the system operating frequency Software is responsible for monitoring the SPLS bit and preventing a write to RFD 0 3 while the PLL is out of lock The RFD bits should always be written to a value of 0x1 or greater before changing the MF bits to ensure the system frequency does not exceed the system s design mar gin since the VCO overshoots in frequency as it tries to compensate for the change in frequency The RFD bits should be changed to their final value only after the MF bits have been written to their final value and PLL lock at the new frequency has been es tablished For example to change from the default system frequency to 16 MHz write the RFD bits to 0x1 then write the MF bits to 0x0 After the PLL locks write the RFD bits to 0x0 The RFD bits can be protecte
37. field of the SWCR This register can be written at any time within the time out period A write of any value other than those shown above resets the servicing sequence requiring both values to be written to the SWSR before the value in the SWTC field is reloaded into the SWSR Reads of the SWSR return zero SWSR Software Watchdog Service Register 0x8007 EFCO 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SWSR RESERVED RESET 000 0000 0 0 0000 00 0000 0 0 0000 0 0 0 0 0 0 0 7 5 2 Software Watchdog Control Register Timing Count The software watchdog control register timing count consists of the software watchdog enable SWE and software watchdog lock SWLK bits and the timing count field for the software watchdog The software watchdog timing count SWTC field contains the 24 bit value that is loaded into the SWSR upon completion of the software watchdog service sequence SIU SYSTEM PROTECTION MOTOROLA REFERENCE MANUAL For More Information On This Product 7 7 Go to www freescale com Freescale Semiconductor Inc When the SWLK bit is cleared this register can be written Once the lock bit is set further writes to this register have no effect In debug mode however the lock bit can be cleared by software The register can be read at any time SWCR SWTC Software Watchdog Control Field Timing Count 0x8007 EFC4 0 1 2 3 4 5 6 7 8 9 10 11 1
38. first access after it has received the AACK signal for the first access The chip select logic asserts the CE of the second access while the data phase of the first access is still in progress if the second access is issued before the first access is com pleted 5 If the first access is to a region that is not under chip select control external glue logic generates all control and handshake signals for the region as for a DRAM controller for example and the second access is to a region that is un der chip select control the chip select module does not pipeline the second ac cess with the first 6 Ifthe first access is to a region under chip select control and the second access is a read access to a region that is not under chip select control the external glue logic designer must decide whether to pipeline the second access with the first The decision depends on system requirements and on the interface type of the region that is not under chip select control 7 If the first access is a burst read access to a burstable region and the second is aread access to another region the chip select module pipelines the second read if the second access is to a region with an interface type that is pipeline able and can hold off its data If ITYPE 8 for the second region the chip select module does not pipeline the second access with the first 8 If the first access is to a synchronous region and the second access is to an asynchronous
39. input frequency on the EXTAL pin A frequency below 125 kHz causes the loss of oscillator circuitry to assert the LOO bit and force the PLL into self clocked mode A frequency above 500 kHz causes the loss of oscillator circuitry to negate the LOO bit and the PLL operates normally The LOO bit can be read any time It can be written only in special test mode The loss of oscillator reset enable LOORE bit in the SCCR indicates how the clock module should handle a loss of oscillator condition LOO asserted When LOORE is clear clock reset is not asserted if a loss of oscillator indication occurs When LOORE is set clock reset is asserted when a loss of oscillator indication occurs The reset module may wait for the PLL to lock before negating reset see SECTION 8 RESET OPERATION The LOORE bit is cleared when clock reset is asserted and may be re initialized by software Note that a loss of oscillator forces the PLL to go out of lock and into the self clocked mode SCM regardless of the state of the LOORE bit 6 11 System Clock Control Register SCCR The SCCR controls the operation of the PLL It is powered by VDDKAP1 The SCCR is not affected by reset conditions that do not cause clock reset Clock reset caused by loss of oscillator loss of lock or external reset causes the register to be reset as indicated in the diagram SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Product 6 15 Go to www free
40. is encoun tered Refer to 4 11 Transfer Error Acknowledge Cycles for further information SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 9 Go to www freescale com Freescale Semiconductor Inc The EBI asserts the data strobe DS signal at the end of a chip select controlled bus cycle provided that either 1 The chip select unit asserts the internal TA signal or 2 The bus monitor timer asserts the internal TEA signal DS is not asserted however if TA or TEA is asserted externally even if TA or TEA is simultaneously asserted internally In addition to being asserted at the end of the bus cycles mentioned above DS is as serted at the end of a show cycle 4 6 Burst Cycles Burst cycles allow the fast transfer of data over the bus The SIU supports both burst write and read accesses The RCPU however supports burst reads but not burst writes The SIU supports fixed length of bursts of four beats Burst cycles can be ter minated early with the BDIP signal Burst reads on the external bus dont start until the internal data bus is available For example when the SIU starts a burst read and does not have L bus data bus grant because there is an L bus cycle in progress an IMB2 access then the SIU holds off the burst read until it can guarantee that it will have the internal bus grant At the start of a burst transfer the master drives the address the address attributes
41. is not contained in the feedback loop of the PLL so changing the RFD bits does not affect PLL operation Note that the system frequency programmed should not exceed the operating fre quency of any of the parts in the target system Figure 6 2 shows the overall block diagram for the PLL Each of the major blocks shown is discussed briefly below Eo XFCN F E OSCCLK UP 7 oy EE ee CHC hal as VCOOUT FEEDBACK DETECTOR DOWN PUMP gt je MODE day VDDSN VSSSN CLOCK MF DIVIDER DELAY MF 0 3 gt X4 TO X11 CLKOUT VDDI VSSI L MPC500 PLL BLOCK Figure 6 2 Phase Locked Loop Block Diagram 6 4 1 Crystal Oscillator The crystal oscillator has an external 10 MQ resistor and two external 36 pf capacitors connected to the EXTAL and XTAL pins as shown in Figure 6 3 The internal oscilla tor is designed to work best with a 4 MHz crystal Crystal start up times depend on the value of the resistor The start up time can be reduced by reducing the value of the resistor SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Product 6 5 Go to www freescale com 6 Freescale Semiconductor Inc 36 pF 4 MHz Ai EXTAL o C 10 MQ i pe 36 pF DI MPC500 XTAL OSC Figure 6 3 Crystal Oscillator 6 4 2 Phase Detector The phase detecto
42. overrides the assertion of TA If AACK has not been asserted for the current bus cycle TEA termi nates both the address phase and the data phase This signal is intended for the cases of a write to a read only address space or an access to a non existent address The signal can be output by a bus monitor timer or some system address protection mechanism such as the chip select logic Negated Indicates that no external device has signaled a bus error Assertion May occur at any time during the address phase or data phase of a bus cycle Negation Must occur one clock cycle after assertion of TEA Asserted By EBI indicates the termination of a cycle from an internal source TA or TEA assertion from the chip select unit TEA assertion from the bus monitor or a show cycle DS can be used to latch data for a bus analyzer It can also aid in following the external bus pipeline Assertion Occurs after the chip select unit asserts the in ternal TA signal or the bus monitor timer asserts the inter nal TEA signal DS is also asserted at the end of a show cycle 2 2 4 Development Support Signals 2 2 4 1 Development Port Serial Data Out DSDO Output only Module Development support SIU REFERENCE MANUAL For More Information On This Product SIGNAL DESCRIPTIONS MOTOROLA 2 11 Go to www freescale com Freescale Semiconductor Inc State Meaning Asserted Negated Indicates the logic level of data being shif
43. refers to the fact that the transactions are indivisible The processor initiates the read and write separately but signals the L bus or external bus interface that it is attempting an atomic operation If the operation fails status is kept so that the processor can try again The processor implements atomic accesses through the lwarx stwex instruction pair B Beat A burst data transfer has a number of units of data represented by states on the E bus associated with it Each unit of data is a data beat Big endian A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered left to right 0 1 2 3 with O being the most significant byte Breakpoint An event that when detected forces the machine to branch to a breakpoint exception routine Burst A multiple beat data transfer In MPC500 family microcontrollers a burst transfer normally includes four data beats Burstable device A burstable device can accept one address and drive out multiple data beats A burstable device must be synchronous Bus master The owner of the address or data bus the device that initiates or requests the transaction Bus transaction A bus transaction consists of an address transfer address phase and one or more data transfers data phase C Cross bus access Access by a master SIU or RCPU on one internal bus l bus or L bus to a slave on the
44. region the chip select module does not pipeline the accesses 9 Ifthe first access is to an asynchronous region the chip select module does not pipeline the second access with the first since both the external address and data bus must be available for the first access until it is completed If the first region requires an extra clock to turn off its buffer the chip select logic allows an extra clock for the region 5 16 Chip Select Timing Diagrams The diagrams in this section show the different device interfaces that the chip select module supports Where applicable the diagrams indicate how the various signals address data and chip select signals are correlated MOTOROLA CHIP SELECTS SIU 5 24 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CAUTION The user must not assume that CE is always asserted simultaneous ly with TS Depending on the state of the pipeline which depends on the interface types of the devices being accessed the chip select unit may delay asserting CE until one or more clock cycles after TS is asserted 5 16 1 Asynchronous Interface An external device with an asynchronous interface requires the address and the chip select signals CE OE and WE to be valid until the end of the access The next ac cess to the same device must wait for the previous access to complete No overlap of accesses is allowed Figure 5 7 and Figure 5 8 illust
45. selects State Meaning Asserted Indicates the memory region for which the chip select is programmed is being accessed CS 1 5 can be programmed as chip enables output enables or write en ables CSO and CS 6 11 can be programmed as output en ables or write enables Negated Indicates the memory region for which the chip select is programmed is not being accessed Timing Comments Assertion Negation These are address phase signals when used as chip enables CS 1 5 only or data phase signals when used as output enables or write enables When these signals are chip enables assertion may be de layed from the assertion of TS 2 2 6 Clock Signals 2 2 6 1 Clock Output CLKOUT Output only Module Clocks State Meaning Asserted Negated Provides a clock which runs continu ously All signals driven on the E bus must be synchronized to the rising edge of this clock 2 2 6 2 Engineering Clock Output ECROUT Output only Module Clocks State Meaning Asserted Negated Provides a buffered clock reference output with a frequency equal to the crystal oscillator fre quency divided by four 2 2 6 3 Crystal Oscillator Connections EXTAL XTAL Input Output Module ER State Meaning Connections for the external crystal to the internal oscillator circuit An external oscillator should serve as input to the EXTAL pin when used MOTOROLA SIGNAL DESCRIPTIONS SIU 2 14 For More Information On This Product REFERENCE MA
46. the register to be reset as indicated in the diagram SCLSR System Clock Lock and Status Register 0x8007 FC54 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED STME MPL LPML RFDL RESERVED STMS CLOCK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED WUR RESERVED SPLSS SPLS LOO CLOCK RESET 0 0 0 0 0 0 0 U 0 0 0 0 0 U U U U Unaffected by clock reset Table 6 10 SCLSR Bit Settings Bit s Name Description 0 3 Reserved 4 STME _ System PLL test mode enable 0 Test mode disabled 1 Test mode enabled 5 MPL MF lock 0 Writes to MF field in SCCR allowed 1 Writes to MF field have no effect 6 LPML_ Low power mode lock 0 Writes to LPM bits allowed 1 Writes to LPM bits have no effect SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Product 6 17 Go to www freescale com Freescale Semiconductor Inc Table 6 10 SCLSR Bit Settings Continued Bit s Name Description 7 RFDL_ Reduced frequency divide lock 0 Writes to RF bits allowed 1 Writes to RF bits have no effect 8 13 Reserved 14 15 STMS System PLL test mode select 00 Normal operation 00 01 11 Special test modes for factory test only 16 22 E Reserved 23 WUR_ Wake up request 0 PDWU pin forced low request power off 1 PDWU pin forced high request power on 24
47. the reservation address e Indicate the current status of the local bus reservation such that it may be sam pled prior to the address phase of the stwex bus cycle The reservation must be set in time to enable a store to the reservation address and must be cleared fast enough to disable a store to the reservation address The EBI samples the CR pin prior to starting an external stwex cycle If the reserva tion is cancelled CR is asserted no cycle starts If the reservation is not cancelled the SIU begins the bus cycle lf ARETRY is asserted the SIU must re sample the CR and BG pins prior to perform ing the external retry If a reservation exists on a non local bus and the SIU begins a stwex cycle to that address on the local bus while the non local bus reservation is cleared the ARETRY signal should be asserted to the SIU and the reservation signal should be cleared be fore BG is asserted to the SIU This means that AACK should not be returned until suc cessful coherent completion of the stwex is ensured The non local bus interface must not perform the non local write or abort it if the bus supports aborted cycles if it asserts ARETRY NOTE Single master systems do not require an external reservation track ing logic In these systems the CR pin should be tied by resistor to the reservation valid high state Alternatively the reservation pin may be configured as a port If the reservation pin is configured as a
48. to www freescale com Freescale Semiconductor Inc word reset 8 8 Control register block 3 7 CR 2 4 4 3 4 21 CR bit 8 2 Cross bus accesses 3 9 Crystal oscillator 6 5 CS 2 14 5 3 CSBAR 5 5 CSBOOT 2 13 5 3 base address 5 33 sub blocks 5 13 CSBTBAR 5 5 CSBTOE 5 3 CSBTOR 5 6 CSBTSBBAR 5 5 CSOR 5 6 CSR 3 2 CT 2 9 4 2 4 8 4 17 Cycle types 4 17 See also CT Cycle types See CT St DATA 2 9 4 2 4 9 Data bus configuration mode 8 7 reset configuration word 5 6 8 8 direction registers 9 1 phase 4 9 registers 9 1 space only 5 9 space protection 5 14 strobe See DS Data bus 2 9 DCE 6 14 6 16 DDRI DDRJ DDRK DDRL 9 4 DDRM 9 2 Debug mode 4 16 5 13 and reset 8 7 Debug register lock 3 2 Decomposed cycles 4 12 Decrementer 6 13 and freeze assertion 3 10 clock enable 6 14 6 16 clock source 6 16 Development serial clock See DSCK serial data in See DSDI serial data out See DSDI DLK 3 2 Doze mode 6 11 DS 2 11 4 2 4 10 DSCK 2 12 8 7 DSDI 2 12 8 7 DSDO 2 11 6 3 DSP 5 9 DSPACE 5 14 MOTOROLA l 2 For More Information On This Product Go to www freescale com a Early overlapping of accesses 5 20 EBI 4 1 ECROUT 2 14 6 3 Emulation memory select 4 17 Enabled active interrupt requests register See IRQAND Engineering clock reference See ECROUT Exception prefix 5 6 5 11 EXTAL 2 14 6 3 External bus interface See EBI crystal connections See EXTAL XTAL filter capacitor connections See XFC
49. 007 FDCO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BA RESERVED RESET Table 5 3 Chip Select Base Address Registers Bit Settings Bit s Name Description 0 19 BA Base Address Bits 0 through 19 of the base address of the block to which the chip select responds Register bit O corresponds to address bit 0 register bit 19 corresponds to address bit 19 20 31 Reserved 5 4 2 Chip Select Option Registers CSBTOR the option register for CSBOOT has the same field definitions as the option registers for CS 1 5 but has different reset values The CSO and CS 6 10 option reg isters contain a subset of the fields in the CSBTOR The CSBOOT sub block option register contains a different subset of the fields in the CSBTOR The reset values of several bits in the chip select option registers depend on the data bus configuration word the state of the internal data bus at reset The TADLY field in the CSBOOT option register is read from the internal DATA 6 8 bits and the PS field is determined from DATA4 In addition the reset value of the PCON field in the option registers for CS 0 11 depends on the value of internal DATAO at reset If DATAO 1 the CS 0 11 ADDR 0 11 pins are configured as chip selects and the PCON field at reset is 0b10 output enable for CSO and 0b00 chip enable for CS 0 11 If internal DATAO 0 at reset the pins are configured
50. 1 12 13 14 15 LO L1 L2 L3 L4 L5 L6 L7 L8 L9 Lio Li os Lig 14 Dos RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOTOROLA INTERRUPT CONTROLLER AND PORT Q SIU 10 6 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 3 2 Enabled Active Interrupt Requests Register The enabled active interrupt requests register IRQAND is a read only status register that is defined by the following equation IRQAND IRQPEND amp IRQENABLE where amp is a bitwise operation IRQAND Enabled Active Interrupt Requests Register 0x8007 EFA4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LO D L2 L3 L4 L5 L6 L7 L8 L Lio Li To Lig Li4 os RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 10 3 3 Interrupt Enable Register The interrupt enable register IRQENABLE is a read write register The bits in this reg ister are affected only by writes from the CPU or other bus master and by reset IRQENABLE Interrupt Enable Re
51. 10 Base address 5 10 of l bus memory block See IMEMBASE of L bus memory block See LMEMBASE registers chip select 5 5 BB 2 4 4 3 4 8 BDIP 2 10 3 2 4 2 4 9 4 11 5 18 5 29 BE 2 6 4 2 4 3 4 8 4 15 5 10 and chip selects 5 17 BG 2 3 4 3 4 8 BI 2 7 4 2 4 11 Block size 5 8 5 10 BMCR 3 10 BME 3 10 7 6 BMLK 7 6 BMT 7 5 7 7 BR 2 2 4 3 4 8 BSIZE 5 8 5 10 Buffers I O 2 1 BURST 2 5 4 2 4 8 Burst cycles 4 10 SIU REFERENCE MANUAL For More Information On This Product INDEX data in progress See BDIP inhibit cycles 4 11 See also BI interface 5 29 transfers 5 32 type 1 5 19 type 2 5 20 Burstable device 5 18 Bus busy See BB Bus cycle address phase 4 8 arbitration phase 4 8 data phase 4 9 Bus grant See BG Bus monitor 7 5 and debug mode 3 10 enable 7 6 enable bit BME 3 10 lock 7 6 timing 7 5 7 7 Bus request See BR BYTE 5 10 5 17 Byte enables See BE GE Cache inhibit 5 9 5 14 Cancel reseration See CR CE 5 1 Charge pump 6 6 Checkstop reset 4 16 5 13 8 2 enable 3 2 Chip enable See CE Chip selects 5 1 address map 5 5 base address registers 5 5 block diagram 5 2 multi level protection 5 11 of system boot memory See CSBOOT option registers 5 6 regions 5 10 reset operation 5 33 See alsoCS CI 5 9 5 14 CLKOUT 2 14 4 3 6 1 6 3 frequency control 6 8 Clock mode See MODCLK Clock module 6 1 Configuration of SIU PCU 3 1 INDEX MOTOROLA l 1 Go
52. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IEN LIX RESERVED IMEMBASE RESERVED RESET i 1 0 0 0 0 0 0 3 0 0 0 0 0 0 Reset value depends on the value of the data bus configuration word during reset Table 3 2 MEMMAP Bit Settings Bit s Name Description 0 LEN L bus memory enable 0 L bus memory disabled 1 L bus memory enabled Reset state depends on the value of the data bus configuration word 1 7 Reserved 8 9 LMEMBASE Base address of the L bus memory block 00 Starting address is 0x0000 0000 01 Ending address is 0x000F FFFF 10 Starting address is OxFFFO 0000 11 Ending address is OxFFFF FFFF Reset value depends on the data bus configuration word 10 15 Reserved 16 IEN l bus memory enable For MCUs with no l bus memory this bit has no effect 0 l bus memory disabled 1 l bus memory enabled 17 LIX L bus to l bus cross bus access enable 0 Disable data accesses to l bus memory 1 Enable data accesses to l bus memory reset value 18 23 Reserved 24 25 IMEMBASE Base address of the l bus memory block 00 Starting address is 0x0000 0000 01 Ending address is 0x000F FFFF 10 Starting address is OxFFFO 0000 11 Ending address is OxFFFF FFFF Reset state depends on the data bus configuration word 26 31 Reserved Notice that if l bus memory and L bus memory are assigned the same region and both are enabled the har
53. 2 13 14 15 0 0 0 0 0 0 SWE SWLK SWTC RESET 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SWTC RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 7 8 SWCR SWTC Bit Settings Bit s Name Description 0 5 Reserved 6 SWE Software watchdog enable 0 Disable watchdog counter 1 Enable watchdog counter 7 SWLK Software watchdog lock 0 Enable changes to SWLK SWE SWTC 1 Ignore writes to SWLK SWE SWTC 8 31 SWTC Software watchdog timing count This 24 bit register contains the count for the software watch dog timer which counts at system clock frequency If this register is loaded with zero the maxi mum time out is programmed 7 5 3 Software Watchdog Register The software watchdog register SWR is a read only register that shows the current value of the software watchdog down counter Writes to this register have no effect SWR Software Watchdog Register 0x8007 EFC8 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED SWR RESET Kea KK dE K e SE DE VER SA E i Ae A a a Ve VE GE a OS GE AAS MOTOROLA SYSTEM PROTECTION SIU 7 8 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 8 RESET OPERATION Reset procedures handle system initialization and recovery from catastrophic failure MPC500 family microcontrollers
54. 2 4 6 Watchpoints WP 0 5 Output only Module Development support State Meaning Asserted lIndicate that a watchpoint event has occurred on the I bus WP 0 3 or L bus WP 4 5 Negated Indicate that no watchpoint event has occurred Timing Comments _Assertion Negation Transitions may occur every clock cy cle This signal is not synchronous with bus cycles Refer to the RCPU Reference Manual RCPURM AD for more in formation on these signals 2 2 5 Chip Select Signals 2 2 5 1 Chip Select for System Boot Memory CSBOOT Input only Module Chip selects State Meaning Asserted lIndicates the boot memory device is being se lected In systems that have no external boot device this pin can be configured as a write enable or output enable of an external memory device At power up this pin defaults as a chip enable of the boot device Negated Indicates the boot device is not being selected SIU SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product 2 13 Go to www freescale com Freescale Semiconductor Inc Timing Comments _Assertion Negation This is an address phase signal when used as chip enable of the boot device or a data phase sig nal when used as output enable or write enable of an exter nal memory device When this signal is a chip enable assertion may be delayed from the assertion of TS 2 2 5 2 Chip Selects for External Memory CS 0 11 Output only Module Chip
55. 2 summarizes the conditions under which internal reset is released for each clock mode Table 8 2 Reset Behavior for Different Clock Modes Clock Mode VDDSN MODCLK Internal DATA19 1 at Reset Internal DATA19 0 at Reset Normal operation 1 1 Release internal reset 15 for an Release internal reset when PLL internal reset source or 17 for is locked and 15 for an internal an external reset clocks after reset source or 17 for an exter RESET is negated nal reset clocks after RESET is negated OR when timeout value in the time base register has ex pired whichever occurs first 1 1 mode 1 0 Release internal reset when PLL is locked and 15 for an internal re set source or 17 for an external reset clocks after RESET is negat ed SPLL bypass 0 1 Release internal reset 15 for an internal reset source or 17 for an mode external reset clocks after RESET is negated MOTOROLA RESET OPERATION SIU 8 6 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 8 2 Reset Behavior for Different Clock Modes Continued Clock Mode Vopen MODCLK Internal DATA19 1 at Reset Internal DATA19 0 at Reset Special test mode 0 0 Release internal reset 15 for an internal reset source or 17 for an external reset clocks after RESET is negated 8 3 Configuration During Reset Many SIU pins can have more than one function The logic
56. 28 Reserved 29 SPLSS System PLL lock status sticky bit 0 PLL has gone out of lock since software last set this bit 1 PLL has remained in lock since software last set this bit 30 SPLS System PLL lock status 0 PLL has not locked 1 PLL has locked 31 LOO Loss of oscillator status 0 Clock detected 1 Crystal not detected MOTOROLA CLOCK SUBMODULE SIU 6 18 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 7 SYSTEM PROTECTION This section describes the system protection features provided by the SIU and the PCU These features include a periodic interrupt timer and a bus monitor located in the SIU and a software watchdog located in the PCU Additional SIU system protection features include the PowerPC decrementer and time base Basic operation of the time base and decrementer is described in the RCPU Ref erence Manual RCPURM AD SECTION 6 CLOCK SUBMODULE provides details of how the SIU implements the time base and decrementer 7 1 System Protection Features e The bus monitor monitors any internal to external bus accesses Four selectable response time periods are available ranging from 16 to 256 system clock cycles An internal bus error signal is generated if a bus time out occurs e The periodic interrupt timer generates an interrupt after a period specified by the user e The software watchdog issues a reset if software does not update the softw
57. 3 If both regions are under chip select control the delays of both regions are known to the chip select logic and the interface type of the first region supports pipelining then the second access if a read can be pipelined with the first 4 For any two consecutive accesses if the latency of either region is not known to the chip select logic the two accesses are pipelined only if the second ac SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 23 Go to www freescale com 9 Freescale Semiconductor Inc cess is aread access to a region with an interface type that can hold off the data until the data bus is available See Table 5 12 For example suppose the first access is to a region that supplies its own TA signal the second access is to another region with ITYPE 8 and TA is re turned by the chip select logic for the second access In this case the chip se lect logic must hold off the second access until the first access is completed because the second region may not be able to hold off its data without an OE On the other hand suppose the first access is to a region that supplies its own TA signal the second access is to another region with ITYPE 3 synchronous OE and TA is returned by the chip select logic for the second access In this case the second region can hold off its data until its OE is asserted The chip select module can pipeline the second access if a read with the
58. 6 11 lock 6 17 mask 6 16 select bits 6 16 LPM 6 11 6 16 LPML 6 11 6 12 6 17 LPMM 6 12 6 16 LSHOW 3 2 LST 3 2 4 11 lwarx 4 19 Machine check exception 4 16 5 13 SIU REFERENCE MANUAL For More Information On This Product Go to www freescale com MASK 4 14 MASKNUM 3 2 MEMMAP 3 2 3 6 3 8 Memory block mapping 3 6 Memory mapping register See MEMMAP Memory regions 5 10 MF 6 8 6 16 lock bit 6 9 6 17 MFD 6 7 MODCLK 2 15 6 3 Module select logic 3 4 MPL 6 9 6 12 6 17 Multi level protection 5 11 Multiplication factor 6 8 6 16 divider 6 7 N Non speculative base address register See SPECADDR mask register See SPECMASK O OE 5 1 5 19 One to one mode 6 9 Oscillator 6 5 loss of 6 18 8 2 Output enable See OE Overlapped accesses 5 18 5 20 P PA 2 16 PAPAR 9 3 PARTNUM 3 2 PB 2 16 PBPAR 9 3 PCFS 7 2 7 5 PCON 5 3 5 9 5 16 PCU address map 1 6 block diagram 1 5 module configuration register See PCUMCR PCUMCR 3 3 PDWU 2 15 6 3 6 13 Pending interrupt request register See IRQPEND Periodic interrupt enable bit 3 10 Periodic interrupt timer See PIT Peripheral control unit See PCU Phase detector 6 6 Phase locked loop See PLL PI 2 16 PIE 3 10 7 2 7 4 7 5 Pin assignment registers 9 1 Pin characteristics 2 1 Pin configuration field See PCON PIPAR 9 5 Pipelined accesses 4 6 5 18 5 21 INDEX MOTOROLA l 3 Freescale Semiconductor Inc to different regions 5 23 to the sam
59. 6 16 6 10 SCLSR BItSEttiNgS toto ve cosas a CES 6 17 7 1 SIU System Protection Address Map 7 1 7 2 PCU System Protection Address Map 7 1 7 3 PCES ENCOdINGS EE 7 3 7 4 Recommended Settings for PCEGIOZ EE 7 3 7 5 Example PIT Time Out Periods kk 7 3 7 6 PIGSR BitSetting EE 7 5 7 7 BMCR e 2 5525 aos a ana aeaa ln as Gere vate Ae 7 6 7 8 SWCR SWTC Bit EIDEN deeg Ee eg 7 8 8 1 Reset Status Register Bit Settings cccceeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 8 2 8 2 Reset Behavior for Different Clock Modes sssesssessesrrrnnesssrrrrnnesssrren 8 6 8 3 Pin Configuration During AGS Cle ic ce Eessen Suter codd See d i eedt 8 7 8 4 Data Bus Reset Configuration Word 8 8 9 1 SIU Port Registers Address Map 9 1 10 1 IMB2 Interrupt Multiplexing snssseeeeenneneeeeeennnnnnnnsennnnnnensenennnnnnnennnnnnnnnenne 10 6 10 2 Interrupt Controller Registers ene 10 6 10 3 PITQIL Bit Seting Sine A E AA 10 8 10 4 Port Q Pin elen 1 10 9 10 5 Port Q Edge Select Field Encodmg EEN 10 10 MOTOROLA SIU XII For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc PREFACE This manual defines the functionality of the system interface unit SIU and peripherals control unit PCU The SIU and PCU are modules in the Motorola MPC500 family of microcontrollers MCUs MPC500 family microcontrollers contain an SIU PCU RCPU a powerPC based processor and optional on chip memory and periphe
60. 6 family MCUs connects on chip peripherals to the processor via the LIMB 1 5 PCU Block Diagram Figure 1 3 shows a block diagram of the PCU SIU OVERVIEW MOTOROLA REFERENCE MANUAL For More information On This Product 1 5 Go to www freescale com Freescale Semiconductor Inc L BUS INTERFACE IMB2 ADDR 0 31 ADDRESS INTERFACE DECODE DATA 0 31 DATA MUX ADDR 0 31 SOFTWARE WATCHDOG PORTQ L BUS IMB2 DATA 0 31 TEST INTERRUPT Pop CONTROLLER s a MPC500 PCU BLOCK Figure 1 3 Peripherals Control Unit Block Diagram 1 6 PCU Address Map Table 1 2 shows the address map for the PCU An entry of S in the Access column indicates that the register is accessible in supervisor mode only S U indicates that the register can be programmed to the desired privilege level Test indicates that the register is accessible in test mode only MOTOROLA OVERVIEW SIU 1 6 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 1 2 PCU Address Map Access Address Register S 0x8007 EF80 PERIPHERAL CONTROL UNIT MODULE CONFIGURATION REGISTER PCUMCR 0x8007 EF84 RESERVED 0x8007 EF8C Test 0x8007 EF90 TEST CONTROL REGISTER TEST CONTROL REGISTER TSTMSRA TSTMSRB Test 0x8007 EF94 TEST CONTROL REGISTER TEST CONTROL REGISTER TSTCNTRAB TSTREPS Test 0x8007 EF98 T
61. BURST TEA AACK TA Handshake Pins PORTI 0 7 BE 0 3 18 CR BI BR BB BG ARETRY Bus control pins bus arbitration PM 2 7 pins ARETRY 19 Release reset when PLL locked Release internal reset 15 clock cy Release internal reset when PLL cles for internal reset sources or locked and 15 clock cycles for in 17 clock cycles for external reset ternal reset sources or 17 clock cy sources after RESET negated ex cles for external reset sources cept in PLL 1 1 mode after RESET negated OR when timeout value in the timebase regis ter has expired whichever occurs first during normal mode only 20 Reserved 21 Reset Configuration Source Latch Configuration from external Latch configuration from internal For DATA 22 31 pins defaults 22 Reserved 23 IEN l bus memory modules are en l bus memory modules are dis abled abled and emulated externally 24 LEN L bus memory modules are en L bus memory modules are dis abled abled and emulated externally 25 PRUMODE Forces accesses to Ports A B I J No effect K and L to go external 26 ADDR 12 15 ADDR 12 15 PB 4 7 27 Reserved 28 Reserved 29 Reserved 30 Test slave mode enable Test slave mode disabled Test slave mode enabled 31 Test Transparent Test transparent mode disabled Test transparent mode enabled Mode Enable SIU RESET OPERATION MOTOROLA REFERENCE MANUAL 8 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 4 P
62. Bus Cycle GE 4 8 4 5 1 Arbitration Phase dee eben eet 4 8 4 5 2 Address PINGS Oi enee Eeer 4 8 4 5 3 aber e 4 9 4 6 BUISUOCYCIOS ebe EE Ee 4 10 4 6 1 Termination of EISEM 4 11 4 6 2 Burst Inhibit Cycles EE 4 11 4 7 Decomposed Cycles and Address Wrapping c ccccceseceeeeeeeeeeeeneeees 4 12 4 8 Preventing Speculative LoadS EEN 4 13 4 9 Accesses 10 1 G Bil POMS rosee aaae iaaa a Ea AAAA an dncseeanss 4 15 4 10 gt Address ROU EE 4 16 4 11 Transfer Error Acknowledge Cycles ccceeeeeeeeeeeeeeeeeeeeeeneeeeeeeeteees 4 16 BAZ Gyele KEE 4 17 ANS e e e 4 18 4 14 Storage Reservation Support EEN 4 19 4 14 1 PowerPC Architecture Reservation Requirements 0 0ee 4 20 4 14 2 E bus Storage Reservation Implementation sssnsseneeeeeeeeeeeeeeeeee 4 20 4 14 3 Reservation Storage Signals ccccccceeseeeeeeeeeeeeeneeeeeeeeeeeeeneeeees 4 21 SECTION 5 CHIP SELECTS 5 1 Chip Select Module Features base 5 1 5 2 Chip Select Block Diagram cceceeeeeeeeeeeeeeeeeeeeneeeeeeeeeeeeceeeeeeeeeeeaaees 5 2 5 3 Chip Select LEE 5 3 5 4 Chip Select Registers and Address Map ceeeeeceeeeeeeeeeeeeeeeeeeeeeeaeees 5 4 5 4 1 Chip Select Base Address Registers cecceeceeeeeeeeeeeeeeeeeeeeneaeees 5 5 5 4 2 Chip Select Option Registers cccccccessseeccceeeeeeessseeeeeeeeeeseeeees 5 6 5 5 Chip Select Te de EE 5 10 5 6 Multi Level Protection EE 5 11 5 6 1 Main Block and Sub Block Pa
63. C CS0 OPTION REGISTER CSORO DN DN ON MO DO MD DOD MD Di DN OD ND OD DN MD OD DM OD DM MD MW mM WM w 0x8007 FDFO CSBOOT SUB BLOCK BASE ADDRESS REGISTER CS BTSBBAR S 0x8007 FDF4 CSBOOT SUB BLOCK OPTION REGISTER CSBTSBOR S 0x8007 FDF8 CSBOOT BASE ADDRESS REGISTER CSBTBAR S 0x8007 FDFC CSBOOT OPTION REGISTER CSBTOR 5 4 1 Chip Select Base Address Registers Base address registers contain the base address of the range of memory to which the chip select circuit responds All base address registers contain the same fields but have different reset values SIU CHIP SELECTS REFERENCE MANUAL MOTOROLA For More Information On This Product 5 5 Go to www freescale com Freescale Semiconductor Inc CSBTBAR CSBOOT Base Address Register 0x8007 FDF8 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BA RESERVED RESET IP IP IP IP IP IP IP IP IP IP IP IP 0 0 0 0 00 000000000 0 0 0 0 0 The reset value of the BA field in the CSBTBAR equals 0x00000 if the exception prefix IP bit in the MSR is zero default and OxFFFOO if IP equals one CSBTSBBAR CSBOOT Sub Block Base Address Register 0x8007 FDFO CSBAR1 CS1 Base Address Register 0x8007 FDEO CSBAR2 CS2 Base Address Register 0x8007 FDD8 CSBAR3 CS3 Base Address Register 0x8007 FDDO CSBAR4 CS4 Base Address Register 0x8007 FDC8 CSBAR5 CS5 Base Address Register 0x8
64. CE FN DATA PHASE TERMINATES OE SYNCHRONOUS 1 ENABLE DATA OUTPUT DATA C n T DEVICE 3 STATE ITS BACK my DRIVERS FROM CLOCK EDGE TA 0 ONE WAIT STATE A UNDEFINED DON T CARE MPC500 SYNC RD EOL TIM Figure 5 12 Synchronous Read with Early Overlap One Wait State 5 16 6 Synchronous Burst Interface The chip select module supports two types of burst interfaces The type 1 burst inter face uses the output enable and the write enable to control the data being driven out or received The type 1 burst interface also requires a BDIP signal to control when the region should output the next beat of the burst For the read case the type 2 burst interface does not require an output enable signal Instead it uses a LAST signal When this signal is asserted at the rising edge of the clock the type 2 burst device places its output buffers in a high impedance state fol lowing the clock edge The CE of the type 2 burst must be valid for the duration of the device s access latency or wait states This type of device also requires a signal with timing similar to that of the TS signal The interface may or may not contain an OE sig nal Any access to a device with type 2 burst interface must be made using chip selects and the ACKEN bit in the option register for the chip select must be set NOTE The LAST and BDIP signals share the same pin The LST bit in the SIU module configuration register SIUMCR sp
65. CSOR4 S 0x8007 FDDO CS3 BASE ADDRESS REGISTER CSBAR3 MOTOROLA OVERVIEW 1 4 For More Information On This Product Go to www freescale com SIU REFERENCE MANUAL Freescale Semiconductor Inc Table 1 1 SIU Address Map Continued Access Address Register S 0x8007 FDD4 CS3 OPTION REGISTER 3 CSOR3 S 0x8007 FDD8 CS2 BASE ADDRESS REGISTER 2 CSBAR2 S 0x8007 FDDC CS2 OPTION REGISTER 2 CSOR2 S 0x8007 FDEO CS1 BASE ADDRESS REGISTER CSBAR1 S 0x8007 FDE4 CS1 OPTION REGISTER CSOR1 S 0x8007 FDE8 RESERVED S 0x8007 FDEC CSO OPTION REGISTER CSORO0 S 0x8007 FDFO CSBOOT SUB BLOCK BASE ADDRESS REGISTER CSBTSBBAR S 0x8007 FDF4 CSBOOT SUB BLOCK OPTION REGISTER CSBTSBOR S 0x8007 FDF8 CSBOOT BASE ADDRESS REGISTER CSBTBAR S 0x8007 FDFC CSBOOT OPTION REGISTER CSBTOR 1 4 Peripheral Control Unit Overview The peripheral control unit PCU consists of the following submodules e Software watchdog provides system protection e Interrupt controller controls the interrupts that external peripherals and internal modules send to the CPU e Port Q provides for digital UO on pins that are not being used as interrupt in puts e Test submodule allows factory testing of the MCU e L bus IMB2 interface LIMB provides an interface between the load store bus and the second generation intermodule bus IMB2 The IMB2 which is compa rable to the IMB on modular M68300 and M68HC1
66. DDR 0 16 0101 64 K ADDR 0 15 0110 128 K ADDR 0 14 0111 256 K ADDR 0 13 1000 512K ADDR 0 12 1001 1M ADDR 0 11 1010 2M ADDR 0 10 1011 4M ADDR 0 9 1100 8 M ADDR 0 8 1101 16 M ADDR 0 7 1110 32 M ADDR 0 6 1111 64 M ADDR 0 5 Since the address decode logic of the chip select uses only the most significant ad dress bits to determine an address match within its block size the value of the base address must be a multiple of the corresponding block size Although the base address registers can be programmed to be any address within the address map the user must avoid programming these registers to values that overlap the addresses of internal modules At power on time the address of the boot device may match that of an internal module because a system can have on chip EPROM for instructions If this occurs the internal access overrides the external access That is the internal access provides the boot instructions and the chip select unit does not run an external cycle The reset value of the BA field in the CSBOOT base address register depends on the value of the exception prefix IP bit in the machine state register Refer to the RCPU Reference Manual RCPURM AD for a description of the machine state register 5 6 Multi Level Protection SIU REFERENCE MANUAL The chip select unit allows protection for an address space within another address space Figure 5 3 illustrates this concept CHIP SELECTS
67. DIP 3 Interface Type ITYPE 001 ITYPE 1000 for Asynchronous Synchronous burst CSBOOT Time to Hi Z 2Clk 4 CSBOOT Port Size 32 Bit 16 Bit 5 Reset Configuration Source Latch configuration from external Latch configuration from internal For DATA 6 13 pins defaults MOTOROLA RESET OPERATION SIU 8 8 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 8 4 Data Bus Reset Configuration Word Continued Data Bus Configuration Function Effect of Mode Select 1 Effect of Mode Select 0 Bit Affected During Reset During Reset 6 8 TA Delay For CSBOOT TA Delay Encoding of Wait States TADLY 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 9 10 IMEMBASE 0 1 IMEMBASE Block Placement 00 Start Addr 0x0000 0000 01 End Addr 0x000F FFFF 10 Start Addr OxFFFO 0000 11 End Addr OxFFFF FFFF 11 12 LMEMBASE 0 1 LMEMBASE SRAM Block Placement 00 Start address 0x0000 0000 01 End address 0x000F FFFF 10 Start address OxFFFO 0000 11 End address OxFFFF FFFF 13 Reset configuration source for Latch configuration from external Latch configuration from internal DATA 14 21 pins defaults 14 CT 0 3 AT 0 1 TS CT 0 3 AT 0 1 TS PJ 1 7 15 WR BDIP WR BDIP PK 0 1 16 PLLL DSDO VF 0 2 DSDO pipe tracking watchpoints PK 2 7 PL 2 7 VFLS 0 1 WP 1 5 17
68. E 0 6 fields PQPAR Port Q Pin Assignment Register 0x8007 EFD4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PQPAO PQEDGE0 PQPA1 PQEDGE1 PQPA2 PQEDGE2 PQPA3 PQEDGE3 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PQPA4 PQEDGE4 PQPAS PQEDGE5 PQPA6 PQEDGE6 PQPA7 PQEDGE7 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 10 4 2 1 Port Q Pin Assignment Fields The port Q pin assignment PQPA 0 7 fields select the basic function of each port Q pin as shown in Table 10 4 Table 10 4 Port Q Pin Assignments PQPA Value Pin Function PORTQ Port Q Data Field Interrupt Request Source 0b00 General Purpose Input A read returns the state of the pin None A write has no effect 0b01 General Purpose Output A read returns the value in the None latch A write drives the value in the latch onto the pin 0b10 TRQ to CPU A read returns the state of the pin From pin if PQEDG field is set to A write has no effect Level otherwise from port Q edge detect logic SIU INTERRUPT CONTROLLER AND PORT Q MOTOROLA REFERENCE MANUAL For More Information On This Product 10 9 Go to www freescale com Freescale Semiconductor Inc Table 10 4 Port Q Pin Assignments PQPA Value Pin Function PORTQ Port Q Data Field Interrupt Request Source 0b11 TRQ to Interrupt Controller A read returns the state of the pin From pi
69. ERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 7 6 PICSR Bit Settings Bit s Name Description 0 Reserved 1 PTE Periodic timer enable 0 Disable decrementer counter 1 Enable decrementer counter 2 PIE Periodic interrupt enable 0 Disable periodic interrupt 1 Enable periodic interrupt 3 4 Reserved 5 7 PCFS PIT clock frequency select To achieve PIT setting of approximately 1 MHz program the PCFS field as shown in Table 7 4 8 14 Reserved 15 PS PIT status 0 No PIT interrupt asserted 1 Periodic interrupt asserted 16 31 PITC Periodic interrupt timing count Number of counts to load into the PIT 7 3 6 Periodic Interrupt Timer Register The periodic interrupt timer PIT register is a read only register that shows the current value in the periodic interrupt down counter Writes to this register have no effect Reads of the register do not affect the counter PIT Periodic Interrupt Timer Register 0x8007 FC44 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED PIT RESET UNDEFINED 7 4 Hardware Bus Monitor Typical bus systems require a bus monitor to detect excessively long data and address acknowledge response times The SIU provides a bus monitor to monitor internal to external bus accesses on the E bus If the external bus pip
70. EST CONTROL REGISTER TEST CONTROL REGISTER TSTCREG1 TSTCREG2 Test 0x8007 EF9C TEST CONTROL REGISTER RESERVED TSTDREG S 0x8007 EFAO PENDING INTERRUPT REQUEST REGISTER IRQPEND S 0x8007 EFA4 ENABLED ACTIVE INTERRUPT REQUEST REGISTER IRQAND S 0x8007 EFA8 INTERRUPT ENABLE REGISTER IRQENABLE S 0x8007 EFAC PIT PORT Q INTERRUPT LEVEL REGISTER PITQIL 0x8007 EFBO 0x8007 EFBC RESERVED SOFTWARE SERVICE REGISTER RESERVED 0x8007 EFCO SWSR S 0x8007 EFC4 SOFTWARE WATCHDOG CONTROL FIELD TIMING COUNT SWCR SWTC S U 0x8007 EFC8 SOFTWARE WATCHDOG REGISTER 0x8007 EFCC RESERVED S U 0x8007 EFDO PORT Q EDGE DETECT DATA RESERVED PQEDGDAT S 0x8007 EFD4 PORT Q PIN ASSIGNMENT REGISTER PQPAR 0x8007 EFD8 RESERVED 0x8007 EFFC SIU OVERVIEW MOTOROLA REFERENCE MANUAL For More Information On This Product 1 7 Go to www freescale com Freescale Semiconductor Inc MOTOROLA OVERVIEW SIU 1 8 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 2 SIGNAL DESCRIPTIONS The tables in this section summarize functional characteristics of the pins found on MPC500 family microcontrollers For a more detailed discussion of a particular signal refer to the section of this manual that discusses the function involved 2 1 Pin Characteristics Table 2 1 shows the characteristics of each pin on the MCU Assume the model for output
71. Freescale Semiconductor Inc SIU SYSTEM INTERFACE UNIT REFERENCE MANUAL This document contains information on a new product under development Motorola reserves the right to change or discontinue this product without notice Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document PowerPC microcontrollers embody the intellectual property of IBM and of Motorola However neither party assumes any responsibility or liability as to any aspects of the per formance operation or other attributes of the microprocessor as marketed by the other party Neither party is to be considered an agent or representative of the other party and neither has granted any right or authority to the other to assume or create any express or implied obligations on its behalf Information such as data sheets as well as sales terms and conditions such as prices schedules and support for the microprocessor may vary as between IBM and Motorola Accordingly customers wishing to learn more information about the products as marketed by a given party should contact that party Motorola reserves the right to modify this manual and or any of the products as described herein without further notice Nothing in this manual nor in any o
72. G DRIVEN BY ANOTHER SLAVE RECEIVE ADDRESS CAN SLAVE PIPELINE y MASTER ASSERT ADDRESS ACKNOWLEDGE ASSERT BUS BUSY E ee y LATCH DATA ASSERT TRANSFER START 7 E ASSERT TRANSFER ACKNOWLEDGE DRIVE ADDRESS In AND ATTRIBUTES eT ADDRESS DRIVE DATA In APADT ASSERTED KNOWLED ASSERT ADDRESS ACKNOWLEDGE RECEIVED ACKNOWLEDGE MPC500 WR CYC FLOW TRANSFER COMPLETE Figure 4 3 Flow Diagram of a Single Write Cycle 4 4 Basic Pipeline The EBI supports a maximum pipeline depth of two that is up to two addresses can be active on a bus at the same time Pipelining is simplified by using SIU chip selects since chip select registers can have the information about the characteristics of each external memory SECTION 5 CHIP SELECTS discusses which cycles can be pipe lined The EBI supports pipelined accesses for read cycles only A write bus cycle starts only when the pipe depth is zero or would have gone to zero if a new cycle had not started A read bus cycle will start when the pipe depth is either zero or one or would have gone to one if a new cycle had not started EXTERNAL BUS INTERFACE SIU REFERENCE MANUAL MOTOROLA 4 6 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc An example of bus pipelining is shown in Figure 4 4 CLKOUT
73. L BUS STATIC RAM SRAM INTERNAL INSTRUCTION BUS I BUS E f 4 KBYTE E LCACHE DEVELOPMENT DEVELOPMENT SUPPORT PORT MPC500 BLOCK Figure 1 1 MPC500 Family MCU Block Diagram 1 1 SIU Overview The SIU consists of modules that control the buses of the chip provide the clocks and provide miscellaneous functions for the system such as chip selects test control re set control and I O ports SIU based microcontrollers MCUs have an internal Harvard architecture and a single external bus The internal buses are the instruction bus l bus and the load store bus L bus The external bus interface EBI connects each of these internal buses with the external bus E bus The chip select block provides user programmable chip se lects to select external memory or peripherals The clock block controls the generation of the system clocks and such features as programmability of the clocks and low pow er modes The reset control function interfaces to the reset pins and provides a reset MOTOROLA OVERVIEW SIU 1 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc status register The I O ports provide untimed I O functions on pins that are not used for their primary function 1 2 SIU Block Diagram A block diagram of the SIU is shown in Figure 1 2 CHIP SELECTS L DATA L BUS L BUS e gt BIU E BUS lt i
74. LA For More Information On This Product 2 3 Go to www freescale com 2 Freescale Semiconductor Inc 2 2 1 3 Bus Busy BB Input Output Module ER State Meaning Asserted The current bus master asserts this signal to in dicate the bus is currently in use The prospective new master must wait until the current master negates this sig nal Negated Indicates that the bus is not owned by another bus master and that the bus is available to the MCU when accompanied by a qualified bus grant Timing Comments Assertion BB is asserted during the address phase of each external bus cycle if it was previously negated It re mains asserted between internal atomic cycles any non burst word accesses to an external 16 bit port Negation Occurs during the clock cycle following termina tion of the data phase of an external bus cycle The signal is negated for half a clock cycle and then placed in a high impedance state 2 2 1 4 Cancel Reservation CR Input only Module ER State Meaning Asserted By an external bus arbiter or reservation snooping logic indicates that there is no outstanding reser vation on the external bus Each RCPU has its own CR sig nal Assertion indicates that the processor should not perform any stwex cycle to external memory Negated Indicates there is an outstanding reservation on the external bus Timing Comments Assertion Can occur at any rising edge of the bus clock This sig
75. LL lock status SPLS bit in the SCSLR to determine lock status The RFD bits should always be written to a value of 0x1 or greater before changing the MF bits to ensure the system frequency does not exceed the system s design mar gin since the VCO overshoots in frequency as it tries to compensate for the change in frequency For example to change from the default system frequency to 16 MHz write the RFD bits to 0x1 then write the MF bits to 0x0 After the PLL locks write the RFD bits to 0x0 When the PLL is operating in one to one mode the multiplication factor is set to one and MEF is ignored Figure 6 2 shows how the PLL uses the MF bits to multiply the input crystal frequency The output of the VCO is divided down to generate the feedback signal to the phase comparator The MF bits control the value of the divider in the PLL feedback loop The phase comparator determines the phase shift between the feedback signal and the reference clock This difference results in either an increase or decrease in the VCO output frequency 6 5 2 RFD 0 3 Reduced Frequency Divider The RFD bits control a prescaler at the output of the PLL The reset state of the RFD bits is 0x3 which divides the output of the VCO by eight SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Product 6 9 Go to www freescale com Freescale Semiconductor Inc These bits can be changed without affecting the PLL s VCO i e no re lock
76. MOTOROLA For More Information On This Product 5 11 Go to www freescale com Freescale Semiconductor Inc MAIN BLOCK HIGH ADDRESS MAIN BLOCK SUB BLOCK HIGH ADDRESS HAS ITS OWN PROTECTION SUB BLOCK SUB BLOCK LOW ADDRESS MAIN BLOCK LOW ADDRESS SUB BLOCK HAS ITS OWN PROTECTION AND OVERRIDES THE MAIN BLOCK S PROTECTION MPC500 BLOCK PROT MAP Figure 5 3 Multi Level Protection Figure 5 3 shows a sub block contained within a main block The main block and the sub block can have different protection mechanisms programmed For example the user can have a separate data space and instruction space within a single chip select region The block size of the sub block should be less than the block size of the main block The protection of the smaller block overrides the protection of the main block 5 6 1 Main Block and Sub Block Pairings Multi level protection is accomplished using a paired set of chip select decoding cir cuits The decoding pairs are specified in Table 5 6 Table 5 6 Main Block and Sub Block Pairings Main Block Sub Block CSBOOT CS1 CS2 CS3 CS4 CS5 lf the address of an access falls within a sub block the protection of the sub block overrides that of the main block The sub block decoding logic overrides the decoding logic of the main block If all match conditions are met the chip select pin of the main block is asserted Notice that only CSBOOT and CS 1
77. N XFCP interrupts 10 5 memory cache hit 4 18 reset 8 2 8 4 F Freeze and time base decrementer 6 14 Frequency control 6 8 D General purpose I O 9 1 H Hold off data 5 18 I O general purpose 9 1 l bus 3 4 memory 3 6 4 18 enable 3 3 IEN 3 3 IMB2 interrupts 10 5 l mem See l bus memory IMEMBASE 3 3 3 6 3 8 Instruction fetch visibility signals See VF Interface type See ITYPE Internal default mode 8 8 interrupts 10 8 memory mapping 3 8 reset flow 8 6 Interrupt controller 10 1 10 3 enable register See IRQENABLE external 10 5 See also IRQ IMB2 10 5 internal 10 8 PIT 10 5 request levels 10 5 10 8 INDEX SIU REFERENCE MANUAL Freescale Semiconductor Inc register See PITQIL request multiplexer control 3 4 sources 10 2 IP 5 6 5 11 IRQ 2 17 10 8 IRQAND 10 6 10 7 IRQENABLE 10 6 10 7 IRQMUX 3 4 10 6 IRQPEND 10 6 ISCTL 4 18 ITYPE 5 10 5 17 5 18 j JTAG reset 8 2 pe LAST 3 2 4 11 5 18 5 20 5 29 L bus 3 4 IMB2 interface 3 4 memory 3 6 enable 3 3 show cycles 3 2 to l bus cross bus access enable 3 3 L bus memory 4 18 LEN 3 3 LIMB 3 4 LIX 3 3 3 9 L mem See L bus memory LMEMBASE 3 3 3 6 3 8 Lock bits and freeze assertion 3 10 Lock PLL 8 2 status 6 14 LOK 3 2 5 4 LOL 8 2 LOLRE 6 9 6 14 6 16 LOO 6 15 6 18 8 2 Loop filter 6 6 LOORE 6 15 6 16 Loss of oscillator 8 2 reset enable 6 15 6 16 status 6 18 Loss of PLL lock 8 2 reset enable 6 9 6 14 6 16 Low power mode
78. NUAL Go to www freescale com Freescale Semiconductor Inc 2 2 6 4 External Filter Capacitor Pins XFCP XFCN Input only Module ER State Meaning Used to add an external capacitor to the filter circuit of the phase locked loop 2 2 6 5 Clock Mode MODCLK Input only Module ER Reset Operation During reset this signal and Vppsn select the source of the system clock Refer to 8 3 Configuration During Reset for details 2 2 6 6 Phase Locked Loop Lock Signal PLLL Output only Module Clocks State Meaning Asserted lIndicates that the phase locked loop is locked Negated Indicates that the phase locked loop is not locked 2 2 6 7 Power Down Wake Up PDWU Output only Module ER State Meaning Asserted Can be used as power down wakeup to exter nal power on reset circuit or assertion can signal other events depending on system requirements PDWU is as serted when bit 0 of the decrementer register changes from 0 to 1 and can also be asserted by software See the RCPU Reference Manual RCPURM AD for details on decre menter exceptions Negated By software indicates the event causing asser tion of PDWU is not or is no longer occurring Timing Comments Negation Does not occur until at least one decrementer clock following assertion 2 2 7 Reset Signals The RESET and RESETOUT signals are used while the part is being placed into or coming out of reset Refer to SECTION 8 RESET OPERATION for more de
79. OOT CS2 and CS4 regions cannot be sub blocks They can only be the main blocks Setting the SBLOCK bit in any of these registers has no effect 5 6 3 Multi Level Protection for CSBOOT The CSBOOT region has a dedicated sub block decoder in addition to its paired sub block decoder CS1 If both sub block decoders are used the CS1 decoder has high er priority than the dedicated sub block decoder That is if an address is contained in both sub blocks the protections specified in the CS1 option register are used If an ad dress is contained in the dedicated sub block and the CSBOOT main block but not the CS1 sub block the protections specified in the CSBOOT sub block option register are used The SBLK bit of the dedicated sub block option register is cleared at power on The bit can be modified after reset if needed The boot region would need to contain enough instructions to reconfigure the chip select registers to provide multi level pro tection shortly after power on 5 7 Access Protection The SUPV DSP and WP bits in the option registers for CSBOOT the CSBOOT sub block and CS 1 5 control access to the address block assigned to the chip select These bits are present in the option registers for chip selects with address decoding logic only they are not present in the option registers for CSO or CS 6 11 In addition the bits take effect only if the chip select is programmed either as a CE or as a sub block If the chip s
80. PA2 PJPA3 PJPA4 PJPA5 PJPA6 PJPA7 RESET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PKPAO PKPA1 PKPA2 PKPA3 PKPA4 PKPA5 PKPA6 PKPA7 PLPAO PLPA1 PLPA2 PLPAS PLPA4 PLPA5 PLPA6 PLPA7 RESET Reset value depends on the value of the data bus configuration word at reset The bits in these registers control the function of the associated pins Setting a bit con figures the corresponding pin as a bus control signal clearing the bit configures the pin as an UO pin Which bus control signals are assigned to port J K and L pins depends on the par ticular microcontroller Refer to the user s manual for the MCU of interest for details 9 5 Port Replacement Unit PRU Mode The entire external bus interface must be supported in order to build an emulator for an MCU The SIU contains support for external port replacement logic which can be used to faithfully replicate on chip ports externally This PRU mode allows system de velopment of a single chip application in expanded mode Access including access time to the port replacement logic can be made transparent to the application soft ware In PRU mode all data data direction and pin assignment registers for ports A B J K and L are mapped externally The SIU does not respond to these accesses allow ing external logic such as a PRU to respond Th
81. Q BLOCK Figure 10 1 Interrupt Structure Block Diagram The interrupt controller does not enforce a priority scheme All interrupt priority is de termined by the software In addition the interrupt controller does not automatically update the interrupt mask upon entering or leaving interrupt processing Any updates to the interrupt mask are the responsibility of software In this way the system is not limited to a particular interrupt priority updating scheme In addition to the interrupt controller on the MCU external peripheral chips in an SIU based system may contain their own interrupt controllers Each interrupt input from an external peripheral chip to the MCU can be routed through the PCU interrupt controller or can be routed directly to the CPU IRQ input This allows the system interrupts to be structured in a cascade where an interrupt controller on an external chip is read only if a certain interrupt on the MCU is serviced or in parallel where all interrupt control lers in the system are read and combined before it is determined which interrupt in the system needs servicing 10 2 Interrupt Sources Sources of interrupt requests to the interrupt controller include the periodic interrupt timer PIT two L bus interrupt request sources and the IRQ 0 6 interrupt request pins The request levels of PIT interrupts IMB2 interrupts and external IRQ 0 2 inter MOTOROLA INTERRUPT CONTROLLER AND PORT Q SIU 10 2 For More Information O
82. RENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CLOCK ts ADDR lt Al J X POSSIBLE A2 CLOCK IN DATA NEXT DATA AT NEXT CLOCK BDIP oe gt 3 LAST DATA D3 DATA DO D1 D2 CLOCK E BUS CLOCK UNDEFINED DONT CARE MPC500 SYNC BWR1 TIM Figure 5 14 Type 1 Synchronous Burst Write Interface Figure 5 15 shows a read access to a type 2 burst interface ITYPE 8 Note that an output enable signal is not required for this type of interface Instead the interface uses the LAST signal SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 31 Go to www freescale com 9 Freescale Semiconductor Inc CLKOUT ADDR 4 LN POSSIBLE A2 POSSIBLE OVER VERLAP ADDRESS LATCHED zk AEN JL 2 WAIT STATES LAST DATA EC CR RT LAST DATA HH ie TA V i S Sm Sm o UNDEFINED DON T CARE MPC500 SYNC BRD2 TIM Figure 5 15 Type 2 Synchronous Burst Read Interface 5 17 Burst Handling The chip select module supports burst accesses with four data beats per burst The following paragraphs describe how the chip select module handles some of the more complex cases e For a single word access to a burstable region the chip select module assert
83. S PIT INTERRUPT COUNTER zai I z A PIE PCFS 2 FREEZE I SEH MPC500 PIT BLOCK Figure 7 1 Periodic Interrupt Timer Block Diagram 7 3 1 PIT Clock Frequency Selection The PIT clock frequency select PCFS field in the PICSR selects the appropriate fre quency for the PIT clock source over a range of external clock or crystal frequencies The bit encodings are shown in Table 7 3 To ensure adequate range for the PIT the input clock signal to the PIT logic should not exceed 4 MHz even if a full frequency input is used instead of an oscillator PLL clocking scheme MOTOROLA SYSTEM PROTECTION SIU 7 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 7 3 PCFS Encodings PCFS Encoding Divide Input Frequency EXTAL by 0b000 4 0b001 8 0b010 16 0b011 32 0b100 64 0b101 Reserved 0b110 Reserved 0b111 Reserved To achieve a PIT setting of approximately 1 MHz program the PCFS field as shown in Table 7 4 Table 7 4 Recommended Settings for PCFS 0 2 Input Frequency Range PCFS 0 2 1 MHz lt FREQ lt 4 MHz 0b000 4 MHz lt FREQ lt 8 MHz 0b001 8 MHz lt FREQ lt 16 MHz 0b010 16 MHz lt FREQ lt 32 MHz 0b011 32 MHz lt FREQ lt 64 MHz 0b100 Reserved 0b101 Reserved 0b110 Reserved 0b111 7 3 2 PIT Time Out Period Selection The PIT time out period is determined
84. S REGISTER RSR 0x8007 FC50 SYSTEM CLOCK CONTROL REGISTER SCCR DM N MO wm 0x8007 FC54 SYSTEM CLOCK LOCK AND STATUS REGISTER SCLSR 0x8007 FC58 0x8007 FC5C RESERVED 0x8007FC60 PORT M DATA DIRECTION DDRM 0x8007FC64 PORT M PIN ASSIGNMENT PMPAR 0x8007FC68 0x8007FC6C 0x8007FC80 PORT M DATA PORTM RESERVED 0x8007FC84 PORT A B PIN ASSIGNMENT PAPAR PBPAR 0x8007FC88 PORT A B DATA PORTA PORTB 0x8007FC8C 0x8007FC94 RESERVED 0x8007FC98 PORT I J K L DATA DIRECTION DDRI DDRJ DDRK DDRL 0x8007FC9C PORT I J K L PIN ASSIGNMENT PIPAR PJPAR PKPAR PLPAR 0x8007FCAO PORT I J K L DATA PORTI PORTJ PORTK PORTL 0x8007 FCA4 0x8007 FD94 RESERVED 0x8007 FD94 0x8007 FD98 CS11 OPTION REGISTER CSOR11 RESERVED 0x8007 FD9C CS10 OPTION REGISTER CSOR10 0x8007 FDAO RESERVED 0x8007 FDA4 CS9 OPTION REGISTER CSOR9Q 0x8007 FDA8 RESERVED 0x8007 FDAC 0x8007 FDBO S8 OPTION REGISTER CSOR8 RESERVED 0x8007 FDB4 CS7 OPTION REGISTER CSOR7 0x8007 FDB8 RESERVED 0x8007 FDBC CS6 OPTION REGISTER CSOR6 0x8007 FDCO CS5 BASE ADDRESS REGISTER 5 CSBARS5 DN DO DM DO DM OM MO MM MM Mm wM 0x8007 FDC4 CS5 OPTION REGISTER CSOR5 S 0x8007 FDC8 S4 BASE ADDRESS REGISTER CSBAR4 S 0x8007 FDCC CS4 OPTION REGISTER
85. Semiconductor Inc 5 18 Chip Select Reset Operation The data bus configuration word specifies how the MCU is configured at reset Table 5 14 summarizes the data bus configuration bits that affect chip selects Table 5 14 Data Bus Configuration Word Settings for Chip Selects Bit s Configuration Function Description Affected 0 Address bus chip selects 0 CS 0 11 ADDR 0 11 configured as address pins 1 CS 0 11 ADDR 0 11 configured as chip select pins default value 1 Exception prefix vector ta 0 Vector table begins at 0x0000 0000 default value ble location 1 Vector table begins at OxFFFO 0000 2 Burst mode type 0 Type 1 burst mode uses BDIP timing default value 0 Type 2 burst mode uses LAST timing 3 ITYPE of boot device 0 Boot device ITYPE 0x08 Synchronous burst 1 Boot device ITYPE 0x01 Asynchronous default value 4 Port size of boot device 0 Boot device has 16 bit port 1 Boot device has 32 bit port default value 6 8 TA delay for CSBOOT 000 0 wait states 001 1 wait state 010 2 wait states 011 3 wait states 100 4 wait states 101 5 wait states 110 6 wait states 111 7 wait states default value REFERENCE MANUAL The boot region can be a ROM or flash EPROM At power on it is assumed that no writing to the region is needed until the chip select logic has been configured Thus no WE is needed at power on time The boo
86. U when one of the following conditions occurs SIU MODULE CONFIGURATION MOTOROLA REFERENCE MANUAL For More Information On This Product 3 9 Go to www freescale com Freescale Semiconductor Inc e Debug mode is entered or e A software debug monitor program is entered as the result of an exception when the associated bit in the debug enable register DER SPR149 is set The following paragraphs explain how the assertion of the freeze signal affects the SIU See the RCPU Reference Manual RCPURM AD for additional details on this signal 3 6 1 Effects of Freeze and Debug Mode on the Bus Monitor When the freeze signal is asserted and debug mode is disabled the bus monitor is unaffected This means that a software monitor must configure the bus monitor to pro vide protection from unterminated bus cycles that occur during debugging When the processor is in debug mode debug mode is enabled and the freeze signal is asserted the bus monitor is enabled The bus monitor is also enabled when debug mode is enabled and a non maskable breakpoint is asserted by the development port These enables override the bus monitor enable bit BME in the bus monitor control register BMCR in the SIU In both cases the bus monitor time out period is whatever was programmed in the BMCR This override allows an external development tool to retain control over the CPU in debug mode by not allowing an external bus cycle to hang the processor in an endless wa
87. UR is cleared when the CPU writes a zero to it Note that to clear the bit it is not necessary to read the bit as a one before writing it as a zero as is required to clear most status bits Note that the WUR bit is not affected by resets and its value should remain as long as the keep alive power is valid At keep alive reset the WUR bit is in an unknown state 6 9 Time Base and Decrementer Support The time base is a timer facility defined by the PowerPC architecture It is a 64 bit free running binary counter which is incremented at a frequency determined by each im plementation of the time base There is no interrupt or other indication generated when the count rolls over The period of the time base depends on the driving frequency The time base is not affected by any resets and should be initialized by software The decrementer is a 32 bit decrementing counter defined by the PowerPC architec ture The decrementer causes an interrupt unless masked by MSR EE when it pass es through zero The decrementer is initialized to OXFFFF FFFF at reset The time base and decrementer use the stand by power supply VDDKAP1 This al lows them to be used while normal power is off The time base and decrementer also continue to function in all low power modes except sleep mode LPM 0b11 in which the oscillator is turned off The state of the decrementer and time base after standby power is restored is indeter minate The decrementer runs cont
88. a chip se includes a data phase for data accesses This cycle is self terminating lect and does not require AACK and TA signals It indicates that an access was made to an address on the external bus and that a cache hit or aborted fetch occurred An instruction access with an address that is an indirect branch target is indicated as a write on the WR signal 0111 Internal register This is an internal visibility cycle It always has an address phase anda data phase This cycle is self terminating and does not require AACK and TA signals It indicates that an access was made to a control regis ter or internal IMB2 address These accesses are always cache inhibit ed 1000 E Mem cache hit These are internal visibility cycles They always have an address phase to CSBOOT region and include a data phase for data accesses These cycles are self ter 1001 E Mem cache minating and do not require AACK and TA signals These encodings in hit to CST region dicate that an access was made to an address on the external bus and 1010 E Mem cache that a cache hit or aborted fetch occurred An instruction access with an hit to CS2 region address that is an indirect branch target is indicated as a write on the 1011 E Mem cache WR signal hit to CS3 region The region indicated is the main chip select region not the sub region 1100 E Mem cache hit to CS4 region 1101 E Mem cache hit to CS5 region 1110 Reserved 1111 Reserved
89. a new manual and there are no changes at this time It has been reformatted for web compatibility SIU SUMMARY OF CHANGES MOTOROLA REFERENCE MANUAL For More Information On This Product S 14 Go to www freescale com lt Freescale Semiconductor Inc This book is a product of the Motorola Advanced Microcontroller Documentation Group in Oak Hill Texas It was written by James Middleton illustrated by Gene Bates and edited by Marilou Groves Camera ready copy and line art were produced with Framemaker 4 running on Macintosh computers The cover was drawn using Adobe Illus trator and Adobe Photoshop for the Macintosh Pre press work on the cover was performed by Imperial Lithograph ics Phoenix Arizona The manual was printed by Banta ISG Spanish Fork Utah under the auspices of the Motorola Semiconductor Products Sector Marketing Services MOTOROLA SUMMARY OF CHANGES SIU S 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Symbol 16 Bit ports 4 15 A AACK 2 6 4 2 4 9 5 15 ACKEN 5 9 5 15 Acknowledge enable 5 9 5 15 ADDR 2 5 4 1 4 8 Address acknowledge signal See AACK bus See also ADDR phase 4 8 retry See ARETRY type See AT wrapping 4 12 Alternate functions of chip select pins 5 3 Arbitration phase 4 8 ARETRY 2 8 4 2 4 9 4 16 4 21 Asynchronous interface 5 18 5 25 with latch enable 5 26 OE 5 19 5 26 AT 2 8 4 2 4 3 4 8 BA 5 6 5
90. a normal external bus cycle Both the address and data phase are seen on the external bus This cycle requires an AACK and a TA sig nal This cycle type is used for sequential fetches and for prefetches of predicted branch targets where the branch condition has not been eval uated before the prefetch It is also used for all non reservation type load store cycles 0001 Reservation start if If the address type is data AT1 0 then this is a data access to the address type is data external bus Both the address and the data phase are seen on the ex ternal bus This cycle requires an AACK and a TA signal When this cy OR cle starts external snooping logic should latch the address to track the Instruction fetch marked reservation as indirect change of flow if ad If the address type is instruction AT 1 then this is an instruction dress fetch cycle marked as an indirect change of flow cycle Both the type is Instruction address and the data phase are seen on the external bus This cycle requires an AACK and a TA signal This cycle type is used when an external address is the destination of a branch instruction or the destination of an exception or VSYNC cycle 0010 Emulation memory select This is a special external bus cycle to emulation memory replacing inter nal l mem or L mem and not resulting in a cache hit Both the address and data phase are seen on the external bus If the address type is in struction AT1 1 and the
91. address is a branch target address this is in dicated as a write on the WR signal Note that there is no indication of whether or not this access is a reservation cycle The user must there fore not allow an external DMA to access this memory when any reser vation may be active This cycle requires AACK and TA signals SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 17 Go to www freescale com Freescale Semiconductor Inc Table 4 10 Cycle Type Encodings Continued CT 0 3 Cycle Type Description 0011 PRU select This is a normal external bus cycle access to a port replacement chip used for emulation support Both the address and the data phase are seen on the external bus This cycle requires an AACK and a TA signal It indicates that an access was made which would have gone to an in ternal port control register if the chip were not operating in PRU mode 0100 LMem These are internal visibility cycles This cycle is self terminating and 0101 L Mem does not require AACK and TA signals These encodings indicate that an access or a cache hit was made to an address on the internal I bus or L bus An instruction access AT1 1 with an address which is an in direct branch target is indicated as a write on the WR signal 0110 E Mem external memory This is an internal visibility cycle It always has an address phase and cache hit not using
92. al glue logic Figure 5 1 is an example of a typical uniprocessor system This kind of system usually consists of a CPU some memories and some peripherals In single master systems the CPU is the only device that can be a bus master on the E bus memories and pe ripherals are slaves MCU INTERNAL MODULE EXTERNAL BUS SIGNALS CPU PERIPHERAL PERIPHERAL L I BUS MPC500 SYS W CS BLOCK Figure 5 1 Simplified Uniprocessor System with Chip Select Logic The chip select module provides the necessary control signals such as the chip en able CE write enable WE and output enable OE for the external memory and peripheral devices In addition the chip select module provides some handshakes for the external bus and some limited protection mechanisms for the system 5 1 Chip Select Module Features e No external glue logic required for typical systems if the chip select module is used SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 1 Go to www freescale com Freescale Semiconductor Inc e Modular architecture for ease of expansion e Twelve chip select pins plus one CSBOOT pin e Pins can be programmed as CEs six maximum OEs or WEs e Capable of supporting pipelineable burstable devices e Returns bus handshake signals for the selected address regions e Provides up to seven programmable wait states for slave devices e Controls the clocki
93. are watchdog service register at regular intervals 7 2 System Protection Programming Models Table 7 1 shows the SIU system protection registers These registers control the op eration of the PIT and the bus monitor Table 7 1 SIU System Protection Address Map Access Address Register S U 0x8007 FC40 Periodic Interrupt Control and Select Register PICSR S U 0x8007 FC44 Periodic Interrupt Timer Register PIT S 0x8007 FC48 Bus Monitor Control Register BMCR Table 7 1 shows the PCU registers involved in the operation of the software watchdog Table 7 2 PCU System Protection Address Map Access Address Register S 0x8007 EFCO Software Watchdog Service Register SWSR S 0x8007 EFC4 Software Watchdog Control Register Timing Count S U 0x8007 EFC8 Software Watchdog Register 7 3 Periodic Interrupt Timer PIT The periodic interrupt timer consists of a 16 bit counter clocked by the input clock sig nal divided by four A 4 MHz system clock frequency results in a one microsecond count interval The input clock signal is supplied by the clock module In order to en SIU SYSTEM PROTECTION MOTOROLA REFERENCE MANUAL For More information On This Product 7 1 Go to www freescale com Freescale Semiconductor Inc sure adequate range for the PIT the input clock signal to the PIT must not exceed 4 MHz even if a full frequency input is used instead of an oscillator PLL clocking scheme The 16 bi
94. as address pins and the PCON field val ues for all option registers are 0b11 non chip select function Refer to 8 3 Configu ration During Reset for more information on the data bus configuration word MOTOROLA CHIP SELECTS SIU 5 6 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CSBTOR CSBOOT Option Register 0x8007 FDFC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BSIZE SBLK SUPV DSP WP Cl RESERVED ACKEN TADLY RESET 1 0 0 1 0 1 0 1 0 0 0 0 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TADLY PS PCON BYTE REGION RESERVED ITYPE RESET From data bus reset configuration word CSBTSBOR CSBOOT Sub Block Option Register 0x8007 FDF4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BSIZE SBLK SUPV DSP WP Cl RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSORO CS0 Option Register 0x8007 FDEC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED PCON BYTE REGION RESERVED RESET 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0b10 if pins are configured as chip selects at reset otherwise 0b11 CSOR1 CS1 Option Regist
95. ash EE PROM to provide a pin configuration word on the instruction or load store data bus during reset For MCUs without such a memory module the SIU provides a mask pro grammed default value This default value may vary for different members of the SIU Refer to the user s manual for the microcontroller of interest for details 8 3 3 Data Bus Reset Configuration Word In either reset configuration mode data bus configuration mode or internal default mode the configuration is accomplished within the MCU by driving a configuration word on the internal data bus before the internal RESET signal is negated At the ne gation of internal RESET those functions that are configured at reset latch their con figuration values from the assigned bits of the internal data bus The format of the data bus reset configuration word is the same regardless of which configuration mode is se lected except that data bus bits 5 13 and 21 have no meaning in internal default mode Table 8 4 describes the configuration options Table 8 4 Data Bus Reset Configuration Word Data Bus Configuration Function Effect of Mode Select 1 Effect of Mode Select 0 Bit Affected During Reset During Reset 0 Address Bus Minimum Bus Mode Maximum Bus Mode ADDR 0 11 CS 0 11 ADDRJ 0 11 Address Pins 1 Vector Table Location Vector Table Vector Table IP Bit OxFFFO 0000 0x0000 0000 2 Burst Type Indication Type 2 LAST Type 1 B
96. bit in the option registers for CSBOOT the CSBOOT sub block and CS 1 5 controls whether the information in the address block can be cached The chip select logic provides the status of this bit to the cache during the data phase of an access If Cl is set the data in the region is not cached MOTOROLA CHIP SELECTS SIU 5 14 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 5 9 Handshaking Control The acknowledge enable ACKEN bit in the option registers for CSBOOT and CS 1 5 determines whether the chip select logic returns address acknowledge AACK and transfer acknowledge TA signals for the region When ACKEN is set the chip select logic returns these signals When ACKEN is set external logic can still return these signals If it does it must assert them before the chip select logic asserts the signals internally When ACKEN is cleared the external device must return them When ACKEN is cleared the chip select logic still returns the BI and PS 0 1 signals Since the chip select logic does not return the TA signal the TADLY field indicating the number of wait states before TA assertion is not used After power on the CSBOOT circuit is enabled to return AACK and TA If the external boot device returns the TA signal however before the chip select logic asserts TA in ternally the external TA assertion terminates the access 5 10 Wait State Control
97. ble for both read and write operations 1 Block is read only Refer to 5 7 3 Write Protection for more information 8 Cl Cache inhibit 0 Information in this block can be cached 1 Information in this block should not be cached Refer to 5 8 Cache Inhibit Control for more information 9 12 Reserved 13 ACKEN Acknowledge enable 0 Chip select logic will not return TA and AACK signals 1 Chip select logic will return TA and AACK signals Refer to 5 9 Handshaking Control for more information 14 16 TADLY TA delay Indicates the latency of the device for the first TA returned Up to seven wait states are allowed 000 0 wait states 001 1 wait state 010 2 wait states 011 3 wait states 100 4 wait states 101 5 wait states 110 6 wait states 111 7 wait states Refer to 5 10 Wait State Control for more information 17 18 PS Port size 00 Reserved 01 16 bit port 10 32 bit port 11 Reserved Refer to 5 11 Port Size for more information 19 20 PCON Pin configuration Note that only pins CSBOOT and CS 1 5 can be CE pins 00 Chip enable CE 01 Write enable WE 10 Output enable OE 11 Alternate function address bus or discrete output Refer to 5 12 1 Pin Configuration for more information SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 9 Go to www freescale com 9 Freescale Semiconductor Inc Table 5 4 Chip Select Option Register Bit Settings Continued
98. by the input clock frequency the divider speci fied in the PCFS field and the timing count specified in the PITC field of the PICSR The time out period is calculated as follows PIT period PITC PIT frequency where the PIT frequency is equal to the PIT input clock frequency divided by a divisor determined by the PCFS bits as specified in 7 3 1 PIT Clock Frequency Selection With a 4 MHz clock frequency and a PCFS value of 0b000 divide by 4 reset value this gives a range from 1 us PITC 0x0001 to 65 5 ms PITC 0x0000 Table 7 5 Example PIT Time Out Periods PITC Value Time Out Period 1 decimal 1 us 5 decimal 5 us 10 decimal 10 us 100 decimal 100 us 1000 decimal 1 00 ms 10000 decimal 10 00 ms SIU SYSTEM PROTECTION MOTOROLA REFERENCE MANUAL For More Information On This Product 73 Go to www freescale com Freescale Semiconductor Inc Table 7 5 Example PIT Time Out Periods PITC Value Time Out Period 50000 decimal 50 0 ms FFFF hex 65 5 ms 0000 hex TI G me O NOTES 1 After a time out is signaled some additional time may elapse prior to any observed action 2 The count value associated with the maximum time out is Ob0000 7 3 3 PIT Enable Bits The PIT enable PTE bit in the PICSR enables or disables the timer When the timer is disabled it retains its current value When the timer is enabled it resumes counting sta
99. cation within the 2 sized memory block that is not imple mented in any memory module on the chip then the CPU takes a machine check ex ception 3 4 4 Control Register Block The internal control registers include all of the SIU registers and all of the configura tion control and status registers of each module on the I bus or L bus The internal SIU MODULE CONFIGURATION MOTOROLA REFERENCE MANUAL For More Information On This Product 3 7 Go to www freescale com 3 Freescale Semiconductor Inc control registers and the IMB are allocated a 512 Kbyte block from 0x8000 0000 to 0x8007 FFFF The internal control registers always occupy the highest numbered 4 Kbytes of this address range 0x8007 F000 to 0x8007 FFFF The IMB2 is allocated the remainder of the 512 Kbyte block The IMB2 address range can vary from chip to chip depending upon the address range required by IMB2 modules but the IMB2 ad dress range always abuts the internal control register address range The size of the IMB2 block is always 2 4K bytes where 13 lt n lt 19 Unlike the memory arrays the internal control registers and IMB2 cannot be disabled for development purposes In addition the IMB2 and control register block are only available in data space not in instruction space An instruction access to the address of a control register results in a data error on the I bus causing the internal TEA signal to be asserted 3 4 5 Internal Memory Mapping Fiel
100. chip select returns AACK it is not visible on the exter nal pins SIGNAL DESCRIPTIONS SIU REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Timing Comments 2 2 2 7 Burst Inhibit Bl Input only Module ER State Meaning Timing Comments SIU REFERENCE MANUAL For More Information On This Product Negated While the MCU is driving BB indicates that the address bus and the transfer attributes must remain driven Assertion May occur as early as the clock cycle after TS is asserted assertion can be delayed to allow adequate ad dress access time for slow devices AACK should be as serted at the same time or prior to the assertion of TA If AACK is returned prior to the assertion of TA the SIU can initiate another cycle while the previous cycle is still in progress that is returning AACK early allows pipelining of bus cycles Negation Must occur one clock cycle after the assertion of AACK High impedance Coincides with negation of BB provided no qualified bus grant exists Asserted Indicates the addressed device does not have burst capability When this signal is asserted the SIU de composes the transfer into multiple cycles incrementing the address for each cycle For systems that do not use burst mode at all this signal can be tied low permanently Negated Indicates the device supports burst mode or that the BI signal is being sent by the chip sele
101. control signal clearing a bit con figures the pin as an I O pin Which bus control signals are assigned to port M pins depends on the particular mi crocontroller Refer to the user s manual for the microcontroller of interest for details 9 3 Ports A and B Ports A and B are eight bit output ports Associated with each port is a data register and a pin assignment register data direction registers are not needed PORTA PORTB Port A B Data Registers 0x8007 FC88 0 1 2 3 4 5 6 7 8 9 0 mum mu 4 Pao Pai Paz Pas Pad Pas Pae PAa7 PBO PBI PB2 PBS PBa PBS Pee mm RESET U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value depends on the value of the data bus configuration word at reset When a port A or port B pin is assigned as a discrete output the value in the port A or port B data register is driven onto the pin PAPAR PBPAR Port A B Pin Assignment Register 0x8007 FC84 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PAPAO PAPA1 PAPA2 PAPA3 PAPA4 PAPA5 PAPA6 PAPA7 PBPAO PBPA1 PBPA2 PBPA3 PBPA4 PBPA5 PBPA6 PBPA7 RESET 1 1 1 1 1 1 1 1 1 1 1 1 2 S K NM SIU GENERAL PURPOSE UO MOTOROLA REFERENCE MANUAL For More Information On This Product 9 3 Go to www freescale com Fr
102. ct at the pin Note that the timing of output port pins does not match the timing of the corresponding bus control pins 9 2 Port M PORTM Port M Data Register 0x8007 FC68 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMO PM1 PM2 PM3 PM4 PM5 PM6 PM7 RESERVED RESET U U U U U U U U 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 On some SIU members the PM2 signal and PM2 and DDM2 bits may not be implemented On these systems the PMPA2 bit may still be active but may select between two non port M pin functions Refer to the user s man ual for the microcontroller of interest for details Writes to PORTM are stored in internal data latches If any bit of the port is configured as an output the value latched for that bit is driven onto the pin A read of PORTM returns the value at the pin only if the pin is configured as a discrete input Otherwise the value read will be the value stored in the internal data latch PORTM can be read or written at any time DDRM Port M Data Direction Register 0x8007 FC60 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DDMO DDM1 DDN2 DDM3 DDM4 DDM5 DDM6 DDM7 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 On some SIU members the PM2 signal
103. ct unit For systems that use SIU chip selects with all external memory the BI pin can remain negated the chip select unit can be programmed to assert BI to prevent bursts Assertion Negation Sampled when AACK is asserted A burst transfer can only be burst inhibited before the first TA assertion Simple asynchronous memory devices should keep AACK negated to keep the address valid They can assert BI at the same time as or before AACK and at the same time as the first TA assertion Synchronous pipelineable memory devices that do not support bursting should return BI with AACK as soon as they are ready to receive the next address Burstable memory devices should negate BI at the same time as or before they assert AACK SIGNAL DESCRIPTIONS MOTOROLA 2 7 Go to www freescale com Freescale Semiconductor Inc 2 2 2 8 Address Retry ARETRY Input only Module ER State Meaning Asserted lIf the MCU is the bus master ARETRY indi cates that the MCU must retry the preceding address phase The MCU will not begin a bus cycle for the clock cy cle following assertion of ARETRY Note that the subse quent address retried may not be the same one associated with the assertion of the ARETRY signal Assertion of ARE TRY overrides the assertion of AACK Negated High Impedance lIndicates that the MCU does not need to retry the last address phase Timing Comments Assertion Must occur at least one clock cycle followin
104. d against further writes by setting the RFD lock RFDL bit in the SCSLR register NOTE The RFD bits do not affect clock frequency when the system clock is operating in 1 1 mode MOTOROLA CLOCK SUBMODULE SIU 6 10 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 6 6 Low Power Modes The clock module provides one normal operating mode and three low power modes The low power mode LPM bits in the SCCR select one of these four modes When one of the three low power modes is selected the EBI prevents the CPU from starting any more bus cycles but allows the current bus cycle to terminate At the end of the current bus cycle the appropriate clocks are stopped and the EBI continues operation as defined for the low power mode selected Note that in debug mode the crystal and the PLL are not shut down but continue to run and provide clocks to the debug module The LPM bits can be protected against further writes by setting the LPM lock LPML bit in the SCLSR register 6 6 1 Normal Mode The normal operating mode state 0x0 is the state out of clock reset This is also the state the bits go to when the low power mode exit signal arrives 6 6 2 Single Chip Mode Mode 0x1 is single chip mode In this mode CLKOUT is turned off This mode can be selected when the MCU is used by itself and does not need to provide a system clock Turning off CLKOUT saves power and improves
105. d during development support 4 14 Storage Reservation Support The PowerPC Iwarx Load Word and Reserve Indexed and stwex Store Word Con ditional Indexed instructions in combination permit the atomic update of a storage lo cation Refer to the RCPU Reference Manual RCPURM AD for details on these instructions The storage reservation protocol supports a multi level bus structure like the one shown in the Figure 4 7 In this figure the E bus is a PowerPC bus interfaced to a non local bus such as a PC AT or VME bus through a non local bus interface For each local bus storage reservation is handled by the local reservation logic The protocol tries to optimize reservation cancellation such that a PowerPC processor is notified of the loss of a storage reservation on a remote bus only when it has issued a stwex instruction to that address That is the reservation loss indication comes as part of the stwex cycle This method eliminates the need to have very fast storage reservation loss indication signals routed from every remote bus to every PowerPC master SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 19 Go to www freescale com Freescale Semiconductor Inc BUS MASTER WR CT 0 3 Croa Gate SNOOP NON LOCAL MCU au LOGIC BUS NON LOCAL BUS E BUS INTERFACE MPC500 STORE RES BLOCK Figure 4 7 Storage Re
106. d from the keep alive power supply VDDKAP1 and Vgg In addition VDDKAP1 powers the PowerPC time base and decrementer This allows the time base to continue incrementing at 1 MHz even when the main power to the MCU is off While the power is off the decrementer also continues to count and may be used to SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Product 6 3 Go to www freescale com Freescale Semiconductor Inc signal the external power supply to enable power to the system at specific intervals This is the power down wakeup feature 6 3 System Clock Sources The Vppsn and MODCLK pins are used to configure the clock source for the MCU The configuration modes are shown in Table 6 3 Table 6 3 System Clock Sources VppsNn MODCLK PLL Options 1 1 Normal Operation 1 0 1 1 mode CLKOUT frequency is equal to oscillator frequency 0 1 PLL bypass mode maximum CLKOUT frequency is equal to one half the oscillator frequency 0 0 Special test mode When both pins are high the CPU clocks are configured for normal operation and the PLL is fully programmable If MODCLK 0 and Vppsn 1 then the PLL enters 1 1 frequency mode In this mode CLKOUT frequency is equal to the oscillator frequency and is not affected by the RFD bits The oscillator can be driven by either an external crystal or an external clock source If Vppsn 0 and MODCLK 1 then the PLL is disabled and bypassed
107. data error to be generated in the internal bus In normal operation this is a set only bit once set it cannot be cleared by software When the internal freeze signal is asserted the bit can be set or cleared by software 0 Normal operation reset value 1 All bits in the SIUMCR and all of the chip select registers are locked 10 13 Reserved 14 15 LSHOW L bus show cycles 00 Disable show cycles for all internal L bus cycles reset value 01 Show address and data of all internal L bus write cycles 10 Reserved 11 Show address and data of all internal L bus cycles Refer to 4 13 Show Cycles for more information 16 23 PARTNUM Part number This read only field is mask programmed with a code corresponding to the number of the MCU 24 31 MASKNUM Mask number This read only field is mask programmed with a code corresponding to the mask number of the MCU 3 2 Memory Mapping Register The internal memory mapping register MEMMAP enables and sets the base address of the L bus and I bus internal memory blocks This register is accessible in supervisor mode only MOTOROLA MODULE CONFIGURATION SIU 3 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc MEMMAP Memory Mapping Register 0x8007 FC20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LEN RESERVED LMEMBASE RESERVED RESET R 0 0 0 0 0 0 0 S j 0 0 0 0 0 0
108. ddress counter 5 13 1 Interface Type Descriptions Table 5 12 list the characteristics of each interface type Note that if software pro grams the ITYPE field to one of the reserved values the chip select signal will never be asserted Table 5 12 Interface Types ITYPE Interface Type Binary 0000 Generic asynchronous region with output buffer turn off time of less than or equal to one clock period see 5 13 2 Turn Off Times for Different Interface Types A device of this type cannot be pipelined Refer to Figure 5 7 and Figure 5 8 0001 Generic asynchronous region with output buffer turn off time of two clock periods see 5 13 2 Turn Off Times for Different Interface Types A device of this type cannot be pipelined The chip select logic inserts a dead clock between two sub sequent accesses to the same region of this type in order to satisfy the high time required by the CE and WE of some memory types MOTOROLA CHIP SELECTS SIU 5 18 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 12 Interface Types Continued ITYPE Interface Type Binary 0010 Synchronous region no burst with asynchronous OE Refer to Figure 5 9 and Figure 5 10 A device with this type of interface is pipelineable can function as an asynchronous device and has the ability to hold off its internal data on a read access until OE is asserted Note that with this i
109. de this bit is forced high to indicate a lock condition The loss of lock reset enable LOLRE bit in the SCCR indicates how the clocks should handle a loss of lock indication SPLS asserted When LOLRE is clear clock MOTOROLA CLOCK SUBMODULE SIU 6 14 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc reset is not asserted if a loss of lock indication occurs When LOLRE is set clock reset is asserted when a loss of lock indication occurs The reset module may wait for the PLL to lock before negating reset see SECTION 8 RESET OPERATION The LOL RE bit is cleared whenever clock reset is asserted and may be re initialized by soft ware CAUTION When the clock is in PLL bypass mode or special test mode setting the LOLRE bit in the SCCR generates a loss of lock reset request since the PLL is off The LOLRE bit must not be set when the clock is in PLL bypass or special test mode The system PLL lock status sticky bit GPLSS in the SCLSR must be initialized by software After the bit is set by software any out of lock indication clears the SPLSS bit even if the out of lock indication is active while the setting takes place The bit re mains clear until software again sets it At clock reset the state of the SPLSS bit is zero since the PLL has not achieved lock 6 10 2 Loss of Oscillator The loss of oscillator LOO status bit in the SCLSR indicates the absence of an
110. ded no qualified bus grant exists Asserted Negated This signal is driven high for a read cy cle and low for a write cycle Assertion Negation WR is an address attribute it is up dated at the start of the address phase and maintained until the start of the next address phase Note that for pipelined accesses it is not valid during the data phase High impedance Coincides with negation of BB provided no qualified bus grant exists 2 2 2 3 Burst Indicator BURST Output only Module ER State Meaning Timing Comments SIU REFERENCE MANUAL Asserted indicates a burst cycle If a burst access is burst inhibited by the slave BURST is driven during each single beat decomposed cycle Negated Indicates current cycle is not a burst cycle Assertion Negation BURST is an address attribute it is updated at the start of the address phase and maintained until the start of the next address phase High impedance Coincides with negation of BB provided no qualified bus grant exists SIGNAL DESCRIPTIONS MOTOROLA For More Information On This Product 25 Go to www freescale com 2 Freescale Semiconductor Inc 2 2 2 4 Byte Enables BE 0 3 Output only Module ER State Meaning BE 0 3 indicate which byte within a word is being access ed External memory chips can use these signals to deter mine which byte location is enabled Table 2 2 explains the encodings during accesses to 32 bit and 16 bi
111. divider 6 5 6 8 6 9 6 17 lock bit 6 18 REGION 5 10 5 17 Register lock 3 2 Reservation start 4 17 RESET 2 15 4 3 8 2 8 4 Reset 8 1 and chip selects 5 33 clock 6 14 configuration 8 7 word 8 8 flow 8 2 power on 8 10 sources 8 1 status register See RSR RESET bit 8 2 RESETOUT 2 16 4 3 8 4 8 6 RFD 6 5 6 8 6 9 6 17 RFDL 6 10 6 12 6 18 RSR 8 1 S SBLK 5 9 5 12 SCCR 6 15 SCLSR 6 17 Show cycles 4 18 Signals 2 1 Single chip mode 6 11 SIU address map 1 3 block diagram 1 3 module configuration register See SIUMCR SIUFRZ 3 1 3 10 6 14 Sleep mode 6 11 Software watchdog 7 7 control register timing count 7 7 enable 7 7 7 8 lock 7 7 7 8 register 7 8 service register 7 7 time out 8 2 timing count 7 7 7 8 SPECADDR 4 14 SPECMASK 4 14 Speculative loads preventing 4 13 INDEX SIU REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SPLS 6 9 6 10 6 14 6 18 SPLSS 6 15 6 18 STME 6 17 STMS 6 18 STOP 3 4 Storage reservation support 4 19 stwex 4 19 Sub block 5 9 5 12 option register 5 13 SUP 3 2 SUPER 5 14 Supervisor mode and chip selects 5 9 5 14 and PCU registers 3 4 and SIU registers 3 2 SUPV 3 4 5 9 SW 8 2 SWCR 7 7 SWE 7 7 7 8 SWLK 7 7 7 8 SWR 7 8 SWSR 7 7 SWTC 7 7 7 8 Synchronous burst interface 5 29 interface 5 26 5 27 OE 5 19 region 5 19 System clock 6 1 lock bits 6 12 sources 6 4 See also CLKOUT System interface unit See SIU iT
112. ds IMEMBASE LMEMBASE The IMEMBASE and LMEMBASE fields in the MEMMAP register map the l bus mem ory and L bus memory respectively to specific locations in the memory map The IM EMBASE field selects one of the four locations in which the l bus memory can be placed and the LMEMBASE field selects one of four locations in which the L bus memory can be placed The following table shows the meaning of the field Note that these locations include the two possible locations for the CPU vector table The ad dress not given start or end depending upon the block depends on the block size Table 3 4 Internal Memory Array Block Mapping LMEMBASE or IMEMBASE Block Placement 00 Starting Address 0x0000 0000 01 Ending Address 0x000F FFFF 10 Starting Address OxFFFO 0000 11 Ending Address OxFFFF FFFF 3 4 6 Memory Mapping Conflicts It is possible to map the L bus memory and the I bus memory to the same address range It is the responsibility of the user to prevent overlapping module assignments Any access to a memory that does not exist causes the cycle to appear on the external bus For example if an MCU does not have an l bus memory module then an access to Lbus memory is sent to the external bus even if the l bus memory enable IEN bit in the MEMBASE register is set If L bus and l bus memories are mapped to the same address space and both mem ories are physically present and are enabled then any access to th
113. dware disables them both because of the mapping conflict Refer to Table 3 5 3 3 Peripheral Control Unit Module Configuration Register The peripheral control unit module configuration register PCUMCR contains fields for stopping the system clock to IMB2 modules place certain PCU registers in either su pervisor or unrestricted memory space and assigning the number of interrupt request levels available to IMB2 peripherals SIU MODULE CONFIGURATION MOTOROLA REFERENCE MANUAL For More information On This Product 3 3 Go to www freescale com Freescale Semiconductor Inc PCUMCR Peripheral Control Unit Module Configuration Register 0x8007 EF80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 STOP IRQMUX RESERVED SUPV RESERVED RESET 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3 3 PCUMCR Bit Settings Bit s Name Description 0 STOP Stop system clock to peripherals controller 0 Enable system clock to IMB2 modules 1 Disable system clock to IMB2 modules 1 2 IRQMUX Interrupt request multiplexer control 00 Disable multiplexing scheme 8 possible interrupt sources 01 2 to 1 multiplexing 16 possible interrupt sources 10 3 to 1 multiplexing 24 possible interrupt sources 11 4 to 1 multiplexing 32 possible interrupt sources Refer to 10 2 3 On Chip Peripheral IMB2 Interrupt Reque
114. e LOLRE bit in the system clock control register If set source of reset is a software watchdog time out This occurs when the software watchdog counter reaches zero If set the source of reset is a checkstop This occurs when the processor enters the checkstop state and the checkstop reset is enabled If set the source of reset is the JTAG module This reset occurs only during production testing Bit s Name 0 RESET 1 LOO 2 LOL 3 SW 4 CR 5 JTAG 6 31 Reserved 8 2 Reset Flow The reset flow can be divided into two flows external reset request flow and the inter nal reset request flow 8 2 1 External Reset Request Flow Figure 8 1 is a flow diagram for external resets MOTOROLA 8 2 RESET OPERATION SIU For More information On This Product REFERENCE MANUAL Go to www freescale com REFERENCE MANUAL Freescale Semiconductor Inc lt gt FROM INTERNAL RESET FLOW ASSERT RESETOUT AND INTERNAL RESET REQUEST INTERNAL BUSES START THE COUNTER IF RESET 0 WAIT FOR CNT 17 Le WAIT FOR PLL TO LOCK THIS STATE DEPENDS ON PLL MODE AND RESET CONFIG WORD IS CNT 17 OR PLL LOCKED CONTINUE REQUESTING BUSES RELEASE RESETOUT AND INTERNAL RESETS AND START THE COUNTER RELEASE BUS REQUESTS AND GO TO IDLE YES MPC500 EX RESET FLOW Figure 8 1 External Reset Request Flow RESET OPERATION MOTOROLA For Mo
115. e for fast relinquishing of the data bus SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 27 Go to www freescale com Freescale Semiconductor Inc CLKOUT fe ADDR K C A OVERLAP ACCESS UNDEFINED WR DONT CARE CLOCK IN ADDRESS FOR READ CE r NEXT POSSIBLE CE op SYNCHRONOUS lk ENABLE DATA OUTPUT DATA D1 Foam gt DEVICE 3 STATE ITS RACK a DRIVERS FROM CLOCK EDGE TA we Tn ONE WAIT STATE MPC500 SYNC RD OE TIM Figure 5 11 Synchronous Read with Early OE One Wait State 5 16 5 Synchronous Interface With Synchronous OE and Early Overlap ITYPE 9 Devices with ITYPE 9 are synchronous with a synchronous output enable They are different from devices with ITYPE 3 in that they support early overlapping of access es That is the region is capable of accepting a second address one clock cycle before the data phase of the first access terminates Notice in Figure 5 11 that CE is asserted one clock cycle earlier than in the previous example Figure 5 10 MOTOROLA CHIP SELECTS SIU 5 28 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CLKOUT WEE ADDR lt lt m J OVERLAP ACCESS 29 EARLY OVERLAP ACCESS CLOCK IN ADDRESSf0R READ
116. e region 5 22 PIT 7 1 7 5 and freeze 3 10 and port Q interrupt levels register See PITQIL clock frequency select 7 2 7 5 count 7 5 enable 7 2 7 4 7 5 interrupt enable 7 2 7 4 7 5 interrupt request level 7 4 interrupts 10 5 status 7 2 7 4 7 5 time out period 7 3 PITC 7 2 7 5 PITIRQL 7 4 PITQIL 10 6 10 7 PJ 2 16 PJPAR 9 5 PK 2 16 PKPAR 9 5 PL 2 16 PLL 6 4 lock signal See PLLL lock status 6 9 6 10 6 14 6 18 sticky bit 6 15 6 18 loss of lock 8 2 test mode enable 6 17 test mode select 6 18 PLLL 2 15 6 3 PLPAR 9 5 PM 2 17 PMPAR 9 3 Port M 9 2 data direction register 9 2 discrete I O signals See PM pin assignment register 9 3 Port Q discrete I O signals See PQ edge detect status 10 8 edge detect data register 10 8 edge fields 10 9 10 10 pin assignment register 10 8 10 9 Port replacement unit 9 1 9 5 Port size bit 5 9 5 16 Ports A and B 9 3 data registers 9 3 discrete output signals See PA PB pin assignment register 9 3 Ports I J K and L 9 4 data direction registers 9 4 data registers 9 4 discrete I O signals See PI PJ PK PL pin assignment registers 9 5 Power down wakeup See PDWU Power on reset 8 10 PQ 2 17 10 8 PQE 10 8 PQEDGDAT 10 8 PQEDGE 10 9 10 10 PQPA 10 9 MOTOROLA l 4 For More Information On This Product PQPAR 10 8 10 9 PRU 9 1 9 5 PRU select 4 18 PS 5 9 5 16 7 2 7 4 7 5 PTE 7 2 7 4 7 5 Q Qualified bus grant 4 8 R Read cycle 4 4 Reduced frequency
117. e that the RCPU never performs speculative stores it always waits until the instruc tion is ready to be retired before writing to external memory Refer to the RCPU Ref erence Manual RCPURM AD for more information When data loaded speculatively from RAM later needs to be discarded this does not ordinarily present a problem For example a load instruction that follows a floating point instruction in the instruction stream could begin execution before the floating point instruction is retired If the floating point instruction generates an exception the result of the load instruction is discarded the exception is processed and the proces sor automatically re issues the load instruction However if the address of the speculative load represents a FIFO device the specu latively loaded data is lost when the exception is processed and the re issued load instruction loads the next data item in the queue Preventing speculative loads is nec essary to prevent this scenario from occurring SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 13 Go to www freescale com Freescale Semiconductor Inc As another example a memory mapped I O device could have a status register that is updated whenever its data register is read If the data register is read speculatively the status register is updated even if the result of the read is subsequently discarded for example again if a previously issu
118. e the CPU instruc tion fetch unit can only run read cycles Similarly l bus masters are able to execute diagnostic programs out of the RAM on the L bus These capabilities require that the MOTOROLA 3 4 MODULE CONFIGURATION SIU For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc addresses of the memory modules on the I bus be known to the L bus address decode logic and vice versa Refer to 3 5 Internal Cross Bus Accesses for details A block diagram of the internal module select scheme is shown in Figure 3 1 FIXED DECODE 0X8000 0000 L MEM MODULE 1 0X8007 EFFF L BUS MAPPING SIGNALS 3 SIU DECODE BLOCK IN SIU AND EACH MODULE READWRITE CONTROL REGISTERS LMEMBASE 4 KBYTE BLOCK 0X8007 F000 IMEMBASE IMB INTERFACE CPU I MEM MODULE BUS MAPPING SIGNALS 3 MPC500 MOD SEL BLOCK Figure 3 1 Internal Module Select Scheme 3 4 1 Internal Memory Categories All internal memory is divided into the following three categories SIU MODULE CONFIGURATION MOTOROLA REFERENCE MANUAL For More Information On This Product 3 5 Go to www freescale com Freescale Semiconductor Inc e bus memory l mem e L bus memory L mem e Control registers and IMB2 interface The internal module selects provide for one block of memory in each category A sin gle block includes both the internal control registers and the IMB2 in
119. e the PLL to continually update and prevent a frequency drift phenomenon known as dead banding 6 4 3 Charge Pump and Loop Filter The UP and DOWN signals from the phase detector control whether the charge pump applies or removes charge respectively from the loop filter The loop filter is shown in Figure 6 4 The resistor is integrated onto the MCU chip the capacitor is connected externally via the XFCP and XFCN pins The charge pump transfers charge differentially the filter is not referenced to either the supply rail or ground This architecture reduces the effects of supply and ground noise on the PLL and ultimately the system clock MOTOROLA CLOCK SUBMODULE SIU For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc XFCP CHARGE PUMP ms 0 1 WF XFCN MCU MPC500 CH PUMP Figure 6 4 Charge Pump with Loop Filter Schematic 6 4 4 VCO The VCO also utilizes a differential architecture to increase noise immunity The differ ential voltage formed across the loop filter denoted by the and signs in Figure 6 4 controls the frequency of the VCO output The frequency to voltage relationship VCO gain is positive and the output frequency is twice the maximum target system frequency 6 4 5 Multiplication Factor Divider The multiplication factor divider MFD divides down the output of the VCO and feeds it back to the phase d
120. ecifies whether the pin uses timing for the LAST signal LST 1 or the BDIP signal LST 0 Type 1 and type 2 burst interfaces both have address latches so the address of the next access to the device can be overlapped with the previous access That is the ad SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 29 Go to www freescale com Freescale Semiconductor Inc dress of an access does not need to be valid after the address has been latched at the rising edge of the clock For type 1 burst interfaces with an asynchronous OE the ITYPE field in the appropri ate chip select option register should be programmed to 060101 For type 1 burst in terfaces with a synchronous OE this field should be programmed to 060111 For type 2 burst interfaces ITYPE should be programmed to 0b1000 Figure 5 13 and Figure 5 14 show a read and write access respective to a type 1 burst interface Note in Figure 5 13 that the OE is asynchronous ITYPE 5 CLKOUT e L L L L L L ADDR lt d A1 X POSSIBLE A2 T A oN LAST DATA CE H BDIP ES NEXT DATA OE ASYNCHRONOUS TURN OFF ENABLE on a De ae mK A Vo WAIT STATE TA Hpi m me o UNDEFINED DON T CARE MPC500 SYNC BRD1 TIM Figure 5 13 Type 1 Synchronous Burst Read Interface MOTOROLA CHIP SELECTS SIU 5 30 For More information On This Product REFE
121. ect Functional Block Diagram 5 3 Chip Select Pins The pin configuration PCON field in each chip select option register configures the associated pin to function as a chip enable CE write enable WE output enable OE or alternate function pin For pins configured for their alternate function the port A pin assignment register configures the pin as either an address bus signal AD DR 0 11 or a port A or B output signal PA 0 7 and PB 0 3 Notice that the CSBOOT pin has no alternate function Table 5 1 describes the chip select pins Table 5 1 Chip Select Pin Functions Chip Select Function Alternate Pin Function in Chip Select Mode Function CSBOOT Can be the CE of the system boot memory power on default In sys tems with no external boot device this pin can be configured as WE or OE of EPROMs or SRAMs CS0 ADDRO PAO Can be WE or OE of EPROMs or SRAMs When configured as a chip CSBTOE select this pin is assigned to be the OE of the CSBOOT pin following reset CST ADDR1 PA1_ Can be CE WE or OE of EPROMs or SRAMs CS2 ADDR2 PA2 Can be CE WE or OE of EPROMs or SRAMs CS3 ADDR3 PA3__ Can be CE WE or OE of EPROMs or SRAMs CS4 ADDR4 PA4 Can be CE WE or OE of EPROMs or SRAMs SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More information On This Product 5 3 Go to www freescale com Freescale Semiconductor Inc Table 5 1 Chip Select Pin Functions
122. ed instruction generates an exception Two registers and their associated logic allow a block ranging in size from 1 Kbyte to 64 Kbytes or parts of the block to be protected from speculative accesses The most significant 22 bits of the address of each L bus cycle are bitwise compared to the non speculative base address register GPECADDR with each result bit equal to one if the bits match A bitwise OR is performed on the lower six bits of the resulting word with the mask in the non speculative mask register SPECMASK If all six result bits are one and the upper 16 result bits are all ones then speculative accesses are pre vented during the current cycle SPECADDR Non Speculative Base Address Register 0x8007 FC24 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BASE ADDRESS RESERVED 0 RESET 000 0000 0 0 0000 0 0 0000 0 0 0 0 0 00 0 0 0 0 0 Table 4 6 SPECADDR Bit Settings Bit s Name Description 0 21 BASE ADDRESS 22 bit base address of region protected from speculative loads 22 31 Reserved SPECMASK Non Speculative Mask Register 0x8007 FC28 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED MASK RESERVED 0 RESET 000 0 0 0 0 0 0 0000 0 0 0000 00 0 000 0 0 0 0 0 0 Table 4 7 SPECMASK Bit Settings Bit s Name Description 0 15 Re
123. eescale Semiconductor Inc 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value depends on the value of the data bus configuration word at reset Each bit in PAPAR or PBPAR controls the function of the associated pin provided the pin is configured for alternate non chip select function in the corresponding chip se lect options register Setting a bit in the PAPAR or PBPAR configures the correspond ing pin as an address bus pin clearing the bit configures the pin as an I O pin Which address bus signals are assigned to port A and B pins depends on the particular microcontroller Refer to the user s manual for the MCU of interest for details 9 4 Ports I J K and L PORTI PORTJ PORTK PORTL Port J K L Data Registers 0x8007 FCAO 0 1 2 3 4 5 6 7 8 9 wm mum mu 45 Po Pm Pe ps P4 Ps Pe Pr Po Pui ps2 Pus Pua Pus Pue Puz RESET U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PKO PK1 PK2 PK3 PK4 PK5 PK6 PK7 PLO PL1 PL2 PL3 PL4 PL5 PL6 PL7 RESET U U U U U U U U U U U U U U U U Writes to port l J K and L data registers are stored in internal data latches If any pin in one of these ports is configured as an output the value latched for the correspond ing data register bit is driven onto the pin A read of one of these data registers ret
124. efault word continues to be driv en on the internal buses This scheme allows users of the internal default mode to limit their required external configuration hardware to two pull down resistors It also allows many options to be configured with a single three state octal buffer 8 3 1 Data Bus Configuration Mode If data bus configuration mode is selected DSDI is asserted then the MCU is config ured according to the values latched from the data bus pins The external data bus is divided into four groups DSDI DATA0 5 e DATA6 13 SIU RESET OPERATION MOTOROLA REFERENCE MANUAL For More Information On This Product 8 7 Go to www freescale com 8 Freescale Semiconductor Inc e DATA 14 21 e DATA 22 31 This grouping allows the user to use three state octal buffers to only drive valid data on the pins for those reset configuration options that the user would want to change The state of the last pin in each group pins 5 13 and 21 determines whether the next set of configuration options use the internal default values or are configured from the external data bus The user is required to drive to a valid level all the pins in any of the groups that are to be changed The functions selected by these pins are shown in Ta ble 8 4 8 3 2 Internal Default Mode If DSDI is held low during reset internal default mode is selected The internal default mode allows MCUs with on board non volatile memory modules such as fl
125. elect unit detects a protection violation it asserts the internal TEA signal and does not assert the external chip enable signal Assertion of TEA causes the pro cessor to enter the checkstop state enter debug mode or process a machine check exception Refer to the RCPU Reference Manual RCPURM AD for details SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 9 13 Go to www freescale com 9 Freescale Semiconductor Inc 5 7 1 Supervisor Space Protection The SUPV bit in the option registers for CSBOOT the CSBOOT sub block and CS 1 5 controls user level access to the associated region If the bit is set access is permitted at the supervisor privilege level only If the bit is cleared both supervisor and user level accesses are permitted When an access is made to the region assigned to the chip select the chip select logic compares the SUPV bit with the internal ATO signal which indicates whether the ac cess is at the user ATO 0 or supervisor ATO 1 privilege level If the chip select logic detects a protection violation SUPV 1 and ATO 0 it asserts the internal TEA signal and does not assert the external chip enable signal This protection applies to data address space only The chip select logic does not check for supervisor access protection on instruction accesses 5 7 2 Data Space Protection The DSP bit in the option registers for CSBOOT the CSBOOT sub block and CS 1 5 cont
126. electromagnetic compatibility The low power mode exit signal is the logical OR of the external reset pin the IRQ 0 1 pins if LPMM 1 the decrementer interrupt and the PIT interrupt Since the oscillator and PLL are still running and locked the low power mode exit sig nal must be a minimum of two system clock cycles and exiting this state does not incur a PLL lock time 6 6 3 Doze Mode Mode 0x2 is doze mode In this state not only is CLKOUT turned off but also all inter nal clocks are turned off However the oscillator and the PLL continue to operate nor mally The low power mode exit signal is the logical OR of the external reset pin the IRQ 0 1 pins if LPMM 1 the decrementer interrupt and the PIT interrupt Since the oscillator and PLL are still running and locked the low power mode exit signal must be a minimum of two system clock cycles and exiting this state does not incur a PLL lock time 6 6 4 Sleep Mode Mode 0x3 is sleep mode In this state all clocks are turned off including the oscillator and the PLL The low power mode exit signal is the logical OR of the external reset pin and the IRQ 0 1 pins if LPMM 1 The decrementer interrupt and the PIT interrupt are not active in this mode Since all clocks are stopped this signal is asynchronous Exiting state 0x3 requires the normal crystal start up time plus PLL lock time or time out SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Pr
127. eline depth is zero all pre vious external bus cycles are complete the monitor counts from transfer start to trans fer acknowledge Otherwise the monitor counts from transfer acknowledge to transfer acknowledge If the monitor times out transfer error acknowledge TEA is asserted internally The bus monitor is always enabled regardless of the value of the BME bit in the BM CR while the internal freeze signal is asserted and debug mode is enabled or while debug mode is enabled and the debug non maskable breakpoint is asserted 7 4 1 Bus Monitor Timing The bus monitor timing BMT field in the BMCR allows the user to select one of four selectable response time periods Periods range from 16 to 256 system clock cycles The programmability of the time out allows for a variation in system peripheral re sponse time The timing mechanism is derived from taps off a divider chain which is clocked by the system clock SIU SYSTEM PROTECTION MOTOROLA REFERENCE MANUAL For More Information On This Product 7 5 Go to www freescale com 7 4 Freescale Semiconductor Inc The time out period should be set for the maximum total cycle time including all beats of a burst i e until TA is asserted for the final beat of a burst cycle not for just the address phase or data phase of the cycle 2 Bus Monitor Lock The bus monitor lock BMLK bit in the BMCR is used to prevent inadvertent writes to the BMCR Once BMLK is set subsequen
128. er 0x8007 FDE4 CSOR2 CS2 Option Register 0x8007 FDDC CSOR3 CS3 Option Register 0x8007 FDD4 CSOR4 CS4 Option Register 0x8007 FDCC CSOR5 CS5 Option Register 0x8007 FDC4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BSIZE SBLK SUPV DSP WP Cl RESERVED ACKEN TADLY RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 7 Go to www freescale com Freescale Semiconductor Inc 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TADLY PS PCON BYTE REGION RESERVED ITYPE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0b00 if pins are configured as chip selects at reset otherwise 0b11 CSOR6 CS6 Option Register 0x8007 FDBC CSOR7 CS7 Option Register 0x8007 FDB4 CSOR8 CS8 Option Register 0x8007 FDAC CSOR9 CS9 Option Register 0x8007 FDA4 CSOR10 CS10 Option Register 0x8007 FD9C CSOR11 CS11 Option Register 0x8007 FD94 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED ssid RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED PCON BYTE REGION RESERVED RESET 0 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0b00 if pins are configured as chip selects at reset otherwise 0b11 Table 5 14 describes the fields in the chip select option registers Table 5 4 Chip Select Option Register Bit Settings Bit s Name Description 0 3 BSIZE Block size This field determines the size of the b
129. es 10 5 10 3 Interrupt Controller epuer sc 22 ceec vorsceeaccaseete lian cuccvensneetucenacweste E 10 6 10 3 1 Pending Interrupt Request Register ssssnneeeeeeeeeeeeneeeerrnneeseerree 10 6 10 3 2 Enabled Active Interrupt Requests Register seeeeeeeeeeeees 10 7 10 3 3 Interrupt Enable Register cc frec cuca aeieuadicenneetegaeiey 10 7 10 3 4 PIT Port Q Interrupt Levels Register AAA 10 7 10 4 POM GY EE EE 10 8 10 4 1 Port Q Edge Detect Data Register AAA 10 8 10 4 2 Port Q Pin Assignment Register AAA 10 9 10 4 2 1 Port Q Pin Assignment Fields ccccceeeeeeeeeeeeeeeeneeeeeeeeeeee 10 9 10 4 2 2 Port ele EE 10 10 GLOSSARY OF TERMS AND ABBREVIATIONS SUMMARY OF CHANGES MOTOROLA SIU viii For More Information On This Product REFERENCE MANUAL Go to www freescale com Fregpenle SSAK Inc Figure Title Page 1 1 MPC500 Family MCU Block Diagram cceeceeeeeeeeeeeeeeeeeseeeeteeeeeeeeeeee 1 2 1 2 SIU Block DIGGIN EG 1 3 1 3 Peripherals Control Unit Block Diagram 1 6 2 1 Output Only and Three State I O Butters 2 1 3 1 Internal Module Select Gcheme Aen 3 5 3 2 Placement of Internal Memory In Memory Map sssssssssseeessessseeessesssreeeess 3 7 4 1 Flow Diagram of a Single Read Cvcle AAA 4 4 4 2 Example of a Read Cycle ss es cacccnccceuseus rept vencedices etre eer GEES 4 5 4 3 Flow Diagram of a Single Write Cycle ececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 4 6 4 4 Example of Pi
130. escale Semiconductor Inc SECTION 4 EXTERNAL BUS INTERFACE The external bus interface EBI interfaces the external bus E bus with the two inter nal buses bus and L bus The E bus is synchronous and supports pipelined and burst transfers Signals driven onto the E bus are required to meet the set up and hold times relative to the rising edge of the bus clock The bus has the ability to support mul tiple masters but its protocol is optimized for a single processor environment 4 1 Features e No external glue logic required for a simple system e Supports different memory SRAM EEPROM types asynchronous synchro nous pipelineable burstable e Fast one clock arbitration possible e Bus is synchronous all signals are referenced to the rising edge of the bus clock e 32 bit data bus 32 bit address bus with byte enables e Compatible with PowerPC architecture e Protocol allows wait states to be inserted during the data phase and supports ear ly burst termination e Supports both 16 bit and 32 bit port sizes e Bus electrical specification minimizes system power consumption 4 2 External Bus Signals Table 4 1 summarizes the E bus signals The following abbreviations are used in this table M Bus master S Slave device A Central bus arbiter T Bus watchdog timer X Any device on the system Table 4 1 EBI Signal Descriptions Mnemonic Direction Description Address Phase Signals ADDR 0 29 M g
131. ese memories is sent to the external bus indicating a memory mapping error On the other hand if l bus and L bus memories are mapped to the same address space and are enabled but if one of them does not exist only access to that memory is sent to the external bus Table 3 5 depicts the actions taken by the SIU under different combinations of the base address enable bits and plugs MOTOROLA MODULE CONFIGURATION SIU For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 3 5 Memory Accesses in Case of Memory Mapping Conflicts l Bus and L Bus l Bus l Bus L bus L Bus Destination of Destination of Memories Memory Memory Memory Memory Access to l Bus Access to L Bus Mapped to the Exists Enabled Exists Enabled Memory Memory Same Address Different Yes No Yes No External Emulation Different Yes Yes Yes Yes l memory L memory Different External Same External Same External Emulation Same l memory Same External Emulation Same L memory External 3 5 Internal Cross Bus Accesses Each internal bus l bus and L bus has a master slave interface in the SIU The slave interface is used for accesses by the internal master RCPU to the external bus to memory on the opposite bus eg L bus to I bus access or to SIU registers The SIU allows masters on either internal bus bus or L bus to access slaves on the other internal bus Acce
132. ese ports always provide three clock cycle access whether PRU mode is enabled or not PRU mode is invoked by pulling DATA25 high during reset Other pins should be con figured as bus control pins SIU GENERAL PURPOSE I O MOTOROLA REFERENCE MANUAL For More Information On This Product 9 5 Go to www freescale com Freescale Semiconductor Inc MOTOROLA GENERAL PURPOSE I O SIU 9 6 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 10 INTERRUPT CONTROLLER AND PORT Q Interrupts provide a mechanism for asynchronous real time communication between I O devices and the CPU The SIU interrupt controller joins the simple interrupt struc ture of the CPU with the complex structure of interrupt sources in the system The CPU has a single maskable external interrupt A complete SIU based system can have mul tiple interrupting modules each with multiple interrupt sources The interrupt controller consolidates all the interrupt sources into a single interrupt sig nal to the processor Interrupt sources include the periodic interrupt timer external in terrupt pins and any IMB2 on chip peripherals External interrupt input pins are grouped into a general purpose port port Q When not used as interrupt inputs any of these pins can be used for digital input or output Port Q operation is described in 10 4 Port Q 10 1 Interrupt Controller Operation SIU The fo
133. etector when the PLL is not operating in 1 1 mode The phase detector controls the VCO frequency via the charge pump and loop filter such that the reference and feedback clocks have the same frequency and phase Thus the input to the MFD which is also the output of the VCO is at a frequency that is the reference frequency multiplied by the same amount that the MFD divides by For example if the MFD divides the VCO frequency by six then the PLL will be frequency locked when the VCO frequency is six times the reference frequency The presence of the MFD in the loop allows the PLL to perform frequency multiplica tion or synthesis When the PLL is operating in 1 1 mode the MFD is bypassed and the effective multiplication factor is one Refer to 6 5 CLKOUT Frequency Control for details on setting system clock frequency with the MF and RFD bits 6 4 6 Clock Delay SIU Besides frequency synthesis the PLL must also align the phase of i e phase lock the reference and system clocks to ensure proper system timing Since the purpose of the RFD is to allow the user to change the system frequency without forcing the PLL to re lock the feedback clock must originate before the RFD i e the output of the VCO The clock delay is a chain of gates that approximates the delay through the RFD clock generation circuits metal routing and the CLKOUT driver This approach does not al CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Informati
134. evelopment Port Serial Clock Input DSCK eeeeeee 2 12 2 2 4 4 Instruction Fetch Visibility Signals VF 0 2 eeeeeeees 2 12 2 2 4 5 Instruction Flush Count NELSON 2 13 2 2 4 6 Watehpoints WPO E 2 13 2 2 5 Elle EE 2 13 2 2 5 1 Chip Select for System Boot Memory CSBOOT ssssssssseseeesnns 2 13 2 2 5 2 Chip Selects for External Memory CO nh 2 14 2 2 6 ere TE 2 14 2 2 6 1 Clock Output CLKOUT e condvecststorsdutraiederhtronesiapentenatianeetis 2 14 2 2 6 2 Engineering Clock Output ECROUT sssssssssssessssssseneesserrrresses 2 14 2 2 6 3 Crystal Oscillator Connections EXTAL XTAL eeeeee 2 14 2 2 6 4 External Filter Capacitor Pins XFCP XFCN eeeeeeee 2 15 2 2 6 5 Clock Mode MODCLK ssssssssssnnesnnnnersnnnrtrnnsrtnnnnnnnnnnnnnnennne 2 15 2 2 6 6 Phase Locked Loop Lock Signal PLLL eeeeeeeeeteeeees 2 15 2 2 6 7 Power Down Wake Up PDWU sssssssssssesssssssrnsssssssrrnnsseerrrrnessee 2 15 2 2 7 Reset Signals eege tae E AAA EEEa 2 15 2 2 7 1 GR WEE 2 15 2 2 7 2 Reset Output RESETOUT GE 2 16 2 2 8 SIU General Purpose Input Output Signals ccceeeeeeeeeeeeeees 2 16 2 2 8 1 Ports A and B PA 0 7 PB 0 7 EE 2 16 2 2 8 2 Ports I J K and L PI 0 7 PJ 0 7 PK 0 7 PL 0 7 2 16 2 2 8 3 Pom MA PMID arene a a a ans 2 17 2 2 9 Interrupts and Port Q Signals eebe Seege DES 2 17 2 2 9 1 Interrupt Requests IRQ 0 7 cccese
135. f the errata sheets data sheets and other supporting documentation shall be interpreted as conveying an express or implied warranty representation or guarantee regarding the suitability of the products for any particular purpose The parties do not assume any liability or obligation for damages of any kind arising out of the application or use of these materials Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer under a separate sale agreement between the marketing party and the customer In the absence of such an agreement no liability is assumed by the marketing party for any damages actual or otherwise Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Neither IBM nor Motorola convey any license under their respective intellectual property rights nor the rights of others The products described in this manual are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the product could create a situation where personal injury or death may occur Should customer purchase or use the products for any such unintended or unauthorized application customer sha
136. frequency of 16 MHz to 44 MHz Table 6 5 summarizes the effect of the MF bits MOTOROLA 6 8 For More Information On This Product CLOCK SUBMODULE Go to www freescale com SIU REFERENCE MANUAL Freescale Semiconductor Inc Table 6 5 Multiplication Factor Bits MF Field Binary Multiplication Factor PLL Frequency with 4 MHz Reference x000 4 16 MHz x001 5 20 MHz x010 6 24 MHz x011 7 28 MHz x100 8 32 MHz x101 9 36 MHz x110 10 40 MHz x111 11 44 MHz Note that the PLL frequency is equal to the CLKOUT frequency when the RFD bits are programmed to 0b0000 divide by one Note also that the value of MF 0 is ignored However this bit should be written to zero in case it is used in future implementations The MF bits should not be programmed to generate a frequency that is greater than the specified operating frequency of the system The MF bits can be read and written at any time However the MF bit field can be write protected by setting the MF lock MPL bit in the SCSLR Changing the MF bits causes the PLL to lose lock If the loss of lock reset enable bit LOLRE is set the loss of lock condition causes the clock module to signal a reset condition to the reset controller The reset controller may wait for the PLL to lock before negating reset Thus the PLL can still be out of lock when RESETOUT is negated Af ter changing the MF bits software should monitor the system P
137. fter the number of wait states it requires The interface keeps the first data beat valid for only one clock Any access to a device with this type of interface must be made using chip selects and the ACKEN bit in the option register for the chip select must be set Because this type cannot hold off its internal data until the data bus is available an access to a region of this type cannot be pipelined with a previous access to the same or a different region That is the address of an access to this region cannot appear on the external bus before the data for the previous access The address for the second access can overlap the data for the first access however In addition if an access to this region is followed by an access to a pipelineable region the second access is pipelined This interface type can function as an asynchronous interface That is a device with this ITYPE can be assigned to the CSBOOT region which comes out of reset configured as an asynchronous region with seven wait states In this case the MCU doesn t latch the data to be read until the assigned number of wait states have elapsed and OE is asserted 1001 Synchronous region no burst with synchronous OE as with ITYPE 3 but with early overlapping of accesses to the region Refer to Figure 5 11 This type of interface must be able to pipeline another access to it one clock cycle before it drives valid data out on a read or receives data on a write for the previo
138. g the assertion of TS if a retry is required TA or TEA must not be asserted during a cycle in which ARETRY is asserted If TA is asserted for any part of a burst cycle ARETRY must not be asserted at any time during the cycle if ARETRY is asserted during a burst cycle it must be asserted before the first beat is terminated with TA Note that BB is not negated until the second clock cycle af ter ARETRY assertion Negation Must occur one clock cycle after assertion of ARETRY 2 2 2 9 Address Type AT 0 1 Output only Module EBI State Meaning Asserted Negated AT 0 1 define the addressed space as user or Supervisor and as data or instruction as shown in Table 2 3 Table 2 3 Address Type Definitions AT 0 1 Address Space Definition 0b00 User data 0b01 User instruction 0b10 Supervisor data 0b11 Supervisor instruction Timing Comments __Assertion Negation The AT 0 1 signals are address at tributes they are updated at the start of the address phase and maintained until the start of the next address phase MOTOROLA SIGNAL DESCRIPTIONS SIU 2 8 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc High impedance Coincides with negation of BB provided no qualified bus grant exists 2 2 2 10 Cycle Types CT 0 3 Output only Module ER State Meaning Timing Comments 2 2 3 Data Phase Signals Asserted Negated Cycle type signa
139. gister The SIU module configuration register SIUMCR configures various aspects of SIU operation This register is accessible in supervisor mode only SIUMCR SIU Module Configuration Register 0x8007 FCO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SIU RESERVED CSR LST 0 SUP DLK LOK RESERVED LSHOW FRZ RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PARTNUM MASKNUM Read Only Fixed Value Read Only Fixed Value Table 3 1 SIUMCR Bit Settings Bit s Name Description 0 SIUFRZ SIU Freeze 0 Decrementer and time base registers and the periodic interrupt timer continue to run while internal freeze signal is asserted reset value 1 Decrementer and time base registers and the periodic interrupt timer stop while the internal freeze signal is asserted Refer to 3 4 Internal Module Select Logic in this manual and to the RCPU Reference Manual RCPURM AD for information on the freeze signal 1 2 ES Reserved SIU MODULE CONFIGURATION MOTOROLA REFERENCE MANUAL For More information On This Product 3 1 Go to www freescale com Freescale Semiconductor Inc Table 3 1 SIUMCR Bit Settings Continued Bit s Name Description 3 CSR Checkstop reset enable 0 No action taken when SIU receives the checkstop signal from the CPU and debug mode not enabled reset value 1 SIU causes a reset upon receiving checksto
140. gister 0x8007 EFA8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LO L1 L2 L3 L4 L5 L6 L7 L8 L9 Lio Li os Lig 4 Dos RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 10 3 4 PIT Port Q Interrupt Levels Register The PIT port Q interrupt levels register PITQIL contains six 5 bit fields for program ming the interrupt request level of the periodic interrupt timer PIT the internal IRQ 0 1 signals from on chip peripherals on the L bus and the IRQ 0 2 interrupt re quest pins Refer to 10 2 Interrupt Sources for more information SIU INTERRUPT CONTROLLER AND PORT Q MOTOROLA REFERENCE MANUAL For More information On This Product 10 7 Go to www freescale com Freescale Semiconductor Inc PITQIL PIT Port Q Interrupt Levels Register 0x8007 EFAC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 IRQOL IRQ1L IRQ2L RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 LBUSOL LBUS1L PITIRQL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 3 PITQIL Bit Settings Bit s Name Description 0 Reserved 1 5 IRQOL Interrupt request level for the 6 10 IRQiL 11 15 IRQ2L IRQO pin Interrupt request level for the IRQ1 pin IRQ2 pin Interrupt request level for the 16
141. h fixed burst access capability burst type 1 and synchronous OE Re fer to Figure 5 13 but with a synchronous not asynchronous OE and to Figure 5 14 Devices with this type of interface are pipelineable and can hold off internal data until OE is asserted The interface keeps the first data beat valid until the BDIP signal indicates that it should send out the next data This interface type can function as an asynchronous interface That is a device with this ITYPE can be assigned to the CSBOOT region which comes out of reset configured as an asynchronous region with seven wait states In this case the MCU doesn t latch the data to be read until the assigned number of wait states have elapsed and OE is asserted SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 19 Go to www freescale com Freescale Semiconductor Inc Table 5 12 Interface Types Continued ITYPE Interface Type Binary 1000 Region with fixed burst access capability burst type 2 Refer to Figure 5 15 This interface type uses the LAST timing protocol Typically this ITYPE is used for burst accesses to DRAM This interface type may have an OE and may have a wait state counter but the chip select logic does not expect the device to have either and will never assert the OE signal OE can be provided by external logic if required or a different ITYPE can be selected The device will drive out the data a
142. hat indicates whether the corresponding interrupt request line is asserted The bit also acts as a status bit if the pins are configured as general purpose inputs or outputs When the pin is configured in edge detect mode the status bit is cleared by reading the bit as a one and then writing it to zero In level sensitive mode the bit remains cleared MOTOROLA 10 8 INTERRUPT CONTROLLER AND PORT Q SIU For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc A write to the port Q data register is stored in the internal data latch and if any PQ bit is configured as an output the value latched for that bit is driven onto the pin A read of this port returns the value at the pin only if the pin is configured as a discrete input Otherwise the value read is the value stored in the internal data latch The port Q data register can be read or written at any time PQEDGDAT Port Q Edge Detect Data Register 0x8007 EFDO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PQEO PQE1 PQE2 PQE3 PQE4 PQE5 PQE6 PQE7 Pao Pai Pa2 Pas Sou Pas Pae PQ7 RESET U U 0 0 0 0 0 0 U U 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED 10 4 2 Port Q Pin Assignment Register The port Q pin assignment register PQPAR contains the port Q pin assignment PQ PA 0 6 fields and the port Q edge PQEDG
143. hat the address of the second access is on the external bus at the same time as the data of the first access Two accesses are pipelined if they are aligned such that the address of the second access is on the external bus before the data of the first access A device is pipelineable if it can latch the address presented to it and does not require the address to be valid on its address pins for the duration of the access to the device The pipelineable device should latch the address at the rising edge of the clock when its CE is asserted Note that only synchronous devices are treated as pipelineable by the chip select logic BDIP and LAST are the E bus burst early termination control signals A memory de vice with a type 1 burst interface may have a BDIP signal as one of its inputs A mem ory device with a type 2 burst interface has a LAST signal as one of its inputs Refer to 5 16 6 Synchronous Burst Interface for a description of these interface types A device may or may not have the ability to hold off its data output until the data bus is available to the device To be able to hold off its data the device needs an OE control input and if the device is burstable it also needs the ability to suspend its internal state machine from advancing to the next data beat until the data bus has been granted to it An example of this is a memory device with burst address advance control such as BDIP to control the incrementing of its internal a
144. hen the pin uses BDIP timing If the bit is set the pin uses LAST timing The timing protocol of the external memory determines whether this bit should be set or cleared Refer to 5 16 6 Synchronous Burst Inter face for examples of both types of timing Burst cycles can also be terminated with the ARETRY signal Refer to 4 10 Address Retry for more information 4 6 2 Burst Inhibit Cycles Burst Inhibit Bl is an address phase termination attribute that is sampled when AACK is asserted The slave asserts BI to indicate to the SIU that the addressed device does not have burst capability If this signal is asserted the SIU transfers the data in multiple SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 11 Go to www freescale com 4 4 Freescale Semiconductor Inc cycles and increments the address for the slave in order to complete the burst transfer A burst can only be burst inhibited until the first data is acknowledged TA asserted Since BI is not sampled until AACK is asserted AACK must be asserted before or at the same time as TA Otherwise the BI pin is never sampled The EBI supports three types of memory These memory types use the AACK and BI signals as follows e A simple asynchronous memory keeps AACK negated to keep the address valid The device can assert BI along with AACK or before AACK and with the first TA e Asynchronous pipelineable non burstable mem
145. her the address is word or double word aligned the EBI wraps the address to fetch the correct data from memory four words or eight half words If the EBI receives TEA for one part of a decomposed cycle it generates TEA internally for the remaining parts of the decomposed cycle as well MOTOROLA EXTERNAL BUS INTERFACE SIU 4 12 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 4 5 Burst Access Address Wrapping Port Size Starting Burst Address Wrapping Half Word Word Boundary Address Address ADDR 28 30 ADDR 28 30 16 bit 000 000 Starting address Double word boundary 001 2 bursts of 4 beats each 010 011 100 101 110 111 16 bit 010 010 Starting address Odd word boundary 011 1 burst of 2 beats 1 burst of 4 beats 100 1 burst of 2 beats 101 The master the EBI terminates the two 110 beat burst with BDIP 111 000 001 32 bit 000 000 Starting address Quad word boundary 010 1 burst of 4 beats 100 110 32 bit 100 100 Starting address Double non quad word boundary 110 1 burst of 4 words word 3 4 1 2 000 010 4 8 Preventing Speculative Loads The SIU can be programmed to prevent speculative loads to a selected external re gion A speculative operation is one which the hardware performs out of order and which it otherwise might not perform such as executing an instruction following a con ditional branch Not
146. inuously after power up unless the decrementer clock enable bit is cleared System software is necessary to perform any initialization The decrementer is not affected by reset and continues counting while reset is assert ed Reads and writes of the time base and decrementer are restricted to special instruc tions Refer to the RCPU Reference Manual RCPURM AD for instructions on reading and writing the time base and decrementer 6 9 1 Time Base and Decrementer Clock Source The TBS bit in the SCCR register controls which clock source drives the time base and the decrementer When TBS is cleared the frequency source is the crystal oscillator divided by four When TBS is set the frequency source is the system clock divided by four SIU CLOCK SUBMODULE MOTOROLA REFERENCE MANUAL For More Information On This Product 6 13 Go to www freescale com Freescale Semiconductor Inc The default source clock is the 4 MHz crystal oscillator 4 With this clock source the period for the time base is Trp 264 1MHz 1 8 x 1013 seconds which is approximately 585 000 years With the same clock source the period for the decrementer is Tpec 222 1MHz 4295 seconds which is approximately 71 6 minutes The time base and the decrementer should be initialized after the TBS is written to avoid the possibility of corrupting the time base as the clock source is switched 6 9 2 Time Base Decrementer and Freeze Assertion The asser
147. ion On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc All transfer errors that occur during an access to a 16 bit port terminate the cycle cur rently in progress If an error occurs during any part of a word access to a 16 bit port the current access is terminated Subsequent bus cycles of the small port access will continue but TEA will be asserted internally with each beat All illegal accesses to internal registers are terminated with a data error causing the bus monitor to assert the internal TEA signal Accesses to unimplemented internal memory locations and privilege violations user access to supervisor register or write to read only location or a write to register which is locked also cause the bus monitor to assert the internal TEA signal Note that the chip select module can also assert the internal TEA signal Refer to 5 7 Access Protection for more information 4 12 Cycle Types The cycle type pins CT 0 3 are address phase signals that provide information about the type of internal or external bus cycle in progress These pins can be used by an external development system to construct a program trace Table 4 10 summarizes the cycle type encodings Refer to the RCPU Reference Man ual RCPURM AD for details on how a development system can use the information provided by these pins Table 4 10 Cycle Type Encodings CT 0 3 Cycle Type Description 0000 Normal bus cycle This is
148. ip select circuit is programmed to return AACK and TA the EBI uses the logical OR of the external TA pin and the internal TA signal returned by the chip select unit Negated While BB is asserted indicates that until TA is asserted the MCU must continue to drive the data for the current write or must wait to sample the data for reads Assertion Must not occur before AACK is asserted for the current transaction TA must not be asserted on cycles ter minated by ARETRY and must not be asserted after the cy cle has been terminated The system can withhold assertion of TA to indicate that the MCU should insert wait states to extend the duration of the data beat Negation Must occur after the clock cycle of the final or only data beat of the transfer For a burst transfer that is not under chip select control the system can assert TA for one clock cycle and then negate it to advance the burst SIGNAL DESCRIPTIONS SIU For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc transfer to the next beat and insert wait states during the next beat 2 2 3 4 Transfer Error Acknowledge TEA Input only Module ER State Meaning Timing Comments 2 2 3 5 Data Strobe DS Output only Module ER State Meaning Timing Comments Asserted By an external device signals a bus error con dition TEA assertion terminates the data phase of the cur rent bus cycle and
149. ip selects A 16 bit port must connect its data lines to the upper 16 bits of the external data bus DA TA 0 15 During an access to a 16 bit port byte enable signals BE 0 1 are used to indicate which bytes of the half word are being accessed and the BE2 ADDR30 pin functions as ADDR30 active high BE3 is asserted low if the operand size is a word and ne gated high if the operand size is a byte or half word This encoding is needed to maintain coherency of word accesses on the external bus Table 4 9 shows how EBI decomposes the word half word and byte accesses to a 16 bit port For each combination of operand size and address placement on the in ternal L data bus the table shows the values of BE 0 3 and indicates which bytes of the operand are accessed and where these bytes are placed on the E bus Table 4 9 EBI Read and Write Access to 16 Bit Ports Operand Size Internal L Bus Internal L Bus BE 0 3 Placement of L Bus Data Bytes On E Bus ADDR 30 31 Data Bytes E Bus DATA 0 7 E Bus DATA 8 15 Accessed Byte 00 Byte 0 0101 Byte 0 X Byte 01 Byte 1 1001 X Byte 1 Byte 10 Byte 2 0111 Byte 2 X Byte 11 Byte 3 1011 X Byte 3 Half Word 00 Bytes 0 to 1 0001 Byte 0 Byte 1 Half Word 10 Bytes 2 to 3 0011 Byte 2 Byte 3 Word 00 Bytes 0 to 3 0000 Byte 0 Byte 1 0010 Byte 2 Byte 3 All transfer errors that occur during a small port access terminate the cycle currently in progress If a
150. irings c ccccceeeeeeeeeeeeeeeeeeeeeeeeeeees 5 12 5 6 2 Programming the Sub Block Option Register cccceeeeees 5 13 5 6 3 Multi Level Protection for CSBOOT EE 5 13 5 7 Access Protection ME 5 13 5 7 1 Supervisor Space Protection ccecccceeeesseeseeeeseeeeeeeeeeeeeeeeeeeeeeess 5 14 SIU MOTOROLA REFERENCE MANUAL For More Information On This Product Go to www freescale com V Preeaglt sptentier me Continued Paragraph Title Page 5 7 2 Data Space Protection WEE 5 14 5 7 3 Write Protection EE 5 14 5 8 Cache Inhibit Control E 5 14 5 9 Handshaking COmiols t 22 ciietel ocak eege ie ee geleed ety 5 15 5 10 Wail State Control ee Ee 5 15 5 11 POM E 5 16 5 12 Chip Select Pin Control E 5 16 5 12 1 Pin Config ration ee 5 16 5 12 2 Byte Enable n E 5 17 5 12 3 Region Control EE 5 17 5 13 Interface Types deeg e Bee ht ve 5 17 5 13 1 Interface Type Descriptions EE 5 18 5 13 2 Turn Off Times for Different Interface Types cccceeeeeeeeeeeees 5 20 5 13 3 Interface Type and BI Generation EE 5 20 5 14 Chip Select Operation Flow Chart sssssssssssssennnsssrsrernnsserrrnrnnsserrrrrnnseee 5 21 Bayon PipeTracking Ee 5 21 5 15 1 Pipelined Accesses to the Same Region c cceeeeeeeeeeeeeenees 5 22 5 15 2 Pipelined Accesses to Different Regions ee 5 23 5 16 Chip Select Timing Diagrams ENEE 5 24 5 16 1 Asynchronous En e 5 25 5 16 2 Asynchronous Interface With Latch Enable
151. it for a transfer acknowledge In addition if the processor is executing normally and runs a bus cycle that is not ter minated a non maskable breakpoint always gains control of the processor by termi nating the bus cycle with the bus monitor so the processor can enter debug mode In this case the non maskable breakpoint is not restartable The processor takes the breakpoint before completing the prologue of the exception handler called as a result of the bus monitor 3 6 2 Effects of Freeze on the Programmable Interrupt Timer PIT When freeze is asserted and the SIU freeze bit SIUFRZ is set in the SIU module con figuration register SIUMCR the PIT is disabled This disable overrides the periodic interrupt enable bit PIE in the periodic interrupt control and select register PICSR in the SIU This allows the count in the PIT to be preserved when execution stops 3 6 3 Effects of Freeze on the Decrementer When freeze is asserted and the SIUFRZ is set in the SIUMCR the decrementer is disabled This allows the value in the decrementer to be preserved when execution stops 3 6 4 Effects of Freeze on Register Lock Bits When freeze is asserted the lock bits in various registers can be set or cleared This allows the protected configurations to be changed and then re locked by a develop ment support system MOTOROLA MODULE CONFIGURATION SIU 3 10 For More information On This Product REFERENCE MANUAL Go to www freescale com Fre
152. l is active low Active low signals are referred to as asserted active when they are low and negated when they are high mnemonics Instruction mnemonics are shown in lowercase bold italics Italics indicate variable command parameters for example bcctrx SIU PREFACE MOTOROLA REFERENCE MANUAL For More Information On This Product xiii Go to www freescale com Freescale Semiconductor Inc Ox0F Hexadecimal numbers 0b001 1 Binary numbers rA O The contents of a specified GPR or the value 0 REG FIELD Abbreviations or acronyms for registers are shown in uppercase text Specific bit fields or ranges are shown in brackets D In certain contexts such as a signal encoding this indicates a don t care For example if a field is binary encoded 0bx001 the state of the first bit is a don t care Nomenclature Logic level one is the voltage that corresponds to Boolean true 1 state Logic level zero is the voltage that corresponds to Boolean false 0 state To set a bit or bits means to establish logic level one on the bit or bits To clear a bit or bits means to establish logic level zero on the bit or bits A signal that is asserted is in its active logic state an active low signal changes from logic level one to logic level zero when asserted and an active high signal changes from logic level zero to logic level one A signal that is negated is in its inactive logic state an active low signal changes from logic level ze
153. le Type ENCOGINGS eggederg ees gege ENEE ee 4 11 EBI Storage Reservation Interface Signals ccceeeeeeeeeees 5 1 Chip Select Pin Functions EE 5 2 Chip Select Module Address Map 5 3 Chip Select Base Address Registers Bit Settings 0 5 4 Chip Select Option Register Bit Gettngs 5 5 Block Size ee a te EE 5 6 Main Block and Sub Block Pairings c eeeeeeeeeeeeenteeeeeeeeees 5 7 TADLY and Wait State Control 5 8 EK SZ reo aloes a ate E EE EE 5 9 Pin Configuration Encodings EN 5 103 BYTE atelier Eege 5 11 REGION Field Encodmgs nn 5 12 Interface TCS as cere cecal thie ee 5 13 Pipelined Reads and Writes nnnnnnaeeneeaeaeeeeneeeeeeeeeeeeernnnnnnnnn 5 14 Data Bus Configuration Word Settings for Chip Selects 6 1 Clocks Module Signal Descriptions ssssseeeeeeeeeenenneeesennnn nenene 6 2 Clock Module Power Guppltes AEN 6 3 System Clock Sources seneenneneeeeeeeeeeeeeeennnrnnnnnnnnnnnnnnnreeeeeeeeeen 6 4 CLKOUT Frequencies with a 4 MHz Crystal 6 5 Multiplication Factor Bits sue Geetesegdeguge deeg Eege 6 6 Reduced Frequency Divider Bits Aen 6 7 Exiting Low Power Mode ccsssecccceeeeeeeeseeeeeeeeeeessseeeeeeeenees 6 8 System Clock Lock Bits ic iisccvsccticceidiiis nina eae SIU REFERENCE MANUAL For More Information On This Product Go to www freescale com MOTOROLA xi Freescale Semiconductor Inc Continued Table Title Page 6 9 SGOGR Eeer
154. ll indemnify and hold IBM and Motorola and their respective officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part MOTOROLA and the Motorola logo are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer PowerPC PowerPC Architecture and POWER are trademarks of IBM Corp used by Motorola under license from IBM Corp MOTOROLA INC 1994 1996 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Ereesde ciktze k eW cbhkter Inc Paragraph Title PREFACE e Ee tke aha an Ai tia atid oll ky cia a AA Ant teh Additional Reading GE Bean nee EE ein AE EEN 1 1 SEENEN ee 1 2 SIU Block Diagram dee ageet Eech 1 3 SIU Address Map EE 1 4 Peripheral Control Unit Overview sssssssssssssssrnnessrrrrrnnnererrrennnee 1 5 PCU Block Diagram 2 diecsbetberrgegieegeek Eve e ed 1 6 PCU Addr ss EE SECTION 2 SIGNAL DESCRIPTIONS 2 1 Pin Characteristics e eege Eet 2 2 el RR ee EE 2 2 1 Bus Arbitration and Reservation Support Signals 2
155. llowing control and status registers associated with the interrupt controller indi cate which of 32 possible interrupt levels are pending and control which interrupt sources are passed on to the CPU e The pending interrupt request register IRQPEND contains a status bit for each of the 32 interrupt levels e The interrupt enable register IRQENABLE contains an enable bit for each of the 32 interrupt levels e The interrupt request levels register PITQIL determines the interrupt request level assigned to each interrupt source If a bit in the IRQPEND register is asserted and the corresponding bit in the IRQEN ABLE register is asserted then the interrupt request line to the CPU will be asserted In other words if an interrupt request is pending on a certain level and that level is en abled in the IRQENABLE register then the CPU IRQ line is asserted These registers are described in greater detail in 10 3 Interrupt Controller Registers Figure 10 1 provides an overview of interrupt management in MPC500 family MCUs INTERRUPT CONTROLLER AND PORT Q MOTOROLA REFERENCE MANUAL For More Information On This Product 10 1 Go to www freescale com 10 30 Freescale Semiconductor Inc MCU IMB2 IMB2 PERIPHERAL PERIPHERAL IMB2 IMB2 IRQ 0 7 MUXED SIU IRQs sl IRQPEND INTERRUPT RQENABLE CONTROLLER IRQAND RCPU IRO IRQ 0 7 MPC505 IR
156. lock associated with the base address 0000 Disables corresponding region 0001 4 Kbytes 0010 8 Kbytes 0011 16 Kbytes 0100 32 Kbytes 0101 64 Kbytes 0110 128 Kbytes 0111 256 Kbytes 1000 512 Kbytes 1001 1 Mbyte 1010 2 Mbytes 1011 4 Mbytes 1100 8 Mbytes 1101 16 Mbytes 1110 32 Mbytes 1111 64 Mbytes Refer to 5 5 Chip Select Regions for more information MOTOROLA CHIP SELECTS SIU 5 8 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 4 Chip Select Option Register Bit Settings Continued Bit s Name Description 4 SBLK Sub block 0 Address space is a main block 1 Address space specified by the BA and BSIZE fields of the corresponding base address and option registers respectively is a sub block within a larger main block Pairing of main blocks and sub blocks is as follows CSBOOT and CS1 CS2 and CS3 CS4 and CS5 Refer to 5 6 Multi Level Protection for more information 5 SUPV Supervisor mode 0 Access is permitted in supervisor or user mode 1 Access is permitted in supervisor mode only Refer to 5 7 1 Supervisor Space Protection for more information 6 DSP Data space only 0 Address block may contain both instructions and data 1 Address block contains data only Refer to 5 7 2 Data Space Protection for more information 7 WP Write protect 0 Block is availa
157. ls Indicate what type of bus cycle the bus master is initiating Refer to Table 4 10 in SECTION 4 EXTERNAL BUS INTERFACE for cycle type encodings Assertion Negation The CT 0 3 signals are address at tributes they are updated at the start of the address phase and maintained until the start of the next address phase High impedance Coincides with negation of BB provided no qualified bus grant exists Depending on the state of the pipeline the data phase starts either one clock cycle after the address phase starts or as soon as the previous data phase completes The data phase completes when it is terminated by transfer acknowledge TA or transfer error acknowledge TEA If the cycle is a burst cycle then multiple TA assertions are required to terminate the data phase Refer to 4 5 3 Data Phase for additional infor mation on data phase signals 2 2 3 1 Data Bus DATA 0 31 Input output Module EBI State Meaning Timing Comments SIU REFERENCE MANUAL For More Information On This Product Asserted Negated Represents the state of data during a read or write 16 bit devices must reside on DATA 0 15 32 bit devices reside on DATA 0 31 Assertion negation On write cycles the SIU drives data one clock after driving TS The data is available until the slave asserts TA During reads the data must be available from the slave with TA The data bus is driven once for non burst transac tions and four times for bu
158. ls on any interrupts generated by on chip peripherals 10 3 Interrupt Controller Registers Control and status registers associated with the interrupt controller indicate which of 32 possible interrupt levels are pending and control which interrupt sources are passed on to the CPU Table 10 2 lists these registers Table 10 2 Interrupt Controller Registers Name Mnemonic Description Pending Interrupt IRQPEND Contains a status bit for each of the 32 interrupt levels Each bit of Request Register IRQPEND is a read only status bit that reflects the current state of the corresponding interrupt signal Interrupt Enable Register IRQENABLE Contains an enable bit for each of the 32 interrupt levels Enabled Active Interrupt IRQAND Logical AND of the IRQPEND and IRQENABLE registers This register Requests Register reflects which levels are actually causing the IRQ input to the CPU to be asserted Interrupt Request PITQIL Contains six 5 bit fields that determine the interrupt request levels of the Levels Register PIT the IRQ 0 2 pins and the IRQ 0 1 signals from on chip peripherals on the L bus 10 3 1 Pending Interrupt Request Register The pending interrupt request register IRQPEND is a read only status register that reflects the state of the 32 interrupt levels IRQPEND Pending Interrupt Request Register 0x8007 EFAO 0 1 2 3 4 5 6 7 8 9 10 1
159. m clock lock and status register SCLSR contains several bits that lock the corresponding bits or fields in the system clock control register SCCR Table 6 8 summarizes the lock bits and the fields that they control Table 6 8 System Clock Lock Bits SCLSR Lock Bit Field in SCCR MPL MF LPML LPM RFDL RFD When a lock bit MPL LPML or RFDL is cleared writes to the corresponding bit or field in the SCCR MF LPM or RFD respectively take effect When the lock bit is set however writes to the corresponding bit or field in the SCCR have no effect All other bits in the SCCR are unaffected The MPL LPML and RFDL bits can be written to zero as many times as required Only a clock reset can clear one of these bits however once it is written to a one In freeze mode the lock bits can be written to a one or to a zero at any time MOTOROLA CLOCK SUBMODULE SIU 6 12 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 6 8 Power Down Wake Up PDWU power down wake up is an output signal used to signal an external power supply to enable power to the system PDWU can be asserted by the decrementer counting down to zero or by the CPU setting the wake up request WUR bit in the SCLSR The WUR bit controls the state of the PDWU pin directly The WUR bit is set when the CPU writes a one to it or when the MSB of the decrementer changes from a zero to a one W
160. mode determine when RESETOUT is released e If the PLL is operating in 1 1 mode or the data bus configuration bit 19 is cleared RESETOUT is released when the PLL is locked e If data bus configuration bit 19 is set and the PLL is not operating in 1 1 mode RESETOUT is released as soon as the 17 clock cycles have finished When the PLL is operating in 1 1 mode the MCU waits until the PLL is locked before releasing RESETOUT since the clock which is an input to the MCU may also be used as an input to other bus devices In addition if other bus devices use the MCU CLK OUT signal to feed a PLL the user must ensure that the PLL is locked before RE SETOUT is released This is achieved by clearing data bus configuration bit 19 at reset While RESETOUT is being asserted the SIU requests control of the I bus and L bus The IMB2 interface requests control of the IMB2 bus Internal reset is released when RESETOUT is released however the internal buses are not released until 16 clock cycles after RESETOUT is negated If an external reset is asserted any time during this process this process begins again This flow is depicted in Figure 8 1 8 2 2 Internal Reset Request Flow Figure 8 2 is a flow diagram for internal reset requests MOTOROLA RESET OPERATION SIU 8 4 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc TO EXTERNAL RESET FLOW 2 IF RESET 0 Le
161. n This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc rupts are assigned by programming the PITQIL register The request levels of IRQ 3 7 external interrupts are assigned fixed values as explained below A block diagram of the interrupt controller and its inputs is shown in Figure 10 2 DATAI31 0 IRQPEND IRQ 0 7 IMB2 TRO O 7 m gt PORTQ BOCH TEST IRQ 0 7 STATE z MACHINE 76 ul Se L BUS BO LEVEL WEE SIS IRQ gt como Pom SCC E IRQMUX 0 1 c E gt 5 a RESET ee 8 E p RAREST IMB2CLOCK Le 4 MPC500 IRQ CONT BLOCK Figure 10 2 Interrupt Controller Block Diagram Figure 10 3 illustrates the interaction of the interrupt controller IRQ inputs and port Q operation SIU INTERRUPT CONTROLLER AND PORT Q MOTOROLA REFERENCE MANUAL For More Information On This Product 10 3 Go to www freescale com Freescale Semiconductor Inc L BUS INTERNAL IMB IRQs EXT IRQO ANY LEVEL EXT IROT ANY LEVEL EXT DOS ANY LEVEL EXT IROS o 5 TROG INTERRUPT GE Ss CONTROLLER EXT IRQ4 oun IRS k S L BUS pop EXT IRO5 Gg ROD EXT IRQ6 IRQ 2 EXT IRQ7 RaT OR CPU IRQ MPC500 IRQ PORT BLOCK Figure 10 3 Port Q IRQ Functional Block Diagram MOTOROLA INTERRUPT CONTROLLER AND PORT Q SIU 10 4 For More information On This Produc
162. n error occurs during any part of a word access to a small port the cur rent access is terminated Subsequent bus cycles of the small port access will contin ue but TEA will be asserted internally with each beat SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 15 Go to www freescale com Freescale Semiconductor Inc 4 10 Address Retry Address retry ARETRY can be used to terminate the address phase Assertion of ARETRY causes the master to re arbitrate and to re run the bus cycle The address retry mechanism can be used to break deadlocks between the E bus and the user s on board I O bus for example a PC AT or VME bus in a hierarchical bus system The address retry mechanism can also be used for error correction purposes After receiving TS the external device must wait at least one clock cycle before as serting ARETRY Note that this could be an issue at low frequencies it is possible for an external device to receive TS decode the address and assert ARETRY in the same clock cycle This is illegal The SIU does not guarantee word coherency if ARETRY is asserted for the second half of a word cycle of a decomposed word transfer The external arbiter is responsible for maintaining the coherency by monitoring the byte enable lines and making sure that no other master updates that location until the retried cycle is successfully com pleted Note that BB is not negated until the
163. n if PQEDG field is set to A write has no effect Level otherwise from port Q edge detect logic 10 4 2 2 Port Q Edge Fields The port Q edge PQEDGE 0 7 fields select whether the port interrupt pin is edge sensitive or level sensitive When the selected transition occurs on a port Q pin a cor responding status bit is set in the PQEDGDAT register Table 10 5 explains the encodings for PQEDGE fields Table 10 5 Port Q Edge Select Field Encoding PQEDGE Edge Select PORTGQE Port Q Value Edge Detect Field 00 Level sensitive Returns zero when read 01 Falling edge sensitive Set on rising edge D 10 Rising edge sensitive Set on falling edge 11 Either edge sensitive Set on either edge MOTOROLA INTERRUPT CONTROLLER AND PORT O SIU 10 10 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc GLOSSARY OF TERMS AND ABBREVIATIONS The glossary contains an alphabetical list of terms phrases and abbreviations used in this book Some of the terms and definitions included in the glossary are reprinted from EEE Std 754 1985 IEEE Standard for Binary Floating Point Arith metic copyright 1985 by the Institute of Electrical and Electronics Engineers Inc with the permission of the IEEE A Atomic A bus access that attempts to be part of a read write operation to the same address uninterrupted by any other access to that address the term
164. n the peripherals controller unit provides edge sensitive or level sensitive I O Refer to SECTION 10 INTERRUPT CONTROLLER AND PORT Q for information on port Q Table 9 1 is an address map of the SIU port registers Table 9 1 SIU Port Registers Address Map Access Address Register S 0x8007 FC60 PORT M DATA DIRECTION DDRM S 0x8007 FC64 PORT M PIN ASSIGNMENT PMPAR 0x8007 FC68 PORT M DATA PORTM 0x8007 FC6C RESERVED 0x8007 FC80 0x8007 FC84 PORT A B PIN ASSIGNMENT PAPAR PBPAR 0x8007 FC88 PORT A B DATA PORTA PORTB 0x8007 FC8C RESERVED 0x8007 FC94 S 0x8007 FC98 PORT J K L DATA DIRECTION DDRI DDRJ DDRK DDRL S 0x8007 FC9C PORT I J K L PIN ASSIGNMENT PIPAR PJPAR PKPAR PLPAR S U 0x8007 FCAO PORT I J K L DATA PORTI PORTJ PORTK PORTL 0x8007 FCA4 RESERVED 0x8007 FCFF 9 1 Port Timing Ports A through L can be used with a port replacement unit PRU These ports provide three clock cycle access If PRU mode is enabled at reset access to these registers is disabled and an external bus cycle is initiated Other non PRU ports provide two clock cycle access Input port pins are sampled synchronously SIU GENERAL PURPOSE I O MOTOROLA REFERENCE MANUAL For More Information On This Product 9 1 Go to www freescale com Freescale Semiconductor Inc After a pin assignment or data direction register is modified the change may require an additional clock cycle to take effe
165. nal is sampled at the same time the MCU samples the arbitration pins for a qualified bus grant prior to starting a bus cycle 2 2 2 Address Phase Signals The address phase is the period of time from the assertion of transfer start TS until the address phase is terminated by one of the following signals address acknowledge AACK address retry ARETRY or transfer error acknowledge TEA TS is valid for one clock cycle at the start of the address phase The address bus and the address attributes described below are valid for the duration of the address phase Refer to 4 5 2 Address Phase for additional information on address phase signals MOTOROLA SIGNAL DESCRIPTIONS SIU 2 4 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 2 2 2 1 Address Bus ADDR 0 29 Output only Module ER State Meaning Timing Comments 2 2 2 2 Write Read WR Output only Module ER State Meaning Timing Comments Asserted Negated Represents the physical address of the data to be transferred Driven by the bus master to in dex the bus slave Low order bit ADDR31 is not pinned out byte enable signals BE 0 3 are used instead see Ta ble 2 2 During accesses to 16 bit ports BE2 pin provides ADDR30 signal Assertion Negation Occurs one clock cycle after a quali fied bus grant Coincides with assertion of BB and TS High impedance Coincides with negation of BB provi
166. ng Low Power E 6 12 6 7 System Clock LOCK Bits AAA 6 12 6 8 Power Down Wake Up EEN 6 13 6 9 Time Base and Decrementer Support cccceeeeeeeeeeeeeeeeeeeeneeeeeeeteees 6 13 6 9 1 Time Base and Decrementer Clock Source cccceeceteteeeeeeeees 6 13 6 9 2 Time Base Decrementer and Freeze Assertion ceeeeeeeeeeeeeees 6 14 6 9 3 Decrementer Clock Enable DCE Bit eeeceseeeeeeeeeeeeeeeeeees 6 14 6 107 Clock EE 6 14 6 10 1 LOSS OF PEE EE steet EE 6 14 6 10 2 LOSS Of EE 6 15 6 11 System Clock Control Register SCOR aa 6 15 6 12 System Clock Lock and Status Register GC 6 17 SECTION 7 SYSTEM PROTECTION 7 1 System deele BET 7 1 7 2 System Protection Programming Models 7 1 7 3 Periodic Interrupt Timer PIT EE 7 1 7 3 1 PIT Clock Frequency Selection EE 7 2 7 3 2 PIT Time Out Period Selection EE 7 3 7 3 3 PIT Enable Bus minana a a E N tess 7 4 7 3 4 PIT Interrupt Request Level and Status cccceeeseeeeeeeeeeeeeeeeeeees 7 4 7 3 5 Periodic Interrupt Control and Select Register cceeeeeeeeeees 7 4 7 3 6 Periodic Interrupt Timer Register ccccccceeeeeeeeeneeeeeeeeeeeeeeeeeees 7 5 7 4 Hardware Bus Monitor AEN 7 5 7 4 1 Bus Monitor Timing EE 7 5 7 4 2 Bu us Monitor e EE 7 6 7 4 3 Gelee EE 7 6 7 4 4 Bus Monitor Control Register cccccccceneeeeeeeeeeeeeneeeeeeeeeeeseaeeeees 7 6 7 5 Software Watchdog EE 7 7 7 5 1 Software Watchdog Service Register
167. ng of data to the slaves during write cycles e Keeps slave sequentially consistent data in the same order as addresses e Programmability for latching and non latching device types burstable and non burstable device types e Programmable address range block size e Programmable burst features interruptible burst on any burstable device pipelineable with other devices during burst cycle supports two different burst protocols e Supports pipelineable accesses up to two concurrent accesses can be outstanding to two different regions one access to each region for two consecutive accesses to the same region overlaps the address phase of the second access with the data phase of the first access e Allows multi level protection within a region The CSBOOT region can have up to two sub levels of protection e Supports both 16 bit and 32 bit port sizes 5 2 Chip Select Block Diagram Figure 5 2 shows the functional block diagram of the chip select module MOTOROLA CHIP SELECTS SIU 5 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc DECODE BUS ADDRESS DECODER TIMING PIN CONFIGURATION BUS LOGIC CIRCUIT CONTROL 3 UNIT PIN CONFIGURATION PIN 1 ba LOGIC CIRCUIT CONTROL UNIT gt LI LI e LI LI LI LI PIN CONFIGURATION Ez LOGIC CIRCUIT CONTROL REGISTER wT MPC500 CS BLOCK Figure 5 2 Chip Sel
168. nsaction on the external bus before placing the chip except clocks and PLL in reset The SIU requests the L bus and I bus and removes the qualified bus grant from the EBI to make sure that no new transaction is started The SIU waits for 32 clock cycles after internal reset request is asserted or for the EBI to indicate that the SIU is idle whichever occurs first Then the SIU asserts RE SETOUT and internal reset RESETOUT and internal reset will be driven out to put the chip into reset Four clock cycles after the assertion of RESETOUT all mode select pins will be sampled except Vppsn DSCK and MODCLK pins which are sampled at the rising edge of RESETOUT RESETOUT is held for a minimum of 15 clock cycles After the 15 clock cycles the state of data bus configuration bit 19 determines when RESETOUT is released e If the PLL is operating in 1 1 mode or the data bus configuration bit 19 is cleared RESETOUT is released when the phase locked loop PLL is locked e If data bus configuration bit 19 is set and the PLL is not operating in 1 1 mode RESETOUT is released as soon as the 15 clock cycles have finished Internal reset is released when RESETOUT is released however the internal buses are not released until 15 clocks after RESETOUT is negated If an external reset is asserted any time during this process the external reset flow be gins This flow is depicted in Figure 8 2 8 2 3 Reset Behavior for Different Clock Modes Table 8
169. nterface type if the MCU receives TA before asserting OE OE may still be asserted and may remain asserted 0011 Synchronous region no burst with synchronous OE Refer to Figure 5 11 A de vice with this type of interface is pipelineable can function as an asynchronous device and has the ability to hold off its internal data on a read access until OE is asserted The chip select logic asserts OE for one clock cycle on accesses to devices with this interface type A device with synchronous OE must be programmed for one or more wait states If the region is programmed for zero wait states with synchronous OE the chip select logic still generates the OE as if the region were programmed for one wait state 0100 Reserved 0101 Region with fixed burst access capability burst type 1 and asynchronous OE Refer to Figure 5 13 and Figure 5 14 A device of this type is pipelineable and can hold off its internal data until OE is asserted The interface keeps the first data beat valid until the BDIP signal indicates that it should send out the next data This interface type can function as an asynchronous interface That is a device with this ITYPE can be assigned to the CSBOOT region which comes out of reset configured as an asynchronous region with seven wait states In this case the MCU doesn t latch the data to be read until the assigned number of wait states have elapsed and OE is asserted 0110 Reserved 0111 Region wit
170. oduct 6 11 Go to www freescale com Freescale Semiconductor Inc 6 6 5 Exiting Low Power Mode Table 6 7 summarizes the events that cause the MCU to exit from each of the three low power modes Table 6 7 Exiting Low Power Mode Event Causing Exit Mode 0x1 Mode 0x2 Mode 0x3 from Low Power Mode RESETOUT assertion Yes Yes Yes TRQ pin assertion if LPMM 1 Yes Yes Yes Decrementer interrupt Yes Yes No PIT interrupt Yes Yes No The low power mode mask LPMM bit in the SCCR is used to mask the IRQ 0 1 pins to the low power mode exit logic When the LPMM bit is zero the IRQ 0 1 pins are disabled from causing an exit from any of the low power modes When the LPMM bit is a one the IRQ 0 1 pins are enabled to cause an exit from any of the low power modes When a low level occurs at the IRQ 0 1 pins and the LPMM bit is a one the LPM bits are cleared and the low power mode exit sequence begins If the LPMM bit 1 then the low power mode exit sequence is started even if a low power mode is not selected The time required to exit the low power modes depends on which mode was selected For modes 1 and 2 the delay from the exit signal being asserted to the clocks starting up is two clock cycles of the frequency that the VCO was programmed to generate The delay for mode 3 is the crystal start up time plus the VCO lock time The LPMM bit can be read or written any time 6 7 System Clock Lock Bits The syste
171. on On This Product 6 7 Go to www freescale com Freescale Semiconductor Inc low for precise phase alignment System applications must not rely on precise phase alignment between the reference and system clocks when the PLL is operating in nor mal frequency synthesis mode In 1 1 mode however the RFD is disabled The feedback clock comes directly from the CLKOUT pin and true phase lock is achieved 6 5 CLKOUT Frequency Control The multiplication factor MF and reduced frequency divide RFD fields in the SCCR determine the system clock CLKOUT frequency Table 6 4 summarizes the avail able CLKOUT frequencies with a 4 MHz crystal Table 6 4 CLKOUT Frequencies with a 4 MHz Crystal RFD 0 3 CLKOUT Hz MF X000 MF X001 MF X010 MF X011 MF X100 MF X101 MF X110 MF X111 x4 x5 x6 x7 x8 x9 x10 x11 0 0000 1 16 000M 20 000M 24 000m 28 000 M 32 000 M 36 000 M 40 000 M 44 000 M 1 0001 2 8 000M 10 000M 12 000M 14 000M 16 000 M 18 000 M 20 000 M 22 000 M 2 0010 4 4 000M 5 000M 6 000M 7 000M 8 000M 9 000M 10 000M 11 000 M 3 0011 8 2 000M 2 500M 3 000M 3 500M 4 000M 4 500M 5 000M 5 500M 4 0100 16 1 000M 1 250M 1 500M 1 750M 2 000M 2 250M 2 500M 2 750M 5 0101 32 0 500M 0 625M 0 750M 0 875M 1 000M 1 125M 1 250M 1 3750 M
172. on Support Signals The bus arbitration signals request the bus recognize when the request is granted and indicate to other devices when mastership is granted There are no separate ar bitration phases for the address and data buses For a detailed description of how these signals interact see 4 5 1 Arbitration Phase The cancel reservation CR signal is used to indicate that the processor should not perform any stwex cycle to external memory This signal is sampled at the same time the MCU samples the arbitration pins for a qualified bus grant 2 2 1 1 Bus Request BR Output only Module ER MOTOROLA SIGNAL DESCRIPTIONS SIU 2 2 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc State Meaning Timing Comments 2 2 1 2 Bus Grant BG Input only Module ER State Meaning Timing Comments SIU REFERENCE MANUAL Asserted Indicates the potential bus master is requesting the bus Each master has its own bus request signal The SIU asserts BR to request bus mastership if its bus grant BG pin is not already asserted and the bus busy BB has not been negated by the current bus master The SIU assumes mastership of the external bus only after receiving a qualified bus grant This occurs when the bus arbiter asserts BG to the SIU and the BB pin has also been negated by the previous bus master The SIU cannot start a cycle on the external bus if the current ma
173. onfigured to be a WE or OE pin For example a PCON en coding of 0b10 and a REGION encoding of 06001 configures the pin as an OE of the memory region defined by CS1 REGION field encodings are shown in Table 5 11 Table 5 11 REGION Field Encodings REGION Memory Region Defined by 0b000 CSBOOT 0b001 CST 0b010 CS2 0b011 CS3 0b100 CS4 0b101 CS5 0b110 Reserved 0b111 Reserved 5 13 Interface Types The chip select module supports a wide variety of devices The interface type ITYPE field in the option registers for CSBOOT and CS 1 5 identifies the characteristics of the device interface These characteristics include whether the external device inter face e Is synchronous or asynchronous e Supports pipelined accesses e Can hold off its internal data SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 17 Go to www freescale com Freescale Semiconductor Inc e Has a synchronous OE an asynchronous OE or no OE e Is burstable or non burstable e Uses the LAST or BDIP protocol for ending a burst transmission The following paragraphs define these concepts A burstable device can accept one address and drive out multiple data beats A burst able device must be synchronous Note that devices with fast static column access are not considered burstable This class of devices is considered asynchronous Two accesses are overlapped if they are aligned such t
174. only and three state I O buffers shown in Figure 2 1 D_IN D_EN OUTPUT Ge PIN D_OUT OUTPUT ONLY BUFFER 3 STATE BUFFER MPC500 I O BUFFERS Figure 2 1 Output Only and Three State I O Buffers Table 2 1 EBI Pin Definitions Mnemonic Buffer Weak When Bus is Granted When Bus Is Not During Reset Type Pull Up Granted Address and Data Bus CS 0 17 AD Output Float unless configured Initially high changes 5 DR 0 11 only as output port clock cycles after reset source is negated ADDR 12 29 3 state Driven unless config Float unless configured Float ured as input port as output port DATA 0 31 3 state Driven if write float if Float unless configured Float read as output port Transfer Attributes WR Output unless config Float unless configured BURST ured as input ports as output port BE 0 3 AT 0 1 CT 0 3 Transfer Handshakes ured as input port as output port ed Input unless configured Float unless configured as an output port as output port ed SIU SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product 2 1 Go to www freescale com 3 state Freescale Semiconductor Inc Table 2 1 EBI Pin Definitions Continued Mnemonic Buffer Weak When Bus is Granted When Bus Is Not During Reset Type Pull Up Granted BDIP LAST 3 state No Output unless config Float unless configured Input port After reset ured as inp
175. ory returns AACK as soon as it is ready to receive the next address and asserts BI e A burstable memory returns AACK and negates BI along with AACK or before AACK CAUTION If a memory region is under chip select control the chip select unit generates BI internally during burst accesses to interface types that do not support burst accesses It is recommended that the BI pin not be asserted during accesses to memory regions controlled by chip selects instead the chip select unit will generate the BI signal inter nally when appropriate 4 7 Decomposed Cycles and Address Wrapping If a burst cycle initiated by one of the internal buses is burst inhibited by the chip se lects or by the pins the EBI decomposes this cycle into four single beat accesses The EBI increments the address internally and sends the received data from the four sin gle external reads back to the originating bus as a burst transaction The EBI breaks a burst access to a device with a 16 bit port into two or three cycles depending on the starting address or eight cycles if BI is asserted and increments the address appropriately Examples of burst access address wrapping are shown in Table 4 5 If a burst access to a device with a 16 bit port is burst inhibited by the chip selects or by external memory asserting the BI pin the EBI decomposes the transfer into eight single beat accesses Depending on the starting address for the burst access and whet
176. other internal bus SIU MOTOROLA REFERENCE MANUAL For More Information On This Product G 1 Go to www freescale com MOTOROLA G 2 Freescale Semiconductor Inc Exception An unusual or error condition encountered by the processor that results in special processing Fixed transaction A bus transaction that couples the address and data phase of the bus cycle together as a single event All E bus transactions are fixed transactions Hold off The ability for a device to delay its data output until the data bus is available To be able to hold off its data the device needs an OE control input and if the device is burstable it also needs the ability to suspend its internal state machine from advancing to the next data beat until the data bus has been granted to it l Bus Internal instruction bus connecting the processor to instruction memory IMB2 Second generation intermodule bus The IMB2 which is comparable to the IMB on modular M68300 and M68HC16 family MCUs connects each on chip peripheral to the RCPU Lem Memory that resides on the l bus Interrupt An external signal that causes the processor to suspend current execution and take a predefined exception L Bus Internal load store bus connecting the processor to internal modules and data memory and to the external bus interface LIMB L bus to IMB2 interface The LIMB connects the internal load store bus to the internal intermodule bus Little endian A byte o
177. our to one multiplexing scheme is used the IMB2 IRQ lines update eight of the 32 bits of the IRQPEND register during each clock cycle A maximum latency of four clock cycles and an average latency of two clock cycles result before the interrupt request can reach the interrupt controller Figure 10 4 illustrates the timing for the four to one multiplexing scheme IMB2 CLOCK IMB2 IRQ 0 7 CH ES EH EH dc MPC500 IRQ MUX TIM Figure 10 4 Time Multiplexing Protocol For IRQ Pins SIU INTERRUPT CONTROLLER AND PORT Q MOTOROLA REFERENCE MANUAL For More Information On This Product 10 5 Go to www freescale com Freescale Semiconductor Inc The IRQMUX field in the PCU module configuration register PCUMCR selects the type of multiplexing the interrupt controller performs Refer to Table 10 1 3 3 Periph eral Control Unit Module Configuration Register provides a description of the PCUMCR Table 10 1 IMB2 Interrupt Multiplexing IRQMUX 0 1 Available IRQ Lev Type of Multiplex Maximum Latency els ing 00 TRQ 0 7 None 1 clock cycle 01 TRQ 0 15 Two to one 2 clock cycles 10 TRQ 0 23 Three to one 3 clock cycles 11 TRQ 0 37 Four to one 4 clock cycles Time multiplexing is disabled during reset but the reset default value enables time multiplexing as soon as reset is released Refer to the user s manual for the particular microcontroller for detai
178. ower on Reset Power on reset occurs when the VDDKAP1 pin is high and Vpp makes a transition from zero to one The SIU does not have a power on reset circuit This function must be provided externally NOTE During the first two clock cycles of power on reset the state of the address bus chip select pins is unknown MOTOROLA RESET OPERATION SIU 8 10 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 9 GENERAL PURPOSE I O Many of the pins associated with the SIU can be used for more than one function The primary function of these pins is to provide an external bus interface When not used for their primary function many of these pins can be used as digital I O pins SIU digital I O pins are grouped into eight bit ports The following registers are asso ciated with each I O port Output only ports do not have a data direction register e Pin assignment register allows the user to configure a pin for its primary func tion or digital I O e Data direction register configures individual pins as input or output pins e Data register monitors or controls the state of its pins depending on the state of the data direction register for that pin If a pin is not configured as an I O port pin in the pin assignment register the data di rection and data registers have no effect on the pin In addition to the SIU ports described in this section port Q i
179. p signal from CPU and debug mode not enabled If debug mode is enabled the MCU enters debug mode when the checkstop signal is received regardless of CSR value Refer to the RCPU Reference Manual RCPURM AD for more infor mation on checkstop resets 4 LST Burst style BDIP or LAST 0 BDIP pin uses BDIP timing reset value assert BDIP during burst negate BDIP during last beat of burst 1 BDIP pin uses LAST timing assert LAST during last beat of burst Refer to 5 16 6 Synchronous Burst Interface for more information 5 Reserved 6 7 SUP Supervisor unrestricted space These bits control access to certain SIU registers Other regis ters are always supervisor access only The access restrictions for each register are shown in Table 1 1 00 Unrestricted access reset value 01 Supervisor mode access only 10 Supervisor mode write access only unrestricted read access 11 Supervisor mode access only 8 DLK Debug register lock This bit can be written only when internal freeze signal is asserted DLK al lows development software to configure show cycles and prevent normal software from subse quently changing this configuration This bit overrides the LOK in controlling the LSHOW field 0 LSHOW field in SIUMCR can be written to reset value 1 Writes to LSHOW field are not allowed 9 LOK Register lock Once this bit is set writes to the SIUMCR and chip select registers have no effect and cause a
180. pelined BUS AEN 4 7 4 5 Write Followed by Two Reads on the E Bus Using Chip Selects 4 7 4 6 External Burst Read EES 4 11 4 7 Storage Reservation Guonalmg ENEE 4 20 5 1 Simplified Uniprocessor System with Chip Select Loge 5 1 5 2 Chip Select Functional Block Diagram ccccceeseeceeeeeeeeeeeeeeeeeeeeeseaaees 5 3 5 3 Multi Level Protection EE 5 12 5 4 Chip Select Operation Flow Chart 5 21 5 5 Overlapped Accesses to the Same Hegton 5 22 5 6 Pipelined Accesses to Two Different Hegoons 5 23 5 7 Asynchronous Read Zero Wait Giatesl 5 25 5 8 Asynchronous Write Zero Wait States cccccccececeeeeeeeeeeeeeeeeeeeeeeeeeees 5 25 5 9 Synchronous Read with Asynchronous OE Zero Wait States 5 26 5 10 Synchronous Write Zero Wait Gates 5 27 5 11 Synchronous Read with Early OE One Wait State eeeeeeees 5 28 5 12 Synchronous Read with Early Overlap One Wait Gratel ee 5 29 5 13 Type 1 Synchronous Burst Read Interface sssssssneneeeeennrnneeesrrerereee 5 30 5 14 Type 1 Synchronous Burst Write Intertace 5 31 5 15 Type 2 Synchronous Burst Read Interface nonnsnnnnnnnnnnnnennnnneneeneneeeeee 5 32 6 1 SIU Clock Module Block Diagram xc ebessi ege ees ee 6 2 6 2 Phase Locked Loop Block Diagram AEN 6 5 6 3 Gry StaliOScilaton eebe easy 6 6 6 4 Charge Pump with Loop Filter Schematic ccceeeeeeeeeeeeeeeeeeeeseeees 6 7 7 1 Periodic Interrupt Timer Block Diagram
181. perform reset with a combination of hardware and software The SIU determines whether a reset is valid asserts control signals per forms basic system configuration based on hardware mode select inputs and then passes control to the CPU Reset is the highest priority CPU exception Any processing in progress is aborted by the reset exception and cannot be restarted Only essential tasks are performed dur ing reset exception processing Other initialization tasks must be accomplished by the exception handler routine 8 1 Reset Sources The following sources can cause reset e External reset pin RESET e Loss of oscillator e Loss of PLL lock e Software watchdog reset e Checkstop reset e JTAG reset All of these reset sources are fed into the reset controller The reset status register RSR reflects the most recent source or sources of reset Simultaneous reset re quests can cause more than one bit to be set at the same time This register contains one bit for each reset source A bit set to logic one indicates the type of reset that last occurred Individual bits in the RSR can be cleared by writing them as zeros after reading them as ones Writing individual bits as ones has no effect The register can be read at all times Assertion of the RESET pin clears all bits except the RESET bit RSR Reset Status Register 0x8007 FC4C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESET LOO LOL SW CR JTAG RESERVED
182. pins cannot be CE pins If one of these pins is configured as a chip enable the pin is never asserted A PCON encoding of 0b11 assigns the pin to its alternate function In this case the value in the port A B pin assignment register PABPAR determines whether the pin operates as an address pin or discrete output pin Refer to 9 3 Ports A and B for more information MOTOROLA CHIP SELECTS SIU 5 16 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 5 12 2 Byte Enable Control The BYTE field is applicable only for pins configured as WE pins This field is used to determine to which of the four E bus byte enables the pin corresponds That is the WE pin will be asserted only when the corresponding E bus byte enable is asserted The encoding is shown in Table 5 10 If the region can always be written in 32 bit quantity this field can be programmed to any value Table 5 10 BYTE Field Encodings BYTE Byte Enabled 0b00 Byte enable 0 0b01 Byte enable 1 0b10 Byte enable 2 0b11 Byte enable 3 H the pin is configured as an OE this field is not used It is assumed the OE pin en ables the outputs of all four bytes of the region onto the 32 bit E bus Thus typically a writable region would have multiple WEs one OE and one CE 5 12 3 Region Control The REGION field indicates which memory region the pin is assigned to This field is used only when the pin is c
183. port the SIU will always consider the reservation to be valid 4 14 3 Reservation Storage Signals SIU REFERENCE MANUAL Reservation storage signals used by the EBI are summarized in Table 4 11 Table 4 11 EBI Storage Reservation Interface Signals Name Direction Description CR Snoop logic gt SIU Cancel reservation Each PowerPC CPU has its own CR signal This signal shows the status of any out standing reservation on the external bus When as serted CR indicates that there is no outstanding reservation This is a level signal ARETRY Non local bus interface Address retry When asserted indicates that the SIU master needs to retry its address phase In case of an stwex cycle to a non local bus on which the storage reservation has been lost this signal is used by the non local bus interface to back off the cy cle EXTERNAL BUS INTERFACE MOTOROLA For More Information On This Product 4 21 Go to www freescale com Freescale Semiconductor Inc MOTOROLA EXTERNAL BUS INTERFACE SIU 4 22 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 5 CHIP SELECTS Typical microcontrollers require additional hardware to provide external chip select signals In the MPC500 family the chip select logic controls the slaves of typical uni processor systems This allows the user to implement simple systems without the need to design any extern
184. pports pipelined accesses to different memory regions depend ing on the properties of the two regions The chip select module tracks the incoming cycles and uses the information in the option registers to control the assertion of the CE WE and OE signals For the chip select module to pipeline accesses to two different regions the first region must be pipelineable otherwise the chip select unit waits for the first access to com plete TA asserted before beginning the second access Figure 5 6 uses two synchronous devices IT YPE 2 to illustrate this pipelining case In this example the first access is to a four wait state region and the second access is to aregion with zero wait states For a second region with wait states the pipelining is similar except the data of the second region takes more time to be available on the bus if the second region cannot hold off its internal data The example is intended to show when the CE or address phase and the data phase of the second access can be given to the region It assumes the device s in the first region is pipelineable and both accesses are initiated by the same bus master CLKOUT ADDR lt A1 READ gt lt A2 READ gt d i 1ST ADDRESS LATCHED DATA 2ND CE ASSERTS DES Oj AA my AA MPC500 PIPED ACC TIM Figure 5 6 Pipelined Accesses to Two Different Regions
185. r is a quad latch Type IV phase frequency detector It compares both the phase and frequency of the reference clock oscchk in Figure 6 2 and the feedback clock The reference clock comes from either the crystal oscillator or an ex ternal clock source The feedback clock comes from either CLKOUT the system clock in 1 1 mode or the VCO output divided down by the MF divider in normal mode When the frequency of the feedback clock is less than half the reference clock the phase detector asserts the UP signal continuously When the feedback frequency is less than the reference clock frequency but greater than half its frequency the UP sig nal is pulsed for a fraction of each reference clock cycle When the frequency of the feedback clock equals the frequency of the reference clock i e the PLL is frequency locked the phase detector pulses either the UP or DOWN signal depending on the relative phase of the two clocks If the falling edge of the feed back clock lags the falling edge of the reference clock then the UP signal is pulsed If the falling edge of the feedback clock leads the falling edge of the reference clock then the DOWN signal is pulsed The width of these pulses relative to the reference clock is dependent on how much the two clocks lead or lag each other Once phase lock is achieved the phase detector continues to pulse the UP and DOWN signals for a very short duration during each reference clock cycle These short pulses forc
186. ral devices Audience This manual is intended for system software and hardware developers and applica tions programmers who are developing products that use an MPC500 family micro controller It is assumed that readers understand operating systems microcontroller system design and the basic principles of hardware interfacing Additional Reading This section lists additional reading that provides background to or supplements the information in this manual e John L Hennessy and David A Patterson Computer Architecture A Quantitative Approach Morgan Kaufmann Publishers Inc San Mateo CA e PowerPC Microprocessor Family the Programming Environments MPCFPE AD Motorola order number e Motorola technical summaries and device manuals for individual MPC500 family microcontrollers and module reference manuals such as this manual and the RCPU Reference Manual order number RCPURM AD that describe the opera tion of the individual modules in MPC500 family MCUs in detail Refer to Motorola publication Advanced Microcontroller Unit AMCU Literature BR1116 D for a complete listing of documentation Conventions This document uses the following notational conventions ACTIVE_HIGH Names for signals that are active high are shown in uppercase text without an overbar Signals that are active high are referred to as asserted when they are high and negated when they are low ACTIVE_LOW A bar over a signal name indicates that the signa
187. rate the asynchronous interface for read and write accesses For the asynchronous write the external memory latches the data when WE is asserted CLKOUT L ET ADDR A1 POSSIBLE A2 CE OE DATA D1 MPC500 ASYNC RD TIM Figure 5 7 Asynchronous Read Zero Wait States CLKOUT ADDR K BS K POSSIBLE A2 OUTPUT BUFFERS CORRELATION Ca hi R STROBE IN DAT el DATA Cn pee OE J MPC500 ASYNC WR TIM Figure 5 8 Asynchronous Write Zero Wait States SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 25 Go to www freescale com Freescale Semiconductor Inc 5 16 2 Asynchronous Interface With Latch Enable Devices with an address latch enable signal such as the Motorola MCM62995A mem ory chip also support unlatched asynchronous read and write interfaces as shown in Figure 5 7 and Figure 5 8 The chip select module supports this type of device in the unlatched asynchronous mode only 5 16 3 Synchronous Interface with Asynchronous OE ITYPE 2 Devices with ITYPE 2 have a synchronous interface with an asynchronous output en able Devices of this type clock the address and the data on the rising edge of CLK OUT On a read access these devices drive the data out as soon as the OE is asserted In addition the interface has the ability to latch the address so the next ac cess to the same device can be overlapped with the previous access
188. rdering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte L Mem Memory that resides on the L bus Overlapped accesses Two accesses are overlapped if they are aligned such that the address of the second access is on the external bus at the same time as the data of the first access Park To allow a bus master to maintain mastership of the bus without having to arbitrate SIU For More Information On This Product REFERENCE MANUAL Go to www freescale com W SIU REFERENCE MANUAL Freescale Semiconductor Inc PCU Peripherals control interface Pipelined accesses Two accesses are pipelined if they are aligned such that the address of the second access is on the external bus before the data of the first access Pipelineable device A device is pipelineable if it can latch the address presented to it and does not require the address to be valid on its address pins for the duration of the access to the device RCPU RISC based PowerPC processor The central processing unit in MPC500 family microcontrollers Show cycle An internal access e g to an internal memory reflected on the external bus using a special cycle marked with a dedicated transfer code For an internal memory hit an address only bus cycle show cycle is generated for an internal memory
189. re Information On This Product 8 3 Go to www freescale com Freescale Semiconductor Inc The external reset flow begins when the RESET pin is asserted low The external re set request has a synchronization phase during which it takes one of the two paths synchronous or asynchronous before getting to the reset control logic The external reset request follows the asynchronous path in the case of power on reset or in case of loss of oscillator Under all remaining conditions the reset request goes through the synchronous path in which the reset request is synchronized with the system clock RESET must be as serted for at least two clock cycles to be recognized by the reset control block Once the reset request passes through the synchronization phase the chip enters re set The RESETOUT pin and the internal reset signal are driven while the chip is in reset Note that this internal reset signal is an output from the reset control block that is sent to the internal MCU modules This signal is different from internal reset request which are inputs to the reset control block Six clock cycles after RESET is negated all mode select pins are sampled except for the VDDSN and MODCLK pins These two pins are sampled at the rising edge of RESETOUT After the RESET pin is negated RESETOUT is held for a minimum of 17 clock cycles After the 17 clock cycles the state of data bus configuration bit 19 and the phase locked loop PLL
190. ro to logic level one when negated and an active high signal changes from logic level one to logic level zero LSB means least significant bit or bits MSB means most significant bit or bits Refer ences to low and high bytes are spelled out MOTOROLA PREFACE SIU xiv For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 10VERVIEW The system interface unit SIU and the peripheral control unit PCU provide system protection clocks interrupt support reset control test support chip select support and interfaces to external and internal buses The SIU and PCU are implemented as two separate units that work together to provide system support and interface the pro cessor with both external and on chip memory and peripherals Figure 1 1 shows how the SIU and PCU work with other components of an MPC500 Family microcontroller This section provides an overview of both the SIU and PCU as well as amemory map and block diagram of each module Later sections of this manual describe the opera tion of each SIU and PCU module in detail SIU OVERVIEW MOTOROLA REFERENCE MANUAL For More Information On This Product 1 1 Go to www freescale com Freescale Semiconductor Inc ON CHIP ON CHIP PERIPHERAL PERIPHERAL INTERMODULE BUS 2 IMB2 PERIPHERAL CONTROL UNIT PCU SYSTEM INTERFACE RISC MCU EXTERNAL BUS PROCESSOR d RCPU INTERNAL LOAD STORE BUS
191. rols whether instruction access is allowed to the address block associated with the chip select If DSP is set the address block is designated as data space no instruction access is allowed This feature can be used to prevent the system from inadvertently executing instructions out of data space When an access is made to the region controlled by the chip select the chip select logic compares the DSP bit with the internal AT1 signal which indicates whether the access is to instruction or data space If the chip select logic detects a protection vio lation DSP 1 and AT1 1 it asserts the internal TEA signal and does not assert the external chip enable signal 5 7 3 Write Protection The WP bit in the option registers for CSBOOT the CSBOOT sub block and CS 1 5 controls whether the address block is write protected If WP is set read accesses only are permitted If WP is cleared both read and write accesses are allowed This feature permits the user to protect certain regions such as ROM regions from being inadvert ently written When an access is made to the region controlled by the chip select the chip select logic compares the WP bit with the internal WR signal which indicates whether the ac cess is a read or a write If the chip select logic detects a protection violation WP 1 and WR 0 it asserts the internal TEA signal and does not assert the external chip enable signal 5 8 Cache Inhibit Control The Cl cache inhibit
192. rst transactions High impedance The pins are placed in a high impedance state during reads or while the bus is idle or when the bus is arbitrated away For write cycles the high impedance state occurs on the clock cycle after the final assertion of TA SIGNAL DESCRIPTIONS MOTOROLA 2 9 Go to www freescale com 2 Freescale Semiconductor Inc 2 2 3 2 Burst Data in Progress BDIP Output only Module ER State Meaning Timing Comments Asserted lIndicates the data beat in front of the current one is needed by the master This signal is asserted at the beginning of a burst data phase Negated Indicates the final beat of a burst This signal can be negated prior to the end of a burst to terminate the burst data phase early Assertion Negation When the LST bit in the SIUMCR is set BDIP uses the timing for the LAST signal When LST is cleared BDIP uses the timing for the BDIP signal Refer to 5 16 6 Synchronous Burst Interface for more informa tion High impedance Coincides with negation of BB provided no qualified bus grant exists 2 2 3 3 Transfer Acknowledge TA Input only Module ER State Meaning Timing Comments MOTOROLA 2 10 Asserted Indicates the slave has received the data during a write cycle or returned the data during a read cycle Note that TA must be asserted for each data beat in a burst transaction If the external access is to a chip select region for which the ch
193. rting with the current value The periodic interrupt enable PIE bit in the PICSR enables or disables PIT interrupts When this bit is cleared the PIT does not generate any interrupts The PIT continues to count even when interrupts are disabled 7 3 4 PIT Interrupt Request Level and Status The PIT interrupt request level PITIRQL field in the PIT port Q interrupt level register PITQIL determines the level of PIT interrupt requests Refer to SECTION 10 INTER RUPT CONTROLLER AND PORT Q for a description of this register The PIT status PS bit is set when the PIT issues an interrupt request This occurs when the modulus counter counts to zero The PS bit is cleared by writing it to zero after reading it as a one Attempting to write this bit to one has no effect 7 3 5 Periodic Interrupt Control and Select Register The periodic interrupt control and select register PICSR contains the interrupt status bit as well as the controls for the 16 bits to be loaded into a modulus counter Reserved bits in this register return zero when read This register can be read or written at any time PICSR Periodic Interrupt Control and Select Register 0x8007 FC40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 PTE PIE RESERVED PCFS RESERVED PS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PITC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOTOROLA SYSTEM PROTECTION SIU 7 4 REF
194. s OE on a read or WE on a write for only one word The burstable region may require an early termination signal such as LAST The EBI is expected to provide the early termination indication to the region e For fixed burst access to a burstable region since all burstable types supported by the chip select module allow fixed burst accesses the chip select module keeps the OE or WE asserted for the length of four words unless the cycle is ter minated early e For a burst access to a non burstable region the chip select module asserts the burst inhibit indication to the EBI and treats the access as a single word access e For a fixed burst access to a burstable small port 16 bit device the chip select module keeps the OE or WE valid until the EBI terminates the burst Depending on the starting address of the burst the EBI breaks the access into two or more cycles and increments the address appropriately The small port device is expect ed to wrap as specified in SECTION 4 EXTERNAL BUS INTERFACE e For a single word access to a device with a small port the chip select module al ways performs a single access to the small port device and indicates to the EBI that the device has a 16 bit port If more data is needed the EBI requests the chip selects to perform another access to the device to complete the transfer MOTOROLA CHIP SELECTS SIU 5 32 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale
195. s __Assertion Negation Accesses to these ports require three clock cycles the same as for external accesses to port re placement logic if a port replacement unit PRU is used 2 2 8 2 Ports I J K and L PI 0 7 PJ 0 7 PK 0 7 PL 0 7 Input Output Module Ports State Meaning Asserted Negated Indicates the logic level of the data be ing transmitted Ports I J K and L share a data register PORTI PORTJ PORTK PORTL data direction register DDRI DDRJ DDRK DDRL and pin assignment register MOTOROLA SIGNAL DESCRIPTIONS SIU 2 16 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc PIPAR PJPAR PKPAR PLPAR Timing Comments __Assertion Negation Accesses to these ports require three clock cycles the same as for external accesses to port re placement logic if a port replacement unit PRU is used 2 2 8 3 Port M PM 0 7 Input Output Module ER State Meaning Asserted Negated Indicates the logic level of the data be ing transmitted Timing Comments _Assertion Negation Accesses to port M require two clock cycles 2 2 9 Interrupts and Port Q Signals SIU MCUs contain up to eight external interrupt pins These pins are grouped into a general purpose port port Q When not used as interrupt inputs any of these pins can be used for digital input or output Refer to SECTION 10 INTERRUPT CONTROLLER AND PORT Q for more information on these pins
196. scale com Freescale Semiconductor Inc SCCR System Clock Control Register 0x8007 FC50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED LPMM TBS DCE LOLRE LOORE 0 MF RESERVED CLOCK RESET 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED LPM RESERVED RFD CLOCK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Table 6 9 SCCR Bit Settings Bit s Name Description 0 2 Reserved 3 LPMM Low power mode mask 0 IRQ 0 1 pins cannot be used to wake up from LPM 1 IRQ 0 1 pins can be used to wake up from LPM 4 TBS Time base decrementer source 0 Source is crystal oscillator 4 1 Source is system clock 4 5 DCE Decrementer clock enable 0 Clock to decrementer is disabled 1 Clock to decrementer is enabled 6 LOLRE Loss of lock reset enable 0 Loss of lock does not cause reset 1 Loss of lock causes reset 7 LOORE Loss of oscillator reset enable 0 Loss of oscillator does not cause reset 1 Loss of oscillator causes reset 8 Reserved 9 12 MF Multiplication factor The output of the VCO is divided down to generate the feedback signal to the phase comparator The MF field controls the value of the divider in the PLL feedback loop The MF and RFD fields determine the CLKOUT frequency Refer to Table 6 4 X000 x 4 X001 x 5 X010 x6 X011 x7 X100 x 8 X101 x9 X110 x 10 X111 x 11 13 21 Re
197. se pins are used to add an external capacitor to capacitor the filter circuit of the phase locked loop MODCLK Clock mode select Input The state of this input signal during reset selects the source of the system clock Refer to 6 3 System Clock Sources Vopen Vsssn Synthesizer power Input These pins supply a quiet power source to the VCO ECROUT Engineering clock Output Buffered output of the crystal oscillator The ECROUT reference output output frequency is equal to the crystal oscillator fre quency divided by four PLLL DSDO PLL lock status or Output Phase locked loop status output or debug output debug output PDWU Power down wake Output Asserted or negated respectively by software setting up or clearing the WUR bit in the SCLSR Also asserted when decrementer counts down to zero Can be used as power down wakeup to external power on reset Circuit 6 2 Clock Power Supplies The power supply for each block of the clock submodule is shown in Table 6 2 Table 6 2 Clock Module Power Supplies Power Supply Blocks Von CLKOUT ECR PIT Clock RFD PLL Digital VDDKAP1 Decrementer Time Base Clock Oscillator SCCR SCCSR Vopen PLL Analog To improve noise immunity the PLL has its own set of power supply pins Vppsyn and GNDegyn Only the charge pump and the VCO are powered by these pins The oscillator system clock control register and system clock control and status reg ister are powere
198. second clock cycle after ARETRY assertion CAUTION TA or TEA must not be asserted during a cycle in which ARETRY is asserted If TA is asserted for any part of a burst cycle ARETRY must not be asserted at any time during the cycle if ARETRY is as serted during a burst cycle it must be asserted before the first beat is terminated with TA 4 11 Transfer Error Acknowledge Cycles A bus timer or system address protection mechanism can assert transfer error ac knowledge TEA to terminate the data phase when one of the following types of bus error conditions is encountered e Write to a read only address space e Access to a non existent address TEA assertion overrides the assertion of TA Assertion of TEA causes the processor to enter the checkstop state enter debug mode or process a machine check excep tion Refer to the RCPU Reference Manual RCPURM AD for details CAUTION TEA must not be asserted during a cycle in which ARETRY is assert ed If the address phase corresponding to the current data phase is still outstanding AACK has not yet been asserted TEA terminates both the address and the data phase That is the EBI generates AACK and TA internally and generates an internal error signal for that cycle If AACK has already been asserted externally the EBI gen erates TA but not AACK internally and generates an internal error signal for that cycle MOTOROLA EXTERNAL BUS INTERFACE SIU 4 16 For More informat
199. seeeeeeeeeeeeeseeneeeesseeeeeeeaes 2 17 2 2 9 2 Port Q PQI e e a a EE 2 17 SECTION 3MODULE CONFIGURATION 3 1 SIU Module Configuration Register cc ccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaees 3 1 3 2 Memory Mapping Register kee 3 2 3 3 Peripheral Control Unit Module Configuration Register ceeee 3 3 3 4 Internal Module Select Logic EEN 3 4 3 4 1 Internal Memory Categories AAA 3 5 3 4 2 Memory Block Mapping eusch Eeer 3 6 3 4 3 Accesses To Unimplemented Internal Memory Locations 3 7 3 4 4 Control Register ee 3 7 3 4 5 Internal Memory Mapping Fields IMEMBASE LMEMBASE 3 8 3 4 6 Memory Mapping Conflicts cccecceeeeeeeeeeeeeeneeeeeeeeeeeeeeeeeeeeeeeeeaees 3 8 3 5 Internal Cross Bus ACCESSES EEN 3 9 3 6 Response to Freeze Assertion Ae 3 9 3 6 1 Effects of Freeze and Debug Mode on the Bus Monitor 3 10 3 6 2 Effects of Freeze on the Programmable Interrupt Timer PIT 3 10 3 6 3 Effects of Freeze on the Decrementer AE 3 10 MOTOROLA SIU iv REFERENCE MANUAL For More Information On This Product Go to www freescale com Freessale SSP EORR Me Continued Paragraph Title Page 3 6 4 Effects of Freeze on Register Lock Bits ccseeeseeeeeeeeeeeteeees 3 10 SECTION 4 EXTERNAL BUS INTERFACE 4 1 Features teren ee 4 1 4 2 External Re e 4 1 4 3 Basie BUS CY ClO eelere 4 3 4 3 1 Read Cycle FlOW EE 4 4 4 3 2 Write CY Oe EE 4 5 4 4 EE ee 4 6 4 5
200. servation Signaling 4 14 1 PowerPC Architecture Reservation Requirements The PowerPC architecture requires that the reservation protocol meets the following requirements e Each PowerPC processor has at most one reservation e The Iwarx instruction establishes a reservation e The lwarx instruction by the same processor clears the first reservation and es tablishes a new one e The stwex instruction by the same processor clears the reservation e A normal store by the same processor does not clear the reservation e A normal store by some other processor or other mechanism such as a DMA to an address with an existing reservation clears the reservation e If the storage reservation is lost it is guaranteed that stwex instruction will not modify storage e The granularity of the address compare is a multiple of the coherent block size which should be a multiple of 4 bytes 4 14 2 E bus Storage Reservation Implementation The E bus reservation protocol requires local external bus reservation logic if need ed to MOTOROLA EXTERNAL BUS INTERFACE SIU 4 20 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc e Snoop accesses to all local bus slaves e Hold one reservation for each local master capable of storage reservations e Set the reservation when that master issues a load with reservation e Clear the reservation when some other master issues a store to
201. served 16 21 MASK Six bit mask that specifies which block or blocks within region specified in SPECMASK reg ister are actually protected from speculative accesses 22 31 Reserved Because the mask register can contain any six bit value the mask can allow for blocks of up to 64 Kbytes and it can provide for smaller blocks of memory that alternately al low and prevent speculative loads Table 4 8 provides several examples In these ex amples the protected blocks are those that match the value in the SPECADDR register MOTOROLA EXTERNAL BUS INTERFACE SIU 4 14 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 4 8 Example Speculative Mask Values Mask Value Protected Region Binary 000000 1 Kbyte block 111111 64 Kbyte block 111110 Every second 1 Kbyte block within a 64 Kbyte block 111101 Every second 2 Kbyte block within a 64 Kbyte block 110011 Every fourth 4 Kbyte block within a 64 Kbyte block 100011 Every eighth 4 Kbyte block within a 64 Kbyte block 010000 Every sixteenth 1 Kbyte block within a 32 Kbyte block Protection from speculative loads can be disabled by setting the SPECADDR register to an internal or unimplemented address range 4 9 Accesses to 16 Bit Ports The EBI supports accesses to 16 bit ports on the external bus 16 bit port size is a chip select option the access must be initiated using one of the ch
202. served 22 23 LPM Low power mode select bits Refer to Table 6 6 and Table 6 7 00 Normal operating mode 01 Low power mode 1 single chip 10 Low power mode 2 doze 11 Low power mode 3 sleep Since all clocks are stopped in sleep mode exiting this mode requires the normal crystal start up time plus the PLL lock time Minimum length of the exit signal is two clocks in single chip mode three clocks in doze mode and until the PLL is stable in sleep mode 24 27 Reserved MOTOROLA CLOCK SUBMODULE SIU 6 16 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Table 6 9 SCCR Bit Settings Continued Bit s Name Description 28 31 RFD Reduced frequency divider The RFD field controls a prescaler at the output of the PLL The MF and RFD fields determine the CLKOUT frequency Refer to Table 6 4 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 1024 1100 1024 1101 1024 1110 1024 1111 2 1024 6 12 System Clock Lock and Status Register SCLSR The system clock lock and status register GCLSR contains lock and status bits for the PLL It is powered by VDDKAP1 The SCLSR is not affected by reset conditions that do not cause clock reset Clock reset caused by loss of oscillator loss of lock or external reset causes
203. so continues to count The power down wakeup pin PDWU can be programmed to signal an external power on reset circuit to enable power to the system whenever the MSB of the decrementer changes from a zero to a one Figure 6 1 is a block diagram of the SIU clock module CLOCK SUBMODULE MOTOROLA For More Information On This Product 6 1 Go to www freescale com Freescale Semiconductor Inc Si 2 zl E Lu gt x lt OSCCLK OSC ad RFD 0 3 b gt VCOOUT LPM3 Q 9 MF 0 3 A e ECROUT 2 S OY ECR LPM gt B1 TBS XTAL EXTAL SI_S_FREEZE _VDDSN__ MODCLK LPM2 TB DEC IM SYSTEM CLKOUT CLOCKS r Lt P SIU CLOCK BLOCK Figure 6 1 SIU Clock Module Block Diagram MOTOROLA CLOCK SUBMODULE SIU 6 2 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 6 1 Signal Descriptions Table 6 1 describes the signals used by the clock module Table 6 1 Clocks Module Signal Descriptions Mnemonic Name Direction Description CLKOUT System clock out Output System clock Used as the bus timing reference by external devices EXTAL XTAL Crystal oscillator Input Output Connections for external crystal to the internal oscil lator circuit An external oscillator should serve as in put to the EXTAL pin when used XFCN XFCP External filter Input The
204. sses from one internal bus to resources on the other bus take at least three clocks because of arbitration and cycle termination delays Access to l bus resources from the L bus is provided to allow access to control regis ters on the I bus It also allows internal instruction memory such as flash EEPROM if present on the chip to be used to store static data tables and values This cycle at least three clocks on the L bus offers performance as good as a two clock external cycle Instruction fetching from L bus memory is intended primarily as a mechanism to allow a customer test program to be downloaded to on chip RAM and executed This is not a high performance instruction fetching mechanism Accesses from the I bus to the L bus are at least three clocks and not burstable Cross bus accesses occur inside the SIU consuming SIU resources during the ac cess Internal SIU registers are not available during cross bus accesses Internal to external cycles are not pipelined with cross bus accesses nor are two consecutive cross bus accesses pipelined Clearing the L bus to l bus cross bus access LIX bit in the MEMMAP register dis ables data accesses to I bus memory This allows load store data stored in a flash memory on the I bus to be moved off chip for development purposes When this bit is cleared L bus to l bus transactions are run externally 3 6 Response to Freeze Assertion The RCPU asserts the freeze signal to the rest of the MC
205. state of certain mode se lect pins during reset determines which functions are assigned to pins with multiple functions These mode select pins determine other aspects of operating configuration as well Basic operating configuration is determined by the DSDI and DSCK pins as shown in Table 8 3 Table 8 3 Pin Configuration During Reset Pin During Reset Function Affected DSCK asserted 1 Debug mode enabled DSCK negated 0 Debug mode disabled DSDI asserted 1 DSDI negated 0 Data bus configuration mode Internal default mode The state of the DSDI pin is latched internally five clock cycles after RESETOUT is as serted The state of the DSCK pin is latched every clock cycle while RESETOUT is asserted The MCU is configured based on the values latched from these two pins The user is responsible for guaranteeing a valid level on these pins five clock cycles after RESETOUT is asserted If DSDI is asserted causing data bus configuration mode to be entered the user must also drive DATA 0 5 at a minimum For any reset source other than external reset the external data pins are latched five clock cycles after internal reset control logic asserts RESETOUT For external resets the data pins are latched five clock cycles after RESET is negated The default reset configuration word is driven onto the internal buses until the external word is latched If no external reset configuration word is latched the d
206. ster is holding the BB pin asserted even if the SIU has received a bus grant BG asserted from the bus arbiter Negated Indicates the MCU is not requesting the address bus The MCU may have no bus operation pending it may be parked or the MCU may be in the process of releasing the bus in response to ARETRY Assertion Occurs when the MCU is not parked and a bus transaction is needed Negation Occurs as soon as the SIU starts a bus cycle af ter receiving a qualified bus grant Asserted By bus arbiter indicates the bus is granted to the requesting device The signal can be kept asserted to allow the current master to park the bus Single master sys tems can tie this signal low permanently Negated lIndicates the requesting device is not granted bus mastership Assertion May occur at any time to indicate the MCU is free to use the address bus After the MCU assumes bus mastership it does not check for a qualified bus grant again until the cycle during which the address bus tenure is com pleted assuming it has another transaction to run The MCU does not accept a BG in the cycles between the as sertion of any TS and AACK Negation May occur at any time to indicate the MCU can not use the bus The MCU may still assume bus mastership on the clock cycle of the negation of BG because during the previous cycle BG indicated to the MCU that it was free to take mastership if qualified SIGNAL DESCRIPTIONS MOTORO
207. sts for details 3 7 Reserved 8 9 SUPV Supervisor access for PCU registers 00 Supervisor unrestricted registers respond to accesses in supervisor or user data space 01 Supervisor unrestricted registers respond to accesses in supervisor space only 10 Supervisor unrestricted registers respond to read accesses in either data space but write accesses can only be performed in supervisor data space 11 Undefined 10 31 SC Reserved 3 4 Internal Module Select Logic The SIU has a unified memory map for the L bus and the I bus The I bus has two masters the RCPU and the SIU One or more memory modules such as flash EEPROM or instruction RAM may be located on the I bus The L bus has at least two masters the RCPU and the SIU One or more slave modules may reside on the L bus These may include memory modules RAM flash EEPROM and on chip IMB2 pe ripherals which are connected via the L bus IMB2 interface LIMB In addition each module on either bus has one or more internal control registers which control the configuration and operation of the module On a memory module these registers are not mapped with the memory array but stay at a fixed address in the memory map Capability is provided to allow masters on one bus to access slaves on the opposite bus L bus masters must be able to access peripherals on the I bus to program their control registers or to program flash memory arrays This is becaus
208. t REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc 10 2 1 External Interrupt Requests The levels of the IRQ 0 2 interrupt request pins are assigned by programming the PIT QIL The remaining interrupt request pins have fixed values IRQ3 always generates a level 6 interrupt request IRQ4 generates a level 8 interrupt request IRQ5 generates a level 10 interrupt request IRQ6 always generates a level 12 interrupt request and IRQ7 always generates a level 14 interrupt request Note that all eight interrupt request pins IRQ 0 6 may not be available on a particular microcontroller Refer to the user s manual for the microcontroller of interest for de tails 10 2 2 Periodic Interrupt Timer Interrupts The periodic interrupt timer PIT is a 16 bit counter that generates an interrupt when ever it counts down to zero provided PIT interrupts are enabled The PITIRQL PIT interrupt request level field in the PITQIL register assigns the interrupt request level for PIT interrupts Refer to SECTION 7 SYSTEM PROTECTION for details of PIT op eration 10 2 3 On Chip Peripheral IMB2 Interrupt Requests The IMB2 has ten lines for interrupt support eight interrupt request lines IRQ 0 7 from the interrupting modules and two multiplexer control inputs ILBS 0 1 This scheme enables the peripheral control unit to transfer up to 32 levels of interrupt re quests to the interrupt controller When the f
209. t S 32 bit address bus Least significant two bits ADDR 30 31 are not pinned out they can be determined from the BE 0 3 pins ADDRO is the most significant bit Address bus is driven by the bus master to index the bus slave TS MoS Transfer start This address control signal is asserted for one clock cycle at the beginning of a bus access by the bus master WR M gt S Write read When this address attribute is asserted a write cycle is in progress When negated a read cycle is in progress For use of WR dur ing show cycles refer to RCPU Reference Manual RCPURM AD SIU EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL For More Information On This Product 4 1 Go to www freescale com Freescale Semiconductor Inc Table 4 1 EBI Signal Descriptions Continued Mnemonic Direction Description BE 0 3 MoS Byte enables These address attribute signals indicate which byte within a word is being accessed External memory chips can use this signals to determine which byte location is enabled Table 4 3 shows the en codings for these pins during accesses to 32 bit and 16 bit ports A device need only observe the byte enables corresponding to the data lanes on which it resides For example a device on data lane DATA 0 7 should use BEO and a device on DATA 0 15 should use BE 0 1 The device should not respond to the bus cycle unless its byte enables are active at the start of the bus cycle AT
210. t counter counts down to zero when loaded with a value from the PIT count PITC field in the PICSR After the timer reaches zero the PIT status PS bit is set and an interrupt is generated if the PIT interrupt enable PIE bit is set to one At the next input clock edge the value in the PITC is loaded into the counter and the process starts over When a new value is loaded into the PITC field the periodic timer is updated i e the new value is loaded into the modulus counter and the counter begins counting The software service routine should read the PS bit and then write it to zero to termi nate the interrupt request The interrupt request remains pending until the PS bit is cleared If the counter reaches zero again before the interrupt service routine clears the PS bit the interrupt request remains pending until PS is cleared Any write to the PITC stops the current countdown and the count resumes with the new value in PITC If the PITC is loaded with the value zero the PIT counts for the maximum period If the PIT enable PTE bit is not set the PIT is unable to count and retains the old count value Reads of the PIT register have no effect on the value in the PIT Figure 7 1 is a block diagram of the PIT I CLOCKS I PIT EXTAL I PTE PITC DIVIDE I FREEZE BY4 CLOCK PCFS I 16 BIT LOGIC gt LOGIC DISABLE DIVIDE I gt MODULUS Li P
211. t device can be internal or external mem ory If internal memory the boot device is not under chip select control If the boot de vice is located externally the chip select logic decodes the address of the access and enables the CE and OE of the boot device appropriately If the external boot device has a type 2 burst interface the LAST signal must be supplied by the EBI Note that at power on the boot region may be located at the upper most or lowermost 64 Mbytes of the address range The CSBOOT base address specified in the BA field of CSBTBAR can be reset to OxFFFO 0000 or 0x0000 0000 accordingly The chip se lect logic asserts the CSBOOT signal for the entire 64 Mbyte range if the access is to external boot memory While RESET is asserted the MCU drives the chip select pins high negated to avoid a possible data bus conflict CHIP SELECTS MOTOROLA For More Information On This Product 5 33 Go to www freescale com Freescale Semiconductor Inc MOTOROLA CHIP SELECTS SIU 5 34 For More information On This Product REFERENCE MANUAL Go to www freescale com SIU REFERENCE MANUAL Freescale Semiconductor Inc SECTION 6 CLOCK SUBMODULE The system clock provides timing signals for the IMB2 and for an external peripheral bus The MCU drives the system clock onto the external bus on the CLKOUT pin The main timing reference for the MPC500 family is a 4 MHz crystal The system operating frequency is generated through
212. t occurs when the external arbiter asserts BG bus grant and the previ ous bus master negates BB the bidirectional bus busy signal This means that no other master is currently running a cycle on the external bus If the SIU is ready to start an external cycle and it does not have a qualified bus grant then it asserts BR bus request until it receives the qualified bus grant Once the SIU receives a qualified bus grant it asserts BB and begins the address phase of the cycle A word aligned access to a 16 bit port results in two bus cycles To preserve word co herency the SIU does not release the bus between these two cycles The external arbiter can park the bus by keeping BG asserted Single master systems should tie this signal low permanently or configure the pin as a port pin which has the same effect Each potential master has its own BG input signal 4 5 2 Address Phase Once the SIU has a qualified bus grant it asserts BB and starts an address phase The SIU drives a new address at the start of the address phase and maintains it on the pins throughout the address phase The signals shown in Table 4 4 are driven at the start of the address phase Table 4 4 Signals Driven at Start of Address Phase Mnemonic Signal Name Type ADDR 0 29 Address bus Address bus TS Transfer start Control WR Write read Address attribute BE 0 3 Byte enables Address attribute AT 0 1 Address type Address attribute CT 0 3
213. t ports Table 2 2 Byte Enable Encodings Byte Enable Use During 32 Bit Port Access Use During 16 Bit Port Access BEO Byte Enable for DATA 0 7 Byte Enable for DATA 0 7 BET Byte Enable for DATA 8 15 Byte Enable for DATA 8 15 BE2 Byte Enable for DATA 16 23 ADDR30 BE3 Byte Enable for DATA 24 31 0 Operand size is word 1 Operand size is byte or half word Timing Comments 2 2 2 5 Transfer Start TS Output only Module ER State Meaning Timing Comments Assertion Negation The BE 0 3 signals are address at tributes they are updated at the start of the address phase and maintained until the start of the next address phase High impedance Coincides with negation of BB provided no qualified bus grant exists Asserted lIndicates the start of a bus cycle Assertion Coincides with the assertion of BB Negation Occurs one clock cycle after TS is asserted High impedance Coincides with negation of BB provided no qualified bus grant exists 2 2 2 6 Address Acknowledge AACK Input only Module ER State Meaning MOTOROLA 2 6 For More Information On This Product Asserted lIndicates that the address phase of a transac tion is complete If the external access is to a chip select region for which the chip select is programmed to return AACK and TA then the external bus interface uses the logical OR of the external AACK pin and the AACK signal returned by the chip select If the
214. t writes to the BMCR have no effect and re sult in a data error on the internal bus Writing a zero to BMLK after it has been set has no effect A write to the BMCR before the lock bit is set can configure protected bits and set the BMLK in the same access The BMLK bit is cleared by reset It can also be cleared by software while the internal FREEZE signal is asserted Software can write BMLK to zero any number of times be fore writing it to one 7 4 3 Bus Monitor Enable The bus monitor enable BME bit in the BMCR enables or disables the operation of the bus monitor during internal to external bus cycles Note that the bus monitor is al ways enabled while freeze is asserted and debug mode is enabled or when debug mode is enabled and the debug non maskable breakpoint is asserted even if BME is cleared 7 4 4 Bus Monitor Control Register A diagram of the BMCR and a description of its bits are provided below BMCR Bus Monitor Control Register 0x8007 FC48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED BMLK BME BMT RESERVED RESET 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 7 BMCR Bit Settings Bit s Name Description 0 3 Reserved 4 BMLK Bus monitor lock 0 Enable changes to BMLK BME BMT 1 Ignore writes to BMLK BME BMT 5 BME Bus monitor enable 0 Disable bus monitor
215. tails on these pins 2 2 7 1 Reset RESET Input only SIU SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product 2 15 Go to www freescale com Freescale Semiconductor Inc Module Reset State Meaning Asserted lIndicates that devices on the bus must reset Negated Indicates normal operation Timing Comments For timing information refer to SECTION 8 RESET OPER ATION 2 2 7 2 Reset Output RESETOUT Output only Module Reset State Meaning Asserted During reset instructs all devices monitoring this signal to reset all parts within themselves that can be reset by software Assertion indicates that the MCU is in re set Negated Indicates normal operation Timing Comments For timing information refer to SECTION 8 RESET OPER ATION 2 2 8 SIU General Purpose Input Output Signals Many of the pins associated with the SIU can be used for more than one function The primary function of these pins is to provide an external bus interface When not used for their primary function many of these pins can be used for digital I O Refer to SEC TION 9 GENERAL PURPOSE I O for more information on these signals 2 2 8 1 Ports A and B PA 0 7 PB 0 7 Output only Module Ports State Meaning Asserted Negated Indicates the logic level of the data be ing transmitted Port A and port B share a data register PORTA PORTB and pin assignment register PAPAR PBPAR Timing Comment
216. te the BI signal internally when appropriate 5 14 Chip Select Operation Flow Chart Figure 5 4 illustrates the operation of the chip select logic for external accesses IDLE IF NEW CYCLE NO MORE DECODES ADDRESS IF MATCH amp DOES NOT VIOLATE PROTECTION ASSERTS CE ASSERTS AACK IF ENABLED RETURNS BI PS 0 1 LAST DATA amp OVERLAP ACCESS y WAITS UNTIL TURN IN THE PIPE WAITS UNTIL DELAY TIME IF WRITE IF READ y SE ASSERTS OE ASSERTS WE J y ASSERTS T IF ENABLED IF BURST MPC500 CS FLOW Figure 5 4 Chip Select Operation Flow Chart 5 15 Pipe Tracking The chip select module supports pipelined accesses to external devices Up to two cy cles can be pending in the chip select module The chip select unit supports pipelined reads for certain types of interfaces Pipelined writes are not supported Table 5 13 summarizes the chip select pipelining of read and write accesses SIU CHIP SELECTS MOTOROLA REFERENCE MANUAL For More Information On This Product 5 21 Go to www freescale com Freescale Semiconductor Inc Table 5 13 Pipelined Reads and Writes First Access Second Access Pipelining Supported Read Read Yes Write Read Yes Read Write No Write Write No The following subsections explain which types of interfaces permit pipelining of read accesses Pipelining of consecutive accesses to the same region is discussed first fol lowed by pipelining of
217. ted out of the development port shift register Timing Comments _ Transitions are relative to CLKOUT in self clocked mode and relative to DSCK in clocked mode Refer to the RCPU Reference Manual RCPURM AD for more information 2 2 4 2 Development Port Serial Data In DSDI Input only Module Development support State Meaning Asserted Negated Indicates the logic level of data being shifted into the development port shift register Reset Operation During reset this pin functions as a reset configuration mode pin If the pin is pulled high while the MCU asserts RESETOUT the data bus pins are used to configure the system when the reset state is exited If the pin is low at the positive edge of RESETOUT then the system is configured by the internal default mode Refer to 8 3 Configuration During Reset for more information on reset operation Timing Comments Transitions are relative to CLKOUT in self clocked mode and relative to DSCK in clocked mode Refer to the RCPU Reference Manual RCPURM AD for more information 2 2 4 3 Development Port Serial Clock Input DSCK Input only Module Development support State Meaning Asserted Negated Provides a clock signal for shifting data into or out of development serial port Reset Operation During reset this pin functions as a debug mode enable pin If the pin is pulled high while the MCU asserts RE SETOUT debug mode is enabled when the reset state is exited For normal operation
218. terface 3 4 2 Memory Block Mapping The l bus memory and the L bus memory can each be mapped to one of four loca tions These locations are at the top and bottom of the 4 Gbyte address range They include the two alternatives for the PowerPC vector map 0x0000 0100 and OxFFFF 0100 The IMEMBASE and LMEMBASE fields in the memory mapping register MEMMAP determine the locations of the Lbus and L bus memory respectively Figure 3 2 shows the mapping of the memory blocks within the memory map MOTOROLA MODULE CONFIGURATION SIU 3 6 For More Information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc VECTOR TABLE LOCATION P BIT 0 POSSIBLE 0x0000 0000 LMEM OR L MEM LOCATION 2 BYTES 16 KBYTE MINIMUM EXTERNAL POSSIBLE ONE OF FOUR POSSIBLE LOCATIONS MEM OR L MEM SELECTED FOR SRAM LOCATION 2 BYTES 16 KBYTE MINIMUM Ox000F FFFC EXTERNAL 0x8000 0000 EXTERNAL RESERVED 0x8007 E000 PERIPHERAL CONTROL UNIT PCU 0x8007 EFFC 0x8007 F000 0x8007 FFFC CONTROL REGISTERS EXTERNAL VECTOR TABLE LOCAT CTO PIT E POSSIBLE OXFFFO 0000 LMEM OR L MEM LOCATION 2 BYTES 16 KBYTE MINIMUM EXTERNAL POSSIBLE LMEM OR L MEM LOCATION 2 BYTES 16 KBYTE MINIMUM OxFFFF FFFC MPC500 ADDRESS MAP Figure 3 2 Placement of Internal Memory In Memory Map 3 4 3 Accesses To Unimplemented Internal Memory Locations H an access is made to a lo
219. the slave in order to complete the burst transfer Data Phase Signals DATA 0 31 Mes 32 bit data bus DATAO is most significant bit DATA31 is the least sig nificant bit During small port accesses data resides on DATA 0 15 BDIP M gt S Burst data in progress This signal is asserted at the beginning of a burst data phase and is negated during the last beat of a burst The master uses this signal to give the slave advance warning of the remaining data in the burst This can also be used for an early termination of a burst cy cle When the LST bit in the SIUMCR is asserted the BDIP pin uses LAST timing If the LST big is negated the BDIP pin uses BDIP timing Refer to 5 16 6 Synchronous Burst Interface for more information TA SM Transfer acknowledge When asserted indicates the slave has received the data during a write cycle or returned the data during a read cycle During burst cycles the slave asserts this signal with every data beat re turned or accepted T S M Transfer error acknowledge Assertion of TEA indicates an error condi tion has occurred during the bus cycle and the bus cycle is terminated This signal overrides any other cycle termination signals e g TA or ARETRY DS M gt S Data strobe Asserted by EBI at the end of a chip select controlled bus cycle Asserted after the chip select unit asserts the internal TA or TEA signal or the bus monitor timer asserts the internal TEA signal
220. tion of the global freeze signal can stop the clock to the time base and dec rementer if the SIUFRZ bit in the SIUMCR 0x8007 FCOO is set The actual freezing of the clock source occurs at the falling edge of the clock 6 9 3 Decrementer Clock Enable DCE Bit The decrementer clock enable DCE bit in the SCCR enables or disables the clock source to the decrementer The default state is to have the clock enabled The actual clock source is determined by the TBS bit The DCE bit does not affect the decrement er until after the next increment time as determined by the clock source 6 10 Clock Resets The following reset conditions cause the internal clock reset signal to be asserted ex ternal reset loss of oscillator when LOORE is set and loss of lock when LOLRE is set Clock reset causes the clock circuitry including the PLL oscillator SCCR and SCLSR to be reset Note that all reset sources cause normal reset processing to occur as described in SECTION 8 RESET OPERATION However only the reset sources mentioned above external reset loss of oscillator and loss of lock result in clock reset 6 10 1 Loss of PLL Lock The system PLL lock status SPLS in the SCLSR indicates the current lock status of the PLL When the SPLS bit is clear the PLL is not locked When the SPLS bit is set the PLL is locked The SPLS bit can be read anytime It can be written only during spe cial test mode In PLL bypass mode and special test mo
221. ts a chip select sig nal that is configured as an output enable of a memory or I O device the device can drive its data onto the E bus 5 4 Chip Select Registers and Address Map Chip select registers are 32 bits wide Reads of unimplemented bits in these registers return zero and writes have no effect One base address register and one option register are associated with each chip se lect pin that can function as a chip enable The CSBOOT pin has a dedicated sub block for multi level protection It has two base address registers and two option reg isters One option register is associated with each pin that can function as a write en able or output enable but not as a chip enable Table 5 2 is an address map of the chip select module As the entries in the Access column indicate all chip select registers are accessible at the supervisor privilege lev el only When set the LOK bit in the SIU module configuration register SIUMCR locks all chip select registers to prevent software from changing the chip select configuration inadvertently Before changing the chip select configuration the user needs to ensure that this bit is cleared MOTOROLA CHIP SELECTS SIU For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc Note that if the processor is modifying the chip select registers of a region and it needs the instructions from that region a region that it is reconfiguring
222. urns the value atthe pin only if the pin is configured as a discrete input Otherwise the value read is the value stored in the internal data latch Port J K and L data registers can be read or written at any time DDRI DDRJ DDRK DDRL Port J K L Data Direction Registers 0x8007 FC98 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DDIO DDH DDI2 DDIS DDI4 DDI5 DDI6 DDI7 DDJO DDJ1 DDJ2 DDJ3 DDJ4 DDJ5 DDJ6 DDJ7 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DDKO DDK1 DDK2 DDK3 DDK4 DDK5 DDK6 DDK7 DDLO DDL1 DDL2 DDL3 DDL4 DDL5 DDL6 DDL7 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The bits in DDRI DDRJ DDRK and DDRL control the direction of the associated pin drivers when the pins are configured as I O pins Setting a bit in these registers con figures the corresponding pin as an output clearing the bit configures the pin as an input MOTOROLA GENERAL PURPOSE I O SIU 9 4 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc PIPAR PJPAR PKPAR PLPAR Port I J K L Pin Assignment Registers 0x8007 FC9C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIPAO PIPA1 PIPA2 PIPA3 PIPA4 PIPA5 PIPA6 PIPA7 PJPAO PJPA1 PJ
223. us access 1010 1111 Reserved 5 13 2 Turn Off Times for Different Interface Types The turn off time for asynchronous devices is equal to the time for OE to negate plus the time for device s outputs to go to a high impedance state For devices with an ITYPE of 0 turn off time is less than or equal to one clock cycle For devices with an ITYPE of 1 turn off time is two clock cycles The turn off time of asynchronous devices must be taken into account in systems that pipeline accesses to devices controlled by chip selects with accesses to devices that are not under chip select control Otherwise external bus contention can result The turn off time for synchronous devices is equal to the time from the rising edge of the device s clock to the time the device s outputs are in a high impedance state This turn off time must be less than or equal to one clock period 5 13 3 Interface Type and BI Generation During a burst access to a region under chip select control that does not support burst accesses the chip select unit asserts the BI signal internally Only regions with an ITYPE of 5 7 and 8 support burst accesses MOTOROLA CHIP SELECTS SIU 5 20 For More information On This Product REFERENCE MANUAL Go to www freescale com Freescale Semiconductor Inc CAUTION It is recommended that the BI pin not be asserted during accesses to memory regions controlled by chip selects instead the chip select unit will genera
224. ut port as output port driven by CPU BI 3 state Yes Input unless configured as output port Float TA 3 state Yes Input unless configured Float listen only only Input port output 3 stat as an output port driven if configured as ed output port TEA 3 state Yes Input unless configured Float listen only only Input port output 3 stat as an output port driven if configured as ed output port ARETRY 3 state Yes Input unless configured Input driven if config Input port output 3 stat as output port ured as output port ed Arbitration BR 3 state No Output unless configured as input port Not affect Float ed by BG BG 3 state Weak pull Input unless configured Output only if config Float down as output port ured as output port BB 3 state Yes Output unless config If relinquishing drive Float ured as input port high then float unless configured as output port Miscellaneous CR DS 3 state Yes Not affected by BG Input unless configured for Float secondary function RESETOUT Output No Not affected by BG RESET Input No Not affected by BG CLKOUT Output No Not affected by BG Not affected NOTES 1 Weak pull ups can maintain an internal logic level one but may not maintain a logic level one on external pins 2 2 Signal Descriptions This section describes the SIU and PCU signals Since MCU pins often have more than one function more than one description may apply to a pin 2 2 1 Bus Arbitration and Reservati
225. ww freescale com Freescale Semiconductor Inc 5 11 Port Size The PS field indicates the port size of the region The chip select logic always returns PS 0 1 for regions under its control Port size encoding is shown in Table 5 8 The 0b00 and 0b11 encodings are reserved if one of these encodings is used the port size defaults to 32 bits Table 5 8 Port Size PS Field Port Size 0b00 Reserved 0b01 16 bits 0b10 32 bits 0b11 Reserved 5 12 Chip Select Pin Control The PCON BYTE and REGION fields of each chip select option register control how the associated pin is used The PCON field determines pin function CE OE WE or alternate function The BYTE field determines which byte enable a WE pin corre sponds to The REGION field assigns a WE or OE pin to one of six chip select regions 5 12 1 Pin Configuration The PCON pin configuration field in the chip select option register configures the as sociated pin to be a CE WE OE or non chip select function pin The encodings are shown in Table 5 9 Table 5 9 Pin Configuration Encodings PCON Pin Assignment 0b00 Chip enable CE 0b01 Write enable WE 0b10 Output enable OE 0b11 Address pin or discrete output Note that only the CSBOOT and CS 1 5 pins can be CE pins If the pin is a CE pin the REGION field does not affect it since each CE pin has its own base address reg ister and decoding logic The CSO and CS 6 11

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