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XMC 7K User Manual

1. MODELS FRONT I O P16 HS P16 SELECT I O P4 SELECT I O SERIAL XMC 7A200 AXM modules 8 lanes 2 global clocks diff 2 global clocks diff pairs pairs 17 LVDS signal 30 LVDS signal pairs pairs XMC 7A200CC N A 8 lanes 2 global clocks diff 2 global clocks diff pairs pairs 17 LVDS signal 30 LVDS signal pairs pairs XMC 7KxxxAX AXM modules 8 lanes 1 global clock diff pair 2 global clocks diff pairs 15 LVDS signal pairs 30 LVDS signal pairs XMC 7KxxxCC N A 8 lanes 2 global clocks diff 2 global clocks diff pairs pairs 17 LVDS signal 30 LVDS signal pairs pairs XMC 7 KxxxF 2 SFP USB JTAG 4 lanes 2 global clocks diff 2 global clocks diff pairs 2 global clock diff pairs pairs 17 LVDS signal 30 LVDS signal pairs 11 LVDS signal pairs pairs Acromag Inc Tel 248 295 0310 www acromag com XMC 7 Series AXM CC F Ordering Information USER S MANUAL The following table lists the orderable models and their corresponding operating temperature range These maximum operating temperatures are determined using 75 96 of the DSP slices and block RAMs at 200 MHz operating frequency The amount of FGPA resources and clock frequency used by your application if less than our test conditions will possibly allow a higher operating temperature Models XMC 7A200CC XMC 7K325CC and XMC 7K410CC are conduction cooled models without front I O Table 1 The XMC 7 series boards are available in these c
2. 148g Weight XMC 7K410F 148g Power will vary dependent on the application Power values are given for the Acromag example design with the AXM EDK board installed on the AX models XMC 7A200 CC Models 3 2 Volt 2 1A 3 3 Aux Volt 17 uA 12 5 Volts VPWR 150 mA 12V 12 Volts eerte 0 1 mA e AE 0 mA XMC 7K325AX CC Models 3 3 VOIES tie eere pne 2 32A 3 3 Aux Volts Ee 17 uA 12 5 Volts VPWR 220 mA 12V 12 Volts oo ee 0 1 mA 212 Volts oett 0 mA XMC 7K410AX CC Models 3 3 VOltS ici 2 32A 3 3 Aux Volt 17 uA 12 5 Volts VPWR 220 mA 12V 12 Volts ee 0 1 mA STD c 0 mA XMC 7K325F 3 3 VOItS eegent 3A 3 3 Aux Volt 17 uA 12 5 Volts VPWR 250 mA 12V i ATI 0 1 mA A A 0 mA 102 www acromag com XMC 7 Series AXM CC F USER S MANUAL XMC 7K410F 3 3 Volts died 3 2A 3 3 Aux Volt 17 uA 12 5 Volts VPWR 250 mA 12V AKTE 0 1 mA e EE 0 mA PCIe BUS COMPLIANCE Spechfication This device meets or exceeds all written PCI Express specifications per revision 2 1 dated March 4 2009 Note PCle Gen 2 signal rates exceed the rated bandwidth of the XMC connectors ENVIRONMENTAL Operating Temperature XMC 7A200 40 C to 55 C XMC 7A200CC 40 C to 475 C cold plate XMC 7K325AX 40 C to 45 C XMC 7K410AX 40 C to 40 C XMC 7K325C
3. BARO 0x3002xx Address X Status Register 0x00300200 Temperature 0x00300204 Vccint 0x00300208 Vccaux 0x00300280 Maximum Temperature 0x00300284 Maximum Vccint 0x00300288 Maximum Vccaux 0x00300290 Minimum Temperature 0x00300294 Minimum Vccint 0x00300298 Minimum Vccaux P1 Front I O XMC 7K325F and XMC 7K410F models only P1 Front Input Data Register Acromag Inc Tel 248 295 0310 The front I O in the provided example design has been configured as 13 LVCMOS inputs and 13 LVCMOS outputs It can also be configured as 11 differential channels with 2 global clock signal pairs It is an instance of Xilinx s LogiCORE IP AXI GPIO The Xilinx IP core has been configured as follows GPIO channel 1 width 13 all inputs GPIO channel 2 width 13 all outputs interrupts enabled The front input data register is used to access the individual input signals The front input includes 13 LVCMOS single ended signals Table 35 shows the bit position assignments for each of the signals Input signal levels are determined by reading this register Output signals are set by writing to the front output data register at base address plus 0x310008 46 www acromag com XMC 7 Series AXM CC F USER S MANUAL This front input data register is a read only register Channel read operations can use 32 bit 16 bit or 8 bit data transfers Table 35 P1 Front Input Data Register BARO 0x310000
4. o No Delay Interrupt Delay Interrupt Active Interrupt on Error When set to 1 this bit indicates an interrupt event has been generated due to an error condition If the Interrupt on Error bit 14 of the CDMA Control register 14 1 an interrupt is generated from the AXI CDMA A CPU write of 1 clears this bit to O 0 No Error Interrupt Error Interrupt Active 15 Reserved 12 Acromag Inc Tel 248 295 0310 34 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Bit s FUNCTION Interrupt Threshold Status This field reflects the current interrupt threshold value in the Scatter Gather Engine Interrupt Delay Time Status This field reflects the current interrupt delay timer value in the Scatter Gather Engine 23 16 31 24 CDMA Current Descriptor Pointer Register Table 21 CDMA Current Descriptor Pointer Register Read Write BARO 0x000A0008 Bit s FUNCTION Writing to these bits has no effect and they are always read as zeros Current Descriptor Pointer This register field is written by the software application in Scatter Gather Mode to set the starting address of the first transfer descriptor to execute for a Scatter Gather operation The address written corresponds to a 32 bit system address with the least significant 6 bits truncated This register field must contain a valid descriptor address prior to the software application writing the CDMA Tail Descripto
5. Receiver Inverted Data Output 13 RD Receiver Non Inverted Data Output 14 VeeR Module Receiver Ground 15 VccR Module Receiver 3 3 V Supply 16 McT Module Transmitter 3 3 V Supply 17 MeeT Module Transmitter Ground 18 ransmitter Non Inverted Data Input 19 TD ransmitter Inverted Data Input 20 VeeT Module Transmitter Ground Ethernet MAC IDs XMC 7K325F and XMC 7K410F models Acromag Inc Tel 248 295 0310 Two Ethernet MAC ID address numbers have been reserved for each XMC 7K325F and XMC 7K410F units The numbers are printed on the labels attached to the board The example design provided by Acromag includes MicroBlaze software running the LWIP TCP IP network protocol suite The 19 WWW acromag com XMC 7 Series AXM CC F Non Isolation Considerations USER S MANUAL MAC ID for each port is set by the software If your application uses the example design as a base for your project replace the MAC IDs in the C source with the IDs printed on the label The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections 4 PROGRAMMING INFORMATION GETTING STARTED Acromag Inc Tel 248 295 0310 This Section provides the specific information necess
6. wn PCIe axi pcie 0 Acromag Inc Tel 248 295 0310 Slave Interface S AXI CTL S AXI S AXI S AXI MEM S AXI S AXI S AXI S AXI S AXI S AXI LITE S AXI s axi lite s axi S AXI CTL Base Name FIT 1 ju CTLO 66 Offset Address 0x000F_0000 0x0100_0000 0x8000_0000 0x6000_0000 0x8000_0000 0x8000_0000 0x0033_0000 0x0032_0000 0x0034_0000 0x000A 0000 0x0031 0000 0x0030 0000 0x0010 0000 OxOO0F 0000 Figure 14 XMC 7KxxxF Address Map Range 5 358 3233233235 Be 4 4 d EE 4 EN A NA 4 A 4 WWW acromag com High Address OxO00F FFFF OxO1FF FFFF OxBFFF FFFF Ox63FF FFFF OxBFFF FFFF OxBFFF FFFF 0x0033 FFFF 0x0032 FFFF 0x0034 FFFF 0x000A FFFF 0x0031 FFFF 0x0030 FFFF 0x0010 FFFF Ox000F_FFFF XMC 7 Series AXM CC F S_AXI_ENETI D JI AXI Ethemet Subsystem S_AXI_ENET1_DMA gt s axi Ke ack D gt DRETT signal detect S_AXI_ENETO_DMA 27 UL Fe axi resetn 0 0 5 memes ori eset out n PA S2mm prmey reset out n ERE EE 2mm sts reset out n u gt D Wm m S AXI ENETOL 5 mot cl ENETO signal detect gt ref_ck _ gt AXI Ethemet Subsystem Figure 15 Block Diagram Ethernet Subsystem Acromag Inc Tel 248 295 0310 67 USER S MANUAL ENET1_sfp ENET1_mac_ir 0 0 ENET1_interrupt 0 0 ENET1_mm2s_introut 0 0 ENET1_s2mm_introut 0 0 M_AXI_ENET1_MM2S M_AXI_ENET1_SG M_AXI_ENET1_S2MM ENETO_sfp ENETO_mac_irq 0 0
7. 4 LVTTL1 O I I x4 x4 x4 Artix 34 30 1 0 x4 x4 x8 Kintex amp hardware hardware PCle 2 1 Global Clock Pairs example example ITAG CC AXM design design Aurora Aurora IPMI 30 LVDS pairs amp 2 Global Clock Pairs Acromag Inc Tel 248 295 0310 Figure 1 Block Diagram AXM CC Models WWW acromag com XMC 7 Series AXM CC F USER S MANUAL JTAG IPMI 11 LVDS Pairs 8 2 Global Clock Pairs x8 PCle 341 0 a 2 Global Clock Pairs x2 hardware example design Aurora x2 hardware example design Aurora 30 LVDS pairs amp 2 Global Clock Pairs Acromag Inc Tel 248 295 0310 Figure 2 Block Diagram F Models 10 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL KEY FEATURES The block diagram shown in Figure 1 illustrates the key features listed below Features common to all models are listed first followed by model specific features Common Features e Reconfigurable Xilinx FPGA The FPGA loads its configuration data from flash memory each time power is applied to the module The host processor can be used to change the flash configuration memory via the PCle bus This provides a means for creating custom user defined designs The FPGA will configure from the updated flash memory on the next power cycle e DDR3 SDRAM 128 Meg x 64 bit DDR
8. DMA Decode Error This bit indicates that an AXI decode error has been received by the AXI DataMover This error occurs if the DataMover issues an address that does not have a mapping assignment to a slave device This error condition causes the AXI CDMA to halt gracefully The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition EMI No CDMA Decode Errors CDMA Decode Error detected CDMA Engine halts 7 Reserved Scatter Gather Internal Error This bit indicates that an internal error has been encountered by the Scatter Gather Engine This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition O No Scatter Gather Internal Errors Scatter Gather Internal Error CDMA Engine halts Acromag Inc Tel 248 295 0310 33 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Bit s FUNCTION Scatter Gather Slave Error This bit indicates that an AXI slave error response has been received by the Scatter Gather Engine during an AXI transfer transfer descriptor read or write This error condition causes the AXI CDMA to gracefully 9 halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condit
9. 14 pies 14 be SIO9 P 15 15 P16 SI 15 be SIO7 P 16 16 _ P16 SI 16 be SIO5 P 17 17 pieSs 17 be SIO3 P 18 18 P16 SI 18 P16 SIO1 N e e B B foo JN jo jur 5 jwin jejo m N Note that any registers bits not mentioned will remain at the default value logic low The P16 output data register is used to access the individual output channels This includes 9 differential output channels Each channel is controlled by a corresponding data bit as shown in Table 43 Channel output signal levels are controlled by writing this register Channel input signals are accessed by reading the P16 input data register at base address plus 0x320000 This P16 output data register is a write only register Channel write operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as output channels 51 www acromag com XMC 7 Series AXM CC F USER S MANUAL Table 43 BARO P16 Output Data Register Write Only BARO 0x320008 Register Bit Channel VHDL Name Schematic Name 0 P16 SO 0 P16 SIO18 GCLK N 1 1 P16 so 1 P16_SIO16_P 2 A P16 so 2 P16_SIO14 P 3 3 P16 So 3 P16_SIO12 P 4 A P16 sofa P16_SIO10 P 5 5 P16 SO 5 P16 SIO8 P 6 6 P16 so 6 P16 SIO6_P 7 2 P16 so 7 P16 SIO4 P 8 ga P16 so 8 be SIO2 P 9 9 __ P16 so 9 be SIOO GCLK P 10 10 jP16 so 10 P16 SIO17 N 11 11 P16 SO 11 P16 SIO15 N
10. 288 signal M AXI AXM rvalid STD LOGIC 289 signal M AXI AXM rready STD LOGIC 290 signal S AXI ACLK STD LOGIC 291 signal S AXI ARESEIN STD LOGIC VECTOR 0 to 0 292 signal AXM INTERRUPT STD LOGIC 293 294 295 296 297 298 ee 299 attribute BOX TYPE STRING 300 attribute BOX TYPE of system component is user black box 301 302 begin 303 FPGA MBISTn 1 304 FPGA MRSTOn 1 305 FPGA ROOTOn lt 1 306 TELIT Acromag Inc Tel 248 295 0310 82 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Delete lines 479 and 480 C JXMC 7K325AX MOD XMC 7K325AX XMC 7K325AX srcs sources i imports system top vhd 469 as in tri i 31 downto 24 gt 000000000000 KA 470 as in tri i 23 downto 16 gt Lane Up 0 to 7 A 171 as_in_tri_i 15 downto 3 gt 0000000000000 a 472 as in tri i 2 gt Channel Up E 473 as in tri i 1 gt 0 474 as in tri i 0 gt GT RESET IN Ha 475 as_out_tri_o 0 gt GT_RESET_IN 476 il 477 pl6 in tri i gt P16 SI s 478 p16 out tri o gt P16 SO x 481 Vp Vn v n gt Vp Vn v n di 482 Vp Vn v p Vp Vn v p lues UD 484 Insert the highlighted lines a C XMC 7K325AX MOD XMC 7K325AX XMC 7K325AX srcs sources i imports system top vhd 469 as in tri i 31 downto 24 gt 000000000000 LA 470 as_in_tri_i 23 downto 16 gt Lane_Up 0 to 7 EI 471 as in tri i 15 downto 3 gt 0000000000000 de 472 a
11. 32 megabytes on XMC 7A models The remaining 48 megabytes are available for MicroBlaze program and data storage 32 megabytes on XMC 7A models The Xilinx LogiCORE IP AXI EMC v3 0 provides the interface between the internal AXI bus and the Micron FLASH device The JTAG port can be used to program the FPGA and access the device for hardware and software debug The JTAG signals are routed to both the XMC P15 connector and either the AXM P1 connector on AXM models or the VHDCI P1 on the Front I O models The JTAG port also allows a host computer to download a bitstream to the FPGA or Flash using the Xilinx Vivado software tool In addition the JTAG port allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA In all 7 series FPGA devices the FPGA bitstream which contains sensitive customer IP can be protected with 256 bit AES encryption and HMAC SHA 256 authentication to prevent unauthorized copying of the design The FPGA performs decryption on the fly during configuration using an internally stored 256 bit key This key can reside in volatile RAM or in nonvolatile eFUSE bits The volatile RAM is powered from the 3 3V AUX pin of the XMC P15 connector The power for the XMC 7 series modules is taken from the XMC P15 connector VPWR 5 12 12 Volt and the 3 3 Volt power pins Table 44 and Figure 4 show the source and capacity of each of the power regulators on the board 54 WWW acromag co
12. ENETO_interrupt 0 0 www acromag com XMC 7 Series AXM CC F ARESETN 0 0 2 EnetO mac ira 0 0 2 Enet0_interrupt 0 0 D USER S MANUAL microblaze 0 axi periph mn Ais ARESETN 0 0 za M02 ai M03 AXL4 C MO4 AXI MOS ai AXI Interconnect gt ENETO 9po 3 0 gt M01 AXI D M02 AX D M AXI MB FLASH microblaze 0 xiconcat microblaze 0 local memory microblaze 0 axi intc a microblaze 0 DLMB Enet0_mm2s_introut gt interrupt l INTERRUPT eps Enet0_s2mm_introut CC 0EBUG ej processor_dk M_AXI_DP m Ea MicreBlaze x AXI Interrupt Controller LS M AXLIC MicroBlaze LMB Rst 0 0 E were asn y risn D sat AXI UART16550 sin m m 0 MBDEBUG 04 Sx Dp MBDEBUG_1 MBDEBUG_1 Interrupt gt Interrupt Debug SYS Ret D Debug SYS Rst MicroBlaze Debug Module MDM Figure 16 Block Diagram Microblaze 0 microblaze 1 axi periph z 4 500 wa a ARESETN 0 0 D RESETN O 0 soo ac k 00_ARESETN O 0 IMO0_ACLK MOO_ARESETN 0 0 oz acik EI M02 ARESETN 0 4 wo3 ACK M03 ARESETN 0 0 M04 ACLK M04 ARESETN 0 0 MOS ACLK MOS ARESETN 0 0 6 acik pe ARESETN 0 0 M01 ACLK or ARESETN 0 0 aba M02 AXI S00 ARESETN 0 0 gt Eneti mac irq 0 0 D Eneti mm2s introut Enti s2
13. z z z z z z z z z z z z z z z z z z z z z GCLK_N Note that any registers bits not mentioned will remain at the default value logic low The P16 input data register is used to access the individual LVDS input channels This includes 10 differential channels which include 2 global clock signal pairs Each channel is controlled by a corresponding data bit as shown in Table 42 50 www acromag com XMC 7 Series AXM CC F P16 Output Data Register Acromag Inc Tel 248 295 0310 USER S MANUAL Channel input signal levels are determined by reading this register Channel output signals are set by writing to the P16 output data register at base address plus 0x320008 This P16 input data register is a read only register Channel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels Table 42 BARO P16 Input Data Register Read Only BARO 0x320000 Register Bit Channel VHDL Name Schematic Name D P16 Si 0 J P16 SIO16 N 1 P16 SI 1 JP16 SIO14 N 2 P16 Si 2 bie SIO12 N 3 P16 Si 3 P16 SIO10 N 4 P16 SI 4 be SIO8_N 5 P16 SI 5 be SIO6_N 6 P16 SI 6 be SIO4 N 7 P16 SI 7 JjP16 SIO2 N 8 jpi6Ss 8 P16 SIOO GCLK N 9 P16 si 9 be SIO18 GCLK P do P16 si 10 be SIO17 P 11 pi6eSs 11 jP16 SIO15 P 12 p16Ss 12 16 SIO13 P 13 13 P16 si 13 be SIO11 P 14
14. 12 12 P16 SO 12 P16 SIO13 N 13 13 P16 SO 13 P16 SIO11 N 14 14 P16 SO 14 P16 SIO9 N 15 15 P16 SO 15 P16 SIO7 N 16 16 P16 SO 16 bie SIO5_N 17 17 P16 SO 17 P16 SIO3 N 18 18 P16 SO 18 P16 SIO1 P Note that any registers bits not mentioned will remain at the default value logic low 5 THEORY OF OPERATION PCI INTERFACE LOGIC Acromag Inc Tel 248 295 0310 This section contains information regarding the design of the board A description of the basic functionality of the circuitry used on the board is also provided Refer to the XMC 7K A block diagrams Figure 1 and Figure 2 as you review this material The PCle bus interface logic implemented in the Acromag example design provides an 8 lane PCle Gen 1 interface to the carrier CPU board on XMC 7K models 4 lanes on XMC 7A models This interface provides access to the example design board functions The PCle bus endpoint interface logic is contained within the FPGA This logic includes support for PCle commands including configuration read write and memory read write In addition the PCle interface supports requester and or completion accesses Maximum payload size of up to 1024 bytes is supported The logic also implements interrupt requests via message signaled interrupts Messages are used to assert and de assert virtual interrupt lines on the link to emulate the Legacy PCI interrupt INTAR signal 52 www acromag
15. 29 CDMA Control Register e or ete Ire e suis 30 CDMA Status Registert 5 5 Ri RR din EEN EEN 32 CDMA Current Descriptor Pointer Register 35 CDMA Tail Descriptor Pointer Register 36 CDMA S Urce AddreSs Register Gen Eist deen ade a DE 36 CDMA Destination Address Register 37 CDMA Bytes to Transfer Register 38 Simple CDMA Programming Example esses eene nnne nnne rh nnns snnt nnns nnn 38 AXI BARO Aperture Base Address 39 BC Te Blees ergeet E o LO OLO p YE 39 PHY Status Control Register 40 AXI Base Address Translation Configuration Register 41 AUr ra Status EUER EN Ee eir e 41 Control Register oh tne tipi tte temet A EE 42 Flash eet Zadni MERE a memi e E 42 Write Protected Bitstream XMC 7A200 CC Models onhy enne 44 AXI XADC Analog to Digital Converter System Monitor 45 P1 Front I O XMC 7K325F and XMC 7K410F models on 46 PL Front lnput Data Register wasza trinm Eee e e eiae que dde Ree ex exea E 46 PT Front Output Data Register A etit mutatae 47 P1 Front Input Global Interrupt Enable Register 48 P1 Front Input Channel Interrupt Enable Register 48 P1 Front Input Channel Interrupt Status Register 48 PA Rear Input DatarRegister ue aso t e Oda aa ey ede SE 48 P4 Rear Output Data Register eo ia OE sue WT EO dE E nun Ea eee sue RE aaa PDA 49 P16 l put Data Reglster uoi rere O OPO sane ee Eee ture A EWG EWA E 50 P16 Output Data EE 51 5 THEORY OF OPERATION a osz re chan eet opa eege s OO desk wss 52 PCIIN
16. 3 4 aurora 8bi0b i aurora 8bi0b 0 exdes MAPPED aurora 8bi0b 0 exdes vhd 16 D Configuration Files 5 H 6 IP Update Log 27 i es IP Sources Libraries Compile Order Figure 12 Design Sources Hierarchy Acromag Inc Tel 248 295 0310 64 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL mgt ci ENETI signal dete Ly NEI signal detect Py men dq 15 0 Dy PCI_RESETn sis cx p WE Figure 13 XMC 7KxxxF Block Diagram Top Level Acromag Inc Tel 248 295 0310 65 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Cell E TE mbO microblaze 0 i ER El Data 32 address bits 4G E M Instruction 32 address bits 4G CZ mbi microblaze 1 B Data 32 address bits 4G HB Instruction 32 address bits 4G Ethernet axi ethernet 0 Oms M Data SG 32 address bits 4G E Data MM2S 32 address bits 4G B Data S2MM 32 address bits 4G Ethernet axi ethernet 1 dma M Data SG 32 address bits 4G E Data MM2S 32 address bits 4G E Data S2MM 32 address bits 4G CDMA axi cdma 0 a Data 32 address bits 4G Ci 3F PCIe axi pde 0 B E M AXI 32 address bits 4G a DDR3 Memory mig 7series 0 en P16 IO es AURORA CNTL STAT m CDMA axi cdma 0 es FRONT IO DDR3 Memory xadc wiz 0
17. Acromag Inc Tel 248 295 0310 103 www acromag com XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 USER S MANUAL Electric Fast Transient Immunity Complies with IEC61000 4 4 class A Radiated Emissions Complies with CISPR 16 2 3 class A Electrostatic Discharge Complies with IEC6100 4 2 Level 2 Conducted Radio Frequency Interference Complies with IEC6100 4 6 class A 104 www acromag com XMC 7 Series AXM CC F Certificate of Volatility USER S MANUAL Certificate of Volatility Acromag Models XMC 7A200 LF XMC 7A200CC LF XMC 7K325AX LF XMC 7K410AX LF XMC 7K325CC LF XMC 7K410CC LF XMC 7K325F LF XMC 7K410F LF Manufacturer Acromag Inc 30765 Wixom Rd Wixom MI 48393 Volatile Memory m Yes No Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed Type SRAM SDRAM etc FPGA based RAM Size 795 x 36 Kbit 410 445 x 36 Kbit 325 365 x 36 Kbit Artix User Modifiable m Yes No Function Data storage for FPGA Process to Sanitize Power Down Type SRAM SDRAM etc SDRAM Size 128 Meg x 64 bit User Modifiable m Yes No Function Data storage for FPGA Process to Sanitize Power Down Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained whe
18. CC F USER S MANUAL be written via the Xilinx Platform USB II cable by placing SW1 position 4 in the off state and writing the flash via the Xilinx Platform USB II cable Table 33 Bitstream Select Flash Write Protect Switch Switch SW1 Function Default Position Position 1 off 2 off 3 off 4 on select golden bitstream off off select user bitstream AXI XADC Analog to Digital Converter System Monitor The XADC Analog to Digital Converter is used to monitor the die temperature and supply voltages of the FGPA The XADC channel sequencer is configured to continuously sample the temperature Vccint and Vccaux channels The results from the A D conversions can be read at the addresses given in column one of Table 34 Data bits 15 to 4 of these registers hold the ADCcode representing the temperature Vccint or Vccaux value Data bits 3 to O are not used The 12 bits output from the ADC can be converted to temperature using the following equation Temperature C BABE L 273 15 4096 The 12 bits output from the ADC can be converted to voltage using the following equation ADCcode SupplyVoltage volts x 3V pply ge volts aoe Additional information regarding the XADC can be found in the Xilinx XADC product guide PGO99 and the user guide UG480 Acromag Inc Tel 248 295 0310 45 www acromag com XMC 7 Series AXM CC F USER S MANUAL Table 34 System Monitor Register Map
19. D gt PCle REFCLK gt gt AXM INTERRUPT SS Saa Sms OX 6280067610 H ORO aie 2 A Figure 24 Modified Block Diagram Delete the port labeled REAR_OUT by right clicking on the port and selecting the delete operation Next left click on the port labeled REAR_IN The External Interface Properties pane will now focus on the REAR_IO_GPIO port as shown in Figure 25 REAR_IO_GPIO Figure 25 External Interface Properties pane Acromag Inc Tel 248 295 0310 75 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Change the name from REAR IN to REAR IO as shown in Figure 26 gt REAR IO GPIO Figure 26 External Interface Properties modified The block diagram should now look like Figure 27 with a single GPIO port named REAR IO on the REAR IO block de system gt HF La mem dq 115 0 L5 a FLASH_oen 0 0 PCI RESETn D gt E PCle_REFCLK gt E Cu AXL AX AXM_INTERRUPT 3 090 0m GH ORS 218 Pf 2 Ie Figure 27 Block Diagram modified Save the modifications to the block diagram by typing Ctrl S or selecting Save Block Design from the File menu Next click on the Generate Block Acromag Inc Tel 248 295 0310 76 www acromag com XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 USER S MANUAL Design command under
20. Mode can be utilized Scatter Gather not included Scatter Gather is included 0 Acromag Inc Tel 248 295 0310 32 www acromag com XMC 7 Series AXM CC F USER S MANUAL Bit s FUNCTION DMA Internal Error This bit indicates that an internal error has been encountered by the DataMover on the data transport channel This error can occur if a O value Byte to Transfer register is fed to the AXI DataMover or DataMover has an internal processing error A Bytes to Transfer register value of 0 only happens if the register is written with zeros in Simple DMA mode or a Bytes to Transfer register value of 4 zero is specified in the Control word of a fetched descriptor is set to 0 Scatter Gather Mode This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition _0__ No CDMA Internal Errors CDMA Internal Error detected CDMA Engine halts DMA Slave Error This bit indicates that an AXI slave error response has been received by the AXI DataMover during an AXI transfer read or write This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition EA No CDMA Slave Errors CDMA Slave Error detected CDMA Engine halts
21. S MANUAL Acromag Inc Tel 248 295 0310 110 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL 12 Revision History Release Date EGR DOC Description of Revision 15 MAY 15 JCL ARP Added XMC 7A200 LF XMC 7A200CC LF XMC 7K325F LF and XMC 7K410F LF models C JCL ARP Added CE compliance statement to specifications section Acromag Inc Tel 248 295 0310 111 WWW acromag com
22. Value 0x00000000 Default Tri State Value OxFFFFFFFF E Enable Interrupt d 1 32 y 0x00000000 0xFFFFFFFF 0x00000000 0xFFFFFFFF Acromag Inc Tel 248 295 0310 Figure 22 Re customize AXI GPIO 73 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL De select the All Inputs check box De select Enable Dual Channel Hit OK The dialog box should look like Figure 23 r He LF Re customize IP A Y ER Y 7 I AXI GPIO 2 0 d h Documentation 73 IP Location LJ Component Name REAR_IO GPIO E All Inputs E All Outputs GPIO Width 32 1 32 Default Output Value 0x00000000 0x00000000 0xFFFFFFFF Default Tri State Value OxFFFFFFFF 0x00000000 0xFFFFFFFF i de At E Enable Dual Channel s axi sch oos au e axi aresem i All Inputs All Outputs GPIO Width 32 1 32 Default Output Value 0x00000000 0x00000000 0xFFFFFFFF Default Tri State Value OxFFFFFFFF 0x00000000 0xFFFFFFFF i f Enable Interrupt Figure 23 Re configured REAR IO Acromag Inc Tel 248 295 0310 74 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The block diagram has changed as shown in Figure 24 There is now only one GPIO port on the REAR IO block Es Diagram x FR Address Editor X GH system_top vhd X Dni 21 4 system gt mem da i 15 0 Q PCI_RESETn
23. and restarting the board If your code does not function as desired you may need to reload the Acromag design example You can reload the Acromag example design via the JTAG port using the Xilinx Vivado tool Upon power up the example design provided by Acromag will again be loaded into the FPGA Note XMC 7A200AX CC models are delivered with two copies of the example design bitstream stored in flash memory One of the copies is stored in a write protected section of the flash If the configuration 20 www acromag com XMC 7 Series AXM CC F FPGA Configuration USER S MANUAL file loaded from the writeable section of flash fails to support the flash write function via the PCle bus a recovery method is available The FPGA can be directed to configure from the backup bitstream by opening switch SW1 position 3 shown in Figure 3 See the Flash Configuration section for a description of the steps required to write new data or to reprogram the example design code to the flash device L1 Sw1 Figure 3 XIVIC 7A200 Switch Location The XMC 7 series modules support configuration in the following modes e Master BPI Up using Linear BPI Flash device e JTAG using Xilinx external program cable The FPGA configuration bitstream is loaded from flash memory on power up PCle CONFIGURATION ADDRESS SPACE Acromag Inc Tel 248 295 0310 This XMC 7 series modules are PCI Express Base Specification Revision v2 1 compliant The PCle bus is def
24. brings the 36 pins of the VHDCI front I O connector out to a 50 pin SCSI connector The Acromag part number is 5025 921 See Table 5 Front VHDCI Field I O Pin Connections A cable drawing is also provided in the accessories section at the end of this manual Acromag provides a 1 meter direct attach cable that connects one SFP port to another SFP port This passive cable can be used to carry 10 Gb Ethernet or Aurora signals to another nearby XMC 7Kxxx module The Acromag part number is TAPCABLE1M A cable drawing is provided in the accessories section at the end of this manual 1000BASE T Copper SFP Transceiver Acromag provides a Copper SFP Transceiver that is compatible with the Gigabit Ethernet and 1000BASE T standards as specified in IEEE Std 802 3 It has an RJ 45 connector and is RoHS compliant and lead free The Acromag part number is 5028 455 A cable drawing is provided in the accessories section at the end of this manual 2 125 Gb S Short Wavelength SFP Transceiver Acromag Inc Tel 248 295 0310 13 www acromag com XMC 7 Series AXM CC F USER S MANUAL Acromag provides 2 125 Gb s Short Wavelength SFP Transceiver that is compatible with the Gigabit Ethernet standard as specified in IEEE Std 802 3 and Fibre Channel FC PI 2 Rev 5 0 It is ROHS compliant and lead free It supports up to 2 125 Gb s bi directional data links The module uses an 850nm Oxide VCSEL laser transmitter The Acromag part number is 5028 452 A drawing is
25. by this field for the associated transfer Writing to this register also initiates the Simple DMA transfer Note A value of zero 0 is not allowed and causes a DMA internal error to be set by AXI CDMA The software application should only write to this register when the AXI CDMA is Idle Writing to these bits has no effect and they are always read as zeros 22 0 31 23 Simple CDMA Programming Example Acromag Inc Tel 248 295 0310 1 Verify the CDMA is idle Read CDMA Status register bit 1 as logic 1 2 Program the CDMA Control register bit 12 to the desired state for interrupt generation on transfer completion 3 Write the desired transfer source address to the Source Address register at 0xA0018 The transfer data at the source address must be valid and ready for transfer If we were to select the DDR memory as the source and wanted to start a move of data from the beginning of DDR we would write 0x80000000 to the Source Address register at OxA0018 4 Write the desired transfer destination address to the Destination Address register at OxA0020 If the destination is the system memory then the following is required a Given physical address of buffer of 0x0000333012345678 b AXIBAR2PCIEBAR_OU offset 000F0208 gt 0x00003330 c AXIBAR2PCIEBAR OL offset OOOFO20C gt 0x12345678 d The least significant 24 bits of this address 0x12345678 must be removed and added to the AXI BARO Apert
26. com XMC 7 Series AXM CC F DDR3 Memory Clock Generation Multi Gigabit Transceivers Acromag Inc Tel 248 295 0310 USER S MANUAL A 128 Meg x 64 bit of DDR3 memory is provided for user applications Four DDR3L memory devices are used to form a 64 bit data bus Each of the devices are 128 Meg x 16 bit 2Gb in size All four devices add to 8Gb or 1GByte total memory The DDR3 interface is implemented in FPGA banks 32 33 and 34 33 to 35 of Artix DCI VRP N resistor connections are implemented on bank 32 DCI functionality in bank 34 is achieved in the XDC by cascading DCI between adjacent banks as follows set property DC CASCADE 32 34 get iobanks 33 DCI is not required with the Artix DDR interface There are four FPGA clock sources available on the board A 2 5V LVDS 200 MHz oscillator U22 is wired to the FPGA global clock input pins AG10 and AH10 AB5 and ABA of Artix The signal names are clk200_p and clk200 n This oscillator is the reference clock for the DDR3 memory interface IDELAY controller This clock is multiplied by two to produce a 400 MHz memory clock for the DDR3 memory Artix models only A 2 5V LVDS 156 25 MHz oscillator U21 is wired to the FPGA global clock input pins AE10 and AF10 Kintex models only The signal names are SYS CLK clk p and SYS CLK clk n This clock is multiplied by four to produce a 625 MHz memory clock for the DDR3 memory A 2 5V LVDS 156 25 MHz oscillator U11 is wired to t
27. input The bit locations in the Set Interrupt Enable correspond with the bit locations given in the Interrupt Enable register Table Table 14 Set Interrupt Enable Register Write BARO 0x00100010 Bits FUNCTION Set AXM Front I O interrupt enable Set AXI CDMA interrupt enable 31 2 Reserved Clear Interrupt Enable register is a location used to clear Interrupt Enable register bits in a single atomic operation rather than using a read modify write sequence Writing a 1 to a bit location in Clear Interrupt Enable register will clear the corresponding bit in the Interrupt Enable register Writing Os does nothing as does writing a 1 to a bit location that corresponds to a non existing interrupt input The bit locations in the clear Interrupt Enable correspond with the bit locations given in the Interrupt Enable register Table Table 15 Clear Interrupt Enable Register Write BARO 0x00100014 Bits FUNCTION Clear AXM Front I O interrupt enable Clear AXI CDMA interrupt enable 31 2 Reserved The Interrupt Vector register is a read only register and contains the ordinal value of the highest priority enabled and active interrupt input INTO always the LSB is the highest priority interrupt input Each successive input to the left has a corresponding lower interrupt priority If no interrupt inputs are active the Interrupt Vector register contains all 1s This Interr
28. provided in the accessories section at the end of this manual 3 PREPARATION FOR USE UNPACKING AND INSPECTION W b d SENSITIVE ELECTRON DEVICES He ox STORE REAR ETROAG D IC Wa ELECTROMAGNETIC MAGNETIC OR RADIGASTIVE FIE ix CARD CAGE CONSIDERATIONS Board Installation Acromag Inc Tel 248 295 0310 Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should only be handled at a static safe workstation Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of
29. system monitor is used to measure FPGA physical operating parameters such as on chip power supply voltages and die temperature 56 www acromag com XMC 7 Series AXM CC F USER S MANUAL 6 FPGA FIRMWARE EXAMPLE DESIGN Acromag provides an FPGA firmware example design that provides host access to each of the hardware peripherals on the XMC module The example design is intended to be a starting point from which customers will develop their customized applications The example design is implemented using the Xilinx Vivado development environment Project Mode design flow XMC 7A200 CC and XMC 7KxxxAX Models Block Diagram Overview Acromag Inc Tel 248 295 0310 The hierarchy of the AXM Model example design is shown in Figure 5 below Figure 5 is a screen clipping from the Hierarchy tab of the Sources pane in the Vivado development environment The example design consists of a combination of VHDL source files and a Xilinx Vivado IP Integrator block diagram At the highest level of the hierarchy is the system top VHDL source file shown in the figure with the least levels of indentation This top level module instantiates the following three lower level modules AXM Dxx system and aurora 8b 10b O exdes ANM Dxx is the top of the hierarchy used to instantiate any of Acromag s digital AXM modules System is the Vivado IP Integrator block diagram source where the majority of the example design logic is located aurora 8b 10b O e
30. 0 system xlconstant 0 0 system xlconstant 0 0 xci EH HiExiconstant_1 system_xlconstant_1_0 system xiconstant 1 0 xc a 1FREAR_IO system_axi_gpio_0_1 system_axi_gpio_0_1 xci C R mbO mbO_imp_1DM7YHW STRUCTURE system vhd 9 LF axi_iic_O system_axi_iic_0_0 system axi iic 0 0 xci LF axi_timer_0 system axi timer D 0 system axi imer 0 0 xci AF axi_uart16550_0 system axi uart16550 0 0 system a uart16550 0 Dach LF mdm 0 system mdm 1 0 system mdm 1 0 xci E F microblaze 0 system microblaze 0 0 system microblaze 0 0 xcdi ER t i T microblaze 0 axi intc system microblaze 0 axi intc D system microblaze 0 axi intc 0 xci i E AF microblaze 0 xlconcat system microblaze 0 xlconcat 0 system microblaze 0 xlconcat 0 xcd B e mb1 imp 5Q8YQ8 STRUCTURE system vhd 7 i ER LF axi_iic_1 system_axi_iic_1_0 system axi iic 1 O xc EB XFaxi timer 1 system axi timer D 1 system axi timer O jc iF microblaze 0 xlconcat system microblaze 0 xlconcat 1 system microblaze 0 xiconcat 1 xci 4 LF microblaze_1 system_microblaze_0_1 system microblaze D 1 xci GER microblaze 1 axi intc system microblaze 0 axi intc Lioustem microblaze 0 axi intc 1 xc G microblaze 1 axi periph system microblaze 0 axi periph 1 STRUCTURE system vhd 8 GH microblaze 1 local memory microblaze 1 local memory imp 17XOTN6 STRUCTURE system vhd 5 i ZE xlconcat_0 system xlconcat D 0 system xlconcat 0 0 xci
31. 3 SDRAM is connected to the FPGA e Interface to Rear P4 Connector The FPGA is directly connected to 64 pins of the rear P4 connector All 2 5 Volt I O standards supported by the Xilinx 7 series devices are available The example design implements LVCMOS single ended signaling e P15 High Speed Interface Eight high speed serial lanes are allocated to the XMC P15 connector These lanes can be used for an 8 lane PCle PCI Express implementation Serial RapidlO or 10 Gigabit Ethernet The Kintex example design includes an 8 lane Gen 1 PCle implementation while the Artix example design includes a 4 lane Gen 1 PCle implementation Features supported on AX models e Acromag ANM Module Support various mezzanine modules AXM model prefix ordered separately allow the user to select the Front I O required for their application e P16 High Speed Interface Eight high speed serial lanes are allocated to the XMC P16 connector in the AX models These lanes can be used for Serial RapidlO PCle 10 Gigabit Ethernet or Xilinx Aurora The example design supports a pair of four lane Aurora interfaces in a chip to chip loopback implementation Features supported on CC models e P16 High Speed Interface Eight high speed serial lanes are allocated to the XMC P16 connector in the CC model These lanes can be used for Serial RapidlO PCle 10 Gigabit Ethernet or Xilinx Aurora The example design supports a pair of four lane Aurora
32. 324 P inout STD LOGIC a 125 CIRL2324 N inout STD LOGIC 126 CIRL25 inout STD LOGIC da 127 CTRL26 inout STD LOGIC X 128 CTRL27 inout STD LOGIC 129 CTRL28 inout STD LOGIC il Wier 131 The following signals are used to interface if 132 pe di 134 go 135 The folloving signals are used to interface 136 P16_SI in std logic vector 17 downto 0 137 P16 SO out std logic vector 17 downto 0 e 138 2 139 Vp Vn v n in STD LOGIC i 140 Vp Vn v p in STD LOGIC Zhi E 81 E C XMC 7K325AX_MOD XMC 7K325AX XMC 7K325AX srcs sources_1fmports system_top vhd to to the Rear I O LVDS port the P16 Standard I O port WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Insert the highlighted lines 127 CTRL26 128 CTRL27 129 CTRL28 inout STD_LOGIC inout STD_LOGIC inout STD LOGIC The folloving signals are used to interface to the Rear I O LVDS port The folloving signals are used to interface to the P16 Standard I O port 136 P16 SI in std logic vector 17 downto 0 137 P16_SO out std logic vector 17 downto 0 139 Vp Vn v n in STD LOGIC 140 Vp Vn v p in STD LOGIC WER 142end system top 143 144architecture STRUCIURE of system top is 145 the block diagram 146 component system is C XMC 7K325AX MOD XMC 7K325AX XMC 7K325AX srcs sources i imports system top vhd 287 signal M AXI AXM rresp STD LOGIC VECTOR 1 downto 0
33. AX XMC 7K325AX runs impl_7K325AX_Dxx XMC 7K325AX mcs when prompted to enter complete file path r w 8 GNXMC Kintex7 Windows files XMC Kintex Waele files c SS oe 2010 x64 R 7 Erase flash block 8 Erase flash chip 22 Compare file to flash 99 Return to main menu Enter selection 5 Select configuration file 1 Example design for 7K32588 with AXM 438 mezzanine module Gz NAcromagNPGCISW_API_WINAconfig_filesN7 K325_AXMA368 mcs 2 Example design for 7K32588 with AXM 475 mezzanine module G N cromagNPGISW_API_WINNconfig_filesN K325_ARMA 5 mcs 3 Example design for 7K325AX with AXM DB1 mezzanine module C Acromag PCISW_API_WIN conf ig_f iles 7K325_AXMD 1 mcs 4 Example design for 7K325AX with AXM D 2 3 4 or EDK mezzanine module C fAcromag PCISW_API_WIN conf ig_f iles 7K325AXK mcs 5 Example design for 7K325AX with AXM D3X63 mezzanine module C Acromag PCISW_API_WIN conf ig_f iles 7K325_AXMDKG 3 mcs 6 Other Enter selection 6 Enter complete file path The following message is displayed indicating the flash write operation is complete Enter 99 twice and answer Y to exit E we we w m 8 GAXMC Kintex7 Windows files XMC Kintex7 Wii files c ate m ts 2010 x64 R EE 6 Other nter selection 6 nter complete file path C RMC 7K325AK_MOD AMC 7K325AKR RMC 7K325AK runsNimpl 7 325808 EDK XMC 7K325804 EDK mcs riting file to flash lt This can t
34. Acromag 4 THE LEADER IN INDUSTRIAL LO Xilinx 7 series FPGA Based XMC Modules USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Copyright 2014 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8501 008C XMC 7 Series AXM CC F USER S MANUAL Table of Contents 1 RELATED PUBLICATIONS 1 iiie er tnit rait eth edere kie ete ede e age a ed etn P eR ee Tre edd de ani en Peas de eb ideo aE 5 2 GENERAL INFORMATION RM 6 Ordering le ei ut Le E 8 KEY FEATURES cirrosis ege SEENEN Ee GE EE 11 PCl Interface Features occorre or EEE yan degna Dee oc e etae ageet 12 Keel REE 12 ENGINEERING DESIGN KIT tegt ais dietas eek ede tn de e Rae eaaet ae td pena reatu Pe Re ERE NER RERO ERR POWA RENS 12 WINDOWS 12 VXWORKS CD ccna c 13 Nd ke 13 Signal Interface Products XMC 7K325F and XMC 7K410F Model 13 3 PREPARATION FOR TE 14 UNPACKING AND INSPECTION eu aan a eee ee aaa aaa aaa aaa aaa aaa aa aaa aaa aaa aaa aaa aaa aaa agaia iiaa 14 CARD CAGE CONSIDERATIONS ee eee eee ea aaa aaa aaa aaa aaa aaa aaa aaa aa aaa aaa aaa aaa AEEA nns 14 Board Installation urna 14 P15 Primary dee ell TE 15 P16 Secondary XMC Connector ect eceve cia 15 Rea
35. C 40 C to 70 C cold plate XMC 7K410CC 40 C to 70 C cold plate XMC 7K325F 40 C to 55 C XMC 7K410F 40 C to 55 C1 Relative Humidity 5 9596 non condensing Storage Temperature 55 to 125 C Non Isolated The PCle bus and the XMC module commons have a direct electrical connection As such unless the XMC module provides isolation between the logic and user I O signals the user I O signals are not isolated from the PCle bus Radiated Field Immunity Complies with IEC61000 4 3 class A Surge Immunity sss Not required for signal I O per European Norm EN61000 6 1 Tested on Acromag VPX4820 carrier with 500 LFM airflow Tested on Acromag VPX4820 CC carrier with thermal interface material Berquist Gap Pad 1500R between the carrier cold plate and the XMC module heatsink 8 Tested on Acromag VPX4820 carrier with 500 LFM airflow Tested on Acromag VPX4820 carrier with 500 LFM airflow 10 Tested on Acromag VPX4820 CC carrier with thermal interface material Berquist Gap Pad 1500R between the carrier cold plate and the XMC module heatsink 11 Tested on Acromag VPX4820 CC carrier with thermal interface material Berquist Gap Pad 1500R between the carrier cold plate and the XMC module heatsink 12 Tested on Acromag VPX4820 carrier with 500 LFM airflow 13 Tested on Acromag VPX4820 carrier with 500 LFM airflow
36. FFF_FFFF 1535M Reserved 0x6000_0000 gt 0x63FF_FFFF 64M Flash AXI EMC see PG100 0x6400_0000 gt 0x7FFF_FFFF 448M Reserved 0x8000_0000 gt 0xBFFF_FFFF 1G DDR3 SDRAM 0xC000_0000 gt 0xFFFF_FFFF 1G Reserved INTERRUPT CONTROLLER The AXI Interrupt Controller concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor using the PCle bus The interrupt controller contains programmer accessible registers that allow interrupts to be enabled queried and cleared under software control over the PCle bus interface Acromag Inc Tel 248 295 0310 24 www acromag com XMC 7 Series AXM CC F USER S MANUAL Table 9 Interrupt Controller Registers BARO Base Addr Bit s Description 0x00100000 31 0 Interrupt Status Register 0x00100004 31 0 Interrupt Pending Register 0x00100008 31 0 Interrupt Enable Register 0x0010000C 31 0 Interrupt Acknowledge Register 0x00100010 31 0 Set Interrupt Enable Register 0x00100014 31 0 Clear Interrupt Enable Register 0x00100018 31 0 Interrupt Vector Register 0x0010001C 31 0 Master Enable Register Note that any registers bits not mentioned will remain at the default value logic low Interrupt Status Register This Interrupt Status register ISR at BARO base address offset 0x100000 is used to monitor board interrupts When read the contents of this register indicate the presence or absence of an activ
37. ING request The EchoServerO program manages the SFP1 Ethernet port It reports status messages over the USB UART in the front panel field I O connector The UART configuration is 9600 baud 8 data bits 1 stop bit no parity It will respond to IP address 192 168 1 10 on subnet 255 255 255 128 The Echoserver1 program manages the SFP2 Ethernet port at IP address 192 168 1 138 on subnet 255 255 255 128 It reports status messages over the JTAG UART when a Xilinx Platform USB Cable is connected to the JTAG connector Bootloader Memory Map Each of the MicroBlaze processors has separate areas assigned in flash and DDR3 SDRAM address space as follows srec bootloader O FLASH IMAGE BASEADDR 0x61000000 size 0x010000 DDR3 SDRAM S AXI BASEADDR 0x80000000 size 0x20000000 srec bootloader 1 FLASH IMAGE BASEADDR 0x62000000 size 0x01000000 DDR3 SDRAM S AXI BASEADDR 0xA0000000 size 0x20000000 EchoServer Memory Map When running the echoserver application three separate DDR3 SDRAM memory areas are assigned to prevent each device from overwriting another device s data echoserver O DDR3 SDRAM S AXI BASEADDR 0x81000000 size Ox1F000000 echoserver 1 DDR3 SDRAM S AXI BASEADDR 0xA0000000 size 0x20000000 DMA Buffer PCle BAR1 memory space DDR3 SDRAM S AXI BASEADDR 0x80000000 size 0x01000000 Acromag Inc Tel 248 295 0310 69 www acromag com XMC 7 Series AXM CC F USER S MANUAL 8 DESIGN MODIFICATION WALK THROUGH This section details the
38. IP Integrator in the Flow Navigator pane to generate the underlying VHDL files for the block design as shown in Figure 28 Flow Navigator gt a Open Synthesized Design 4 Implementation 5 Implementation Settings gt Run Implementation b a Open Implemented Design 4 Program and Debug 6 Bitstream Settings Y Generate Bitstream D jg Open Hardware Manager Figure 28 Flow Navigator pane 77 www acromag com XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 USER S MANUAL The Generate Output Products dialog box shown in Figure 29 will appear Click on the Generate button E a ji Generate Output Products _ 8 The following output products will be generated cs Preview ala Ji system bd m 4 Synthesis m M Implementation C Simulation Qut of Context Settings Figure 29 Generate Output Products Dialog Vivado will display the following pop up on completion E Generate Output Products o Generation of output products completed successfully The system component and its instantiation in the system top vhd file must now be updated with changes made to the ports of the REAR IO block Open the system wrapper vhd file in C XMC 7K325AX MOD XMC 7K325AX XMC 7K325AX srcs sources 1 bd system hdl to see the updated component definition Prior to the update the system component definition included ports labeled REA
39. R IN tri i and REAR OUT tri o Now the updated system component definition has REAR IO tri i REAR IO tri o and REAR IO tri t 78 www acromag com XMC 7 Series AXM CC F USER S MANUAL Open the system top vhd file located in C XMC 7K325AX MOD XMC 7K325AX XMC 7K325AX srcs sources 1 imports Delete lines 152 and 153 Bg C XMC 7K325AX_MOD XMC 7K325AX XMC 7K325AX srcs sources_1fimports system_top vhd letz RO out std logic vector 31 downto 0 Wi 134 Wiss The following signals are used to interface to the P16 Standard I O port de 136 P16_SI in std logic vector 17 downto 0 ES 137 P16 SO out std logic vector 17 downto 0 138 fe 139 Vp Vn v n in STD LOGIC 140 Vp Vn v p in STD LOGIC il IMP 1142 end system top E 143 28 144 architecture STRUCTURE of system top is gal 145 the block diagram l 146 component system is 6 147 port 148 Vp_Vn_v_n in STD LOGIC 149 Vp_Vn_v_p in STD LOGIC e 150 P16_IN_tri_i in STD LOGIC VECTOR 17 downto 0 E P16 OUT tri o out STD LOGIC VECTOR 17 downto O0 lo 152 j 153 154 AS IN tri i in STD LOGIC VECTOR 31 downto 0 155 AS OUT tri o out STD LOGIC VECTUR 0 to 0 156 PCI RESETn in STD LOGIC 157 LCLK out STD LOGIC 158 clk200 in STD LOGIC 159 SYS CLK clk n in STD LOGIC 160 SYS CLK clk p in STD LOGIC 161 FLASH advn out STD LOGIC 162 FLASH cen out STD LOGIC VECTOR 0 to 0 Acromag Inc
40. R S MANUAL Ch Positive Pin Description Pin Negative Pin Description Pin 2 Ro p sa ROO27 N 28 juoosp 57 RIO28 N 29 uoo p 38 RI029_N 30 Rlo30p 61 Roy 31 boat GCLK P 62 RIO31_GCLK_N 64 The example design implements 2 5volt LVCMOS I O to the rear connector Alternatively 2 5volt LVDS I O can be used on the rear connector This connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the carrier board AMP 120521 1 or equivalent Front Panel Field UO Connector XMC 7K325F and XMC 7K410F models The front panel provides access to a 36 pin VHDCI connector and two SFP port connectors The VHDCI connector provides interfaces to JTAG USB and 26 single ended or 13 differential O signal pairs Two of the signal pairs are routed to global clock pins on the Kintex 7 device The 26 front I O signals connect directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt I O standards The IOSTANDARD attribute can be set in the user constraints file UCF The example design configures the Front I O as LVCMOS25 low voltage CMOS in the user constraints file The tables included in the Front Input Data Register and Front Output Data Register sections can be used to map the LVCMOS signals to the signal names given in the table below The Front I O can alternatively be defined for LVDS 25 L
41. Register Bit VHDL Name Schematic Name 0 FI 0 FIOO N I FA SES 2 FI 2 FIO2 N 3 Hj FON 4 FI 4 FIO4_N 5 F6 SEN 6 F6 FEH 7 HU FON 8 Hg POH 3 HG FON 10 LED Foton 11 FI 11 HO11 GCLK N 12 FI 12 FIO12 GCLK N P1 Front Output Data Register The front output data register is used to control the 13 LVCMOS output signals Each signal is controlled by a corresponding data bit as shown in Table 36 P1 output signals are controlled by writing this register P1 input signals are accessed by reading the front input data register at base address plus 0x310000 This front output data register is a read writable register Channel operations use 32 bit 16 bit or 8 bit data transfers Table 36 P1 Front Output Data Register BARO 0x310008 Register Bit VHDL Name Schematic Name 0 FO 0 FIOO P 1 FO 1 FIO1 P 2 Fog DOP 3 706 PSP Fou Foa 5 706 FoP 6 oe POST 7 FoU FoP 3 oe FIo8_P 9 706 RER 10 FOO PO 11 FO 11 FIO11_GCLK_P 12 FO 12 FIO12 GCLK P Acromag Inc Tel 248 295 0310 47 www acromag com XMC 7 Series AXM CC F P1 Front Input Global Interrupt Enable Register USER S MANUAL This register provides the master enable disable for the P1 Front I O interrupt output to the Interrupt Controller Table 37 Front Input Global Interrupt Enable Register BARO 0x31011C Bit s 0 30 Front Input Global Interrupt Enable Regis
42. TE 13 VPWR 1a MSDA 15 VPWR 16 MSCL 17 PEROT NC 18 GND Mc 19 REFCLKO P REFCLKO N N C WAKE ROOTH N C The P16 secondary XMC connector connects directly to the user programmable FPGA for both high speed Giga bit data signals and standard I O user signals The user I O pins are connected to FPGA banks with VCCO pins powered by 2 5 volts Thus these user I O pins support the 2 5 volt I O standards The IOSTANDARD attribute can be set in the design constraints file xdc For example P16 user I O can be defined for LVDS 25 Low Voltage Differential Signaling The example design configures the P16 I O as LVCMOS25 low voltage CMOS in the design constraints file The tables included in the P16 Input Data Register and P16 Output Data Register sections 15 WWW acromag com XMC 7 Series AXM CC F Rear P4 Field I O Connector 5 N C not connected Acromag Inc Tel 248 295 0310 USER S MANUAL can be used to map the LVCMOS signal to the signal names given in this table The 2 5 volt I O standards available are listed in the 7 Series FPGAs SelectlO Resources User Guide available from Xilinx Table 3 P16 Secondary XMC Connections Pin A B C D E F 1 oo 1867 2 17 N 3 oe 517P 4 SIS N 5 oos sis P 6 S13 N 7 DPO7 _ si3 P SIN 3 SES 10 9 N 11 so P 2 S7N 13 SE 1a S5 N 15 ss P 16 S3N 7 SS 18 SCH 19 REFCLKO P REFCLKO N SOG P N C JROOTON S1 P The example design implement
43. TERFACE NO LEE ER DDR3 MEMON dee Add A ca w me Atar ee EE 53 Clock Generation mecza ia A e A 53 Multi Gigabit TTM VE ataca 53 32MB kineEaF BPI FlashR oninia nh t e tea AAA A O 54 STAG POM EE 54 Encryption Key Storage eg a eii 54 Acromag Inc Tel 248 295 0310 3 www acromag com 10 11 12 XMC 7 Series AXM CC F USER S MANUAL Power System DEVICES z edet rere oh aude e b eun ev dove A er utate ne pede ane ai SE 54 Syst m Mo D e dle 56 FPGA FIRMWARE EXAMPLE DESIGN A 57 XMC 7A200 CC and XMC 7KxxxAX Models Block Diagram Overview cccccccssccesssecsssceeseceeseeceseeees 57 XMC 7KxxxF Models Block Diagram esses enne nnne nennen nnne tenni nass aaa 63 XMC 7 XXE SOWAN haea and aatem cee deci WE ntn d vins s 69 Bootloader Memory Map i cta adi 69 EchoServer Memory Map a ci 69 DESIGN MODIFICATION WALK THROUGH isses eene enne oaza aaa tense entes sse aaa aaa en tenis nnns 70 Copy the Project uice tret deua t Fa ee iet naa re aede eus Ped ges 70 Modify the Source Elei 71 Modify the Constraints File etd irrita rte PR A dee OO dead cn ev db 85 Compile thie Desi ee Eege a TW RARE Re ENTER si 89 Generate Bitstream oe AAA e meti itas 91 Write Configuration File to Flash e nanena aaa aa aaa kaza nnne nennen E nnns sss a nnns 97 SERVICE AND A Aa Aa dee Aaa eege ORGA 101 SERVICE AND REPAIR ASSISTANCE eene enne nnne r anaona s seen nnns senten seen nnn 101 PRELIMINARY SERVICE PROCEDURE eene aaa aaa aaa aaa a
44. Tel 248 295 0310 79 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Insert the highlighted lines qe dF B di RO out std_logic vector 31 downto 0 T39 The following signals are used to interface to the P16 Standard I O port 136 P16 SI in std logic vector 17 downto 0 T37 P16 SO out std logic vector 17 downto 0 138 139 Vp Vn v n in STD LOGIC 140 Vp Vn v p in STD LOGIC ISP 142 end system top 143 144 architecture STRUCTURE of system top is 145 the block diagram 146 component system is 147 port 148 Vp Vn v n in STD LOGIC 149 Vp Vn v p in STD LOGIC 150 P16 IN tri i in STD LOGIC VECTOR 17 downto 0 151 P16 OUT tri o out STD LOGIC VECTOR 17 downto 0 152 153 154 155 AS IN tri i in STD LOGIC VECTOR 31 downto 0 156 AS OUT tri o out STD LOGIC VECTOR 0 to 0 157 PCI RESETn in STD LOGIC 158 LCLK out STD LOGIC 159 clk200 in STD LOGIC 160 SYS CLK clk n in STD LOGIC 161 SYS CLK clk p in STD LOGIC 162 FLASH advn out STD LOGIC Acromag Inc Tel 248 295 0310 80 WWW acromag com XMC 7 Series AXM CC F Delete lines 132 and 133 USER S MANUAL 143 142 end system top Acromag Inc Tel 248 295 0310 144 architecture STRUCTURE of system top is 145 the block diagram 146 component system is 121 CTRL1920_N inout STD LOGIC a 122 CTRL2122_P inout STD_LOGIC QU 23 CTRL2122 N inout STD LOGIC de 124 CIRL2
45. a_8b10b_0_exdes MAPPED aurora 8b 9 5 Text 1 H E Configuration Files 2 E B Update Log 11 H E Constraints 1 4 Simulation Sources 1 z B m Hierarchy IP Sources Libraries Compile Order Figure 20 Sources Pane showing expanded hierarchy The block diagram will open as shown in Figure 21 Double click on the REAR IO block located in the lower right portion of the diagram Ea Diagram X R Address Editor X h system_top vhd x Ki e 1 dq o 15 a mem da 115 0 EJ LFS nen seng g FLASH qwen 1 0 a gt FLASH addr 24 0 l F D As IN a D as our ran s gt pde 7x mgt F PCLRESETN E Mesi 4 y D M AXI AXM x xkoncat 0 Q 8 ih u Concat sys aD EI vo vn Ki a200 Ey Figure 21 Block Diagram Acromag Inc Tel 248 295 0310 72 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The Re customize IP dialog for the AXI GPIO IP will appear as shown in Figure 22 e ik Re customize IP x T AXI GPIO 2 0 Documentation 73 IP Location E Show disabled ports GPIOd Il s axi aresem p ll Component Name REAR IO GPIO All Inputs All Outputs GPIO Width 32 Default Output Value 0x00000000 Default Tri State Value OXFFFFFFFF Y Enable Dual Channel GPIO 2 All Inputs Y All Outputs GPIO Width 32 Default Output
46. aa aaa aaa DRENANTE KENARA 101 WHERE TO GET HELP zoo tio e re EO Pee Ove ha dea aie een rate BO koe e Ee eaa as 101 SPECIFICATION EE 102 PHYSICA Lei ii a A AA A A ta A AA EE 102 POWER iii ia a dt did 102 PCle BUS COMPLIANGE cia err e Rr aida Ee ree eid eee ero epa pru e 103 ENVIRONMENTAL cocaina a idas 103 Ta NP tate RR dnce 105 LS gu 106 XMC 7K325F and XMC 7K410F Accessories aaa aa aa aa aa aaa eene aaa nnn nnn nennt nnns nsns 106 VHDCI Cable O 106 SFP Direct Attach Cable cccccccccccssssssnsececessesssssensecececsessassansececessessansaesececessessaasanseceeaesesseasanes 107 1000BASE T Copper SFP Transceiver neneeese eaa aana a aa ana aE aea aSa aN ETEei 108 2 125 Gb s Short Wavelength SFP Transceiver aaa aaa aaa aaa aaa aaa aaa 109 Revision HISTORY o itte ee tt aet tttm 111 Acromag Inc Tel 248 295 0310 4 www acromag com XMC 7 Series AXM CC F USER S MANUAL All trademarks are the property of their respective owners IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility The information contained in this manua
47. ail Descriptor Pointer register needs to be programmed with the address of the first word of the last descriptor of the chain When the AXI CDMA executes the last descriptor and finds that the Tail Descriptor pointer matches the address of the completed descriptor the Scatter Gather Engine stops descriptor fetching and waits See the Xilinx AXI Central Direct Memory 29 www acromag com XMC 7 Series AXM CC F USER S MANUAL Access product guide PG034 for additional details for Scatter Gather operations Table 18 AXI CDMA Registers BARO Base Addr Bit s Description 0x000A0000 31 0 CDMA Control Register 0x000A0004 31 0 CDMA Status Register 0x000A0008 31 0 Current Descriptor Pointer Register 0x000A000C 31 0 Reserved 0x000A0010 31 0 Tail Descriptor Pointer Register 0x000A0014 31 0 Reserved 0x000A0018 31 0 Source Address Register 0x000A001C 31 0 Reserved 0x000A0020 31 0 Destination Address Register 0x000A0024 31 0 Reserved 0x000A0028 31 0 Bytes to Transfer Register Note that any registers bits not mentioned will remain at the default value logic low CDMA Control Register This register provides software application control of the AXI CDMA Table 19 CDMA Control Register Read Write BARO 0x000A0000 Bit s FUNCTION This bit is reserved for future definition and will always return zero Indicates tail pointer mode is enabled to the Scatter Gather Engine T
48. ake several minutes ile write complete Last address written 88629636 Flash status address MBBBBBBB gt Ready and no errors Flash status details Clear flash status Read flash data Write flash data Urite configuration file to flash Write code file to flash Erase flash block Erase flash chip Compare file to flash Return to main menu ter selection You must cycle the power to the XMC 7K325AX module in order to load the updated configuration file into the FPGA Acromag Inc Tel 248 295 0310 100 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL 9 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 3 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the carrier and or XMC module with one that is known to work correctly is a good technique to isolat
49. and Dynamic Link Libraries DLLs that are compatible with a number of 12 www acromag com USER S MANUAL XMC 7 Series AXM CC F VxWorks Linux programming environments The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a software product sold separately consisting of VxWorks software This software Model PMCSW API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCl I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag provides a software product consisting of Linux software This software Model PMCSW API LNX is composed of Linux libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Signal Interface Products XMC 7K325F and XMC 7K410F Models VHDCI Cable Direct Attach Cable Accessory cables that interface to the front VHDCI connector and SFP ports are available from Acromag Acromag provides a cable that
50. and rate switching for Gen2 capable cores Table 28 PHY Status Control Register Read Write BARO 0x000F0144 Bit s FUNCTION Reports the current link rate 0 0 2 5GT s 5 0 GT s Reports the current link width a la x2 x4 x8 Reports the current Link Training and Status State Machine state Encoding is specific to the underlying Integrated Block 8 3 Reports the current lane reversal mode No reversal Tn Lanes 1 0 reversed Lanes 3 0 reversed Lanes 7 0 reversed Reports the current PHY Link up state pn Link down 11 Acromag Inc Tel 248 295 0310 40 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL AXI Base Address Translation Configuration Register Aurora Status Acromag Inc Tel 248 295 0310 The address space for PCle is different than the AXI address space To access one address space from another address space requires an address translation process These register are needed for DMA transfers that move data to the system memory buffer The location of the system memory buffer is loaded into these registers AXI Base Address Translation Configuration register at BARO OXF0208 must be written with the most significant 32 bits of the address in system memory to which the DMA transfer is to read or write An example of the c code used to set this register with the physical address is shown below AXI Base Address Translation Confi
51. ary to program and operate the board 1 The XMC 7 series modules are shipped with the example design FPGA bitstream stored in the flash memory This example design bitstream operates with the driver software included in the support package Upon power up the XMC 7 series module will automatically configure the FPGA with the example design bitstream stored in flash As a first step become familiar with the appropriate example design for your model The board will perform all the functions of the example design as described in this manual The Example Design Memory Map section gives a description of the I O registers provided by the example design It will allow testing of PCle interface read write of DDR3 memory all digital I O ports interrupts P16 Aurora loopback and DMA operation It is strongly recommended that you become familiar with the board features by using the example design as provided by Acromag CAUTION Do not attempt to reconfigure the flash memory until after you have tested and become familiar with the XMC 7 series module as provided in the example design 2 After you are familiar with the module s features and have tested it using the example design proceed to the DESIGN MODIFICATION WALK THROUGH Here you will modify the example design VHDL code slightly The configuration flash must be overwritten to test your design Once the flash is erased you will not be able to go back to the example design by simply powering down
52. ated by the corresponding interrupt input An interrupt input that is active and masked by writing a 0 to the corresponding bit in the Interrupt Enable register will remain active until cleared by acknowledging it Unmasking an active interrupt causes an interrupt request output to be generated if the Master Interrupt Enable bit 0 in the Master Enable register is set Writing Os has no effect as does writing a 1 to a bit that does not correspond to an active input or for which an interrupt input does not exist The bit locations in the Interrupt Acknowledge register correspond with the bit locations given in the Interrupt Enable register Table Table 13 Interrupt Acknowledge Register Write BARO 0x0010000C Bit s FUNCTION 0 Clear AXM Front I O interrupt request 1 Clear AXI CDMA interrupt request 31 2 Reserved Set Interrupt Enable register is a location used to set Interrupt Enable register bits in a single atomic operation rather than using a read modify write 27 www acromag com XMC 7 Series AXM CC F Clear Interrupt Enable Register Interrupt Vector Register Master Enable Register Acromag Inc Tel 248 295 0310 USER S MANUAL sequence Writing a 1 to a bit location in the Set Interrupt Enable register will set the corresponding bit in the Interrupt Enable register Writing Os does nothing as does writing a 1 to a bit location that corresponds to a non existing interrupt
53. bled the interrupt immediately generates a request on the IRQ output An interrupt must be cleared by writing to the Interrupt Acknowledge Register as described below Reading this Interrupt Enable register indicates Acromag Inc Tel 248 295 0310 26 www acromag com XMC 7 Series AXM CC F Interrupt Acknowledge Register Set Interrupt Enable Register Acromag Inc Tel 248 295 0310 USER S MANUAL which interrupt inputs are enabled where a 1 indicates the input is enabled and a 0 indicates the input is disabled Table 12 Interrupt Enable Register Read Write BARO 0x00100008 Bit s FUNCTION 0 hen set indicates an interrupt from AXM module or Front I O is enabled See the appropriate AXM module data sheet for information on the source of this interrupt o Disabled 1 Enabled 1 hen set indicates an AXI CDMA interrupt enable See the CDMA section for source of this interrupt 0 Disabled 1 Enabled Reserved D NA 1 NA 31 2 The Interrupt Acknowledge register is a write only location that clears the interrupt request associated with selected interrupt inputs Note that writing one to a bit in Interrupt Acknowledge register clears the corresponding bit in Interrupt Status register and also clears the same bit itself in the Interrupt Acknowledge register Writing a 1 to a bit location in the Interrupt Acknowledge register will clear the interrupt request that was gener
54. bpi x16 Configuration file SAX XMC 7K325AX runsfimpl_7K325AX_Dxx 7K325AX mcs State of non config mem I O pins Pull none D Program Operations Address Range Configuration File Only NONE v The flash write progress is displayed A Program Configuration Memory Device o Flash programming completed successfully Las Acromag Inc Tel 248 295 0310 96 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Write Configuration File to Flash Start the PCle7KDemo program to program the FPGA from the host PC The following screen is displayed Type 2 to locate the board to be programmed r a GAXMC Kintex7 Windows files XMC Kintex7 Windows files c_examples PCle7K msdev_2010 x64 R PCIe 7K Demonstration Program K Main Menu Demo instructions 2 Locate Choose board 79 Exit Enter selection The following screen is displayed Type 1 to select the 7K325AX XMC module Ww 8 GAXMC Kintex7 Windows files XMC Kintex7 Windows files c_examples PCle7K msdev_2010 x64 R PCIe 7K Demonstration Program K Main Menu Demo instructions Locate Choose board 29 Exit 1 4 Select board to open Acromag Inc Tel 248 295 0310 97 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The following screen is displayed Type Y r 8 GAXMC Kintex7 Windows files XMC Kintex7 Windows files c_examples PCle7K msdev_2010 x64 R LEE PCIe 7K Demonstrati
55. d BARO 0x340000 Bit s 0 Aurora Reset Control 0 Removed from Reset 1 Held in Reset 1 Reserved 2 Channel UP Loopback Channel is down 1 Loopback Channel is up Function 3 15 Reserved 16 23 Link Link is down 1 Link is up 24 31 Reserved D rite logic low has no effect 1 rite logic high has no effect This Control register provides a single output signal It is accessed at base address plus 0x340008 The Control register bit 0 is used take the Aurora link into and out of reset Set to logic 1 the link is held in reset and set to logic O the link is removed from reset Table 30 Aurora Control Register Read Write BARO 0x340008 Bit s Function Aurora Reset Control Removed from Reset Held in Reset rite logic low has no effect rite logic high has no effect The BPI flash memory provides 64M bytes of non volatile memory for storing the FPGA configuration bitstream and program code or data storage for an embedded MicroBlaze processor The system CPU cannot directly access the flash memory The CDMA controller must be used to transfer data between DDR3 memory and Flash The system CPU must first write read data to from DDR3 memory and then initiate a DMA transfer to move the data to from Flash memory The CDMA controller must also be utilized to read write Flash memory control and status registers The BPI
56. e a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 624 1541 Fax 248 624 9234 Email solutions acromag com Acromag Inc Tel 248 295 0310 101 www acromag com XMC 7 Series AXM CC F 10 SPECIFICATIONS PHYSICAL POWER Acromag Inc Tel 248 295 0310 USER S MANUAL Length tecto itte iet 149 0 mm 5 866 in Width tete tete 74 0 mm 2 913 in Stacking Height 10 0 mm 0 394 in Weight XMC 7A200 110g Weight XMC 7A200CC 115g Weight XMC 7K325AX 123g Weight XMC 7K325CC 117g Weight XMC 7K410AX 123g Weight XMC 7K410CC 117g Weight XMC 7K325F
57. e interrupt for each of the active interrupting sources Each bit in this register that is set to a 1 indicates an active interrupt signal on the corresponding interrupt input Bits that are O are not active The bits in the ISR are independent of the interrupt enable bits in the Interrupt Enable register Interrupts even if not enabled can still show up as active in the ISR Table 10 Interrupt Status Register Read Write BARO 0x00100000 Bit s FUNCTION 0 hen set indicates an interrupt from either the AXM module AXM models or Front I O F Models See the appropriate AXM module user s manual for information on the source of this interrupt 0 Disabled 1 Enabled hen set indicates an AXI CDMA interrupt See the CDMA section for source of this interrupt Disabled 1 Enabled The ISR register is writable by software only until the Hardware Interrupt Enable bit in the MER has been set Given these restrictions when this Acromag Inc Tel 248 295 0310 25 www acromag com XMC 7 Series AXM CC F USER S MANUAL register is written to any data bits that are set to 1 will activate the corresponding interrupt just as if a hardware input became active Data bits that are zero have no effect This allows software to generate interrupts for test purposes Interrupt Pending Register This Interrupt Pending register IPR at BARO base address offset 0x100004 is used to monitor board inte
58. ec burst data transfer rate can be achieved when utilizing eight lanes e PCIe Bus Master The PCle interface logic becomes the bus master to perform DMA transfers e DMA Operation The example design includes a DMA controller to move data between the DDR3 memory and the PCle bus interface e Compatibility PCI Express Base Specification v2 1 compliant PCI Express Endpoint Provides one multifunction interrupt The XMC 7 series modules are compatible with XMC VITA 42 3 specification for P15 The XMC 7 series products require support drivers specific to your operating system Supported operating systems include Linux Windows and VxWorks Acromag provides an engineering design kit for the XMC products sold separately a must buy for first time 7 series module purchasers The design kit model XMC 7KA EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files The 7 series modules are intended for users fluent in the use of Xilinx FPGA design tools Acromag provides software products sold separately to facilitate the development of Windows applications interfacing with Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCI I O Cards This software model PCISW API WI consists of low level drivers
59. ector with spring latch at one end and a 36 position CHAMP 0 8mm plug connector with screw latch at the other end The cable length is 2 meters 6 56 feet Specifications Voltage wieza ette etus 30VAC Current erede terret eet 1 5 Amperes for single circuit 0 5 amperes at 10 C 0 3 Ampere 10096 energized per Champ 0 8mm Connector Operating Temperature Range 40 C to 85 C Lenigthi eoe entere Cete erroe ntes 2m 6 56 feet CABLE MADISON CABLE CORP SCREW LATCH 50KBK00004 OR 50KBK00012 OR 50KBK00013 OR PIN 50 HITACHI CABLE MANCHESTER 48711 50 SCSI 2 PLUG CONNECTOR TYCO AMP 749111 4 ehe PIN 36 E CHAMP 0 8mm H 4 PLUG CONNECTOR H TYCO AMP 787131 2 PIN 26 E SHIELDED E BACKSHELL E PIN 19 P1 106 www acromag com XMC 7 Series AXM CC F USER S MANUAL SFP Direct Attach Cable Acromag offers a 1 meter cable that connects one SFP port to another SFP port This cable supports speeds up to 10 Gbps The Acromag part number is TAPCABLE1M Specifications Length ict eto ene ds 1m Gender rette tieu Male Male Current rer eere e derer epe 0 5A max per contact teil TE 30V max Shielded etre yes LENGTH SEE CHART SEEN ERE TT 11 26 SEE DETAIL 1 s PAD 20 DETAIL 1 PAD 1 f SCALE 2 1 WIRING DIAGRAM P1 END P2 END PAD SIG Acromag Inc Tel 248 295 0310 107 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL 1000BASE T Copper SFP Transcei
60. em ID Subsystem Vendor ID 0x7000 XMC 7K325F 0x7001 XMC 7K410F 16D5 0x7002 XMC 7K325AX 0x7003 XMC 7K410AX 0x7004 XMC 7K325CC 0x7005 XMC 7K410CC 0x7006 XMC 7A200 0x7007 XMC 7A200CC 12 l Not Used 13 14 l Reserved 15 Max Lat 15 Maxlat 15 This board is allocated a 4M byte block of memory BARO to access the PCle interrupt I O registers XADC registers and Flash memory The PCle bus decodes 4M bytes for BARO for this memory space This board is also allocated a 16M byte block of memory BAR2 to access DDR3 memory The PCle bus decodes 16M bytes for BAR2 for this memory space BARO MEMORY MAP The BARO memory address space is used to access the PCle interrupt Front Rear and P16 I O registers System Monitor registers and Flash memory Note that the base address for the board BARO in memory space must be added to the addresses shown to properly access these registers Table 8 BARO Registers BARO Base Address Size Description 0x0000_0000 gt 0x0000_7FFF 32K Reserved AXM Module see specific AXM 0x0000_8000 gt 0x0000_8FFF 4K model user s manual for additional address detail 0x0000_9000 gt 0x0009_FFFF 604K Reserved 0x000A_0000 gt 0x000A_FFFF 64K CDMA see PGO034 0x000B_0000 gt 0x000E_FFFF 256K Reserved PCle AXI Bridge Control see PG054 Interrupt Controller see PG099 0x0011_0000 gt 0x002F_FFFF 1M Reserved XADC System Mo
61. er at base address plus 0x330008 48 www acromag com XMC 7 Series AXM CC F USER S MANUAL This rear input data register is a read only register Channel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels The rear I O can also be configured as differential channels with 2 global clock signal pairs Table 40 BARO Rear Input Data Register Read Only BARO 0x330000 Register Bit Channel VHDL Name Schematic Name 0 0 Rio Bon GCLK P o o o1 ORE BOL P 2 R Roi 3 R 3 Rios A fRifa Roi 5 R5 RIOS E R 6 X Bo 7 ORE Bo 8 R8 Bos 9 R 9 Bos 10 10 Rigo Bon 11 11 RW Bot 12 12 fRifio RIO22 13 13 fRif13 RIO13 14 14 Raa RIO14 15 15 aus RIO15 16 16 bei RIO16 17 17 Ria Bo 18 18 aus Bois 19 19 mi 19 RIO19 20 20 Jup fRIO20 21 21 fRif21 RIO21 22 22 qm 22 RIO22 23 23 _ fRif23 RIO23 24 24 Ja RIO24 25 25 Del RIO25 26 26 269 RIO26 27 27 R7 RIO27 28 28 ag RIO28 29 29 ag RIO29 30 30 Rio _ fIO30 31 31 RI 31 RIO31 GCLK P v oo Y O1 w E vo jujojojojo o u vojojfojojojojojojojojojojfojojojojojo o u o Note that any registers bits not mentioned will remain at the default value logic low P4 Rear Output Data Registe
62. flash device is organized as eight 64 Mbit partitions See Table 31 below Each partition contains 32 Blocks Each block contains 256K bytes The FPGA bitstream occupies partitions O and 1 XMC 7A200 CC models are 42 www acromag com XMC 7 Series AXM CC F USER S MANUAL delivered with a duplicate copy of the FPGA example bitstream stored in partitions 2 and 3 The flash memory is a 16 bit device it does not support single byte accesses Note The Flash memory includes One Time Programmable OTP blocks Acromag writes the protection bits for these Acromag Inc Tel 248 295 0310 blocks during factory programming to disable this feature Table 31 Flash Memory Map Read Write BARO 0x60000000 Partition Block Address Range word addresses 7 255 63FCO0000 63FFFFFF 224 63800000 6383FFFF 6 223 637C0000 637FFFFF 192 63000000 6303FFFF 5 191 62FC0000 62FFFFFF 160 62800000 6283FFFF 4 159 627C0000 627FFFFF 128 62000000 6203FFFF 3 127 61FC0000 61FFFFFF MES 61800000 6183FFFF 2 617C0000 617FFFFF MOS 61000000 6103FFFF 1 63 60FC0000 GOFFFFFF 43 www acromag com XMC 7 Series AXM CC F USER S MANUAL Partition Block Address Range word addresses 60800000 6083FFFF 0 607C0000 607FFFFF 0 60000000 6003FFFF Write Protected Bitstream XMC 7A200 CC Models only Acromag Inc Tel 248 295 0310 XMC 7A200 CC Modes are shipped from the factory w
63. gisters The host processor cannot directly access FLASH memory this must be done using the CDMA AURORA ONT STAT GIO LO AS IN 3 GPI LO AS OUT AXI GPIO Figure 6 Block Diagram Top Level The hierarchical block named CDMA Central Direct Memory Access shown in Figure 7 includes two sub blocks axi cdma O and axi interconnect The AXI interconnect expands the M AXI interface to allow it to transfer data to and from the three slave devices DDR3 memory Flash memory and the PCle bridge control registers The CDMA controller is configured to support scatter gather The scatter gather master interface can only access DDR3 memory CDMA M AXI CDMA SG MEM Figure 7 Block Diagram CDMA Acromag Inc Tel 248 295 0310 59 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The hierarchical block named PCIe PCI Express shown in Figure 8 includes the axi pcie axi intc and three interconnect blocks The AXI slave interface entering the block from the left comes from the CDMA controller Axi interconnect 2 expands the CDMA master interface to two master interfaces to allow the CDMA controller to transfer data to and from both the PCle control registers in the PCle interface and host memory through the PCle bridge Axi interconnect 1 expands the axi pcie S AXI CTL slave interface to two slave interfaces to allow reads writes from both the CDMA controller and the axi pcie master The latter allows the host processor to read
64. guration register at BARO OXF020C must be written with the least significant 32 bits of the address in system memory to which the DMA transfer is to read or write An example of the c code used to set this register with the physical address is shown below Example C code define AXIZPCIeBAR OU DWORD u64BaseAddress 0xF0208 Hdefine AXI2PCleBAR_OL DWORD u64BaseAddress 0xF020C iStatus PCle7K_DmaGetBuffPhysAddress iHandle amp u64PhyAddr AXI2PCleBAR_OU DWORD u64PhyAddr gt gt 32 AXI2PCleBAR_OL DWORD u64PhyAddr amp Oxffffffff This sets the system memory physical address which will be appended with the values written into either the DMA source or destination registers at 0xA0018 or OxA0020 respectively See the example in the CDMA section for additional details The Aurora Status register is used to monitor eight Aurora loopback lanes that are on the P16 connector The XMC module must be installed on a carrier that has a P16 loopback cable connected to enable the channels to connect This Aurora Monitor register is accessed at base address plus 0x340000 The Aurora Monitor register bit O is used take the Aurora link into and out of reset Set to logic 1 the link is held in reset and set to logic 0 the link is removed from reset 41 WWW acromag com XMC 7 Series AXM CC F Control Register Flash Memory Acromag Inc Tel 248 295 0310 USER S MANUAL Table 29 Aurora Status Register Rea
65. hat additional source files exist at lower levels in the hierarchy that are not shown Acromag Inc Tel 248 295 0310 63 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL zm ma ot AE Messages 1 4 warninas GC Design Sources 33 Eh da system top STRUCTURE system top vhd 2 Ode system system system bd 1 CAR system STRUCTURE system vhd 12 ZF AURORA_CNTL_STAT system axi gpio 0 3 system axi apio 0 3 xci Ob CDMA CDMA imp 18J058S STRUCTURE system vhd 2 H E DDR3 Memory DDR3 Memory imp 9MYWN STRUCTURE system vhd 6 ah Ethernet Ethernet imp AGBREI STRUCTURE system vhd 4 GF axi_ethernet_0 system axi ethernet 0 0 system axi ethernet 0 Dach Za ethernet 0 dma system axi ethernet 0 dma 0 system axi ethernet 0 dma 0 xcd EN axi ethernet 1 system axi ethernet 1 0 system axi ethernet 1 0 xd Za ethernet 1 dma system axi ethernet 1 dma 0 system axi ethernet 1 dma 0 xd H FLASH Memory FLASH Memory imp JXFHRU STRUCTURE system vhd 3 LF FRONT IO system axi gpio D 4 system axi gpio D 4 xci 4FP16_1O system axi gpio 0 2 system a apio 0 2 xdi B PCIe PCIe imp 1EUS8M3 STRUCTURE system vhd 8 ER hh Host Peripherals system axi interconnect D 1 STRUCTURE system vhd 11 ka intc 1 system axi intc 1 0 system axi intc 1 0 xci hal pe D system axi pde 0 0 system axi pde 0 Dech oF proc sys reset 1 system proc sys reset 1 O0 system_proc_sys_reset_1_0 xci LF xiconstant_
66. he FPGA MGT clock input pins C8 and C7 AG16 and AH16 of Artix The signal names are CLK156 P and CLK156 N A 1 8V LVCMOS 80 MHz oscillator U13 is wired to the FPGA EMCCLK clock input at pin R24 Y26 Artix This oscillator provides the timing for fast parallel loading of the FPGA bitstream from flash memory on power up The XMC 7 series modules provide access to up to 16 MGTs e Eight of the MGTs are wired to the PCle x8 Endpoint P15 XMC connector e Eight of the MGTs are wired to the P16 XMC connector The example design implements dual 4 lane Aurora interfaces connected to the eight transceivers The F Models provide access to 14 of the 16 MGTs e Eight of the MGTs are wired to the PCle x8 Endpoint P15 XMC connector e Four of the MGTs are wired to the P16 XMC connector The example design implements dual 2 lane Aurora interfaces 53 www acromag com XMC 7 Series AXM CC F 32MB Linear BPI Flash JTAG Port Encryption Key Storage Power System Devices Acromag Inc Tel 248 295 0310 USER S MANUAL e Two of the MGTs are wired to SFP ports The example design implements a 1000 BaseX Ethernet interface on each SFP port A Linear BPI FLASH memory provides 64 megabytes of non volatile storage that is used for FPGA configuration and MicroBlaze program code or data storage The FLASH device is Micron part number PC28F512G18F The lower 16 megabytes of memory space are dedicated to storage of the FPGA bitstream
67. his bit is fixed to 1 and always read as 1 when Scatter Gather is included If the CDMA is built with Scatter 1 Gather disabled Simple Mode Only the default value of the port is O _0__ Tail Pointer Mode is Disabled Tail Pointer Mode is Enabled Soft reset control for the AXI CDMA core Setting this bit to a 1 causes the AXI CDMA to be reset Reset is accomplished gracefully Committed AXI4 transfers are then completed 0 2 Other queued transfers are flushed After completion of a soft reset all registers and bits are in the Reset State Ea Reset Not in Progress Acromag Inc Tel 248 295 0310 30 www acromag com XMC 7 Series AXM CC F USER S MANUAL Bit s FUNCTION Reset in Progress This bit controls the transfer mode of the CDMA Setting this bit to a 1 causes the AXI CDMA to operate in a Scatter Gather mode Note This bit must only be changed when the CDMA engine is IDLE CDMA Status bit 1 1 Changing the state of this bit at any other time has undefined results Note This bit must be set to a O then back to 1 by the software application to force the CDMA Scatter Gather engine to use a new value written to the CDMA Current Descriptor Pointer register Note This bit must be set prior to setting Bit 13 of this CDMA Control register o Simple DMA Mode Scatter Gather Mode 11 4 Reserved Interrupt on Complete Interrupt Enable When set to 1 it allows an interrupt after completed DMA
68. if the system buffer physical address OxS6ABCDEF were given then the AXI Base Address Translation Configuration registers at BARO 0xF0208 and OxFO20C must be set to 0x0 and 0x56 ABCDEF respectively The least significant 24 bits of this address OxS6ABCDEF must be removed and added to the AXI BARO Aperture Base address The new AXI address is 0x01000000 OxOOABCDEF OxO1ABCDEF These values are then appended by the PCle AXI bridge to give the final PCle address of the system memory location Final PCle Address Ox56ABCDEF Intermediate Address OxABCDEF The PCle AXI Bridge is an interface between the AXI bus and the PCle This bridge provides the address translation between the AXI4 memory mapped embedded system and the PCle system The AXI Bridge for PCle translates the AXI memory read or writes to PCle Transaction Layer Packets TLP 39 www acromag com XMC 7 Series AXM CC F USER S MANUAL packets and translates PCle memory read and write request TLP packets to AXI interface commands Table 27 PCle AXI Bridge Control Registers BARO Base Addr Bit s Description oi 31 0 See Xilinx pg055 Memory Map 0x000F0144 31 0 PHY Status Control Register Geh 31 0 See Xilinx pg055 Memory Map 0x000F0208 31 0 TWO IN E ES oai mm 2 ore my SE See Xilinx pg055 Memory Map PHY Status Control Register This register provides the status of the current PHY state as well as control of speed
69. imp JXFHRU STRUCTURE system vhd 2 iFP16 IO system axi gpio D 2 system axi apio 0 2 xci wb PCIe PCIe imp 1EU98M3 STRUCTURE system vhd 8 AF REAR_IO system axi gpio D 1 system axi apio D 1 xcd F xlconcat_0 system xlconcat D D system xlconcst D 0 xci E o Linen 8bi0b i aurora 8bi0b D exdes MAPPED aurora 8bi0b D exdes vhd 12 H 6 Configuration Files 2 H 6 IP Update Log 11 E 4 Constraints 5 i ch 1 constrs AXM A75 3 100000000 i XMC 7KxxxAX timing xdc Bh AXM_A75_timing xdc target e constrs AXM Dxx 3 active J debug xdc target Du XMC 7KxxxAX physical xdc XMC 7KxxxAX_timing xdc a Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order Figure 5 Design Sources Hierarchy The top level block diagram of the example design is shown in Figure 6 below This view has reduced detail showing only the AXI interfaces between blocks and interfaces to external I Os For more detail on AXI bus see UG761 Blocks with a dark background color include lower level blocks which are expanded and shown in the following paragraphs The PCle interface provides the path through which the host processor communicates with the XMC module peripherals This diagram shows that the host processor can directly access DDR3 Acromag Inc Tel 248 295 0310 58 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL memory REAR IO P16 IO AURORA CNTL STAT and CDMA re
70. ined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCle bus memory and configuration spaces The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCle card As a Plug and Play card the board s base address and system interrupt request are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCle bus configuration access is used to read write the PCle card s configuration registers When the computer is first powered up the computer s system configuration software scans the PCle bus to determine what PCle devices are present The software also determines the configuration requirements of the PCle card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address 21 www acromag com XMC 7 Series AXM CC F CONFIGURATION REGISTERS Acromag Inc Tel 248 295 0310 USER S MANUAL Since this board is not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space The configuration registers are also used to indicate that the board requires an interrupt request The s
71. interfaces in a chip to chip loopback implementation Features supported on F models e P16 High Speed Interface Four high speed serial lanes are allocated to the XMC P16 connector on the F model These lanes can be used for Serial RapidlO PCle or Xilinx Aurora The example design supports a pair of two lane Aurora interfaces in a chip to chip loopback implementation Acromag Inc Tel 248 295 0310 11 www acromag com XMC 7 Series AXM CC F PCle Interface Features Software ENGINEERING DESIGN KIT Windows Acromag Inc Tel 248 295 0310 USER S MANUAL e Interface to Front I O Connector The FPGA is directly connected to a front I O connector All 2 5 Volt I O standards supported by the Xilinx 7 series devices are available on 13 signal pairs A JTAG port is included for configuration and for use with the Xilinx ChipScope FPGA debugger The USB UART interface provides a COMM port device for the host processor to connect to the MicroBlaze UART e Example Design Provided The example design includes implementation of the DDR3 memory PCle bus 8 lane Gen 1 control of digital front and rear I O and 1 Gig Ethernet 1000 X interface to the SFP modules e PCIe Bus The example design includes a PCI Express Generation 1 interface operating at a bus speed of 2 5 Gbps per lane per direction On Kintex based models eight lanes are supported Artix models support 4 lanes Maximum payload size is 1024 bytes Up to 4 GBytes s
72. ion _0__ No Scatter Gather Slave Errors Scatter Gather Slave Error CDMA Engine halts Scatter Gather Decode Error This bit indicates that an AXI decode error has been received by the Scatter Gather Engine during an AXI transfer transfer descriptor read or write This error occurs if the Scatter Gather Engine issues an address that does not have a mapping assignment to a slave device 10 This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition O No Scatter Gather Decode Errors Scatter Gather Decode Error CDMA Engine halts 11 Reserved Interrupt on Complete When set to 1 this bit indicates an interrupt event has been generated on completion of a DMA transfer either a Simple or Scatter Gather If the Interrupt on Complete bit 12 of the CDMA Control register 1 an interrupt is generated from the AXI CDMA A CPU write of 1 clears this bit to O Note When operating in Scatter Gather mode the criteria specified by the interrupt threshold must also be met 0 No IOC Interrupt IOC Interrupt active Interrupt on Delay When set to 1 this bit indicates an interrupt event has been generated on a delay timer time out If the Interrupt on Delay Timer bit 13 of the CDMA Control 13 register 1 an interrupt is generated from the AXI CDMA A CPU write of 1 clears this bit to O
73. ion Files 2 H IP Update Log 11 AG Constraints 1 4 Simulation Sources 1 IP Sources Libraries Compile Order 85 www acromag com XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 USER S MANUAL Double click on the XMC 7KxxxAX xdc constraints file to open it a Z mc ati ae B Design Sources 15 EPA system top STRUCTURE system_top vhd 3 CS AXM AXM_Dxx STRUCTURE AXM_Dxx vhd 6 Ai system i system system bd 1 H 4Maurora_8b10b i aurora_8b10b_0_exdes MAPPED aurora amp H Text 1 4 3 Configuration Files 2 B P Update Log 11 EJ f5 Constraints 1 Ere constrs 1 1 E MC 7KxxxAX xdc target 4 Simulation Sources 1 4 Hierarchy IP Sources Libraries Compile Order To change the single ended signal names to differential signal names rename all of the signals labeled RO to RIO P in lines 194 to 323 Rename all of 86 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL the signals labeled RI to RIO N in lines 194 to 323 only lines 194 thru 213 are shown in figure Acromag Inc Tel 248 295 0310 87 WWW acromag com XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 USER S MANUAL Select lines 194 to 323 Type Cntrl R to open the replace dialog box Select options as shown Click Find Find what RI Replace with RIO N Target Direction G
74. ires an interrupt to be 31 24 generated Timer begins counting when the CDMA is IDLE CDMA Status bit 1 1 This generally occurs when the CDMA has completed all scheduled work defined by the transfer descriptor chain reached the tail pointer and has not satisfied the Interrupt Threshold count Note Setting this value to zero disables the delay timer interrupt CDMA Status Register This register provides status of the AXI CDMA Table 20 CDMA Status Register Read Write BARO 0x000A0004 Bit s FUNCTION This bit is reserved for future definition and will always return zero CDMA Idle Indicates the state of AXI CDMA operations When set and in Simple DMA mode the bit indicates the programmed transfer has completed and the CDMA is waiting for a new transfer to be programmed Writing to the Bytes to Transfer register in Simple DMA mode causes the CDMA to start not Idle 1 When set and in Scatter Gather mode the bit indicates the Scatter Gather Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed Writing to the tail pointer register automatically restarts CDMA Scatter Gather operations 0 Not Idle CDMA is Idle 2 Reserved Scatter Gather Included This bit indicates if the AXI CDMA has been implemented with Scatter Gather support included C SG ENABLE 1 This is used by application software drivers to determine if Scatter Gather
75. ith two copies of the Acromag example design firmware stored in flash memory Each firmware image occupies two partitions The image stored in partitions 2 and 3 is intended to be replaced by the user s custom firmware The image stored in partitions O and 1 is write protected by the example design firmware Table 32 XMC 7A200 CC Flash Memory Map Partitions Address Range word addresses 6 7 Available for user data storage 4 5 Not accessible 2 3 User Bitstream 0 1 Golden Bitstream This write protected image can be relied upon to always configure the FGPA with a functioning PCI express interface that will allow the host to overwrite the customer s firmware stored in the second two partitions Switch SW1 position 4 selects the bitstream that will be loaded into the FPGA after the next power cycle Switch SW1 position 4 in the on state selects the write protected golden configuration bitstream SW1 position 4 in the off state selects the user modifiable configuration bitstream Note With SW1 position 4 in the off state and flash address line A23 unconditionally driven high as is done in the Acromag example design partitions 4 and 5 of the flash memory are not accessible The golden bitstream can be overwritten by placing SW1 position 4 in the on state and writing the flash via the Xilinx Platform USB II cable The user configuration bitstream stored in partitions 2 and 3 can also 44 WWW acromag com XMC 7 Series AXM
76. l is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc 1 RELATED PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the board and the Xilinx Vivado development environment Kintex 7 FPGAs Data Sheet DC and AC Switching Characteristics ds182 7 Series FPGAs Memory Resources User Guide ug473 7 Series FPGAs Configurable Logic Block User Guide ug474 7 Series FPGAs SelectlO Resources User Guide ug471 7 Series FPGAs Clocking Resources User Guide ug472 7 Series DSP48E1 Slice User Guide ug479 7 Series FPGAs GTX GTH Transceivers User Guide ug476 7 Series FPGAs Integrated Block for PCI Express v3 0 Product Guide pg054 Zynq 7000 AP SoC and 7 Series Devices Memory Interface Solutions v2 3 User ug586 Guide Vivado Design Suite Tutorial Design Flows Overview ug888 Vivado Design Suite Tutorial Designing IP Subsystems Using IP Integrator ug995 AXI Reference Guide ug761 Methods for Integrating AXIA based IP Using Vivado IP Integ
77. le 17 Master Enable Register Read Write BARO 0x0010001C Bit s FUNCTION Master IRQ Enable 0 I dE All Interrupts Disabled All Interrupts Enabled Hardware Interrupt Enable 1 EE Software Interrupts Enabled Hardware Interrupts Only Enabled 31 2 Not Used bits are read as logic 0 The AXI Central Direct Memory Access CDMA core is a soft Xilinx Intellectual Property core The CDMA provides direct memory access between system memory over the PCle bus and the memory resident on the XMC 7 series module The basic mode of operation for the CDMA is Simple DMA In this mode the CDMA executes one programmed DMA command and then stops This requires that the CDMA registers need to be set up by system software over the PCle bus for each DMA operation required Scatter Gather is a mechanism that allows for automated DMA transfer scheduling via a pre programmed instruction list of transfer descriptors Scatter Gather Transfer Descriptor Definition This instruction list is programmed by the user software application into a memory resident data structure that must be accessible by the AXI CDMA Scatter Gather interface This list of instructions is organized into what is referred to as a transfer descriptor chain Each descriptor has an address pointer to the next descriptor to be processed The last descriptor in the chain generally points back to the first descriptor in the chain but it is not required The AXI CDMA T
78. lobal Forward Selected text Backward Match case 8 Entire Scope Match whole word From Cursor Use Regular Expressions Wildcards And then click All eplace 88 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Result after editing Select Save File from the File menu or type Cntrl S to save the changes Compile the Design Compile the design by selecting the appropriate Design Run for the installed AXM module For this example select the Dxx AXM module design run by right clicking on impl_7K325AX_Dxx and then choosing launch runs from the pop up menu Constraints WNS TNS WHS THS TPWS FailedRoutes LUT FF BRAM DSP constrs D 0 18 0 00 0 04 0 00 0 00 constrs AXM A75 evi constrs_AXM_A75 0 11 0 00 0 04 0 00 0 00 14 ov synth_7K325AX_Dxx active constrs AXM Dxx f impl 7K325AX Dxx active constrs AXM Do 0 15 0 00 0 04 0 00 Acromag Inc Tel 248 295 0310 89 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The following dialog box appears Click OK 60 Default Launch Directory gt 9 Launch runs on local host Number of jobs Generate scripts only Make Active Run Runs to Launch 1 There is no netlist available OK to launch synthesis first Implementation will automatically start when synthesis completes CC Care Acromag Inc Tel 248 295 0310 90 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Generate Bitstrea
79. m When the synthesis and implementation steps are complete Vivado displays the following dialog box Click OK to proceed with generating the bitstream Implementation Completed DS o Implementation successfully completed Next C Open Implemented Design Q Generate Bitstream C View Reports F Don t show this dialog again L When bitstream generation is complete the following dialog box is displayed Click on the OK button if you want to view implementation details otherwise click on the Cancel button and proceed to the next step Bitstream Generation Completed o Bitstream Generation successfully completed Next Don t show this dialog again L jJ The flash image mcs file will be created in the implementation directory for the current run The flash image file will eventually be loaded into Flash memory For this example the file C XMC 7K325A_MOD XMC 7K325AX runs impl_7K325AX_Dxx 7K325AX mcs will be created If a Xilinx programming adapter is attached to a powered XMC 7K325AX board through a JTAG connection then the Flash can be programmed at this Acromag Inc Tel 248 295 0310 91 www acromag com XMC 7 Series AXM CC F USER S MANUAL time The Flash can also be programmed from the host PC over the PCle bus if the Acromag example firmware is currently loaded in the FPGA Skip to next step Select Open Hardware Manager under Program and Debug in the Flow Naviga
80. m XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 Table 44 Power Distribution USER S MANUAL www acromag com Reference T Power Rail Power Device Designator Description Volts m LTM4601 U14 FPGA VCCINT 1 0 12 0A LTM8023 U15 AXM module power 5 0 2 0A LTM4615 U19 FPGA VCCO FLASH 1 8 4 0A LTM4615 U19 FPGA VCCO DDR3 1 35 4 0A LTM4615 U19 FPGA VCC AUX 2 0 15A TPS51200 U5 DDR3 VREF 0 675V 3 A TPS51200 U5 DDR3 Termination 0 675V 3 A LTC3022 U18 FPGA VCCO 2 5 1 5A LTM4615 U17 FPGA MGTAVCC 1 0 4 0A LTM4615 U17 FPGA MGTAVTT 1 2 4 0A LTM4615 U17 FPGA MGTVCCAUX 1 8 1 5A TPS77015 U13 FPGA BBRAM 1 5V 0 05 A 55 XMC 7 Series AXM CC F System Monitor Acromag Inc Tel 248 295 0310 USER S MANUAL 1 0V pA 5 0V gt P15 U14 XMCVPWR 3 5 12 LTM4601 PIS U15 gt XMC 12V LTM8023 P15 XMC 3 3V 3 3V LTM4615 0 675V U5 0 675V TPS51200 U18 2 5V LTC3022 U17 1 0V IM 1 2V A 1 8V LTM4615 P15 U7 LSM Wars d TPS77015 AUX Figure 4 Power Distribution The System Monitor provides status information for the 7 series device The system monitor is located in the center of the FPGA die The System Monitor function is built around dual 12 bit 1 megasamples per second Analog to Digital Converter The
81. memory over the PCle bus The on board Flash memory loaded with configuration data allows automatic configuration of the FPGA on power up Acromag Inc Tel 248 295 0310 6 www acromag com XMC 7 Series AXM CC F USER S MANUAL These modules include the following interfaces Four or eight high speed serial lanes are allocated to the XMC P15 connector These lanes can be used for PCle PCI Express Serial RapidlO or 10 Gigabit Ethernet The example design will support a four or eight lane Gen 1 PCle implementation with one DMA channel for data transfer between the PCle bus and on board DDR3 memory Eight four on XMC xxxF models high speed serial lanes are also allocated to the XMC P16 connector These serial lanes can be used for Serial RapidlO PCle Gigabit Ethernet XAUI or Xilinx Aurora The example design will support dual Aurora interfaces for use of these lanes Two global clocks and 34 select I O signals will also be provided on the P16 connector Select I O signals are 2 5V I O pins that can be selected from single ended I O standards LVCMOS HSTL and SSTL and differential UO standards LVDS HT LVPECL BLVDS Differential HSTL and SSTL The P4 rear I O connector will provide two global clock differential pairs and 30 LVDS signal pairs The board features 128 Meg x 64 bit DDR3 SDRAM and 32 Meg x 16 bit parallel Flash The parallel Flash provides storage for both the FPGA configuration data and MicroBlaze CPU program storage
82. mm introut In6 microblaze_0_xlconcat microblaze 1 axi intc AXI Interrupt Controller AXI Interconnect M01 AXI gt M02 AXI gt M AXI MB FLASH gt M06 AXI INTERRUPT LMB Rst 0 0 D z Micro3laze Acromag Inc Tel 248 295 0310 MicroBlaze Figure 17 Block Diagram Microblaze 1 68 nc gt ENET1_IIC iiezinte_irpt 9po 3 0 gt ENET 1_gpo 3 0 _AXI_DC AXI IC WWW acromag com XMC 7 Series AXM CC F USER S MANUAL 7 XMC 7KxxxF Software The XMC 7KxxxF models include two MicroBlaze processors that manage the TCP IP stacks in the example design This section describes the embedded system software There are two Ethernet ports on the board Each port has an associated DMA controller and MicroBlaze processor The Vivado project folder contains an SDK project subfolder for the embedded system named XMC 7KxxxF sdk There are four projects in the workspace two for each MicroBlaze processor The projects named srec bootloader O and srec bootloader 1 are small programs that are included in the FPGA configuration bitstream and are loaded into block RAMs during FPGA configuration The purpose of the srec bootloader is to copy the larger program EchoServer from flash memory to DDR3 SDRAM and start execution of the EchoServer program The EchoServer is a simple program that will echo ICMP packets received from a P
83. mory xadc wiz 0 s axi lite Reg 0x0030_0000 64K v 0x0030_FFFF a P16 IO S AXI Reg 0x0032 0000 64K v 0x0032 FFFF REAR IO S AXI Reg 0x0033 0000 64K v 0x0033 FFFF x AURORA CNTL STAT S AXI Reg 0x0034 0000 64K v 0x0034 FFFF DDR3 Memory mig 7series 0 S AXI memaddr 0x8000 0000 1G xBFFF FFFF Table 45 XMC 7KxxxAX Address Map XMC 7KxxxF Models Block Diagram The hierarchy of the F Model example design is shown in Figure 12 below Figure 12 is a screen clipping from the Hierarchy tab of the Sources pane in the Vivado development environment The example design consists of a combination of VHDL source files and a Xilinx Vivado IP Integrator block diagram Atthe highest level of the hierarchy is the system top VHDL source file shown in the figure with the least levels of indentation This top level module instantiates the following three lower level modules AXM_Dxx system and aurora 8b 10b O exdes AXM_Dxx is the top of the hierarchy used to instantiate any of Acromag s digital AXM modules System is the Vivado IP Integrator block diagram source where the majority of the example design logic is located aurora 8b 10b O exdes is the wrapper for the Xilinx IP Core Generator generated example design for Aurora The IP Integrator block diagram labeled system is compiled to produce a lower level hierarchy of VHDL source files that are shown beneath system The symbol to the left of each of the labeled subsystems indicates t
84. n power is removed m Yes No Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 64Mbyte m Yes Storage of Code for Clear Flash memory No FPGA by erasing all sectors of the Flash Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize One Time Programmable 272 bytes Yes The OTP area has Not applicable area in flash device m No been disabled by writing the lock registers with zeroes Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 512x8 bit Yes Storage of Code for Not applicable m No IPMI Interface Device Acromag Representative Name Title Russ Nieves Dir of Sales and Marketing Email rnieves Qacromag com Office Phone 248 295 0823 Office Fax 248 624 9234 Acromag Inc Tel 248 295 0310 105 www acromag com XMC 7 Series AXM CC F 11 Accessories USER S MANUAL XMC 7K325F and XMC 7K410F Accessories VHDCI Cable SHIELDED BACKSHELL TYCO AMP 749889 3 Acromag Inc Tel 248 295 0310 Acromag offers a cable that brings the 36 pins of the VHDCI front I O connector out to a 50 pin SCSI 2 connector The Acromag part number is 5025 921 See Table 5 Front VHDCI Field I O Pin Connections The cable assembly uses a 25 paired round shielded jacketed flat cable 50 conductors total with a 50 position SCSI 2 male conn
85. nitor see DS790 0x000F_0000 gt 0x000F_FFFF 64K 0x0010_0000 gt 0x0010_FFFF 64K 0x0030_0000 gt 0x0030_FFFF 64K Acromag Inc Tel 248 295 0310 23 www acromag com XMC 7 Series AXM CC F USER S MANUAL BARO Base Address Size Description P1 Front I O AXI GPIO 0x0031_0000 gt 0x0031_FFFF 64K XMC 7KxxxF models see PG144 0x0032_0000 gt 0x0032_FFFF 64K P16 I O AXI GPIO see PG144 PA Rear I O AXI_GPIO see PG144 Aurora Control Status AX _GPIO see PG144 0x0035 0000 0x00FF FEEF 12M Reserved 0x0033_0000 gt 0x0033_FFFF 64K 0x0034_0000 gt 0x0034_FFFF 64K Note that any registers bits not mentioned will remain at the default value logic low CDMA MEMORY MAP The Central Direct Memory Access CDMA controller can access the following devices Flash memory DDR3 memory AXI to PCI bridge BARO and the control registers for the PCle interface Note that the PCle interface cannot directly access Flash memory transfers to and from Flash must be initiated by the CDMA controller The CDMA controller includes the scatter gather function If used the scatter gather descriptor list must be located in DDR3 memory BARO Base Address Size Description 0x0000_0000 gt 0x000E_FFFF 960K Reserved PCle AXI Bridge Control 0x000F_0000 gt 0x000F_FFFF 64K see PGO54 0x0010_0000 gt 0x5
86. on Program K Main Menu 1 Demo instructions 2 Locate Choose board 79 Exit Enter selection 2 1 7K325AX 2 7K325F 3 7K41BAX 4 7K410F Select board to open 1 7K3258X board lt s gt found K325AR board opened Is the FPGA configured with an ficromag example design Y N Enter the appropriate selection for the AXM module you have attached For this example 4 was entered to indicate an EDK AXM module is attached Answer N to the question Is AXM D02 D03 D04 or EDK mezzanine attached Select function 6 to choose Flash commands r we we w w a G AXMC Kintex7 Windows filesiXMC n indie filesic r examples PCle7K mecie 2010 x64 R EJ 4 ficromag example design for 7K3258X with AXM DG2 DB3 DB4 or EDK 5 ficromag example design for 7K325808 with AXM DX03 6 ficronag teg x design for 7K32588 with Front I O Enter selection Is ARXM D62 D83 104 or EDK mezzanine module attached Y N N la Demo instructions Locate Choose board d Interrupt Configuration w Raw memory access Uiew status information N Flash commands Li N Example Design DDR3 memory menu DMA transfers Rear 1 0 menu HR P16 1 0 menu Display PCI configuration registers 99 Exit Enter selection Ee Acromag Inc Tel 248 295 0310 98 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Read the warning and then hit any key E we we EE ww 8 GNXMC Kintex7 Window
87. onfigurations MODELS FPGA OPERATING TEMPERATURE RANGE XMC 7A200 Artix 7 XC7A200T 40 C to 55 C 500 LFM airflow XMC 7A200CC Artix 7 XC7A200T 40 C to 475 C cold plate XMC 7K325AX Kintex 7 XC7K325T 40 C to 45 C 500 LEM airflow XMC 7K410AX Kintex 7 XC7K410T 40 C to 40 C 500 LEM airflow XMC 7K325CC Kintex 7 XC7K325T 40 C to 70 C cold plate XMC 7K410CC Kintex 7 XC7K410T 40 C to 70 C cold plate XMC 7K325F Kintex 7 XC7K325T 40 C to 55 C 500 LFM airflow XMC 7K410F Kintex 7 XC7K410T 40 C to 55 C 500 LFM airflow 1 Tested on Acromag VPX4820 carrier with 500 LFM airflow Tested on Acromag VPX4820 CC carrier with thermal interface material Berquist Gap Pad 1500R between the carrier cold plate and the XMC module heatsink 3 Tested on Acromag VPX4820 CC carrier with thermal interface material Berquist Gap Pad 1500R between the carrier cold plate and the XMC module heatsink Tested on Acromag VPX4820 CC carrier with thermal interface material Berquist Gap Pad 1500R between the carrier cold plate and the XMC module heatsink Acromag Inc Tel 248 295 0310 www acromag com XMC 7 Series AXM CC F USER S MANUAL Po I I I I I I I I I I I I 1 I I I I I I I i 44 LVDS Pairs 2 Global Clock Pairs m
88. ow Voltage Differential Signaling in the user constraints file The 2 5 volt I O standards available are listed in the Kintex 7 User Guide available from Xilinx Table 5 Front VHDCI Field UO Pin Connections Ch mo B es TK 4 FIOO_N FIO1_P 5 FIO1_N O 1 CECR TN IZA s pose p Fon a Fop b Fon 5 Fose b hey por A 7 FIO7_P FIO7_N 29 Acromag Inc Tel 248 295 0310 18 www acromag com XMC 7 Series AXM CC F USER S MANUAL Ch Positive Pin Pin Negative Pin Pin s pog 20 Fon o Foor box 10 poi p Foi 1 ouer hs boer 1j fior sake hs fior sakn Us p Les USB_VBUS from host hs GND 36 The example design implements 2 5volt LVCMOS I O at the front connector Alternatively 2 5volt LVDS I O can be used on the front connector This connector is a 36 pin female receptacle header SAMTEC VHDCR 36 01 M RA or equivalent which mates to the male connector SFP Module Connectors XMC 7K325 and XMC 7K410F models Table 6 SFP Module Pin Connections Pin Symbol Pin Description 1 VeeT Module Transmitter Ground 2 x_Fault Module Transmitter Fault 3 ransmitter Disable 4 SDA 2 wire Serial Interface Data Line 5 SCL 2 wire Serial Interface Clock 6 Mod_ABS Module Absent 7 RSO Rate Select 8 Rx LOS Receive Loss of Signal Indication 9 VeeR Module Receiver Ground 10 VeeR Module Receiver Ground 11 VeeR Module Receiver Ground 12 RD
89. r The rear output data register is used to access the individual LVCMOS output channels This includes 32 single ended channels Each channel is controlled by a corresponding data bit as shown in Table 41 Acromag Inc Tel 248 295 0310 49 WWW acromag com XMC 7 Series AXM CC F P16 Input Data Register Acromag Inc Tel 248 295 0310 USER S MANUAL This rear output data register is a read writable register Channel operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as output channels Table 41 BARO Rear Output Data Register Read Write BARO 0x330008 Register Bit e e B B foo JN jo un w w o WININININININ INININ e e e a e iS S OJ oo 1 o ui o N E O lo oo u lo ju w N 31 Channel HDL Name Schematic Name RIOO M 1 1 ofi Ro 2 Roo Rio2 3 RoB JOS 4 RO R04 5 Ro JOS 6 po Bos 7 Row JO 8 Pos Rios lg RIO9 so Rogo oun 11 Roui Rion 12 Ro 2 Bo 13 fo 3 Rios 14 _ Roga Rion 15 fo 5 Rio15 16 fo 1i6 fIO16 17 Roa Rion 18 boug fIO18 19 _ fo 19 Riog 20 foo fiIo20 21 Rog _ Rioz1 22 kof fI022 23 Ropa 023 24 RoQ4 Rioz4 25 RO 25 RIO25 26 fRo 26 fIO26 27 kRo 7 fI027 28 bo fiIo28 29 Ros Krio29 30 fo 30 Joan 31 RO 31 RIO31 GCLK_N N z z z z z z z z
90. r in the XMC 7K325 AX folder Acromag Inc Tel 248 295 0310 70 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Modify the Source Files The Sources pane will display the Hierarchy tab as shown below in Figure 19 Click the symbol left of system top STRUCTURE to expand the hierarchy a Tw a G3 GA Design Sources 15 v system top STRUCTURE system_top vhd 3 H Text 1 H 6 Configuration Files 2 H 5 IP Update Log 11 4 Constraints 1 H Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order i LN Templates Figure 19 Vivado Sources Pane Beneath system top are the three components instantiated in system top vhd AXM_Dxx vhd system bd and aurora 8b10b exdes vhd ANM Dxx vhd is a top level wrapper that instantiates the selected Acromag AXM module source This selection is made by passing the appropriate value for the VHDL generic AXM MODULE to system top This is configured by choosing the appropriate Design run which will be explained in a later section Next open the Vivado IP Integrator block design by double clicking on the line system i system system bd 1 Acromag Inc Tel 248 295 0310 71 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL z Seat ae Design Sources 15 BAA system top STRUCTURE system_top vhd 3 A AXM AXM_Dxx STRUCTURE AXM Dxx vhd 6 D system i system system bd 1 G aurora _8b10b_i auror
91. r P4 Field I O Connector eee eee eee aaa aaa aaa aaa enne nens se seen eit n sss asse ense Ennan sensn 16 Front Panel Field I O Connector XMC 7K325F and XMC 7K410F models eee 18 SFP Module Connectors XMC 7K325 and XMC 7K410F model 19 Ethernet MAC IDs XMC 7K325F and XMC 7K410F model 19 Non Isolation Considerations a enne aaa enne aaa enne nnne nets tenen nnne 20 4 PROGRAMMING INFORMATION 20 ciam cy dido 20 ducpweeniieme H 21 PCle CONFIGURATION ADDRESS GSPACE ee ee ae ea ea een aaa aaa aaa aaa aaa tnr innen enn snnt 21 CONFIGURATION REGISTERS me ewa eee ae ea aaa ea aaa aaa aaa aaa nnne initiis aaa aaa aaa aaa stesse nennt 22 BARO MEMORY MAP cionado Z WO SYTA PEP Eet 23 CDMA MEMORY MA Pacino 24 INTERRUPT CONTROLLER qc 24 Interrupt Status Reglster EE 25 Interrupt Pending Register urere a ESEE aane Por bo aX rade C RUP ARE DDR aaa dees 26 Interrupt Enable Register bk 26 Interrupt Acknowledge Register 27 Set Interrupt Enable Register 27 Clear I tertupt Enable Register eiie a didas 28 Acromag Inc Tel 248 295 0310 2 www acromag com XMC 7 Series AXM CC F USER S MANUAL Interrupt Vector Register eee e eet ds ta OKE 28 Master Enable Register Lectt eia E tei ree ee 28 AXIECD MA
92. r Pointer register value Failure to do so results in an undefined operation by the CDMA On error detection the Current Descriptor Pointer register is updated to reflect the descriptor associated with the detected error Note The register should only be written by the Software application when the AXI CDMA is Idle 31 6 Acromag Inc Tel 248 295 0310 35 www acromag com XMC 7 Series AXM CC F USER S MANUAL CDMA Tail Descriptor Pointer Register CDMA Source Address Register Acromag Inc Tel 248 295 0310 This register provides Tail Descriptor Pointer for the AXI CDMA Scatter Gather Descriptor Management Table 22 CDMA Tail Descriptor Pointer Register Read Write BARO 0x000A0010 Bit s FUNCTION Writing to these bits has no effect and they are always read as zeros Tail Descriptor Pointer This register field is written by the software application in Scatter Gather Mode to set the current pause pointer for descriptor chain execution The AXI CDMA Scatter Gather Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer When the AXI CDMA is in Scatter Gather Mode a write by the software application to this register causes the AXI CDMA Scatter Gather Engine to start fetching descriptors starting from the Current Descriptor Pointer register value If the Scatter Gather engine is paused at a tail poin
93. raints file The 2 5 volt I O standards available are listed in the 7 Series FPGAs SelectlO Resources User Guide available from Xilinx Two of the signal pairs BIO GCLK P N and RIO31 CCLK P N are connected to clock capable I O pins on the FPGA These pins provide a direct path to global clock buffers in the FPGA As LVDS signal pairs the signals can be grouped as 32 LVDS I O pairs The LVDS pairs are arranged in the same row in Table 4 For example RIO1 P and RIO1 N form a signal pair The P identifies the Positive input while the N identifies the Negative input Table 4 Rear Field I O Pin Connections Ch Positive Pin Description Pin Negative Pin Description Pin o Rioo sake 1 Bos 3 1 Rore 1 2 korn a 2 Rozp 5 RO2N 7 s por sess 4 op 3 Ron in 5 RIO5_N 12 6 boer 13 Ron e 7 RIO7P 14 RIO7 N 16 8 bor 17 RIOB N 19 9 lose ER kon bo 10 Rioo p 21 RO10 N 23 u Rons 22 Ronn 24 12 Ron 25 DEER 27 Goar s RIO13 N 28 14 Rios P 29 RIO14 N 31 15 Rios P Tan RIO15_N 32 16 boer aa RIO16_N 35 17 Rorre 3a _RIOI7_N 36 18 RO p 37 R18 N 39 19 RO p 38 DEER a0 20 Ro p 41 R20 as 21 Joi P 42 RIO21 N 44 22 bor 45 RIO22 N 47 23 i023 P 46 RIO23 N 48 24 our 49 RIO24 N 51 25 RIO25 P Tag RIO25 N 52 26 RIO26_P 53 J RIO26 N 55 17 WWW acromag com XMC 7 Series AXM CC F USE
94. rator xapp1204 LogiCORE IP AXI GPIO v2 0 Product Guide pg144 Acromag Inc Tel 248 295 0310 5 www acromag com XMC 7 Series AXM CC F USER S MANUAL LogiCORE IP AXI Central Direct Memory Access v4 1 Product Guide for Vivado pg034 Design Suite LogiCORE IP AXI Interconnect v2 1 Product Guide pg059 LogiCORE IP AXI Interrupt Controller INTC v4 1 Product Guide for Vivado Design pg099 Suite LogiCORE IP AXI XADC v1 00a pg019 LogiCORE IP AXI EMC v3 0 Product Guide pg100 LogiCORE IP AXI Bridge for PCI Express v2 5 pg055 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS ug480 Analog to Digital Converter User Guide Clocking Wizard v5 1 LogiCORE IP Product Guide pg065 Zynq 7000 AP SoC and 7 Series Devices Memory Interface Solutions v2 2 ds176 Vivado Design Suite User Guide Embedded Processor Hardware Design ug898 AXI Ethernet Subsystem v6 2 pg138 LogiCORE IP AXI DMA v7 1 pg021 AXI IIC Bus Interface v2 0 pg090 LogiCORE IP AXI UART Lite v2 0 pg142 LogiCORE IP AXI Timer v2 0 pg079 o O o o 3 DDR3L RS 2Gb memory MT41K128M16JT 125IT K Spec Parallel Nor FLASH PC28F512G18FE www micron com ANSI VITA 42 0 2008 standard ANSI VITA 42 3 2006 ANSI VITA 46 0 2007 standard 2 GENERAL INFORMATION The XMC 7 series modules are XMC modules with the heart of the design being a Xilinx 7 series reprogrammable FPGA Re configuration of the FPGA is possible via a direct download into the Flash configuration
95. rite Acceptance Thread ID Width Single Thread S00 AXI D Round Robin 2 2 io S01_AXI 0 Round Robin 2 2 0 S02 AXI D Round Robin ve 2 Mk Z d5S00 AXI Zem AN El 5802 AXI M00 AXI D aclk aresetn Figure 11 AXI Crossbar Slave Interface Settings Acromag Inc Tel 248 295 0310 62 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Table 45 shows a screen clipping from the Address Editor tab of the Block Design view The offset address and block size for each peripheral can be set using this editor This table shows the master interfaces of each peripheral and lists the devices that each can access along with the base addresses 1 Cell Slave Interface Base Name Offset Address Range High Address SE CDMA jaxi_ cdma 0 Data 32 address bits e pce o S AXI CTL CTLO OxOOOF 0000 64K Ox000F FFFF PCle axi_pcie_0 S AXI BARO 0x0100 0000 16M v Ox01FF FFFF FLASH Memory axi emc 0 S AXI MEM MEMO 0x6000 0000 64M v Ox63FF FFFF sa DDR3 Memory ig _ 7series 0 S AXI memaddr 0x8000 0000 1G v OxBFFF FFFF E ga Data SG ress bits 4G DDR3 TS 7series 0 S AXI memaddr 0x8000 0000 1G v OxBFFF FFFF GF PCIe axi pde 0 El M AXI 32 address bits 4G ua MAR 5 cdma 0 S AXI LITE Reg 0x000A 0000 64K v O0x000A FFFF PCIe axi pcie 0 S AXI CTL CTLO 0x000F_0000 64K v 0x000F_FFFF u M AXI AXM M AXI AXM Reg 0x0000 8000 Ka r 0x0000 8FFF PCle axi intc 1 s axi Reg 0x0010 0000 64K 0x0010_FFFF ua DDR3 Me
96. rovides die temperature monitor outputs used by the memory interface to adjust its timing to compensate for temperature dependent timing DDR3 Memory SA PCIE MEM S AXI CDMA SG MEM S AN COMA MEM xadc wiz 0 s axi lite NC ad Hte kee Vp Vn Il pVp Vn XADC Wizard Figure 9 Block Diagram DDR3 Memory Acromag Inc Tel 248 295 0310 60 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Figure 10 shows the expanded view of the MEM AXI interconnect block of Figure 9 Performance tuning can be accomplished by configuring the AXI Crossbar block Double clicking on the xbar block invokes the Re customize IP option in Vivado The Re customize IP dialog is shown in the following paragraph MEM AXI Interconnect Figure 10 MEM AXI Interconnect Acromag Inc Tel 248 295 0310 61 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The Slave Interfaces tab of the AXI Crossbar Re customize dialog box provides the option to choose the arbitration scheme and assign priorities to each of the slave interfaces Other performance tuning options are also available See the Xilinx LogiCORE IP AXI Interconnect Product Guide PGO59 for a detailed description r 7 s AF Re customize IP IC a AXI Crossbar 2 1 A Documentation 5 IP Location E Show disabled ports Component Name DDR3 Memory MEM xbar Master Interfaces Address Connectivity Slave Interface Arbitration Priority Read Acceptance W
97. rrupts Reading the contents of this register indicates the presence or absence of an active interrupt signal that is also enabled Each bit in this register is the logical AND of the bits in the Interrupt Status register and the Interrupt Enable register Table 11 Interrupt Pending Register Read BARO 0x00100004 Bit s FUNCTION 0 hen set indicates an interrupt from the AXM module or Front I O See the appropriate AXM module user s manual for information on the source of this interrupt o Disabled 1 Enabled 1 hen set indicates an AXI CDMA interrupt See the CDMA section for source of this interrupt O0 Disabled 1 Enabled 31 2 Reserved D NA 1 NA Interrupt Enable Register This is a read write register Writing a 1 to a bit in this register enables the corresponding Interrupt Status bit to cause assertion of the interrupt output This Interrupt Enable bit set to 0 does not inhibit an interrupt condition from being captured It will still show up in the Interrupt Status register even when not enabled here To show up in the Interrupt Pending register it needs to be enabled here Writing a O to a bit disables or masks the generation of interrupt output for the corresponding interrupt input signal Note however that disabling an interrupt input is not the same as clearing it Disabling an active interrupt prevents that interrupt from reaching the IRQ output When it is re ena
98. s 2 5 volt LVCMOS I O at the P16 connector Alternatively 2 5 volt LVDS I O can be used on the P16 connector Configured as LVDS signal pairs the signals can be grouped to match the ANSI VITA 46 0 X38s pattern map A total of 19 differential signal pairs are provided 16 on AX models These differential signal pairs connect to column C and F of the P16 XMC connector as shown in Table 3 For example S3 P and S3 N form a signal pair There are two global clock differential pairs available SOG_P SOG_N and S18G_P S18G_N The P identifies the Positive input the N identifies the Negative input The XMC P16 Secondary connector is a 114 pin Samtec ASP 103614 05 connector The connector complies with ANSI VITA 42 3 2006 The rear I O P4 connector connects directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt I O standards The IOSTANDARD attribute can be set in the design constraints file 16 WWW acromag com XMC 7 Series AXM CC F Acromag Inc Tel 248 295 0310 USER S MANUAL XDC The example design configures the rear P4 I O as LVCMOS25 low voltage CMOS in the design constraints file The tables included in the P4 Rear Input Data Register and P4 Rear Output Data Register sections can be used to map the LVCMOS signal to the signal names given in the table below The rear I O can alternatively be configured for LVDS_25 Low Voltage Differential Signaling in the design const
99. s files XMC Kintex7 Windows files c_examples PCle7K msdev_2010 x64 R e Demo instructions Locate Choose board Interrupt Configuration Raw memory access View status information Flash commands N i Example Design 7 DDR3 memory menu 8 DMA transfers 9 Rear 1 0 menu Pi6 1 0 menu 13 Display configuration registers 243 Displ PCI fi i i 79 Exit Enter selection V lecti 6 gt gt gt CAUTION 4444444444444X4X4X4444X4X4444X4X44X4 X 4 N Take care not to inadvertently erase any configuration data stored in flash to continue Type 5 to write the updated bitstream file to Flash we we w w w B GNXMC Kintex7 Windows files XMC Kintex7 Windows files c_examples PCle7K msd lev 2010x64R Wale Enter selection 6 gt gt gt CAUTION 44444444444444X4X4X44X4XXXX4XXX4X444 X 4 Take care not to inadvertently erase any configuration data stored in flash Press any key to continue Flash status address BBBBBBAB gt Ready and no errors Flash status details Clear flash status Read flash data Write flash data Write configuration file to flash Write code file to flash Erase flash block Erase flash chip Compare file to flash Return to main menu er selection Acromag Inc Tel 248 295 0310 99 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Type 6 to choose the new configuration file and then enter C XMC 7K325AX_MOD XMC 7K325
100. s in tri i 2 gt Channel Up ES 473 as in tri i 1 gt 0 474 as in tri i 0 gt GT RESET IN d 475 as out tri o 0 gt GT RESET IN 476 il 477 pl6 in tri i gt P16 SI vs 478 pl6_out_tri_o gt P16 SO 479 sf 480 481 g 482 Vp Vn v n gt Vp Vn v n g 483 Vp_Vn_v_p gt Vp_Vn_v_p 484 ca 1485 Acromag Inc Tel 248 295 0310 83 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Next I O buffers must be added Add the highlighted text rear io tri i gt rear io tri i rear io tri o gt rear io tri o rear io tri t gt rear io tri t Vp Vn v n gt Vp Vn v n Vp Vn v p Vp Vn v p S03 FLASH IOB for i in 0 to 15 generate 504 begin 505 IOBUF inst IOBUF 506 generic map 507 DRIVE gt 12 Select Save File from the File menu or type Cntrl S to save the changes Acromag Inc Tel 248 295 0310 84 WWW acromag com XMC 7 Series AXM CC F Modify the Constraints File Acromag Inc Tel 248 295 0310 USER S MANUAL The constraints file must be updated Expand the Constraints file list by clicking of the symbol left of Constraints in the Sources pane as shown Block Design system a z mm oti A B Design Sources 15 CRRA system top STRUCTURE system_top vhd 3 SR AXM AXM_Dxx STRUCTURE AXM_Dxx vhd 6 Di system i system system bd 1 E aurora_8b10b_ aurora_8b10b_0_exdes MAPPED aurora H 6 Text 1 H E Configurat
101. steps required to make a simple modification to the example design and compile the project files to produce a new FPGA configuration file The process to update the configuration flash with the new file will also be covered The example design has the REAR IO interface configured as two unidirectional 32 bit single ended ports one input and one output In this walk through we will reconfigure the REAR IO to be a 32 bit bidirectional differential port This change will require updating the block diagram top level VHDL source and the constraints file Copy the Project To begin we will copy the example design project to a new work area Create a new folder CAXMC 7K325AX MOD Open the example project C XMC 7K325AX xpr Under the File menu select the Archive Project command Enter C XMC 7K325AX_MOD in the Archive location field as shown in Figure 18 Select Include configuration settings Deselect Include run results Hit OK n gt Archive Project Create a compressed zip file that contains all the sources settings and other files associated with d this project d Archive name XMC 7K325AX Archive location C XMC 7K325AX MOD u Archive file will be created at C XMC 7K325AX_MOD XMC 7K325AX xpr zip w Include configuration settings Figure 18 Archive Project Dialog Navigate to the C XMC 7K325AX_MOD folder and extract the archived project files Open the Vivado project XMC 7K325AX xp
102. t Hardware Device Properties ETSI gt SR xc7k325t 0 Name xc7k325t 0 Part xc7k325t ID code 43651093 IR length 6 Status Programmed Programming file C XMC 7K325AX_MOD XMC 7K325AX XMC 7I Probes file 7 XMC 7K325AX_MOD XMC 7K325AX XMC 7 User chain count 4 Acromag Inc Tel 248 295 0310 94 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The following window appears Scroll to select the mt28gu512aax1e bpi x16 device Click OK r 2 Add Configuration Memory Device o Choose a configuration memory part This can be changed later Device xc7k325t 0 Filter Manufacturer All v Density Mb All z Select Configuration Memory Part Search Q Name 44 28t512m29ew bpi x16 t 28f256m29ew bpi x16 4 28f128m29ew bpi x16 44 mt28gu0 1gaax 1e bpi x16 mt28gu512aax1e bpi x16 44 mt28gu256aax 1e bpi x16 4 28f128g18f bpi x16 44 28f00ap33b bpi x16 4 28f00ap33e bpi x16 The following dialog box appears Click OK cw Do you want to program the configuration memory device now Acromag Inc Tel 248 295 0310 95 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL The following dialog box appears Browse to select the flash image file mcs that you want to write to flash Click OK to write the file to flash Select a configuration file and set programming options Memory Device gt mt28gu512aax 1e
103. ter Reserved Front Input interrupt enable P1 Front Input Channel Interrupt Enable Register The Channel Interrupt Enable Register shown in Table 38 provides a second interrupt enable bit for the input channel Bit 1 is reserved since Channel 2 is configured as output only Table 38 Front Input Channel Interrupt Enable Register BARO 0x310128 Front Input Channel Interrupt Enable P1 Front Input Channel Interrupt Status Register The Channel Interrupt Status Register shown in Table 39 indicates the interrupt status for the input channel This bit is set when any of the 13 inputs change state This bit implements Toggle On Write TOW access The status of the bit toggles when a value of 1 is written to it Table 39 Front Input Channel Interrupt Status Register BARO 0x310120 Bit s Front I O Channel Interrupt Status Register P4 Rear Input Data Register Acromag Inc Tel 248 295 0310 Channel O interrupt status Interrupt not active Ea 1 Interrupt active The rear input data register is used to access the individual input channels The rear input includes 32 LVCMOS single ended channels Each channel is controlled by a corresponding data bit as shown in the P4 Rear Output Data Register Channel input signal levels are determined by reading this register Channel output signals are set by writing to the rear output data regist
104. ter pause point the Scatter Gather engine restarts descriptor execution at the next sequential transfer descriptor If the AXI CDMA is not idle writing to this register has no effect except to reposition the Scatter Gather pause point Note The software application must not move the tail pointer to a location that has not been updated with valid transfer descriptors The software application must process and reallocate all completed descriptors clear the completed bits and then move the tail pointer The software application must move the pointer to the last descriptor address it has updated 5 0 This register provides the source address for simple DMA transfers by AXI CDMA If a location in system memory is the source address it must be set with the AXI aperture base address 0x01000000 the least significant 24 bits of the system memory address 36 www acromag com XMC 7 Series AXM CC F USER S MANUAL In addition the physical address of the location in system memory must be set in the Address Translation Register which is described in the PCle AXI Bridge Control section Table 23 CDMA Source Address Register Read Write BARO 0x000A0018 Bit s FUNCTION Source Address Register This register is used by Simple DMA operations as the starting read address for DMA data 31 0 transfers The address value written can be at any byte offset Note The software application should only
105. the carrier board plus the installed XMC module within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering Remove power from the system before installing board cables termination panels and field wiring 14 WWW acromag com XMC 7 Series AXM CC F P15 Primary XMC Connector P16 Secondary XMC Connector Acromag Inc Tel 248 295 0310 USER S MANUAL The P15 XMC connector is wired per the VITA 42 0 standard Most of the P15 signals connect directly to the user programmable FPGA The P15 connector provides the 8 lane PCI Express interface to the host processor a JTAG interface and an I C interface to a serial memory device XMC 7A200 XMC 7K325AX and XMC 7K410AX models require 12V and 12V power when an AXM module is installed that requires 12V and 12V power All models require 3 3AUX power in order to maintain the encryption key stored in volatile memory if that feature is required The JTAG signals connect to the FGPA for configuration and debugging Table 2 P15 Primary XMC Connector Pin A B c D E F eg VPWR 2 GND nsns 3 e VPWR a GND MRSTOR 5 VPWR 6 Hav 7 VPWR EEN 3 VPWR 10 GAO 11 VPWR 2 GND MPRSN
106. tor pane Flow Navigator Project Manager 8 Project Settings 3 Add Sources Q Language Templates LF IP Catalog 4 IP Integrator Create Block Design 53 Open Block Design Ey Generate Block Design 4 Simulation Simulation Settings J Run Simulation 4 RTL Analysis a Open Elaborated Design 4 Synthesis 8 Synthesis Settings Run Synthesis EY Open Synthesized Design 4 Implementation 8 Implementation Settings gt Run Implementation gt Open Implemented Design 4 Program and Debug 5 Bitstream Settings Y Generate Bitstream a Open Hardware Manager Acromag Inc Tel 248 295 0310 92 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Click on OpenTarget and then Auto Connect Hardware Recent Targets Closed Targets gt ig Open New Target Acromag Inc Tel 248 295 0310 93 www acromag com XMC 7 Series AXM CC F USER S MANUAL Right click on xc7k325t O 1 and then select Add Configuration Memory Device Hardware Manager localhost xilinx_tcf Xilimx 0000 13ca721401 mE NI Status Er E localhost 1 E Bo xilinx_tcf Xilinx 000013ca721401 1 Open EB RAE AD Hardware Device Properties Program Device Refresh Device Add Configuration Memory Device Boot from Configuration Memory Device Program BBR Key Clear BBR Key Program eFUSE Registers Export to Spreadshee
107. transfers EM Interrupt on Complete Disabled Interrupt on Complete Enabled Interrupt on Delay Timer Interrupt Enable When set to 1 it allows a delayed interrupt out This is only used with Scatter 13 Gather assisted transfers _0__ Delayed Interrupt Disabled Delayed Interrupt Enabled Interrupt on Error Interrupt Enable When set to 1 it allows an error to generate an interrupt out o Error Interrupt Disabled Error Interrupt Enabled 15 Reserved Interrupt Threshold value This field is used to set the Scatter Gather interrupt coalescing threshold When Interrupt On Complete interrupt events occur an internal counter counts down from the Interrupt Threshold setting When the count reaches zero an interrupt out is generated by the CDMA engine Note The minimum setting for the threshold is 0x01 A write of 0x00 to this register has no effect If the CDMA is built with Scatter Gather disabled Simple Mode Only the default value of the port is zeros 14 23 16 Acromag Inc Tel 248 295 0310 31 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL Bit s FUNCTION Interrupt Delay Time Out This value is used for setting the interrupt delay time out value The interrupt time out is a mechanism for causing the CDMA engine to generate an interrupt after the delay time period has expired This is used for cases when the interrupt threshold is not met after a period of time and the CPU des
108. upt Vector register acts as an index for giving the correct Interrupt Vector Address Table 16 Interrupt Vector Register Read BARO 0x00100018 Bits FONCTION 31 0 Ordinal value of the highest priority enabled active interrupt OxFFFFFFFF if no interrupt inputs are active This is a 2 bit read write register The two bits are mapped to the two least significant bits of the location The least significant bit contains the Master Enable bit and the next bit contains the Hardware Interrupt Enable bit Writing a 1 to the Master Enable bit enables the IRQ output signal Writing a 28 www acromag com XMC 7 Series AXM CC F AXI CDMA Acromag Inc Tel 248 295 0310 USER S MANUAL 0 to the Master Enable bit disables the IRQ output effectively masking all interrupt inputs The Hardware Interrupt Enable bit is a write once bit At reset this bit is reset to 0 allowing the software to write to the Interrupt Status register to generate interrupts for testing purposes and disabling any hardware interrupt inputs Writing a 1 to this bit enables the hardware interrupt inputs and disables software generated inputs Writing a 1 also disables any further changes to this bit until the device has been reset Writing 1s or Os to any other bit location does nothing When read this register will reflect the state of the Master Enable and Hardware Interrupt Enable bits All other bits will read as Os Tab
109. ure Base address The new AXI address is 0x01000000 0x00345678 0x01345678 Write 0x01345678 to OxA0020 5 Write the number of bytes to transfer to the CDMA Bytes to Transfer register O0xA0028 Writing this register also starts the transfer 6 Either poll the CDMA Status register bit 1 for logic 1 or wait for the CDMA to generate an interrupt if enabled 38 www acromag com XMC 7 Series AXM CC F AXI BARO Aperture Base Address System Memory Physical Address 0x56xxxxxx gt 0xF0208 8 OxF020C AXI BARO Aperture Base Address 0x01000000 Example of AXI address used to reach system host memory 0x01ABCDEF PCle AXI Bridge Control Acromag Inc Tel 248 295 0310 USER S MANUAL 7 Clear the interrupt if generated by writing a 1 to bit 12 of the CDMA Status register 8 Ready for another transfer Go back to step 1 The AXI BARO aperture base address of 0x01000000 is set as the base address on the AXI bus used to reach system host memory for CDMA transfers The address 0x01000000 is the AXI BARO Aperture Base address In Vivado IP Integrator the address map will show that a 16Meg address space for the AXI BARO Aperture Base Address is reserved Table 26 AXI BARO Aperture Base Address Window into PCle Interface 0x01000000 gt 0x01FFFFFF 16M AXI BARO Aperture Base Address The following is an example of how the AXI BARO aperture base address is used For example
110. ver ITEM DIM mm TOL mm A 13 55 8 45 13 20 13 30 14 10 1 40 70 20 4 20 2 30 1nn 3 20 47 50 37 15 43 00 2 55 1 60 22 70 2 50 0 60 N lt xXZ lt CHOMUEFAx 1MmQ00 Acromag Inc Tel 248 295 0310 0 25 02 02 02 0 3 0 2 REF REF 015 n1 01 02 0 3 02 01 REF 03 102 1015 Acromag offers a SFP Transceiver that is compatible with the Gigabit Ethernet and 1000BASE T standards as specified in IEEE Std 802 3 It is ROHS compliant and lead free The Acromag part number is 5028 455 Specifications Operating Temperature Range 40 C to 85 C Connector 108 www acromag com XMC 7 Series AXM CC F USER S MANUAL 2 125 Gb s Short Wavelength SFP Transceiver Acromag provides 2 125 Gb s Short Wavelength SFP Transceiver that is compatible with the Gigabit Ethernet standard as specified in IEEE Std 802 3 and Fibre Channel FC PI 2 Rev 5 0 It is RoHS compliant and lead free The Acromag part number is 5028 452 Specifications Connector eee e eee nekeran eriin Duplex LC BIER seess cese Up to 2 125 Gb s Cable lengths 500m on 50 125um Multi Mode Fiber 300m on 62 5 125um Multi Mode Fiber E 850 nm Oxide VCSEL oT EE less than 500 mW Operating temperature range 400C to 859C Applications 1 25 Gb s 1000Base SX Ethernet Dual Rate 1 063 2 125 Gb s Fibre Channel Acromag Inc Tel 248 295 0310 109 WWW acromag com XMC 7 Series AXM CC F USER
111. write BARs Base Address Registers within the PCle bridge in order to support non contiguous host memory buffers The axi interconnect block named Host Peripherals expands the PCle master interface to provide access to the nine devices shown Axi intc 1 is an interrupt controller whose output drives the interrupt input to the PCle controller This connection is not shown due to the reduced detail view used to produce this diagram PCle axi_interconnect_2 AXI Memory Mapped To PCI Express Host_Peripherals M AXI PCIE REAR IO M AXI PCIE P16 IO M AXI PCIE CTSTAT m m TE axi interconnect 1 E RS AXI Interconnect ii S00 AXI a emn Mm AN ji i MM AXI Interconnect M_AXI_PCIE_AXM axi_intc_1 AXI Interrupt Controller AXI Interconnect Figure 8 Block Diagram PCle The hierarchical block named DDR3_Memory shown in Figure 9 includes an axi interconnect XADC A D converter System Monitor and the DDR memory interface mig 7series D The axi interconnect expands the slave interface port of the memory interface to three ports The three masters that can access DDR3 memory are the PCle bridge and the two master ports of the CDMA controller scatter gather and data transfer The axi interconnect provides many bus interface functions including arbitration width conversion buffering up sizing down sizing and synchronizing The XADC block was included in the DDR3 Memory block because it p
112. write to this register when the AXI CDMA is Idle CDMA Destination Address Register Acromag Inc Tel 248 295 0310 This register provides the destination address for simple DMA transfers by AXI CDMA If a location in system memory is the destination address it must be set with the AXI aperture base address 0x01000000 the least significant 24 bits of the system memory address In addition the physical address of the location in system memory must be set in the Address Translation Register which is described in the PCle AXI Bridge Control section Table 24 CDMA Destination Address Register Read Write BARO 0x000A0020 Bit s FUNCTION Destination Address Register This register is used by Simple DMA operations as the starting write address for DMA data 31 0 transfers Note The software application should only write to this register when the AXI CDMA is Idle 37 www acromag com XMC 7 Series AXM CC F CDMA Bytes to Transfer Register USER S MANUAL This register provides the value for the bytes to transfer for Simple DMA transfers by the AXI CDMA Table 25 CDMA Bytes to Transfer Register Read Write BARO 0x000A0028 Bit s FUNCTION Bytes to Transfer This register field is used for Simple DMA transfers and indicates the desired number of bytes to DMA from the Source Address to the Destination Address A maximum of 8 388 606 bytes of data can be specified
113. xdes is the wrapper for the Xilinx IP Core Generator generated example design for Aurora The IP Integrator block diagram labeled system is compiled to produce a lower level hierarchy of VHDL source files that are shown beneath system The symbol to the left of each of the labeled subsystems indicates that additional source files exist at lower levels in the hierarchy that are not shown 57 WWW acromag com XMC 7 Series AXM CC F USER S MANUAL a S m at 2 E F Design Sources 14 ERAS system top STRUCTURE system top vhd 3 E 4WAXM AXM xxx STRUCTURE AXM xxx vhd 3 E G AXM_DO1_GEN AXM_DO1 AXM D01 vi 0 STRUCTURE AXM_DO1v1_0 vhd 1 EI AM Dxx vi 0 S00 AXI inst AXM Dxx vi 0 S00 AXI arch imp AXM Dxx vi 0 SO0 AXI vhd 3 zb genIntStat Int InterruptStatus arch imp InterruptStatus vhd gt gen DIFF TS DIFF TS DirectionChange arch imp DirectionChange vhd Lagoon DIG TS DIG TS DirectionChange arch imp DirectionChange vhd Gi AXM 1 DOx GEN AXM DOx AXM_DOx_v1_0 STRUCTURE AXM_DOxv1_0 vhd 1 D G ANM A75 GEN AXM A75 AXM_A75_v1_0 STRUCTURE AXM_A75v1_0 vhd 1 Ed system i system system bd 1 E Ee system STRUCTURE system vhd 8 i F AURORA CNTL STAT system axi gpio D 3 system axi apio 0 3 xcd Mh CDMA CDMA imp 18J058S STRUCTURE system vhd 2 E DDR3 Memory DR 3 Memory imp 9MYWN STRUCTURE system vhd 6 Mh FLASH Memory FLASH Memory
114. ystem software then programs the configuration registers with the interrupt request assigned to the board The PCle specification requires software driven initialization and configuration via the Configuration Address space This board provides 512 bytes of configuration registers for this purpose It contains the configuration registers shown in Table 7 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Register which must be read to determine the base address assigned to the board and the interrupt request that goes active on a board interrupt request Table 7 Configuration Registers Reg D31 D24 D23 D16 D15 D8 D7 DO Num 0 Device ID Vendor ID 0x7000 XMC 7K325F 0X7001 XMC 7K410F 16D5 0x7002 XMC 7K325AX 0x7003 XMC 7K410AX 0x7004 XMC 7K325CC 0x7005 XMC 7K410CC 0x7006 XMC 7A200 0x7007 XMC 7A200CC 1 l Status Command 2 Class Code 118000 RevID 00 3 l BIST Header Latency Cache 4 5 64 bit Memory Base Address for Memory Accesses to PCle interrupt I O registers System Monitor registers and Flash memory 4M Space BARO 6 7 64 bit Memory Base Address for access to DDR3 memory 16M Space BAR2 8 10 Not Used 22 www acromag com XMC 7 Series AXM CC F USER S MANUAL 11 Subsyst

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