iSIM Active Filter Designer Overview
Contents
1. 1 27 1 1 D 140 EH Select 5261 58 to EE Select ELS105 5 EES Select ELS163 Select 021653 WC e m m Intersil Picking Suitable Op Amp Solutions The part choices are sorted by minimally acceptable to increasing design margin to the requirements The top device in the table generated for each stage is deemed minimally suitable and 1 the default part filled into the top boxes Going down the list gives more design margin This step requires a device selection for each stage before the next step hitting Design At any time you can change a stage to inverting which then constrains the solution op amps to be VFA since CFA devices cannot easily be applied to the those topologies e The Setup and design process works in gain magnitudes but it does report if the overall filter is inverting or non inverting 27 intersil Picking Suitable Op Amp Solutions e To summarize the computed minimum requirements for each stage shown on this screen include Bandwidth if the stage in non inverting Gain Bandwidth Product if inverting Slew rate Maximum Vopp including any step overshoot or frequency response peaking Maximum input Vipp e These terms are used to constrain and sort the table of op amp selections to parts that Can operate at the specified total supply voltage Will not clip given that supply voltage and output swing including any2. Lid Select E 2 2 2 5 4 5 4 Select FA 5 8 2 2 25 4 5 Seiect FA 5 7 7 5 2 6 02 3 s Select FA 83 3 so 5 8 5 0 02 3 s s Seiect FA 106 2 1 5 2 3 3 s s ERR Select FA 198 2 5 5 6 4 5 5 Select CFA s 5 2 14 3 4 5 3 Eid Select FA 65 2200 2 5 3 5 2 6 ot intersil The 2nd most important thing is that the Constraints can only be changed if you sitting on the final stage as the active stage This is mainly related to the final output Vpp target That can be updated for the last stage but is then calculated for all previous stages and hence cannot be updated if you are sitting on those earlier stages for amplifier selection purposes e While sitting on each stage tab the tool is computing and reporting the implied requirements for that stage These include Bandwidth if the stage is non inverting Since this can be either a VFA or CFA op amp gain bandwidth is not used in this line So taking the required BW number times the stage gain will give you the required GainBandwidth Product if you want to use VFA op amp this stage If you change the stage to be inverting only VFA devices can be used and this computation reports the required Gain Bandwidth Product GBP 22 i nte rsi Adjustments Available on the Setup stage On any given stage you can change the topology from non inverting default to inverting and that immediately updates the recommended amplifier list at the bottom
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4. The Tool is Mainly an Implementation Aid f you need help deciding on the filter shape try this web site free download that has a lot of filter shape design tools just need to get the pole locations from here or the shape description to use in the iSim Active Filter Designer Filter Wiz PRO Exact pole locations and advanced features may require you to purchase the full version 16 intersil __ AC Response Preview From whatever settings are used in the upper section of the Requirements screen hitting Update Preview will generate the ideal Gain Phase and Group delay These are used later to compare to the actual circuit level implementation Here is the screen after hitting Update Preview intersil Home Application Requirements LES ummary Designs Filter Designer Design Requirements 3 2 9 3 gt lal Gain dB 2 8 ui i o 72 m 2 Phase deg Group Delay us oe T 10000 100000 1 06 Fi intersil Two Primary Flows through Active Filter Designer 1 Semi Automatic flow is where you want to use some of the pre loaded filter shapes and let the tool do most of the work for you This is the default mode and is what is shown on first entering the tool This flow also decides for you the sequence of poles order gt 2 and how
5. to produce that output from an ideal input step and takes 2X that number for a design target Possible op amps to use in each stage use this Slew Rate calculation to constrain the list to op amps that offer at least 9096 of this calculated value 24 intersil Picking Suitable Op Amp Solutions The goal of this Setup page is to pick a suitable op amp that Will work in each stage in the design If possible the tool will automatically pick the closest fit as you come into this step but that can be overridden by picking one of the parts listed at the bottom of the screen Selecting on the red part number will take you to the product page for that device showing package styles pricing availability etc e These are often different devices auto filled in each stage but these can often be made the same device with a little effort e Changing the supply voltage will typically show a completely different set of op amps For instance going to 10V total supply with 6Vpp output will show the following screen hit the Apply key after you update the supply voltage and output swing fields 25 intersil Modifying the Constraints gives new part choices e More CFA parts show up here as the prior setting of 5V supply and 2Vpp output violated the 1 6V headroom on those CFA parts intersil Estim im m out Nominal Nominal Headroom Vcc Min Vcc Max 1k MSRP En nV Vcc V Is mA V v v Price Des
6. 151 ACTIVE FILTER DESIGNER Michael Steffes Sr Applications Manager 12 15 2010 SIMPLY SMARTER Introduction to the New Active Filter Designer Scope and Intent Getting into the tool e Two Primary Design Flows Semi automatic design User specified poles and gains for each stage From design targets pick op amps simulate and save share features Example Designs e Supporting Information 2 intersil Scope and Intent of the Active Filter li Intent is to deliver working designs using Intersil s Precision and High Speed Op amps Basic filter types that will be supported Low Pass High Pass Bandpass The list above will be the rollout sequence Low pass filter designs are available at this initial Feb 2010 release intersil Important Terminology Filter is the highest level classification Low Pass High Pass Notch Bandpass Allpass etc Filter Order is the number of poles in the transfer function ist order is just a single energy storage element like an RC filter 2nd order stages are only complex poles in this tool 20 5 2nd through 6th order filters supported by the tool built up as a combination of 1st and 2nd order stages no 3rd order stages Filter Shape describes the pole locations Infinite number of possible combinations of multiple pole locations some standard ones include Butterworth Chebyshev e
7. 1s2 in F 240p F 4I R1 R2 S1 5428127 R1 R2 S2 19124021 360 0650 mLJw eT 20 cC 7 od Cu NL voi cast 7 C2 s2 x f T by 4 c d gt RF S1 1 RES RG S1 560 RG S2 0 45 4n 383 O ss intersil Design Summary and Saving Sharing Options This summarizes the overall targets the constraints and the final circuit design e Down below on this screen are the BOM the AC Transient and or noise sims that have been done e Most importantly in the upper right are paths to go on from here Save the design the little floppy icon This saves the design locally in your filter tool folder so you open it up and work on it later Once saved you can also share the design by emailing it from the Saved Designs tab Download to PDF This takes the design summary and creates a pdf version that can be saved and then easily emailed around to colleagues customers Download to iSim PE This ports the schematic into a more general purpose simulator where added operations can be performed These include MonteCarlo simulations re ordering the stages converting it to a single supply design etc 34 intersil Added Information and Filter Tool Extensions Full User s manual added March 2010 Designer s Manual for the iSim Active Filter Designer AN1548 Additional parts will be easily added to the tool as they become available new parts o
8. AC Results AC Output 1 Filter AC Output Le Ei 31 4 9 164 10 0 11 04 1004 100 di nid 20 Phase 14 0 70 Phase 94 204 A Quin 70 4 124 1004 40 n XN 8 71 120 104 i 310 200 10 NK 19 gt 15 io b e 5 17035 21930058 20 Po 1 ra 0 a ANS a 8 6419 40049 50 XD 3 220 2 23 104 2 i 500 0 5 4 F 54 M 2 500 110 X 14 320 0 en 0 7004 140 T 370 a4 30 800 170 10000 100000 1e 06 1 07 10000 100000 1e 06 16 07 Frequency Hz All AC Outputs 164 100 100 144 c La ama a 124 100 0 10 200 0 x 2 7 4 643 300 A 3 e 40073 a 00 2 600 o 5 Frequency Hz GroupDelay Phase Gain GroupDelay Phase 1 intersil Comparison of Actual to Ideal AC Response This viewer also has two cursors that can be moved and a zoom in feature Here we see very good overall fit for the simulated filter response vs ideal Note the 40dB gain at low frequencies 32 inte sil Design Summary and Saving Sharing Options Going back to the Filter tool from the waveform viewer and clicking Design Summary will give the following screen Design Design not sa PDF Download Ej Download Schematic 60 69dBc Stage 10 50000 Stage2 10 0000 Staget 92 cs
9. Design Requirements Select Filter Low Pass Select Filter Order 4 Yes Filter Cutoff Frequency s Enter Poles Manually Pass Gand Gain v v Select Filter Shape Butterworth Filter Shape Butterworth This filter shape offers the flattest passband gain response at Wl Update Preview E Continue the expense of relatively slow rolloff in the transition region There are no gain npples in either the passband or stopband Active Filter Design Tool Overvis region The step response does show some overshoot that increases with filter order Asctive Fitter Designer Users Guide F sae F tart Testing 10067202 Sctive Filter Dex aner Gain ang Sequencing Impact on Output Noige 14 intersil The Tool is Mainly an Implementation Aid e Many vendor tools provide some filter shape help as an early step in their tools This is used to arrive at a desired filter order and pole locations to hit a particular skirt shape how fast the cutoff band rolls off Usually this is specified in terms of stop band attenuation at a certain frequency above the desired passband e The Active Filter Designer assumes you already know the target shape and or the approximate order or filter poles you want to implement The tool mainly works on getting the right op amp selected and design implemented in a way the will yield a successful board level implementation 15 intersil
10. SL28413 ISL28136 VFA 5 1 5 0 9 2 4 5 5 ISL28136 ISL28236 ISL28114 VFA 7 7 5 0 4 1 8 5 5 ISL28214 ISL28414 ISL28127 VFA 10 30 2 2 4 5 40 ISL28227 ISL28110 VFA 12 30 2 6 9 40 ISL28210 ISL24021 VFA 15 10 2 4 5 19 ISL28191 VFA 61 5 2 6 3 5 5 ISL28191 ISL28291 ISL55001 VFA 68 30 9 8 30 ISL55002 ISL28190 VFA 83 3 5 8 5 3 5 5 ISL28190 ISL28290 EL8101 VFA 106 5 2 3 5 5 EL8100 EL 8201 EL8401 EL5103 165 10 5 5 12 6 EL5102 EL5203 EL5101 VFA 170 10 2 5 5 12 6 EL5100 EL8103 VFA 198 5 5 6 4 5 5 EL8102 EL5105 VFA 264 10 5 5 12 6 EL5104 EL5205 EL2126 VFA 500 30 5 4 30 EL2125 VFA 700 30 10 8 4 30 ISL55190 VFA 700 5 16 3 5 5 ISL55290 EL5131 VFA 900 10 3 5 5 13 EL5130 EL5161 CFA 95 10 0 75 5 12 6 EL5160 EL5261 EL5163 CFA 140 10 1 5 5 12 6 EL5162 EL5263 EL8108 CFA 190 12 14 3 4 5 13 EL8108 HFA1105 CFA 270 10 5 8 9 11 HFA1145 HFA1109 CFA 340 10 9 6 9 11 EL5165 CFA 370 10 5 5 12 6 EL5164 EL5167 CFA 620 10 8 5 5 12 6 EL5166 6 intersi Feature set for the New Upgraded Macromodels Typical room temp nominal power supply voltages used to produce the following characteristics e Open and closed loop 1 0 impedances Open loop gain and phase Closed loop bandwidth and frequency response peaking under different external conditions Loading effects on closed loop frequency response Input noise terms including 1 f effects Slew rate Input and Output Headroom limits to 1 0 voltage swing Supply current at nominal specified supply v
11. about Active Filters The Active Filter Designer includes numerous features that might appear to violate some widespread myths Current feedback amplifiers CFA s cannot be used in active filters They are in fact very suitable as wideband gain blocks if that is what is needed in the filter stage Cannot be used easily with reactive feedback type topologies such as the MFB or infinite gain circuit Gain of 1 is required for the active filters or low gain The gain is a design variable and can be accounted for in setting the R s and C s But it does interact strongly with the amplifier bandwidth if VFA devices are used and this is also accounted for in the design algorithms provided in the tool Equal R or Equal C designs are required or desirable This comes from simplified academic developments or where the text is headed towards integrated solutions close cap ratio s desirable for integrated filters Not really a required constraint for discrete implementations intersil Entry from the main Intersil Web site intersil Home Products Design Assistance Applications English HAI Japanese MIESZ Chinese Korean View Cart Ordering ompany Info Search Advanced Search SIMPLY SMARTER Product Families ATE ICs Automotive ICs Comenanicalions ICs D2 udo Audio ICs Data Converters Digtal Potentiometers DCPs Digtal ICs Display ICs Industnal
12. ctive Filter Designer NEW egulation Integrated FET UPDATED Inverting Gain Non Inverting Gam Transimpedance Differential Amplifier strumentation Amplifier ower Supply Support Battery Management oad the offline schematic you can do c that you can analysis a 0 Download iSim PE iSim is a Trademark of Intersil Americas Toc 2003 2020 Intersil Americas Inc All rights reserved 12 sils iSim is sil s broad po 1 suitable Intersil de ble for immediate fe ar managemen tools are broken into Power and Op amps The top selection in the op amps Is this new design tool a simu n is also iSim is available for Power Management Intersils Sim simula aris th dynamic ds to ma ur input and c vill be listed and those with a design button bie or simulat a reference schematic will be generated ons Dased in ented zo al Amplifiers provides tion and high fiers Tools in ng Gain configuration age Low Pass Filte to that application al ou pick cation o High Pass Filter Each to models in most cases are interested i Please Clicking the Active Filter Designer takes you to gt intersil iSim Active Filter Designer User Log In Email Address Design Requirements Interview Enter your filter design requirements such as
13. oltages Nominal input DC error terms 1 3 of specified data sheet test or specified limits intended to give 16 error term on one polarity Load current reflected into the power supply current 7 intersil Features not supported by the Macromodels e Harmonic distortion effects e Composite video differential gain and phase errors Output current limiting if any Disable operation if any Thermal effects and or over temperature parameter variation Limited performance variation vs supply voltage modeled Part to part performance variation due to normal process parameter spread Any performance difference arising from different packaging e Multichannel device crosstalk effects 8 intersi Enhanced Capability Provided by the Tool e Semi automatic design flow for multi stage filters Spreads the gain from 1 to 10V V total between the stages and sequences the poles order gt 2 in a way that reduces non linear effects e Significantly improved circuit implementations Noise effects considered and reduced if possible 2nd order issues in the feedback and gain setting elements considered loading noise BW phase margin e Resistor solutions adjusted to account for amplifier bandwidth effects to hit the desired pole locations more precisely This also allows reduced amplifier bandwidth vs target Fo design margin than many currently available design tools intersil Common Misconceptions
14. peaking or step overshoot effects considering the output headroom of each device Provides at least 9096 of the computed minimum BW and slew rate Will not limit on the input given the supply voltage and input headroom limits of each device considered 28 inte rsil e Once we have design targets for each stage and amp selected hitting the Design key will go off and compute the R s and C s for each stage and come back with a completed design At that point the total specified supply is split into Vs 2 halves and the design is shown as a DC coupled ground centered signal swing implementation Hitting Design from the previous screen 10V supply 6V output swing gives the following active filter design 29 inte rsil Example Design Output Page Note the multi channel versions at the bottom and the simulation options at the top Hitting the AC tab will run an AC simulation intersil Design Summary 210 77 Filter Analysis Schematic Current Design not saved ra POWERED BY FA configure L3 noise Lac L3 Transient ED WebSIM J simetrix intersil 30 Output of the AC simulation key Clicking on the Filter AC Output opens a waveform viewer where we can add the Ideal Gain Phase and Group Delay Doing that Antersil Michael Steffes Logout Give Feedback Design IMMCS E My Designs Filter Analysis Waveforms ave
15. r as needed older parts not currently included Last update in Nov 2010 Op Amps the tool have totally updated upgraded Spice Macromodels Next addition will be the High Pass Filter flow followed by the BandPass Filter flow during 2011 If you use the tool and find an issue please try to re create it keeping track of exactly how you got to that point and report it using the Feedback option It is also helpful to save the design and share it 35 intersil
16. s Band Gain v v 3 1 enar Fo and Q 2 amp Q s a oT nust be un normalized ase ter t t amp Q an ain for each sta i F Group Delay us 19 intersil Hitting Continue from the Requirements page will go the Setup page where numerous implementation parameters are considered and available for modification This step starts out with some default assumptions This is where the real work begins in matching op amps to the desired filter implementations For multi stage filters the most important thing to notice on this next screen is which stage is active in the setup screen This is the red color on the Stage tab It comes into this step with the last stage as the default active stage This is where the design constraints can be updated Those also default to the values shown on the next slide but can be modified 20 intersil Setting up the Design e The goal for this step is to pick the right op amps for each stage given the topology filter targets and constraints 7 Home Application Requirements Setup UNDC NEM C E My Designs Michael Steffes Logout Give Feedback Filter Designer Stage Stage Design Constraints Select Resistor Precisio Vout Feedback GBP BW Slew Rate Nominal Nominal Headroom Vcc Min VecMax 1k MSRP Type MHz V us En nV Vec V Is mA V v Price Description
17. tc Filter Topology describes the op amp implementation to achieve a particular 1st or 2nd order set of filter poles Sallen Key is one popular one 4 intersi Low Pass Active Filter Design Range e The design tool supports a very wide range of requirements Cuttoff frequencies from 5Hz to 50Mhz 7 decade range Total filter gain from 1 to 10V V in semi automatic design flow but up to 125V V 3 stage design in the manual design flow Filter order from 2 to 6 The filter order from 2 to 6 implies from 1 to amplifier stages Higher order filters tend to require extreme element precision to hit the higher Q targets that come along with orders gt 6 Amp Model List with New MacroModels Table of op amps in the Intersil Active Filter Designer sorted by VFA then CFA and then by ascending GBP or BW for CFA as of Dec 2010 Single Single Dual Quad Channel Topology GBP BWr Nominal Typ Is Min Vcc Max Vcc Channel Versions Versions Part VFA CFA MHz Total Vcc mA at Vcc Disable Version ISL28194 VFA 0 0035 5 0 00033 1 8 5 5 ISL28194 ISL28195 VFA 0 01 5 0 001 1 8 5 5 ISL28195 ISL28158 VFA 0 2 5 0 034 2 4 5 5 16128158 ISL28258 ISL28156 VFA 0 25 5 0 039 2 4 5 5 ISL28156 ISL28256 ISL28133 VFA 0 4 5 0 018 2 5 5 ISL28233 15128433 EL8176 VFA 0 4 5 0 055 2 4 5 5 EL8176 ISL28276 ISL28476 ISL28107 VFA 1 30 0 21 4 5 40 ISL28207 ISL28117 VFA 1 5 30 0 44 4 5 40 ISL28217 ISL28113 VFA 2 5 0 09 1 8 5 5 ISL28213 I
18. this is the only thing that can be changed when you are sitting on earlier stages Sitting on the last stage you can change the following global constraints Desired total supply voltage range here is 1 8V to 40V This supply voltage is assumed to be the same for all stages Maximum final stage Output Swing Vpp limited to be from 1096 to 9096 of Vs Linearity Target either SFDR if frequency domain or Step if step response If SFDR also asks for maximum expected frequency and desired distortion range Resistor tolerance exact 0 596 196 or 296 This effects the filter accuracy in that exact R solutions might be snapped to available values probably shifting the achieved filter shape off somewhat 23 inte rsil Adjustments Available on the Setup stage e Several of these constraints are feeding into the Estimated minimum slew rate required reported on each stage Slew rate is estimated to achieve either an SFDR target or step response without slew limiting The SFDR constraint is a necessary but not sufficient condition to achieve a certain distortion level you might still not get the SFDR with a device offering the reported slew rate but you reduce your chances if the device does not have at least the reported slew rate for that stage For a step response the tool is looking at the pole locations of that stage and the desired nominal Vopp or Vstep at the output It then computes the peak dV dT
19. to implement the total target gain It is essentially sequencing from high to low Q stages in low to higher gains in those stages in going from input to output 2 Manual Pole selection is where you have some specific pole locations you wish to implement and want to enter those directly This also allows you to select the Frequencies Gains and Q s over a wider range than the semi automatic path This is all selected in the row that asks Enter Poles Manually This defaults to No but clicking Yes changes this screen to accept user entry for each stage The order setting still sets the number of stages and an odd order 3 or 5 forces the real pole to be the last stage 18 intersil Manual Pole Entry Option Here the entry screen has been changed by clicking Yes on the Enter Poles Manually line and we have changed the gain in each stage to 10 giving an overall filter gain of 100 10 in each stage is the maximum for 2 stage designs and manually set the Q s to get a 4th order Butterworth shape then hit Update Preview again Hitting the Continue key from here intersil CU UL MEME Requirements NNI EESTI Michael Steffes Logout Give Feedback Filter Designer Design Requirements Select Filter Low Pass gt Select Filter Order 4 s Enter Poles Manually ves C no Int d Filt f o o gt requency ined kHz Pas
20. type order cutoff frequency gain etc Preview the design with ideal plots of the gain phase and group delay of the filter 13 109 in Register Compatibility Checks Sf Javascript Sf Pop ups Windows P Adobe Flash Player 8 or higher Sf Cookies iSim PE iSim Active Filter Designer iSim selects and sorts op amps suitable to each stage After you have selected the op amps it then designs for the R s and C s considering numerous 2nd order effects Design Verification by Remote Simulation Your design is displayed on an online schematic This virtual evaluation platform allows you to test the design with simulations for AC Noise and Step Transient analysis Summary Download Design amp More iSim generates a design report including design summary schematic bill of material and simulation results You may also share your design with other users and or download your Schematic to iSim PE intersil First Step in Getting to a Filter Implementation Coming into the tool fresh will give you the first Requirements screen set up to a default condition Hitting the drop down keys will show other options inter App caiion My Designs Filter Designer The active fiter designer vas updated 11 14 2010 to inc dition te slightiy adjust the automatic gain allocation algorithm to reduce o peaking in the filter stages uncer certain conditions
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