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G9001/G9002 User`s Manual 040327

1. Write cycle aen De Tia TRWA cs Tosrw LJ Trwes WRQ N Fi Teswr LT rar oe WR L TwR Jk TWRD D 15 0 lt l TowR Item Symbol Condition Min Max Unit Address setup time for RD WR 4 Tarw 18 ns Address hold time for RD WR T TRWA 0 ns CS setup time for RD WR 4 Tcsaw 8 ns CS hold time for RD WR T Tawcs 0 ns WRQ ON delay time for CS 4 Tcswt_ Ci 40pF 11 ns WRQ ON delay time for RD J Trowt CL 40pF Note 1 17 ns WRQ signal LOW time Twalt Note 2 12Tcik ns TRDLD C 40pF Note 3 4 2Tork 24 ns Data output delay time for RD 4 Ci 40pF Note 5 5g TwrHo C 40pF Note 4 0 ns Data output delay time for WRQ T Ci 40pF Note 5 i0 Data float delay time for RD T TroHo C 40pF 28 ns WR signal width TWR Twr Note 6 14 ns Data setup time for WR T Towr 22 ns Data hold time for WR T Twro 0 ns Note 1 Only when reading memory area address 078h to 1FFh WRQ LOW will be output by RD LOW Note 2 When CKSL LOW or CKSL HIGH the WRQ signal LOW level will be held for 24 x Terk Note 3 When CKSL LOW or CKSL HIGH the data output delay time will be 4Tcik 24 Note 4 When reading memory address addresses 078h to 1FFh Note 5 When reading non memory addresses addresses 078h to 1FFh Note 6 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until WR goes HIGH 1 36 7 4 5 I F
2. Command I O buffer Address Device No 5000h Bit 0 to 7 078h 0 Bit 8 to 15 079h 1 5004h Bit 0 to 7 07Ah 2 Bit 8 to 15 07Bh 3 5008h Bit 0 to 7 07Ch 4 Bit 8 to 15 07Dh 5 500Ch Bit 0 to 7 07Eh 6 Bit 8 to 15 07Fh 7 Use this function when you want to reduce the number of addresses used in the central device Note For all bits marked with a the upper bits of the device address should be set in order starting from the left end of the bits For bits marked with an amp when the port is 0 or 1 set the bit to 0 When the port is 2 or 3 set the bit to 1 For bits marked an x either 0 or 1 may be used G9002 I O device G9003 PCL device G9004 CPU emulation device 1 25 Command Description 0101 0001 0 x xxxx 5100h to 517Fh Write to the I O communication error flag area The contents of the I O buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0101 0010 O xxx 5200h to 527Fh Write to the input change interrupt setting area The contents of the I O buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0101 0011 0 xxx 5300h to 537Fh Write to the input change interrupt flag area The contents of the I O buffer are written into a word in this area
3. Conditions Results Transmission ae Cable Terminating Pulse I F chip Max rate devises used resistor transformer length 20 Mbps 32 CAT5 100 ohm 1000 uH RS485 100m 20 Mbps 64 CATS 100 ohm 1000 uH RS485 50 m 10 Mbps 64 CAT6 100 ohm 1000 uH RS485 100 m Note In the figures above the maximum length figures are results from ideal conditions in a laboratory In actual use the results may not be the same 2 1 Cable Commercially available LAN cables were used CAT5 Category 5 CAT6 Category 6 We used these LAN cables because they are high guality cheap and easy to obtain Lower guality cables such as cheap instrument cables may significantly reduce the effective total length of the line LAN cables normally consist of several pair of wires Make sure to use wires from the same pair for one set of communication lines Even when using cables with the same category and rating the performance of each cable manufacturer may be different Always use the highest guality cables in the same category 2 2 Terminating resistor Select resistors that match the impedance of the cable used ae Normally a 100 ohm resistor is recommended Therefore we used terminating resistors with this value Adjusting this resistor value may improve the transmission line quality 2 3 Pulse transformer We recommend using pulse transformers in order to isolate the GND of each local device By isolating the GNDs the
4. Note 2 When CKSL LOW or CKSL HIGH the ACK signal LOW level will be held for MIN 4 x Tork MAX 20Tcik 15 Note 3 When CKSL LOW or CKSL HIGH the data float delay time will be 4Tcix 1 38 8 External dimensions Plastic QFP13 64pin Unit mm 10 w es 82 9 0 125 I 40 ll I O device G9002 User s Manual Il 2 1 Outline This LSI is an I O device for the Motionnet system The central device can control input and output signals for four ports each of which can be specified as an input or output port using terminal settings One port 8 bits 2 Features Four I O terminal ports can be controlled Each port has 8 bits Input or output operation can be selected for each port Specify the I O selection using the LSI terminals The signal logic can be specified for each I O port Specify the logic using the LSI terminals A single 3 3 V power source is all that is needed Connections can be made to 5 V devices on the main terminals 3 Basic specifications 3 1 I O device specifications G9002 Item Description Number of input output ports 4 input output ports 1 port 8 bits Input or output operation can be selected using the terminals The I O signal logic can be set for each port using the terminals Transfer system Cyclic transfer Package 80 pin QFP Mold size 12 x 12 x 1 4 mm Power source 3 3 V 10 Storage temperatur
5. O Input change The bit positions which are HIGH correspond to device and port numbers whose input has changed YES Process specified by user Process specified by the user In this step process all the flags that have become HIGH the other flags do not need to be processed Write back the data you just read in order to clear the Com 0x5300h or WORK change interrupt flag Outpw 0x0004h Data Note that the command is different from the one used to read the data Outpw 0x0000h Com LOOP LOOP 1 NO Note 2 LOOP lt 16 Although this example checks the interrupt flags on all the addresses by using loop processing you can check A YES just the areas required End The read command is constructed as follows 15 14 13 12111 10 9 8 7 6 5 413 2 1 0 0 1 1 0101011110 X IX amp When writing data used to Specify the address in these 8 bits clear the flags these bits The lower 2 bits of the address byte are not used Leave become 0101 them at 0 The lowest bit marked with an amp is empty Leave it at 0 Note 1 In the address creation step above the program shifts the LOOP variable three bits left This is done to create the command above Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 4 16 IV 10 2 5 Check and cle
6. Communication line If the pulse transformer is atthe end of the communication line insert a terminating resistor GND either before or after the pulse transformer G9000 series SN74LVC244A Note 1 The pull down resistor to GND should be 5 to 10 k ohms 1 15 1 6 Complete configuration We recommend a configuration with the central device at one end of the line and the local devices at other end as shown below If you want to place the central device in the middle of the line use two communication lines so that the central device is effectively at the end of each line Central device SIB SIA 4 sol 5 5 a SOEH J a 3 5 D Si n Local device Gi 5 SI A a SO fa 8 le ISOEH If needed construct the 3 S same configuration on this side J WJOJSULIL Terminating resistors are needed at the ends of the line Insert them either before or after the pulse transformer to get JBNIBOSUEI eur the same effect Terminating resistors are not needed anywhere except for the ends of the line Local device A AAA JQUUOJSUEI JOA OSUE SUI JOWMOJSUBIL JOAIQOSUB eur 11 16 2 Recommended environment Shown below are the results of our experimental communication results and the environment used for the experiment These results can be used to design your own system However other system configurations are possible The example below is only for your reference
7. The lower 2 bits of the address byte are not used Leave them at 0 The lowest bit marked with an amp is empty Leave it at 0 Note 1 In the address creation step above the program shifts the LOOP variable five bits left This is done to create the command above Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 16 4 IV 12 2 6 Communication with port data port data and data device status This section describes data exchange using the I O port on an I O device G9002 and how to obtain the status of a data device Assume that the local devices to be used are as follows Only an example of how to read the status is given for the PCL device G9003 Device type Item to configure Configuration data Output data I O device Device address 2 Port 0 Input Port 1 Output 12h Port 2 Output 34h Port 3 Output 56h PCL device Device address 5 Note The port area configuration of the PCL device G9003 is always as follows fixed Port No Mode Description Port 0 Input Main status MSTSBO lower 16 bits Port 1 Input Main status MSTSB1 upper 16 bits Port 2 Input Input value from the general purpose I O port IOPIB Port 3 Output Output value to the general purpose I O port IOPIB 1 When the whole address map can be used Write data to the I
8. WORK WORK and 0x9FFEh WORK WORK or 0x6001h Outpw 0x00C2h WORK Specify the mask and port data to monitor In this case a logical AND process may not be needed Write 2 When using only the lower 8 bytes in the address map The central device details that can be seen from an external CPU are from the command area to the data transmission reception FIFOs Use commands to access other areas Specify the device data for device numbers 4 and 7 To set the data write the data to the I O buffer Then issue a write command to the target s device number area Outpw 0x0004h 0x6001h Outpw 0x0000h 0x5208h A write command is constructed as follows 15 14 13 12111 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 O OJ 1i OJOJ X XJ amp Specify the address here The lower 2 address bits are not used Leave them at 0 Positions marked with amp are not used Leave them at 0 IV 8 2 4 Check and clear any existing input change interrupts When the port status set in the previous section changes an input change interrupt will occur This section describes how to check and clear this interrupt 1 When the whole address map is used Assume that the routine is started by an interrupt being issued INT LOW Read the status data in the central device Sts Inpw 0x0000h Note 1 WORK LOOP lt lt 1 Shift the loop variable
9. 1 CAER A CPU access error occurred When there is a problem accessing a CPU such as a data send command being written when there is no data to send this bit becomes 1 The central device then outputs an interrupt signal INT Once the status of this bit is read it returns to 0 The details of the error can be checked by reading the interrupt status Not defined Always 0 REF When there is not yet sent output port data this bit becomes 1 Write a 1 to the output port area When cyclic communication to all the ports has completed this bit returns to 0 TDBB When there is data to send in the transmitting FIFO this bit becomes 1 After data is written to the transmitting FIFO this bit becomes 1 Once a data send command or a transmitting FIFO reset command is written this bit returns to 0 10 RDBB When data has been received in the receiving FIFO this bit becomes 1 When receiving data from a data device this bit becomes 1 After a CPU has read all of the data received this bit returns to 0 11 Not defined Always 0 12 SBSY Becomes 1 when I O communication cyclic communication starts RBSY Is 1 during a reset 14 DBSY Is 1 during system communication or data communication 15 Not defined Always 0 Note 1 The details of an error that occurred due to an attempt to communicate a type of information to an I O device that is diff
10. 101h Port data No 1 Device No 0 Port1 da data No 1 Device No 0 Port 110000 0010 102h Port data No 2 Device No 0 Port 2 coi data No 2 Device No 0 Port 110000 0011 103h Port data No 3 Device No 0 Port 3 poi data No 3 Device No 0 Port poe eth Wer 1 1111 1100 1FCh Port data No 252 Device No 63 Port 0 Port data No 252 Device No 63 111111101 1FDh Port data No 253 Device No 63 Port pen A De 11111 1110 1FEh Port data No 254 Device No 63 Port 2 DA ee No 254 Device No 63 111111111 1FFh Port data No 255 Device No 63 Port san ea 2 Dasi No 63 o Note 1 Write in lower bit to upper bit order This order is especially important when accessing the FIFO used exclusively for sending data Note 2 Read in lower bit to upper bit order This order is especially important when accessing the FIFO used exclusively for receiving data l 15 Address map 2 I F mode 3 A1 to A8 Writing Reading 0 0000 000 000h Command bits 0 to 15 Status bits 0 to 15 0 0000 001 002h Invalid Interrupt status bits 0 to 15 0 0000 010 004h Input output buffer bits 0 to 15 Input output buffer bits 0 to 15 0 0000 011 006h Data transfer FIFO bits 0 to 15 Data receiving FIFO bits 8 to 15 9 Tn 190 2 Not defined 56 words Not defined 56 words 0 0111 011 076h Any data written here will be ignored Always read as 00h 00111100 078h Device information
11. Address setup time for RD WR Tarw 18 ns Address hold time for RD WR T Trwa 0 ns CS setup time for RD WR 4 Tosrw 8 ns CS hold time for RD WRT Tawcs 0 ns WRQ ON delay time for CS Tcswr Ci 40pF 11 ns WRQ ON delay time for RD J Taowr C1 40pF Note 1 17 ns WRQ signal LOW time Twalt Note 2 12Tcik ns TRDLD C 40pF Note 3 4 2Tork 24 ns Data output delay time for RD Ci 40pF Note 5 5g Twtio CL 40pF Note 4 0 ns D ata output delay time for WRQ T Ci 40pF Note 5 i Data float delay time for RD T Tomo Ci 40pF 28 ns WR signal width TWR Twr Note 6 14 ns Data setup time for WR T Towr 22 ns Data hold time for WR T Twao 0 ns Note 1 Only when reading memory area address 078h to 1FFh WRQ LOW will be output by RD LOW Note 2 When CKSL LOW or CKSL HIGH the WRQ signal LOW level will be held for 24 x Terk Note 3 When CKSL LOW or CKSL HIGH the data output delay time will be 4Tcix 24 Note 4 When reading memory address addresses 078h to 1FFh Note 5 When reading non memory addresses addresses 078h to 1FFh Note 6 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until WR goes HIGH 1 35 7 4 4 I F mode 3 IF1 H IFO L Read cycle ae Tarw TRWA cs T CSRW LJ TRWCS WRQ Tcswr gf 3 srt Twat K gt RD TRDWT A TroHD D 15 0 Qi NP
12. Electrical Characteristic dosen una Aa ana Nama ee aa 1 33 7 1 Absolute maximum ratings iii I 33 7 2 Recommended operating conditions nnne 1 33 123 DG CHAnaCleriStes i nas eta Ba ena Dini ema Bun Tema inn Tenan aa alun 1 33 7 4 AC characteristics sienne 1 34 7 4 1 System clock iii 1 34 7 4 2 Reset timing manakala 1 34 7 4 3 I F mode4 IF1 H IF0 H ii 1 35 7 4 4 I F mode 3 IF1 H IFO L Wanna I 36 7 4 5 I F mode 2 IF1 L IF0 H i 1 37 7 4 6 I F mode 1 IF1 L IFO L i 1 38 8 External dimensions iii 1 39 Ii VO device 9002 SEE AAA A LL ALLA LOI Il 1 RENAE EE Rin Il 3 2 Feature Seanoinn CE MARA Ah A AA AA AA ARA NN NAN ne Il 3 BASIC SPECITICANONS AS E E anti AA IA AAAS T na Il 3 3 1 I O device specifications G9OO2 oooooWo oWoooWoWoW Wo iii Il 3 4 Hardware Description 40an ANE EN NN EN NE a Il 4 4 1 List of terminals QFP 80 rint a a a Il 4 4 2 Terminal assignment drawings Woo WWW WWW Waka Il 6 4 3 Complete block diagram ee Il 7 4 4 Functions of terminalS WWW sise Il 8 4 4 1 E C Il 8 AA DA RST a Il 8 4 4 3 CKSL i Il 8 4 4 4 DNO to DIN EE Il 8 4 4 5 DNSM ii Il 9 4 4 6 DNSO ii Il 9 4 4 7 SPDO SPD1 EEE Il 9 4 4 8 TUD E Il 9 4 4 9 TMD E Il 9 4 4 10 TOUT iii Il 10 A 4 11 SO RR Ie Il 10 4 4 12 SOEH SOEL 2 Il 10 4 4 13 SQE
13. PMDO 000 Output Output Output Output L L L 001 Input Output Output Output L L H 010 Input Input Output Output 3 H L 011 Input Input Input Output L H H Ta Input Input Input Input Hanan When a local device is a data device the ports used to exchange data status or general purpose ports have a different meaning for each device Device type 0 I O device 1 Data device Use of device 0 Do not use 1 Used Ex To get device information for device Nos 0 and 1 access address 078h For a 16 bit CPU address 078h 15 14 13 12111 10 9 8 7 6 5 413 2 1 0 Device No 1 Device No 0 l 18 4 5 2 I O communication area flags The central device communicates with all the I O ports using cyclic communication In this type of cyclic communication if a communication error occurs for a specific I O device on three consecutive communication cycles the central device will treat this as an I O communication error When this error occurs the bit in this area corresponding to the device number will become 1 By checking these bits you can identify the I O device in error Ex When reading address 0B8h For a 16 bit CPU address 0B8h 15 14 13 12111 10 9 817 6 5 413 2 1 0 Ss Error on device number 15 Error on device number 0 As seen above the lowest bit s
14. Torst Torst Internal RST Item Symbol Min Standard Max Unit Reset length Twrsti 10 Clock cycles Delay time Torst 10 Clock cycles Note 1 The reset signal must last at least 10 cycles of the system clock While resetting Make sure the clock signal is continuously available to the device If the clock is stopped while resetting the device cannot be reset normally Note 2 After the internal RST goes LOW the central device automatically resets the internal memory area to all zeros address 078h to 1ffh After the reset is complete the central device is once again ready During the reset the status RBSY bit 13 remains 1 Therefore make sure that this bit has returned to 0 before accessing the central device at the end of a reset The following are the minimum times needed to reset the internal memory area CKSL L 270 Terk 6 75 usec at 40 MHz CKSL H 540 Terk 6 75 usec at 80 MHz 7 4 3 I F mode 4 IF1 H IFO H Read cycle A 8 0 gt Tarw TRWA cs _Tesrw LJ Trwcs WRQ Di ff Tesir Twr RD TROWT ka Toro D 7 0 i L So TRDLD TwrHD Write cycle A 8 0 Tarw Lr cs Tes J Trwcs WRQ N gt Tcswr L JI ri Lo WR L Tur J k Twro D 7 0 lt Towr Item Symbol Condition Min Max Unit
15. Use this function when you want to reduce the number of addresses used in this device 0101 0100 OHHH amp 5400h to 547Fh Write to the port data area The contents of the I O buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0110 0000 O xx 6000h to 607Fh Read the device information area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device 0110 0001 O x xxxx 6100h to 617Fh Read the I O communication error flag area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device 0110 0010 O xxx 6200h to 627Fh Read the input change interrupt setting area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device 0110 O 11 O xxx 6300h to 637Fh Read the input change interrupt flag area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device 0110 0100 OHHH amp 6400h to 647Fh Read the port data area The contents of the word in this area are copied to the I O buffer Use this fun
16. be very similar We used 1000 uH pulse transformers However in order to obtain better response characteristics you may want to try pulse transformers with a larger reactance Line transceivers We used TEXAS Instruments chips for the experiments Other possibilities are available from MAXIM and LINEAR TECHNOLOGY who offer very high performance transceivers Connectors If possible the connectors should match the cable characteristics Although we did not use them modular type connecters will be better for LAN cables Cable connections Do not connect one cable to another cable using connectors etc In a multi drop system the number of cables increases as the number of local devices increase However connecting a cable just to extend the line should be avoided Processing of excess cable Excess cable left over after making all the runs should be eliminated Unneeded cable length may restrict the line overall usable length and may introduce electrical noise Circuit board substrate Create circuits on a substrate with 4 or more layers to prevent the introduction of noise Estimating cable length in the system design phase In the first estimate use shorter line lengths In the actual system configuration lines may be lengthened Estimates made using the maximum length may lead to impossible communication distances Minimum cable length Each cable must be at least 60 cm 23 1 2 in long Although this may see
17. 111 6 1 1 5 Connecting to a CPU without a wait function 1 7 T2 ACCESS TIMING Ae E Ian ea nana anna nan RI lie 111 8 12 12 Normal access asia ea sn an anang naa 111 8 2 1 1 Write to the I O buffer or the data transfer FIFO Jaan 111 8 1 2 1 2 Writing to a memory address WWW W nnaaknnnnnakan 111 9 1 2 1 3 Read timing Bei niente eck RENA ii AAA Nan 111 9 12222 Access by COMMANAS At HS NA AAN 11 10 1 2 2 1 Write operation command is 11 10 1 2 2 2 Write data to memory using write commands oom 11 11 1 2 2 3 Read data from memory using read commands oom 11 12 1 3 Line transceiver and pulse transformer for the central device oooooooWoWoWoW Woo 1 13 1 4 Line transceivers and pulse transformers for local devices iooooWoWW Woo 1 14 1 5 A connection example of a level Shifter Woo WWW Wc 11 15 1 6 Complete configuration ss 11 16 2 Recommended environment iii 1 17 Pea Gabe nilo ace AI AAA IAA AA AA AA RA AA AA Ai Aa Ad Aaa Aa Av Aa Ai da Ai dn alice Li 1 17 2 2 Terminating TESISEOT oooo WooW Woo WWW sise 11 17 2 3 Pulse transformer 1 17 2 4 WF Chips sante ote asus egies 1 17 2 5 Parts used in our experiments is 11 18 2 6 Other precautions WWW 11 18 IV Software Examples flow chart WWW Jalllnnlllaakaan IV 1 Te ASSUM PI ON ona aio an IV 3 1 1 Environm
18. 13 12 11 10 9 817 6 5 413 2 1 0 0 1 0 1 0 0 0 0 0 X amp Specify the address here The lower bit is not used in the address Leave it at 0 Positions marked with amp are not used Leave them at 0 IV 6 2 3 Set up an input change interrupt Assume that the central device wants to detect changes on the ports for the following two local devices Device No Port numbers to monitor for change 4 Port 0 7 Port 1 Port 2 1 When the whole address map can be used Specify the ports to monitor for device numbers 4 and 7 Be careful not to corrupt the data for device numbers 5 and 6 Outpw 0x00C2h 0x6001h End In I F mode 3 address 00C2h has the following meaning Monitor Port 1 and if there is a change on this port an input change interrupt will be issued Device No 7 Device No 6 Device No 5 Device No 4 15 14 13 12 11 10 9 817 6 5 413 2 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 Port 2 Port 1 poh 0 This address also contains a change interrupt setting for parts of device Nos 5 and 6 In order to prevent problems with the settings for these parts it is better to read the address and then use a mask IV 7 An example of how to use a mask to prevent corruption of the settings for device numbers 5 and 6 WORK Inpw 0x00C2h Read the current
19. 4 5 1 Device information area sise I 18 4 5 2 I O communication area flags akan I 19 4 5 3 Change to Input Port Interrupt Setting area om I 20 4 5 4 Change In Input Interrupt Flag area I 21 4 5 5 Portdata areas nee en MR A nana 1 21 A6 StAtUs eaa ee AR AR A tl 1 22 4 7 Interrupt status isie rina ae Ea Anali anna 1 23 4 8 Command eek nn an an An abi 1 24 5 Deseription Of the SOftware gan nana an aan ama aan Bana A 1 27 5 1 Outline dicontrol nana na Ran an Ra na aan ALI AIA de I 27 5 11 Communication Control sampan an aa a a A l 27 5 1 2 Communication type nan Naa 1 27 D 1 3 Input chang interrupts nsnnniamninnninnninnninnninnninnninmn nn is aa 1 29 5 1 4 Break function an asuhan he ae iii Lene 1 29 5 1 5 Control of communication errors 1 29 D 2 Operating procedures Nana rr na ell ea 1 31 D2 Reset SB Aa au nana nana rie dici Ri ia 1 31 5 2 2 I O communication procedures iii l 31 5 2 3 Data communication procedure iii l 31 5 2 4 Exclude a device with an error l 31 5 2 5 Restoring excluded devices to cyclic communications l 31 5 3 Status after reset Wo t ntun nanan unnu aAA AAEE AKARA anna ana ana ana anna l 31 6 How to calculate the communication cycle time ss I 32 6 1 Time required for one cycle is 1 32 6 2 Time required for one complete data communication oooooooooWoWoW Woo I 32 6 3 Total cycle time including data communication I 32 T
20. 5203 0 2 5203 ims Printed in Japan
21. Available 58 RST Negative Reset Available 59 DNSM Negative Mode to set the device number Available 60 DNSO O Negative Serial output of next chip device number 61 GND GND from the power supply 62 CKSL Select clock rate L 40 MHz H 80 MHz Available 63 VDD Power source 4 3 3 V 64 GND GND 65 PMDO Selects input output port mode 0 Available 66 PMD1 Selects input output port mode 1 Available 67 PMD2 Selects input output port mode 2 Available 68 SPDO 5 Selects communication speed 0 Available 69 SPD1 Selects communication speed 1 Available 70 VDD Power source 43 3 V 71 GND GND 72 CLK Reference clock 73 VDD Power source 43 3 V 74 GND GND 75 DN5 Negative Device number bit 5 Available 76 DN4 Negative Device number bit 4 Available 77 DN3 Negative Device number bit 3 Available 78 DN2 Negative Device number bit 2 Available 79 DNI Negative Device number bit 1 Available 80 DNO Negative Device number bit 0 common with the Available serial input line Il 5 4 2 Terminal assignment drawings Or Xx UYU 2 DOD QQR Znnros da a z bb ss 08 Io 8 ZAN 7 E 8 DNSO P26 P25 P24 P23 P22 P21 P20 VDD GND P17 P16 P15 P14 P13 P12 P11 P10 P1N GND VDD Ki O kep z O 0 2 NM no N o a z 9 25 5 9 S 92 o Ss gI1 0 0 0 n n 017 Q a UYU 2 5 D LU DO OK EF O 2
22. Device No 0 1 Device information Device No 0 1 01011011 OB6h Device information Device No 62 63 Device information Device No 62 63 0 1011 100 OB8h 1 0 communication error flags I O communication error flags Device No an Mn Me cs SARA A 01011111 OBEh 1 0 communication error flags I O communication error flags Device No Device No 48 to 63 48 to 63 0 1100 000 OCOh Input change interrupt settings Device Input change interrupt settings Device Prec Noer MNOS ON di No Oto 3 re ri 01101111 ODEh Input change interrupt settings Device Input change interrupt settings Device No 60 to 63 No 60 to 63 0 1110 000 OEOh Input change interrupt flags Device No 0 Input change interrupt flags Device No 0 Deedee ee acne ctl eee cee CN naa i an O 1111 111 OFEh Input change interrupt flags Device No Input change interrupt flags Device No 60 to 63 60 to 63 1 0000 000 100h Port data No 0 1 Device No 0 Port 0 Port data No 0 1 Device No 0 Port 0 1 1 10000001 102h Port data No 2 3 Device No 0 Port 2 Port data No 2 3 Device No 0 Port 2 PER Man Me Ren AA ea Sana aa 3 REMI ISIS A an net Re El OO AS tence mena pal Ol ed Ne Dena an Soden ns 1 1111 111 1FEh Port No 254 255 Device No 63 Port 2 Port data No 254 255 Device No 63 3 Port 2 3 Note The hexadecimal notation for the addresses above are written with th
23. MRER Note Locate each pin number from the markings on the chip As shown in the figure above pin number 1 is at the lower left of the NPM logo mark Il 6 4 3 Complete block diagram SI SO SOEH SOEL Communication control Device number DN 5 0 DNSM Manage device DNSO number Manage level MSEL output MRER Watchdog timer T PO 7 0 P1 7 0 PMD 2 0 BEE P2 7 0 P 3 0 N P3 7 0 lhe Timing signal SPD 1 0 Clock control CLK H CKSL au Il 7 4 4 Functions of terminals 4 4 1 4 4 2 4 4 3 4 4 4 CLK This is an input terminal of the reference clock By setting of the CKSL terminal either of the following clock rate signals can be connected CKSL L 40 MHz CKSL H 80 MHz By selecting either of these clock rates the serial communication transfer rate does not change This clock rate selection affects communication precision For a small scale serial communication and transfer rate below 10 Mbps use of the center device with 40 MHz does not give any restriction With 20 Mbps transfer speed however a longer communication line or a large number of connected local devices may deteriorate communication precision due to collapse of signals on the circuit This deterioration of communication quality can be corrected inside the LSI if the deterioration level is not much In order to improve correction precision evenness of the clock duty is required In other words if the duty is ideal 50 50
24. O device output port If the system is in the middle of cyclic communication just write the data here and it will be sent automatically to the target I O device Ports 2 and 3 can be specified at the same time 16 bit CPU Outpw 0x0108h 0x1200h Outpw 0x010Ah 0x5634h Read stat Sts Inpw 0x0000h PRC If you want to confirm whether the port data you wrote has been transferred use the following routine If you don t need to check it you don t need to use this routine Data Inpw 0x0108h Get the data input from I O device port 0 This area will be filled with data automatically by cyclic communication Discard the upper 8 bits Sts Inpw 0x0114h Read ports 0 and 1 at device address 5 This area might be automatically set as the status data for the PCL device This area will be filled with data automatically by cyclic communication End IV 13 2 When using only the lower 8 bytes in the address map Outpw 0x0004h 0x1200h Put the data in the I O buffer and issue a write Outpw 0x0000h 0x5404h command Outpw 0x0004h 0x5634h Outpw 0x0000h 0x5405h In order to read port 0 on device number 2 and then Outpw 0x0000h 0x6404h read the I O buffer Data Inpw 0x0004h Discard the upper 8 bits Issue a read command to read port 0 on device Outpw 0x0000h 0x640Ah number 5 and then read the I O buffer Sts Inpw 0x1140h A read command is constructed as fol
25. Refreshed output data The I O device refreshes the received data while the output signal MSEL is LOW indicates that the data was successfully received The refresh timing will be slightly advanced or delayed depending on the data receive timing of the central device G9001 However when MSEL changes from LOW to HIGH the I O device must have already read the received data Therefore if you want to use the received data by another external device take out the data during MSEL is HIGH so that you can get reliable data Input data set timing MSEL Internal register Px 7 0 The I O device reads the data input on the ports using basically the same timing for the output data It sends the data it receives to the central device G9001 in the next cyclic communication The I O device reads the data on its input lines while MSEL is LOW To send it data from outside do so while MSEL is HIGH so that the I O device will be looking at stable data when the signal goes LOW again Also unless it is receiving cyclic communications from the central device G9001 normally the I O device G9002 will not read data that is sent to its input ports 1 14 6 External dimensions 80 pin LAFP Unit mm 0 25 TYP C 0 1 45 40 055 0 045 o BE SA pa I get Ai p gt 0 45 min Me ca 0 75 max Il 15 III Connection Examples and Recommended Environments G9000 Series IIl 1 1 2 1 Connection examples 1 1 An exampl
26. and an interrupt signal is output When data is received from a data device RDBB status register bit 10 becomes 1 so that the central device can read the data until receiving FIFO is emptied If data communication commands are written continuously further data communication will be postponed until another round of I O communications is executed once the current data communication is complete This ensures continuity in the cyclic I O communications After a local device has received data it will ignore any further data received until it has read out all of the data received and it will not send any response to the central device while reading the data The central device will generate a no response error in this case and retry the communication An example of how to write the data 01234567h to the RMV the feed amount register in a PCL device G9003 When using a 16 bit CPU 1 First write an RMV write command 0090h to the transmitting FIFO 006h 2 Next write the lower 16 bits data 4567h for the RMV register into the transmitting FIFO 006h 3 Finally write the upper 16 bits data 0123h to be sent to the RMV register into the transmitting FIFO 006h Details of the data transmitting FIFO 1st word 0090h 2nd word 4567h 3rd word 0123h When using an 8 bit CPU 1 First write the lower half of the RMV write command 90h to the transmitting FIFO 006h 2 Then write the upper half 00h of th
27. be done See the flow chart for writing command data to the FIFO Make sure the first data written sends 1184h to the FIFO This is the operation command for the CPU emulation device The CPU emulation device interprets the data received as follows 15 14 13 12 11 10 9 817 6 5 413 2 1 0 mam a ae a E Number of Processing Setting to Starting irpailione details refresh the Communication wait setting address description omitted Starting address Address to output on the address bus when the CPU emulation device is substituted for a CPU When it substitutes for a 16 bit CPU the lowest bit is ignored always 0 Address modification When the number of repetitions is set to 1 or more the CPU emulation device will repeat multiple processes continuously In this case specify how to modify the addresses that will be output for each process OX Address is fixed 10 Increment the address When an 8 bit CPU 1 When a 16 bit CPU 2 11 Decrement the address When an 8 bit CPU 1 When a 16 bit CPU 2 Processing details Specify what the CPU should do 001 Write 010 Read The description of other combined processes is omitted Number of repetitions When 0 is specified the G9004 will execute the process details one time When 1 or more is specified the G9004 will execute the operation specified in the processing details the number of repetitions 1 Now interpret
28. break frame it will output an interrupt request to the CPU 3 Write a command 1100h check all of the excluded devices and refresh the device information area 5 3 Status after reset Command 0000h Status 0001h Interrupt status 0000h I O buffer 0000h Data transmitting FIFO Undetermined Data receiving FIFO Undetermined Device information All 00h IO communication error flag All 00h Input change interrupt setting All 00h Input change interrupt flag All 00h Port data All 00h I 31 6 How to calculate the communication cycle time The calculations of the communication cycle time can be classified as follows K Communication speed figure Communication speed Mbps K 20 1 10 2 5 4 2 5 8 N Number of local devices connected B Number of bytes of data to send when sending 2 bytes of data B 2 6 1 Time required for one cycle Basic item Required time us Communication time required per local device CT 7 7XK Cycle time CT 7 4 x N us Ex Calculating the cycle time with a communication speed of 20 Mbps and 30 local devices 7 7 x 1 7 4 x 30 453 us 6 2 Time required for one complete data communication There are two types of data communications as follows 1 When there is data in the response from a local device the data length is variable 2 When there is no data in the response
29. input change interrupt will occur In the case of device data If bit 0 on input port 0 changes from 0 to 1 an input change interrupt will occur For ports other than input port 0 if the input port data changes an input change interrupt will occur the same way as it does for I O data The PCL device handles the status register 16 bits as input ports 0 and 1 and the general purpose I O terminal status register as input port 2 data using I O communication The status register consists of bits to stop operation to indicate an error has happened and to indicate an event has occurred Using the input change interrupt function the central device can output an interrupt request by changing the status of the PCL device Break function Local devices have BRK terminals By applying a HIGH to the terminal for a certain length of time to create a break signal the local device will enter the break waiting status Also the central device periodically sends a break frame sending request to the local devices every 16384 cycles in I O communication or approximately every 250 msec at 20 Mbps offering another way to make a break The local devices in break waiting status send break frames when they receive a break frame send request More than one device may send a break at once The central device recognizes the break frame and outputs an interrupt request to a CPU It also sets the BRK bit bit 1 in the status register to 1 Th
30. lon 4 MA 2 4 V HIGH output voltage Von Baya Vas 0 05 V Vor 0 4 V 4 mA LOW output current To Bi directional UF Vo 0 4V 8 mA HIGH output current loH Von 2 4 V 4 mA Il 12 5 4 AC characteristics 5 4 1 System clock Terk 1 When setting CKSL L Item Symbol Min Max Unit Freguency fcuk 40 MHz Cycle Tek 25 ns HIGH duration Ter 10 15 ns LOW duration Tor 10 15 ns Note In order to secure good communication guality use a clock offering the nearest figures to the standards above For details see the CLK section of the Terminal Function in this manual 2 When setting CKSL H Item Symbol Min Max Unit Freguency fcuk 80 MHz Cycle Tek 12 5 ns HIGH duration TCLKH 5 ns LOW duration Tor ns 5 4 2 Reset timing RST Twesti gt Tprst Torst Internal RST Item Symbol Min Max Unit Reset length Twasri 10 Clock cycles Delay time Torst 10 Clock cycles Note 1 After the internal RST goes LOW the I O device will be ready Note 2 The reset signal must last at least 10 cycles of the system clock While resetting make sure the clock signal is continuously available to the device If the clock is stopped while resetting the device cannot be reset normally 11 13 5 4 3 5 4 4 Fixed output data timing MSEL Ba an Px 7 0
31. mode 2 IF1 L IFO H Read cycle A 8 1 Tarw TRWA cs Tesrw Li TRwcs nRa Tcswr aa Twait RD TROWT A Tomo D 15 0 LL lt So TRDLD TwrHD Write cycle A 8 1 TRAN Trwa cs LTosry LJ Trwes WRQ N fa Teswr LT rar an WR L TwR J k TWRD D 15 0 S TowR Item Symbol Condition Min Max Unit Address setup time for RD WR 4 Tarw 18 ns Address hold time for RD WR T Tawa 0 ns CS setup time for RD WR 4 Tcsaw 8 ns CS hold time for RD WR T Tawcs 0 ns WRQ ON delay time for CS Teswr__ Ci 40pF 11 ns WRQ ON delay time for RD 4 Taowr CL 40pF Note 1 17 ns WRQ signal LOW time Twalt Note 2 12Tcik ns TRDLD CL 40pF Note 3 4 2Tork 24 ns Data output delay time for RD Ci 40pF Note 5 5g Twrko CL 40pF Note 4 0 ns D ata output delay time for WRQ T Ci 40pF Note 5 i0 Data float delay time for RD T Troup C 40pF 28 ns WR signal width TWR Twr Note 6 14 ns Data setup time for WR T Towr 22 ns Data hold time for WR T Twro 0 ns Note 1 Only when reading memory area address 078h to 1FFh WRQ LOW will be output by RD LOW Note 2 When CKSL LOW or CKSL HIGH the WRQ signal LOW level will be held for 24 x Terk Note 3 When CKSL LOW or CKSL HIGH the data output delay time will be 4Tcik 24 Not
32. or data communication is complete and the next chunk of data can be sent to the transmitting FIFO buffer this bit becomes 1 and the central device outputs an interrupt signal INT Once the status of this bit is read it returns to 0 BRKF When the central device receives a break frame this bit becomes 1 and an interrupt signal INT is output Once the status of this bit is read it returns to 0 IOPC Becomes 1 when any input port which had enabled the input change interrupt setting and that status changed The central device then outputs an interrupt signal INT This signal is an OR of all 256 input port change interrupt flag bits When all the bits return to 0 this bit returns to 0 EIOE Becomes 1 when an I O communication error occurs The central device then outputs an interrupt signal INT This signal is an OR of all 64 I O communication error flag bits When all the bits return to 0 this bit returns to 0 EDTE Becomes 1 when a data or system communication error occurs The central device then outputs an interrupt signal INT Once the status of this bit is read it returns to 0 ERAE Becomes 1 when a local device reception processing error occurs The central device then outputs an interrupt signal INT Once the status of this bit is read it returns to 0 Then the device number and details where the reception processing error occurred can be checked by reading the interrupt status Note
33. possible while maintaining the proper conditions for soldering Package body temperature C Max peak temperature 260 C CERA Eta at AA Less than 10 seconds at 250 C Preliminary heating 140 to 200 C 60 to 120 sec Main heating 220 C or higher Less than 35 sec Time A profile applied to lead free soldering 4 Solder dipping causes rapid temperature changes in the packages and may damage the devices Therefore do not use this method VI 2 3 2 I O device G9002 1 In order to prevent damage caused by static electricity pay attention to the following Make sure to ground all equipment tools and jigs that are present at the work site Ground the work desk surface using a conductive mat or similar apparatus with an appropriate resistance factor However do not allow work on a metal surface which can cause a rapid change in the electrical charge on the LSI if the charged LSI touches the surface directly due to extremely low resistance When picking up an LSI using a vacuum device provide anti static protection using a conductive rubber pick up tip Anything which contacts the leads should have as high a resistance as possible When using a pincer that may make contact with the LSI terminals use an anti static model Do not use a metal pincer if possible Store unused LSIs in a PC board storage box that is protected against static electricity and make sure there is adequate clearance betwe
34. reading buffer and then reads the data from this buffer In order to secure the necessary data transfer time 2 clock cycles at 40 MHz the central device outputs WRQ L in response to RD L when reading the memory area Please note the output delay time for reading data For details about the output delay time see section 7 4 AC characteristics in the G9001 manual 1 2 2 Access by commands The central device has 9 address terminals used to access 512 bytes of Memory The access timing for each of these addresses is shown below However for certain CPUs this amount of memory is not directly available In this case just use three address terminals to access 8 bytes in the central device When addressing in this fashion commands are used to access addresses beyond the basic 8 bytes The access timing used to access the memory area in the central device with commands is different from the method used for direct memory address However CPU s with a wait function don t need to be aware of these timing requirements since they use the WRQ terminal on the central device For CPUs that don t have a wait function monitor the IFB output or use software to observe the timing described below this is essential 1 2 2 1 Write operation command The operation commands shown below commands that don t need data such as Start and Stop use the write timing to write continuously to the command area address 1 when the I F mode 4 The
35. sets the status register data communication system communication error occurrence bit EDTE to 1 and stores the device number which has an error EDNO to 5 in the interrupt status register The CPU checks the data communication system communication error interrupt status when an interrupt occurs and then reads the interrupt status bits EDNO to 5 to determine which device has an error and whether the local device received data or not LNRV The interrupt signal is reset when the interrupt status is read 3 Other error processing 1 When a local device detects an error in the receiving frame such as a CRC error it does not respond 2 When any of the following errors occurs in a local device it sends notice of the error to the central device in a response frame In YO communication a local device receives a frame that is different from the I O setting PMD terminal setting in case of an I O device An I O device receives a data communication frame A data device receives a frame larger than the receiving buffer capacity 3 If the communication line does not change after 20 usec or longer when communicating at 20 Mbps after the central device has finished sending data it concludes that the local device could not receive the data In data communications and system communications the central device attempts sending the data three times During this time it also attempts to reestablish communications by inserting on
36. signal SIB receiving circuit Memory area Data transfer Transfer processing circuit Serial signal transfer circuit 4 4 Functions of terminals 4 4 1 4 4 2 4 4 3 CLK This is an input terminal of the reference clock By setting of the CKSL terminal either of the following clock rate signals can be connected CKSL L 40 MHz CKSL H 80 MHz By selecting either of these clock rates the serial communication transfer rate does not change This clock rate selection affects communication precision For a small scale serial communication and transfer rate below 10 Mbps use of the center device with 40 MHz does not give any restriction With 20 Mbps transfer speed however longer communication lines or a large number of connected local devices may deteriorate communication precision due to collapse of signals on the circuit This deterioration of communication guality can be corrected inside the LSI if the deterioration level is not much In order to improve correction precision however evenness of the clock duty is required In other words if the duty is ideal 50 50 the capacity to correct collapse of the signals in the communication lines can be improved On the contrary if the duty is not ideal the center device cannot cope with collapses of the communication line As a result if the duty is close to ideal the center device can be used with 40 MHz When connecting more than one oscillator the duty will n
37. system will have greater resistance to electrical noise If pulse transformers are not used the transmission distance may be less We used 1000 uH transformers in our experiments 2 4 I F chip We selected I C chips with specifications better than the RS485 standard In the experiment we used 5 V line transceivers When 5 V line transceivers are used level shifters are needed to make the connections 1 17 2 5 Parts used in our experiments Show below is alist of the parts used in the interface circuits of our experiments Use of other parts may change the system s response This list is only for your reference Parts Manufacturer Model name CAT5 Oki Wire Co Ltd F DTI C5 SLA CAT6 Oki Wire Co Ltd DTI C6X Pulse transformer JBC Co Ltd DP101 102F Line transceiver TEXAS INSTRUMENTS SN75LBC180AP Level shifter TEXAS INSTRUMENTS SN74LVC244ADB 2 6 Other precautions Cables When you are planning long distance transmission cable quality will be the single most important factor Specialized cables designed for use as field buses such as those by CC Link and LONWORKS have guaranteed quality and may be easier to use Pulse transformers Needless to say the pulse transformers should handle 20 Mbps 10 MHz without becoming saturated The transformer s inductance is also important Since up to 64 pulse transformers may be connected the actual working specifications of these devices must
38. the capacity to correct collapse of the signals in the communication lines can be improved On the contrary if the duty is not ideal the center device cannot cope with collapses of the communication line As a result if the duty is close to ideal the center device can be used with 40 MHz When connecting more than one oscillators the duty will not be ideal In this case select 80 MHz The central device divides the frequency inside and creates 40 MHz frequency If you do not want to 80 MHz frequency you may prepare a separate 40 MHz oscillator for this LSI RST This is an input terminal for a reset signal By input L level signal the central device is reset As the central device synchronizes with a clock arrange a circuit so that it does not disconnect the clock while resetting Reset signal length longer than 10 clock cycles is required CKSL Use to select clock rate L Connect 40 MHz clock frequency to the CLK terminal H Connect 80 MHz clock frequency to the CLK terminal Select this when the duty of the 40 MHz clock collapses too much DNO to DN5 Input terminals for setting device address Since these terminals use negative logic setting all the terminals to zero calls up device address 3Fh There are two methods for entering a device address Select the input method using the DNSM terminal Il 8 4 4 5 DNSM Select the input method for loading the device address 1 When the DNSM H Specify an address
39. the central device should be pulled up 111 6 1 1 5 Connecting to a CPU without a wait function The central device can be connected to a CPU that does not have a wait function Lets look at an example with the CPU interface using I F mode 4 while it is connected to an Intel 8031 8 bit CPU Since this CPU does not have a terminal for executing a wait function care is needed when programming VDD 8031 intel A8 to A15 A9 to A15 P2 0 to P2 7 IF1 IFO ALE PO 0 to PO 7 System reset Points 1 Set IF1 H and IFO H I F mode 4 2 Since the 8031 does not have a wait terminal the WRQ terminal cannot be used However some waiting time is needed to be able to access the central device since it takes some time to finish processing a command and a wait function is therefore essential for continuous access operations In the example above the IFB output terminal on the central device is connected to a port on the 8031 The IFB bit is monitored using a routine in the 8031 so that the 8031 does not try to access the central device while it is processing a command Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows A3 to A15 Connect these lines to the decoding circuit and use them to create the CS signal A0 to A2 Connect these lines to AO to A2 on the central device A3 to A8 on the central device should be connected
40. to 256 ports 2048 bits for I O connection The center device provides input interrupt function to a CPU Local devices are classified into the following devices YO device dedicated to control I O port PCL device to generate pulse strings CPU emulation device to control data communication between CPUs and other peripheral equipment Local devices are allocated device numbers 0 to 63 with hardware These device numbers can be assigned at random in a Motionnet system Further by system communication device numbers can automatically be allocated The center device is integrated with a memory for I O ports Thus the center device can operate I O status just like accessing normal memories The center device is integrated with four types of CPU I F circuits Z80 8086 H8 68000 etc As it applies for typical CPU interfaces it will offer wide possibility to interface with a variety of CPUs The center device normally uses 512 bytes area as address area However if resource is shorted it can use 8 byte areas Input 3 3 V single power as power supply However the major terminals can be connected to devices that run with 5 V 3 General specifications 3 1 Communication system specifications Item Description Reference clock Note 1 40 MHz or 80 MHz Communication speed Note 2 2 5 M 5 M 10 M or 20 Mbps Communication sign NRZ sign Communication protocol NPM origin
41. to GND Note 2 Pull up D8 to D15 to VDD externally 5 to 10 K ohms 1 7 1 2 Access timing 1 2 1 Normal access The central device has 9 address terminals used to access 512 bytes of memory The access timing for each of these addresses is shown below CPUs that have a wait function can be connected to the WRQ terminal on the central device so that they can be used without special concern for signal timing However CPUs without a wait function must monitor the IFB output or use one of the following timing schemes this is essential 1 2 1 1 Write to the I O buffer or the data transfer FIFO The timing for writing to the I O buffer address 4 and 5 when I F mode 4 or the data transfer FIFO address 6 and 7 when I F mode 4 is shown below A wait time is necessary to perform continuous writing The wait must be 4 clock cycles or longer at 40 MHz 1 Does not use the WRQ output CPU does not have a wait function Address Next address a a DATA _ wait of 4 clock cycles or longer at 40 MHz must be inserted by the CPU software 2 Uses the WRQ output CPU has a wait function Address SO Tn In o WRQ 7 DATA The CPU automatically waits for the required period of time 111 8 1 2 1 2 Writing to a memory address The timing for writing to the memory area 078h to 1FFh with I F mode 4 is shown below A wait time is necessary to perform continuous writing The wait must be 6 clock cycles or lo
42. 1 bit left to create the read Add 0x00e0h WORK address Data Inpw Add Read the contents of the address that was created Input change YES The bit positions which are HIGH correspond to device and port numbers whose input has changed In this step process all the flags that have become re HIGH the other flags do not need to be processed Process specified by the user Write back the data you just read in order to clear the Outpw Add Data change interrupt flag Loop Loop 1 Although this example checks the interrupt flags on all the addresses by using loop processing you can check just the areas required Note 1 In the address creation step above the program shifts the LOOP variable one bit left 2x This is because the address number to read increases by 2 each time the loop is executed Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 4 16 IV 9 2 When using only the upper 8 bytes in the address map Assume that the routine is started by an interrupt being issued INT LOW Sts Inpw 0x0000h Read the status data in the central device LOOP 0 WORK LOOP lt lt 3 Note 1 Com 0x6300h or WORK Outpw 0x0000h Com eae loop variable 3 bits left to create the read Data Inpw 0x0004h Read the contents of the target address using the command that was just created N
43. 11 B Bit 1 on port 1 Available 26 P12 B Bit 2 on port 1 Available 27 P13 B a Bit 3 on port 1 Available 28 P14 B Bit 4 on port 1 Available 29 P15 B Bit 5 on port 1 Available 30 P16 B Bit 6 on port 1 Available 31 P17 B Bit 7 on port 1 Available 32 GND GND 33 VDD Power source 43 3 V 34 P20 B Bit 0 on port 2 Available 35 P21 B Bit 1 on port 2 Available 36 P22 B Bit 2 on port 2 Available 37 P23 B Bit 3 on port 2 Available 38 P24 B Bit 4 on port 2 Available 39 P25 B Bit 5 on port 2 Available 40 P26 B Bit 6 on port 2 Available 41 P27 B Bit 7 on port 2 Available 42 VDD Power source 43 3 V 43 GND GND 44 P30 B Bit 0 on port 3 Available 45 P31 B Bit 1 on port 3 Available Il 4 No Signal name I O Logic Description 5 V interface 46 P32 B Bit2 on port 3 Available 47 P33 B Bit 3 on port 3 Available 48 P34 B Bit 4 on port 3 Available 49 P35 B Bit 5 on port 3 Available 50 P36 B Bit 6 on port 3 Available 51 P37 B Bit 7 on port 3 Available 52 GND GND 53 VDD Power source 43 3 V 54 PON Negative Ka Sets P20 to P27 to use negative Available 55 P3N Negative ae Sets P30 to P37 to use negative Available 56 SOEI Positive Enables serial output 57 BRK Positive Reguests a break frame to be sent
44. 40 MHz clock proprietary to the center device To select clock rate specify using the LSI terminal In either clock rate the maximum speed of 20 Mbps is the same Note 2 Select the communication speed using the LSI terminal Regardless of the selection of the communication speed the reference clock remains the same Note 3 NPM recommends using a system with a pulse transformer Note 4 The number of I O ports in the parenthesis is true when the all the connected local devices are connected as I O device When data devices are connected such as PLC device the number of available I O points will be decreased However basic cyclic cycle alt frequency does not change When the center device communicates data the frequency will be changed For this matter see the Calculation of communication time in this manual 3 2 Center device specifications G9001 Item Description Address area Normally it uses 512 bytes area A0 to AB However 8 bytes area A0 to A2 can be used when using the I O buffer Note Address map Address h Writing Reading 000to 001 Command Status 002 to 003 Invalid Interrupt status 004 to 005 I O buffer I O buffer 006 to 007 Data sending FIFO Data receiving FIFO 008 to 077 Not specified 112 bytes ci specified 112 ytes Device information 8 bits Device information 8 078t0 0B7 device bits de
45. 6 4 IV 11 2 When using only the upper 8 bytes in the address map WORK LOOP lt lt 5 Com 0x6100h or WORK Outpw 0x0000h Com Data Inpw 0x0004h Process specified by the user Com 0x5100h or WORK Communication error Outpw 0x0004h Data Outpw 0x0000h Com LOOP LOOP 1 YES Note 2 LOOP lt 4 Assume that the routine is started by an interrupt being issued INT LOW Read the status data in the central device Note 1 Shift the loop variable 5 bits left to create the read address Read the contents of the target address using the command that was just created The bit positions which are 1 correspond to device and port numbers whose input has changed In this step process all the flags that are 1 the other flags do not need to be processed Write back the data you just read in order to clear the change interrupt flag Note that the command is different from the one used to read the data Although this example checks the interrupt flags on all the addresses by using loop processing you can check just the areas required The read command is constructed as follows 10 9 15 14 13 12 11 8 7 413 2 1 0 0 1 1 0 0 0 0 F 0 6 5 I IXIXIXIX amp When writing data used to clear the flags these bits become 0101 Specify the address in these 6 bits
46. After writing a read command the central device reads data from the I O buffer After a read command is sent the central device needs an interval of 8 reference CLK cycles at 40 MHz before the data can be read by the CPU When reading data from the I O buffer there is no restriction on the timing It can be read in any order Read commands must be written low bit to high bit order When the WRQ terminal is connected to the wait terminal on the CPU the timing is controlled automatically by the CPU s wait control function Read data from the memory Next operation Address CS WR RD po a re A Data Command A wait of 8 clock cycles at 40 MHz 11 12 1 3 Line transceiver and pulse transformer for the central device To make connections for serial communication use RS 485 line transceivers driver receiver and pulse transformers 1000 uH or equivalent Connect the line transceivers as shown below On a transmission line connect terminating resistors suitable for the cable impedance 100 ohms or similar The position of the terminating resistor can be either before or after the pulse transformer The same effect will be obtained at either position When using a 5 V line driver receiver ICs such as a level shifter are needed to assert signals on lines such as SO SOEH and SI Line transceiver 3 3 V Note 3 Terminating Pulse transformer resistor 1000 uH or Serial line 1 Line
47. F1 H IFO L 8086 type CPU VDD ALE latch A16 to A19 Pad ADO to AD15 te lt circuit IF1 IFO System reset System reset Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows Address signal as used in this example refers to signals output from the latching circuit A3 to A19 Connect these lines to the decoding circuit and use them to create the CS signal A0 to A2 Connect these lines to AO to A2 on the central device Connect A3 to A8 on the central device to GND 1 4 1 1 3 I F mode 3 IF1 L IFO H H8 type CPU Decoding WRQ DO to D15 RST System reset Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows A3 to A15 Connect these lines to the decoding circuit and use them to create the CS signal A0 to A2 Connect these lines to AO to A2 on the central device A3 to A8 on the central device should be pulled up 1 5 1 1 4 I F mode 1 IF1 L IFO L 68000 type CPU IF1 GND control circuit System reset Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows A3 to A23 Connect these lines to the decoding circuit and use them to create the CS signal AO to A2 Connect these lines to AO to A2 on the central device A3 to A8 on
48. Motionnet G9001 G9002 Center device I O device User s Manual NP Nippon Pulse Motor Co Ltd Preface Thank you for considering our super high speed serial communicator LSI the G9000 To learn how to use the G9000 read this manual to become familiar with the product The handling precautions for installing this LSI are described at the end of this manual Make sure to read them before installing the LSI What Motionnet is As a next generation communication system the Motionnet can construct faster and more volume large scale systems with wire saving than conventional T NET system conventional LSI product to construct serial communication system by NPM Further it has data communication function which the T NET does not have so that it can control data control devices such as PCL series pulse train generation LSI made by NPM The Motionnet system consists of one center device connected to a CPU bus a maximum of 64 local devices all connected using cables of two or three conductive cores Cautions 1 Copying all or any part of this manual without written approval is prohibited 2 The specifications of this LSI may be changed to improve performance or quality without prior notice 3 Although this manual was produced with the utmost care if you find any points that are unclear wrong or have inadequate descriptions please let us know 4 We are not responsible for any results that o
49. O Negative Interrupt request Available 38 WRQ O Negative Wait request Available 39 IFB O Negative CPU I F is busy Available 40 MCRY O Negative By detecting a communication line Available signal this signal becomes L for a rated interval 41 MERR O Negative When received an error frame and no Available response this signal becomes L level for a rated interval 42 GND O GND 43 MERF O Negative When receiving an error response Available frame this signal becomes L level for a rated interval 44 MSYN O Negative The level reverses at each cyclic cycle Available 45 SOEL O Negative Enable serial output 46 SOEH O Positive Enable serial output 1 6 Signal name I O Logic Description 5V interface 47 SO O Positive Serial output 48 VDD 43 3 V power input 49 SPDO Communication speed setting bit 0 Available 50 SPD1 Communication speed setting bit 1 Available 51 SIA Positive Serial input A 52 GND GND 53 VDD 43 3 V power input 54 SIB Positive Serial input B 55 GND GND 56 CKSL Clock selection L 40 MHz H 80 MHz Available 57 GND GND 58 CLK 2 Reference clock 59 VDD 43 3 V power input 60 GND GND 61 GND GND 62 GND GND 63 RST Negative Reset 64 VDD 43 3 V power input Note 1 I in the I O column is for input O is output and B
50. PCL device 8 bytes FIFO and the PCL device returns receipt process error format error 4 4 19 MSYN This is a monitor output of cyclic communication cycle Each time a cyclic communication cycle ends this signal level changes between L and H 1 13 4 5 Address map Address map 1 I F mode 4 Please be aware of Notes 1 and 2 while accessing AO to A8 Writing Reading 000000000 000h Command bits 0 to 7 Note 1 Status bits 0 to 7 0 0000 0001 001h Command bits 8 to 15 Note 1 Status bits 8 to 15 0 0000 0010 002h Invalid Interrupt status bits 0 to 7 00000 0011 003h Invalid Interrupt status bits 8 to 15 00000 0100 004h Input output buffer bits 0 to 7 Input output buffer bits 0 to 7 0 0000 0101 005h Input output buffer bits 8 to 15 Input output buffer bits 8 to 15 0 0000 0110 006h Data transfer FIFO bits 0 to 7 Note 1 Data receiving FIFO bits 0 to 7 Note 2 0 0000 0111 007h Data transfer FIFO bit 8 to 15 Note 1 Data receiving FIFO bits 8 to 15 Note 2 9 sa 1000 008h Not defined 112 bytes Not defined 112 bytes 0 0111 0111 077h Any data written here will be ignored Always read as 00h 0 0111 1000 078h Device information Device No 0 0 1011 0111 0B7h Device information Device No 63 Device information Device No 63 0 1011 1000 OB8h I O communication error flags I O communication error flags kenggnganan ll Device NO O to 7 h Bevice N
51. al method Communication method Half duplex communication Communication I F Note 3 RS 485 or pulse transfer Connection method Multi drop connection Number of local devices 64 devices max Cyclic communication cycle when 20 Mbps When using 8 local devices IN 128 points OUT 128 points 0 12 msec Note 4 When using 16 local devices IN 256 points OUT 256 points 0 24 msec When using 32 local devices IN 512 points OUT 512 points 0 49 msec When using 64 local devices IN 1024 points OUT 1024 points 0 97 msec Note 1 When transferring data with 20 Mbps speed and if the clock duty can be maintained to ideal 50 50 condition the center device can be operated by inputting 40 MHz clock signal The above ideal conditions mean that an oscillator and the center device are connected as 1 1 and close to each other Actually even these conditions cannot establish 50 50 However a duty approximate to the ideal one will be established Even if the ideal duty is broken a little when signal lines are shorter and or the number of local devices is smaller the center device can operate without any trouble For the details see the section for the CLK terminal When the signal lines are longer and or the number of connected local devices is greater and if it is difficult to warranty the clock duty you should take measures such as preparing an 80 MHz signal or preparing a
52. ar I O communication errors If the same device number reports the same fault 3 times in a row in cyclic communication an error occurs This section describes how to check and clear this I O communication error 1 When the whole address map can be used Assume that the routine is started by an interrupt being issued INT LOW Read the status data in the central device Sts Inpw 0x0000h Note 1 WORK LOOP lt lt 1 Shift the loop variable 1 bit left to create the read address Add 0x00B8h WORK Read the contents of the address that was just created Data Inpw Add Bit positions which are 1 correspond to device numbers Communication AH where an I O communication error has occurred error In this step process all the flags that are 1 the other Process specified by the user flags do not need to be processed Outpw Add Data LOOP LOOP 1 Write back the data you just read in order to clear the change interrupt flag Although this example checks the interrupt flags on all the addresses by using loop processing you can check just the areas required Note 1 In the address creation step above the program shifts the LOOP variable one bit left 2x This is because the address number to read increases by 2 each time the loop is executed Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 1
53. ccur from using this LSI regardless of item 3 above l Genter device 121010 T aa Rae ata l 1 IT OULI net osn da lla ananda nahan ala 1 3 2 Features iano E a AE E e ae aa aa E E E EE A E aa 1 3 3 General specificationS Woo siennes l 4 3 1 Communication system specifications WWW manek 1 4 3 2 Center device specifications G9001 WWW WWW WWW mnnnekn 1 5 4 Hardware description sisi 1 6 4 1 A list of terminals QFP 64 WWW W W W W anakanak 1 6 4 2 Terminal allocation diagramme l 8 4 3 Entire block diagram sisi I 9 4 4 Functions of terminals Wo WWW mann I 10 AANG GE RE ae pena PPE CECE PTO RS ea ee a ri di ne e ere i a I 10 AD ERM SR dente ca ia aaa e a I 10 44 31 OKOL Sawa eee ae RRR RAR Ran GAS Cae ee i a I 10 4 4 4 IFO Flos ssaa ERA RARE RELA REA Ra Rsa RAR RARA ARA RA AA l 11 4 4 5 CS l 11 4 4 6 RD WR AO and WRQ iii l 11 4 4 7 INT iii l 11 4 4 8 VFB EE l 11 4 4 9 MA to AB l 11 4 4 10 DO to D7 iii l 11 4 4 11 D8 to D15 i I 12 4 4 12 SPDO SPDI1 ASEE EESSEEEEASEEEEASEEEEESEE EEES SEE EEES E Ennen EEEE l 12 4 4 13 SO I 12 4 4 14 SOEH SOEL i I 12 4 4 15 SIA SIB ii I 12 44 16 MGRY cise eb ee BE AA III II AGO GI la I 13 4 4517 MERR sana ial catalogs i ails I 13 44 18 MERE aka A aa I 13 4 4 19 MSYN been tea ea SA Ak Ales I 13 4 5 Address Map ena ANN NN SNN an l 14
54. cks the read status EDTE flag If a Dev Sts Inpw 0x0000h communication error occurs the next process should not be started If there is no error the PCL6045A B will begin En 17 gt operation In this step it is not clear if the PCL6045A B is YES operating or not Error processing IV 19 Sts 28h Inpw 0x01A0h Outpw 0x0006h 0x0400h Outpw 0x0000h 0x4028h Dev Sts Inpw 0x0000h Error processing G9004 status bit 1 in this case eguivalent to port 0 indicates whether reception by the local devices is complete When the G9004 completes all the processes specified this bit becomes 1 In other words this will mean that the PCL6045A B has definitely started operation if there is no problem with the command data Put a reset instruction command for the local receive processing complete flag in the FIFO Write a data communication command send the command data stored in the FIFO When CEND HIGH and EDTE 0 the local device flag has been reset IV 20 For a detailed description of the G9004 CPU emulation device see the user s manual In this paragraph a simple explanation will be provided following the example above Assume that the G9004 is substituting for a 16 bit CPU Let the CPU emulation device substitute for a CPU The description of how to set the external terminals on the CPU emulation device is omitted The present subject is how to define the CPU operation to
55. communication cyclic communication In YO communication the central device communicates continuously to perform I O control of the I O devices This communication takes place in cycles Communication starts with the local device that has the lowest device number and proceeds through all the devices that are present When the 1 27 3 communication with the device that has the highest number is complete the central device again starts to communicate with the local device that has the lowest device number If the communication target is a data device it exchanges information such as device status By writing an I O communication start command the central device communicates only with devices whose device information bit is set to 1 This communication continues until an I O communication stop command is written Data communication In data communication the central device communicates with other data devices such as the PCL G9003 device Normally the central device executes cyclic I O communications continuously A data communication command from a CPU allows you to perform data communications by interrupting the cyclic I O communications After writing data to the data transmitting FIFO write a send data command The central device will start the data communication on an interrupt when the current I O communication is complete When the data communication is complete the CEND bit 0 in the status register changes to 1
56. ction when you want to reduce the number of addresses used in this device Note For all bits marked with a the upper bits of the device address should be set in order starting from the left end of the bits For bits marked with an amp when the port is 0 or 1 set the bit to 0 When the port is 2 or 3 set the bit to 1 For bits marked with an x either 0 or 1 may be used If all of the address map byte 512 bytes requested by the central device are allocated so that a CPU can see them the commands from 5000h and after as shown above are not needed If the resources controlled by a CPU are limited and only 8 bytes are available for addresses the commands from 5000h and up can be used to access to all of the addresses owned by the central device 1 26 5 Description of the software 5 1 Outline of control 5 1 1 Communication control The central device controls all the communications One communication cycle consists of a communication from the central device to the local devices and the communication from the local devices back to the central device The response from the local devices may include I O information and data 5 1 2 Communication type System communications I O communications and data communications are the three communication types available 1 System communications System communications automatically confirm the connection status device type and I O port se
57. ded operating conditions ltem Symbol Rating Unit Power supply voltage Voo 0 3 10 V Input voltage Vin Vss to Von V Input voltage 5V 1 F Vin Vss to 5 5 V Storage temperature Ta 40 to 85 G 7 3 DC characteristics Item Symbol Condition Min TYP Max Unit Current consumption laa CLK 80 MHz 45 mA Output leakage current loz 1 1 uA Input capacitance 10 pF LOW input current In 1 uA HIGH input current lHL 1 uA LOW input current Vi 0 8 V HIGH input current Vin 2 0 V LOW output voltage VoL lou 6 MA 0 4 V HIGH output voltage Vo lon 6 MA Voo 0 4 V LOW output current lo Vor 0 4 V 6 mA HIGH output current lou Von Voo 0 4 V 6 mA Internal pull up resistance Rup 20 120 K ohm 1 33 7 4 AC characteristics 7 4 1 System clock Terk 1 When setting CKSL L Item Symbol Min Standard Max Unit Freguency fcuk 40 40 MHz Cycle Tok 25 25 ns HIGH duration Teteh 10 12 5 15 ns LOW duration Tor 10 12 5 15 ns Note In order to secure good communication guality use a clock offering the nearest figures to the standards above For details see the CLK section of the terminal function in this manual 2 When setting CKSL H Item Symbol Min Standard Max Unit Freguency fcuk 80 MHz Cycle Tek 12 5 ns HIGH duration Teuku ns LOW duration TeLkL ns 7 4 2 Reset timing RST Twrsti rr 1
58. demam r ere a iar a aan Il 10 44 14 S AAT a a ain Da NN NN Il 10 4 4 15 MEER he r a a eed Il 10 44 16 MSEL ct RADI IA Il 10 4 4 17 BRK i RR IRR OI E An Il 10 4 4 18 PMDO to PMD2 kecca a a e es Il 11 4 4 19 PON PIN P2N PSN aa a a e a a Il 11 4 4 20 POO to 07 P10 to 17 P20 to 27 P30 to 37 Il 11 4 5 otat s after restanu ae a ira ie cia nana iaia hai iaia aaa uao Il 11 5 Electrical CharaCteriSti Santan maan a aa Baung E aan 11 12 5 1 Absolute maximum ratings sise 11 12 5 2 Recommended operating conditions 11 12 5 3 DO characteristics Massa agama de ii send ananda ama 11 12 5 4 AC CharacteriStiCS asu anni Basa ana ana done Dana ana Da ai ag 11 13 5 4 1 SYSTEM clock ia aa alone ala se lacune aan ea ia debate 11 13 5 4 2 Reset timing bi dana Rona Bap a i naga amahnaya nasi 11 13 5 4 3 Fixed output data timing iii 11 14 5 4 4 Input data set TIMING Mann ian mo sasee anoman anon aman 11 14 6 External dimensions ii iii Wo W W Wen an ane ea ane Il 15 Ill Connection Examples and Recommended Environments ooooooWo 1 1 1 Gonnection examples fist li ata lek ll nan be nan aan ale 111 3 1 1 An example of a circuit to interface a CPU to a central device Woo 1 3 1 1 1 I O mode 4 IF1 H IFO H iii III 3 11220 modes IF4 H IF0 LE aya an ai sa sa ee eA 1 4 T 1 3 YO mode 3 FI 55 IOS HI aer hati batam o aa eel 1 5 1 1 4 1 0 mode T IFT ls IF O E saci eta dna aan asa aa ana
59. e status of a device to make sure that port 0 is not monitoring all the bits For details about which status information corresponds to which port see the user s manual for each data device For examples of use see point 2 in the Change In Input Interrupt Setting section of Software Examples in Chapter IV 1 20 4 5 4 Change In Input Interrupt Flag area If a port has been specified in the area for setting Change In Input Interrupts when its port status changes the central device will issue an interrupt to a CPU and change the bit to a 1 The interrupt allows the CPU to determine the device number and port number or status which changed by reading this area Ex To monitor port 2 on device number 0 To read the status of device number 0 you must access address OEOh Port 3 Port 2 Port 1 Port 0 For a 16 bit CPU address OEOh 15 14 13 12 11 10 9 817 6 5 4AN 3 2 1 0 Device No 3 Device No 2 Device No 1 Device No 0 4 bits correspond to each local device The lower 4 bits are the Input Interrupt Setting area of the local device with the lowest address number The lowest bit among these 4 corresponds to port 0 the next bit corresponds to port 1 and so forth To check other local devices specify the address by using the following rule discard any remainder Address 0EOh device number 2 The procedure is the same for an 8 bit CPU e
60. e 4 When reading memory address addresses 078h to 1FFh Note 5 When reading non memory addresses addresses 078h to 1FFh Note 6 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until WR goes HIGH 1 37 7 4 6 I F mode 1 IF1 L IFO L Read cycle A 8 1 DES cs Tsa a LS A0 R W WR kl Tscs Tsrw ACK WRQ Tess TRws TSLAKR TSHAKR D 15 0 TDAKLR Write cycle ya Tcss LS AO Tsrw AN WR TSLAKW TSHAKW ACK WRQ Toa D 15 0 rr TAKDH Item Symbol Condition Min Max Unit Address setup time for LS The 17 ns Address hold time for LS T Tes 0 ns CS setup time for LS 4 Tes 10 ns CS hold time for LS T Tees 0 ns R W setup time for LS 4 Taws 2 ns R W hold time for LS T Tsaw 14 ns TSLAKR C 40pF Note 1 2Tcir 14Tak 15 ns ACK ON delay time for LS Tsiaw Ci 40pF Note 2 2Toig i 10Toix 15 ns TsHaxr Ci 40pF 7 ns ACK ON delay time for LS T Toman Ci 40pF 7 n Data float delay time for ACK 4 Toar Ci 40pF Note 3 2Tcik ns Data float delay time for LS T Tso C 40pF 14 ns Data setup time for LS T Tost 22 ns Data hold time for ACKL TAKDH 0 ns Note 1 When CKSL LOW or CKSL HIGH the ACK signal LOW level will be held for MIN 4 x Tork MAX 28Tcik 15
61. e Device No Input port Output ports 1 I O device 10 Port 0 Port 1 to 3 2 PCL device 11 Port 0 to 2 Port 3 3 YO device 20 Port 0 to 2 Port 3 Note The port attributes of the PCL device are fixed Input ports 0 and 1 contain status information 1 When the whole address map can be used all 512 bytes Specify device data for device numbers 10 and 11 Outpw 0x0082h 0x8B81h h i Specify device data for device number 20 Outpw 0x008ch 0x0083h Be careful not to corrupt the data for device number 21 Outpw 0x0000h 0x3000h Start cyclic communication For information about device data values see section 5 1 2 in Chapter I With a PCL device this value is always 8Bh IV 5 2 When using only the lower 8 bytes in the address map The details in the central device that can be seen by an external CPU are from the command area to the data transmission reception FIFOs Use commands to access other areas Specify the device data for device numbers 10 and 11 To set the data write the data to the I O buffer Then issue a write command to the target s device number area Outpw 0x0004h 0x8B81h Outpw 0x0000h 0x5014h Outpw 0x0004h 0x0083h Outpw 0x0000h 0x5028h Specify the device data for device number 20 Be careful not to corrupt the data for device number 21 Outpw 0x0000h 0x3000h A write command is constructed as follows Start cyclic communication 15 14
62. e RMV write command to the transmitting FIFO 007h 3 Next write bits 0 to 7 67h for the RMV register into the transmitting FIFO 006h 4 Next write bits 8 to 15 45h intended for the RMV register into the transmitting FIFO 007h 5 Next write bits 16 to 23 23h to be sent to the RMV register into the transmitting FIFO 006h 6 Finally write bits 24 to 31 01h for the RMV register into the transmitting FIFO 007h Details of the data transmitting FIFO 1st byte 90h 2nd byte 00h 3rd byte 67h 4th byte 45h 5th byte 23h 6th byte 01h 1 28 5 1 3 5 1 4 5 1 5 Input change interrupt When the status of an input port changes the central device can output an interrupt request to a CPU A bit corresponding to any input port number whose status changed can be set to 1 in the interrupt setting register And if the input port data changed while receiving I O communication data the central device will output an interrupt request to a CPU and it will change the bit in the input change interrupt flag register which corresponds to the input port number to 1 Then the CPU checks the input change interrupt status IOPC 1 when an interrupt occurs and reads the input change interrupt flag to identify which input port changed By writing back the flag data just read the interrupt can be reset In the case of an I O device If the input port data changed while receiving I O data an
63. e assumption that AO 0 1 16 Address map 3 I F mode 1 2 A1 to A8 Writing Reading 11111 111 1FFh Command bits 0 to 15 Status bits 0 to 15 1 1111 110 1FCh Invalid Interrupt status bits 0 to 15 11111 101 1FAh Input output buffer bits 0 to 15 Input output buffer bits 0 to 15 1 1111 100 1F8h Data transfer FIFO bits 0 to 15 Data receiving FIFO bits 8 to 15 1 1111 011 1F6h Not defined 56 words Not defined 56 words 1 1000 100 188h Any data written here will be ignored Always read as 00h 11000011 186h Device information Device No 0 1 Device information Device No 0 1 10100 100 148h Device information Device No 62 63 Device information Device No 62 63 1 0100 011 146h I O communication error flags I O communication error flags Device No Ct RE Device No 0 to 15 101018 10100 000 140h I O communication error flags T I O communication error flags Device No Device No 48 to 63 48 to 63 1 0011 111 13Eh Input change interrupt settings Device Input change interrupt settings Device Dee e Mine ilo Oa ea an Tr ll Notons cr nr 10010000 120h Input change interrupt settings Device Input change interrupt settings Device No 60 to 63 No 60 to 63 1 0001 111 11Eh Input change interrupt flags Device No O Input change interrupt flags Device No 0 RR aa RR Re O O 10000000 100h In
64. e cycle of I O communications If the result is still not good after the three attempts the central device outputs an interrupt request to the CPU If the communication line does not change during the three attempts the central device concludes that the local device has not received the data and it will set LNRV bit 7 in the interrupt status register to 1 4 When a frame received by the central device is faulty such as a CRC error the central device sends a resend request to the local device a request to send the same data again It automatically sends the resend request up to three times During this time the central device also inserts one cycle of I O communications for a retry If the result is still no good after three resend requests the central device outputs an interrupt request to the CPU When sending this resend request since the local device already has the data LNRV bit 7 in the interrupt status register will be set to 0 1 30 5 2 Operating procedure 5 2 1 5 2 2 5 2 3 5 2 4 5 2 5 Reset After turning ON the power make sure to reset at least once before starting any operation 1 To perform a reset place a LOW on the RST terminal for at least 10 reference clock cycles 2 Wait until the status bit 13 RBSY becomes 0 I O communication procedures 1 Write a command 1000h start system communications to all the devices and allow the device information area to be set automatically If t
65. e easiness from a CPU is identical One line can connect to max 64 devices Even when two lines are used the max number of devices is 64 I 12 4 4 16 MCRY This is a monitor output to confirm communication When a signal is transferred on the signal line this terminal outputs L signal If there is no signal on the signal line this terminal outputs H signal 4 4 17 MERR This is a monitor output to check communication guality When the center device receives an error frame such as a CRC error or when it cannot receive a response frame within 20 us the signal becomes L only for 128 cycles 3 2 us of the CLK By measuring the condition using the counter you can check communication guality 4 4 18 MERF This is a monitor terminal to confirm communication control status When the center device receives an error response frame this terminal outputs L level signal only for 0 2 seconds The error response frame is as follows A local device normally receives signals from the center device if there is no CRC error on the local device However it may possible that the received data do not match with the local device status such as receiving output data on the input port In this case the local device sends back the data to the center device in order to notify the center device that the received data is useless This is error response frame Other case is that a local device sends data longer than 8 bytes to a
66. e input ports However do not use any settings not shown 4 4 19 PON P1N P2N P3N Specify the input output logic for each port PON corresponds to port 0 P1N corresponds to port 1 P2N corresponds to port 2 and P3n corresponds to port 3 If a port is set HIGH by the corresponding PxN terminal then when this port is HIGH the central device will see a 1 If a port is set LOW by the corresponding PxN terminal then when this port is LOW the central device will see a 1 4 4 20 POO to 07 P10 to 17 P20 to 27 P30 to 37 Input output port terminals When used in output mode these terminal outputs are open drains Therefore they should be pulled up externally a few k ohms is all that is needed 1 5 V input and output are possible in the following conditions As an input Connect a 5 V signal As an output the pins can be pulled up to 5 V 2 Be careful not to provide too much voltage by reflection or linking 3 We recommend the use of diodes at each terminal to prevent the possibility of too much voltage 4 5 Status after reset POO to P07 When PON LOW HIGH when PON HIGH LOW when output is selected P10 to P17 When P1N LOW HIGH when P1N HIGH H LOW when output is selected P20 to P27 When P2N LOW HIGH when P2N HIGH LOW when output is selected P30 to P37 When P3N LOW HIGH when P3N HIGH LOW when output is selected Note A HIGH output H means that the terminal is externally pulled up to th
67. e of a circuit to interface a CPU to a central device Four modes are available for connecting a CPU to the central device Shown below is an example for connecting a CPU to the IFO and IF1 terminals Please note that the CPU shown in the connection example below is only a representative example If the interface is similar CPUs other than the one shown below may be connected in this fashion For details see the hardware instructions for the CPU you are using 1 1 1 I F mode 4 IF1 H IFO H VDD Z80 type CPU MO Decoding IF1 A9 to A15 a IFO A0 to A8 l eni IORQ RD WRQ DO to D7 RST System reset Note 1 When you use an interrupt controller the CPU will output IORQ as an interrupt acknowledge signal that is used to determine the interrupt vector At this time when this LSl s CS terminal goes LOW the LSI may output a WRQ signal and still not be able to capture the vector properly Therefore arrange the decoding circuit so that it only functions when the M1 signal is HIGH Note 2 Pull up terminals D8 to D15 to VDD externally 5 to 10 k ohms Note 3 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows A3 to A15 Connect these lines to the decoding circuit and use them to create the CS signal AO to A2 Connect these lines to AO to A2 on the central device Connect A3 to A8 on the central device to GND 111 3 1 1 2 I F mode3 I
68. e range 40 to 125 C Operation temperature range 40 to 85 C Il 3 4 Hardware Description 4 1 List of terminals QFP 80 No Signal name I O Logic Description 5 V interface 1 MRER O Negative Goes LOW for a specified time when an abnormal communication is received 2 MSEL O Negative Goes LOW fora specified time when this I O device is receiving data 3 TOUT O Negative Watchdog timer output 4 TMD Enable the watchdog timer Available 5 TUD Specify the operation when the watchdog Available timer signal TOUT is output 6 SI Positive Serial input 7 SOEL O Negative Enables serial output 8 SOEH O Positive Enables serial output 9 SO O Positive Serial output 10 PoN Negative Ka Sets POO to PO7 to use negative Available ogic 11 VDD Power source 43 3 V 12 GND GND 13 POO B Bit 0 on port 0 Available 14 POI B 5 Bit 1 on port 0 Available 15 P02 B Bit 2 on port 0 Available 16 P0O3 B Bit 3 on port 0 Available 17 P04 B Bit 4 on port 0 Available 18 PO5 B Bit 5 on port 0 Available 19 P06 B Bit 6 on port 0 Available 20 PO7 B Bit 7 on port 0 Available 21 VDD Power source 43 3 V 22 GND GND 23 PIN Negative LOW Sets P10 to P17 to use negative Available logic 24 P10 B Bit 0 on port 1 Available 25 P
69. e voltage provided by the power supply Output circuits for the I O port terminals are open drains in order to handle a 5 V output Therefore an external pull up resistor is essential for correct operation A resister with a few K ohms is all that is needed to pull up the terminal 1 11 5 Electrical Characteristics 5 1 Absolute maximum ratings Vss OV Item Symbol Rating Unit Power supply voltage Vop 0 3 to 5 0 V Input voltage Vin 0 3 to Vpp 0 3 V Input voltage 5V 1 F Vin 0 3 to 7 0 V Output resisting voltage open drain Vopp 0 3 to 7 0 V Input current lin 10 mA Storage temperature Tsto 40 to 125 C 5 2 Recommended operating conditions Vss OV Item Symbol Rating Unit Power supply voltage Vpp 0 3 10 V Input voltage Vin Von V Input voltage 5V 1 F Vin Up to 5 5 V Storage temperature Ta 40 to 85 V 5 3 DC characteristics Vss OV Item Symbol Condition Min Max Unit Current lia CLK 80 MHz 36 mA consumption Output leakage current loz 10 HA Input capacitance 5 6 pF LOW input current In 10 10 uA HIGH input current ln 10 10 uA Terminals except CLK 0 8 V POM laa Vi CLK terminal Voox0 2 V Terminals except CLK 2 0 V FIGH input current Vin CLK terminal Vox 0 8 V lo 4 MA 0 4 V LOW output voltage Vor Bi directional I F lo 8mA 0 4 V lo 1 uA Vss 0 05 V
70. eiving buffer capacity 8 to 11 ERAO to 3 These are access error codes from a CPU The code is stored until the next time an error occurs 0001 The device number was zero and an I O communication start command was written 0010 Tried to write data with a start sending command without any 12t015 CAEOto3 data to send 0011 While the DBSY 1 a device tried to do one of the following 1 Reading or writing to the transmitting or receiving FIFO 2 Wrote a system start command or a data communication start command 0100 Tried to send data to a device that is not in use When the ERA code is 0010 or 0011 the device number is not available in the EDN 1 23 4 8 Command COMW PA AN COMB1 COMBO de SS S S rt a N 15 14 13 12 Note Write to the 8 bit CPU I F IFO H IF1 1 in the following order COMBO then COMB1 Command Description 0000 0000 0000 0000 NOP 0000h Invalid command 0000 0001 0000 0000 Resets the software 0100h Resets the central device This is the same function as the RST input 0000 0010 0000 0000 Resets the transmitting FIFO 0200h Resets only the data transmitting FIFO 0000 0011 0000 0000 Resets the receiving FIFO 0030h Resets only the data receiving FIFO 0001 0000 0000 0000 System communication to all devices 1000h Polls all of the devices device Nos 0 to 63 one by one and refreshes the device info
71. en the LSls Never directly stack them on each other as it may cause friction that can develop an electrical charge 2 Operators must wear wrist straps which are grounded through approximately 1M ohm of resistance 3 Use low voltage soldering devices and make sure the tips are grounded 4 Do not store or use LSls or a container filled with LSIs near high voltage electrical fields such those produced by a CRT 5 To preheat LSls for soldering we recommend keeping them at a high temperature in a completely dry environment i e 125 C for 24 hours The LSI must not be exposed to heat more than 2 times 6 When using an infrared reflow system to apply solder we recommend the use of a far infrared pre heater and mid infrared reflow devices in order to ease the thermal stress on the LSIs a NN gt Product flow direction Far infrared heater pre heater Mid infrared heater reflow heater Package and substrate surface temperatures must never exceed 260 C and 230 C for 30 to 50 seconds Temperature C AOA A 230 190 reno na 180 Time 60 to 120 seconds 35 to 50 seconds Recommended temperature profile of a far infrared heater hot air reflow 7 When using hot air for solder reflow the restrictions are the same as for infrared reflow equipment 8 If you will use a soldering iron the temperature at the leads must not be 260 C or less for more than 10 seconds and must not be 350 C or less for mo
72. ent and precautions used for the descriptions IV 3 12 Commands Used nan sr en dede MAN ede tent A kaan ata Aa IV 3 2 SOltWare EXampl s Axiata an ba Nr au nana inang dunt suns Na Elda iii IV 4 2 1 Start of the simplest cyclic communication ss IV 4 2 2 The central device specifies the data for the local devices that are connected IV 5 2 8 Set up an input change interrupt WWW kekanan IV 7 2 4 Check and clear any existing input change interrupts seeeessssssssrrrrssssssriirnrrtsssrrnrnnnnsssssrnnnn IV 9 2 5 Check and clear I O communication errors IV 11 2 6 Communication with port data port data and data device status oo IV 13 2 7 Data communication 1 Put the value in the register of the PCL device G9003 IV 15 2 8 Data communication 2 Read a register in a PCL device G9003 ooooo oWoooomo IV 16 2 9 Data communication 3 Start the PCL device G9003 Wo IV 17 2 10 Data communication 4 Start a PCL6045A B using a CPU emulation device IV 19 2 11 An example of measuring when a break OCCUFS WWW Woo WWW mo IV 23 V Troubleshooting he tante nu ma Hate oo nee hac ena Pan Mena neon V 1 1 Checking the central device sise V 1 2 Cheeking the local JeVIGES ee tenan ana Lal V 1 82 Checking the System ts ett hi Al A LARA AA AAN ee V 1 VI Handling Precautions senin tani Ketama
73. erent from that called for in the PMDO to 2 settings can be checked by reading the interrupt status When errors occur on more than one device only the device number where the last error occurred would be shown 1 22 4 7 Interrupt status ISTW RS TSTBI ISTBO 14 1 11 15 3 12 10 9 8 7 6 5 4 3 2 1 0 ERA2 LNRv o EDNS EDN4 EDN3 EDN2 EDN2 EDNO Bit Symbol Description Contains the device number of the device with an EDTE 1 or ERAE 1 error from receiving I O data that is different from the setting in ERA 0001 PMD These details are stored until the next time an error occurs 0 to 5 EDNO to 5 6 Not defined Always 0 When a local device is not receiving data this bit is 1 When the data communication or system communication terminates with an error EDTE 1 only when receiving attribute information 7 LNRV and if a local device cannot receive data from the central device this bit becomes 1 The local device does not respond When the local device has received the data this bit returns to 0 This condition is stored until the next time an error occurs These are identification codes for received data processing errors on a local device The code is stored until the next time an error occurs 0001 Received I O data is different from the PMD settings 0010 An I O device received a data communication frame 0011 A data device received frames larger than the rec
74. erial input signal for communication Positive logic MRER Monitor output used to check communication guality When the I O device receives an error frame such as a CRC error this terminal goes LOW for exactly 128 CLK cycles 3 2 us By timing this interval using a counter you can check the guality of the communication MSEL Communication status monitor output When the I O device receives a frame intended for this device and everything is normal when communication MFER is OFF this terminal goes LOW for exactly 128 CLK cycles 3 2 us This can be used to check the cyclic communication time BRK By providing HIGH pulses that are longer than the specified interval the I O device will be made to wait for a break frame When the I O device receives a break frame send request from a central device it immediately sends a break frame A pulse at least 3200 usec long is needed in order to be seen as the BRK input pulse positive logic 11 10 4 4 18 PMDO to PMD2 Terminals used to determine the port direction of the four I O ports These terminals can set the ports as follows PMD2 PMD1 PMDO P0 7 0 P1 7 0 P2 7 0 P3 7 0 L L L Output Output Output Output L L H Input Output Output Output L H L Input Input Output Output L H H Input Input Input Output H L L Input Input Input Input When PMDO to 2 are set other than as shown above all the ports will b
75. es this communication will write the data to the register specified in the data details Outpw 0x0000h 0x4028h Sts Inpw 0x0000h Read status Waits until the data communication is complete This process may be waiting for an interrupt YES Error processing Check the EDTE bit If the data communication failed take the defined steps Note that the EDTE bit will be cleared by reading the status The EDTE bit changes with the same timing as the CEND bit A data communication command is constructed as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 0 0 Specify the address in these IV 15 2 8 Data communication 2 Read a register in a PCL device G9003 The example of data communication below shows how to read a register that is integrated in the PCL device G9003 Assume that the local devices to be used are as follows Assume you want to read the register value in the PCL device Device type Configuration item Configuration data PCL device Device address 40 28h Write a read command from the PCL device register to the FIFO Register access command of the PCL device is specified in the user s manual for the G9003 Outpw 0x0006h 0x00DOh Have data communication with the specified device number A PCL device that received this communication re
76. even for a very short time 2 Take precautions against the influence of heat in the environment and keep the temperature around the LSI as cool as possible 3 Please note that ignoring the following may result in latching up and may cause overheating and smoke Do not apply a voltage greater than 3 3V greater than 5V for 5V connectable terminals to the input output terminals and do not pull them below GND Please consider the voltage drop timing when turning the power ON OFF Consider power voltage drop timing when turning ON OFF the power Make sure you consider the input timing when power is applied Be careful not to introduce external noise into the LSI Hold the unused input terminals to 3 3 V or GND level Do not short circuit the outputs Protect the LSI from inductive pulses caused by electrical sources that generate large voltage surges and take appropriate precautions against static electricity 4 Provide external circuit protection components so that overvoltages caused by noise voltage surges or static electricity are not fed to the LSI 2 Precautions for transporting and storing LSIs 1 Always handle LSls carefully and keep them in their packages Throwing or dropping LSIs may damage them 2 Do not store LSIs in a location exposed to water droplets or direct sunlight 3 Do not store the LSI in a location where corrosive gases are present or in excessively dusty environments 4 Store the LSls in an anti s
77. evice attribute information This command polls the specified devices and copies the attribute information into the data receiving FIFO The device information area does not change The details of the data receiving FIFO are as follows Bits 0 to 4 Number of bytes for the longest piece of data 8 1 Bits 5 to 7 Not used not defined Bits 8 to 15 Device type code I O device 01h Data device 81h Bits 16 to 18 Set the I O port PMD terminal information when an I O device is selected Bit 19 Always 0 Bits 20 to 31 Data device type G9003 000h G9004 001h 0011 0000 0000 0000 Start I O communication 3000h Start I O communication with devices that have a 1 in the device in use bit in the device information 0011 0001 0000 0000 Stop I O communication 3100h Stop the current I O communication 0100 0000 00 Data communication 4000h to 403Fh Sends data in the transmitting FIFO to the specified devices The data received in response will be stored in the receiving FIFO 0100 0001 0000 0000 Cancel data communication 4100h Halt the data communication and reset the transmitting FIFO This command will be ignored after the data has been sent 0101 0000 O xx Write to the Device information area 5000h to 507Fh The contents of the I O buffer are written into a word in the device information area As an example the relationship between the I O buffer details and the device information area are listed below
78. from 00h to 3Fh using the DNO to DN5 terminals 2 When the DNSM L Input a DNSO signal that is output by some other chip on the DNO terminal on this device When using this input method this chip has an address egual to the other chip s address plus one When using this method connect terminals DN1 to DN5 to GND When two seguential sets of serial data match the data is taken to be a device address 4 4 6 DNSO The numeric eguivalent of the address on DNO to DN5 4 1 will be output after being converted into a serial bit stream Connect this output to another local device s DNO terminal make all the other DNSM terminals of that local device LOW so that other devices can get the address and pass it along to the next data sending device Please note that the next address after 3Fh DN 5 0 000000 is 00h 4 4 7 SPDO SPD1 Set the communications speed All of the devices on the same communication line must be set to the same speed SPD1 SPDO Communication speed L L 2 5 Mbps L H 5 Mbps H L 10 Mbps H H 20 Mbps 4 4 8 TUD A watchdog timer is included on the chip to assist in administration of the communication status see the TMD terminal section When the data transmission interval from a central device to this device exceeds the set time the watchdog timer times out This terminal is used to set output conditions when the watchdog timer times out When TUD HIGH The LSI keeps it
79. from a local device Basic item Required time us Data sending time ST B x 0 6 3 25 x K Response time with data JT B x 0 6 5 65 x K Response time without data JT 5 05 x K One complete data communication cycle ST JT 7 4 us 6 3 Total cycle time including data communication The total time can be obtained by adding the data communication times to the ordinary communication cycle time Ex 1 Communication speed 20 Mbps 34 local devices are connected and on 4 occasions the data communication consisted of 2 bytes for sending and 6 bytes for receiving Cycle time Cyclic time Data communication time x Number of times of data communication 7 7 x 1 7 4 x 34 2 x 0 6 3 25 x 1 6 x 0 6 5 65 x 1 7 4 x4 518 4 21 1 x 4 597 8 us Note The formula above contains some margin for error In actual operation a shorter total time can be obtained However if a communication error occurs the total time will be longer than the calculated time I 32 7 Electrical Characteristics 7 1 Absolute maximum ratings Item Symbol Rating Unit Power supply voltage Voo Vss 0 3 to 4 0 V Input voltage Vin Vss 0 3 to Vpop 0 5 V Input voltage 5V I F Vin Vss 0 3 to 7 0 V Output current Terminal lout 30 mA Storage temperature Tsto 65 to 150 Le 7 2 Recommen
80. ges to input ports and status changes in data devices can be detected automatically and then the central device can generate an interrupt INT for a CPU This area can be addressed by writing bits that correspond to the local device number whose status you want to monitor When a bit is setto 1 its status will be monitored Ex When you want to monitor port 2 on device number 0 In order to specify device number 0 you have to access address OCOh Port 3 Port 2 Port 1 Port 0 For a 16 bit CPU address 0COh 15 14 13 12 111 10 9 817 6 5 4AN 3 R 1 0 Device No 3 Device No 2 Device No 1 Device No 0 As shown above there are 4 bits which correspond to each local device The lowest 4 bits will be the area for setting up interrupts for the local device with the lowest address number The lowest of the 4 bits corresponds to port 0 the next bit corresponds to port 1 and so forth When you want to monitor another local device determine the address using the following rule discard any remainder Address 0COh device number 2 The rule is the same for an 8 bit CPU except that the data will be transferred in units of 8 bits Since mainly status information corresponds to each port on data devices you just enter a 1 for the port which has the status you want to monitor For details see 5 1 3 Change to Input Interrupts Be especially careful when monitoring th
81. h the cable impedance at both ends of the transmission line The terminating resistors can be either before or after the pulse transformer The same effect will be obtained at either position When using a 5 V line driver receiver ICs such as a level shifter are needed to assert signals on lines such as SO SOEH and SI 1 Circuit example for a single local device VDD Line transceiver Local device 3 3 V Terminating Pulse transformer resistor 1000 uH or Serial line Device number DNO to DN5 LI DNSM Note 1 Make the wiring as straight and short as possible circuit on a circuit board GND 1 14 Using the connections shown below the address of the local device above will be the address of the local device underneath it plus 1 2 Circuit example for multiple local devices Local device Line transceiver 3 3 V Pulse transformer Terminating resistor Serial line Note 1 Make the wiring as straight and short as possible circuit on a circuit board Device number DNO to DNS DNSM Local device GND Note 2 The pull down resistor to GND should be 5 to 10 k ohms 1 5 connection example of a level shifter When using a 5 V line transceiver a level shifter is needed Shown below is an example of the connections for a level shifter TI SN74LVC244A and a line transceiver TI SN75LBC180A SN75LBC180A Pulse transformer 1 I l
82. he device information is already known you may write data information to the devices from the CPU 2 Place an initial value in the port data area Steps 1 and 2 can be performed in either order 3 Write a command 3000h to start I O communications After that write output information to the port data area when needed and read input information from the port data area Data communication procedure 1 Write data to be sent multiple words to the data transmitting FIFO 2 Write a send data command 4000h to 403Fh to send the data 3 Wait until the status bit 0 CEND becomes 1 4 If data has been received the status bit 10 RDBB will become 1 Until the status bit 10 RDBB returns to 0 the central device will read the response data from the data receiving FIFO Note 1 While I O communication is stopped data communication is disabled Note 2 Writing a send data command clears the data receiving FIFO Exclude a device with an error 1 The central device reads the interrupt status bits EDNO to 5 to identify the deice which has an error 2 Set the device in use bit in the device information area which corresponds to the device with an error to 0 Restoring excluded devices to cyclic communications Set the corresponding device in use bit in the device information area to 1 Or 1 Senda rising edge ON signal to the excluded local device s BRK terminal 2 When the central device receives the
83. he central device The lowest bit is fixed to 0 Data Data to write 16 bits Return value None 2 Read command from the central device Inpw Address Address Value corresponding to the address map in the central device The lowest bit is fixed to 0 Return value Read data 16 bits IV 3 2 Software Examples 2 1 Start of the simplest cyclic communication The simplest example is to issue a system communication command let the central device automatically collect data from the local devices and then start cyclic communication Send a system communication command to all local devices Outpw 0x0000h 0x1000h Sts Inpw 0x0000h Read status Waits for completion of the system communication Without a completion signal the central device cannot start the next operation Start cyclic communication YES Outpw 0x0000h 0x3000h IV 4 2 2 The central device specifies the data for the local devices that are connected This method assumes that the data for the local devices is already known and this data is manually specified in the address map of the central device Then cyclic communication is started By doing this mis settings in local devices can be found rather easily an error occurs when there is a mis setting For example assume that the following three devices are connected The device numbers shown below are in decimal notation Local device typ
84. hows the error status of the local device with the lowest address number By reading OB8h local device numbers from 0 to 15 can be checked In the same way by reading BAh you can check device numbers 16 to 31 To determine the address proceed as follows discard any remainder Address 0B8h Device No 8 For an 8 bit CPU Address 0B8h 7 6 5 4 3 2 1 0 Error on device number 7 Error on device number 0 The bits are read in groups of 8 by an 8 bit CPU but the meaning of each bit is the same The device number refers to the number allocated to each local device The numbers are specified on the external terminals on local devices Duplicate use of the same number is prohibited To clear flags In order to return a bit to 0 that was changed to a 1 when an error occurred write a 1 to this bit The simplest way to clear a flag is to write the same data back to the same I O communication error flag position that it was read from For examples of how to use these flags see point 2 in the Check and Clear I O Communication Errors in Software examples in Chapter IV I 19 4 5 3 Change to Input Port Interrupt Setting area Port information for the I O devices that are connected can be obtained automatically using the cyclic communication system The central device also uses cyclic communication to periodically obtain status information for the data devices that are connected These chan
85. is both directions Note 2 As for the terminals with available in the 5V interface column note the following These terminals can be input at 5 V level signal These are deleted diodes for overcurrent protection on 3 3 V lines If over voltage may be possible to charge due to reflection linking or inductive noise we recommend inserting a diode for overcurrent protection Without overcurrent protection diode Level shifter V gt Outputs from 5V devices can be connected to the center device asfar as these are TTL level Even if a signal is pulled up to 5V the output level will be less than 3 3 V However CMOS level signals cannot be connected On the CPU bus interface pull up of 5 V level is possible for stabilizing bus lines prevent floating Use 10 k ohm or larger capacity pull up resistors 4 2 Terminal allocation diagram IX 3 Z L oa ao 85528 Q gt 000 10 gt O SPDO D12 SPDI GND SIA D11 GND D10 VDD D9 SIB D8 GND VDD CKSL D7 GND D6 CLK D5 VDD D4 GND GND GND D3 GND D2 RST D1 VDD DO Note For each pin number see the marks on the actual LSI As shown above to the lower left of the NPM logo mark is the 1st pin 4 3 Entire block diagram RST SPD 1 0 Clock control CKSL circuit CLK CS Memory area RD control circuit WR IF 1 0 A 8 0 RI Command D 15 0 CPU an control circuit Data receiving FIFO Receipt data processing Circuit SIA Serial
86. is function is used to restore the devices that were excluded from the system such as by device extension or due to an error The CPU detects an interrupt caused by a break and can then issue a system communication command This allows it to refresh all the devices in polling operation or to refresh the device information for devices that are currently stopped Control of communication errors 1 YO communication errors When an I O communication error occurs the central device does not retry the communication However if it fails to communicate three times in a row three consecutive cycles the central device will output an interrupt request to the CPU It will also set the I O communication error flag bit that corresponds to the I O device number to 1 1 29 The CPU checks the existence of an I O communication error interrupt EIOE 1 in the status register when an interrupt occurs and then reads the I O communication error flags to see which I O device has an error By writing back the flag data just read the interrupt is reset If needed the device with an error can be excluded from further cyclic communication by software processing in the CPU 2 Data communication system communication errors When data communications or system communications from the central device fail it automatically retries the communication three times If it fails all three times the central device outputs an interrupt request to the CPU It also
87. it 1 Available 3 CS Negative Select chip Available 4 WR l Negative Write Available 5 RD Negative Read Available 6 AO Positive Address bus bit 0 LSB Available 7 LAI Positive Address bus bit 1 Available 8 A2 Positive Address bus bit 2 Available 9 A3 Positive Address bus bit 3 Available 10 GND GND 11 Ad Positive Address bus bit 4 Available 12 A5 Positive Address bus bit 5 Available 13 A6 Positive Address bus bit 6 Available 14 A7 Positive Address bus bit 7 Available 15 A8 Positive Address bus bit 8 Available 16 VDD 43 3 V power input 17 DO B Positive Data bus bit O LSB Available 18 D1 B Positive Data bus bit 1 Available 19 D2 B Positive Data bus bit 2 Available 20 D3 B Positive Data bus bit 3 Available 21 GND GND 22 D4 B Positive Data bus bit 4 Available 23 D5 B Positive Data bus bit 5 Available 24 D6 B Positive Data bus bit 6 Available 25 D7 B Positive Data bus bit 7 Available 26 VDD 43 3 V power input 27 D8 B Positive Data bus bit 8 Available 28 D9 B Positive Data bus bit 9 Available 29 D10 B Positive Data bus bit 10 Available 30 D11 B Positive Data bus bit 11 Available 31 GND GND 32 D12 B Positive Data bus bit 12 Available 33 D13 B Positive Data bus bit 13 Available 34 D14 B Positive Data bus bit 14 Available 35 D15 B Positive Data bus bit 15 Available 36 VDD 43 3 V power input 37 INT
88. lows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01 110 110111010101 amp Specify the address here When accessing ports 0 and 1 0 When accessing ports 2 and 3 1 A write command is constructed as follows 15 14 13 12 11 10 9 8 7 6 5 413 2 1 0 0 1 1 0 0 1 0 0 0 amp Specify the address here IV 14 2 7 Data communication 1 Put the value in the register of the PCL device G9003 The data communication example below shows data being placed in a register that is integrated in the PCL device G9003 Assume that the local devices to be used are as follows Assume that 00123456h will be placed in the RMV register of the PCL device Device type Configuration item Device number PCL device Device address 40 28h Store the data in the receiving FIFO in the following Outpw 0x0006h 0x0090h order Outpw 0x0006h 0x3456h 1 Write the command to the PCL device register Outpw 0x0006h 0x0012h 2 Write the data lower 16 bits 3 Write the data upper 16 bits The writing order to the FIFO is specified for the PCL device in the user s manual for the G9003 The register access command for the PCL device is specified in the user s manual for the G9003 Start data communication with the specified device number A PCL device that receiv
89. ly 40 MHz or 80 MHz 5 Is the CKSL terminal set correctly LOW 40 MHz HIGH 80 MHz 6 Does the IF 1 0 terminal setting match the CPU that is connected 7 Is the data transfer speed identical throughout the system 8 Do the access times follow the specified timings 9 Is there open state input terminal 2 Checking the local devices 1 Is power supplied properly 3 3 V only 2 Is the external clock signal stopped while a reset signal is input 3 Is the reset signal released 4 Is the clock signal supplied correctly 40 MHz or 80 MHz 5 Is the CKSL terminal set correctly LOW 40 MHz HIGH 80 MHz 6 Does the data transfer speed match the setting on the central device 7 When the DNSM is HIGH is the address set properly through the DN 5 0 terminal The address must be set using negative logic 8 When the DNSM is LOW are the signals from other local devices through the DNSO terminal connected to the DNO terminal If this signal is held LOW normal address setting cannot be performed 9 Is one of the DNSO signals connected to the DNO terminals of multiple local devices Connect the DNSO signals in a daisy chain arrangement 10 Is an SOEL signal output by another local device connected to the SOEI terminal Only the SOEH signal can be connected to the SOEI terminal 11 When the device being checked is an I O device is the PMD 2 0 terminal setting wrong Is the combination of input and output ports set prope
90. m contradictory to the excess cable precaution this minimum length is necessary 11 18 Using different cables in one system Do not mix cables from different manufacturers even when they are in the same category Different cable models from the same manufacturer should not be used either Using different cables together may deteriorate the communication guality 11 19 11 20 IV Software Examples flow chart G9001 IV 2 1 Assumption This Chapter outlines software for the central device using flow charts In the flow charts reguired variables are used for convenience 1 1 Environment and precautions used for the descriptions The descriptions below assume that I F mode 3 is selected Therefore a 16 bit data bus is used Address map details are found in item 2 I F mode 3 of the Address Map section in Chapter 1 The addresses described there will be used in the descriptions in this section Also these descriptions are based on the assumption that the wiring connections around the central device have been properly prepared and that the connected local devices are turned on And of course we presume that connections to the serial line and the termination resistances are all correct 1 2 Commands used We will use the following two commands to access the address map in the central device 1 Write command to the central device Outpw Address Data Address Value corresponding to the address map in t
91. n an BNN NN NS VI 1 Design precautions 2 Precautions for transporting and storing LSIs 3 Precautions for mounting rek aa a a 3 1 About the central device G9001 3 2 Irdevice G9002 Se AA aa ieee eee eee NN 4 Other precautions I Center device G9001 User s Manual Outline This LSI is a center device of the Motionnet system It contains 256 byte RAM for controlling I O and 512 byte RAM for data communication and can control up to 64 local devices The local devices can be classified into I O devices that control input output signals such as G8014C on the T NET system and data device that control by data such as G8015 It allocates device numbers from 0 to 63 for each local device One I O device has 4 ports 1 port 8 bits for input output select input output by terminals Therefore connecting all the local devices to the center device as I O device you can connect I Os of 2048 points 64 units x 4 ports x 8 bits 2048 by serial communication One data device can communicate max 256 bytes data maximum data length of the PCL device will be 8 byte communication Suppose that all of the local devices connected to the center device as PCL devices G9003 64 axes can be controlled by serial communication Features Maximum data transfer speed is 20 Mbps Transfer cycle time is less than 1 msec when 64 local devices are connected in case of cyclic communication only One center device can connect up
92. nger at 40 MHz 1 Does not use the WRQ output CPU does not have a wait function Address CS ii ee _ wr ET DATA wait of 6 clock cycles or longer at 40 MHz must be inserted by the CPU software 2 Uses the WRQ output CPU has a wait function Address So 9 Se TTT WR fs ET wa KW WWW DATA ln CPU automatically waits for the required period of time 1 2 1 3 Read timing The data read timing for reading the status addresses 0 and 1 when the I F mode 4 the data receive FIFO addresses 6 and 7 when the I F mode 4 and the memory area 078h to 1FFh when the I F mode 4 is shown below When reading the I O buffer addresses 4 and 5 when the I F mode 4 no waiting time is needed A wait of 4 clock cycles is needed for continuous reading at 40 MHz 1 Does not use the WRQ output CPU does not have a wait function Address Address DATA wait of 4 clock cycles or longer at 40 MHz must be inserted by the CPU software III 9 2 Uses the WRQ output CPU has a wait function Address Next address Qs _ la NS WRQ a DATA The CPU automatically waits for the required period of time Note The memory area 078h to 1FFh when the I F mode 4 is shared with the internal serial reception circuit In order to prevent a conflict between reading by a CPU and the internal timing the central device transfers data from the memory area internal RAM to an indirect
93. o Oto 7 ai 0 1011 1001 OB9h I O communication error flags I O communication error flags lee na ena AD EME No 8 t0 15 10 o ee DEVICE No 8 t0 15 sec ta 0 1011 1110 OBEh I O communication error flags I O communication error flags _ 4 Device No 48 to 55 _______ Device No 48 to 55 0 1011 1111 OBFh I O communication error flags I O communication error flags Device No 56 to 63 Device No 56 to 63 011000000 0COh Input change interrupt settings Device Input change interrupt settings 0 1100 0001 0C1h Input change interrupt settings Device Input change interrupt settings No 2 3 Device No 2 3 011011110 ODEh Input change interrupt settings Device Input change interrupt settings Ut NO 80 61 A Device No 60 61 oo cauia 0 1101 1111 ODFh Input change interrupt settings Device Input change interrupt settings No 62 63 Device No 62 63 011100000 OEOh Input change interrupt flags Device No Input change interrupt flags Device EER AE ee LC aa 0 1110 0001 OE1h Input change interrupt flags Device No Input change interrupt flags Device 2 3 No 2 3 Dh 2 OO BRE e AE NOOO OY PA A 0 1111 1111 OFFh Input change interrupt flags Device No Input change interrupt flags Device 62 63 No 62 63 I 14 1 0000 0000 100h Port data No 0 Device No 0 Port 0 Port data No 0 Device No 0 Port 10000 0001
94. of the CPU you are planning to use and check with which mode you can connect Note The classification of the CPU interface modes above is applicable only for the center device The CPU emulation device G9004 also has unique CPU interface modes Mode classification of this is different than the above CS Input L level signal to this terminal when accessing this LSI RD WR A0 and WRQ Connect I F signals with a CPU Input signals vary with setting of the IFO to 1 For the details see items IFO and IF1 INT Outputs an interrupt reguest signal When not using this terminal keep this terminal open IFB Use this terminal when connecting with a CPU having no wait control input terminal By reading a command from a CPU this signal becomes L level When the command process is complete this signal returns to H level After confirming that this terminal is H level access the center device A1 toA8 Enter address signal to these terminals When the IF1 is L address bus A1 to A8 are inverted inside When to control at 8 byte area process as follows IF1 terminal status A 8 3 process Remarks H Pull up set to H I F mode 1 2 L GND set to L I F mode 3 4 4 4 10 DO to D7 Connect lower 8 bits of the data bus 4 4 11 D8 to D15 Connect upper 8 bits of the data bus When used as I F mode 4 IF1 H IFO H pull up or pull down with 5 to 10 K ohms resistor Use of one resistor for 8 lines is al
95. ot be ideal In this case select 80 MHz The central device divides the freguency inside and creates 40 MHz freguency If you do not want 80 MHz freguency you may prepare a separate 40 MHz oscillator for this LSI RST This is an input terminal for a reset signal By inputting an L level signal the central device is reset As the central device synchronizes with a clock arrange a circuit so that it does not disconnect the clock while resetting Reset signal length longer than 10 clock cycles is reguired CKSL Use to select clock rate L Connect 40 MHz clock freguency to the CLK terminal H Connect 80 MHz clock freguency to the CLK terminal Select this when the duty of the 40 MHz clock collapses too much 1 10 4 4 4 IFO IF1 Specify CPU I F mode Set status CPU signal to connect to terminals Example IF1 IF2 Duta un Wh A0 WRQ of CPU terminal terminal terminal terminal L L I F mode 1 VDD R W LDS DTACK 68000 L H I F mode 2 RD HWR VDD WAIT H8 H L I F mode 3 RD WR GND READY 8086 H H I F mode 4 RD WR AO WAIT Z80 4 4 5 4 4 6 4 4 7 4 4 8 4 4 9 This LSI has the following four interface modes The above four CPUs are typical ones among CPUs currently available on the market Even if a CPU you are examining is other than the above CPUs most of the CPUs can be connected using either of the interfaces above For details see the hardware specification sheets
96. put change interrupt flags Device No Input change interrupt flags Device No 60 to 63 60 to 63 O 1111 111 OFEh Port data No 0 1 Device No 0 Port 0 Port data No 0 1 Device No 0 Port 0 REATO RL TA RE RRR AE De nn a ee Kata 0 1111 110 OFCh Port data No 2 3 Device No 0 Port 2 Port data No 2 3 Device No 0 Port 2 nr SO eee teehee keep er rr 00000001 002h Port data No 252 253 Device No 63 Port data No 252 253 Device No 63 sbieco ledro D Tara i riad Foro in nin 0 0000 000 000h Port No 254 255 Device No 63 Port 2 Port data No 254 255 Device No 63 3 Port 2 3 Note The hexadecimal notation for the addresses above are written with the assumption that AO 0 l 17 Note The discussion of address maps below largely concerns I F mode 3 4 5 1 Device information area With system communication the central device polls all local devices from device 0 to 63 According to the response from local devices the central device can confirm the connection status device type settings for the I O port on each local device and refresh its own device information area When a CPU knows the device information the central device can write to it 8 bits of device information are required for each device 7 6 5 4 3 2 1 0 01010 Device information LU I O setting Set value Port0 Port1 Port2 Port3 PMD2 PMD1
97. r write command and place the data in the Outpw 0x0006h 0x0000h FIFO Outpw 0x0000h 0x4028h Lastly issue a device communication command Dev Sts Inpw 0x0000h Check the EDTE bit to see if this data communication ended normally before starting the next data communication YES Error processing Outpw 0x0006h 0x0092h RFH setting Outpw 0x0006h 0x0200h Process the next set of data the same way Outpw 0x0006h 0x0000h Outpw 0x0000h 0x4028h Dev_Sts Inpw 0x0000h Error processing IV 17 Outpw 0x0006h 0x0095h RMG settin Outpw 0x0006h 0x00C7h kiai Outpw 0x0006h 0x0000h Outpw 0x0000h 0x4028h Dev_Sts Inpw 0x0000h cone YES YES Ta Outpw 0x0006h 0x0051h Outpw 0x0000h 0x4028h Finally place a start command for the PCL device in the FIFO and send it to the G9003 using data communication When the G9003 receives the data correctly NO the PCL device should start Check the EDTE bit to see if the device eno 17 gt communication was successful or not YES Dev Sts Inpw 0x0000h End IV 18 2 10 Data communication 4 Start a PCL6045A B using a CPU emulation device The CPU emulation device a G9004 can substitute for a CPU and it can be connected to normal CPU peripheral devices This section gives an example of how to start the PCL6045A B LSI made by NPM that is used to generate pulse trains for 4 axes Device
98. re than 3 seconds VI 3 4 Other precautions 1 When the LSI will be used in poor environments high humidity corrosive gases or excessive amounts of dust we recommend applying a moisture prevention coating 2 The package resin is made of fire retardant material however it can burn When baked or burned it may generate gases or fire Do not use it near ignition sources or flammable objects 3 This LSI is designed for use in commercial apparatus office machines communication eguipment measuring equipment and household appliances If you use it in any device that may require high guality and reliability or where faults or malfunctions may directly affect human survival or injure humans such as in nuclear power control devices aviation devices or spacecraft traffic signals fire control or various types of safety devices we will not be liable for any problem that occurs even if it was directly caused by the LSI Customers must provide their own safety measures to ensure appropriate performance in all circumstances VI 4 Notes NPM NIPPON PULSE MOTOR CO LTD Tokyo Office No 16 13 2 chome Hongo Bunkyo ku Tokyo 113 0033 Japan Phone 81 3 3813 8841 Fax 81 3 3813 7049 E mail device npm co jp http www pulsemotor com NIPPON PULSE AMERICA INC 1073 East Main Street Radford VA 24141 U S A Phone 1 540 633 1677 Fax 1 540 633 1674 E mail info nipponpulse com http www nipponpulse com MNAL No G9001 G9002 1A
99. rly 12 When the device being checked is an I O device are the settings on PON P1N P2N and or P3N correct Using these terminals the signal logic can be changed for each port 13 Is there an open state input terminal 14 After releasing a reset does the TOUT terminal go LOW If so a local device is waiting for a signal from the central device The devices themselves must be appropriate 3 Checking the system 1 Is cable polarity correct Twisted pair cables must be used The polarity of these two lines must be correct The output from Y on the RS485 chip must be connected to input A on another RS485 chip and output Z must be connected to input B Are there termination resistors at both ends of the cable Is a terminal resistor connected in some other position not at the ends When a 5V line transceiver is used is a level shifter connected Is the inductance of the pulse transformer too low Is the pulse transformer connected properly Are there any faulty contacts on connectors Is the same address used for two local devices 2 3 4 5 6 7 8 9 Are pulse transformers connected to all branch points V 1 10 If a pulse transformer is not used is the GND signal connected to all the branch points shared GND 11 Is the operating voltage on all the line transceivers at the same level V 2 VI Handling Precautions 1 Design precautions 1 Never exceed the absolute maximum ratings
100. rmation areas that correspond to each device number The device information contains the following Device in use 0 when no response and 1 when it responds Device type Reset to 1 when it is a data device YO setting information 0001 0001 0000 0000 1100h System communication to all devices except those devices excluded from cyclic communication After checking the device information area the central device polls all the devices whose device in use bit is set to 0 one by one and refreshes the device information areas that correspond to each device number The details are refreshed the same as by writing a command 1000h 0001 0010 00 1200h to 123Fh System communication to specified devices The central device polls only the specified devices and refreshes the device information areas that correspond to each specified device number The details are refreshed the same as by writing a command 1000h Note For all bits marked with a the upper bits of the device address should be set in order starting from the left end of the bits For bits with marked with an amp when the port is 0 or 1 set the bit to 0 When the port is 2 or 3 set the bit to 1 For bits marked with an x either 0 or 1 may be used 1 24 Command Description 0001 0011 00 Obtain attribute information for the specified devices 1300h to 133Fh The polling response frame consists of d
101. ruction corresponds to the FH speed start command on the PCL6045A B After receiving this instruction the PCL6045A B starts feeding pulses at FH speed Groups of commands can be stacked up for sending in the FIFO When a certain number of commands is stored in the FIFO send the command data to the CPU emulation device using data communication While interpreting the command data received the CPU emulation device will repeat its operation as a substitute for a CPU When all of the commands have been received the CPU emulation device turns on a bit in the status data which mean that the local side has completed the reception process This is passed along to the central device by cyclic communication Notes Be careful about the size of the command data group sent to the CPU emulation device The FIFO in the central device is 256 bytes long As long as the command group size does not exceed this value there should not be a problem However if the communication data increases the ratio of data that need to be caught as communication errors such as electrical noise will increase If the amount of data is small the data packet size used for sending is also small and it may be possible to for data packets to pass through between burst of noise If the packet size is too large a data collapse may occur due to a noise environment CRC error in which case proper communication cannot be established If the communication line is too long or the n
102. s current status When the TUD LOW The LSI is Reset 4 4 9 TMD Specify the time for the watchdog timer The watchdog timer is used to administer the communication status When the interval between data packets sent from a central device is longer than the specified interval the watchdog timer times out the timer restarts its count at the end of each data packet received from a central device The time out may occur because of a problem on the communication circuit such as disconnection or simply because the central device has stopped communicating The time used by the watchdog timer varies with communication speed selected Watchdog timer setting TMD terminal 20 Mbps 10 Mbps 5 Mbps 2 5 Mbps L 5 ms 10 ms 20 ms 40 ms H 20 ms 40 ms 80 ms 160 ms Il 9 4 4 10 4 4 11 4 4 12 4 4 13 4 4 14 4 4 15 4 4 16 4 4 17 TOUT Once the watchdog timer has timed out this terminal goes LOW SO Serial output signal for communication Positive logic tri state output SOEH SOEL Output enable signal for communication The difference between the SOEH and SOEL is that the logic is inverted When sending SOEH HIGH and SOEL LOW SOEI When using more than one I O device connect the SOEH signal of the other I O device to this terminal By being wire OR ed with the output enable signal from this I O device the device outputs an enable signal to SOEH or SOEL SI S
103. so available 4 4 12 SPDO SPD1 Specify communication speed with these terminals SPD1 SPDO Communication speed L L 2 5 Mbps L H 5 Mbps H L 10 Mbps H H 20 Mbps All of the devices on the communication line shall be set to the same speed Either 40 MHz or 80 MHz is connected to the clock signal as far as you do not mistake setting of the CKSL you can get communication speed of 20 Mbps 4 4 13 SO Serial output signal for communication Positive logic Connect this line to a data input of a RS485 device 4 4 14 SOEH SOEL Output enable signal for communication Difference between SOEH and SOEL is that only logic is different When sending signals SOEH will become H and SOEL will become L Connect either of needed signal to the data enabled input of a RS485 device 4 4 15 SIA SIB Serial input signals for communication Positive logic Basically these two are identical in functions Each of them can construct independent signal line as follows Line Transceiver Center i III device 0000000e Commonly using the serial output signal SO from the center device provide RS485 and pulse transformer individually for each line the signal line load can be decreased When connecting to many local devices on one line or when a signal line is long signal quality will be deteriorated remarkably In order to prevent this problem separate to two lines Even divided into two lines us
104. tatic storage container and make sure that no physical load is placed on the LSls VI 1 3 Precautions for mounting 3 1 About the central device G9001 1 Plastic packages absorb moisture easily Even if they are stored indoors they will absorb moisture as time passes Putting the packages in to a solder reflow furnace while they contain moisture may cause cracks in plastic case or deteriorate the bonding between the plastic case and the frame The storage warranty period is one year as long as the moisture barrier bags are not opened 2 If you are worried about moisture absorption dry the chip packages thoroughly before reflowing the solder Dry the packages for 20 to 36 hours at 125 5 C The packages should not be dried more than two times 3 To heat the entire package for soldering such as infrared or superheated air reflow make sure to observe the following conditions and do not reflow more than two times Temperature profile The temperature profile of an infrared reflow furnace must be within the range shown in the figure below The temperatures shown are the temperature at the surface of the plastic package Maximum temperature The maximum allowable temperature at the surface of the plastic package is 260 C peak A profile The temperature must not exceed 250 C A profile for more than 10 seconds In order to decrease the heat stress load on the packages keep the temperature as low as possible and as short as
105. the values placed in the FIFO as follows Interpreted results To address 04h While incrementing the address number Write data Two times Write data two times to address 04h while adding one to the address each time Then what data should be written This corresponds to two words written to the FIFO sequentially Since the G9004 will execute the process two times two words need to be written IV 21 In all the following operations were commanded by the CPU emulation device 1st process Write 0100h to the specified address 004h 2nd process Write 0000h to the specified address 006h Actually these operations are equivalent to the procedures used to place data in the I O buffer of the PCL6045A B After that instructions are needed about which data should be written to which register These are eguivalent to the following blocks written to the FIFO Let s look at them 0100h and 0081h were written to the FIFO The first data is sent to the CPU emulation device The interpreted meanings are as follows Interpreted results Write data 0081h to specified address 00h once This instruction is used to issue a command to the PCL6045A B and has the meaning write the contents of the I O buffer into the PRFL register Now the data are sent to the PRFL In the same way commands can be stacked up in the FIFO so that the register setting is complete The last 0100h and 0051h mean write 0051h to address 00h This inst
106. transceiver 3 3 V Note 3 Terminating resistor Pulse transformer Serial line 2 GND NV Note 1 When connecting the serial lines to line transceivers make the path as short and straight as possible Serial line 1 and serial line 2 are identical except for their serial signal input terminals on the central device SIA and SIB In order not to load the lines too heavily two identical line inputs are provided If there are only a few local devices and the serial line is relatively short a single one of the input lines named above will be enough to maintain a reliable signal If you will not be using one or the other of the two inputs SIA or SIB connect the unused terminal SIA or SIB to VDD or GND Note 1 When connecting the serial lines to line transceivers make the path as short and straight as possible Running these lines on a PC board could deteriorate the communication performance Note 2 Pull down resistors to GND should be 5 to 10 k ohms Note 3 The following ICs can be used as 3 3 V line transceivers Ex 1 ADM3491AN DIP or ADM3491AR SOIC made by ANALOG DEVICES Corporation 2 MAX3362EKA SOT made by MAXIM Corporation 1 13 1 4 Line transceivers and pulse transformers for local devices Use RS 485 line transceivers and pulse transformers 1000 uH or equivalent to make serial communication connections Connect the line transceivers as shown below Connect terminating resistors which matc
107. ttings of each local device By writing a system communication start command 1000h the central device polls all of the local devices device No 0 to 63 one by one and refreshes the device information area according to the response from the local devices 8 bits are used for the device information about each device 7 6 4 3 2 1 0 0 0 5 0 H I O setting Device information Set value Port0 Port 1 Port2 Port 3 PMD2 PMD1 PMDO 000 Output Output Output Output L L L 001 Input Output Output Output L L H 010 Input Input Output Output L H L 011 Input Input Input Output L H H ar a Input Input Input Input RS When a local device is a data device the ports used to exchange data status or general purpose ports have a different meaning for each device When the device information is already known to a CPU you can write data from a CPU When a system communication is started during I O communication the central device halts the I O communication and executes the system communication which has a higher priority Device type 0 I O device Use of device 0 Do not use 1 Data device 1 Used After the system communication is complete the central device will restart the I O communication Even if I O communications are halted the central device can still execute system communications 2 I O
108. turns the specified register data to the central device The returned data is stored in the receiving FIFO Outpw 0x0000h 0x4028h Dev Sts Inpw 0x0000h Read status Waits until the data communication will complete This process may be waiting for an interrupt YES Error processing Com Inpw 0x0006h Read the data in the receiving FIFO Data L Inpw 0x0006h The data details and order are specified in the user s Data H Inpw 0x0006h manual for the G9003 n Since 3 words of return data are specified the communication is completed by reading the FIFO three times If the number of words in the return data is not known read the status in the central device Keep reading the receiving FIFO until the RDBB bit goes LOW Data Inpw 0x0006h Dev_Sts Inpw 0x0000h When reading data while checking the RDBB RDBB 1 IV 16 2 9 Data communication 3 Start the PCL device G9003 The data communication example below shows how to start pulse output by setting the registers in the PCL device G9003 The local devices are the same as in the previous section Assume that the data to place in the PCL device are as follows only the data needed to trigger the ulse output Register name Set value Remarks RFL 00000100h RFH 00000200h RMG 00C7h Multiplication rate 1 Outpw 0x0006h 0x0091h RFL setting Outpw 0x0006h 0x0100h Write a registe
109. type Configuration item Configuration data G9004 Device address 40 28h Registers to set in the PCL6045A B Register name Set value Remark PRFL 00000100h PRFH 00000200h PRMG 012Bh Multiplication rate 1 Send command data to the G9004 and it will process it one command at atime similar to a CPU to control the PCL6045A B Instruction to write data to the PCL6045A B I O buffer Instruction to write the data in the I O buffer of the PCL6045A B to the PRFL register Outpw 0x0006h 0x1184h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0081h Outpw 0x0006h 0x1184h Outpw 0x0006h 0x0200h Instruction to write data to the PCL6045A B I O buffer Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Instruction to write the data in the I O buffer of the Outpw 0x0006h 0x0082h PCL6045A B to the PRFH register Outpw 0x0006h 0x1184h Outpw 0x0006h 0x012Bh Instruction to write data to the PCL6045A B I O buffer Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Instruction to write the data in the I O buffer of the Outpw 0x0006h 0x0085h PCL6045A B to the PRMG register EJEP PUEWWO Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0051h Instruction to the PC6045A B to start feeding a pulse train Data communication command send the command Outpw 0x0000h 0x4028h data stored in the FIFO This step che
110. umber of local devices connected is too great it is better to send command data after dividing it into smaller pieces IV 22 2 11 An example of measuring when a break occurs The central device sends a break frame request periodically every 16 384 cycles of I O communication or every 250ms at 20 Mbps At this time if there is a device that has just been added to the communication line it places an H on the BRK terminal for a certain interval the local device will return a break frame If the central device receives this break frame it sets the BRKF bit in the status STSW register HIGH and changes the INT signal to LOW Now using the interrupt the CPU can see that a new device has been added The software is started when an interrupt is received INT LOW Sts Inpw 0x0000h The status in the central device is read Outpw 0x0000h 0x1000h System communication commands are assigned to all local devices IV 23 IV 24 V Troubleshooting During the initial design stage your system may not function normally due to simple misunderstandings or you may need to think about the problem differently If your system does not function normally after it is completely designed check the following 1 Checking the central device 1 Is power supplied properly 3 3 V only 2 Is the external clock signal stopped while a reset signal is input 3 Is the reset signal released 4 Is the clock signal supplied correct
111. vice Reset I O communication I O communication OPO error flag error flag Set input port change Set input port change GEDORE interrupt interrupt Reset input port change Input port change OSCO interrupt flag interrupt flag 100 to 1FF I O port data I O port data Communication 1 to 128 word frame 1 word 16 bits data length Data When communicating 3 words write 1 register of PCL 19 3 us communication When communicating 128 words 168 1 us time CPU I F Integrated 4 types of CPU I F circuit Z80 8086 H8 68000 etc Transfer method Cyclic transfer for I O port transit transfer for data communication Package 64 pin QFP model section 10 x 10 x 1 4 mm Power source 3 3 V 10 Storage 65 to 150 C temperature range Operating 40 to 85 C temperature range Note By issuing an operation command to the center device you can access the entire address area through a single I O buffer It will take more time than direct access Required address area is only 8 bytes 3 address signals For concrete use example see the software examples in chapter IV 4 Hardware description 4 1 A list of terminals QFP 64 Signal name 1 0 Logic Description 5V interface 1 IFO CPU I F mode setting bit 0 Available 2 IA CPU I F mode setting b
112. xcept that data will be handled in units of 8 bits To clear flags In order to return a bit to O that was changed to a 1 when a change occurred the input write a 1 to this bit The simplest way to clear a flag is to write the same data back to the same input change interrupt flag area that it was read from For examples of use see point 2 in the Change In Input Interrupt Setting section of Software Examples in Chapter IV 4 5 5 Port data area This area is used primarily to set the data for output ports on I O devices and to check the data from the input ports When the local device is a data device this area is used to read status information and set data for the general purpose port if any needs to be set To access this area see the device number and port number described in the address map To learn which status register corresponds to which port when the local device is a data device see the user manual for that device For examples of use see point 2 in the Change In Input Interrupt Setting section of Software Examples in Chapter IV I 21 4 6 Status STSW er TSTSBI STSBO Ann Aa 15 14 TS en T 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DBSY RBSY SBSY 0 RDBB TDBB REF 0 CAER ERAE EDTE EIOE IOPC BRKF CEND Bit Symbol Description CEND Becomes 1 when ready for data to be written to the transmitting FIFO buffer When the system communication
113. y must wait 8 clock cycles or longer to perform continuous writing at 40 MHz 1 Does not use the WRQ output CPU does not have a wait function Address Next address ie y DATA waiting period of 8 clock cycles 2 Uses the WRQ output CPU has a wait function at 40 MHZ or longer must be inserted by the CPU software 11 10 Address ee wao a L DATA The CPU automatically waits for the required period of time 1 2 2 2 Write data to memory using write commands The write commands can be used to write data to certain memory areas Shown below is the write timing when I F mode 4 is selected Intervals of 4 clock cycles at 40 MHz are needed to write data into the I O buffer or to write write commands into the command area The following operations both read and write require intervals of at least 8 clock cycles at 40 MHz The data can be written in any order However the commands must be written in low bit high bit order When the WRQ terminal is connected to the wait terminal on a CPU the timing is controlled automatically by the CPU s wait control function Write data to the memory Next operation Address CS alia DATA on A wait of 4 clock cycles at 40 MHz A wait of 8 clock cycles at 40 MHz 1 11 1 2 2 3 Read data from memory using read commands Use read commands to read data from certain memory areas The read timing when I F mode 4 is selected is shown below

G9001/G9002 User`s Manual 040327

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