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1. BERBERS did dada fap S LO O nm ID MN NM WM N N ID 1D mm n ln ao mana o O IO IO 9 0 0 o 1 lo lo lo EERTE EEEE AFSANNDDAADADAAAGOAAAOFFMDPDSlOaona ana aaAaAnA OaAanaaAnaAaAn SSSSSSSSSSSSSSSSSSSSSSLSSSRSSLLK LLL D2 PB2 109 72 Pu7 CSD3 D1 PB1 110 71 VCC DO PBO 111 70 PDO KBO INTO TDO 112 69 PD1 KBT INTT TDI 113 68 PD2 KB2 INT2 GND 114 67 PD3 KB3 INT3 OE 115 66 PD4 KB4 INT4 UDS PC1 116 65 PD5 KB5 INT5 AS 117 64 PD6 KB6 INT6 A0 118 63 PD7 KB7 INT7 IDS 119 62 GND RW 120 61 LDO DTACK PC5 121 60 LD1 RESET 122 59 LD2 _ vec 123 58 LD3 WE PC6 124 57 LFRM JTAGRST 125 MC68328PV 56 LLP BBUSW 126 TOP VIEW 55 LCLK A 127 54 LACD A2 128 53 VCC A3 129 52 PKO SPMTXDO A4 130 51 PK1 SPMRXDO A5 131 50 PK2 SPMCLKO AG 132 49 PK3 SPSEN GND 133 48 PK4 SPSRXD1 A7 134 47 PK5 SPSCLK1 A8 135 46 PK6 CE2 A9 136 45 PK7 CET A10 137 44 GND Ati 138 43 PMO CTS A12 139 42 PM1 RTS A13 140 41 PM2 IRO6 A14 14 40 PM3 IRO3 VCC 142 39 PM4 IRO2 A15 143 38 PM5 IRQ1 A16 PAO 144 37 PM6 PENIRQ O OrFNMYMTMNOOMAMOYTAMTWNO OR DDWOrYATAVMNTWO CO OS OOF Ol COO ss eS SS oS e e ANN NNN N N N 9 MN OOOO OD EREPEZRETELLLLSEE DSSS RBZ SSESSeo Ese ES 22353 VSagengs 32865858 sax OC rom 73 LALALA LLL 2PEBFES aeRO Goa a a otoz O co E Fa S E
2. LCD Controller A 4 BIT LCD DATA BUS PBSIZ 10 FLM Le q ENE fle iNES q HINES O q UNEN q Net p AR nae a LP 1 2 3 39 40 SCK UTL P E ee LD0 XXXXX va X pa X fos 777 X0152X10 156 LD1 2000001011105 X0 gt X0 153 X 10 1571 LD2 XXXXX 0 21 X 10 6 X010 X 10 1541 X 10 158 LD3 XXXXX 10 31 X_ 10 71 X 10 11 gt FLM LINE 1 LINE 2 LINE 3 LINE LINE LINE 1 eo M j T I E Po ANNI Te LP f 1 2 m 2 1 m 2 SCLK eS ll LDO XXXXX vX 0 OA X056 T CO AO LD1 1 X10 157 X 10 159 XX foum 3 Xfm XXKXK 1 BIT LCD DATA BUS PBSIZ 00 NE 1 LINE 2 LINE 3 LINE 4 LINE LINE 1 ll ll ARE La I 1 AS E 1 BPE eS ne od SO a a 1 2 3 79 80 m 1 m SCLK _ TN LIL a ee ee LD0 30000 Cra Xm a o por 021 X o m 11XXXX E o Q e z 3 Es e ll m D Figure 8 4 LCD Interface Timing for 4 2 and 1 Bit Data Widths 8 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller 8 2 4 DISPLAY CONTROL The LCD controller drives non split monochrome STN LCD panels with a maximum of 1 0
3. ADDRESS NAME WIDTH DESCRIPTION RESET VALUE HEX PAGE Base 0x000 SCR 8 System Control Register Ox 4 2 Base 0x004 MRR 32 Mask Revision Register System Base 0x100 GRPBASEA 16 Chip Select Group A Base Register 0x0000 5 4 Base 0x102 GRPBASEB 16 Chip Select Group B Base Register 00 5 4 Base 0x104 GRPBASEC 16 Chip Select Group C Base Re 0x0000 5 4 Base 0x106 GRPBASED 16 Chip Select Group D Base Reg 0x0000 5 4 Base 0x108 GRPMASKA 16 Chip Select Group A Mas 0x0000 5 5 Base 0x10A GRPMASKB 16 Chip Select Grou 0x0000 5 5 Base 0x10C GRPMASKC 16 Chip Select Gr 0x0000 5 5 Base 0x10E GRPMASKD 16 0x0000 5 5 Base 0x110 CSAO 32 ption O Register 0x00010006 5 6 Base 0x114 CSA1 32 t Option 1 Register 0x00010006 5 6 Base 0x118 CSA2 32 elect Option 2 Register 0x00010006 5 6 Base 0x11C CSA3 3 ect Option 3 Register 0x00010006 5 6 Base 0x120 CSBO 3 Chip Select Option O Register 0x00010006 5 6 Base 0x124 CSB1 2 roup B Chip Select Option 1 Register 0x00010006 5 6 Base 0x128 Group B Chip Select Option 2 Register 0x00010006 5 6 Base 0x12C Group B Chip Select Option 3 Register 0x00010006 5 6 Base 0x Group C Chip Select Option O Register 0x00010006 5 6 Base 0 csc1 32 Group C Chip Select Option 1 Register 0x00010006 5 6 Base 0x138 CSC2 32 Group C Chip Select Option 2 Register 0x00010006 5 6 Base 0x13C CSC3 32 Group C Chip Select Option 3 Register 0x00010006
4. 14 1 1 PWM Co This register co PWM operation Output pin status is also accessible 15 7 6 5 4 3 2 1 0 E UNUSED LoAD Pin o poL PM o CLKSEL pedo RESET VALUE 0000 PWMIRQ Pulse Width Module Interrupt Request This bit indicates that a period compare posted an interrupt Users can set this bit to immediately post a PWM interrupt for debugging purposes This bit automatically clears itself after it is read while set eliminating an extra write cycle in the interrupt service routine If the IRQEN bit is 0 this bit can be polled to indicate the status of the period comparator 0 No PWM period rollover 1 PWM period rolled over 14 2 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pulse Width Modulator IRQEN Interrupt Request Enable This bit controls the PWM interrupt While this bit is low the interrupt is disabled 0 PWM interrupt disabled 1 PWM interrupt enabled LOAD Load This bit forces a new period It loads the period and width registers and automatically clears itself after the load has been performed For slow PCLK periods the actual load may occur some time after the MPU writes this bit as the load occurs on the next rising PCLK edge PIN Pin This bit indicates the current status of the PWM output pin and can c immediately after it is read depending on the current state of the pin
5. gt _ Figure 11 1 UART Block meh 11 2 SERIAL INTERFACE SIGNALS There are five UART signals that you can acce ny or all of the UART signals the appropriate port bits can be programmed to u ir UART function Refer to Section 7 Parallel Ports for information abo ogramming the ports TXD The transmit data pin is data is an output In infra red m transmitted For RS 232 app transmitter For infra red applications r serial output During normal mode NRZ bit period pulse is output for each 0 bit pin must be connected to an RS 232 is pin can directly drive an infra red transceiver module e CTS The clear i active low input that controls the transmitter Normally the tr i until this signal is active low before transmitting a character If S bit is set the transmitter sends a character whenever a character i smit This signal can then serve as a general purpose input with a rea e CTS STATUS bit This pin can post an interrupt on any tran If if the interrupt is enabled e receive data pin is the receiver serial input During normal operation NRZ Non Return to Zero data is expected In infrared mode a narrow pulse is expected for received Use external circuitry to convert the infra red signal to an electrical signal RS 232 applications need an external RS 232 receiver to convert from RS 232 voltage levels 11 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information
6. Bir 45 44 as 42 41 10 9 8 7 6 5 gs 2 4 0 FIELD COMPARE VALUE RW RW RESET OxFFFF ADDR Ox FF FFF604 TIMER 1 AND Ox FF FFF610 TIME COMPARE VALUE This field is used as a reference count matches this value a compare event is generated he timer counter 10 5 4 Timer Unit 1 and 2 Capture Registers The timer unit 1 and 2 capture TCR1 and TCR capture operation when an edge occurs on the read only and cleared at system reset TCR1 AND TCR2 N BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TURE VALUE ch the counter value during a ing TIN pin These registers are R W R RESET 0x0000 ADDR Ox FF FFF606 TIMER 1 AND Ox FF FFF612 TIMER 2 CAPTURE V his field is a snapshot of the TCRx when a capture event occurs 10 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timers 10 5 5 Timer Unit 1 and 2 Counter Registers The timer unit 1 and 2 counter TCN1 and TCN2 registers are 16 bit read only registers You can read them anytime without disturbing the current count TCN1 AND TCN2 BT 15 14 13 12 11 10 9 8 7 6 5 41 3 2 1 0 FIELD COUNT RW R RESET 0x0000 ADDR Ox FF FFF608 OR TIMER 1 AND Ox FF FFF61
7. BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PUY PUO 0 0 0 0 0 0 0 0 RESET OXFFOO ADDR OXFFFFF41A 7 10 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD POL7 POL6 POLS POL4 POL3 POL2 POL1 POLO IQEN7 IQEN6 IQENS IQEN4 IQEN3 IQEN2 IQEN1 IQENO RESET 0x0000 ADDR OxFFFFF41C BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD 0 0 0 0 0 0 0 0 IQEG7 IQEG6 IQEGS 1Q IQEG3 IQEG2 IQEGt IQEGO RESET 0x0000 ADDR OXFFFFF41E DIR Direction 0 7 These bits control the direction of the correspondin corresponding port pin is an output pin and when it i input pin At reset these bits default to 0 ort a bit is high the e corresponding port pin is an D Data 0 7 These bits control or report the data on th the data to the pins Data can be re report the signal level on the pin pin Notice that the actual value o configured as edge sensitive i en the DIR bits are high D 7 0 control any bit While the DIR bits are low D 7 0 iting to a read only bit doe
8. m BBUSW DO TMS TCK Figure 16 2 M68328 Processor Signal Configuration 16 2 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications and Design Examples The PLLVCC and PLLGND pins should have a luf bypass capacitor as close to them as possible to reduce the noise induced into the PLL clock synthesis circuit In general PLLVCC and PLLGND can be connected to the main power supply with adequate filtering Bypass capacitors for normal VCC and GND pins are also recommended Because JTAG is not used in general operations those related signals TDI TMS and TCK should be pulled high through resistors to avoid unknown states The IRQ7 connects to a debouncing circuit in this example to generate a Level 7 interrupt of the M68328 processor when the ABORT button is activated Y Note PLLVCC must always operate at 3 3V even when using the 5V MC68328 version 16 1 2 Memory Interface 16 1 2 1 EPROM INTERFACE The M68328 processor supports both 8 bit and 16 bit de individually programmed for 8 or 16 bits however externally supplied BBUSW signal Figure 14 3 to EPROM The OE signal controls the EP processor performs a read cycle 8 bit or 16 CSAO is connected to the CE signal of th connected to the CE signals of the other E can tie the EPROM CE signal to However this is not recommen in will be on all the time c
9. the clock is always off Set the WID time periods but it can be awakene These bits are not affected controller these bits are no PCEN or STOP bit aft nin set e PC EN bit When an interrupt disables the power ers should enter the doze mode by setting the s been serviced Typically it is the STOP bit that is When the MC68328 processor begins operation after reset the power controller is disabled and the MC68EC00O0 internal clock runs continuously To reduce the power consumed by the MC68ECO000 the power controller is enabled when the STOP or PCEN bit is set The value in the WIDTH register determines the duty cycle of the clock bursts that are applied to the MC68EC000 when PCEN is set If an interrupt is received the power controller is automatically disabled It is up to the interrupt service routine to re enable the power controller 15 8 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Phase Locked Loop and Power Control The CLKO pin is an external reference of the internal MC68EC000 clock If the external system does not require CLKO it can be disabled by clearing the CLKEN bit in the PLL control register further reducing the normal operation power consumption 15 3 3 2 DOZE OPERATION The MC68EC000 clock can be disabled for extended periods by setting the STOP bit or WIDTH register bits to 00000 and setting the PC EN
10. GBA Group Base Address 31 This bit selects the starting address the group base mask register define t the address on the ad roup address range The corresponding bits in lock size for the group This field is compared to ermine if the group is decoded ether or not the contents of its base address register and address mask re valid The programmed chip selects do not assert until this bit is set A reset clears this bitin each base address register 0 Content is not valid 1 Content is valid 5 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chip Select Logic 5 2 2 Group Base Address Mask Registers The group base address mask registers GRPMASKA GRPMASKD define the address comparison range for a group of devices When the bits in this register are set to 1 the bits in the corresponding address lines A 31 20 compare true don t care GRPMASKA GRPMASKD BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD GMA31 GMA30 GMA29 GMA28 GMA27 GMA26 GMA25 GMA24 GMA23 GMA22 GMA21 GMA20 RESERVED RW RW RW RW RW RW RW RW RW RW RW RW RW RESET 0x0000 ADDR Ox FF FFF108 10A 10C 10E GMA Group Mask These bits mask address A 31 20 They are used to se all the mask bits are cleared A 31 20
11. 7 1 1 Port K Programming Assume the slave SPI is to be enabled the master SPI and the PCMCIA are not used we would like to configure 0 1 and 2 as general I O input ports pins 6 and 7 as output ports and th i 3 4 and 5 are used for Slave SPI module 3 are clear to be used as slave SPI special purpose mode its 2 0 are set for I O mode in port K direction register OxCO bits 7 6 are set so that port pins are outputs bits 5 3 are clear have no effect on direction of the pins bits 2 0 are clear so that port pins are inputs Value in port K data register bits 7 6 are written with the value to be output on port K pins 6 and 7 bits 5 3 when read contain the current value on the slave SPI pins bits 2 0 contain current value on port K pins 0 1 and 2 Special purpose pins SEL 0 can be either read from or written to If the pin is output only data can be written and read back via the data register If the pin is input only the value in 7 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports the corresponding bit in the data register can be read This value reflects the current logic level on the pin Writing to this bit has no effect 7 2 PULL UP PORTS The pull up ports E F G K and M operate just like the basic ports except they have some additional pull up resistors to be configured Each port has four configura
12. For More Information On This Product Go to www freescale com gt on zZ a8 ma SE 2u Om ma ee gt m lt 5 m gt Freescale Semiconductor Inc Serial Peripheral Interface Slave PHA Phase This bit sets the phase relationship between SPSCLK and SPSRxD Refer to Figure 9 2 0 Phase 0 normal data is captured on the leading edge of SPSCLK 1 Phase 1 data is captured on the trailing edge of SPSCLK POL Polarity This bit controls the polarity of the SPSCLK 0 The inactive state value of the clock is low idle 0 1 The inactive state value of the clock is high idle 1 SPISEN Slave SPI Enable This status bit enables the slave SPI module 1 SPIS module enabled 0 SPIS module disabled default DATA These are the data bits shifted from the external device At every 8th SPSCLK edge data from the peripheral is loaded into this buffered data buffer is not accessed an interrupt N NV amp before the next byte is received it will be Ww e OVRWR bit will be set posting 13 4 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 14 PULSE WIDTH MODULATOR The pulse width modulator PWM provides high quality sound generation and accurate motor control This section describes the PWM block The PWM is a simple free running counter with two compare registers that each perform a part
13. PG3 TOUT2 TIMER 2 OUTPUT PORT G 3 This bidirectional signal can be programmed to toggle or generate a pulse of one system clock duration when timer counter channel 2 reaches a reference value By default after reset this pin becomes general purpose input PG3 2 1 14 PWM Pin PG2 PWMO PULSE WIDTH MODULATOR OUTPUT PORT G 2 This pin can serve as the PWM output signal When it is PWMOUT it produces synthesized sound which can be connected to a filter and audio amplifier to generate melody and tone By default after reset this pin becomes general purpose input PG2 2 1 15 Real Time Clock Pins PG7 RTCO REAL TIME CLOCK OUTPUT INPUT PORT While PCO MOCLK is high this pin is a dedicated input that pro kHz clock to the real time clock While PCO MOCLK is i output constant time tick pulses at the crystal frequency MOCLK is low this pin becomes general purpose in s the 32 768 kHz or 38 4 n be programmed to after reset while PCO 2 1 16 LCD Controller Pins LD3 LDO LCD DATA BUS This output bus transfers pixel data to accommodate the programmal one two or four bits are supporte inverted for those LCD panels that re nel for display The pixel data is arranged e data width selection Panel interfaces of can also program the output pixel data to be ire it uses LDO to display pixel 0 0 Some LCD panel nel data bus where data bit 3 of the panel displays pixel tions from the MC68328 LD bus to th
14. a LU D l wi cc O E Ps m gt T m Q e le O ES Freescale Semiconductor Inc Real Time Clock 9 3 2 RTC Alarm Register The real time clock alarm ALARM register specifies the exact time that the real time clock will generate an alarm interrupt to the processor The HOURS MINUTES and SECONDS fields of this register can be read or written at any time After a write the alarm timer assumes the new values Unused bits read 0 ALARM BT 31 30 29 28 27 26 25 24 23 22 12120 19 18 17 16 FIELD HOURS NUTES RW R W R W RW MW RESET 0x00000000 ADDR Ox FF FFFB04 FIELD SECONDS R W R W R W RESET 0x0000000 ADDR AN HOURS When this field is read the current s e alarm s hour can be set to any value between 0 and 23 decimal t MINUTES When this field is read the cu ing of the alarm s minute can be set to any value between 0 and 59 decim SECONDS When this fie current setting of the alarm s second can be set to any value between decimal 9 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Real Time Clock 9 3 3 RTC Control Register The real time clock control CTL register has two configurable bits that enable or disable real time clock operation and select the
15. Addr Valid to OE Asserted 4 CE1 CE2 Access Time OE CE1 CE2 Negated to Data High Impedance Addr Invalid to Data Invalid Hold Time MOTOROLA MC68328 USER S MANUAL 11 10 97 17 8 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics e 1 gt U us re aN E A31 A0 2 oc zui gt zo oc lt Q al E Lu XL mre MES 9 D15 DO Figure 17 5 PCMCIA Read 17 5 DCELECTRICAL SPECIFICAT CHARACTERISTIC SYMBOL Input high voltage except EXTAL Input low voltage Vi GND 0 3 0 8 vV Clock input high voltage E VIHC 0 7 Vop Vpp 0 3 V y pins lin 1 0 uA 4V 0 4V Its 5 0 uA Vou 0 8Vpp V VoL 0 4 vV Cin 7 pF 14 Load capacitance 3 CL 50 pF NOTES 1 Not including internal pull up 2 Currents listed are with no loading 3 Capacitance is periodically sampled rather than 100 tested MOTOROLA MC68328 USER S MANUAL 11 10 97 17 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics wo e E Qn am z ToO Ex ga w no MOTOROLA MC68328 USER S MANUAL 11 10 97 17 10 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 18 MECHANICAL SPECIFICATIONS
16. EXTA CRYSTAL PHASE LOCKED SYSCLK ILLATOR lise iat PIXCLK DMACLK CLK32 Figure 15 1 PLL Block Diagram 15 1 PROGRAMMING MODEL The PLL has three registers that provide complete control and status information Descriptions of these registers follow MOTOROLA MC68328 USER S MANUAL 11 10 97 15 1 For More Information On This Product Go to www freescale com bu ZI Sti vu om 39 m DA om oo jo 3o os Q Freescale Semiconductor Inc Phase Locked Loop and Power Control 15 1 1 PLL Control Register This register illustrated in Figure 3 2 controls the overall PLL operation Several bits are provided for control of the dynamic performance of the PLL Refer to Section 3 4 3 for operation details 15 14 13 12 11 10 9 8 f 6 5 4 3 2 1 0 UNUSED PIXCLK SEL SYSCLK SEL UNUSED CLKEN DISPLL RSVD Address FF FFF200 Reset Value 2410 PIXCLK SEL These bits select the master frequency for the LCD pixel clock The master clock is derived from the VCO frequency as shown by the list below 000 VCO 2 001 VCO 4 010 VCO 8 011 VCO 16 1XX VCO 1 binary 100 after reset SYSCLK SEL These bits select the master frequency for cree 328 processor system clock The ncy as master clock is derived from the VCO fre wn by the list below 000 VCO 2 001 VCO 4 010 VCO 8 011 VCO 16 1XX VCO 1 bin after reset These bits can be
17. Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter TX DATA Transmit Data This field is the parallel transmit data inputs While in 7 bit mode D7 is ignored While in 8 bit mode all bits are used Data is transmitted LSB first A new character is transmitted when these bits are written These bits are read as 0 11 4 5 UART Miscellaneous Register The UART miscellaneous UMISC register contains miscellaneous bits to control test features of the UART Some bits are intended for factory use only and should not be disturbed UMISC 1 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 np RX POL eo RW CLK FORCE RTS FIELD RES cac perg LOOP RESERVED cont RTS R W RW RW RW RW RW RW RESET 0x0000 ADDR Bits 8 11 and 15 Reserved These bits are reserved for factory testing a CLK SRC Clock Source This bit selects the source of the 1 ansmit and receive When high the bit clock is derived directly from the i ust be configured as an input When low normal the bit clock is supplied by d rate generator This bit allows high speed synchronous applications in which a k is provided by the external system Bit clock generated by rate generator Bit clock supplied fro IO input Error erate normal parity rate inverted parity error LOOP Loopback Mode This bit controls loopback for
18. MOCLK functioniis nee sable the PLL When the on chip PLL is enabled Bit 0 can be used as a enera O BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD DIR6 DIRS DIR4 0 DIR2 DIR DIRO 0 D6 D5 D4 0 D2 Di DO RESET 0x0000 ADDR OxFFFFF410 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD 0 0 0 0 0 0 0 0 0 SEL6 SEL5 SEL4 0 SEL2 SEL1 SELO RESET 0x0000 ADDR OxFFFFF412 MOTOROLA MC68328 USER S MANUAL 12 9 97 7 9 For More Information On This Product Go to www freescale com N E a Oo a pe Ww a oc lt a v gt a gt ka rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports DIR Direction 0 7 These bits control the direction of the corresponding port pin When a bit is high the corresponding port pin is an output pin and when it is low the corresponding port pin is an input pin These bits reset to O and have no effect on the pins while the SEL bits are low D Data 0 7 These bits control or report the data on the pins while the associated SEL bits are high If the DIR bits are high pins configured as output D 7 0 control the data to the pins When the DIR bits are low pins configured as input D 7 0 report the actual signal level on the pins The data bits may be read or written at any time If a pin is confi
19. RW RAW RW RW RW RAW R W RW RESET 0x00FF BIT A5 0 E 0 20 9 8 7 6 5 gt a N o FIELD INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO PWM WKB RSVD RTC WDT UART TMR2 SPIM R W RW RW RW RW RW RAW RW RW RW RW RW RW RW RAW RW RW RESET OxFFFF ADDR Ox FF FFF308 SPIM Wake Up SPI Master Interrupt 0 Disallow SPI master interrupt from waking up the pr 1 Enable SPI master interrupt to wake up the processor default at reset TMR2 Wake Up Timer 2 Interrupt 0 Disallow timer 2 interrupt from waking up th 1 Enable timer 2 interrupt to wake up t O efault at reset UART Wake Up UART Interrupt 0 Disallow UART interrupt from wa up processor 1 Enable UART interrupt to u ocessor default at reset WDT Wake up Watchdog Timer ri 0 Disallow watchdog timer interrupt from waking up the processor 1 Enable watchdog ti i pt to wake up the processor default at reset 0 interrupt from waking up the processor 1 Enab ck interrupt to wake up the processor default at reset Bit 5 These reserved and should remain at their default value WKB Wa p Keyboard Interrupt 0 Disallow keyboard interrupt from waking up the processor 1 Enable keyboard interrupt to wake up the processor default at reset PWM Wake up PWM Interrupt 0 Disallow pulse width modulator in
20. RW RW RW RW RW RESET Ox00FF BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD MinT7 MINT6 MINTS MINT4 MINT3 MINT2 MINT1 MINTO MPWM MKB RSVD MRTG MWDT MUART MTMR2 MSPIM R W RW RW RW RW RW RW RW RW RW RW RW W R RW RW R W RESET OxFFFF ADDR Ox FF FFF304 MSPIM Mask SPI Master Interrupt O Enable serial peripheral interface ma 1 Mask serial peripheral interface m efault at reset 5 E gt ce cr wz fe o MTMR2 Mask Timer 2 Interrupt O Enable timer 2 interrupt 1 Mask timer 2 interrupt def t MUART Mask UART Interrupt 0 Enable UART interrupt Bit 5 Reserved MKB Mask Keyboard Interrupt 0 Enable keyboard interrupt 1 Mask keyboard interrupt default at reset MPWM Mask PWM Interrupt 0 Enable pulse width modulator interrupt 1 Mask pulse width modulator interrupt default at reset MOTOROLA MC68328 USER S MANUAL 12 9 97 6 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller MINTO Mask External INTO interrupt 0 Enable INTO interrupt 1 Mask INTO interrupt default at reset MINT1 Mask External INT1 interrupt O Enable INT1 interrupt 1 Mask INT1 interrupt default at reset MINT2 Mask External INT2 interrupt O Enable INT2 interrupt 1
21. 0 PWM output is low 1 PWM output is high POL Polarity This bit controls the PWM output pin polarity Normall e output pin is set high at period boundaries and goes low when a width compa S 0 Normal polarity 1 Inverted polarity PWMEN Pulse Width Module b This bit enables the PWM While disable e PWM is in low power mode and the prescaler does not count The output pin is forced to 1 or O depending on the setting of the POL bit 0 PWM disabl Y Disabling the PWM may cause a glitch on the output depending on the current state of the counter 1 PWM enabled MOTOROLA MC68328 USER S MANUAL 11 10 97 14 3 For More Information On This Product Go to www freescale com x faa ae SS u5 36 gt oF U Se 2u be E DF Freescale Semiconductor Inc Pulse Width Modulator When this bitis set high the PWM is enabled and begins a new period The following actions occur The output pin changes state to start a new period The clock prescaler is released and begins counting The counter begins counting The comparators are enabled The IRQ bit is set indicating the start of a new period if IRQEN is set CLKSEL Clock Select These bits select the output of the divider chain The codings are 000 Divide by 4 001 Divide by 8 011 Divide by 32 100 Divide by 64 110 Divide by 256 111 Divide by 512 14 1 2 Period Register This register controls the PWM period When
22. 10 6 3 Watchdog Control and Status Register The watchdog control and status register WCSR consists of three control or status bits At power up or reset the watchdog timer is enabled WCSR BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WRST FI WDEN R W RW RW RW RESET 0x0001 ADDR Ox FF FFF618 WRST Watchdog Reset This status bit indicates whether a software reset has occurre writing a 0 to it nbe cleared only by 0 No watchdog timer reset occurs 1 A software reset has occurred TIMERS 8 Fl Forced Interrupt This bit selects whether an interrupt or a sof times out When this bit is set the gener register 0 Software reset mode T interrupt is disabled 1 Forced watchdog interrupt ins of software reset WDEN Watchdog Ena This bit enables the t hen this bit is low the watchdog is disabled default at reset et will occur when the watchdog timer is maskable in the interrupt mask tware interru MOTOROLA MC68328 USER S MANUAL 12 9 97 10 9 For More Information On This Product Go to www freescale com EE Timers Freescale Semiconductor Inc 10 10 S gt MC68328 USER S MANUAL 12 9 97 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc SECTION 11 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER The
23. Freescale Semiconductor Inc LCD Controller programmed plus one The default value will toggle the LACD signal on each new frame which is required by many LCD panel manufacturers LACD is also referred to as the M signal by some LCD panel manufacturers LACDRC BIT 7 6 5 4 3 2 1 0 FIELD ACD3 ACD2 ACD ACDO RW RW RW R W RW R W RESET 0x00 ADDR Ox FF FFFA23 ACD Alternate Crystal Direction Control 0 3 This bit represents the LACD toggle rate control code 8 7 LINE BUFFER CONTROL aa Y 8 7 1 LCD Pixel Clock Divider Regist The LCD pixel clock divider LPXCD regi as configure the pixel clock for the LCD display LPXCD A BIT 7 6 5 4 3 2 1 0 FIELD PCD5 PCD4 PCD3 PCD2 PCD PCDO RW RW NY RW RW R W RW RW RESET 0x00 ADDR Ox FF FFFA25 will be used directly which bypasses the divider circuit The PIXCLK source is selected by the PCDS bit in the LCKCON register 8 21 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com r O o Q e zZ pr e Fr m a Freescale Semiconductor Inc LCD Controller 8 7 2 LCD Clocking Control Register The LCD clocking control _CKCON register is used to configure the length of a DMA burst the number of clock cycles per DMA word access the size of the external bus interface and the pixel clock divider source
24. Mask INT2 interrupt default at reset MINT3 Mask External INT3 interrupt O Enable INT3 interrupt 1 Mask INT3 interrupt default at reset MINT4 Mask External INT4 interrupt 0 Enable INT4 interrupt 1 Mask INT4 interrupt default at reset MINT5 Mask External INT5 interrupt O Enable INT5 interrupt 1 Mask INT5 interrupt default at r i MINT6 Mask External INT6 interr O Enable INT6 interrupt 1 Mask INT6 interrupt defau Qz o4 Zm 33 Da oc D ra D 0 Enable IRQ2 interrupt 1 MaskIRQ2 interrupt default value at reset MIRQ3 Mask IRQ3 Interrupt 0 Enable IRQ3 interrupt 1 Mask IRQ3 interrupt default value at reset 6 10 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller MIRQ6 Mask IRQ6 Interrupt 0 Enable IRQ6 interrupt 1 Mask IRQ6 interrupt default value at reset MPEN Mask Pen Interrupt 0 Enable pen down interrupt 1 Mask pen down interrupt default value at reset MSPIS Mask Serial Peripheral Interface SPI Slave Interrupt 0 Enable SPI slave interrupt 1 Mask SPI slave interrupt default value at reset MTMR1 Mask Timer 1 Interrupt O Enable timer 1 interrupt 1 Mask timer 1 interrupt default value at reset MIRQ7 Mask IRQ7 Interrupt When set this bit indicates that the IRQ7 interrupt i itionally th
25. PARALLEL PORTS The DragonBall microprocessor supports up to 10 parallel ports that can be configured either as general purpose input output ports or as a dedicated peripheral interface There are three types of ports basic pull up and interrupt This section describes these ports and how to configure their functions 7 1 BASIC PORTS The basic ports A B C E F G J and K multiplex tw tions on each port pin A general I O function A special purpose function to support on chip mo e ta register direction register and rs affect the function direction and output i port For example you can configure rt to choose the associated pin s function Each port has three configurable 8 bit regist select register Each of the 8 bits in the re data of each of the corresponding eight pin each bit in the select register of a The direction register determines whethe ort pin is an output or input pin If you configure the SEL bit for a particular pin to be us ith a special purpose function then the direction of the pin will depend on that functio this case configuring the corresponding bit in the direction register doe e ffect on the pin The corresponding bit in the data ogic level on the pin If you configure the SEL bit for a particular I O function then you may have to choose whether this pin will If the port pin is used as an input pin the corresponding bit in current logic level on the pin If the por
26. Signals PK7 PK6 CE1 CE2 These pins can be programmed as either parallel I O port K7 6 or the PCMCIA 1 0 chip enable signals When programmed as the PCMCIA chip enables CE1 and CE2 are active low card enable signals driven by the MC68328 processor CE1 enables even bytes CE2 enables odd bytes CE1 and CE2 are decoded for assertion by CSD3 2 1 10 Master SPI Pins PKO SPMTXD MASTER SPI TRANSMIT DATA PORT K 0 This pin is the master SPI shift register output By default after reset this pin becomes general purpose input PKO PK1 SPMRXD MASTER SPI RECEIVE DATA PORT K 1 This pin is the input to the master SPI shift register By default general purpose input PK1 PK2 SPMCLK MASTER SPI CLOCK PORT K 2 This pin is the clock output when the SPIM is enable while the SPIM is idle In polarity 1 mode this sign reset this pin becomes general purpose input 2 1 11 Slave SPI Pins AN PK5 SPSCLK SLAVE SPI CLOCK PO This pin is the slave SPI clock output It after reset this pin becomes general purpose input PK5 DN EIVE PK4 SPSRXD SLAVE SPI REC TA PORTK4 This pin is the slave SPI shift register input By default after reset this pin becomes general In mode this signal is low is high during idle By default after PK3 SPSSE ABLE PORT K 3 This pin is the able While this signal is active 8 clocks shift data into the slave SPI Thi grammable to be active high or low By default after reset it bec
27. The TXD port directly interfaces with popular infra red transceivers 11 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter 11 3 2 Receiver The receiver accepts a serial datastream and converts it into a parallel character It operates in two modes 16x and 1x In 16x mode it searches for a START bit qualifies it then samples the succeeding data bits at the bit center Jitter tolerance and noise immunity are provided by sampling at a 16x rate and using a voting technique to clean up the samples In 1x mode RXD is sampled on each rising edge of the bit clock After locating the START bit the DATA bits PARITY bit if enabled and STOP bits are shifted in If PARITY is enabled parity checking is performed and its status is reported in the UART receiver register Similarly frame errors and breaks are checked and reported When directly control the pin As with the transmitter the receiver FIFO is flexible If y remains in the FIFO the FIFO can then be e latency the FIFO half interrupt is used Thi entered into the FIFO If the FIFO is not interrupt is generated whenever one or m ta ready interrupt is used This ters are present in the FIFO er expects narrow pulses for each 0 bit When the infra red mode is ena r received otherwise normal NRZ is d An infra red transceiver
28. register should be configured so that DragonBall s external and internal interrupts can be handled properly by their software handlers If an interrupt occurs before the IVR has been programmed the interrupt vector number OxOF is returned to the CPU as an uninitialized interrupt which has the interrupt vector 0x3C ir 4 BIT 7 6 5 4 3 2 1 0 FIELD VECTOR y 0 RW RW R R RESET ADDR Ox FF FFE300 VECTOR This field is the upper five bits of the interrupt 0 These lower three bits are always se infroms the interrupt r whether the interrupt signal is an edge triggered or level sensitive in s whether it has positive or negative polarity ICR BIT 15 IN eae oc se 4 ie 2 i 0 FIELD PO ET3 ET6 RESERVED RESET 0x0000 R W R W ADDR Ox FF FFF302 POL1 Polarity 1 This bit controls interrupt polarity on IRQ1 In level sensitive mode negative polarity means that an interrupt occurs when the signal is at logic level low Positive polarity means that an interrupt occurs when the signal is at logic level high In edge triggered mode negative polarity means that an interrupt occurs when the signal goes from logic level high to logic 6 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller leve
29. 1 Table 2 1 Signal Groups CEI TIO VACIA CTO Lower Data Bus PBIO PB7 PB0 D7 DO Upper Data Bus D15 D8 CEI i Se Bus Control PCIO PC1 UDS PC2 LDS PC5 DTACK AS F W OEF Interrupt Control PDIO Keyboard PD7 PDO KB7 KBO NT7 INTO EATA nterrupt A a ce a O a propor A CI A A A SPI Master TWA XDO PK1 SPMRXDI PK2 SPMCLKO 3 SPI Slave f PKSISPSEN PK4 SPSRXDI PK5 SPSCLKI 3 r P Yov a SNOILdIHOS3d IWNDIS 7 Note All pins except EXTAL support TTL levels EXTAL when used as an input clock needs a CMOS level To ensure proper low power operation all inputs should be driven CMOS level Using a TTL level to drive those inputs could result in higher power consumption 2 2 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt a m o le E v l e 2 z Freescale Semiconductor Inc Signals 2 1 1 Power Pins The MC68328 processor has 20 power supply pins Users should be careful to reduce noise potential crosstalk and RF radiation from the output drivers Inputs may be 5 V or 3 3V when VDD 3 3V or 5V respectively without damaging the device e VDD 7 7 power pins VSS 9 9 ground pins e PLLVDD 1 1 power pin for the PLL e PLLVSS 1 1 ground pin for the PLL 2 1 2 4 Clock Pins EXTAL EXTERNAL CLOCK CRYSTAL INPUT low frequency phase lo
30. DO RESET 0x0000 ADDR OXFFFFF438 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FIELD 0 o o o o o SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO RESET 0x0000 ADDR OXFFFFF43A re 0 7 DIR Di These bits control the direction of the corresponding port pin When a bit is high the corresponding port pin is an output pin and when it is low the corresponding port pin is an input pin These bits reset to O and do not affect the behavior of the pins while the SEL bits are low D Data 0 7 These bits control or report the data on the pins When the DIR bits are high D 7 0 control the data to the pins Data can be read from or written to any bit While the DIR bits are low D 7 0 report the signal level on the pins In this case writing to a read only bit does not affect 7 16 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com v gt a gt ka rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports the pin Notice that the actual value on the pin is reported when a pin is read At reset all data bits default to 0 SEL Select 0 7 The select register allows you to individually select the function for each port pin When you set a bit in this register the corresponding port pin is configured as a genera
31. Data High Impedance oO 30 ns 21 JAS Asserted to UWE WE Assented o O f oo f o ms 22 JOWE CWE Width Assented SSCS S 23 AS UDS DS Negated to Datalnval Ja frs 24 OWE WE Negatedio Data Invalid Ts 25 UWE CWENegated to TS Negated RO y 17 2 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics SO S 2 S3 A S FG S7 SO Sl KLIS x j z0 o A31 A0 a A LO gt AS 10 Ne O Ei gt 10 N RW gt Pa 7 gt a Yo wo e E Qn am z ToO Ex ga w no Ag E Al Figure 17 1 Chip Select Write Cycle Timing when CPU is Bus Master MOTOROLA MC68328 USER S MANUAL 11 10 97 17 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics Table 17 2 AC Electrical Specifications Chip Select Read Cycle Timing CHARACTERISTIC UNIT EEC a fs 2 Aadcr Valid o CSexAssered SSCS Y 3 3 E m Cc m O 4 2 e gt ka gt n 0 CLKO High to R W Valid AS High to R W Invalid AS High to CSxx Negated CSxx Width Negated CLKO High to OE Invalid CLKO Low to AS UDS LDS Negated AS UDS LDS Negated to DTACK Negated DTACK Asserted Data In Valid Data Inp
32. EN MODE EN EVEN EN EN R W RW RW RW RW RW RW RW RW RW RW RESET ADDR UART EN UART Enable This bit enables the UART TN the UART is disabled to save power When is bit re it is high the UART is active Th eceiver register to initialize the FIFO and character status bits 0 UART disabled 1 UART enabl 7 he RT is first enabled after a cold reset before enabling interrupts set ARTEN and RXEN bits and perform a word read operation on the UART r RX EN eiver Enable This bit enables the receiver block When this bit is low the receiver is disabled and the receive FIFO is flushed This bit resets to 0 O Receiver disabled and receive FIFO flushed 1 Receiver enabled MOTOROLA MC68328 USER S MANUAL 12 9 97 11 7 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter TX EN Transmitter Enable This bit enables the transmitter block When this bit is low the transmitter is disabled and the transmit FIFO is flushed This bit resets to 0 0 Transmitter disabled and transmit FIFO flushed 1 Transmitter enabled CLK MODE Receiver Clock Mode This bit controls the operating mode of the receiver When this bit is low the receiver is in 16x mode where it synchronizes to the incoming data stream and samples at the perceived
33. Go to www freescale com v gt a gt ka rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports AA ated eles Oy A A a a FIELD DIR7 DIR6 DIRS DIRA DIRS DIR2 pIR1 pIRO D7 D6 D5 D4 D3 D2 bt DO RESET 0x0000 ADDR OXFFFFF448 BIT 15 A ks a al 10 9 8 7 6 5 4 3 2 1 0 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PU1 PUO SEL7 SEL6 SEL5 S SEL3 SEL2 SEL1 SELO RESET OXFF02 ADDR OXFFFFF44A DIR Direction 0 7 These bits control the direction of the correspondin associated port pin is an output pin and when it is lo pin These bits reset to 0 and do not affect the b i a bit is high the esponding port pin is an input ins while the SEL bits are low D Data 0 7 These bits control or report the data on th the data to the pins Data can be re D 7 0 report the signal level on th on the pin Notice that the actual value data bits default to 0 case writing to a read only bit does not affect in is reported when a pin is read At reset all PU Pull Up 0 7 These bits enable the pull up resistors on the port When high the pull up resistors are low the pull up resistors are disabled The pull ups are enabled ister allows you to individually select the function for each port pin When you is register the corresponding port pin
34. Inc Real Time Clock The real time clock may be in the process of updating the hours minutes or seconds data so the data value may be incorrect if a read and an update occur at the same time When reading this register you should make two reads and compare the results If the reads do not compare make another read and use the new value The following code fragment illustrates the preferred method Hours minutes and seconds values are returned in the CPU s DO register These operations must be completed within 1 second move l HMS DO make the first read cmp l HMS DO make the second read and compare beq s GOOD if the reads compare done move l HMS DO bad compare make another read GOOD rts return RHMSR Ya BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD HOURS MINUTES R W R W R W R W R W RESET 0x000000 ADDR 0x hd R RESET x00000000 ADDR NZ Ox FF FFFBOO nt hour can be set to any value between 0 and 23 decimal Id will update the hour of the current time SECONDS R W SECONDS When this field is read the current second and can be set to any value between 0 and 59 decimal Writing a new value to these bits will update the new second of the current time MOTOROLA MC68328 USER S MANUAL 12 9 97 9 3 For More Information On This Product Go to www freescale com x a o
35. M328BASE 000 Chip Select Registers CS Group Base Registers GRPBASEA equ M328BASE 100 GRPBASEB equ M328BASE 102 GRPBASEC equ M328BASE 104 GRPBASED equ M328BASE 106 CS Group Mask Registers GRPMASKA equ M328BASE 108 Sa GRPMASKB equ M328BASE 10A m3 GRPMASKC equ M328BASE 10C 25 GRPMASKD equ M328BASE 10E mo Group A CS Registers Te CSAO equ M328BASE 110 5 CSAL equ M328BASE 114 mz CSA2 equ M328BASE 118 CSA3 equ M328BASE 11C Group B Re ter CSBO equ M328BASE 120 CSB1 equ M328BASE 124 CSB2 equ M328BASE 128 CSB3 equ M328BASE 12C i Registers CSCO equ M328BASE 13 CSC1 equ M328BASE 134 CSC2 38 CSC3 3C i CSDO CSD1 CSD2 CSD3 PLLCE M328BASE 200 M328BASE 202 M32 8BASE 204 trol Registers equ M32 8BASE 206 7 PCTLR Interrupt Registers i i i Control Reg Freq Select Reg Test Reg Control Reg IVR equ M328BASE 300 Interrupt Vector Reg ICR equ M328BASE 302 Interrupt Control Reg IMR equ M328BASE 304 Interrupt Mask Reg IWR equ M328BASE 308 Wakeup Enable Reg ISR equ M328BASE 30C Interrupt Status Reg IPR equ M328BASE 310 Interrupt Pending Reg PIO Registers Port A Registers 16 6 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com PADIR PADATA PASEL PBDIR PBDATA PBSEL PCDIR PCDATA PCSEL PDDIR PDDATA PDPUEN PDPO
36. On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter e RTS The request to send pin is an output that serves two purposes Normally the receiver indicates that it is ready to receive data by asserting this pin low This pin would be connected to the far end transmitters CTS pin When the receiver detects a pending overrun it negates this pin For other applications this pin can serve as a general purpose output controlled by the RTS bit in the UART receiver register e GPIO The general purpose input output bidirectional pin has several functions It can be a general purpose input that can post interrupts on any transition is controlled by the GPIO bit in the UART baud control register can serve as the source of the clock to the baud rate generator or can output the bit clock at the selected baud rate O O O C 11 3 SERIAL OPERATION The UART module has two operating modes NRZ and infra associated with RS 232 Each character is transmitted a at the beginning and a Stop bit 1 at the end Data bits a first and each bit is presented for a full bit time If p is after the most significant bit Figure 11 2 illustrates an 8 bit odd parity aX RZ mode is usually limited by a Start bit 0 itted least significant bit d the parity bit is transmitted CII A character 41 hex with STOP BIT EE m
37. Ri 0 25 0 010 y J VZ GAGE PLANE La lt E gt y gt lt 61 R2 013 020 0 005 DETAIL C lt Z Cs 22 00 BSC 0 866 ea 11 00 BSC 0 433 BSC v 22 00BSC 0 8668 ve TT0085c 043E y 0 25REF 0 010R NT QOREF 0 039R 0 09 016 0 004 0 006 or 77 13 Figure 2 2 144 Lead Plastic Thin Quad Flat Package 2 12 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 3 ARCHITECTURE To improve total system throughput and reduce component count board size and cost of system implementation the DragonBall combines a powerful MC68EC000 processor with intelligent peripheral modules and a typical system interface logic The architecture of the DragonBall consists of the following blocks e ECOOO core Chip select logic and bus interface Clock synthesizer and power management Interrupt controller Parallel general purpose I O ports Timers e Low power stop logic N LCD controller UART e Real time clock Y e Pulse width modulat iliar with 68K architecture If you are not get a copy of the mber M68000UM AD and M68000 Programmer s er M68000PM AD from your local Motorola sales office MOTOROLA MC68328 USER S MANUAL 12 9 97 3 1 For More Information On This Product Go to www freescale com ARCHITECTURE O Freescale Semiconductor Inc Architecture SYNLOALIHOYV PARALLE
38. Rotate right without extend CMPA Compare address ROXL Rotate left with extend CMPM Compare memory ROXR Rotate right with extend CMPI Compare immediate RTE Return from exception DBcc Test cond decrement and branch RTR Return and restore DIVS Signed divide RTS Return from subroutine DIVU Unsigned divide SBCD Subtract decimal with extend MOTOROLA MC68328 USER S MANUAL 12 9 97 3 5 For More Information On This Product Go to www freescale com ARCHITECTURE O SAYNLOALIHOYV Freescale Semiconductor Inc Architecture Table 3 2 Instruction Set MNEMONIC DESCRIPTION MNEMONIC DESCRIPTION EOR Exclusive OR Scc Set conditional EORI Exclusive OR immediate STOP Stop EORI to CCR Exclusive OR immediate to condition SUB Subtract codes EORI to SR Exclusive OR immediate to status SUBA Subtract address register EXG Exchange registers SUBI Subtract immediate EXT Sign extend SUBQ Subtract quick JMP Jump SUBX JSR Jump to subroutine SWAP es LEA Load effective address TAS LINK Link stack TRAP LSL Logical shift left TRAPV LSR Logical shift right est MOVE Move K nlink MOVEA Move address 3 2 CHIP SELECT LOGIC AND B FACE The system control register SC II o configure the system status and control logic register double mapping bus r eration and module control register protection on the DragonBall mable general purpose chip select signals Each Thee mali face handles the transfer of information betwee
39. You can also use it to turn on the LCD controller LCKCON BIT 7 6 5 4 3 2 1 0 FIELD LCDON DMAt6 WS3 ws2 WS1 WSO DWIDTH PCDS RW RW R W RW R W RW R W RW RW RESET 0x40 ADDR Ox FF FFFA27 LCDCON LCD Control This bit controls the LCD controller 0 Disable the LCD controller 1 Enable the LCD controller Note The internal LCD control ic e simultaneously switched off with the FLM pulse DMA16 16 Word DMA This bit controls the lengt NG rst WS DMA B This bit r 0 clock cycle transfer 1000 9 clock cycle transfer 000 clock cycle transfer 1001 10 clock cycle transfer 0010 3 clock cycle transfer 1010 11 clock cycle transfer 0011 4 clock cycle transfer 0100 5 clock cycle transfer 0101 6 clock cycle transfer 0110 7 clock cycle transfer 0111 8 clock cycle transfer 1011 12 clock cycle transfer 1100 13 clock cycle transfer 1101 14 clock cycle transfer 1110 15 clock cycle transfer 1111 16 clock cycle transfer MC68328 USER S MANUAL 12 9 97 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc LCD Controller DWIDTH Data Width This bit displays memory data width that indicates the size of the external bus interface 0 16 bit memory 1 8 bit memory PCDS Pixel Clock Divider Source Select 0 Selects the SYSCLK output of the PLL 1 Selects the PIXCLK output of the
40. Zero wait states 001 One wait state 010 Two wait states 011 Three wait states 100 Four wait 101 Five wait 5 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chip Select Logic 5 3 PCMCIA 1 0 SUPPORT The Dragonball supports PCMCIA 1 0 memory card chip selects and read write signals To meet the fanout requirement use external buffers to interface to the memory card The PCMCIA address range is decoded with CSD3 CSD3 CHIP SELECT DECODE gt PCMCIA SE SIGNAL P DECODE Figure 5 2 PCMCIA Block a 5 3 1 PCMCIA Configuration SS C The DragonBall can access PCMCIA 1 0 re s by setting the decode range for CSD3 to the area of memory where the me card is to be accessed You must configure nd Bits 6 and 7 of Port K bits must also be Bit 6 in Port C for its PCMCIA funct configured for their PCMCIA fun CE1 Read or write accesses to the area decoded by CSD3 asserts the corresponding PCMCIA control signals N x CONTROL ADDRESS DATA e o e l E o uu lu og 2 I o O MOTOROLA MC68328 USER S MANUAL 12 9 97 5 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chip Select Logic lt o p on m m m O 2 je Q o 5 10 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information
41. a 16 67MHz Processor Clock electable Bus Sizing Support for Connecting to 8 and 16 Bit Devices Cod n MOTOROLA MC68328 USER S MANUAL 11 6 97 1 1 For More Information On This Product Go to www freescale com 3 a O i Cc O e z Freescale Semiconductor Inc Introduction System Integration Module Supports Glueless System Design 1 System Configuration and Programmable Address Mapping L Memory Interface for SRAM EPROM and Flash Memory Sixteen Programmable Peripheral Chip Selects with Wait State Generation Logic LY PCMCIA 1 0 Support Interrupt Controller with 13 Flexible Inputs Programmable Interrupt Vector Generator Maximum of 77 Individually Programmable Parallel Port Signals Dual Channel 16 Bit General Purpose Counter Timer Multimode Operation Independent Capture and Compare isters Automatic Interrupt Generation 60ns Resolution for a 16 67MHz System Clock Hardware and Software Watchdog Timers Separate Input and Output Pins for Capture an ar O C O C O Phase Locked Loop and Power Management AU 3 3V Operation OY Fully Static HCMOS Technology 11 Programmable Clock Synthesizer for Full Frequency Control 1 Doze Mode Capability LL Low Power Mode Control L1 CPU Can Be Shut Dow e L Sleep Mode Can Be Eneas utting Down the Phase Locked Loop PLL LCD Controller U Software Programmab en Size to Drive Single Monochrome STN Panels L Directly Drives Common LCD Drivers an
42. a DMA access is in progress the CPU will wait until the DMA controller has completed its access before interrupt processing begins Figure 15 3 describes the power controller operation In this example the clock bursts at about 15 duty cycle so the MC68EC00O0 is active about 15 of the time The remainder of the time the MC68ECO000 is in sleep mode When a wakeup event occurs the clock immediately restarts so the processor can service the wakeup event interrupt The power controller burst period is 31 CLK32 periods or approximately 1 msec Note that the LCD DMA controller has access to the bus at all times and the SYSCLK master clock to all peripherals is continuously active pe 1 MSE SYSCLK CPUCLK CPU ACTIVE CPU ACTIVE CPU DOZE CPU ACTIVE Figure 15 3 Po c ol Operation 15 3 2 MPU Interface One register is associated with the po control block Figure 3 6 illustrates the bits in the power control register PCTL 15 14 13 12 pJ 9 8 7 6 5 4 3 2 1 0 l 39 oE 2 QQ Se a su we wa za rZ aa RSVD PCEN STOP 0 WIDTH Address FF FFF206 b Reset Value 001F PC E This bit ols the operation of the power controller While this bit is low the clock to the is continuously on While this bit is high the clock is bursted to the MC68EC000 under control of the width comparator An interrupt that can wake up the MC68ECO000 disable
43. all other chip selects are negated You should use CSAO to decode an EPROM ROM memory s In this case the first two long words of the EPROM ROM memory space shoul ammed to space and the initial PC should point to the start up code within the EPROM ROM hat the processor can execute the start up code to bring up the system Note The DragonBall does not support the reset instruction It will not cause a reset RESET is an input only pin on the Drago e information about core interrupts see the Motorola application note called A n of Interrupts for the MC68000 part number AN1012 6 3 INTERRUPT CONTROLL When interrupts are rec ntroller they are prioritized and the highest enabled pending interrupt is p Before the CPU responds to this interrupt the status register is copied inte he S bit of the status register is set which puts the processor into The CPU then responds with an interrupt acknowledge s of the address bus reflect the level of the current interrupt The interr erates a vector number during the interrupt acknowledge cycle s this vector number to generate a vector address Except for the reset CPU saves the current processor status including the program counter value to the next instruction to be executed after the interrupt and the saved copy gister The new program counter is updated to the content of the interrupt vector which points to the interrupt service routine The CPU then resumes instruction exec
44. an active low pulse for on clock or a toggle output The output can also be used as a loopback input to the seco mer which results in a 32 bit timer Each timer has a 16 bit timer capture register that latches the value of the counter when a defined transition of TIN1 or TIN2 is sensed by the corresponding input capture edge detector You can select the type of transition that is triggering the capture by configuring the CE field in the TCTLx When a reference event occurs the CAPT bit is set in the TSTATx and a maskable interrupt is generated to the processor Neither timer is active at reset and must be programmed according to your application 10 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timers 10 3 SOFTWARE WATCHDOG TIMER OPERATION The software watchdog timer protects against system failures by enabling you to escape from unexpected input conditions external events or programming errors This dedicated 16 bit timer serves as the software watchdog timer You can program the watchdog compare register WRR with the timeout value The watchdog counter will start counting from O until it reaches this timeout value If your software does not clear the counter before it reaches the timeout the timer assumes that a system failure has occurred and the software watchdog logic initiates either a soft reset of the chip or a maskable interrupt to th
45. asserted For each memory area you c cycle termination signal called DIACK with a p The 16 general purpose chip selects allo used in a system without external decode configuration would be an 8 bit EP and a nonvolatile flash memory more information te generation logic A typical bit SRAM four simple I O peripherals 6 Applications and Design Examples for MOTOROLA MC68328 USER S MANUAL 12 9 97 5 1 For More Information On This Product Go to www freescale com e o e l E o uu lu og 2 I o O Freescale Semiconductor Inc Chip Select Logic GROUP BASE REGISTER CHIP SELECT BASE REGISTER ADDR gt gt gt q UDS gt Y LDS gt COMPARE LOGIC gt COMPARE LOGIC RW gt AS gt A A CSAD GROUP MASK REGISTER CHIP SELECT MASK REGISTER gt CSAT gt CSA2 CSA CSAO gt CSAS CSB CSA1 3 gt CSA3 CSC csa2 CSD CSA3 Ls JJ AX gt CSD3 CO OGI DTACK __ DTACK GENERATION lt lt b y gt gt Y O gt F 0 D o zl O S o S e v on m m O 4 las e 2 o chip select is programmable and the registers have read write capability so that the program
46. at the default multipl P 0x23 Q 0x1 with a 32 768kHz crystal or multiplier of 432 P 0x1D Q 0xB with a 38 400kHz crystal With a 32 768kHz crystal standard baud clocks can be generated to within 0 05 accuracy With a 38 400kHz crystal the baud clocks are generated with 0 error Table 11 1 indicates the values to use in the UART baud control register for these system frequencies Note When CLK MODE is set to 1 1x mode the divide by 16 block is bypassed so the generated clock will be 16 times faster 11 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter 11 3 4 MPU Interface The MPU interface includes all status and control registers and all miscellaneous logic This block directly connects to the internal 68000 bus and provides address decode for three address lines and a full 16 bit read write port The interrupt line is the logical OR of the eight interrupt sources When the UART EN bit is low the master clock to all UART blocks is disabled thus keeping power consumption to a minimum 11 4 PROGRAMMING MODEL 11 4 1 UART Status and Control Register The UART status and control USTCNT register controls overall U ration USTCNT BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TX TX TX EMPTY HALF AVAIL EN RXRDY FIELD UART RXEN TXEN CLK PARITY ODD En
47. bit to 1 The MC68EC000 clock is enabled again when it receives an interrupt At the end of the service routine the power controller can be re enabled putting the MC68EC000 back into DOZE mode Once the MC68EC000 clock is disabled only an interrupt or hardware reset can re enable it Users can program the duty cycle register WIDTH bits for burst d between 0 31 and 31 31 This effectively provides a variable cloc and power dissipation of between 0 and 100 of the system clock freq remental steps However by setting the STOP bit most applications will e the least amount of power by entering doze mode whenever possible While in DOZE mode the port I O pins remain in the stat CLKO may still be active while the processor core i operation CLKO should be disabled CLKO is c register The data bus is pulled up by internal pu in DOZE mode and the LCDC is not using th mode For lowest power the CLKEN bit of the PLL control while the MC68ECO000 core is s to load screen refresh data 15 3 3 3 SLEEP OPERATION The PLL is disabled in the SLEE the 32 kHz clock continuously operates to keep the real time clock operation p events can activate the PLL and the system clock will begin to operate in 2 msec SLEEP mode is entered by setting the DISPLL bit in the PLL Control Regi Section 3 2 5 for more information While in SLEEP mo O pins remain in the state prior to entering SLEEP mode CLKO will not be fesist he PLL i
48. data b an program the polarity of the FRM LP and SCLK signals as well as pixel d ypes of LCD panels synchronized so you must program register As a general rule select rosstalk characteristics cause the pes of LCD panels even from the same oO MOTOROLA MC68328 USER S MANUAL 12 9 97 8 3 For More Information On This Product Go to www freescale com ao WwW pa par O o Z Q o o a QO r O o Q e zZ pr e Fr m a Freescale Semiconductor Inc LCD Controller 8 2 OPERATION The LCD s DMA controller is a fly by 16 bit wide fast data transfer machine The LCD screen has to be refreshed continuously at a rate of approximately 50 70Hz which means the image data in memory is periodically read and transferred to the corresponding pixels on the screen The refresh is divided into small bursts of 8 or 16 word reads When the internal line buffer needs data it asserts the BR signal to request the bus from the core Once the core grants the bus by asserting the BG signal the DMA controller gets control of the bus signal and issues 8 or 16 word reads from memory During LCD access cycles the chip select logic asserts the output enable and chip select signals for the corresponding system memory chip inside the system integration module You can achieve the minimum bus bandwidth obstruction by using zero LCD access wait states 1 clock per access See Section 8 9 Calculating Bandw
49. equ SFFFF202 PLL Frequency Control Register 2COMPARE equ SFFF610 Timer 2 Compare Value Register 2CONTROL equ SFFF60C Timer 2 Control Register R equ SFFF304 Interrupt Mask Register move 1 IMR SP save the Interrupt Mask register move 1 Sfffffffd IMR enable ONLY Timer2 interrupt move w S0001 T2COMPARE set compare value to 2 move w 0119 T2CONTROL enable Timer 2 with CLK32 source SYNC btst b 47 PLLFREQ synchronize to CLK32 high level beg s SYNC CLK32 is still not high go back move w NEWFREQ PLLFREQ load the new frequency ori b 8 PLLCONTROL 1 disable the PLL in 30 clocks stop 2000 stop enable all interrupts the PLL shuts down here and waits for the Timer 2 interrupt 15 4 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Phase Locked Loop and Power Control interrupt service for Timer 2 occurs here move w SP IMR restore the Interrupt Mask Register rus PLL is now at the new frequency The PLL has reacquired lock and SYSCLK is stable The master frequency should only be changed during an early phase of the boot up sequence 15 2 5 PLL Shutdown The procedure for PLL shut down to place the system in sleep mode is made to the frequency The difference is that the system can be awaken ilar to changes below illustrates the flow It is assumed that all periph shut down before the PLL stops lea
50. frequency for the reference crystal clock CTL AAA FIELD ENABLE 38 4 RESERVED R W R W R W R W RW R W RESET 0x0000 ADDR Ox FF FFFBOC ENABLE RTC Enable 1 Enable real time clock O Disable the real time clock interrupts This doe n you are disabling the real time clock you are just disabling all real tim terrupts 38 4 38 4kHz Reference Select 1 Reference frequency is 38 4kHz 0 Reference frequency is 32 768 Bits 4 0 Reserved These bits are reserved and sho 9 3 4 RTC Interrupt S ter The real time clock in ister ISR indicates the status of the various real time clock interrupts Each bit i hen its corresponding event occurs You can clear an RTC interrupt by writi D cted when the processor enters doze or sleep mode This ISR BIT ea 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAY ALARM MIN sw FIELD 1HZ cag FLAG FLAG FLAG R W RW RW RW RW RW RW RESET 0x0000 ADDR Ox FF FFFBOE MOTOROLA MC68328 USER S MANUAL 12 9 97 9 5 For More Information On This Product Go to www freescale com x a e pa a LU D a wi cc O O E m gt T l m Q 2 le le A Freescale Semiconductor Inc Real Time Clock 1Hz FLAG 1Hz Flag When the 1Hz interrupt is enabled this bit is set every second
51. in the interrupt status r clear this interrupt When this bit is low IRQ3 is a level sensitive interrupt In this c ou must clear the external source of the interrupt O Level sensitive interrupt default atres 1 Edge sensitive interrupt ET6 IRQ6 Edge Trigger Select When this bit is set the IRQ6 sig you must write a 1 to the IRQ6 bit i rrupt status register to clear this interrupt When this bit is low IRQ6 is a lev itive interrupt In this case you must clear the external Bits 0O 7 Rese These bi reserved and should remain at their default value 6 5 3 rupt Mask Register The interrupt mask IMR is a control register that can mask out a particular interrupt if the corresponding bit for the interrupt is set There is one control bit for each interrupt source When an interrupt is masked the interrupt controller will not generate an interrupt request 6 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller to the CPU but its status can still be observed in the interrupt pending register At reset all the interrupts are masked and all the bits in this register are set to 1 IMR BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESERVED MIRQ7 MTMR1 MSPIS MPEN MIRQ6 MIRQ3 MIRQ2 MIRQ1 R W Rw RW RW
52. interrupt by writing a 1 to this bit writing a O has no effect 0 No level 3 interrupt is pending 1 Level 3 interrupt is pending IRQ6 Interrupt Request Level 6 When this bit is set it indicates that an external device is requesting an interrupt on level 6 If IRQ6 is set to be a level sensitive interrupt you must clear the source of the interrupt If IRQ6 is set to be an edge triggered interrupt you must clear the interrupt by writing a 1 to this bit Writing a O to this bit has no effect O No level 6 interrupt pending 1 Level 6 interrupt is posted 6 5 6 Interrupt Pending Register interrupts are pending If an the interrupt but not in the interrupt status it will be set in both registers The read only interrupt pending register IPR indicates interrupt source requests an interrupt but that interrupt is maskregister then that interrupt bit will be set in this regi register If the pending interrupt is not masked i i N lt BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESERVE IRQ7 TMR1 SPIS PEN IRQ6 IRQ3 IRQ2 IRQ1 R W R R R R R R R R RESET BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD INT7 INT6 411 INT2 INT1 INTO PWM KB RSVD RTC WDT UART TMR2 SPIM R W R R R R R R R R R R R R R RESET ADDR Ox FF FFF310 SPIM SPI Maste
53. is configured as a general purpose I O leared the corresponding port pin is configured as a peripheral interface 7 19 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports v gt E gt m p y e D 3 mn 7 20 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 8 LCD CONTROLLER The DragonBall liquid crystal display controller provides display data for an external LCD driver or LCD panel module The following list summarizes the main features of the LCD controller System Memory is Used as Display Memory Which Elimina e Need for Dedicated Video Memory Provides a Standard Panel Interface for Common LCD Dri Supports Single Screen Non Split Monochrome L Is e Fast Fly by 16 Bit Wide Burst DMA Screen Refresh sfers from System Memory e Maximum Display Size is 1 024 x 512 and i Split Panel Sizes Are 320 x 240 and 640 x 200 e Supports 1 2 or 4 Bit Wide LCD D Black and White or Four Out of Seven ous Gray Levels le to a Maximum of 32 x 32 Pixels Interfaces e Hardware Blinking Cursor that i e Supports Hardware Panning o 8 1 ARCHI As illustr re 8 1 the LCD controller consists of six main blocks e MP rface registers e Screen A controller Line buffer e Cursor control logic ao WwW
54. is enabled MOTOROLA MC68328 USER S MANUAL 12 9 97 5 3 For More Information On This Product Go to www freescale com e o e l E o uu lu og 2 I o O O o ie on m m m O 2 je Q o Freescale Semiconductor Inc Chip Select Logic 5 2 PROGRAMMING MODEL The chip select module of the DragonBall microprocessor contains registers that you can use to control external devices such as memory Chip selects do not operate until the register in a particular group of devices is initialized and the V bit is set in the corresponding group base address register The only exception is the CSAO signal which is the boot device chip select 5 2 1 Group Base Address Registers There are four 16 bit group base address registers GRPBASEA GRPBASED in the chip select module one for each chip select group The group base address registers and the group mask registers decode the upper address bits and the chip select option registers decode the lower address bits There are four chip selects in each gro r example in group A the chip selects are CSA0 CSA1 CSA2 and CSA3 GRPBASEA GRPBASED BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GBA GBA21 GBA20 RESERVED V FIELD GBA31 GBA30 GBA29 GBA28 GBA27 GBA26 GBA25 GBA24 R W RW RW R W Rw RW RW RW RW RW RW RESET ADDR FFF 2 104 106
55. lets you optimize a visual effect for your particular panel or application CODE MAPPING DATA GRAY CODE 00 f aooo MOTOROLA MC68328 USER S MANUAL 12 9 97 8 13 For More Information On This Product Go to www freescale com e WwW pa par O o Z Q o a o a r O o Q e zZ pr e Fr m a Freescale Semiconductor Inc LCD Controller Table 8 3 Gray Palette Selection GRAY PALETTE GRAY CODE DENSITY 8 2 9 Low Power Mode When the LCDON bit of the LCKCON register i e LCD controller enters a low power mode by stopping the pixel clock re the next line buffer fill DMA In this mode there can be no additional screen lay refresh operations Before entering low power mode the DMA contro be pointed to a blank screen image to prevent high logic levels on the L being driven to the LCD panel The high logic levels could cause increase umption led PANEL_OFF that turns off the panel for low power mode The not support this signal However a parallel I O pin used in conjunction wi switching device can be used to perform this function To turn off the panel usi llel 1 O pin follow these steps the LCD controller by clearing the LCDON bit tem software should ensure thatthe PANEL_OFF signal is deasserted before writing LCDON to 0 When the LCD controller is switched back on LCDON set to 1 DMA and screen refresh activities will resume synchronously To turn on an LCD di
56. midnight interrupt alarm interrupt and a stopwatch interrupt At reset all RTC interrupts are disabled IENR Br 15 14 13 12 ME FIELD 1HZEN ALMEN MINEN SWEN R W RW RW RW RW RW RESET 0x0000 ADDR Ox FF FFFB10 1HZEN 1Hz Interrupt Enable This bit enables an interrupt at a 1Hz rate 1 A 1Hz interrupt is enabled 0 A 1Hz interrupt is disabled 24HREN 24 Hour Interrupt Enable This bit enables an interrupt at mid 1 A 24 hour interrupt is enabled 0 A 24 hour interruptis disabl ALMEN Alarm Interr Ena This bit enables the terr 1 Ana ruptis enabled 0 Ana e t is disabled MINE e Interrupt Enable This bit es the minute tick interrupt 1 A minute tick interrupt is enabled 0 A minute tick interrupt is disabled MOTOROLA MC68328 USER S MANUAL 12 9 97 9 7 For More Information On This Product Go to www freescale com x a e pa re wi D wi cc O O Ps m gt T a E m e e O ES Freescale Semiconductor Inc Real Time Clock SWEN Stopwatch Interrupt Enable This bit enables the stopwatch interrupt 1 A stopwatch interrupt is enabled 0 A stopwatch interrupt is disabled Note The stopwatch counts down and remains at 3F hex until it is reprogrammed If this bit is enabled with 3F hex in the RTC stopwatch register an interrupt will be posted
57. on the next minute tick 9 3 6 RTC STOPWATCH REGISTER The real time clock stopwatch STPWCH programmable register c value When the stopwatch interrupt is enabled this countdo Value minute and an interrupt is posted when the countdown value reac tains countdown isdecremented every STPWCH Y BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD STOPWATCH COUNT R W R W R W RESET Ox ADDR FF FFFB12 STOPWATCH COUNT NS This field contains the wat ountdown value which can be a maximum of 62 minutes tiva The countdown will again until a nonzero value less than 63 minutes is written to this regi 9 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 10 TIMERS The DragonBall microprocessor contains two identical general purpose 16 bit timers and a software watchdog timer The block diagram of a timer module is illustrated in Figure 10 1 TIMER CLOCK E YSTEM CONTROLREGISTER PRESCALER DIV 16 ae pap 32KHZCLOCK PRESCALAR REGISTER CLOCKGENERATOR ja TIN EVENT REGISTER gt INTERRUPT MPUBUS COMPARE REGISTER a gt TOUT COUNTER REGISTER CAPTURE REGISTER y Figure 10 1 Ge CAPTURE DETECT rpose Timer Block Diagram 10 1 FEATURES The following list summarizes the main features of the genera
58. p DPN Figure 16 8 Hardware Configuration 16 14 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications and Design Examples 16 3 POWER SAVING TIPS You can save power on the MC68328 by following these tips Keep the core shut down as much as possible by putting itin doze mode Setthe STOP bit in the power control register during any peiod of inactivity Shut down the PLL to enter sleep mode Set the DISPLL bit in the PLL control register to conserve power when the processor is inactive for an extended period of time Avoid the following pull up resistor conditions to save the most power LY When an internal pull up is enabled on an input with an external low LL When an internal pull up is enabled on an I O with the inter it low evice driving it t device driving e outputs have an internal pull up that will not consume excess current whe driven high However some external devices may require that t i the MC68328 port be low to save the most power Disable the pull ups on inputs that are always ernally Inputs that are continuously driven from an external devic quire an internal pull up resistor istor on the MC68328 l O ports o a high or low state by the external You can save power by disabling the intern that are configured as inputs and always device Disable the I O port internal pu
59. pa par O o Z Q o o a Frame rate control e LCD panel interface QO MOTOROLA MC68328 USER S MANUAL 12 9 97 8 1 For More Information On This Product Go to www freescale com rc O i Q e pr e Fr m a Freescale Semiconductor Inc LCD Controller PIXCLK CLOCK CLOCK FAST SLOW ADDRESS JUUUL JUL LCD DRIVER the eae LCD gt INTERFACE MPU A 68EC000 INTERFACE H CORE REGISTERS FRAME CONTROL bag aa SCHEEN CURSOR DMA LOGIC Lat CS MI OE A SYSTEM m LINE BUFFER MEMORY AN y Figure 8 1 ontroller Block Diagram 8 1 1 MPU Interface trol registers that enable you to operate different features onnected directly to the MC68ECO000 core internal bus memor st to fill the line buffer You can program the number of DMA clock cycles 1 to 16 per transfer to support systems with varieable memory speed requirements When the DMA transfer begins one clock cycle is added to the first data word has one clock cycle added to the transfer and the number of clock cycles selected As shown in Figure 8 2 and Figure 8 3 this gives the initial chip select memory more time without generating a clock cycle penalty on subsequent data transfers of the line fill 8 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On T
60. system test purposes When this bit is high the receiver input is internally connected to the transmitter and the RxD pin is ignored This bit does not affect the transmitter 0 Normal receiver operation 1 Internally connect transmitter output to receiver input 11 16 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter RTS CONT RTS Control This bit selects the function of the RTS pin 0 RTS pinis controlled by the RTS bit 1 RTS pin is controlled by the receiver FIFO When the FIFO is full one slot remaining RTS is negated RTS Request To Send This bit controls the RTS pin while the RTS CONT bit is 0 0 RTS pinis 1 1 RTS pin is 0 IRDA EN IrDA Enable This bit enables the infra red interface 0 Normal NRZ operation 1 Infra red operation LOOP IR Loopback Mode for Infra Red This bit controls a loopback from transmitter to infrared interface This bit is provided for system testing O No infra red loop 1 Connect infra red transmit RX POL Receiver Polarity This bit controls the expected polarity of the received data infra red idle ceiver MOTOROLA MC68328 USER S MANUAL 12 9 97 11 17 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter 1
61. the pins Data can be read from or it While the DIR bits are low D 7 0 report the signal level on the pins Int ase writing to a read only bit does not affect the pin Notice that the actual value on t in is reported when a pin is read At reset all data bits default to 0 i RTCOUT bit is disabled and PG7 becomes an l time clock reference PU Pull Up 0 7 These bits enable th istors on the port When these bits are high the pull up resistors are ena n they are low they are disabled SEL S Thes ster allows you to individually select the function for each port pin When you set a bit is register the corresponding port pin is configured as a general purpose I O When a bit is cleared the corresponding port pin is configured as a peripheral interface At reset all bits in the select register are cleared 7 15 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com v gt po gt a rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports 7 5 8 Port J Registers Port J is multiplexed with eight chip select signals that are described in the table below Table 7 5 Port J Bit Functions BIT PORT OTHER FUNCTION FUNCTION As with other ports each bit can be individually i se as general purpose lO or chip selects a 10 DIRO sm 1 a a ida T 9 FIELD DIR7 DIR6 DIR5 DIRA DIRS IR D7 D6 D5 D4 D3 D2 D1
62. watchdog compare register WRR contains the reference value so that when there is a match between this value and the value in the watchdog counter the watchdog timer times out This value resets to OxFFFF WRR 4 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD COMPARE VALUE RW RW RESET OXFFFF ADDR Ox FF FFF61A COMPARE VALUE When the counter counts up to the value in thi or a maskable interrupt is generated depen status register WCSR The programme force interrupt mode changes in the WCS 10 6 2 Watchdog Counter i The watchdog counter register WCN 16 bit counter It can be read at anytime without disturbing the current c rite cycle to this register causes the counter and prescaler er an internal MC68328 reset he FI bit in the watchdog control and ue in the register will not be affected when the to be reset A write o Ss be executed on a regular basis so that the watchdog timer is never allowe ach the reference value during normal program operation WCN BIT 15 14 13 19 4 10 9 8 7 6 5 4 3 2 4 0 FIELD COUNT R W R W RESET 0x0000 ADDR Ox FF FFF61C COUNT This field represents the current count value 10 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timers
63. www freescale com Freescale Semiconductor Inc Timers CLKSOURCE Clock Source This field controls the clock source to the timer The stop count mode freezes the timer without causing the value in the counter to be reset to 0x0000 000 Stop count clock disabled System clock to timer System clock divided by 16 TIN pin is the clock source 1xx 32kHz or 38kHz clock 001 010 011 TEN Timer Enable This bit enables the timer module 0 1 TPRER1 AND TPRER2 Timer disabled Timer enabled Note When this bit transitions from 0 to 1 the registers are unaffected is re to 0x0000 The other BT 15 14 13 aaa 0 FIELD PRESCALER RW R W RESET 0x0000 ADDR Ox FF FFF602 TIMER 1 AND Ox FF FFF60E TIMER 2 MOTOROLA MC68328 USER S MANUAL 12 9 97 For More Information On This Product Go to www freescale com mines the divide value of the prescaler between 1 and 256 0x00 divides the OxFF divides it by 256 TIMERS 8 SYAWIL Freescale Semiconductor Inc Timers 10 5 3 Timer Unit 1 and 2 Compare Registers The timer unit 1 and 2 compare TCMP1 and TCMP2 registers are used as a reference value so that when the timer counter matches its value with these registers a compare event occurs These registers are set to all ones at system reset TCMP1 AND TCMP2
64. 1 18 S gt MC68328 USER S MANUAL 12 9 97 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc SECTION 12 SERIAL PERIPHERAL INTERFACE MASTER The serial peripheral interface SPI is a high speed synchronous serial port for communicating to external devices such as A D converters and nonvolati interface is a 3 or 4 wire system depending on unidirectional or bidirecti only function as a master device It is upward compatible with SPls that are rola s 6805 microcomputer chips The SPI master SPIM transfers data between the MC6 devices in bursts over a serial link Enable and clock sig sor and peripheral e exchange data evice the SPIM output port block diagram of the SPIM SPMCLK SPMRXD SPMTXD 6 ce wi T Es mE ag LL am ce ne MOTOROLA MC68328 USER S MANUAL 11 10 97 12 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Master POL 1 PHA 1 SPMCLK POL 1 PHA 0 SPMCLK POL 0 PHA 1 SPMCLK POL 0 PHA 0 SPMCLK SPMTXD SPMRXD Bo Pr Pra Bred 6s om Figure 12 2 Master SPI Operatio 12 1 OPERATION 12 1 1 Operation Within the SPIM Module To perform a serial data transfer follow the Set NS Data rate bits 15 13 SPMEN
65. 24 x 512 pixels in the grayscale mode at a refresh rate of 60 70Hz It is most efficient when the screen width is a multiple of the DMA controller s 16 bit bus width Due to the limitations of LCD driver technology large screens like 640 x 480 are usually organized in split screen format which is not supported by DragonBall The actual limit is the number of rows that require a high driving voltage The DragonBall s 4 bit LCD interface will drive up to 1 024 rows and a maximum of 512 columns 8 2 4 1 LCD SCREEN FORMAT The LCD panel s screen width and height can be programmed in the software Figure 8 5 illustrates the relationship between part of a large graphics file displayed on screen versus the actual page in pixel c lt q VIRTUAL PAGE WIDTH VPW SCREENSTARTING ADDRESS SSA ES Es h a SCREEN WIDTH XMAX a z A AS E E 5 T _ a z 2 e LE z fa g de Es a 3 CURSORXPOSITION ES oS z w CX0 32 I4 E a a uy gt E oO A CURSOR WIDTH CW gt Figure 8 5 LCD Screen Format lt The LCD e th LXMAX and screen height LYMAX registers specify the size of the LCD p LCD controller starts scanning the display memory at the location pointed to by th screen starting address LSSA register which means the LCD panel will display th aded area in Figure 8 5 The virtual page width VPW and virtual page height VPH parameters specify the maximum page width
66. 4 TIMER 2 COUNT This field represents the current count value 10 5 6 Timer Unit 1 and 2 Status Registers The timer unit 1 and 2 status TSTAT1 and TSTAT i indicate the status of each timer When a capture event occurs the CAPT bit wi tin these registers and when a compare event occurs the COMP bit is set ear these bits to clear the interrupt if enabled These bits are cleared 0x00 and will clear only if they have been read while set This requirement en terrupt will not be missed if it occurs BIT 15 14 13 FIELD CAPT COMP R W R W R W RESET 0x0000 ADDR Ox FF FFF60A TIMER 1 AND Ox FF FFF616 TIMER 2 CAPT When high it indicates that a capture event has occurred Writing 0 to this bit clears the timer capture register 0 No capture event occurred 1 A capture event occurred COMP Compare Event When this bit is high it indicates that a compare event has occurred 0 No compare event occurred 1 A compare event occurred MOTOROLA MC68328 USER S MANUAL 12 9 97 10 7 For More Information On This Product Go to www freescale com TIMERS SYAWIL Freescale Semiconductor Inc Timers 10 6 PROGRAMMING THE SOFTWARE WATCHDOG TIMER The software watchdog timer has a watchdog compare register a watchdog counter register and a watchdog control and status register 10 6 1 Watchdog Compare Register The 16 bit
67. 5 6 Base 0x140 CSDO 32 Group D Chip Select Option 0 Register 0x00010006 5 6 Base 0x144 CSD1 32 Group D Chip Select Option 1 Register 0x00010006 5 6 Base 0x148 CSD2 32 Group D Chip Select Option 2 Register 0x00010006 5 6 Base 0x14C CSD3 32 Group D Chip Select Option 3 Register 0x00010006 5 6 Base 0x200 PLLCR 16 PLL Control Register 0x2400 PLL Base 0x202 PLLFSR 16 PLL Frequency Select Register 0x0123 PLL MOTOROLA MC68328 USER S MANUAL 12 9 97 3 9 For More Information On This Product Go to www freescale com ARCHITECTURE O Freescale Semiconductor Inc Architecture Table 3 3 Programmer s Memory Map Continued ADDRESS NAME WIDTH DESCRIPTION RESET VALUE HEX PAGE Base 0x207 PCTLR 8 Power Control Register 0x1F PCTL Base 0x300 IVR 8 Interrupt Vector Register 0x00 6 6 Base 0x302 ICR 16 Interrupt Control Register 0x0000 6 6 Base 0x304 IMR 32 Interrupt Mask Register OxOOFFFFFF 6 8 Base 0x308 IWR 32 Interrupt Wakeup Enable Register OxOOFFFFFF 6 11 Base 0x30C ISR 32 Interrupt Status Register 0x00000000 6 14 Base 0x310 IPR 32 Interrupt Pending Register 6 17 Base 0x400 PADIR 8 Port A Direction Register 7 7 Base 0x401 PADATA 8 Port A Data Register 7 7 Base 0x403 PASEL 8 Port A Select Register 00 7 7 Base 0x408 PBDIR 8 Port B Direction Register 0x00 7 8 Base 0x409 PBDATA 8 Port B Data
68. 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt a m o le E v l e 2 z Freescale Semiconductor Inc Signals 2 1 3 System Control Pins RESET This active low input signal causes the entire MC68328 processor CPU and peripherals to enter the reset state cold reset Users should drive this signal low for at least 100 msec at initial power up to ensure that the crystal oscillator starts and stabilizes BBUSW Boot Bus Width Select This input defines the data bus width for the boot chip select CSAO BBUSW 0 means the boot chip select addresses an 8 bit memory space BBUSW 1 means the boot memory space is 16 bits wide Users can create a mixed 8 16 bit memory system by programming the memory space widths in the various chip select control registers 2 1 4 Address Bus Pins These are the address lines driven by the 68EC000 core or b ntroller for panel refresh DMA The chip select module can decode the entire 4 G address map In many applications only the lower portion of the address lines ed reserving any unused address pins for parallel I O functions A15 A0 These address output lines are not SS er I O signals PA7 PA0 A16 A23 These address lines are multiplexe A When programmed as I O ports they they are output only address signals These serve as general purpose I O ports o signals default to address lines at r re the address lin
69. 800000 Group Mask 8MB move w 0081 GRPBASED PERI 0x00800000 Ox00FFFFFF move w 0001 GRPBASEA Enable at the end J FE H He He He He ER Feke Fe He KR ERE ER ERE Ae He He EKER ER ER ERE e He eHe ERE RARA RARA Ae He Ae e He He He RARA EK t H LCD init i g EFE He e ede he de e he He He He He e He de e de ke de e He He Fe e He He e e EK e e He EER e e e He He He e ERK He He e He He He He He He He He He he e e He He He Hede e e MOTOROLA MC68328 USER S MANUAL 11 10 97 16 9 For More Information On This Product Go to www freescale com oF mo ge 25 ma 4 x DO ETA ae m aS Freescale Semiconductor Inc Applications and Design Examples jmp _main jmp to main program 16 2 2 Chip Select Access Time Calculation The time path that is critical in the M68328 processor application using the CS signals is shown in Figure 14 5 The chip select access time is from CS asserted to when data must be valid to the processor so Si S2 S3 S4 S5 S6 S7 wa a ASES ADDR CSxx y i taccess DATA lt n v Figure 16 5 AQ Timing An equation for the a DW can be developed from Figure 14 5 This equation applies to ECOOO core accesses taccess t2 wher ck cycle time w ber of wait states to be programmed in the chip select register 16 10 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appl
70. A19 26 A9 Pers 23 A10 Att 125 Af Mao 4 A12 A13 28 A13 Ata 29 ATA pe ais 13 AIS _CSA0 22 IGE Aig 2 A16 OE 240E A17 130 Af7 Aig 131 A18 Figure 16 3 EPROM Interface 16 4 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications and Design Examples 512KX8 512KX8 SRAM SRAM DO 13 Ag 112 A1 D8_13 p D1 14 D ra 11 A2 D9 14 a D215 59 a2 O0 A3 D10 15 p2 D3 17 p a39 M4 D11_17 D3 gt 17 n3 3 A B11 17 D4_18lb4 A4 8 A5 Di2_ 18154 D5 19 p5 A5 Z AG D13 19 55 D6 20 6 A7 D14 20 nida D6 A6 2 Dis 2112 D7 21 p7 A7 15 A8 21 07 Ag 27 A9 Ag 26 A10 Ato 123 At A11 125 At2 At2 14 A13 A13 28__A14 Ata 3__A15 A15 31 A16 CSB022 log Ate 12 A17 _CSB022 5 OE 24 G A17 30 A18 OE_24 3 LWE_29 W A18 1 A19 UWE 29 W 512KX8 SRAM CSB222 2 A16 OE_24 ES Al 30 A17 UWE 29 yy aig 1 A8 8 Bit Port SRAM Figure 16 4 SRAM Interface MOTOROLA MC68328 USER S MANUAL 11 10 97 For More Information On This Product Go to www freescale com A18 A19 16 5 DESIGN EXAMPLES a z lt n Z oS E lt 3 l a a lt Freescale Semiconductor Inc Applications and Design Examples 16 2 SYSTEM INITIALIZATION EXAMPLES 16 2 1 Software Listing 1 Initialization Code M328BASE equ FFF000 SIM28 System Configuration Registers SCR equ
71. ANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications and Design Examples PWM block PWM IRQ 500 15 auto clear after reading Timer block timerl capture 60a 0 clear by writing zero timer2 capture 616 1 clear by writing zero timer2 compare 616 0 clear by writing zero SPI Master block SPIM IRQ 802 7 clear by writing zero SPI Slave block SPIS IRQ 700 15 auto clear after reading Real Time Clock block Period IRQ f f fffb0e 6 clear by writing zero eliminate 1 Hz Flag fffb0e 4 clear by writing zero Day Flag fffb0e 3 clear by writing zero Alarm Flag ff fffb0e 2 clear by writing liminate Port D block edge mode bit IRQ f f 418 7 0 external IRQ sou System Interrupts IRQ7 30c 23 level mode IRQ1 f 30c 16 edge mode IRQ1 f 30c 16 level mode IRQ2 f f 30c 17 edge mode IRQ2 f 30c 17 level mode IRQ3 f 30c 18 e edge mode IRQ3 ff 30c t one level mode IRQ6 f 30c rnal IRQ source edge mode IRQ6 f 30c writing one 16 2 5 SPIM Initialization Example The following is an example system usin external device such as an A D converter M68328 processor Port PK7 serves uses a polling mechanism
72. CALCULATING BANDWIDTH The LCD s DMA controller consumes bus bandwidth by periodi This is an important consideration for the high performance h acces memory stem designer 8 9 1 Bus Overhead Considerations The following example describes the issues for estimatin dwidth overhead to the data bus Consider a typical scenario Screen size 320 x 240 pixels Bits per pixel 2 bits pixel Screen refresh rate 60 H System clock 16 67 Host bus size 16 bit DMA access c NF r 16 bit word The period 7 that the LCD controller must update one line of the screen is 1 1 iS 60Hz x 240lines EQ 1 69 4us Atthe e the line buffer must be filled The duration Toma which the DMA cycle will take up t us is T _ 320pixels x 2bitperpixel x 2clock Dee 16 67MHz x 16bitbus EQ 2 4 8us 8 26 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller Thus the percentage of host bus time taken up by the LCDC DMA is Poma P _ 48 us DMA 7 69 4 us EQ 3 6 92 oc Ww pa par O o Z Q o a o a QO MOTOROLA MC68328 USER S MANUAL 12 9 97 8 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller r O o Q e zZ pr e Fr m a 8 28 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www
73. Freescale Semiconductor Inc SECTION 1 INTRODUCTION INTRODUCTION The MC68328 DragonBall microprocessor is designed to save you time power cost board addition the signals between the CPU and a peripheral run from the same clock which could require time delays nected timed with the same nly the essential signals are brought ists of a surface mount plastic TQFP on your board designers Its functionality and glue logic are al clock fully tested and uniformly documented out to the pins The DragonBall s primary designed to leave the smallest possible fo This manual will discuss the details o DragonBall microprocessor Howe it assumes you have a basic knowledge of 68K architecture If you are not familiar wit you should get copies of the M68000 User s Manual M68000 Progra Reference Manual and A Discussion of Interrupts for the j s manual You can go to the Motorola website at http www motorola com ownload these documents or you can contact your local sales itialize configure and operate the ins the main features of the DragonBall microprocessor 00 Static Core Processor 1 100 Compatibility with MC68000 and MC68ECO000 Processors 1 32 Bit Internal Address Bus m 24 Bit External Address Bus with Optional 32 Bit Address Bus for a 4G Address Space 16 Bit On Chip Data Bus for MC68EC000 Bus Operations Static Design Allows Processor Clock to Be Stopped to Save Power 2 7MIPS Performance Using
74. IS Register 0x0000 SPIS Base 0x800 SPIMDATA 16 SPIM Data Register 0x0000 SPIM Base 0x802 SPIMCONT 16 SPIM Control Status Register 0x0000 SPIM Base 0x900 USTCNT 16 UART Status Control Register 0x0000 11 7 Base 0x902 UBAUD 16 UART Baud Control Register 0x003F 11 10 Base 0x904 URX 16 UART RX Register 0x0000 11 12 MOTOROLA MC68328 USER S MANUAL 12 9 97 3 11 For More Information On This Product Go to www freescale com ARCHITECTURE O gt D O Ss m e 4 i pu m Architecture Freescale Semiconductor Inc Table 3 3 Programmer s Memory Map Continued ADDRESS NAME WIDTH DESCRIPTION RESET VALUE HEX PAGE Base 0x906 UTX 16 UART TX Register 0x0000 11 13 Base 0x908 UMISC 16 UART Misc Register 0x0000 11 15 Base 0xA00 LSSA 32 LCD Screen Starting Address Register 0x00000000 8 15 Base 0xA05 LVPW 8 LCD Virtual Page Width Register OxFF 8 15 Base 0xA08 LXMAX 16 LCD Screen Width Register 0x03FF 8 16 Base 0xA0A LYMAX 16 LCD Screen Height Register 0x01FF 8 16 Base 0xA18 LCXP 16 LCD Cursor X Position Register 8 17 Base 0xA1A LCYP 16 LCD Cursor Y Position Register 8 17 Base 0xA1C LCWCH 16 LCD Cursor Width amp Height Register 0x0101 8 18 Base 0xA1F LBLKC 8 LCD Blink Control Register 7F 8 18 Base 0xA20 LPICF 8 LCD Panel er ion 0x00 8 19 Base 0xA21 LPOLCF 8 LCD P
75. L PDIRQEN PDIRQEDGE PEDIR PEDATA PESEL PEDIR PFDATA PFSEL PGDIR PGDATA PGSEL PJDIR PJDATA PJSEL PKDIR PKSEL Timer Registers TCTL1 TPRER1 TCMP1 TCR1 TCN1 TSTAT1 TCTL2 TPRER2 MOTOROLA equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ Freescale Semiconductor Inc M328BAS M328BAS M328BAS M32 8BAS M328BAS M32 8BAS M32 8BAS M328BAS M328BAS M328BAS M32 8BAS M328BAS M328BAS M32 8BAS M328BAS M328BAS M328BAS M32 8BAS M328BAS M328BAS M328BAS M328BAS M328BAS M32 8BAS M32 8BAS M328BAS M328BAS M328BAS M328BAS 328BAS M328BAS 328BAS 328BAS M328BAS M328BAS M328BAS 328BAS M328BAS M328BAS Applications and Design Examples E 433 ers Re egisters tion Reg a Reg ect Reg Port Registers 8 Direction Reg 449 Data Reg 44A Pullup Enable Reg E 44B Select Reg E 500 Control Reg E 502 Period Reg E 504 Width Reg E 506 Counter Timer 1 Registers E 600 Control Reg E 602 Prescalar Reg E 604 Compare Reg E 606 Capture Reg E 608 Counter E S60A Status Reg Timer 2 Registers E 60C Control Reg E S60E Prescalar Reg E 400 Directio
76. L 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Slave 13 3 1 SPI Slave Register This register controls the SPI operation and reports its status The lower byte is the input data received from an external source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPIS IRQ EN DATA OV SPIS IRQ EN POL RDY WR PHAS ROL EN DAIA ADDRESS SPISIRQ Slave SPI Interrupt Request This interrupt flag bit is asserted at the end of an 8 bit transfer The fer should be read before the completion of another 8 bit transfer This bit is c by writing a one to it It is a leve 6 IRQ 0 No interrupt posted 1 Interrupt posted IRQEN Slave SPI Interrupt Request Enable X This bit enables the SPIS_IRQ interrupt and is set 0 Interrupt disabled 1 Interrupt enabled ENPOL Enable Polarity This bit controls the polarity of the ignal and is initially set to 0 AV ta buffer contains updated data The DATARDY flag is the data is read a W c 3 ae ra uo ag Ju ai ce mE OVWR Overwrite This bit indicates that the data buffer was overwritten An interrupt is posted when an overwrite occurs The OVRWR flag is automatically cleared after the data is read O Data buffer is intact 1 Data buffer has been overwritten data stream is corrupted MOTOROLA MC68328 USER S MANUAL 11 10 97 13 3
77. L I O PORTS DUAL EC000 PULSE WIDTH 16 BIT STATIC MODULATOR TIMER CORE MODULE 8 16 BIT CHIP SELECT BUS INTERFACE LOGIC CLOCK SYNTHESIZER BUS PAND SIZING conoi e ARION MC68EC000 INTERNAL B REAL TIME CLOCK PCMCIA SUPPORT INTERRUPT CONTROLLER UART LCD WITH CONTROLLER INFRA RED SUPPORT PARALLEL 1 O PORTS Figure onBall Block Diagram 3 1 CORE The MC68ECO000 co ragonBall is an updated implementation of the M68000 32 bit microprocessor main features of the core are Low po e 32 bi us and 16 bit data bus 1 ata and address registers 56 powerful instruction types that support high level development languages 14 addressing modes and five main data types e Seven priority levels for interrupt control The core is completely code compatible with other members of the M68000 families which means it has access to a broad base of established real time kernels operating systems languages applications and development tools 3 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture 3 1 1 Core Programming Model The core has 32 bit registers and a 32 bit program counter see Figure 3 2 The first eight registers D7 DO are data regist
78. LUE HEX PAGE Base 0x439 PJDATA 8 Port J Data Register 0x00 7 16 Base 0x43B PJSEL 8 Port J Select Register 0x00 7 16 Base 0x440 PKDIR 8 Port K Direction Register 0x00 7 17 Base 0x441 PKDATA 8 Port K Data Register 0x00 7 17 Base 0x442 PKPUEN 8 Port K Pullup Enable Register 0x3F 7 17 Base 0x443 PKSEL 8 Port K Select Register 0x3F 7 17 Base 0x448 PMDIR 8 Port M Direction Register Ox 7 18 Base 0x449 PMDATA 8 Port M Data Register 7 18 Base 0x44A PMPUEN 8 Port M Pullup Enable Register OxFF 7 18 Base 0x44B PMSEL 8 Port M Select Register 02 7 18 Base 0x500 PWMC 16 PWM Control Register 0x0000 PWM Base 0x502 PWMP 16 PWM Period Register 0x0000 PWM Base 0x504 PWMW 16 0x0000 PWM Base 0x506 PWMCNT 16 0x0000 PWM Base 0x600 TCTL1 16 0x0000 10 4 Base 0x602 TPRER1 16 0x0000 10 5 Base 0x604 TCMP1 16 OxFFFF 10 6 Base 0x606 TCR1 16 0x0000 10 6 Base 0x608 TCN1 16 0x0000 10 7 Base 0x60A TSTAT1 Timer Unit 1 Status Register 0x0000 10 7 Base 0x60C TCTL2 1 er Unit 2 Control Register 0x0000 10 4 Base 0x60E TPREP 6 Timer Unit 2 Prescaler Register 0x0000 10 5 Base 0x610 Timer Unit 2 Compare Register OxFFFF 10 6 Base 0x612 16 Timer Unit 2 Capture Register 0x0000 10 6 Base 0x 16 Timer Unit 2 Counter Register 0x0000 10 7 Base 6 TSTA 16 Timer Unit 2 Status Register 0x0000 10 7 Base 0x61 WCSR 16 Watchdog Control and Status Register 0x0001 10 9 Base 0x61A WRR 16 Watchdog Compare Register OxFFFF 10 8 Base 0x61C WCN 16 Watchdog Counter Register 0x0000 10 8 Base 0x700 SPISR 16 SP
79. M Per es ANT a es ars RIC A CUDA v in this port As with other ports each pin can be individually cts or general purpose I O pin as needed There are only 6 pins ave BIT MAA A es ea ae FIELD DIRA DIRS DIR2 DIRI DIRO D7 D6 D5 D4 D3 D2 Di DO RESET 0x0000 ADDR OXFFFFF420 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PU1 PUO SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO a RESET 0x8080 ADDR OXFFFFF422 7 12 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports DIR Direction 0 7 These bits control the directions for the associated port pin When a bit is high the corresponding port pin is an output pin and when it is low the corresponding port pin is an input pin These bits reset to 0 and do not affect the pins while the SEL bits are low D Data 0 7 These bits control or report the data on the pins When the DIR bits are high D 7 0 control the data to the pins Data can be read from or written to any bit When the DIR bits are low D 7 0 report the signal level on the pins In this case writing to a read only bit does not affect the pin Notice that the actual value on the pin is reported when a pin is read At
80. N 410 20 0 008 H L M N 144 O 1 i DETAIL A oo DETAIL B SES r O DETAIL A aa gt gt BASE METAL lt D gt 73 N ROTATED 90 Y 144 PL 0 080 000 T L MO N 36 NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI lt A gt Y14 5M 1982 S zi 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 4 DATUMS L M AND N TO BE DETERMINED AT DATUM PLANE H 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE T 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION lt wt ALLOWABLEPROTRUSION IS 0 25 0 010 PER SIDE J DETAIL C DIMENSIONS A AND B DO NOT INCLUDE MOLD N MISMATCH AND ARE DETERMINED AT DATUM LINE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLEDAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0 35 0 014 2 D ES gt 2 is m Dn le 2 uU e zZ oz a 0 08 0 003 DETAIL B SEATING PLANE om MIN MAX MIN MAX 20 00 BSC 0 790 BSC A1 10 00 BSC 0 394 BSC B 20 008sC 0 790 BSC c2 1000 BE 0 394 BSC 0 055 0 063 0 05 0 005 ym Alo Re g
81. NE Be ae 20 00 BSC 0 790 BSC 10 00 BSC 0 394 BSC 20 00 BSC 0 790 BSC c2 10 00 BSC 0 394 BSC 40 Ti 0 063 Pass foo fo Ll C1 DETAIL C 100 BSC Tv _ _22 00BSC__ 00 B 0 4 Y 025REF_ 0 010 R 1 00 REF 0 039 R AA 0 09 0 16 0 004 0 006 pa po ppp para 070077 Lee Tie 132 112 137 Figure 18 2 MC68328 144 Lead Plastic Thin Quad Flat Pack Specs 18 2 C68 2 USERS M NU AL Pr MOTOROLA For More Information Put Go to www freescale com Freescale Semiconductor INC rechanical Specifications MOTOROLA C68328 USER S MAN L 1 89 98 18 3 For More Intormation On is Product Go to www freescale com Mechanical Specifications Freescale Semiconductor Inc 18 4 C68328 USER S MAN L 1 89 98 MOTOROLA For More Intormation On is Product Go to www freescale com
82. On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 6 INTERRUPT CONTROLLER The interrupt controller supports a variety of interrupts from internal and external sources This block prioritizes and encodes pending interrupts and generates interrupt vector numbers during the interrupt acknowledge cycle INTERRUPTS INTERRUPT PENDING REGISTER WY 117 INTERRUPT MASK REGISTER ENS N ATOR E 5 E gt ce ce wis EOS o VECT PRIORITY GENER ENCODER IPL 0 2 ure 6 1 rrupt Controller Block Diagram The interrupt c pports 23 edge and level sensitive interrupts There are seven interrupt levels L has the highest priority and level 1 has the lowest Interrupts can originat owing sources pheral interface SPI slave that needs service level 6 Timer 1 event level 6 TRQ6 external interrupt level 6 PENIRQ level 5 Serial peripheral interface SPI master that needs service level 4 Timer 2 event level 4 e UART event level 4 MOTOROLA MC68328 USER S MANUAL 12 9 97 6 1 For More Information On This Product Go to www freescale com Qz o4 Zm 33 Da oc D ra D Freescale Semiconductor Inc Interrupt Controller e Watchdog timer interrupt level 4 e Real time clock interrupt level 4 Keyboard interrupt level 4 PWM interrupt level 4 General purpose interrupt INT O 7 level 4 IRQ3 externa
83. PLL Note The PCDS bit requires an LCD controller off on sequence before any changes will occur 8 7 3 LCD Last Buffer Address Register The LCD last buffer address LLBAR register is used t igure the number of memory words required to fill one line on the LCD panel BIT 7 6 5 4 3 2 1 0 FIELD LBAR4 LBAR3 LBAR2 LBAR1 RW RW RW R W RW R W RESET ADDR Ox FF FFFA29 LBAR Last Buffer These bits repre white display and whit r a grayscale display For panning add one more count in black d two for gray display oc wi pa O o Z Q o a o a QO MOTOROLA MC68328 USER S MANUAL 12 9 97 8 23 For More Information On This Product Go to www freescale com r O o Q e zZ pr e Fr m a Freescale Semiconductor Inc LCD Controller 8 7 4 LCD Octet Terminal Count Register The LCD octet terminal count register LOTCR is used to confure the time interval from the end of the current line to the beginning of the next line on the LCD display LOTCR BIT 7 6 5 4 3 2 1 0 FIELD OTC8 OTC7 OTC6 OTC5 OTC4 OTC3 OTC2 OTC1 R W R W R W R W R W R W R W R W R W RESET Ox3F ADDR Ox FF FFFA2B OTC Octet Terminal Count 8 1 These bits control the time interval from the end of the current next line They allow the frame refresh rate to be finely a T greater than LLBAR by four for a bla
84. R La E a o mo SE aso ea o se gt 38 GPIO DELTA GPIO Change Status This bit indicates that a change has occurred on the GPIO pin If the GPIO interrupt is enabled this bit posts an interrupt You can write this bit to a 1 to post an immediate interrupt for debugging purposes This bit must be cleared by writing O to clear the GPIO interrupt 0 No GPIO interrupt posted 1 GPIO interrupt posted MOTOROLA MC68328 USER S MANUAL 12 9 97 11 11 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter GPIO GPIO Status Control If GPIO is configured as an input this bit indicates the current state of the GPIO pin If GPIO is configured as an output this bit controls the state of the pin 0 GPIO pin is low 1 GPIO pin is high GPIO DIR GPIO Direction This bit controls the direction of the GPIO pin When this bit is high the pin is an input When this bit is low GPIO is an output 0 GPIO is input 1 GPIO is output GPIO SRC GPIO Source This bit controls the source of the GPIO pin When high the s st x clock from the baud rate generator When low the source is the GPIO bit When GPIO DIR bit is 0 this bit has no function 0 GPIO driven by GPIO bit 1 GPIO driven by a bit clock from the b erator BAUD SRC Baud Source This bit controls the clock source to the b O Baud rate gen
85. Register 0x00 7 8 Base 0x40B PBSEL 8 Port B Select Reg 0x00 7 8 Base 0x410 PCDIR 8 0x00 7 9 Base 0x411 PCDATA 8 0x00 7 9 Base 0x413 PCSEL 8 0x00 7 9 Base 0x418 PDDIR 8 0x00 7 10 Base 0x419 PDDATA 8 0x00 7 10 Base 0x41A PDPUEN 8 up Enable Register OxFF 7 10 Base 0x41C PDPOL D Polarity Register 0x00 7 10 gt Base 0x41D ort D IRQ Enable Register 0x00 7 10 Base 0x41F Port D IRQ Edge Register 0x00 7 10 m Q Base 0x420 Port E Direction Register 0x00 7 12 E Base 0x421 Port E Data Register 0x00 7 12 Base 0x 8 Port E Pullup Enable Register 0x80 7 12 Base 8 Port E Select Register 0x80 7 12 Base 0x42 8 Port F Direction Register 0x00 7 13 Base 0x429 PFDATA 8 Port F Data Register 0x00 7 13 Base 0x42A PFPUEN 8 Port F Pullup Enable Register OxFF 7 13 Base 0x42B PFSEL 8 Port F Select Register OxFF 7 13 Base 0x430 PGDIR 8 Port G Direction Register 0x00 7 14 Base 0x431 PGDATA 8 Port G Data Register 0x00 7 14 Base 0x432 PGPUEN 8 Port G Pullup Enable Register OxFF 7 14 Base 0x433 PGSEL 8 Port G Select Register OxFF 7 14 Base 0x438 PJDIR 8 Port J Direction Register 0x00 7 16 3 10 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Table 3 3 Programmer s Memory Map Continued ADDRESS NAME WIDTH DESCRIPTION RESET VA
86. S Figure 18 1 MC68328 144 Lead Plastic Thin Quad Flat Pack Pin Assignment VOTERA For More R aT On this Product et Go to www freescale com Mechanical Specifications Freescale Semiconductor Inc CASE 918 02 144 TQFP 0 20 0 008 H L M N 6 0 20 0 008 H L M N 144 O Gl 1 DETAIL A B v DETAIL B ERa T iy lt D DETAIL A TES gt gt BASE META 73 ROTATED 90 4 Y 144 PL 0 08 0 003 T L M N 36 NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 4 DATUMS L M AND N TO BE DETERMINED AT DATUM PLANE H DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE c 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION eA lt a ALLOWABLEPROTRUSION IS 0 25 0 010 PER SIDE lt may y Y op Zs a crs DIMENSIONS A AND B DO NOT INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM LINE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION TTT ALLOWABLEDAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0 35 0 014 a 0 08 0 003 DETAIL B SEATING PLA
87. SFFF202 Al lea FFF200 AO WAIT move w A1 DO s hronize to rising CLK32 edge bpl w WAIT ait for CLK32 to go high bset 3 A0 isable the PLL stop 2000 stop fetching and wait for any IRQ The system waits After the IRQ r LL to restart after a wakeup IRQ struction flow continues from here e fort jump to housekeeping routine because an interrupt was asserted and was not disabled as a wake up event in the Interrupt Wake Up Enable Register An interrupt can be a wake up event and still be masked from causing a CPU interrupt See Section 2 3 3 5 15 3 POWER CONTROL MODULE OVERVIEW The power control module improves power efficiency as it allocates power clocks to the CPU core and other modules in the MC68328 processor under software control Clocks can be enabled in bursts While executing tasks that require significant CPU resources the clock can be enabled for extended periods of time While the CPU is relatively idle the clock can be disabled or bursted with a low duty cycle When a wakeup interrupt occurs the clock is immediately enabled allowing the CPU to service the request The DMA controller is not affected by the power controller It has full access to the bus while the CPU is idle keeping MOTOROLA MC68328 USER S MANUAL 11 10 97 15 5 For More Information On This Product Go to www freescale com l 230 OF 2 QQ Ser S ou a uy O na lt A IZ aq 2u 2x o gt Zm 30 m DA om Q
88. T ADDR 8 3 2 LCD Virtual Page Wi r The LCD virtual page width LVPW register specifies the virtual page width of the LCD panel in terms of byte co PW is a 9 bit value However VPO is a fixed value of zero that aligns this registe page width in pixels divi ich is 16 for black and white displays and 8 for grayscale displays LVPW BIT 7 6 5 4 3 2 1 0 FIELD P8 VP7 VP6 VP5 VP4 VP3 VP2 VPI R W R W R W R W R W R W R W R W RESET OxFF ADDR Ox FF FFFA0S MOTOROLA MC68328 USER S MANUAL 12 9 97 8 15 For More Information On This Product Go to www freescale com oc wi par O Z Q o a o a QO rc O o Q e zZ pu as e md m a Freescale Semiconductor Inc LCD Controller 8 4 SCREEN FORMAT REGISTERS 8 4 1 LCD Screen Width Register Th LCD screen width register LXMAX specifies the width of the LCD panel in pixels On a line pixels are numbered 0 to LXMAX for a screen width of LXMAX 1 pixels LXMAX 1 must be a multiple of 16 LXMAX AA A Mara a E FIELD XM9 XM8 XM7 XM6 XM5 XM4 X xme XM1 XMO RW RW R W RW RW RW RW R W RW RW RESET 0x03FF ADDR Ox FF FFFA08 8 4 2 LCD Screen Height Register The LCD screen height register LYMAX specifies t eight of the LCD panel in pixels or lines The lines are numbered from 0 to LYMAX MAX 1 lines wh
89. T2 interrupt 1 INT2 interrupt is pending INT3 External INT3 Interrupt 0 No INT3 interrupt 1 INTS interrupt is pending INT4 External INT4 Interrupt O No INT4 interrupt 1 INT4 interrupt is pending INT5 External INT5 Interrupt O No INT5 interrupt 1 INT5 interrupt is pending INT6 External INT6 Interrupt 0 No INT6 interrupt 1 INT6 interrupt is pending INT7 External INT7 Interrupt 0 No INT7 interrupt 1 INT7 interrupt is pending IRQ1 Interrupt Request Level 1 vice has requested an interrupt on level 1 If rrupt you must clear the source of the interrupt ed interrupt you must clear the interrupt by writing set to be a level sensitive interrupt you must clear the source of the interrupt If IRQ2 signal is set to be an edge triggered interrupt you must clear the interrupt by writing a 1 to this bit writing a O has no effect O No level 2 interrupt is pending 1 Level 2 interrupt is pending IRQ3 Interrupt Request Level 3 When set this bit indicates that an external device has requested an interrupt on level 3 If IRQ3 signal is set to be a level sensitive interrupt you must clear the source of the interrupt 6 16 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller If IRQ3 signal is set to be an edge triggered interrupt you must clear the
90. TL2 to configure the overall operation of the timers TCTL1 AND TCTL2 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FRR CAPTUREEDGE OM IRQEN CLKSOURCE TEN R W RW RW RW RW RW RW RESET 0x0000 ADDR Ox FF FFF600 TIMER 1 AND Ox FF FFF60C TIME FRR Free Run Restart This bit controls the timer operation when a reference curs In the free run mode r the timer counter continues normal counting from its cur In the restart mode the counter is reset to 0 then resumes counting 0 Restart mode reset counter to 0 and resume ting 1 Free run mode continue t o run CAPTURE EDGE This field control the operation of the unction 00 Disable interrupt on capture event 01 and generate interrupt on capture 10 Nx and generate interrupt on capture 11 i r falling edges of TINx and generate interrupt on capture OM Output This bit contro mode of the timer after a reference compare event a gt low pulse for one SYSCLK period oggle output IRQEN Reference Event Interrupt Enable This bit enables the timer interrupt when a reference event occurs These maskable timer interrupts are a level 6 interrupt for timer 1 or a level 4 interrupt for timer 2 0 Disable interrupt on reference event 1 Enable interrupt on reference event 10 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to
91. TX empty interrupt enabled MOTOROLA MC68328 USER S MANUAL 12 9 97 11 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter TX HALF EN Transmitter Half Enable When this bit is high it enables an interrupt when the transmit FIFO is less than half full When it is low the TX half interrupt is disabled This bit resets to 0 0 TX half interrupt disabled 1 TX half interrupt enabled TX AVAIL EN Transmitter Available Enable When this bit is high it enables an interrupt when the transmitter has a slot available in the FIFO When it is low this interrupt is disabled This bit resets to 0 S gt 0 TX avail interrupt disabled e 1 TX avail interrupt enabled lavn 11 10 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter 11 4 2 UART Baud Control Register The UART baud control UBAUD register controls the operation of the baud rate generator and the GPIO pin lt resets to Ox003F UBAUD BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD AAA GRO BAUD DIVIDE PRESCALER RW RW aw RW RW RW RW RW RW RESET 0x003F ADDR Ox FF FFF902 9 Table 11 1 Baud Rate Divider Prescaler ues BAUD RATE DIVIDE
92. Universal Asynchronous Receiver Transmitter GPIO DELTA EN General Purpose l O Delta Enable This bit enables an interrupt when the GPIO pin while configured as an input changes state The current state of the GPIO pin is read in the UART baud control register 0 GPIO interrupt disabled 1 GPIO interrupt enabled CTS DELTA EN CTS Delta Enable When this bit is high it enables an interrupt when the CTS pin changes state When this bit is low this interrupt is disabled The current status of the CTS pin is read in the UART transmitter register 0 CTS interrupt disabled 1 CTS interrupt enabled RX FULL EN Receiver Full Enable When this bit is high it enables an interrupt when the receiver FIFO is full This bit resets to 0 ON receiver FIFO is more than half full 0 RX full interrupt disabled 1 RX full interrupt enabled RX HALF EN Receiver Half Enable When this bit is high it enables an interru This bit resets to 0 0 RX half interrupt disabled 1 RX half interrupt bled When this bit is high the FIFO When i O interrupt when the receiver has at least one data byte in errupt is disabled This bit resets to 0 RX i led e t enabled Transmitter Empty Enable When this bitis high it enables an interrupt when the transmitter FIFO is empty and needs data When it is low this interrupt is disabled This bit resets to 0 0 TX empty interrupt disabled 1
93. W RW RW RW RW RW RW RW RESET 0x0000 ADDR Ox FF FFFA1A CYP Cursor Y Position 8 0 These bits represent the cursor s vertical starting position Y in pixel count from O to LYMAX ao wi par O o Z Q o a o a QO MOTOROLA MC68328 USER S MANUAL 12 9 97 8 17 For More Information On This Product Go to www freescale com E o Q fo z 3 Es e Le ES m D Freescale Semiconductor Inc LCD Controller 8 5 3 LCD Cursor Width and Height Register The LCD cursor width and height LCWCH register is used to configure the width and height of the cursor LCWCH Bm Bl 14 130 5128 511 wl oOo Bl vr cn 4 0 1300 00050 0 O FIELD CW4 CW3 CW2 CW1 CWO CH4 CH3 CH2 CH1 CHO R W R W R W RW RW RW RW R W R W RW RW RW RW RESET 0x0101 ADDR Ox FF FFFA1C CW Cursor Width 0 4 These bits specify the width of the hardware cursor in pixel 1 to 31 CH Cursor Height 0 4 These bits specify the height of the hardware cursor in p om 1 to 31 7 Note The cursor is disabled if the C i tto zero 8 5 4 LCD Blink Control Re The LCD blink control LBLKC registe cursor NZ LBLKC L 6 to control the blinking characteristic of the BIT 7 5 4 3 2 1 0 FIELD BK BOS BD5 BD4 BD3 BD2 BD1 BDO RW R RW RW RW RW RW R
94. W RESET 0x7F ADDR Ox FF FFFA1F BKEN Blink Enable This bit indicates when the link enable cursor stays on instead of blinking This bit defaults to zero 1 Blink enable O Blink disable 8 18 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller BD Blink Divisor 0 6 These bits indicate when the cursor will toggle once per specified number of internal frame pulses plus one The half period can be as long as two seconds 8 6 LCD PANEL INTERFACE REGISTERS 8 6 1 LCD Panel Interface Configuration Register The LCD panel interface configuration LPICF register is used to configure the bus width of the LCD bus interface You can also use it to enable a grayscale display LPICF pla BIT 7 6 5 4 3 2 1 0 FIELD S BSIZO GS R W RW R W R W RESET 0x00 ADDR Ox FF FFF PBSIZ Panel Bus Width 0 1 N This bit indicates the size of the LCD pan 00 1 bit 01 2 bit Abit N 11 Unused Ny GS Grayscale This bit is the gra le mode bit If this bit is set it enables 4 grayscale level 2 bits per is 0 which selects binary pixel non grayscale operation o ote The GS bit requires an LCD controller off on sequence before any changes will occur 3 E e S a 3 MOTOROLA MC68328 USER S MANUAL 12 9 97 8 19 For More Information On This Prod
95. Y e MAPPING a E X 8 Y 1 RATA 6 11 05 41 4 41 lt 3 Y1 062 41 X1 Y 1 Q a y 9 SYSTEM ROM RAM 00 BYTE ORIENTED FOR CLARITY Figure 8 6 Mapping Memory Data on the Screen MOTOROLA MC68328 USER S MANUAL 12 9 97 8 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller DPRAM_BASE IMMR 8 OxFFFF0000 0x2000 ERAM 01 BD DATA uCODE DPRAM_BASE IMMR amp OXFFFF0000 0x2200 ERAM 10 BD DATA CODE DPRAM_BASE IMMR amp OxFFFF0000 0x2400 ERAM 11 BD DATA uCODE DPRAM_BASE FFF0000 0x2800 BD DATA DPRAM_BASE IMMR amp 0xFFFF0000 0x2E00 BD DATA CODE DPRAM_BASE IMMR amp 0xFFFF0000 0x3C00 PARAMETER RAM NOTE The shaded area indicates the area that is implemented on the silicon Figure 8 7 Grayscale Generation rc O o Q e zZ pu as e md m a 8 12 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller 8 2 7 Grayscale Generation The LCD controller is configured to only drive non split monochrome LCD panels It cannot handle color STN or TFT panels However grayscale generation can be selected by setting the GS bit in the LCD panel interface configuration LPICF register In grayscale mode the number of data words for displaying the gray levels increas
96. a og OF oO OM A elelel ele START BIT BIT 0 PARITY BIT Az Asc A Character with Odd Parity The polarity o smitted pulses and the expected receive pulses can be inverted so that a dir nection can be made to external infrared transceiver modules that use active low pu 3 illustrated a character in infra red mode he EN ee 218 Clelgl E m am 0 0000 MAGS gq E E 2 wn T V a Figure 11 3 IrDA ASCII A Character with Odd Parity MOTOROLA MC68328 USER S MANUAL 12 9 97 11 3 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter The UART module is easy to use from both a hardware and a software perspective Five working registers provide all of the status and control functions and they are optimized for a 16 bit bus For example all status bits associated with the received data are available along with the data byte in a single 16 bit read All register bits are readable and most are read write The modem control signals are flexible CTS is an input that can provide hardware flow control to the transmitter or it can serve as a general purpose input A maskable interrupt is posted on each transition of this signal RTS is an output from the receiver that indicates that the receiver has space in the FIFO for data This bit can be configured as a general purpose output A GPIO pin is provided that can bring an external bit clo
97. ad of the two data bus halves in an 8 bit system The internal data bus is ide All internal registers can be read or written in one zero wait state cycle registers enable 16 and 8 bit data bus widths for each of the 16 chi tranges You can initi i i 0 or 1 on the BBUSW width to be used in any given system All external a at do not match one of the chip select address ranges are assumed to be performed for a 16 bit transfer lt can also be a cessed every other byte The boot chip select is initialized from res response to any address except the on chip register space OxXXFFFOOO to 0 F This ensures that a chip select to the boot ROM or EPROM will fetch t and execute the initialization code which should set up the chip select ran A logic 0 on the BBUSW pi makes it 16 bits wide A boot ROM device are initialized to be nonvali set makes t oot device s data bus 8 bits wide and a logic 1 us port size for CSAO and the data width of the e state of the BBUSW pin The other chip selects are If the group address and chip select registers are programmed to overlap the CSx signals will overlap too Unused chip selects must be programmed to 0 wait states and 16 bits wide Map them to dummy space if necessary When you are configuring the chip select signals the core can be set to write to a read only location This causes the CS and DTACK signals to not be asserted and the BERR signal to be asserted if a bus error timer
98. ad from the Fl 0 Character is not a break character 1 Character is a break character PARITY ERROR Parity Error When high this read only bit indicates that the curr error thus indicating the possibility of corrupted data read from the FIFO While parity is disabled t as detected with a parity is updated for each character RX DATA Receive Data the DATA READY bit is 0 While in all bits are active 11 4 4 UART Transmi Register e controls transmitter operation contains the data to be transmitted and repo s of the operation UTX AAA A aes eae OAMI moar R W R R R W RW RW RW RW Ww RESET 0x0000 ADDR Ox FF FFF906 FIFO EMPTY FIFO Empty This read only bit indicates that the transmit FIFO is empty 0 Transmitter FIFO is not empty 1 Transmitter FIFO empty 11 14 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter FIFO HALF FIFO Half This read only bit indicates that the transmit FIFO is less than half full 0 Transmitter FIFO more than half full 1 Transmitter FIFO less than half full TX AVAIL Transmit FIFO Available This bit indicates that the transmit FIFO has at least one slot available for data 0 Transmitter does not need data 1 Transmitter needs data SEND BREAK Se
99. and an interrupt is generated to the processor 1 A 1Hz interrupt occurs 0 No 1Hz interrupt occurs DAY FLAG Day Flag When the 24 hour interrupt is enabled this bit is set for every 24 hour clock increment at midnight and an interrupt is generated to the processor 1 A 24 hour rollover interrupt occurs 0 No 24 hour rollover interrupt occurs ALARM FLAG Alarm Flag When an alarm interrupt is enabled this bit is set on a comp real time clock current time and the alarm register s value The hours If a single alarm is required you must clear the in interrupt in the RTC interrupt enable register m will reoccur every 24 isable the alarm 1 An alarm interrupt occurs O No alarm interrupt occurs MIN FLAG Minute Flag When a minute interrupt is enabled generated to the processor 1 A minute tick occurs 0 No minute tick on every minute tick and an interrupt is abled this bit is set when the stopwatch minute countdown d an interrupt is posted to the processor 9 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Real Time Clock 9 3 5 RTC Interrupt Enable Register The real time clock interrupt enable register IENR allows you to individually enable different real time clock interrupts The real time clock provides five interrupts a 1 second interrupt 1 minute interrupt 1 day at
100. and height respectively By changing the LSSA register a screen sized window can be vertically or horizontally scrolled or panned anywhere inside the virtual page boundaries The software must position the LSSA properly so that the scanning logic s system memory pointer SMP does not stretch beyond VPW nor VPH You should use the VPH parameter for boundary checks but there is no LVPW register MOTOROLA MC68328 USER S MANUAL 12 9 97 8 9 For More Information On This Product Go to www freescale com ao wi par O o Z Q o o a O E o Q e z 3 Es e ll m D Freescale Semiconductor Inc LCD Controller 8 2 5 Cursor Control Logic To define the position of the hardware cursor the LCD controller maintains a vertical line counter YCNT to keep track of the pixel s current vertical position YCNT in conjunction with the horizontal pixel counter XCNT specifies the screen position of the current pixel data that is being processed When the pixel falls within a window specified by the cursor reference position CXP 10 bit register CYP 9 bit register cursor width CW 5 bit counter and cursor height CH 5 bit counter the original pixel bits are passed transparently replaced with a full black or complemented for reversed video The cursor can be static or blinking which is determined in the LCD blink control register LBLKC If you choose a static cursor reversed video is opti
101. are compared aga group base address register In this case the group h and the rest of the bits are clear the group is s i programmed in the group base address register p You can decode each chip select by comparing the lower address lines with the contents of the chip select option registers If the me for a group of devices is small you can program the groups to a common s and use the chip select option registers to decode the areas for each chip select 0 For a match to occur mo line must match the corresponding bit in the GRPBASEx regist 1 The corresponding address line compares true don t care r size For example if lue programmed in the space If the GMA20 bit is set 1 are the same as the value des 2M of space for the group Bits O 3 Reserved MOTOROLA MC68328 USER S MANUAL 12 9 97 5 5 For More Information On This Product Go to www freescale com e o e l E o uu lu og 2 I o O O o ie on m m m O 2 je Q o Freescale Semiconductor Inc Chip Select Logic 5 2 3 Chip Select Option Registers There are four 32 bit chip select option registers CSA0O 3 and CSBO 3 in each chip select group one for each chip select signal Chip selects in group A and B decode address lines A 23 16 for a minimum 64K space Chip selects in group C and D decode address lines A 23 12 for a minimum 4K space When a group address match and a chip select option ad
102. at PIX_CLK_SOURCE is derived fro PLL control register 2 Last buffer address register LBAR LBAR 240 16 15 LBAR 240 8 30 for grayscale 3 Calculate the value of the OTCR register This v ntrols the time required between two line pulses Select a value s gt LBAR as required OTCR LBAR 4 19 OTCR LBAR 8 38 for graysca Increasing the value in ED LP period 4 Calculate the frequency Frequency 16 58MHz AX x OCTET x 16 16 58MHz 3 x 160 x 38 x 16 for grayscale 5 Zz If OCTET 31 then frequ 69Hz OCTET is the OTCR register value oF mo ge 25 ma 4 x DO ETA ae m aS 16 16 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 17 ELECTRICAL CHARACTERISTICS wo e E Qn am z ToO Ex ga w no lt add info about data strobes gt This section provides information on the maximum ratings for the MC68328 processor 17 1 MAXIMUM RATINGS Supply Voltage Vcc 0 3t07 0 v vw oases wwf Sr Maximum Operating Temperature TL to A A EA T pe o Storage Temperature EN 55 to 150 17 2 POWER CONSUMPTIC NI o lt BE 3 3 V TYPICAL MAX Operating 6M 15 30 mA Stand 10 20 uA 17 3 CTRICAL SPECIFICATION DEFINITIONS The AC specifications presented consist of output delays input setup and hold times and sig
103. aud Control Reg 22 UARTRX equ M328BASE 904 Rx Reg ae UARTTX equ M328BASE 906 Tx Reg xo UARTMISC equ M328BASE 908 Misc Reg 56 ms LCDC Registers Yo LSSA equ M328BASE S A00 Screen Sta rR LVPW equ M328BASE A05 Virtual i LXMAX equ M328BASE A08 Screen W LYMAX equ M328BASE S ADA LCXP equ M328BASE A18 LCYP equ M328BASE SAI1A LCWCH equ M328BASE SAI1C Height Reg LBLKC equ ol Reg LPICF equ nterface Config Reg LPOLCF equ rity Config Reg LACDRC equ M Rate Control Reg LPXCD equ el Clock Divider Reg LCKCON equ locking Control Reg LLBAR Last Buffer Addr Reg LOTCR Octet Terminal Count Reg LPOSR Panning Offset Reg Frame Rate Control Mod Reg Gray Palette Mapping Reg L Interrupt Control Reg i RTC M328BASE B00 Hrs Mins Secs Reg RTCALMO qu M328BASE B04 Alarm Register 0 RICALMIR equ M328BASE B08 Alarm Register 1 RICCTL equ M328BASE SBOC Control Reg RTCISR equ M328BASE BOE Interrupt Status Reg RTCIENR equ M328BASE B10 Interrupt Enable Reg RSTPWCH equ M328BASE B12 Stopwatch Minutes Reset_start move w 2700 sr mask off all interrupts J FFER He He He Ae e k Fek Fe He Ae RE ER e H Fe e Fe He ERK EKER ERK Fe Ae He He KEK EKER EKER KERR ERK EKER ERK RK RARA i Initialize I O according to user s configuration 7 16 8 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicondu
104. ble registers a select register direction register pull up register and data register You can enable the pull up resistor of a particular pin by setting the corresponding bit in the pull up register Pull up resistor can be individually enabled for each port pin whether it is configured as a general I O port or a special purpose port Figure 7 2 illustrates the internal logic of a pull up port Pa y DATA TO MODULE DATA FROM MODULE MPU BUS OUTPUT ENABLE FROM MODULE MOTOROLA MC68328 USER S MANUAL 12 9 97 7 3 For More Information On This Product Go to www freescale com N E a Oo a pan Ww par a oc lt a v gt po gt a rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports 7 3 INTERRUPT PORT The interrupt port port D is a basic port and a pull up port except it has additional interrupt capabilities Figure 7 3 illustrates the internal logic of the interrupt port Port D does not share its port pins with o as a general purpose l O port interrupt g six configurable registers a directi register INT enable register an peripheral modules It is intended to be used ing port or keyboard input port Port D has r data register pull up register polarity The interrupt port generate ine inte the interrupts These inte i nals t signals The individual port pins generate eight of known as INT 0 7 Each interrupt signal either can te
105. c t any time The VCO frequency is unaffected by changes CLKEN This bit enabl LKO pin while high DISPLL Di This bit while high disables the PLL The system clock is shut down and the MC68328 processor assumes its lowest power state Only the 32 kHz clock runs Refer to Section 3 2 5 for a description of the preferred method for PLL shutdown Once the PLL is disabled only a wake up interrupt or reset can re enable it 1 PLL disabled O PLL enabled 15 2 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Phase Locked Loop and Power Control 15 1 2 Frequency Select Register This register illustrated in Figure 3 3 controls the two dividers of the dual modulus counter One additional bit assists the software to protectthe PLL from accidental writes that change the frequency Another bit prepares for the VCO frequency change While this register can be accessed as bytes it should always be written as a 16 bit word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLK32 PROT UNUSED Qc PC Address FF FFF202 Reset Value 0123 CLK32 Clock 32 This bit indicates the current status of the CLK32 signal and synch e software to the 32kHz reference clock when the VCO frequency is to be ch d or the PLL is to be disabled Refer to Section Section 15 2 PLL Operation for d PROT Pr
106. cale Semiconductor Inc Chip Select Logic Bits 7 4 Reserved These bits are reserved and should be set to 0 RO Read Only This bit configures the memory space selected by this chip select as read only Otherwise read or write accesses are allowed However writes to read only space cause a write protection violation to occur as described in Section 4 1 1 System Control Register 0 Read write 1 Read only WAIT Wait State Selection This field determines the number of wait states that are added befo internal DTACK signal is returned for the chip select 000 Zero wait states 001 One wait state 010 Two wait states 011 Three wait states 100 Four wait states 101 Five wait states 110 Six wait states 111 External DTACK CSC AND CSD DN BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD AC23 AC22 AC21 20 19 A aci7 AC16 AC15 AC14 AC13 AC12 RESERVED BUSW R W RW RW Ri R W RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD AM23 22 AM2O AMI AM18 AM17 AM16 AM15 AM14 AM13 AM12 RO WAIT R W RW RW RW RW RW RW RW RW RW RW RW RAV RESET 0x00010006 ADDR Ox FF FFF130 134 138 13C 140 144 148 14C AC23 AC12 Address Compare 23 12 for Groups C and D This field together with the AMx fi
107. center of each bit period When this bit is high the receiver is in 1x mode where it samples the datastream on each rising edge of the bit clock This bit resets to 0 0 ol 4 16x clock mode 1x clock mode PAR EN Parity Enable This bit controls the parity generator in the transmitter ts cker in the receiver A a When this bit is high they are enabled and when it is low disabled 0 Parity disabled 1 Parity enabled ODD EVEN Odd or Even Parity Selectio This bit controls the sense of the p en and checker When this bit is high odd parity is generated on the trans r cted on the receiver When it is low even parity is generated and expected Thi as no function if PARITY EN is low O Even parity 1 Odd parity f stop bits transmitted after a character When this bit is high when it is low one stop bit is sent This bit has no effect on the receiver ects one or more stop bits STOP bit transmitted STOP bits transmitted 8 7 Character Word Length This bit controls the character length When this bit is high the transmitter and receiver are in 8 bit mode When it is low they are in 7 bit mode The transmitter then ignores B7 and the receiver sets B7 to 0 0 7 transmit and receive bits per character 1 8 transmit and receive bits per character 11 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
108. ck and white display to the beginning of the egister value must be for a grayscale display 8 7 5 LCD Panning Offset Register Starting from the left of the LCD screen ing offset register LPOSR is used to configure the bits in memory that will b LPOSR LN BIT 7 6 5 3 2 1 0 FIELD BOS POS2 POS1 POSO RW R W R W R W R W RESET 0x00 ADDR Ox FF FFFA2D BOS set This bit i d in black and white mode in conjunction with the POS bits BOS must be set to zero for grayscale data O Start from the first byte when retrieving binary pixel data for the display 1 Active display will start from the second byte Note The cursor reference position must be adjusted separately from software when this register has been modified 8 24 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller POS Pixel Offset Code 0 2 These bits specify which of the eight pixels in the first or second GS 0 BOS 1 only octet retrieved from the line buffer is the first to be displayed on the screen 000 implies that pixel 7 the first shifted out will be the first to be displayed on every horizontal line in the current frame 8 8 GRAYSCALE CONTROL REGISTERS 8 8 1 LCD Frame Rate Modulation Control Register The LCD frame rate modulation control LFRCM register contains default values that will gi
109. ck into the module It can also serve as a general purpose input with a maskable interrupt posted on each transition It can be configured as an output that provides a bit a signal under software control The UART module consists of a transmitter a reciever a generator and an MPU interface 11 3 1 Transmitter transmits it serially While the FIFO is empty the transmitter outputs continuous idle 1 in NRZ mode and 0 in infra red mode When a character is availabl i n the START STOP and PARITY if enabled bits are added to the c s serially shifted at the selected bit rate The transmitter posts a maskabl n it needs more data from the CPU Three interrupts are available If you want t vantage of the 8 byte FIFO the FIFO empty interrupt should be enabled i t service routine the FIFO should be interrogated after each byte is loaded data will be loaded into the FIFO r FIFO has completely empti e a system that has a large interrupt service s case the transmitter generates an interrupt when aracter continuous 0s Your software must know the baud rate The bit must be asserted for a sufficient amount of time to generate a valid break can generate parity errors for debugging purposes The transmitter operates ock provided by the baud rate generator character Yo from the 1x c While the infra red interface is enabled the transmitter produces a pulse that is 3 46 of a bit time for each 0 bit that is sent
110. cked loop is enabled creating the high speed from a low frequency reference EXTAL may be used with XTAL to con i oscillator and clock generator If an external clock in a crystal is used the clock source should be connected to EXTAL and X ected The internal PLL generates the system clock at 16 58 MHz fr e z or 38 4 kHz source When an external clock is used it must provide a CMOS level at this input frequency While PCO MOCLK is high the PLL is disa he system clock must be connected to the EXTAL pin If the real time clock 2 768 kHz or 38 4 kHz must be driven into PG7 RTCO XTAL CRYSTAL OUTP This output connects t is used XTAL shoul ator output to an external crystal If an external clock unconnected CLKO CLO This output c erived from the on chip clock oscillator and is internally connect ck output of the internal PLL This signal is provided for external refere output can be disabled to reduce power consumption PCO MO Clock Mode Select Port C I O While this pin is high the MC68328 processor is in the external clock mode and the on chip PLL is disabled The system clock must be driven into the EXTAL pin While this pin is low itenables the PLL Either a 32 768 kHz or 38 4 kHz clock can be driven in to the EXTAL pin or a crystal can be connected between EXTAL and XTAL to create an oscillator PCO MOCLK can be programmed as a general purpose I O while the internal PLL is enabled 2 3 MC68328 USER S MANUAL 11
111. conductor Inc Architecture 3 1 2 Data and Address Mode Types The core supports five types of data and six main types of address modes as described in the following tables DATA TYPES ADDRESS MODE TYPES Bits Register direct Binary coded decimal digits Register indirect Bytes Absolute Words Program counter relative Long words Immediate Implied Table 3 1 Address Mo ADDRESS MODE Register direct address Data register direct Dn Address register direct An Absolute data address Absolute short xxx W Absolute long xxx L Program counter rela Relative wi d46 PC Relative da PC Xn 7 An gt register indirect An 3 nt register indirect An 3 indirect with offset d4 An 8 d register indirect with offset dg An Xn Cc a iate data address Immediate XXX Quick immediate 1 8 plied address Implied register SR USP SP PC NOTE Dn Data Register An Address Register Xn Address or Data Register Used as Index Register SR Status Register PC Program Counter SP Stack Pointer USP User Stack Pointer lt gt Effective Address dg 8 Bit Offset Displacement dig 16 Bit Offset Displacement xxx Immediate Data 3 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture 3 1 3 Instruction Set The ECO000 core instruction set supports hig
112. ctor 104 Level 2 Interrupt Autovector 112 Level upt Autov 116 e Autovector bd 120 MT errupt Autovector 124 Le errupt Autovector 128 RAP Instruction Vectors 188 192 Unassigned Reserved 30 3F 48 63 User Interrupt Vectors 5 o EATA 10 17 16 23 EAA m a a INTERRUPT CONTROLLER Note The DragonBall does not provide autovector interrupts At system start up you need to program the user interrupt vector so that the processor can handle interrupts properly MOTOROLA MC68328 USER S MANUAL 12 9 97 6 3 For More Information On This Product Go to www freescale com Qz o4 Zm 33 Da oc D E ra D Freescale Semiconductor Inc Interrupt Controller 6 2 RESET The reset exception corresponds to the highest exception level A reset exception is processed for system initialization and to recover from a catastrophic failure Any processing that is in progress at the time of the reset is aborted and cannot be recovered Neither the program counter nor the status register is saved The processor is forced into the supervisor state The interrupt priority mask is set at level 7 The address in the first 2 words of the reset exception vector is fetched by the processor as the initial SSP Supervisor Stack Pointer and the address in the next two words of the reset exception vector is fetched as the initial program counter At start up or reset the default chip select CSAO is asserted and
113. ctor Inc Applications and Design Examples OOOO ICICI ROO ROO I ICICI ROO ROO OOOO OOOO II I RR RR OOOO ICI ORIO ICICI ROO ROO ROO OOOO ROR I I I RR RR LCD Temp init for screen protection i j FE He e He He He ve He e He de He Fe He ER Fe e e He He Fe He ERK EKER ER Fe He ERK RK e he Ae e He He Ae e e e He e e ERK EKER ERERERER EK move l 00410000 LSSA frame starting address move b 14 LVPW virtual width move w 319 LXMAX xmax 16 move w 199 LYMAX 7ymax 16 move b 14 LLBAR LBAR move b 1b LOTCR RPTC move b 2 LPXCD pixel clock 1 3 sysclk move b 504 LPICF 74 bit LCD data no grey D an move b e0 LCKCON enable lcdc 16 words per gu 28 ox An move b 1c SCR enable bus error bit 3z clr 1 do ag elm dl ow les d2 clr a3 cir d4 E alr d5 clr l d clr d7 move 1 40010F09 CSAO move l 50010F09 CSA1 move l 60010F09 CSA2 move l 70010F09 CSA3 move w S000F GRPMASKA UPA MASK init move w 0000 GRPBA A BASE init rt add 0x0 Size 8MB SRAMO 0x00000000 0x003FFFFF CSBO 0x0 0x000FFFFF CSB1 0x00100000 0x001FFFFF OF00 CSB2 CSB2 0x00200000 0x002FFFFF OF00 CSB3 CSB3 0x00300000 0x003FFFFF 0030 GRPMASKB Group Base 0x00000000 Group Mask 4MB 0001 GRPBASEB SRAMO 0x00000000 0x003FFFFF Enable Valid Bit after setting up registers move l f 0010007 CSD3 CSD3 PCMCIA 4MB 6 w s move w 0070 GRPMASKD Group Base 0x00
114. d Modules LY Maxim Four Grayscale Levels AU Syst Be Used as Display Memory e Clock d 24 Hour Time 1 Programmable Alarm Pulse Width Modulation Output for Sound Generation J Programmable Frame Rate LY 16 Bit Programmable 1 Motor Control Support Two Serial Peripheral Interface Ports MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction UU External POCSAG Decoder Slave Support A Digitizer For A D Input or FLEX Pager Master Support IEEE 1149 1 Boundary Scan Test Access Port JTAG Operation From DC To 16 67MHz Processor Clock Operating Voltage of 3 3V 0 3V e Compact 144 Lead Thin Quad Flat Pack TQFP Packaging z S E o gt a e ia E MOTOROLA MC68328 USER S MANUAL 11 6 97 1 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 2 SIGNALS This section contains a description of the MC68328 DragonBall microprocessor signals as memory mapped registers of the device are invisible on the e made by the core to internal or external memory mappe atio external bus SIGNAL DESCRIPTIONS Ay MOTOROLA MC68328 USER S MANUAL 11 6 97 2 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signals 2 1 SIGNAL DESCRIPTIONS The DragonBall signals are grouped as shown in Table 2
115. default at reset Q1 interrupt from waking up the processor interrupt to wake up the processor default at reset 0 Disallow IRQ2 interrupt from waking up the processor 1 Enable IRQ2 interrupt to wake up the processor default at reset IRQ3 Wake up IRQ3 Interrupt 0 Disallow IRQ3 interrupt from waking up the processor 1 Enable IRQ3 interrupt to wake up the processor default at reset MOTOROLA MC68328 USER S MANUAL 12 9 97 6 13 For More Information On This Product Go to www freescale com Qz o4 Zm 33 Da oc D ra D Freescale Semiconductor Inc Interrupt Controller IRQ6 Wake up IRQ6 Interrupt 0 Disallow IRQ6 interrupt from waking up the processor 1 Enable IRQ6 interrupt to wake up the processor default at reset PEN Wake up Pen Interrupt 0 Disallow pen down interrupt from waking up the processor 1 Enable pen down interrupt to wake up the processor default at reset SPIS Wake up Serial Peripheral Interface SPI Slave Interrupt 0 Disallow SPI slave interrupt from waking up the processor 1 Enable SPI slave interrupt to wake up the processor default at reset TMR1 Wake up Timer 1 Interrupt 0 Disallow timer 1 interrupt from waking up the processo 1 Enable timer 1 interrupt to wake up the processor d fault eset IRQ7 Wake up IRQ7 Interrupt 0 Disallow IRQ7 interrupt from waking up th 1 Enable IRQ7 interrupt to wake up the proc ro
116. ding port pin is an output pin and when it is low the corresponding port pin is an input pin These bits reset to O and have no effect on the pins while the SEL bits are low D Data 0 7 These bits control or report the data on the pins when the corresponding SEL bits are high If the DIR bits are high pins configured as output D 7 0 control the data to the pins While the DIR bits are low pins configured as input D 7 0 report the signal level on the pins The 7 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports data bits may be read or written at any time If a pin is configured as input only a write to the corresponding bit in this register does not affect the pin These bits reset to 0 SEL Select 0 7 These bits select whether the data bus DO D7 or general purpose I O signals are connected to the pins When a bit is high the corresponding port pin is configured as a general purpose 1 O and when they are low port B is a lower byte data bus 7 5 3 Port C Registers Port C is multiplexed with the M68000 bus control signals described in Table 7 2 Table 7 2 Port C Bit Functions PORT FUNCTION x o Ce ce ee MECO LIO E e TT Port C has three config register Although th isters only six bits are used to individually configure the six port pins Bit only when the on chip PLL is selected because the
117. dress match occurs a chip select is generated CSAx AND CSBx BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD Ac23 AC22 AC21 AC20 AC19 AC18 AC17 AC16 RESERVED BUSW R W RW RW RW RW RW RW RW RW R W FIELD AM23 AM22 AM21 AM20 AM19 AM18 AM17 AM16 RESE O WAIT RW RW RW RW RW RW RW RW RW R W R W RESET 0x00010006 ADDR Ox FF FFF110 114 118 11C AC23 AC16 Address Compare 23 16 f This field together with the AMx field def Some of the address bits overlap i chip select register The overlappi S finally decode a chip select mparison range for this chip select se address and mask registers and the flexibility to select a large group and Bits 23 17 Reserved These bits are reserv AA to 0 BUSW Bus W This bit sets t he memory space selected by this chip select ote This bit is read only for CSAO and reflects the logic level on the BBUSW pin AM23 AM16 Address Mask 23 16 for Groups A and B This field masks the corresponding bits in the ACx field 0 For a match to occur the address line must match the corresponding bit in the CSAx or CSBx register 1 The corresponding address line compares true don t care 5 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Frees
118. e CPU depending on the FI bit in the WRR Therefore once the software watchdog timer is enabled your software must clear the software watchdog timer periodically so that it never reaches its timeout value The maskable interrupt generated is cleared by clearing the watchdog counter ascaler module The he output of this The software watchdog timer uses the 32kHz clock as the inp prescaler circuitry divides the clock input by a fixed value of ei of 65535 or OXFFFF in hex Note At reset the watchdog timer is en y the watchdog control status application if you do not he watchdog timer you should turn it off in the system boot up is recommended that you turn the software watchdog cessor in sleep or doze because the watchdog these modes The value of the software watchdog timer off before you timer will continu run i timer SY d at any time plexed with the Port G I O signals See Section 7 Parallel about enabling the timers 10 4 SIGNALS e TOUT1 PG5 and TOUT2 PG3 This pin is the output of the timer and can be programmed to toggle or pulse when a compare event occurs MOTOROLA MC68328 USER S MANUAL 12 9 97 10 3 For More Information On This Product Go to www freescale com TIMERS EE Freescale Semiconductor Inc Timers 10 5 PROGRAMMING THE GENERAL PURPOSE TIMERS 10 5 1 Timer Unit 1 and 2 Control Registers You can use the timer unit 1 and 2 control registers TCTL1 and TC
119. e LCD panel data bus dicates the start of a new display frame LFLM becomes active after the first line pulse of the frame and remains active until the next line pulse at which point it de asserts and remains inactive until the next frame LFLM can be programmed to be an active high or an active low signal LP LINE PULSE This signal latches a line of shifted data onto the LCD panel It becomes active when a line of pixel data is clocked into LCD panels and remains asserted for 8 pixel clock periods LP can be programmed to be either an active high or an active low signal 2 9 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com O 2 D z gt m o le E v l e 2 z Freescale Semiconductor Inc Signals LCLK SHIFT CLOCK This is the clock output to which the output data to the LCD panel is synchronized LCLK can be programmed to be inverted LACD ALTERNATE CRYSTAL DIRECTION This output is toggled to alternate the crystal polarization on the panel and is used to protect the crystal from DC voltages This signal can be programmed to toggle at a period from 1 to 16 frames 2 1 17 JTAG Testing Pins TCK TEST CLOCK This pin provides a test clock input for boundary scan test logic define e IEEE1149 1 standard If JTAG is not used or during normal operation TC be connected to an extrnal pullup resistor TMS TEST MODE SELECT This input c
120. e SPMCLK polarity 0 Active high polarity O idle 1 Inverted polarity 1 idle BIT COUNT These bits select the transfer length up to 16 sferred 0000 1 bit transfer 1111 16 bit transfer 12 3 2 SPIM Data Register This register exchanges data with external slave devices 15 14 13 12 11 11 8 7 6 5 4 3 2 1 0 DATA ADDRESS FF F RESET VALUE 0000 DATA These e data bits to be exchanged with the external device The data must be loaded H bit is set At the end of the exchange data from the peripheral is present in hese bits contain unknown data if they are read while the XCH bit is set A write to these bits will be ignored while the XCH bit is set As data is shifted MSB first outgoing data is automatically MSB justified For example if the exchange length is 10 bits the MSB of the outgoing data is bit 9 The first bit presented to the external slave device will be bit 9 followed by the remaining 9 bits af ce Th TX Es uo ag LL Ef TE ane Note Users should reload the data every time for each transfer before setting the XCH bit MOTOROLA MC68328 USER S MANUAL 11 10 97 12 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 13 SERIAL PERIPHERAL INTERFACE SLAVE The slave serial peripheral interface SPI operates as an externally clocked slave allowing the MC68328 proces
121. e level 7 interrupt is known as nonmaskable interrupt in the rchitecture This means that when all interrupts are masked in the CPU sta level 7 interrupt can still be recognized by the microprocessor On the MC6 er you can set this bit to block IRQ7 interrupt from being sent to the process 0 Enable IRQ7 interrupt 1 Mask IRQ7 interrupt 6 5 4 Interrupt Wake gister The interrupt wake up IWR enables the corresponding interrupt source to start the power cont uence When a bit in this register is set the bit positions in this register correspond to the bits in the interrupt status ding register and interrupt mask register 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED IRQ7 TMR1 SPIS PEN IRQ6 IRQ3 IRQ2 IRQ1 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO PWM WKB RSVD RTC WDT UART TMR2 SPIM R W R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESET OxFFFF ADDR Ox FF FFF308 MOTOROLA MC68328 USER S MANUAL 12 9 97 6 11 For More Information On This Product Go to www freescale com 5 E gt ce cr wis e o Qz o4 Zm 33 Da oc D E ra D Freescale Semiconductor Inc Interrupt Controller IWR BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W
122. eal time clock reference signa signals are described in Table 7 4 DA UNCTION FUNCTION a CA ICC MECO eae TEO INICIO ONCE IN als Refer to the timer pulse ion of the signal functions All d to an I O pin As with other r PG7_RTCO is a dedicated input for OCLK bit port C pin 0 is high The BIT MEAN AAA E 2 1 o0 FIELD DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIRO D7 D6 D5 D4 D3 D2 Di DO RESET 0x00xx 7 14 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com v gt po gt a rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR OxFFFFF430 BT 15 14 13 12 MA a ee eae FIELD PU7 PUG PU5 PU4 PU3 PU2 PU1 PUO SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO RESET OXFFFF ADDR OXFFFFF432 DIR Direction 0 7 These bits control the direction of the corresponding port pin W corresponding port pin is an output pin and when it is low the c sponding port pin is an input pin These bits reset to O and do not affect the behavior c are low D Data 0 7 These bits control or report the data on the pins Whe R bits are high D 7 0 control the data to
123. eescale Semiconductor Inc Applications and Design Examples 16 1 1 M68328 Processor Signal Configuration A low boot bus width select BBUSW at reset means that the system will boot up with an 8 bit ROM A low mode clock MOCLK signal at reset means that the M68328 processor uses the 32 768kHz crystal and enables its internal PLL to supply the clock for the entire chip The suggested circuit for PLL is shown in Figure 14 2 The RESET signal should be connected to the JTAGRST signal to ensure that the entire chip including the JTAG block is reset properly at the same time The RESET and JTAGRST should be held low for more than 100ms before they are released as required by the M68EC000 user s manual There is no power on reset circuit implemented in the M68328 processor therefore use external circuits either from a MC1455 mono stable timer or power on reset signal from most of the power supply chips to generate the RESET signal The RESET signal in this example connects to a debouncing circuit to generate a reset for the M6832 32 768kHz 20pF XTAL EXTAL PLLVCC gt luf To Power Supply vos yy gt To Power Suppl GND s PRY Avec 10K J ore MC68328 A 16 67MHZ QA TA ABORT A T ihe M LK Avec Avcc Avcc 10K 10K 10K 7 Ol lt O 4 g
124. eld defines the comparison range for this chip select Some of the address bits overlap in the group base address and mask registers and chip select register The overlapping gives you the flexibility to select a large group and finally decode a chip select Bits 17 19 Reserved These bits are reserved and should be set to 0 MOTOROLA MC68328 USER S MANUAL 12 9 97 5 7 For More Information On This Product Go to www freescale com e o e l E o uu l lu og 2 I Ss O O o p on m m m O 2 je Q o Freescale Semiconductor Inc Chip Select Logic BUSW Bus Width This bit sets the bus width of the memory space selected by this chip select 0 8 bit 1 16 bit AM23 AM12 Address Mask 23 12 for Groups C and D This field masks the corresponding bits in the ACx field 0 For a match to occur the address line must match the corresponding bit in the CSCx or CSDx register 1 The corresponding address line compares true don t care RO Read Only This bit configures the memory space selected by this chip se read only Otherwise read or write accesses are allowed However writes to read o ause a write protection violation to occur as described in Secti 1 1 tem Control Register 0 Read write 1 Read only WAIT Wait State Selection This field determines the number of wait state t added before an internal DTACK signal is returned for the chip select 000
125. enable bit 9 IRQEN interrupt enable PHA phase control bit 5 POL polarity control bit 4 BIT count data burst le bits 3 0 Load data 0 O O O O O 0 Zm m qe su Om L2 52 ao 4 m gt Dr 12 2 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Master 12 1 2 Phase Polarity Configurations The SPIM transfers data in and out of the shift register with the SPICLK Data is clocked using any one of the variations of clock phase and clock polarity The clocked transfer may be programmed in phase and in polarity Figure 12 2 In phase 0 operation output data changes on falling clock edges while input data is shifted on rising edges In a phase 1 operation output data changes on rising edges of the clock and is shifted on falling edges Polarity 1 inverts the data clock relationships This flexibility allows operation with most serial peripheral devices on the market 12 2 SIGNAL DESCRIPTIONS The following signals are multiplexed with other signals in port K R to Section 7 1 10 for more information SPMTxD TRANSMIT DATA This pin is the shift register output A new data bit is presented SPMCLK in normal mode or on each falling edge of SP in i each rising edge of the SPMRxD RECEIVE DATA This pin is the shift register input A new bit is shi i ch falling edge of SPMCLK whi
126. er IPR 6 4 VECTOR GENERATOR any address in the exception vector table However many o assigned to the core s internal exceptions and cannot b range of address space from 0x100 through 0x400 wh locate user interrupt vectors For example if you write a interrupt vector base is set to point to 0x100 0x40 lt lt 2 which is the beginning of the user interrupt vectors shown in Table 6 1 The codi ctor numbers is provided in Table 6 2 Table 6 2 Inter Vector Numbers XXXXX110 A Q interrupt vector register NOTE xxxxx is replaced by the upper five bits of the 6 5 PROGRAMMING MODEL This section describes registers that you may need to configure so that the interrupt controller can properly process interrupts generate vector numbers and post interrupts to the core MOTOROLA MC68328 USER S MANUAL 12 9 97 6 5 For More Information On This Product Go to www freescale com 5 E gt ce cr wis Je o Qz o4 Zm 33 Du oc D ra D Freescale Semiconductor Inc Interrupt Controller 6 5 1 Interrupt Vector Register The interrupt vector register IVR programs the upper five bits of the interrupt vector number During the interrupt acknowledge cycle the lower three bits encoded from the interrupt level are combined with the upper five bits to form an 8 bit vector number The CPU uses the vector number to generate a vector address During system start up the IVR
127. erator source m clock 1 Baud rate generator DA GPIO pin GPIO DIR must be 0 DIVIDER Clock Divider This field controls the clock fre produced by the baud rate generator The bits are encoded as follows 101 U 110 Divide by 64 111 Divide by 128 PRESCALER Clock Prescaler This field controls the divide value of the baud rate generator prescaler The divide value is determined by the following formula prescaler divide value 65 decimal PRESCALER 11 12 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter 11 4 3 UART Receiver Register The UART receiver URX register contains the status of the receiver The high byte of this register resets to 0x00 This register contains random data until the first character is received The CHARACTER STATUS field is updated and valid with each data character Status and data must be read as a 16 bit word URX BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GROUP FIFO STATUS CHARACTER STATUS DATA FIELD a one TA 0 OVRUN ae BREAK a RX DATA R W R R R R R R R R RESET OxOXxxx ADDR Ox FF FFF904 FIFO FULL FIFO Full This read only bit indicates that the receiver FIFO is full a ay generate an overrun 0 Receive FIFO not full no interrupt po 1 Rece
128. ere is a keyboard interrupt its default value 1 Keybc pt is pending PWM Modulator Interrupt This bit i ates that a PWM period rollover event occurs This is a level 4 interrupt 0 No pulse width modulator period rollover event occurred 1 Pulse width modulator period rolled over INTO External INTO Interrupt O No INTO interrupt 1 INTO interrupt is pending INT1 External INT1 Interrupt No INT1 interrupt INT1 interrrupt is pending mb oll 6 18 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller INT2 External INT2 Interrupt 0 No INT2 interrupt 1 INT2 interrupt is pending INT3 External INT3 Interrupt 0 No INT3 interrupt 1 INT3 interrupt is pending INT4 External INT4 Interrupt O No INT4 interrupt 1 INT4 interrupt is pending INT5 External INT5 Interrupt 0 No INT5 interrupt 1 INT5 interrupt is pending INT6 External INT6 Interrupt 0 No INT6 interrupt 1 INT6 interrupt is pending INT7 External INT7 Interrupt 0 No INT7 interrupt 1 INT7 interrupt is pending IRQ1 Interrupt Request Level 1 vice has requested an interrupt on level 1 If rrupt you must clear the source of the interrupt set to be a level sensitive interrupt you must clear the source of the interrupt If IRQ2 signal is set to be an edge tr
129. ers that are used for byte 8 bit word 16 bit and long word 32 bit operations When using the data registers to manipulate data they affect the status register SR The next seven registers A6 A0 and the user stack pointer USP can function as software stack pointers and base address registers These registers can be used for word and long word operations but they do not affect the status register The D7 DO and A6 A0 registers can be used as index registers 31 16 15 8 7 0 D TERS 31 16 15 0 A0 A ADDRESS REGISTERS AS A6 31 161 0 A7 USP USER STACK POINTER 31 0 PC PROGRAM COUNTER 0 SR STATUS REGISTER ure 3 2 User Programming Model In supervisor m SSP ca O pper byte of the status register and the supervisor stack pointer med as shown in Figure 3 3 0 A7 SSP SUPERVISOR STACK POINTER SR STATUS REGISTER Figure 3 3 Supervisor Programming Model Supplement The status register contains the interrupt mask with seven available levels as well as an extend X negative N zero Z overflow V and carry C condition code The T bit indicates when the processor is in trace mode and the S bit indicates when it is in supervisor or user mode MOTOROLA MC68328 USER S MANUAL 12 9 97 3 3 For More Information On This Product Go to www freescale com ARCHITECTURE O Freescale Semi
130. es are all zeroes Users should note that there may be contention if a gic 1 levels are driving these pins during or after reset NY PF7 PF0 A31 A24 ended address for 68EC000 core and are multiplexed with port e lines are not used as addresses because most memory chips can ess than 16 Mbytes These pins default to the port F I O function These bus pins after re 2 1 5 Data Bus Pins D15 D0 The flexible data bus interface design of the MC68328 processor allows users to program the lower byte of the data bus in an 8 bit only system as general purpose I O signals D15 D8 The upper byte of the data bus is not multiplexed with any other signals In pure 8 bit systems this is the data bus In mixed 8 16 bit systems 8 bit memory blocks or peripherals should be connected to this bus 2 4 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt a m o le E v l e 2 z Freescale Semiconductor Inc Signals PB7 PB0 D7 DO This bus is the lower data byte or general purpose I O In pure 8 bit systems this bus can serve as a general purpose I O The WDTH8 bit in the system control register SF FFO00 should be set to one 1 by software before the port can be used In 16 bit or mixed 8 16 bit systems these pins must function as the lower data byte 2 1 6 Bus Control Pins AS ADDRESS STROBE This active low output signal
131. es as opposed to black and white mode Also the line buffer must be filled before the next line is displayed Therefore the LCD pixel clocking LCD frame refresh rate line buffer fill and line to line interval are affected by the selection of grayscale mode The frame refresh rate and pixel clocking are determined by the LCD pixel clock divider LPXCD register Frame refresh is also a function of the LCD screen size in pixels Therefore the LXMAX and LYMAX registers are factors for calculating frame refresh Figure 8 6 illustrates grayscale mapping and its memory requirement 8 2 8 Gray Palette Mapping Using a proprietary frame rate control FRC algorithm the LC ntroller can generate a maximum of four out of seven simultaneous gray levels ing the 2 bit data into four 3 bit gray codes Then four out of seven bit densities are rom the gray palette table Figure 8 6 illustrates how the 2 bit pixel data are defined in the software programmabl Each of the four 3 bit codes obtained from 11 46 94 and 1 from the gray palette table driving voltages vary which means t 3 bit gray codes The GMN bits alette mapping registers LGPMRs ble select a density level 0 1 4 9 6 1 2 in Table 8 2 Crystal formulations and effect may or may not be linearly related to the frame rate For certain gra thmic scale such as 0 and 1 might be more effective than a linearly sp le like 0 5 46 11 4 and 1 A flexible mapping scheme
132. external to the DragonBall microprocessor transforms the infra red signal into an electrical signal MOTOROLA MC68328 USER S MANUAL 12 9 97 11 5 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter 11 3 3 Baud Rate Generator The baud generator provides the bit clocks to the transmitter and receiver blocks It consists of a prescaler and a 2 divider The baud rate generator master clock source can either be the system clock SYSCLK or it can be provided by the GPIO pin input mode By setting the BAUD SOURCE bit in the UART baud control register to 1 an external clock can directly drive the baud rate generator For synchronous applications the GPIO pin can be configured to serve as an input or output for the 1x bit clock The baud rate generator block diagram is illustrated in Figure 11 4 MASTER CLOCK BAUD SRC YSCLK 250 PRESCALER GPIO IN CLK16 DIVIDER DIVIDE BY 2 CLK1 CLK MODE CLK SRC r mi 11 3 3 1 DIVIDER The divider N y divider with eight taps The available taps are 1 2 4 8 16 32 64 and 128 The selected tap is the 16x clock CLK16 for the receiver itof the UART status and control register is high CLK1 signal transmitter When th is directly source 11 3 3 2 P The baud generator provides standard baud rates from many system cies However it is optimal if the PLL is operating
133. freescale com Freescale Semiconductor Inc SECTION 9 REAL TIME CLOCK The real time clock RTC provides a current time stamp of seconds minutes and hours It operates on the low frequency 32kHz or 38 4kHz reference clock crystal 9 1 FEATURES The following list summarizes the features of the real time cl Full clock features seconds minutes and hours e Minute countdown timer with interrupt Programmable alarm with interrupt Once per second once per minute and o interrupts e 32 768kHz or 38 4kHz operation The real time clock block diagram is illustr i ure 9 1 x 8 1PPS PPM 1PPH a S2 76BKHZ PRESCALER seconD P MINUTE gt HOUR 8 ol rT a i z A O l ALARM COMPARATOR INTERRUP Spr CONTROL SECOND MINUTE HOUR CONTROL Pen oe l LATCH LATCH LATCH lt lt INTERRUPT amp y ENABLE L gt INTERRUPT STATUS m ADDRESS EC000 DATA BUS lt ____ gt BS CONTRO DECODE Figure 9 1 Real Time Clock La MINUTE STOPWATCH lt lt MOTOROLA MC68328 USER S MANUAL 12 9 97 9 1 For More Information On This Product Go to www freescale com O E m gt T E m Q 2 e le A Freescale Semiconductor Inc Real Time Clock 9 2 OPERATION 9 2 1 Prescaler and Counter The prescaler divides the 32 768kHz
134. from memory and provides control signals frame line pulse clocks and data to the LCD module It supports monochrome STN LCD modules with a maximum of four grayscale levels with frame rate control System RAM can be used as display memory and DMA frees the CPU from panel refresh responsibilities 3 8 UART The UART communicates with external devices with a standard asynchronous protocol at baud rates from 300bps to 115 2kpbs The UART provides the pulses to directly drive standard IrDA transceivers 3 9 REAL TIME CLOCK A The real time clock provides time of day with one second re either 32 76 or 38 4kHz as a clock source to keep pro ime power is applied to the chip which can be in sleep or do NS O uses the crystal eps time as long as gt D O Ss m e 4 i D m 3 8 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture 3 10 PROGRAMMER S MEMORY MAP The memory map is a guide to all on chip resources Use the following table as a guide when configuring your chip The base address used in the table is OxFFFFFOOO and OxFFFOOO from reset If a double mapped bit is cleared in the system control register then the base address is OxFFFFFOOO Unpredictable results occur if you write to any 4K register space not documented in the table Table 3 3 Programmer s Memory Map
135. gnal this pin accepts an activ level triggered interrupt from the pen input device for a pen down action PM5 PM2 IRQ1 IRQ2 IRQ3 IRQ6 These pins can be programmed to either parallel I O PM rupt input When they function as interrupt inputs they can be programmed to be vel triggered with either high or low polarity IRQ6 generates a level 6 interrupt IR IRQ2 and IRQ1 generate level 3 2 and 1 interrupts respectively 2 1 8 Chip Select Pins CSA0 BOOT CHIP SELECT CSAO is the default chip select after r 3 set to 6 wait states and decodes all address ranges except internal register ad ce It can be reprogrammed during the boot sequence to another addr range and a different number of wait states PE7 PE1 CSB3 CSBO CSA3 CHIP SELECT GROUP A AND B inder of the Group A and Group B chip selects and are that are not needed as chip selects can be programmed as purpose l Os 2 1 9 PCMCIA 1 0 PINS PC6 WE WRITE ENABLE PC6 This pin can be programmed as either PC6 parallel I O or a write enable signal for the PCMCIA 1 0 card interface The MC68328 processor drives the active low WE signal to indicate a memory write transfer to the PCMCIA 1 0 card When programmed as I O it serves as PC6 2 6 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com O 2 D ES gt z m 22 le 2 v l e 2 a Freescale Semiconductor Inc
136. gured as input only a write to the corresponding bit in this register does not effect the pin These bits reset to 0 SEL Select 0 7 The select register allows you to individually select the function set a bit in this register the corresponding port pin is configure When a bit is clear the corresponding port pin is configured as a all bits in the select register are cleared each port pin When you das eneral purpose l O s control signal At reset 7 5 4 Port D Registers Port D has special features that allow it to be u use port D as a general purpose l O port other ports each pin can be configured a configured as an input each pin ca signals are presented to the interru interrupt can be generated This interr and it is presented to the interrupt contro board input port You can also l purpose interrupt port As with the utput on a bit by bit basis When interrupt These individual interrupt odule as INT 7 0 In addition a group OR negative logic of all pins on the port as a keyboard KB interrupt Each interrupt can be config either as a level sensitive interrupt or an edge triggered interrupt The polarit e in pt can also be selected Each pin is equipped with a switchable pull up re BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D DIR5 DIRA DIR3 DIR2 DIR1 DIRO D7 D6 D5 D4 D3 D2 Di DO RESET 0x0000 ADDR OXFFFFF418
137. h level languages that facilitate programming Almost every instruction operates on bytes words and long words and most of them can use any of the 14 address modes By combining instruction types data types and address modes you can have access to over 1 000 instructions These instructions include signed and unsigned multiply and divide quick arithmetic operations binary coded decimal BCD arithmetic and expanded operations through traps Table 3 2 Instruction Set MNEMONIC ABCD DESCRIPTION MNEMONIC Add decimal with extend MOVEM ADD Add MOVEP ADDA Add address MOVEQ ADDQ Add quick MOVE from ADDI Add immediate MOVE to S to status register ADDX Add with extend MOVE CR ove to condition codes AND Logical AND ove user stack pointer ANDI AND immediate LS Signed multiply ANDI to CCR AND immediate to condition code Unsigned multiply ANDI to SR AND immediate to status register CD Negate decimal with extend ASL Arithmetic shift left Negate ASR Arithmetic shift right Negate with extend Bcc Branch conditi No operation BCHG Bit test change Ones complement BCLR Bit test and r Logical OR BRA OR immediate BSET et ORI to CCR OR immediate to condition codes BS nch to subroutine ORI to SR OR immediate to status register B Bit PEA Push effective address CHK Check register against bounds RESET Reset external devices CLR Clear operand ROL Rotate left without extend CMP Compare ROR
138. hin Quad Flat Pack TQFP are shown in Figure 2 2 SSSSSSISSSSSSLSSASSSSSSLSSRSSLRR LLL D2 PB2 09 PJ7 CSD3 D1 PB1 10 VCC DO PBO t1 PDO KBO INTO TDO 12 PD1 KBI INTT TDI 13 PD2 KB2 INT2 GND 14 PD3 KB3 INTS OE 15 PD4 KB4 INT4 UDS PCt 16 PDS KBS INTS AS 17 PD6 KB6 INT6 A0 18 PD7 KB7 INT7 LDS PC2 19 GND RW 20 LDO JTACK PC5 21 LD1 RESET 22 LD2 T VCC 23 LD3 PC6 24 LFRM JTAGRST 25 MC68328PV LLP BBUSW 26 TOP VI LCLK A 27 LACD A2 28 vec A3 29 PKO SPMTXDO A4 30 PK1 SPMRXDO A5 31 PK2 SPMCLKO A6 32 PK3 SPSEN GND 33 PK4 SPSRXDI A7 34 PK5 SPSCLKI A8 35 PK6 CE2 A9 36 PK7 CE1 A10 37 GND A11 38 PMO CTS A12 39 PM1 RTS A13 40 PM2 IRO6 A14 41 PM3 IRO3 Vcc 42 PM4 IRO2 A15 43 PM5 IRQ1 A16 PAD 44 PM6 PENIRQ RANRARRAARSSSSS88 8585858 8R O95 58228 CLA LS JO LLL gt EBES sea pero a oF3s FS ES E Fo E Figure 2 1 Pin Assignment 2 11 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signals 40 20 0 008 H L M
139. hip select can be n be programmed only by the ection of M68328 processor le When the M68328 OE signal will always be asserted and the CSA1 and CSA2 are s To achieve better faster timing users k the CSAx signal to the EPROM OE signal r conscious system because the EPROM 16 1 2 2 SRAM INT 16 bit 8 bit x 2 during a wri signal the U ed for the W signal Y Note The WE signal of the M68328 processor supports PCMCIA 1 0 when CSD3 is in use It cannot be used for general SRAM write enable signals MOTOROLA MC68328 USER S MANUAL 11 10 97 16 3 For More Information On This Product Go to www freescale com on zu GE wn Z x ER w oz a9 aw aw lt A Freescale Semiconductor Inc Applications and Design Examples 27C040 27C040 512KX8 512KX8 EPROM EPROM DO 13 12 At D8 13 DI 14 E A 11 A2 DI 14 D2 _15 p2 a2 40 A3 D10 15 D3 17 p3 as 9 A4 DI 17 D4 18 54 As 8 A5 Di2 18 D519 55 as 7 A6 D13 19 DS 20 pe as 6 A7 D14 20 D7 21 p7 A7 5 A8 Di5 21 as 27 A9 ag 26 A10 ato 23 Ati Att 25 A12 aro 4 A13 A13 28 A14 ara 29 A15 A15 3 At6 Ss CSAT22 GE ate 12 A17 _CSAT22 mu OE 24 lo A17 30 A18 OE 24 22 Aig 31 A19 ES u 27C040 SO 512KX8 z EPROM hd m DO 13 ag DI 14 By D2 _15 p2 D3_17 p3 D418 54 D5 19 p5 D6_ 20 pg 7 21157 TSA2Z22 CSA222 log rps 2 A17 OE 24i OE 245E 117 30 A18 Aig 81
140. his Product Go to www freescale com Freescale Semiconductor Inc LCD Controller 8 1 3 Line Buffer The line buffer collects display data from system memory during DMA cycles and outputs it to the cursor control logic The input is synchronized with the fast DMA clock and the output is synchronized to the relatively slow LCD pixel clock PIXCLK 8 1 4 Cursor Logic When enabled the cursor control logic generates a block shaped cursor on the display screen You can adjust the cursor height and width anywhere between 1 and 31 pixel counts The cursor can be black or it can be in reversed video The blinking rate is adjustable when the blink enable bit is set 8 1 5 Frame Rate Control The frame rate control FRC is primarily used for a grayscal maximum of four gray levels out of seven density levels 0 shown in Table 8 2 The density level corresponds to th turned on when the display is refreshed frame by fr driving voltage may vary you can tune the visual gra palette mapping register LGPMR to obtain th d can generate a 11 16 3 4 1 as imes the pixel is being rystal formulations and y programming the LCD gray Blinking or flickering will occur if all LCD pixel two 4 bit numbers XOFF and YOFF in th odd numbers that differ by two Diff i optimal offset values to vary among manufacturer 8 1 6 LCD Panel In N The LCD panel inter packs the display data in the correct size and outputs it to the LCD panel
141. ications and Design Examples where t DATA setup requirement 20 ns cCLKO es T a ADDR X X X CSxx q laccess DATA E x X y g t2 Figure 16 6 LCD Chip Select Ac An equation for the access time tacess can b m Figure 14 6 This equation applies to ECOOO core accesses tacess 1 WS T t te where WS wait states where T system clock perio where t CSxx delay 30ns where t DATA setup requi nt 20ns nitialization is idle low and an LCD pixel clock is not provided to the LCD current may be induced in the LCD panel glass due to unknown values ters this DC current causes permanent demage to the LCD panel oid this situation users may either turn off the LCD VEE high ve or ve ower on default or initalize the LCD controller immediately after the processor e temporary initialization routine protects the LCD panel screen voltage as has started 16 2 4 Programming the Interrupt Controller The interrupt controller level is summarized as shown in Figure 14 5 Basically all 7 levels of the 68EC000 are used Because some of the interrupts are lumped into one interrupt level such as Level 4 a user s interrupt service routine should resolve the priority by reading the MOTOROLA MC68328 USER S MANUAL 11 10 97 16 11 For More Information On This Product Go to www freescale com on zu E wn ox EX w lt q oz 59 aw aw XAO Freescale Semico
142. ich is equal to the screen height in pixel count LYMAX BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD ae Se M8 YM7 YM6 YM5 YM4 YM3 YM2 YM1 Yvo RW RW RW RW Rw Rw RW I Rw RW Rw Rw RESET 0x01FF ADDR GG Ox FF FFFAOA 8 16 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller 8 5 CURSOR CONTROL REGISTERS 8 5 1 LCD Cursor X Position Register The LCD cursor X position LCXP register is used to configure the horizontal position of the cursor LCXP A 1 10 8 a o il eaen lino FIELD CC1 CCO CXP9 CXP8 CXP7 CXP6 CXP5 CXP1 CXPO RW R W R W R W RW RW RW RW RW RW RW RESET 0x0000 ADDR Ox FF FFFA18 CC Cursor Control 00 Transparent Cursor is disabled 01 Full density black cursor 10 Reversed video 11 Do not use Invalid CXP Cursor X Position 8 0 These bits represent the cursor s horizont rting position X in pixel count from 0 to LXMAX 8 5 2 LCD Cursor Y Psion Re ter The LCD cursor Y LG YP register is used to configure the vertical position of the cursor ll LCYP BT 15 14 E arar FIELD CYP8 CYP7 CYP6 CYP5 CYP4 CYP3 CYP2 CYP1 CYPO R W RW RW R
143. icular task PWMOUT The PWM outputs a pulse stream of varying frequency and duty cycle as determined by the his makes the PWM ideal for motor control The PWM output tones with a simple external low pass filter connected may alternately be u i ible to produce high quality digitally generated voice The to the output pin x faa ae SS u5 36 gt oF be between 6 The following figure relates the pulse stream to the filtered audio out PULSE STREAM FILTERED AUDIO SS A Figure 14 2 PWM Generating Audio MOTOROLA MC68328 USER S MANUAL 11 10 97 14 1 For More Information On This Product Go to www freescale com U Se 2u SE EE DF Freescale Semiconductor Inc Pulse Width Modulator The width and period registers are double buffered so that a new value can be loaded for the next cycle without disturbing the current cycle At the beginning of each period the contents of the buffer registers are loaded into the comparator for the next cycle Sampled audio can be recreated by feeding a new sample value into the width register on each interrupt The prescaler provides operating flexibility Figure 11 3 illustrates its functionality The prescaler contains a variable divider that can divide the incoming clock by certain values between 2 and 256 inputclock clk sel PCLK clk sel 14 1 PROGRAMMING Bo This section describes the pj mo registers and control bits
144. id Ss gt n n wo e E Qn am z ToO Ex ga w no Sa oe ee 31 3 ninja ninja n n MOTOROLA MC68328 USER S MANUAL 11 10 97 17 6 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics S1 N e E Qn am z ToO Ex ga w no Ps R 2 pa a lt lt gt lt a lt S E ZA a lt gt lt gt lt Er y lt EC or RQ NV lt a E c E lt 5 A Y A iE gt STITFT 0 o Q q Q x pral O amp 2 LL O lt kx Xx b QO O Figure 17 3 LCD DMA Read Cycle Timing when the DMAC is the Bus Master MOTOROLA MC68328 USER S MANUAL 11 10 97 17 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics Table 17 4 AC Electrical Specifications PCMCIA Write Cycle Timing CHARACTERISTIC UNIT am ua D1 witeGytetime gt e 2 par Set Time CET OEE Resend Fa FT 3 Addr Valid to WE Asserted WE Negated to Address Invalid Data Setup to WE Negated 6 WE Negated to Data Invalid Hold Time wo e E Qn am z ToO Ex ga w no A31 A0 x Y A Figure 17 4 PCMCIA Write Cycle Timing Table 17 5 ical Specifications PCMCIA Read Cycle Timing Q Read Cycle Time Addr Access Time
145. idth for more information 8 2 1 DMA As shown in Figure 8 2 and Figure 8 3 data is efficiently fetched from memory Each burst is limited to 8 16 words which reduces the possible late other peripherals such as the interrupt controller For example the average latency LK 5MHz with a 16 word burst is approximately 2 4us SYSCLK INTERNAL BR 1 INTERNAL BG l ADDRESS LA i DATA i Figure 8 2 Three Clocks per LCD DMA Transfer Two Wait States 8 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller To operate the DMA begins with an internal bus request from the DMA to the core and a bus grant to the DMA controller when the processor has given up the bus The DMA cycle on the bus begins with chip select assertion and addressing for the first data word to be transferred A DMA cycle is indicated on the bus when a chip select is asserted with AS negated One clock cycle is added to the first data transfer of the DMA to allow for chip select access time For example if the number of clock cycles selected for each DMA data word transfer is two the first data word would transfer in three clocks Subsequent data word transfers occur in two clock cycles to the end of the DMA burst If the number of wait states selected is zero the DMA contro
146. iggered interrupt you must clear the interrupt by writing a 1 to this bit writing a O has no effect O No level 2 interrupt is pending 1 Level 2 interrupt is pending IRQ3 Interrupt Request Level 3 When set this bit indicates that an external device has requested an interrupt on level 3 If IRQ3 signal is set to be a level sensitive interrupt you must clear the source of the interrupt MOTOROLA MC68328 USER S MANUAL 12 9 97 6 19 For More Information On This Product Go to www freescale com 5 E gt ce ce wis EO o Freescale Semiconductor Inc Interrupt Controller If IRQ3 signal is set to be an edge triggered interrupt you must clear the interrupt by writing a 1 to this bit writing a O has no effect 0 1 No level 3 interrupt is pending Level 3 interrupt is pending IRQ6 Interrupt Request Level 6 When this bit is set it indicates that an external device is requesting an interrupt on level 6 If IRQ6 is set to be a level sensitive interrupt you must clear the source of the interrupt If IRQ6 is set to be an edge triggered interrupt you must clear the interrupt by writing a 1 to this bit Writing a 0 to this bit has no effect O No level 6 interrupt pending 1 Level 6 interrupt is posted Qz o4 Zm 33 Da oc D E ra D 6 20 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 7
147. indicates that a valid address is present on the address bus lt is not asserted during LCD DMA accesses R W READ WRITE This output signal defines the data bus transfer as a read or wri PC1 UDS UPPER DATA STROBE PORT C I O This pin can be programmed as UDS or as a general pur strobe UDS output this active low signal is asserted w ernal ECOOO core does a 16 bit word access or an even byte access It is not asserted during LCD DMA accesses PC2 LDS LOWER DATA STROBE PORT This pin can be programmed as LDSor a rpose I O When used as lower data strobe LDS output this active low signal d when the internal ECOOO core does a 16 bit word access or an odd byte t asserted during LCD DMA accesses LWE UWE LOWER BYTE W E AND UPPER BYTE WRITE ENABLE On awrite cycle to a 16 bit port thes tive low output signals indicate when the upper or lower 8 bits of the data b i id data In 8 bit mode or when the BSW bit in the chip write enable UWE for write enable control PC4 IRQ7 LEV T PORT C I O When program a rals this signal is an active low input which when asserted will generate a leve errupt to the CPU When programmed as l O it becomes the PC 4 parallel PC5 D DATA TRANSFER ACKNOWLEDGE PC5 This pin ca programmed as parallel I O PC5 or DTACK While programmed as DTACK this input signal indicates that the data transfer has been completed DTACK is normally generated internally for all chip selects F
148. isab ed p bu NA h Si Output High Output High N A nput nput nput nput nput nput nput nput Input Internal Pul Disab DEFAULT RESET PULL UP STATUS Internal Pull up 65 Enabled Internal Pull up Enabled Internal Pull up 67 Enabled Internal Pull u Enabled NETO na q KE ernal Pull eas 8 8 8 8 8 N PIN NUMBER d Enabled up ed Internal Pull up Disabled Internal Pull up Disabled Internal Pull up Disabled Internal Pull up Disabled ull up d u d p u d p up Internal P Disable Internal Pul Enable Internal Pul Enable Internal Pu Enabled up Internal Pull up Enabled Internal Pull up Enabled Internal Pull up Enabled Internal Pull up Enabled Internal Pull up Enabled Internal Pull up Enabled 0 1 2 3 4 5 7 A 17 16 14 13 12 11 10 18 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports Table 7 1 Reset Default Port Assignments Continued DEFAULT PORT I O DEFAULT PORT DEFAULT PIN RESET TYPE RESET STATE RESET PULL UP NUMBER FUNCTION STATUS G IN yo P 26 7 5 PROGRAMMING MODEL 7 5 1 Port A Registers N Port A is multiplexed with address lin 6 u 5 u 4 u PG2 Pu 23 1 u 0 u Depending on the system s specifications you can decide which of these a use Unused address pins can serve a
149. ive FIFO full interrupt posted FIFO HALF FIFO Half This read only bit indicates that the 0 Receive FIFO less than f terrupt posted 1 Receive FIFO more than hal interrupt posted When h is read only bit indicates that the receiver overwrote data in the FIFO The character this bit set is valid but at least one previous character was lost Under normal circumstances this bit should never be set It indicates that your software is not keeping up with the incoming data rate This bit is updated and valid for each received character 0 No FIFO overrun 1 FIFO overrun detected MOTOROLA MC68328 USER S MANUAL 12 9 97 11 13 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter FRAME ERROR Frame Error When high this read only bit indicates that the current character had a framing error missing STOP bit which indicates the possibility of corrupted data This bit is updated for each character read from the FIFO 0 Character has no framing error 1 Character has a framing error BREAK Break When high this read only bit indicates that the current character was detected as a break The DATA bits are all 0 and the STOP bit was also 0 The FRAME ERROR bit will always be set when this bit is set If odd parity is selected PARITY ERROR will also be set along with this bit This bit is updated for each character re
150. l mode Beware of outputs sourcing current for externally powered down devices When the MC68328 is powered nin sleep or doze mode the output pins remain in the state they were in before goi sleep This may cause an external device with its power turned off to try m the MC68328 output pins that are connected to it In this case itm make sure the MC68328 output pin is in the low state and that intern i Open in e excess current drain JTAG inputs are often forgotten e Inp t not being driven rail to rail consume excess current MOTOROLA MC68328 USER S MANUAL 11 10 97 16 15 For More Information On This Product Go to www freescale com On zZ 25 ox An lt oz a9 a A L ta Freescale Semiconductor Inc Applications and Design Examples 16 3 1 LCD Refresh Frequency The following sequence of steps can be used to determine the values required for the PIXCLK divider _CDC PXCD last buffer address register LBAR and octet terminal count register OTCR These registers all affect the refresh rate of the LCD panel The following example assumes a screes size of 240 x 160 1 Calculate the pixel clock divider for grayscale DIV PIX_CLK_SOURCE XMAX x 2 x YMAX x REFRESH_RATE for grayscale DIV PIX_CLK_SOURCE XMAX x YMAX x REFRESH_RATE DIV 16 58MHz 240 x 2 x 160 x 70 3 08 23 Divider must be a whole number so round to 3 Byte write 02 register to set the divider equal to 3 Notice th
151. l interrupt level 3 IRQ2 external interrupt level 2 IRQ1 external interrupt level1 The interrupt controller generates a programmable vector for each interrupt level listed above These interrupt vectors are referred to as interrupt autovecto r interrupt vectors in the 68EC000 compatible exception vector table in T 6 1 EXCEPTION VECTORS A vector number is an 8 bit number that can be mul pe ain the address of an exception vector An exception vector is the memor from which the processor fetches the address of a software routine that i i le an exception Each exception has a vector number and a exception described i in the Table 6 1 User i DragonBall and the vector numbers for user interrupts are configurable For a mation regarding exception processing see the M68000 Progra erence Manual ector Assignment VECTORS SPACE ASSIGNMENT NUMBERS e Ju rt AN ae TEN CL ee mc so ase A oe oe so ose stron 7 fs es ow so IT Ts fs foe so ten 7 Co foc so travian 7 Te fe fe om so rege ios 7 OS CN III IA a e foe so OO erea 6 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller Table 6 1 Exception Vector Assignment Continued Unassigned Reserved Unassigned Reserved Uninitialized Interrupt Vector Unassigned Reserved Spurious Interrupt 100 Level 1 Interrupt Autove
152. l low Positive polarity means that an interrupt occurs when the signal goes from logic level low to logic level high 0 Negative polarity default at reset 1 Positive polarity POL2 Polarity 2 This bit controls interrupt polarity for IRQ2 In level sensitive mode negative polarity means that an interrupt occurs when the signal is at logic level low Positive polarity means that an interrupt occurs when the signal is at logic level high In edge triggered mode negative polarity means that an interrupt occurs when the signal goes from logic level high to logic level low Positive polarity means that an interrupt occurs when the signal goes from logic level low to logic level high 0 Negative polarity default at reset 1 Positive polarity POL3 Polarity 3 This bit controls interrupt polarity for IRQ3 In level interrupt occurs when the signal is at logic lev polarity means that an interrupt occurs whe level low Positive polarity means that an inter level low to logic level high rs when the signal goes from logic 0 Negative polarity default a 1 Positive polarity POL6 Polarity 6 This bit controls interr that an interrupt occ interrupt occurs whe is at logic level high In edge triggered mode negative polarity mean E t occurs when the signal goes from logic level high to logic level low Posit O means that an interrupt occurs when the signal goes from logic ative polarity default at re
153. l purpose l O When a bit is cleared the corresponding port pin is configured as a chip select 7 5 9 Port K Registers Port K is multiplexed with signals that are related to the serial peripheral interfaces and PCMCIA Table 7 6 describes these signals Table 7 6 Port K Bit IA Tea o FUNCTION o Bo SPIN TX Pt m Jemio 2 sta sPmoio A a s aa Joss mo Ps a Y sas es fronce 7 arr rower As with other ports e peripheral interface Lf ty Bl eM we Py Wl 104 eo Bl ev GS a Ss ela oe FIELD DIR5 DIRA DIRS DIR2 DIR1 DIRO D7 D6 D5 D4 D3 D2 D1 DO RESET Oxo000 ADDR OXFFFFF440 BIT 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PU1 PUO SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO RESET Ox3F3F ADDR OXFFFFF442 7 17 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com v gt E gt m p y e a 3 7 Freescale Semiconductor Inc Parallel Ports DIR Direction 0 7 These bits control the direction of the corresponding port pin When a bit is high the corresponding port pin is an output pin and when it is low the corresponding port pin is an input pin These bits reset to O and do not affect the behavior of the pins while
154. l purpose timers pare with Programmable Mode for the Output Pins Free Run and Restart Modes The software watchdog timer has the following features e 16 Bit Counter and Reference Register e Maximum Period of 16 38 Seconds 0 25ms Resolution Timeout Causes System Reset or a Maskable Interrupt MOTOROLA MC68328 USER S MANUAL 12 9 97 10 1 For More Information On This Product Go to www freescale com TIMERS EE Freescale Semiconductor Inc Timers WATCHDOG TIMER COMPARE REGISTER INTERRUPT COMPARATOR cowpanaron OTS Reser 16 BIT COUNTER MPUBUS CLOCK PRESCALER 32KHZ CLOCK Figure 10 2 Software Watchdog Timer BI g 10 2 GENERAL PURPOSE TIMER OPERATIO The clock input to the prescaler can be selecte the corresponding timer input TIN1 or TIN2 em clock divided by 1 or 16 z or 38kHz reference clock 1 and 2 control TCTLx registers The p e programmed to divide the clock input by a value between 1 and 256 Each timer can be configured to n bit is set in the timer unit 1 and 2 status TCTLx a maskable interrupt is gener to the processor Notice that timer 1 event is a level 6 interrupt and a ti ent isa level 4 interrupt When the timer reaches the reference value the ti continues to count from value You can configure this by setting or clearing the ignal on the TOUT1 or TOUT2 pin when it reaches the reference value as the OM bit of the TCTLx This signal can be either
155. le in normal mode or on each rising edge of inverted mode SPMCLK SHIFT CLOCK This pin is the clock output When t IM bled a selectable number of clock pulses is issued While POL 0 this signal i the SPIM is idle When POL 1 this signal is high during idle 12 3 SPI MASTER REGISTE These registers control the SPIM operation and report its status The data register exchanges data with external slave devices After reset all bits are set to 0000 ntrol Status Register the SPIM operation and reports its status 11 10 9 8 7 6 5 4 3 2 1 0 SPIM SPIM IRQ DATA RATE RES RES RES EN XCH RQ EN PHA POL BIT COUNT ADDRESS FF FFF802 RESET VALUE 0000 MOTOROLA MC68328 USER S MANUAL 11 10 97 12 3 For More Information On This Product Go to www freescale com afi ce wo T Es wid ag LL am TE ane 0 Zm m qe su Qm L2 z 25 4 m gt D Freescale Semiconductor Inc Serial Peripheral Interface Master DATA RATE These bits select the baud rate of the SPMCLK based of divisions of the system clock The master clock for the SPIM is SYSCLK The bits are encoded as 000 Divide by 4 001 Divide by 8 010 Divide by 16 011 Divide by 32 100 Divide by 64 101 Divide by 128 110 Divide by 256 111 Divide by 512 SPIMEN SPI Master Enable This bit enables the SPIM The enable should be asserted befo ing an exchange and sh
156. ller will complete each data transaction of the DMA burst in one clock with the exception of the first data word transfer which occurs in two clocks as shown in Figure 8 6 When the DMA controller has filled the line buffer it negates th ernal BR signal and relinquishes the bus to the core If the core is in sleep mode srnal bus is always granted to the DMA controller which allows LCD images to be displayed while saving system power SYSCLK INTERNAL BR INTERNAL BG ADDRESS DATA y Figure 8 3 One Clock per DMA Transfer 0 Wait States MOTOROLA MC68328 USER S MANUAL 12 9 97 8 5 For More Information On This Product Go to www freescale com o wi a O o Z Q o o a QO r O i Q e pr e Fr m a Freescale Semiconductor Inc LCD Controller 8 2 2 Interfacing the LCD Controller with an LCD Panel With the following signals you can interface the LCD controller to an LCD panel 8 2 2 1 LCD DATA BUS SIGNALS The LD3 LDO signals output bus transfers pixel data to the LCD panel for display Data is arranged differently on the bus depending on the LCD data width mode selected as shown in Figure 8 3 System software can also program the output pixel data to be inverted See Section 8 6 2 LCD Polarity Configuration Register for more information The LCD data bus uses LDO to display pixel O O Some LCD panel manufact
157. mal because it can be seen by inverting the original pixels If you choose a blinking cursor the original pixels and cursor display will periodically alternate 8 2 6 Display Data Mapping The LCD controller supports 1 or 2 bit per pixel graphics mod 1 bit per pixel each bit in the display memory correspo corresponding pixel on the screen is either complet per pixel the frame rate control circuitry in the LCD controll tones on the LCD panel by adjusting the densiti maximum of four gray levels can be simultaneo The system memory data in 1 and 2 bit SD ge non grayscale mode pixel in the LCD panel The In grayscale mode 2 bit ill generate intermediate gray s over many frames A d on the LCD screen es are mapped as illustrated in 8 10 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller LCD DRIVERS 0 0 1 0 2 0 1 0 N E E Q a S 0 Y 1 1 Y 1 2 Y 1 X 1 Y 1 2 BIT PER PIXEL MODE 7 6 5 4 3 21 0 0 0 1 0 2 0 3 0 DISPLAY MAPPING X 4 Y 1 X 3 Y 1 X 2 Y 1 X 1 Y 1 SYSTEM ROM RAM BYTE ORIENTED FOR CLARITY 1 BIT PER PIXEL MODE A 4 7 6 5 4 3 2 1 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 DISPLA
158. med values can be read back You can choose whether the chip select allows read only or read write accesses whether a DTACK signal is automatically generated for the chip select the number of wait states from zero to six and data bus size selection ZA Note The chip select logic does not allow an address match during interrupt acknowledge Function Code 7 cycles 5 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chip Select Logic 5 1 1 Programmable Data Bus Size Each chip select can be configured to address an 8 or 16 bit space You can mix 16 and 8 bit contiguous address memory devices on a 16 bit data bus system If the core performs a 16 bit data transfer in an 8 bit memory space then two 8 bit cycles will occur However the address and data strobes remain asserted until the end of the second 8 bit cycle In this case only the external core data bus upper byte D 15 8 is used and the least significant bit of address A0 increments automatically from one to the next AO should be ignored in 16 bit data bus cycles even if only the upper or lower byte is being read or written For an external peripheral that only needs an 8 bit data bus interface and does not require contiguous address locations unused bytes on empty addresses use a chip select configured to a 16 bit data bus width and connect to the D 7 0 pins This lances the lo
159. n Reg E 401 Data Reg E 403 Select Reg Port B Registers E 408 Direction Reg E 409 Data Reg E 40B Select Reg Port C Registers E 410 Direction Reg E 411 Data Reg E 413 Select Reg Port D Registers E 418 Direction Reg E 419 Data Reg E 41A Pullup Enable Reg E 41C Polarity Reg E 41D IRQ Enable Reg E 41F IRO Edge Reg Port E Registers E 420 Direction Reg E 421 Data Reg E 423 Select Reg Port F Registers E 428 Direction Reg E 429 Data Reg E 42B Select Reg Port G Regis S E 430 Directio g E 431 MC68328 USER S MANUAL 11 10 97 16 7 For More Information On This Product Go to www freescale com DESIGN EXAMPLES Q z lt n z e lt 2 a a lt Freescale Semiconductor Inc Applications and Design Examples TCMP2 equ M328BASE 610 Compare Reg TCR2 equ M328BASE 612 Capture Reg TCN2 equ M328BASE 614 Counter TSTAT2 equ M328BASE 616 Status Reg Watchdog Registers WCR equ M328BASE 618 Control Reg WRR equ M328BASE 61A Reference Reg WCN equ M328BASE 61C Counter SPI Registers SPI Slave Registers SPISR equ M328BASE 700 SPIS Reg 7SPI Master Registers SPIMDATA equ M328BASE 800 Control Status Reg SPIMCONT equ M328BASE 802 Data Reg UART Registers e USTCNT equ M328BASE 900 Status Control Reg 35 UBAUD equ M328BASE 902 B
160. n the internal core and the memory peripherals or other processing elements in the external address space It consists of a 16 bit M68000 data bus interface for internal only devices and an 8 or 16 bit or mixed data bus interface to external devices 3 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture 3 3 PLL CLOCK SYNTHESIZER AND POWER CONTROL The clock synthesizer can operate with either an external crystal or an external oscillator using an internal phase locked loop PLL An external clock can also be used to directly drive the clock signal at the operational frequency You can save power on the DragonBall by turning off peripherals that are not being used reducing processor clock speed or disabling the processor altogether An interrupt at the interrupt controller logic that runs during low power mode allows you to wake up from this mode Programmable interrupt sources cause the system to wake up On chip peripherals can initiate a wake up from doze mode and the external interrupts and real time clock can wake up the core from sleep mode 3 4 INTERRUPT CONTROLLER The interrupt controller prioritizes internal and external interr vector number during the CPU interrupt acknowledge cycle In provided so that an interrupt service routine of a lower ity inte by a higher priority interrupt request The on chip interru feature
161. nal skew times All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals The MC68328 supports internal and external transfer acknowledge as well as 16 bit or 8 bit data transfer mode The diagrams in following sections illustrate the bus timing for these various modes of operation MOTOROLA MC68328 USER S MANUAL 11 10 97 17 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics 17 4 AC ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES Frequency 0 to 16 MHz GND 0 V Ta TL to TH see Figures 13 1 through 13 5 2m Table 17 1 AC Electrical Specifications Write Cycle Timing Y PARA TA Be min max E 1 CLROFighto Address Valid 2 2 Addr Valid 10 US Assened a O as 37 CLKO High to AS Asserted SSCS a a AS Assorted to US Asserted SSCS 80s PS AS Wiain Assented a A as e CSix Width Assorted AA rs 7_ CLKO High to UDS TOS Assented SSCS a as 8 DTACK Asynchronous Input Setup Time BH S o CLKO High to Address RW wai SSCS oof o ns P10 AS WidthNegated SSCS SOs Pi CLKOHightoRWVaid a YY o a2 ASHigh to RWinaid SSCS Ts 13 JAS High to CSxxNegated IO a s 14 050 Width Negated o YO pas 15 CLKOHighto OE Invalid fs 16_ CLKO Lowto AS UDS DS Negas 22 0 30 rs 18 AS UDS DS Negated to DTACK Negated 2 o es ns 19 CLKOHightoDataVaid Oo o RO 20 AS UDS LDS Negated to
162. nd Break This bit forces the transmitter to send a break character The transmitter fi es sending the character in progress if any then sends a break until this itis eset You are responsible for ensuring that this bit is high for a sufficient period of gt generate a valid break You can continue to fill the FIFO and any charac remaining will be transmitted when the break is terminated 0 Do not send break 1 Send break continuous 0 s IGNORE CTS Ignore CTS This bit when high forces the CTS pin pr effectively ignoring the external pin i general purpose input 0 Transmit only while CTS pin 1 Ignore CTS pin ode the CTS pin can serve as a sserted CTS STATUS CT This bit indicate 1 pin is high us of the CTS pin A snapshot of the pin is taken resented to the data bus When the IGNORE CTS bit is high eral purpose input CTS DELTA CTS Delta When high this bit indicates that the CTS pin has changed state and generates a maskable interrupt The current state of the CTS pin is available on the CTS STATUS bit You can generate an immediate interrupt by setting this bit high This feature is useful for software debugging The CTS interrupt is cleared by writing 0 to this bit 0 CTS pin did not change state since last cleared 1 CTS pin changed state MOTOROLA MC68328 USER S MANUAL 12 9 97 11 15 For More Information On This Product Go to www freescale com lavn
163. nductor Inc Applications and Design Examples interrupt status register ISR and the interrupt pending register IPR Among interrupt levels their priority is shown in Figure 14 5 with Level 7 being the highest Oo Note Keyboard down is the OR negative logic of all inputs on the keyboard port 16 2 4 1 METHOD FOR CLEARING INTERRUPTS Some of the interrupt sources have different clearing conventions Figure 14 6 summarizes interrupt status clearing 16 2 4 2 INTERRUPT LEVEL SUMMARY Level 7 IRQ7 Level 6 SPIS Timer 1 H oF mo ge 25 ma 4 x DPO ETA ae m aS RO6 Level 5 PENIRO Level 4 SPIM Timer 2 UART Parallel I O 8 interrupts mo WatchDog while not in Force R Real Time Clock Keyboard Down Pulse Width Modulator Level 3 IRQ3 Level 2 IRQ2 Level 1 IRQ1 16 2 4 3 INTERRUPT CLEARING SUMMARY ADDRESS BIT POSITION CLEAR BY UART block GPIO Delta ff 902 15 clear by writing zero CTS Delta ff 906 8 clear by writing zero RX FIFO Full ff 904 15 auto clears when FIFO not full RX FIFO Half ff 904 14 auto clears when FIFO less than half full RX Data Ready 904 13 auto clears when FIFO is empty TX FIFO Empty 906 15 auto clears when FIFO not empty TX FIFO Half ff 906 14 auto clears when FIFO greater than half full TX Available EE f906 13 auto clears when FIFO is full 16 12 MC68328 USER S M
164. ng a O has no effect SCR BIT 7 6 5 4 3 2 1 0 FIELD BETO WPV PRV BETEN sO DMAP RESERVED WDTHB RW RW R W RW R W RW R W R W RW RESET 0x0C ADDR Ox FF FFFO00 BETO Bus Error Time Out This status bit indicates whether or not a bus error timer h ccurred When a bus cycle is not terminated by the DTACK signal after 128 clo ave elapsed the BETO bit is set However the BETEN bit must be set for a error timeout to occur This bit is cleared by writing a 1 writing a O has no effec 0 1 A bus error timer time out did n A bus error timer time out occurs accessed or because a wri oil use an undecoded address space has been ilege violation has occurred WPV Write Protect Violation This status bit indicates that a write protect violation has occurred If a write protect violation occurs and the BETEN bit is not set the cycle will not terminate The BETEN bit must be set g a write protect violation This bit is cleared by olation indicates that If a privilege violation occurs and the BETEN bit is not set the cycle will erminate The BETEN bit must be set for a bus error exception to occur during a privilege violation This bit is cleared by writing a 1 writing a O has no effect 0 A privilege violation did not occur 1 A privilege violation has occurred BETEN Bus Error Timeout Enable This control bit enables the bus error timer O Disable the bus er
165. ng at OxFFFFFOOO f address space for their registers 4 bit and OxFFFO000 32 bit les double mapping in a 32 bit ters appear only at the top of the 4G The system control register allow interface and hardware watchdog ection handler code to investigate the caus exceptions and resets The hardware watchdog atchdog timer provide system protection The ol system operation functions like bus sists of a watchdog counter that when enabled begins to pin is asserted for internal or external bus accesses The rminates the count but if the count reaches terminal count before is asserted until AS is negated The bus error timeout logic uses one The software watchdog timer resets the DragonBall if enabled and not cleared or disabled before reaching terminal count The software watchdog timer is enabled at reset For information about timer operation see Section 8 3 Software Watchdog Timer MOTOROLA MC68328 USER S MANUAL 12 9 97 4 1 For More Information On This Product Go to www freescale com l O E z QO m E N gt 77 O O wn a Y m le rs s a 3 9 Freescale Semiconductor Inc System Control 4 1 1 System Control Register The 8 bit read write system control register SCR resides at OxFFFOOO or OXFFFFFOOO after reset The SCR cannot be accessed in user data space if the SO bit is set to 1 Writing a 1 to the status bits in this register clears them but writi
166. not affect the behavior of the pins while the SEL bits are low MOTOROLA MC68328 USER S MANUAL 12 9 97 7 13 For More Information On This Product Go to www freescale com N E a O a pa Ww par a oc lt a v gt a gt ka rc m rc v e a 4 wo Freescale Semiconductor Inc Parallel Ports D Data 0 7 These bits control or report the data on the pins When the DIR bits are high D 7 0 control the data to the pins Data can be read from or written to any bit When the DIR bits are low D 7 0 report the signal level on the pins In this case writing to a read only bit does not affect the pin Notice that the actual value on the pin is reported when a pin is read At reset all D bits default to 0 PU Pull Up 0 7 These bits enable the pull up resistors on the port When high the pull up resistors are enabled and when they are low they are disabled The pull up resistors are enabled at reset SEL Select 0 7 The select register allows you to individually select the function for ea in When you set a bit in this register the corresponding port pin is configured as a general purpose I O When a bit is cleared the corresponding port pin is configure asar dress line 7 5 7 Port G Registers Port G is multiplexed with timer and serial communi modulator real time clock and UART sections 8 bits are implemented in the registers and ports each bit can be individually configure a 32 768kHz r
167. nterrupt See Section 8 Timers for more information about timer operation 0 No timer 2 event occurred 1 Timer 2 event has occurred UART UART Interrupt Request When this bit is set it indicates that the UART module needs service This is a level 4 interrupt 0 No UART service request is pending 1 UART service is needed WDT Watchdog Timer Interrupt Request This bit indicates that a watchdog timer interrupt is pending 0 1 No watchdog timer interrupt A watchdog timer interrupt is pending oil RTC Real Time Clock Interrupt Request This bit indicates that the real time clock is requesting an interrupt 0 No real time clock interrupt 1 A real time clock interrupt i Bit 5 Reserved This bit is reserved and should remai KB Keyboard Interr gt This bit indicates wh ere is a keyboard interrupt 5 E gt ce ce wis EO o its default value 0 No pulse width modulator period rollover event occurred 1 Pulse width modulator period rolled over INTO External INTO Interrupt 0 No INTO interrupt 1 INTO interrupt is pending INT1 External INT1 Interrupt O No INT1 interrupt 1 INT1 interrrupt is pending MOTOROLA MC68328 USER S MANUAL 12 9 97 6 15 For More Information On This Product Go to www freescale com Qz o4 Zm 33 Da oc D E ra D Freescale Semiconductor Inc Interrupt Controller INT2 External INT2 Interrupt 0 No IN
168. olarity Configuration Reg 0x00 8 20 Base 0xA23 LACDRC 8 ACD M Rate Control ister 0x00 8 20 Base 0xA25 LPXCD 8 LCD Pixel Clock 0x00 8 21 Base 0xA27 LCKCON 8 0x40 8 22 Base 0xA29 LLBAR 8 LCD Last s Register Ox3E 8 23 Base 0xA2B LOTCR 8 L ount Register Ox3F 8 23 Base 0xA2D LPOSR 8 Cc Offset Register 0x00 8 24 Base 0xA31 LFRCM LCD e Sr aa Control 0xB9 8 25 Base 0xA32 LGPMR 16 LCD Gray Palette Mapping Register 0x1073 8 25 Base 0xB00 HMSR RTC Hours Minutes Seconds Register OxXXXXXXXX 9 2 Base 0xB04 2 RTC Alarm Register 0x00000000 9 4 Base 0xB0C RTC Control Register OxXX 9 5 Base 0xB0 8 RTC Interrupt Status Register 0x00 9 5 Base 0 P IEN 8 RTC Interrupt Enable Register 0x00 9 7 Base 0xB1 2 STPWCH 8 RTC Stopwatch Register 0x00 9 8 3 12 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 4 SYSTEM CONTROL The DragonBall microprocessor contains a system control register that enables the system software to customize the following functions e Access permission from the internal peripheral registers Address space of the internal peripheral registers e Bus timeout control and status bus error generator 4 1 OPERATION The on chip resources use a reserved 4 096 byte blo This block is double mapped to two locations at reset The DMAP bit in the system control registe system If you clear this bit the on chip p eral re address range starti
169. omes gener e input PK3 2 1 12 UART Pins PG0 TXD UART TRANSMIT DATA PORT G 0 This pin is the transmitter serial output While in normal mode NRZ data is output While in IrDA mode a 3 16 bit period pulse is output for each zero bit transmitted For RS 232 applications this pin must be connected to an RS 232 transmitter For infrared applications this pin can directly drive an IR LED or IR transceiver TXD signal By default after reset this pin becomes general purpose input PGO 2 7 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt m o le E v l e 2 z Freescale Semiconductor Inc Signals PG1 RXD UART RECEIVE DATA PORT G 1 This pin is the receiver serial input While in normal operation NRZ data is expected While in infrared mode a narrow pulse is expected for each zero bit received An external IR transceiver RXD signal may be connected directly to this pin RS 232 applications need an external RS 232 line receiver to convert voltage levels By default after reset this pin becomes general purpose input PG1 PMO CTS CLEAR TO SEND PORT M 0 This input controls the transmitter Normally the transmitter waits until this signal is active low before a character is transmitted If the IGNORE CTS bit is set the transmitter sends a character whenever a character is ready to transmit This pin can then be
170. ontrols test mode operations for onboard test ined by the IEEE 1149 1 standard If JTAG is not used this pin should be connecte VDD or pulled up through an external pullup resistor TDI TEST DATA IN This input is used for serial test instructio the IEEE 1149 1 standard If JTAG i pulled up through an external pu t data for internal test logic defined by is pin should be connected to VDD or TDO TEST DATA OUT This output is used for seria i ions and test data for on chip test logic defined by e left not connected or may drive the TDI pin of scan chain JTAGRST J This input is resetting the JTAG module for on chip test logic defined by the IEEE boundary scan In normal operation this pin should be connected to ICHIZ IN CIRCUIT HIGH IMPEDANCE This input may be used as a means of isolating MC68328 signals during in circuit testing When ICHIZ is asserted all of the MC68328 signal pins are high impedance When HIZ is high the MC68328 operates normally HIZ may also be asserted to accomodate in circuit test programming of external memory components such as FLASH memories 2 10 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt a m o le E v l e 2 z Freescale Semiconductor Inc Signals 2 2 PIN ASSIGNMENT The MC68328 pin assignment is shown in Figure 2 1 Mechanical specifications for the 144 pin T
171. or default at reset 6 5 5 Interrupt Status Register During the interrupt service the interrupt by examining the interrupt status register I the corresponding interrupt is poste the same level the software han application n determine the source of the interrupt ach bit in this register when set indicates re If there are multiple interrupt sources at to prioritize them depending on the he rrupt status register reflects the interrupt request from their e the specific sections about the timer SPI master SPI slave real time clock pulse width modulation for details about how to clear the i j active low edge triggered interrupt request and an IRQ7 Each interrupt status biti interrupt is cle interrupts IR 2Q3 and IRQ6 interrupts can be cleared by writing a 1 to the C 5 bit in the register When programmed as level triggered interrupts SPIM SPI Master Interrupt Request When this bit is set it indicates that a data transfer is complete You must clear this interrupt in the serial peripheral interface control register This interrupt is a level 4 interrupt 0 No SPI Master interrupt pending 1 A SPI Master interrupt is posted 6 14 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller TIMER2 Timer 2 Interrupt Request This bit indicates that a timer 2 event has occurred This is a level 4 i
172. or systems that address spaces outside of the chip select ranges DTACK must be generated externally PC5 DTACK must have an external pull up resistor if programmed for the DTACK function OE OUTPUT ENABLE This active low signal is asserted during a read cycle of the MC68328 processor which enables the output of either ROM or SRAM This signal also serves the PCMCIA 1 0 interface to indicate a read cycle 2 5 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt a m o le E v l e 2 z Freescale Semiconductor Inc Signals 2 1 7 Interrupt Control Pins PDO PD7 KB0 KB7 INTO INT7 KEYBOARD AND GENERAL PURPOSE INTERRUPT LINES Users can program these signals as interrupt inputs or parallel I O ports For an interrupt port application INTO INT7 can be configured to perform keyboard interrupt functions Keyboard interrupt pins KBO KB7 are pulled high internally and connected to the rows of the keyboard matrix with the column driven low When any one key of the row lines is pressed an interrupt is generated to signal to the CPU to scan the keys This feature together with the pen interrupt contributes a significant portion of the power management activities PM6 PENIRQ PEN INTERRUPT INPUT AND GENERAL PURPOSE Users can program this pin as a general purpose I O PM6 or pen i input When programmed as a pen interrupt si
173. otect Bit This bit protects the P and Q counter values from addi ites After this bit is set by software the frequency select register cannot be written a reset clears this bit QC Q Count These bits control the Q counter N PC P Count These bits control the P counter 15 2 PLL OPERATIO This section describes operatio d preferred sequences to control the PLL 15 2 1 Initial At initial pow stal oscillator begins oscillation within several hundred milliseconds reset remains asserted the PLL begins the lockup sequence and locks E onds of the crystal oscillator startup Once lockup occurs the system ailable at the default master frequency of 16 580608 MHz assuming a 32 768 kHz crystal To generate the master frequency multiply the reference 32 768 kHz by the PLL divisor The default divisor is 506 The divisor can be changed under software control and is outlined below Note The default divider value 506 was selected as it can directly generate standard baud frequencies at accuracies of better than 0 05 MOTOROLA MC68328 USER S MANUAL 11 10 97 15 3 For More Information On This Product Go to www freescale com l 230 OF 2 QQ Ser S ou a uy O na lt A IZ aq bu ZI 55 yr om 39 mo DA om oo jo 3o os Q Freescale Semiconductor Inc Phase Locked Loop and Power Control 15 2 2 Divider The PLL uses a dual modulus prescaler to reduce power consum
174. ould be negated after the exchange is complete This bit m written into the SPIM data register 0 SPI master disable 1 SPI master enable XCH This bit triggers the state machine to gen rate After the n bit transfer new data ma least 2 SPI clocks should elapse b transfer is completed 1 Initiate exchange N 0 SPI is idle or ex AA completion of exchange can disable the incoming SPIM interrupt by masking it in the IMR in the interrupt controller e clock count clocks at the selected bit al and another exchange initiated At ing this bit This bit remains set until the SPIMIRQ Master Interrupt Request An interrupt is asserted at the end of an exchange assuming IRQEN is enabled This bit is asserted until users clear it by writing a 0 Users can write these bits to generate an IRQ on demand This bit can also be polled with IRQEN bit clear 0 No interrupt posted 1 Interrupt posted 12 4 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Peripheral Interface Master IRQEN Interrupt Request Enable This bit will enable the SPIM interrupt This bit is cleared to 0 on reset and must be enabled by software 0 Interrupts disabled 1 Interrupts enabled PHA Phase This bit controls the SPMCLK phase shift 0 Normal phase 1 Shift advance to opposite phase POL Polarity This bit controls th
175. ption This approach divides the VCO frequency by 14 before it is fed to the rest of the divider chain Dual modulus counters operate differently from other counters in that the overall divide ratio is dependent on two separate values P and Q Besides the power saving advantage above a divisor of 225 decimal every divisor is available to fine tune the VCO in 32 kHz steps The formula for the dual modulus divider is Divisor 14 P 1 Q 1 Where 1 lt Q lt 14 P gt Q 1 Below the value of 225 some divisors are not allowed as the P relationships cannot be met 15 2 3 Normal Startup When the MC68328 processor is awakened from sleep mo achieves lock within a few milliseconds The crystal oscillat powerup so the crystal startup time is not a the PLL achieves lock y a system interrupt the PLL is always on after initial er clock starts operation after 15 2 4 Change of Frequenc To change the VCO frequency use the se ce below This fragment assumes all peripherals have been disabled an is operating at the highest possible frequency SYSCLK SEL 100 NE EQ is the new frequency value P and Q values to be programmed This routi n s Timer 2 to wake up the PLL after two CLK32 ticks ill b e new frequency The interrupt service routine for the should just clear the Timer 2 interrupt and return This code was N equ somevalue 7P and Q value of new frequency L ROL equ FFF200 PLL Control Register LFR
176. r Interrupt Request When this bit is set it indicates that a data transfer is complete You must clear this interrupt in the serial peripheral interface control register This interrupt is a level 4 interrupt 0 No SPI Master interrupt pending 1 A SPI Master interrupt is posted MOTOROLA MC68328 USER S MANUAL 12 9 97 6 17 For More Information On This Product Go to www freescale com 5 E gt ce cr wis e o Qz o4 Zm 33 Da oc D ra D Freescale Semiconductor Inc Interrupt Controller TIMER2 Timer 2 Interrupt Request This bit indicates that a timer 2 event has occurred This is a level 4 interrupt See Section 8 Timers for more information about timer operation 0 No timer 2 event occurred 1 Timer 2 event has occurred UART UART Interrupt Request When this bit is set it indicates that the UART module needs service This is a level 4 interrupt 0 No UART service request is pending 1 UART service is needed WDT Watchdog Timer Interrupt Request This bit indicates that a watchdog timer interrupt is pending 0 y No watchdog timer interrupt A watchdog timer interrupt is pending ol RTC Real Time Clock Interrupt Request This bit indicates that the real time clock is esting an interrupt 0 No real time clock interrupt 1 A real time clock interrupt i Bit 5 Reserved This bit is reserved and should remai KB Keyboard Interr NS This bit indicates wh
177. r or disabled in the port D INT enable register The remaining interrupt i of these eight interrupt signals and the result is the keyboard KB i e interrupt controller The KB interrupt can also be enable or masked in the inte trol module te Edge protect circuitry on port D uses the system clock Therefore edge interrupts cannot generate wake up interrupts when the chip is in sleep or doze mode 7 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Ports 7 4 DEFAULT PORT CONFIGURATIONS At reset or when the RESET signal is asserted the DragonBall ports default to their reset configurations You should examine the default value for each port carefully and if necessary reconfigure the port according to the requirements of your application Table 7 1 contains the default port configurations N p a O a pa Ww par a oc lt a Table 7 1 Reset Default Port Assignments PORT DEFAULT PORT I O DEFAULT PORT DEFAULT NAME RESET TYPE RESET STATE RESET PULL UP FUNCTION STATUS A w f mw c VO nput o me N N PA7 A23 PA6 A22 PA5 A21 PA4 A20 PA3 A19 PA2 A18 PA1 A17 PAO A16 PB7 D7 PB6 D6 PB5 D5 PB4 D4 PB3 D3 PB2 D2 PB1 D1 PB0 DO gt gt N N N gjo R RZ 2Z 2z B plo e N oa n olo M U oO E 2 C o Co E Co o O Basic I O Output High Basic I O Input Exte
178. re low pins configured as input D 7 0 report the signal level on the pins The D bits may be read or written at any time If a pin is configured as input only a write to the corresponding bit in this register does not affect the pin These bits reset to 0 SEL Select 0 7 The select register allows you to individually select the function set a bit in this register the corresponding port pin is configure When a bit is clear the corresponding port pin is configured as a reset all bits in the select register are cleared h port pin When you eneral purpose l O ss line A 16 23 At 7 5 2 Port B Registers Port B is multiplexed with data lines D7 DO On pins In an 8 bit only system these pins can b sequence must configure port B as TO o He Bee 128 511 5108 9 Ble G EN ANa 2 a oO FIELD DIR7 DIR6 DIRS DIR4 NN FDIRO D7 pe D5 D4 D3 D2 Dt Do RESET 0x0000 ADDR OxFFFFF408 ta lines are connected to the s general I O In this case the boot up rt is not affected by the BUSW pin D BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Ne 0 0 0 0 0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO RESET 0x0000 ADDR OxFFFFF40A DIR Direction 0 7 These bits control the direction of the corresponding port pins When a bit is high the correspon
179. reference clock down to 1 pulse per second An alternate reference frequency of 38 4kHz is also supported The real time clock hours minutes seconds RTCHMS register consists of three groups of bits that track the current time in hours minutes and seconds in a 24 hour format The seconds and minutes counters are 6 bits long and the hours counter is 5 bits long The prescaler stages are tapped to support several features Periodic interrupts at 1Hz or 1 second and 1 minute as well as the midnight rollover interrupt are supported 9 2 2 Alarm You can set an alarm interrupt by setting the HOURS MINU ECONDS fields in the RTC alarm RTCALRM register An interrupt is enabled w A N bit in the RTC interrupt enable register RTCIENR is set An interrupt i ste en the current time matches the time in the RTCALRM register 9 2 3 Minute Stopwatch one minute resolution It generates an The minute stopwatch performs a countdown wit interrupt when the programmable length of ti i utes expires For example to save power you can use the minute stopwatch n off the LCD display after a minute of idle At consecutive minute increments in pwatch value is decremented The interrupt is generated when the NY to 1 at any ti fter a write the current time assumes the newly written values Unused bits read 0 9 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor
180. reset all data bits default to 0 PU Pull Up 0 7 These bits enable the pull up resistors on the port When high t enabled and when they are low they are disabled The port E B after reset ll up resistors are o resistor is enabled SEL Select 0 7 The select register allows you to individually select t set a bit in this register the corresponding port pin i When a bit is cleared the corresponding po n for each port pin When you igured as a general purpose I O ed as a chip select signal 7 5 6 Port F Registers Port F is multiplexed with address li you can decide which of these a can serve as parallel I O pins Depending on the system s specification use outside the chip Unused address pins BIT i eS ie ae a 10 9 8 7 6 5 4 3 2 1 0 FIELD DIR7 DIR6 Dl DIR2 DIR1 DIRO D7 D6 D5 D4 D3 D2 Di DO RESET 0x0000 ADDR OXFFFFF428 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PU1 PUO SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO RESET OXFFFF ADDR OXFFFFF42A DIR Direction 0 7 These bits control the direction of the corresponding port pin When a bit is high the corresponding port pin is an output pin and when it is low the corresponding port pin is an input pin These bits reset to O and do
181. rnal Pull up Require A Basic 1 O Input External Pull up Require D QS h PC4 IRQ g z 4 y Ap El Ee PC3 gt PC1 UDS UDS Basic I O PD7 KB7 PD7 Interrupt I O Input Interrupt Internal Pull up Disabled E PD6 KB6 Interrupt I O Input Interrupt Internal Pull up Disabled En MOTOROLA MC68328 USER S MANUAL 12 9 97 7 5 N N N N n A A JA A d E d 7 A A A A abled abled For More Information On This Product Go to www freescale com v gt E gt m p y e a 3 7 Parallel Ports Freescale Semiconductor Inc PORT NAME PD5 KB5 PD4 KB4 PD3 KB3 PD2 KB2 PD1 KB1 PDO KBO PE7 CSB3 O PE6 CSB2 A PE5 CSB1 A PE4 CSB q a PE3 CSA3 O PE1 CSA1 PF7 A31 a ra v m w O gt to 7 6 Table 7 1 Reset Default Port Assignments Continued DEFAULT RESET FUNCTION PDS PD4 PD3 PD2 PD1 CSA1 HANA lt OA PF5 IN a S P P P F PF F PF 3 2 4 0 7 PG MC68328 USER S MANUAL 12 9 97 TYPE Eo p I O LV Pull up I O Pull up I O Pull up I O Pull up I O Pull up I O Pull up I O Pull up I O Pull up I O Pull up I O DEFAULT PORT RESET STATE Input Interrupt isabled b Input Interrupt PBisab ed a Input Interrupt PDisab ed Input Interrupt PBisab ed p Input Interrupt PBisab ed d Input Interrupt PD
182. ror timer 1 Enable the bus error timer 4 2 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Control SO Supervisor Only This control bit limits on chip registers to supervisor accesses only 0 User and supervisor mode 1 Supervisor only mode DMAP Double Map This control bit controls the double mapping function 0 The on chip registers are mapped at OxFFFFFOOO OxFFFFFFFF 1 The on chip registers are mapped at 0xxxFFF000 0xxxFFFFF Bit 1 Reserved This bit is reserved and reads 0 WDTH8 8 Bit Width Select This control bit allows the D 7 0 pins to be used for portB input ut 0 Not an 8 bit system 1 8 bit system l O E z fo m E N gt 77 O MOTOROLA MC68328 USER S MANUAL 12 9 97 4 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Control O wn a Y m le 2 Es a 3 9 4 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 5 CHIP SELECT LOGIC The DragonBall microprocessor contains 16 general purpose programmable chip select signals which are arranged in four groups of four Among them there ar special purpose chip select signals CSA0 and CSD3 The CSAO signal i signals are
183. s e Prioritized interrupts Fully nested interrupt environment N e Programmable vector generation Unique vector number generat interrupt level e Interrupt masking Wake up interrupt masking and generates a esting is also pt may be suspended r has the following 3 5 PARALLEL AL PURPOSE I O PORTS i 7 general purpose I O ports that you can configure as general purpose o edicated peripheral interface pins Each pin can be independent 2d as a general purpose I O pin even when other pins related to that on heral are used as dedicated pins If all the pins for a particular peripheral are co as general purpose I O the peripheral will still operate normally 3 6 TIME The software watchdog timer protects against system failures by providing a way for you to escape from unexpected input conditions external events or programming errors Once started the software watchdog timer must be cleared by software on a regular basis so that it never reaches its time out value When it does reach its time out value the watchdog timer assumes that a system failure has occurred and the software watchdog logic resets or interrupts the core MOTOROLA MC68328 USER S MANUAL 12 9 97 3 7 For More Information On This Product Go to www freescale com ARCHITECTURE O Freescale Semiconductor Inc Architecture 3 7 LCD CONTROLLER The LCD controller is used to display data on an LCD module lt fetches display data
184. s parallel I O pins After reset port A ults to the address function There are three configurable registers that ct the behavior of each pin in this port the select register direction register and data re r The corresponding bits in these registers correspond to each port pin E MA A e FIELD DIR7 IAS DIRA DIRS DIR2 DIR DIRO D7 D6 D5 D4 D3 D2 D1 Do RESET 0x0000 ADDR OxFFFFF400 an a ae eo ee ee ee ea es esa FIELD 0 0 0 o0 o o o o SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SELO RESET 0x0000 ADDR OxFFFFF402 MOTOROLA MC68328 USER S MANUAL 12 9 97 7 7 For More Information On This Product Go to www freescale com N E a Oo a pe Ww a oc lt a v gt E gt m p y e D 3 mn Freescale Semiconductor Inc Parallel Ports DIR Direction 0 7 These bits control the direction of the corresponding port pins When a bit is high the corresponding port pin is an output pin and while it is low the corresponding port pin is an input pin These bits are reset to 0 and have no effect on the pins while the SEL bits are low D Data 0 7 These bits control or report the data on the pins when the corresponding SEL bits are high If the DIR bits are high pins configured as output D 7 0 control the data to the pins When the DIR bits a
185. s disabled To maintain reliable edges on CLKO it is e lO MOTOROLA MC68328 USER S MANUAL 11 10 97 15 9 For More Information On This Product Go to www freescale com l 39 S 2 QQ Ser o ow a we na lt A IZ aq Freescale Semiconductor Inc SECTION 16 APPLICATIONS AND DESIGN EXAMPLES This section discusses the details of a simple M68328 processor base system which will illustrate the simplicity of the system hardware design and glueless interf memory and peripheral devices when using the M68328 processor The 8 bit and 16 bit memory is also demonstrated This system consists e M68328 16 58MHz using 32 768kHz crystal e 512K boot EPROM x 1 8 bit interface e 2M general purpose EPROM 16 bit interface Y e 512K SRAM 8 bit interface 2M general purpose SRAM 16 bit interfac 16 1 MEMORY MAP The M68328 processor can support up to 4 ess space This example uses an address space under 16M for simplicity N 00000 003FFFFF 2 5MB SRAM CSB0 CSB1 CSB2 400000 007FFFFF EMB EPROM CSAO CSA1 CSA2 on zu GE wn Z x ER w oz a9 aw ow lt A 00800000 00BFFFFF PCMCIA 1 0 CARD 4MB SPACE UNUSED 00FFF000 00FFFFFF 68328 INTERNAL REGISTERS Figure 16 1 Memory Map MOTOROLA MC68328 USER S MANUAL 11 10 97 16 1 For More Information On This Product Go to www freescale com oF mo ge 25 ma 5 x DO ETA ae m aS Fr
186. s not affect the eported when a pin is read Bits that are ead 1 when an edge is detected The interrupt Note Port D edge interrupts cannot generate wake up events when the chip is in sleep mode POL Polarity 0 7 These bits select the input signal polarity When the bits are high the input data is inverted before it is presented to the holding register and when the bits are low the data is presented as is Interrupts are active high or rising edge while these bits are low Interrupts are active low or falling edge while these bits are high MOTOROLA MC68328 USER S MANUAL 12 9 97 7 11 For More Information On This Product Go to www freescale com N E a Oo a pan Ww a oc lt a v gt E gt m p y e a 3 7 Freescale Semiconductor Inc Parallel Ports IQEN Inerrupt Enable 0 7 These bits allow the individual interrupts to be presented to the interrupt controller block These bits when high enable INT 7 0 interrupt generation When the bits are low INT 7 0 interrupt generation is disabled IQEG Edge Enable 0 7 These bits when high enable edge triggered interrupts When the bits are low level sensitive interrupts are selected The polarity of the edge rising or falling is selected by the POL bits 7 5 5 Port E Registers Port E is multiplexed with seven chip select signals that are describ table below Table 7 3 Port E Bit Function PORT ce oe A
187. s the power controller by a negation of this bit The user s interrupt service routine must reenable this bit to reenter power save operation This bit resets to zero In association with the width bits this bit acts as a throttle from doze to CPU active 1 Power control enabled 0 Power control disabled MOTOROLA MC68328 USER S MANUAL 11 10 97 15 7 For More Information On This Product Go to www freescale com 2u 2x o gt Zm zo mo DA om Qu So 30 os o Freescale Semiconductor Inc Phase Locked Loop and Power Control STOP This bit immediately enters the power save mode without waiting for the power controller to cycle through a complete burst period This bit disables the CPU clock after the bus cycle that follows the next CLK32 rising edge When the system is to enter the doze mode this bit is set On the next burst period or interrupt the clock will restart for its allotted period This bit is reset to zero and is cleared on wake up events 1 Stop CPU clock enter doze mode 0 Normal CPU clock bursts WIDTH Width of CPU clock bursts These bits reset to 11111 1F 00000 0 31 duty cycle 00001 1 31 duty cycle 00010 2 31 duty cycle 11111 31 31 duty cycle increments While the WIDTH ursted to the CPU at a duty cycle of ways on While the WIDTH is zero the CPU should be disabled for extended These bits control the width of the CPU clock bu is 1 and the power controller is enabled
188. set itive polarity 7 Note Clear your interrupts after you change modes When you change modes from level to edge interrupts an edge can be created which causes an interrupt to be posted ET1 IRQ1 Edge Trigger Select When this bit is set the IRQ1 signal is an edge triggered interrupt In edge triggered mode you must write a 1 to the IRQ1 bit in the interrupt status register to clear this interrupt When MOTOROLA MC68328 USER S MANUAL 12 9 97 6 7 For More Information On This Product Go to www freescale com 5 E gt ce cr ws fe Zo Qz o4 Zm 33 Da oc D E ra D Freescale Semiconductor Inc Interrupt Controller this bit is low IRQ1 is a level sensitive interrupt In this case you must clear the external source of the interrupt 0 Level sensitive interrupt default at reset 1 Edge sensitive interrupt ET2 RQ2 Edge Trigger Select When this bit is set the IRQ2 signal is an edge triggered interrupt In edge triggered mode you must write a 1 to the IRQ2 bit in the interrupt status register to clear this interrupt When this bit is low IRQ2 is a level sensitive interrupt In this case you must clear the external source of the interrupt O Level sensitive interrupt default at reset 1 Edge sensitive interrupt ET3 IRQ3 Edge Trigger Select When this bit is set the IRQ3 signal is an edge triggered interrupt In edge triggered mode you must write a 1 to the IRQ3 bit
189. sor to interface with external master devices for example FLEX paging decoder The interface is a 3 wire system consisting of the clock enable and data input pins It is compatible with SPls that are popular on Motorola s 6 icrocomputer chips ver a serial link unting 8 clock cycles the process Figure The SPI transfers data to the MC68328 processor from a perip A clock controlled by the external device controls trans fter the shift register data moves to a read buffer generating 13 1 is a block diagram of the slave SPI hd MPUINTERFACE QA SPSCLK SPSEN Mo 3 SHIFTREGISTER D SPI Block Diagram POL 0 PHA 1 SPSCLK POL 0 PHA 0 SPSCLK SPSEN SPSRXD 87 86 85 84 83 B2 B1 BO Figure 13 2 SPI Slave Operation MOTOROLA MC68328 USER S MANUAL 11 10 97 13 1 For More Information On This Product Go to www freescale com a wi c 3 ao uo ag Zu gi TE nZ 0 zZ a8 m SE 2u Om ma ee gt m lt n m gt Freescale Semiconductor Inc Serial Peripheral Interface Slave 13 1 OPERATION Users first initialize the SPI slave SPIS program register The SPIS then waits for the input enable SPSEN and clock SPSCLK to control the data transfer The shift register fills with data over the next 8 clock cycles On the eighth clock the shift register contents loads into the data buffer The SPISIRQ bit is set po
190. splay follow these steps 1 Turn on the LCD controller by setting the LCDON bit 2 Delay 1 2ms 3 Turn on the VLCD by programming the I O pin to turn on the external transistor 8 14 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LCD Controller 8 3 SYSTEM MEMORY CONTROL REGISTERS 8 3 1 LCD Screen Starting Address Register You should program the LCD screen starting address LSSA register with the 32 bit screen starting address of the LCD panel Notice that only the upper 31 bits of this register are programmable Bit O is always 0 so that starting address is always at an even address The LCD DMA controller transfers pixel data from system memory beginning at the address pointer stored in this register This register points to the data word containing the first pixel on the screen LSSA BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Md FIELD SSA31 SSA30 SSA29 SSA28 SSA27 SSA26 SSA25 SSA24 SSA23 SSA22 1 SS SSA19 SSA18 SSA17 SSA16 R W RW RW RW RW RW RW RW RW RW RW R RW R W RW R W BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA5 SSA4 SSA3 SSA2 SSA1 0 FIELD ssai5 SSA14 SSA13 SSA12 SSA11 SSA10 SSA9 R W R W RW R W R W RW RW RW R W RW RW R W R W R W RESE
191. sting an interrupt The valid data in the buffer awaits the service routine access The clock input performs shifts depending on phase and polarity In phase 0 mode PHA 0 serial data are strobed on the leading edges of SPSCLK In phase 1 mode PHA 1 data are strobed in on trailing edges The polarity POL specifies the inactive state value of SPSCLK While POL 1 the idle state of the SPSCLK is high While POL 0 the idle state of the SPSCLK is low This flexibility allows operation with most seri i the market data byte from an external master the SPIS interrupt is poste em is in sleep e system clock The SPIS bit bit 21 in the wakeup control register IWR at loc FFF308 must be set for the wakeup sequence to occur 13 2 SIGNAL DESCRIPTIONS SPSRXD This pin is the serial data input to th edge of SPSCLK while in normal polarity inverted mode POL 1 4 Refer to Section 7 1 10 for more r Anew bit is shifted in on each leading ron each trailing edge of SPSCLK in is multiplexed with other signals to port K bit SPSCLK This pin is the shift SPSEN This pin indic transfer is in progress After the enable becomes active the SPIS sta Cc responds to clock edges for data transfer 13 3 S LAVE REGISTER This register controls the SPIS operation and reports its status The data register contains the data transmitted by the external master After reset all bits are set to 0000 13 2 MC68328 USER S MANUA
192. t pin is used as an output onding bit in the data register will output a 1 and clearing the bit will special purpose function For example while the port K Bit 0 of the select register is cleared this pin is the output master serial peripheral interface TXD signal In this case Data to Module signal in Figure 7 1 is connected to the master serial peripheral interface TXD signal Since this bit is output only the Output Enable from module signal is always asserted and the Data to module signal is not used Another example is that the port K Bit 1 can be used as the master serial peripheral interface RXD input only signal In this case the Output Enable from module input is negated and the Data from module signal is not used The Data to module signal is connected to the master serial peripheral interface RXD input Figure 7 1 illustrates the internal logic of each basic port MOTOROLA MC68328 USER S MANUAL 12 9 97 7 1 For More Information On This Product Go to www freescale com N E a O a pa Ww par a oc a v gt E gt m p y e D 3 mn Freescale Semiconductor Inc Parallel Ports Note To preventa glitch write the intended data to the data register before you change the mode in the select register from unselected 0 to selected 1 DATA TO MODULE DATA DIRECTION SEL gt Operation DATA FROM MODULE MPU BUS OUTPUT ENABLE FROM MODULE
193. terrupt from waking up the processor 1 Enable pulse width modulator interrupt to wake up the processor default at reset 6 12 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller INTO Wake up External INTO 0 Disallow INTO interrupt from waking up the processor 1 Enable INTO interrupt to wake up the processor default at reset INT1 Wake up External INT1 0 Disallow INT1 interrupt from waking up the processor 1 Enable INT1 interrupt to wake up the processor default at reset INT2 Wake up External INT2 0 Disallow INT2 interrupt from waking up the processor 1 Enable INT2 interrupt to wake up the processor default at rese INT3 Wake up External INT3 0 Disallow INT3 interrupt from waking up the processor 1 Enable INT3 interrupt to wake up the processor de t INT4 Wake up External INT4 0 Disallow INT4 interrupt from waking up the 1 Enable INT4 interrupt to wake up the proce roc default at reset INT5 Wake up External INT5 0 Disallow INT5 interrupt to wake 1 Enable INT5 interrupt to wake u ssor default at reset 5 E gt ce ce wis EOS o INT6 Wake up External INT6 0 Disallow INT6 interrupt fr i 1 Enable INT6 interrupt to wake u m waking up the processor wake up the processor default at reset p the processor he processor
194. the SEL bits are low D Data 0 7 These bits control or report the data on the pins When the DIR bits are high D 7 0 control the data to the pins Data can be read from or written to any bit While the DIR bits are low D 7 0 report the signal level on the pins In this case writing to a read only bit does not affect the pin Notice that the actual value on the pin is reported when a pin is read At reset all data bits default to 0 PU Pull Up 0 7 These bits enable the pull up resistors on the port When hig freg p resistors are enabled and when they are low they are disabled SEL Select 0 7 The select register allows you to individually select t set a bit in this register the corresponding port pin i When a bit is clear the corresponding port pi n for each port pin When you igured as a general purpose l O as a peripheral interface 7 5 10 Port M Registers Port M is multiplexed with signals th elated to the interrupts and UART Each bit has a selectable pull up resistor that NS o it Table 7 7 describes these signals able 7 7 Port M Bit Functions TO PORT OTHER FUNCTION FUNCTION NACI INICIA INICIAN me S ro o ae 0 PEN IRQ 7 Bit 7 UART GPIO As with other ports each pin can be individually configured as needed Notice that Pin 7 is a dedicated pin for use as a UART GPIO and cannot be used as a general purpose IO pin 7 18 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product
195. the cou value matches the value in this register an interrupt is posted and the counter rt another period 15 14 13 5 4 3 2 1 0 12 11 10 9 o N RESET VALUE 0000 PERIOD Period This is the value that resets the r There is one special case when this register is 00 the output is never set high 0 duty cycle ADDRESS FF FFF504 RESET VALUE 0000 WIDTH Width When the counter reaches the value in this register the output is reset 14 4 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pulse Width Modulator 14 1 4 Counter This read only register is the current count value and can be read at any time without disturbing the counter COUNT ADDRESS S EF FFFSOS RESET VALUE 0000 COUNT Count This is the current count value x faa Be u5 36 gt oF MOTOROLA MC68328 USER S MANUAL 11 10 97 14 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 15 PHASE LOCKED LOOP AND POWER CONTROL The PLL is a flexible clock source for the MC68328 It provide clock at frequencies from 13 MHz to the maximum operationa in 32 KHz steps Sth of the master provides an efficient power control mechanism for t 3328 processor see Figure 3 1 below l 230 OF 2 QQ Ser S ou a uy O na Qa zs ac
196. to cap t SPIM operation The hardware con The SPIM data should be reloaded h time before initiating the SPIM control register exchange bit Although the exa does not use interrupt service the polling routine ter SPIM to capture data from an evice can be directly connected to the ble signal to the A D converter This example rom the A D converter and illustrates the ion is shown in Figure 16 8 MOTOROLA MC68328 USER S MANUAL 11 10 97 16 13 For More Information On This Product Go to www freescale com DESIGN EXAMPLES Q z lt n z e lt 2 a a lt Freescale Semiconductor Inc Applications and Design Examples should poll the IRQ bit for an indication of a completed transfer Do not poll the exchange bit for exchange completion Program SPI Baud rate phase polarity SPM_EN int enabl le transfer count Program port PK7 SELECT DIRECTION OUTPUT DATA 1 Put the channel num Put the A D channel number to the A D Initiate the Exchange Toggle PK7 set bit 8 in the SPIM register mx _ Poll the SPIM inte gt SPIM control register b y Yes oF mo ge 25 ma 5 x DO ETA ae m aS Data read receive data clear interrupt flag QS lear port PK7 OUTPUT DATA 0 ure 16 7 SPIM Data Capture Flowchart PK7 ltl cs ANALOG MC145050 SPMCLKP E SCLK AD CONV VOLTAGE MC68328 AN SPMRXD a DOUT lt SPMTXD 92
197. u So 30 os o Freescale Semiconductor Inc Phase Locked Loop and Power Control the screen refreshed The following sections describe the use and operation of the power control block CPU BUS REQUE CPU BUS GRAN BURST WIDTH CONTROL CLK68K controller is disable he MC68EC000 clock is continuously on When the block is enabled s begins to burst In normal operation the MC68EC000 does not have to operate Usually it waits for user input An interrupt from the keyboard for example disables the power controller and the clock again becomes continuous When the software completes its service of the task the power controller can again be enabled to burst the clock and reduce power consumption Clock control is in increments of approximately 3 1 31 When the burst width control sub block indicates that the CPU clock s time slot has expired and is to be disabled clock control requests the bus from the CPU After the bus is granted the clock stops Bus grant to the DMA controller is asserted and the DMA controller has complete access to the bus If a wakeup interrupt event occurs while the CPU clock is disabled the clock is immediately enabled and the CPU processes the interrupt The DMA 15 6 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Phase Locked Loop and Power Control controller always has priority so if
198. uct Go to www freescale com rc O o Q e zZ pu as e md m a Freescale Semiconductor Inc LCD Controller 8 6 2 LCD Polarity Configuration Register The LCD polarity configuration LPOLCF register is used to configure the polarity of the panel interface signals and the data bus LPOLCF BIT 7 6 5 4 3 2 1 0 FIELD LCKPOL FLMPOL LPPOL PIXPOL RW RW RW R W RW R W RESET 0x00 ADDR Ox FF FFFA21 LCKPOL LCD Shift Clock Polarity This bit controls the polarity of the LCD shift clock active edge 0 Active negative edge of LCLK 1 Active positive edge of LCLK FLMPOL First Line Marker Polarity This bit indicates the first line marker polari N 0 Active high 1 Active low LPPOL Line Pulse Polarity N This bit indicates the line polarity 0 Active high 1 Active lo The LCKPOL FLMPOL and LPPOL bits require an LCD controller off on sequence before any changes will occur PIXPOL Polarity This bit indicates pixel polarity 0 Active high 1 Active low 8 6 3 LACD Rate Control Register The LACD signal will toggle once every 1 to 16 FLM cycles based on the value specified in the LACD rate control register LACDRC The actual number of FLM cycles is the value 8 20 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com r O o Q e zZ pr e Fr m a
199. uct Go to www freescale com Freescale Semiconductor Inc LCD Controller toggle on every frame The LACD output signal is synchronized with the trailing or falling edge of the line pulse LP enclosed by FLM Table 8 1 ACDRC Value and Number of Frames LACDRC NUMBER OF FRAMES 8 2 3 LCD Panel Interface Timing The LCD controller continuously transfers pixe bus The LCD bus is timed by the LSCLK LLP a the pixel data into the display drivers internal shift shifted pixel data into a wide latch at the f line of the displayed page CD panel via the LCD data nals The LSCLK signal clocks ister The LLP signal latches the e while the LFLM signal marks the first The LCD controller is designed to t monochrome LCD panels Figure 8 4 illustrates the LCD interface timing for 4 2 and 1 bit LCD data bus operations The line pulse signifies the end of the current line of serial data The LLP signal enclosed by the LFLM signal marks the end of the first line of the current frame Some LCD panels might use an active low LFLM signal and reversed pixel data To change the polarity of these signals LPPOL SCLKPOL and PIXPOL bits to 1 The LLP and LFLM signals for all panel modes that the LCD controller supports MOTOROLA MC68328 USER S MANUAL 12 9 97 8 7 For More Information On This Product Go to www freescale com e W al pa e E E z Q O a o p QO Freescale Semiconductor Inc
200. universal asynchronous receiver transmitter UART allows serial communication with external devices such as modems and other computers Data is er rted in character blocks at data rates ranging from 300bps to over 500Kbps using an start stop format 11 1 FEATURES The following list contains the main features of the e Full Duplex Operation Flexible 5 Wire Serial Interface Direct Support of IrDA Physical Laye Robust Receiver Data Sampling with 8 Byte FIFOs for Transmit and R e 7 and 8 Bit Operation with Optional Generation and Bre ction Baud Rate Gener The UART performs all normal operations associated with start stop asynchronous communication Serial data is transmitted and received at standard bit rates using the internal baud rate generator For those applications that need other bit rates a 1x clock mode is available in which you provide the data bit clock Figure 11 1 shows a high level block diagram of the UART module MOTOROLA MC68328 USER S MANUAL 12 9 97 11 1 For More Information On This Product Go to www freescale com lavn Freescale Semiconductor Inc Universal Asynchronous Receiver Transmitter RX miS RXD A RECEIVER lt H lt ES XD w gt u ign T lt O Zaz lt E 5 5 gt IX E E 5 FIFO TRANSMITTER z lt gt GPIO gt m CTS D _ BAUDGEN 3 RTS BA
201. urers specify their LCD panel data bus in which data bit 3 of the panel displays pixel 0 0 For these panels connections from the DragonBall s LD bus to the LCD panel data b significance LD3 connects to panel data 0 LD2 to panel data 1 LDO to panel data 3 can program the LFLM signal to be active high 8 2 2 3 LINE PULSE SIGNAL The LP si panel It becomes active when a ling ix asserted for a duration of eight pi either active high or active low S ecti for details 8 2 2 4 LCD SHIFT CKS The LSCLK signal is the clock output that is synchronized to the L nel output data Your system software can program the LSCLK i ithe i active low See Section 8 6 2 LCD Polarity Configuration iods You can program the LP signal to be n 8 6 2 LCD Polarity Configuration Register ernate the crystal polarization of the panel This provides an AC polarity change crystal degradation of the LCD panel caused by DC voltage Your system program this signal to toggle at a 1 to 16 frame period The alternate crystal direction LACD or M pin will toggle after the preprogrammed number of FLM pulses Your system software can also program the ACD rate control register LACDRC so that LACD will toggle once every 1 16 frames The targeted number of frames is equal to the alternate code s 4 bit value plus one The default value for LACDRC is zero which means LACD will 8 6 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Prod
202. used as a is ready to receive data transmitter s CTS pin When the receiver detects a pending overrun it negates t pin can be a general purpose output controlled by t ti programmed as parallel I O it becomes PM1 general purpose input PM1 e receiver register When it is reset this pin becomes PM7 GPIO UART GENERAL PURPO This pin provides several functions f and a master clock for the baud ge UART GPIO an provide a bit clock input or output By default after reset this pin becomes 2 1 13 Timer Pins PG6 TIN1I TIMER This bidirectional pi ic By default after reset this pin becomes general purpose input PG4 T MER 2 INPUT PORT G 4 This bidirectional signal can be programmed as a clock input that causes events to occur in timer counter channel 2 either causing a clock to the event counter or providing a trigger to the timer value capture logic By default after reset this pin becomes general purpose input PG4 PG5 TOUT1 TIMER 1 OUTPUT PORT G 5 This bidirectional signal can be programmed to toggle or generate a pulse of one system clock duration when timer counter channel 1 reaches a reference value By default after reset this pin becomes general purpose input PG5 2 8 MC68328 USER S MANUAL 11 6 97 MOTOROLA For More Information On This Product Go to www freescale com 2 D z gt 2 m o le E v l e 2 z Freescale Semiconductor Inc Signals
203. ut Setup Time to CLKO Low AS UDS LDS Negated to Data High Impedance AS UDS LDS Negated to Data Invalid n e lt gt poj gt O 4 m D YN oO gn n 3 3 3 3 3 3 njijujjuja n a 4 6 8 9 17 4 MC68328 USER S MANUAL 11 10 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics SO S 2 S3 4 5 S6 7 Q Sl LLNS ee y gt lt s Aod ol gt ko w gt ma C LKO N e E Qn am z ToO Ex ga w no l gt e 20 gt gt A D15 DO yl j lt a Figure 17 2 Chip Select Read Cycle Timing when the CPU is the Bus Master MOTOROLA MC68328 USER S MANUAL 11 10 97 17 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical Characteristics Table 17 3 AC Electrical Specifications LCD DMA Read Cycle Timing ae CHARACTERISTIC 1 CLKO High to Address Valid CLKO High to CSxx Asserted Data Input Setup Time to CLKO High CSxx Width Asserted AS Negated to CSxx Asserted 6 RAW High to CSxx Asserted AS High to CSxx Negated 8 CSxx Width Negated 9 OE Asserted to CSxx Asserted DMAC Address Hold Time CSxx Negated to AS Asserted CLKO High to CSxx Negated CSxx Negated to OE R W Inval
204. ution to execute the interrupt service routine Interrupt priority is based on the interrupt level If the CPU is currently processing an interrupt service routine and a higher priority interrupt is posted the process described above repeats and the higher priority interrupt is serviced If the priority of the newer interrupt is lower than or equal to the priority of the current interrupt execution of the current interrupt handler continues This newer interrupt is postponed until its priority becomes the highest Interrupts within a same level should be prioritized in software by the interrupt 6 4 MC68328 USER S MANUAL 12 9 97 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Controller handler The interrupt service routine should end with the rte instruction which restores the processing state prior to the interrupt The DragonBall provides one interrupt vector for each of the seven user interrupt levels These interrupt vectors form the user interrupt vector section of Table 6 1 The user interrupt vectors can be located anywhere within the address range 0x100 to 0x400 You can program the five most significant bits of the interrupt vector number but the lower three bits reflect the interrupt level that is being serviced All interrupts are maskable by the interrupt controller If an interrupt is masked its status can still be accessed in the interrupt pending regist
205. ve you satisfactory results when used with most LCD panels Ho you do add a value it should be odd and not even LFRCM BIT 7 6 5 4 3 2 1 0 FIELD XMOD3 XMODO 4 YMOD3 YMODO R W R W R W RESET ADDR omar 1 XMODX and YMODX Frame n Control These bits modulate adjacent pixe when using frame rate con targeted LCD panel Se ues must be optimized by manually fine tuning the Gray Palette Mapping for details 8 8 2 LCD Gr pping Register The LCD gray p g register LGPMR is used to map the 2 bit grayscale value to its gray palet LGPMR 2 BIT 15 lolo aii Gis 4 6 2 x 0 FIELD gt GLEVEL1 GLEVELO GLEVEL2 GLEVEL3 i R W R W R W R W R W 2 RESET 0x0173 8 ADDR Ox FF FFFA32 8 O GLEVELx Grayscale Level 0 3 These bits represent the gray palette code bit position n 0 1 2 output for pixel input data m 0 for pixel data 00 1 01 2 10 3 11 This 3 bit code will then select one of seven bitstreams of different densities See Section 8 2 8 Gray Palette Mapping for details MOTOROLA MC68328 USER S MANUAL 12 9 97 8 25 For More Information On This Product Go to www freescale com rc O o Q e zZ pu as e md m a Freescale Semiconductor Inc LCD Controller For example 2 BIT GRAYSCALE VALUE LEVEL LOG GRAY LINEAR IN MEMORY LEVEL GRAY LEVEL 0019 CIT 8 9

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