Am186CC Microcontroller Power Management Circuit Application
Contents
1. XOR in vec voc voc 11k 11k 11k 11k HOOK SW d if a G 5 ENABLE 4MHz Schmitt Trigger R DE Q a AND onhk SCH K K ig d Grit pn E oi pn E or S sl Souk CLK vog d ot d g ai ai 4 H is 11 S 2 VC VC NOR 4MHz A S faa comer Se A3 zo e oz ENABLE 32KHz HK ZOUT vec 2 B J enD woe AND ak SH MHz ed 3 Ge iN ge Ek 7 NOR 32kHz 5 out en Fars Ze vcc enD S E 2 32 7KHz Oscil NOR 24MHz Serves as ar f vec s NOR pwrgood vec 11K POWERGOOD 100K o J Schmitt Trigger 0 1 uF Ge RESET gt XORZ ENABLE 24 MHz EN ouT vec anD voc 24 MHz Oscil 11K HLDA CLKSEL1 Cz t 11K PCS4 CLKSEL2 gt Figure 5 Power Management Circuit Schematic OM AMDO MEASUREMENTS Test Conditions The PMC is tested with an Am186CC microcontroller reference design ISDN TA board All devices not applicable to the test were removed from the board leaving the CPU DRAM Flash memory and a UART for loading code Because the board is not designed with power management in mind it utilizes 5 V DRAM and Flash memory devices even though the Am186CC microcontroller is a 3 3 V device The ISDN TA board uses 5 V memory devices with a 3 3 V microcontroller to accommodate the S T controller for the ISDN TA appl2. CPU runs to perform its task efficiently and effectively Ensuring that devices not in use are shut down or in power saving mode and configuring PIOs to their most power efficient state are essential to power management Software also plays an important part in power management The core of the design can be used for a variety of specifications For the purpose of example and reference we emulated the Am186CC microcontroller PMC used in an ISDN TA with a telephone hand set This application includes three different power requirements E A normal power consuming stage occurs when power to the ISDN TA is available at the remote location the house or business where the phone is Copyright 1999 Advanced Micro Devices Inc All rights reserved located in which there is no real power saving requirement E A medium power saving stage occurs when there is no power available from the terminal adapter TA remote location and a call is being placed or received In this medium power stage the ISDN TA receives 450 mW of power from its central office WR A low power stage occurs when no power is avail able from the ISDN TA remote location and no call is being attempted or received In this case the ISDN TA only receives 25 mW of power from its cen tral office entering a very low power saving mode Figure 1 and Figure 2 on page 2 illustrate the contents of the design The power to the ISDN TA is monitored by the Frequency Select bl
3. HLDA CLKSEL1 and PCS4 CLKSEL2 of the Am186CC microcontroller to configure the PLL to 2x mode when the signal is POWERGOOD or to PLL Bypass mode when the sig nal is POWER NOTGOOD Am186 CC Microcontroller Power Management Circuit Application Note 5 SON UOL edI ddy n3119 JUBWAHeUeYWY JAMO J9JJOAJUOIOIOIN DOwi9SLwiy PULSE SAFTEY 41k HOOK SW ENABLE 4MHz Schmitt Trigger FREQUENCY OUTPUT CONTROL AND onhk vee el T Jm our s ENABLE 34 KHz D E a A GND VCC AND offhk 4 MHz Oscil L NOR 32KHz OUT EN vec L 8 vcc anp H 32 7KHz Oscil NOR 24MHz When input 1 to a NOR gate is RESET that particular frequency is selected voc NOR pwrgood es as an INVERTER 11K POWERGOOD o of Schmitt Trigger RESET f ENABLE 24 MHz EN OUT vec 4 GND wee 24 MHz Oscil PLL CONFIGURATION HLDA CLKSEL1 C gt PCS4 CLKSEL2 Figure 4 Power Management Circuit Schematic In Sections OM 9 ON uonesiddy n3119 JUBWAaHeUeW JAMO J9 O1 UODOIIIW DOwi9SLwy
4. appropriate frequency when needed Software plays a key role in managing the Am186CC microcontroller by monitoring the frequency at which the system is running to determine when to take additional power saving measures such as configuring the PlOs putting peripheral devices in Low or Shutdown mode and even putting the Am186CC microcontroller in Halt mode when necessary The PMC combined with good software methodology provides good power management for the Am186CC microcontroller enabling it to meet many stringent power requirements AMD the AMD logo and combinations thereof and Am186 are trademarks of Advanced Micro Devices Inc Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies Disclaimer The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifi cations and product descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intel lectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including
5. but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice 10 Am186 CC Microcontroller Power Management Circuit Application Note
6. putting the UART transceiver in Shutdown mode This condition is caused by the DRAM s increased power consumption which is caused by the code language and the typical requirement that DRAM needs to be constantly refreshed The code in Row 3 is identical to the code in Row 2 ex cept the UART transceiver is not put in Shutdown mode and only two HDLCs are running The total in crease in total system current draw reflects the UART transceiver running and indicates that the HDLCs do not draw a significant amount of current 8 Am186 CC Microconiroller Power Management Circuit Application Note Power Management Measurements Table 3 contains the power measurement values taken with the PMC attached to the Am186CC and using code that monitors the power input to the system and manages the power consumption according to the different stage needs The system running at 48 MHz indicates that full power is being supplied to the simulated TA therefore no power management is required The total current consumption is higher than the total current consumption of the Code 3 values in Table 1 because of the additional current draw of the PMC The system running at 4 MHz indicates that the TA is not receiving power from the remote location and is re ceiving limited power from the phone company through the phone line for an incoming or outgoing call This causes the PMC to enable the 4 MHz oscillator This triggers the PM code disabling addres
7. Am186 CC Microcontroller Power Management Circuit Application Note by Gino Davis and Douglas Paulson AM This application note describes the power use design cosiderations and functions of the Am186 CC microcontroller power management circuit PMC INTRODUCTION Devices that operate efficiently at high speeds and low voltages are essential for producing successful products This is achieved by innovative designs improved fab processes better materials and power management Power management plays an important role in the power efficiency of a device to help it meet stringent system power requirements and increased mobile power supply longevity Therefore the Am186CC microcontroller is combined with a power management circuit capable of providing substantial power savings The Am186CC microcontroller power management cir cuit PMC is modeled from and integrates the system management principles of power supervision compli ance to the standard to which you are designing and efficiency Supervising power and its requirements and assuring power is being used in the most efficient way are simple and effective methods of power manage ment design Because the CPU s power use is directly related to the frequency at which the CPU is running managing the operating frequency of the CPU is a major consider ation in power consumption management The stage or present task required by the CPU determines at which frequency the
8. D10 AD11 AD12 AD13 AD14 AD15 INTO INTI INT2 INT3 INT4 INT5 INT6 PIO19 INT PIO7 NMI DRQO P1O9 DRQ1 ARDY PIO8 SRDY PIO35 HOLD TMRIN1 PICO CLKOUT UGLK USBSOF USBSCI P1021 UCS ONCE USBX1 INT PWD PIO6 HLDA CLKSEL1 TMROUTO P1028 TMRINO P1027 TMROUTI PIO RES RESOUT LCS RASO MCSo UCSX8 PIO4 MCS1 CAS1 MCS2 CASO 759 MCS3 RAS1 PIOS PCS0 USBSEL1 PIO13 PCS1 USBSEL2 PIO14 PCS2 PCS3 PCS4 CLKSEL2 PIO3 PCS5 TESTMODE PIO2 PCS6 PIO32 PCS7 PIO31 RD WR PRODTST P1015 WLB WHB ALE P1033 DT R PIO29 DEN DS PIO30 CLKSEL2 BHE ADEN PIO34 SO USBXCVR Si S2 S6 Am186CC BSIZES Qso Controller asi RXDA DDA RXDA TXDA DUA TXDA RCLKA DCLA CLKA TCLKA FSCA FSCA CTSA TSCA PIO17 RTRA P1018 RXDB RXDB PIO36 TXDB TXDB P1037 RCLKB CLKB PIO40 TCLKB FSCB P1041 CTSB TSCB PIO38 RTRB PIO39 RXDC RXDC P1042 TXDC TXDC P1043 RCLKC CLKC P1022 TCLKC FSCC P1023 CTSC TSCC PIO44 RTRC P1045 RXDU RXDD RXDD P1026 TXDU TXDD TXDD P1020 CTSU TCLKD FSCD P1024 RTRU RCLKD CLKD PIO25 RXDHU PIO16 TXDHU CTSHU CTSD TSCD PIO46 RTRHU RTRD P1047 SDEN P1010 SCLK PIO11 SDATA P1012 USBD UDMNS USBD UDPLS RSRVD1 UXVRCV RSR
9. MENT KEY POINTS Although the PMC is designed for a simulated TA application with three different power requirements the circuit is easily tailored for other specifications and or applications For example if your application only required two different power modes utilizing a 25 MHz frequency at 2x PLL mode and a 12 MHz frequency in PLL Bypass mode the following are some of the major PMC modifications for these specifications M Replace the 24 MHz oscillator with the 25 MHz crystal E Remove the AND offhk the 32 KHz enable flip flop the 32 KHz oscillator and the NOR 32 KHz gate mM Remove the two Pulse Safety flip flops This is optional Because the frequency is not switched on the fly the two Pulse Safety flip flops are not required E Replace the 4 MHz oscillator with the 12 MHz oscil lator E Tie the Q output of the 12 MHz flip flop to the A input of the NOR 4 MHz gate which is now called the NOR 12 MHz gate mM Remove the XOR in gate and tie the output of NOR 12 MHz gate to the A input of XOR out gate Table 3 Power Management Measurements foruspeeD vec voca DRAM FLASH TRANS POR OTHER TOTAL Ceme o sa e ve 7 124 2575 Came ne or we ma 82 m ms Derez 175 os oam au ta ora 46 Notes 1 All values are in mA unless otherwise specified 2 The code for generating the measurements in this table can be found in the Am186 CC Microcontroller Powe
10. ON This section provides a more detailed description of how the circuit operates Although this reference is designed for a TA application with three separate power requirement modes the core of the design can be applied to a wide range of applications Figure 4 on page 6 shows the sections of the Am186CC PMC schematics Figure 5 on page 7 shows the entire Am186CC PMC schematics without boxes around each section Frequency Select WR When NOR pwrgood gate inputs are High 4 MHz and 32 KHz enabling flip flops are cleared disabling the 4 MHz and 32 KHz oscilla tor regardless of the HOOK SW position Enabling the active High 24 MHz oscillator and driving a Low signal to input 1 of the NOR 24 MHz gate outputs the 24 MHz frequency to X1 WR When NOR pwrgood gate inputs are Low 24 MHZ oscillator is disabled MHz and 32 KHz flip flops are active and fre quency selection is determined by the input to the respective AND gate which comes from the HOOK SW position When OFF HOOK Input 1 to the AND onhk gate is Low disabling the 4 MHz oscillator Inputs 1 and 2 to AND offhk are High which enables the 32 KHz oscillator and sends a Low signal to the NOR 32 KHz gate which outputs the 32 KHz frequency to X1 When ON HOOK Input 1 to the AND offhk gate is Low disabling the 32 KHz oscillator Inputs 1 and 2 to the AND onhk gate are High which enables the 4 MHz oscillator and sends a Low signal to NO
11. R 4 MHz gate which outputs a 4 MHz frequency to X1 Pulse Safety The PMC design requires changing between 4 MHz and 32 KHz frequencies on the fly without resetting the processor The two flip flops in series ensure that when alternating from 4 MHz to 32 KHz frequencies the Am186CC microcontroller continues to receive full pulses When alternating from 32 KHz to 4 MHz fre quencies short pulses are not a major concern because the 32 KHz frequency periods are long The Am186CC microcontroller must be in the PLL Bypass mode when alternating between frequencies The Am186CC microcontroller must receive a full pulse sig nal short or runt pulses violate the Am186CC microcontroller timing specification 4 Am186 CC Microcontroller Power Management Circuit Application Note Frequency Output Control Three NOR gates control the frequency output to X1 Whenever input 1 to NOR 32 KHz NOR 4 MHz or NOR 24 MHz is Low the respective gate outputs the frequency on its input pin 2 Two or more of these NOR gates never have a Low signal on pin 1 at the same time WR 24 MHz Output When pin 1 of the NOR 24 MHz gate is Low the 24 MHz frequency is driven on pin 2 of this gate outputting this frequency to pin 2 of the XOR out gate Meanwhile the NOR 4 MHz and 32 KHz gates are driving out High signals to both the XOR in gate pins which in turn drives out a Low signal to pin 1 of XOR out With pin 1 of the XOR out gate low the XOR out gate outp
12. VD2 UXVEN RSRVD3 UTXDMNS C gt UART LOWPOWER m OFF ON HOOK RSRVD4 UTXDPLS Figure 3 Am186CC Microcontroller Signals Used With Power Management Circuit e POWERGOOD HOM AMDO Table 1 Signal Descriptions gg Description o Configure PLL The two pins are used to configure the PLL to its various modes The PLL can also be configured to 4x and CLKSEL1 1x modes but the 4x and 1x modes are not applicable in this reference CLKSEL2 e When CLKSEL1 and CLKSEL2 are both Low the PLL is configured to Bypass mode e When CLKSEL1 and CLKSEL2 are both High the PLL is configured to 2x mode For more information about CLKSEL1 and CLKSEL2 refer to the Am186 CC CH CU Microcontrollers User s Manual order 21914B HOOK SW Functions as a telephone receiver that is on or off the hook OSCILLATOR IN Inputs one of three oscillator frequencies from the power management circuit to the Am186CC microcontroller POWERGOOD Functions as main power to the TA RESET Resets the Am186CC microcontroller when the POWERGOOD signal is initiated to either the POWERGOOD or POWER NOTGOOD state TCLKA Drives the HDLC transmitter and is connected to and controlled by PIO1 UART LOWPOWER P1022 is used to put the UART s transceiver into shutdown mode when in the power managed state vcc Power is supplied to the TA at its remote location general power to the entire application CIRCUIT OPERATI
13. ed OFF HOOK High ON HOOK Low 1 Disables previous running oscillator 1 Disables previous running oscillator 2 Enables 4 MHz oscillator 2 Enables 32 7 KHz oscillator Figure 1 System Power Management Clocking Timing Flow Chart POWERGOOD Functions as main power to the terminal adapter TA E POWERGOOD logic level High Power is available at the TA remote location WR POWER NOTGOOD logic level Low Power is not available at the TA remote location functioning as a power failure HOOK SW Functions as a receiver on the TA being off or on hook WR ON HOOK logic level Low No outgoing or incoming call is being attempted E OFF HOOK logic level High Either an outgoing or incoming call is being attempted Off Hook On Hook Frequency Pulse ___ Select P Control Frequency d Output gt x Control Power To System Reset e Y C gt RESET PLL Configure l gt CLKSEL1 C gt CLKSEL2 Figure 2 Power Management Circuit Block Diagram 2 Am186 CC Microcontroller Power Management Circuit Application Note oyN uonesiddy n3119 JUBWAaHeUeW JAMO J9 O1 UODOIIIW DOwi9SLwy OSCILLATOR IN CLKSEL1 Ut X1 X2 USBX2 AO Al A2 e7 AS A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 ADO AD1 AD2 AD3 AD4 ADS AD6 AD7 AD8 AD9 A
14. eme msa as oma 125 2000 _ a eme ne as ss we ne ass Note All values are in mA unless otherwise specified Row 1 contains measurements taken with code that is designed to keep the CPU busy simulating maximum use of the Am186CC microcontroller All four HDLC channels are in loopback at 1 8 clock speed All three timers are running one timer drives the TCLK pin of all four HDLC channels the two other timers are in a con tinuous loop but their outputs are not driving any PIO pins The High Speed UART is continuously busy while all unused PIOs are set up as inputs The code is writ ten in assembly language and is designed to run from Flash memory and not DRAM Although the VCC in row 1 in Table 2 is the highest value of the three VCC values the TOTAL value in row 1 is the lowest value of the three TOTAL values This condition is caused by running the code from the Flash instead of the DRAM which saves power Row 2 contains code that puts the UART transceiver in Shutdown mode runs four HDLCs uses one timer to drive the HDLCs transmit clock and runs one timer constantly while the third timer is off The code also accesses the S T interface and synchronous serial interface SSI to simulate a terminal adapter application This version of code is written in C language and runs out of DRAM which shows a significant increase in total system power draw even though nearly 20 mA is eliminated by
15. ications Anyone interested in designing a power management system and or application with the Am186CC microcontroller should use CMOS 3 3 V memory to utilize power more efficiently Although the ISDN TA board is not designed for this particular application it provides a platform for demonstrating and testing the PMC General Power Measurements It is important to note that all of the power measurements derived from these test conditions and documented in this application note show what to expect when following the guidelines described in this document However you can obtain better power efficiency than that described in this application note by using better power efficient parts and practicing good programming methodology Table 2 contains a sample of a test measurements taken under various conditions to establish expected baseline current draw values Power Measurement Descriptions VCC Am186CC microcontroller digital current draw VCCA Am186CC microcontroller analog current draw DRAM 5 V high performance CMOS dynamic RAM FLASH 5 V CMOS Flash memory TRANS 5 V RS232 transceiver OTHER Other parts on the board such as the system crystal and the 3 3 V LDO that collectively consume measurable current draw PM CIR The total current draw of the PMC in Table 3 only TOTAL The total current draw of the entire board Table 2 General Power Measurements cove cuspe vec voca DRAM FLASH TRANS OTHER TOTAL 2
16. ock using simple logic and software The power is also used to determine when the Am186CC microcontroller is reset and to configure the PLL of the Am186CC microcontroller The HOOK signal and the receiver ON HOOK OFF HOOK switch is also monitored by the Frequency Select block for determining the appropriate frequency for the different stages The Pulse Control block ensures that the Am186CC microcontroller does not receive any short or runt pulses while switching frequencies on the fly in the PLL Bypass mode In addition the Frequency Output Control block ensures that only one frequency outputs to the Am186CC microcontroller Although there are other methods of providing the various frequencies to the CPU this design uses three different oscillators with different frequency speeds to accommodate the application requirements Also the switches for the POWERGOOD and HOOK SW circuit shown in Figure 3 on page 3 are used for simulating inputs to the circuit and the switches are not needed for functionality of the circuit Figure 3 on page 3 and Table 1 on page 4 describe the Am186CC microcontroller signals used by the applica tion node Publication 23111 Rev A Amendment 0 Issue Date November 1999 AMD POWERGOOD POWERGOOD High POWER NOTGOOD Low r Enable 24 MHz oscillator 1 Reset board Reset board 2 Configure PLL to BYPASS mode Configure PLL to 2X mode Hook SW is Don t Care 3 Power Management code enabl
17. r Management Codekit Software V1 0 May 18 1999 Am186 CC Microcontroller Power Management Circuit Application Note 9 AMD Again this is just an example of how the circuit can be made to accommodate different system requirements Proper termination of unused PIO pins are important in achieving low power Because most PIOs have alternate functions and some have either internal pullups internal pulldowns or Schmitt Trigger Inputs it is important to consult the Am186 CC CH CU Microcontroller User s Manual order 21914 for proper termination of unused PIOs Running your code from the most efficient memory possible is also a contributing factor to power management As indicated by the measurements in Table 1 the TOTAL measurement is low although Row 1 shows the VCC is drawing more current indicating that the CPU is working harder because the code is being executed out of Flash memory which is the more efficient memory in this case When there is no activity in the system executing the HALT command which puts the system in Halt mode is recommended Depending on the particular system design putting the processor in Halt mode can save the total system power as much as 20 Trademarks SUMMARY Power managing the Am186CC microcontroller depends largely on managing the system speed frequency as efficiently as possible The PMC is designed to handle most of this for you by monitoring key signals and switching to the
18. s multiplexing on the data bus putting the UART transceiver in Shutdown mode configuring unused PIOs as high impedance in puts and transmitting the HDLC in low power mode The 32 7 KHz measurements result from no power being supplied from the remote location and no incom ing or outgoing call being attempted The PMC enables the 32 7 KHz oscillator and the PM code Then the PMC puts the Am186CC microcontroller in Halt mode and periodically brings the microcontroller out of Halt mode to check for incoming or outgoing calls The fluc tuating current in DRAM is caused by the CPU going in and out of Halt mode thus having fluctuating current in the TOTAL measurement Although not evident the VCC current also varies but in the pA range which is not apparent in the VCC measurement Typical currents being very low are measured to be approximately 2 5 3 0 WA MHz This low lec rate not only enables low power consumption but also contributes to a low EMI signature This current rate is AMDO based on measurements taken under the test conditions described in Table 3 The current rate is a typical representation of what customers can see in their application designs NOTE This measurement only applies when the microcontroller is run at higher frequencies e g 4 MHz and above At lower frequencies this measurement tends to increase due to an Lk constant that is always present but less apparent at higher frequencies POWER MANAGE
19. uts the frequency generated on its pin 2 to X1 E 4 MHz Output When pin 1 of the NOR 4MHz gate is Low the 4 MHz frequency is being driven on pin 2 of this gate outputting this frequency to pin 1 of the XOR in gate Meanwhile the NOR 32 KHz gate is driving out a Low signal to pin 2 of the XOR in gate With pin 2 of the XOR in gate Low the fre quency generated on pin 1 is outputted to input pin 1 of the XOR out gate while the NOR 24 MHz gate is driving a Low signal to pin 2 the of XOR out gate With pin 2 of the XOR out gate Low the XOR out gate outputs the frequency generated on its input pin 1 to X1 AMDO E 32 KHz Output When pin 1 of the NOR 32 KHz gate is Low the 32 KHz frequency is being driven on pin 2 of this gate outputting this frequency to pin 2 of the XOR in gate Meanwhile the NOR 4 MHz gate is driving out a Low signal to pin 1 of the XOR in gate With pin 1 of the XOR in gate Low the fre quency being generated on pin 2 is being outputted to input pin 1 of the XOR out gate while the NOR 24 MHz gate is driving a Low signal to pin 2 the of XOR out gate With pin 2 of the XOR out gate Low the XOR out gate outputs the frequency generated on its input pin 1 to X1 Reset XOR reset is used for generating a reset to the Am186CC microcontroller with the initiation of a POWERGOOD or a POWER NOTGOOD signal AND reset is used for an initial board power up reset PLL Configuration These two outputs are connected to
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