DP7120 20A DC-DC Intelligent dPOL Data Sheet 8V to 14V Input
Contents
1. 100 4 r 10096 l 95 90 90 S 80 3996 Vo 0 7V o Vo 0 7V O g0 3 3 E CUM Vo 1 2V Q ves o oz o 70 Vo 1 2V 75 Vo 1 8V Vo 1 8V dz 70 SM 60 j s 6 5 1905 d Vo 2 5V 5096 Vo 3 3V 60 i Vo 3 3V B 5596 4 4 L 4 Vo 5 5V 4 0 5 0 0 5 10 1h 20 25 8 9 10 11 12 13 14 Load Amps IBV Volts Figure 11 Effciency vs Load Vinz12V Fswz1MHz Figure 13 Efficiency vs Vin Fsw 1MHz 9596 9 90 4 8 85 7 o gt 80 6 o s Vo 0 7V E Vo 0 7V o 7596 4 5 Vo 1 2V za Vo 1 2V a 70 o 4 5 Kos Vo 1 8V EM Vo 1 8V 1 Vo 2 5V an Vo 2 5V s Vo 3 3V V0 73 3V 5096 4 0 d 1 t T 0 5 10 15 20 25 0 5 10 15 20 25 Load Amps Load Amps Figure 12 Efficiency vs Load Vinz8V Fswz1MHz Figure 14 Dissipation vs Load Vinz12V Fsw 1MHz WT BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 11 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output AN PUWEI HE WP C hanging the Shape of Power T Programmable Features Performance parameters of DP7120 dPOL converters can be programmed via the industry standard IC communication bus Each parameter has a default value stored in the volatile memory registers detailed in Table 1 The setup2. 5 10 Load Amps 15 20 25 Figure 6 Efficiency vs Load Vin 8V Fsw 500KHz Efficiency 500KHz 1MHz Vout Volts Figure 7 Efficiency vs Vout at Vin 12V Load 20A BCD 00259 Rev 1 0 12 Feb 2013 www power one com Efficiency 95 90 o2 cn oO o Co S ES Vin 12V l cm oO ES 4 6596 4 1 2 3 4 5 6 Vout V Figure 8 Efficiency vs Output Voltage lout 7A Fsw 500kHz Efficiency P diss Watts NM Ww 4 un c eo O 10096 4 95 1 M Vo 1 2V 7596 4 7096 poo o n 1 V01 BV 65 4 L Vo 2 5V 60 Vo 3 3V 55 7 Vo 5 5V 50 8 9 10 11 12 13 14 IBV Volts Figure 9 Efficiency vs Vin Fsw 500kHz Vo 0 7V Vo 1 2V Vo 1 8V Vo 2 5V Vo 3 3V 5 10 15 20 25 Load Amps Figure 10 Power Dissipation Vin 12V Fsw 500KHz WT Page 10 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN POWET ONE S Changing the Shape of Power
3. 35 osvo v wo onem AS fros v mes resas I AED O w wwo t m wx Mwwmumabww ime sosonvoo 39 mw O cesa manoa s 9 Ww muss Patapeurentsouce tov o3 30 m omm mmmemm m m Aen m meam m 7 AES Inputs ADDRO ADDRA EN IM ViL x ViH x Vhyst x 0 3 x VDD VDD 0 5 0 3 x VDD V V V LOW level input voltage 0 7 x VDD 0 1 x VDD HIGH level input voltage Hysteresis of input Schmitt trigger External pull down resistance ADDRX forced low Power Good and OK Inputs Outputs 25 175 10 kOhm Oi RdnL ADDR lup PG lup OK ViL x ViH x Vhyst x gt Pull up current source input forced low PG U 725 0 3 x VDD VDD 0 5 0 3 x VDD Pull up current source input forced low OK T gt LOW level input voltage 0 7 x VDD 0 1 x VDD HIGH level input voltage lt Hysteresis of input Schmitt trigger loL LOW level sink current at 0 5V Current Share Bus CS pin ho 3 E Oi lup CS ViL CS Pull up current source at VCS OV 0 84 LOW level input voltage 0 3 x VDD V ViH_CS HIGH level input voltage RA VDD 0 5 Vhyst_CS Hysteresis of input Schmitt trigger Reda IEEE o WO Oi s gt BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 7 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN PUWEI HE VIC hanging the Shape of Power 5 Pin Assignments and Desc
4. r a 30 Controls A OnOff Controls Group v System r a 50 Margining Low Nom High Groups GroupB Gop O Group D Front End Send Cmd r a g0 Cmd Figure 57 Example Overtemp Fault Ingection in the GUI In Figure 57 we see the effects of injecting an Overtemp OT fault Note that dPOL 0 shows an OT fault dPOL 0 and 1 are in the same Group and fault propagation for the dPOL is to propagate to the group dPOL 4 and above are in Groups B and C Propagation is not enabled from Group A to B The OT fault shows up as an orange indicator in the dPOL and RUN status LEDs Group LEDs show yellow indicating all of the members of the group have shut down Fault recovery depends whether the fault is a latching or non latching fault A non latching fault is cleared by unchecking the checkbox clears the fault trigger The dPOL will re BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com start after the 130ms time out of non latching faults hiccup time Group and System follows restart Latching faults clear in one of two ways The first method is to clear the fault trigger uncheck the checkbox note the dPOL remains off since the fault is latching Alternately a latched fault can be cleared by toggling the EN pin or by commanding the dPOL to turn off and turn off again via the GUI interface obviously more convenient Therefore once the fault trigger is cleare
5. Duration of each voltage step is calculated by dividing the master clock frequency generated by the DPM Since all dPOLs in the system are synchronized to the master clock the matching of voltage slew rates of different outputs is very accurate as it can be seen in Figure 25 and Figure 30 TC Tracking Configuration Address 0x03 R W 0 R W 0 RW 1 RW 1 RW 1 RIW 0 R W 0 TI m R Ro se e O T Fo Bit 7 Bit 0 Bit 7 Unimplemented read as 0 Bit6 4 R 2 0 Vo rising slew rate 0 0 05 V ms default when in bus terminator mode 1 0 1 V ms default 2 0 2 V ms 3 0 25 V ms 4 0 5 V ms 5 1 0 V ms 6 2 0 V ms 7 Reserved Bit 3 SC Turn off slew rate control 0 disabled 1 enabled default Bit 2 0 F 2 0 Vo falling slew rate 0 0 05 V ms 1 0 1 V ms 2 0 2 Vims 3 0 25 V ms default when in bus terminator mode 4 0 5 V ms default 5 1 0 V ms 6 2 0 V ms 7 Reserved Figure 24 Tracking Configuration Register TC During the turn on process a dPOL not only delivers current required by the load lLoap but also charges the load capacitance The charging current can be determined from the equation below BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com dV lene Croan X dt Where Cioap is load capacitance dVp dt is rising voltage slew rate and lcua is charging current When selecting the rising slew rate a user needs to ensure that lioan lcua loce
6. fft Home l quee l e 3 gi 120 Bus Caniue Device __zm7316 EM 7316 oe 2 75 Group A Type Bus Voltages Devices Faults User Memon a OO DP 115 Gop ABCD Right click table to modify displayed parameters or select E di Preferences Q amp 0 DP7115 Auotn MPs Q M Audievd PMorier AAR Parameter Pal 00 Pol 01 Pol 02 Pol 3 Pal 04 Group B Shono AME Parallel Bu Addi n Ui m 03 04 o DP7DI5 Dru dus Mame DP7115 DP7115 DP7UI5 POOF AuDev a Ein Ej Alias DP7115 DP7l15 DP70UI5 DP7007 AuDev H m Vendor Power ne Power ne PowerOne PowerOne gt Group C Poll Package Size 222x12 222412 222412 222x12 03 DP7007 jn NHEM Output Vokage e 35V 235v 1 85 V 1 52v m Curent Limit 188A 1884 1384 3 2 m Load Regulation mV A 165 mV A mV A OD AA Margining High 5x 5X 5t 55 Margining Low EX 6 7 x Under Voltage Tak 75 75 75x Power Good Low 90x 3n 90 30 Power Good Hig 110 1105 110 110 Over oltage 130 130 1x 130 Tuma Delay 2 ms 20 ms Ome 20 ms Tune Delay 15 ms 15 ms 13 ms 11ms Rising Slew Rates 020V ms 020 V ms O20 V ms Q0 20 V ms Faing Slew Aae 5 V ms 0 50V ms 50 V ms 050 v ms Zeral Zero Polel Pale Poles Pull Frequency 500 kHz 500 kHz 0 a Command Log Honitoring step on O4 Sep Z0le z 41 z8 Honitaring step on 4 3ep zD0lz 41 3 Honito ring ep an 4 S3ep 2D0l2 02 41
7. DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POWET ONne VJ C hanging the Shape of Power approximately the same level the dominant or master dPOL will tend to carry slightly more of the load than the others In addition to the CS interconnection the DPM must be informed of the sharing configuration This is done in the DPM Configure Devices window shown in Figure 55 Just to the right of each dPOL address set the spin control to one of 10 possible sharing busses the number is an accounting aid for firmware The GUI automatically copies common parameters changed in one dPOL s setup information into all dPOLs connected to the parallel bus Some parameters such as load sharing must be set independently 7 9 1 CS and Regulation Load Regulation is an important part of setting up two or more dPOLs to share load The dPOL designated the master should have a lower Load Regulation setting than the other dPOL s connected to its sharing bus In operation the negative CS duty cycle in each dPOL is proportional to the unit s load current As the loading goes up the negative period gets wider A dPOL which sees CS duty greater than its internally calculated value will increase its output voltage to increase its load share Non zero regulation on the other hand tends to lower output voltage as loading increases It also tends to retard the calculated CS period The effect
8. PHS 1 0 Phase selection 0 Single phase PWMO 1 Dual phase PWMO and PWM2 2 Triple phase PWMO PWM1 and PWM2 3 Quad phase PWMO PWM1 PWM2 and PMW3 Bit 5 FRQ PWM frequency selection 0 500 kHz default 1 1000 kHz Bit 4 Unimplemented Read as 0 Bit3 0 INT 3 0 PWM interleave phase with respect to SD line 0x00 0 phase lag 0x01 22 5 phase lag 0x02 45 phase lag 0x1 F 337 5 phase lag Figure 46 Interleave Configuration Register INT 7 7 3 Interleave and Input Bus Noise When a dPOL turns on its high side switch there is an inrush of current If no interleave is programmed inrush current spikes from all dPOLs in the system reflect back into the input source at the same time added together as shown in Figure 47 BCD 00259 Rev 1 0 12 Feb 2013 www power one com Tek Stop ____ 4 ________ TA 0120mV i o l i 22 0mV ERES QUT DLE li ee er sede Ere ES TA 1 00us EUN f i je 296ns a 14 i Ch4 Pk Pk NNNM co RRB 0 2 52 4mv P NE 11 3mV j Bj 37 80 Figure 47 Input Voltage Noise No Interleave Figure 48 hows the input voltage noise of the three output system with programmed interleave Instead of all three dPOLs switching at the same time as in the previous example the switching cycle of dPOLs V1 V2 and V3 start at 67 5 180 and 303 75 of phase delay respectively Noise is spread evenly across the switching cycle resulting in more than 1 5 times re
9. Rising Slew Rates are V1 1V ms V2 0 5V ms V3 0 2V ms Tek Run e c J Trig v J Chl High Maret puce MER Ee ee ae Um s ve warmers ww ied i id i ied 4 Ch2 High H 1 850 Y Ch3 High 1520V CRT eee led i HY TST PE SOS TOO EAN AS TEAN E TPP SO OS TO OPS COR SOE OES TE SOO E TER OE A A TE S EEC SOE AE Om Se Rr NRI TE 1 Chi 500mV BL SY 5300mV CTR 00ms A chi f 220mV WEE 500mv 5 12 00 Figure 27 Sequenced Turn On Rising Slew Rate is Programmed at 1V ms V2 Delay is 2ms V3 delay is 4ms Tek Run Ch1 High 2 050 V Ch2 High 1 850 V Ch3 High 1 520 V S00mV Ch2 s00mv M4 00ms A Chl Soomv Ch3 S00mV amp i i3 60 20 Figure 28 Two outputs delayed 5ms All slew rates at 0 5V ms BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com 7 3 3 Pre Bias In some applications power may leak from a powered circuit to an unpowered bus typically through ESD protection diodes The dPWER controller in the dPOL holds off turn on its output until the desired ramp up point crosses the pre bias point as seen in Figure 29 Tek Run Trig Ch1 High 2 050 V Ch2 High 1 850 V Ch3 High 1 520 V 1 assbrasabissebasssisssstecnstasnMannMnnMenaPresabrsssbnsssbesssrsssabesssnanedton ma toon Cha soomv AMA ooms A Chl Soomv Ch3 500mV 5 Figure
10. of these two actions regulation and CS tracking cause the dPOL or dPOLS with higher regulation values to track the loading of the dPOL with a lower regulation value The Load Regulation setting insures the master will carry a slightly higher share of the common load Load Regulation is set in the Device Configure Output dialog as noted earlier Best sharing is done when the slave devices have two to three steps higher Load Regulation values Less and sharing is Slightly unstable ripple noise increases more regulation and sharing becomes much less equal Note that the GUI does not automatically bump up regulation for dPOLs attached to the same regulation bus This must be done by hand Also it is recommended that the dPOL closest to the biggest load element on the shared output bus be set up to act as the group s master BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com 7 9 2 CS and Interleave Since shared busses tend to have relatively high currents interleaving switching of shared bus dPOLs is generally desirable The lowest noise generation is usually achieved when shared bus dPOL interleave phasing is set to approximately equally spaced intervals 7 10 Monitoring Along with status information dPOL converters can monitor their own performance parameters such as output voltage output current and temperature The output voltage is measured at the output sense pins output current is measured using the ESR of
11. the output inductor and temperature is measured by the thermal sensor built into the controller IC Output current readings are adjusted based on temperature readings to compensate for the change of ESR of the inductor with temperature A 12 Bit Analog to Digital Converter ADC converts the output voltage output current and temperature into a digital signal to be transmitted via the serial interface 12Bits for the Voltage 8 Bits for the Current and Temperature Monitored parameters are stored in registers VOM IOM and TMON that are continuously updated in the DPM at a fixed refresh rate of 1sec These monitoring values can be accessed via the lC interface with high and low level commands as described in the DPM Programming Manual Shown in Figure 54 is a capture of the GUI System Monitor while operating the Z1 DM7300 Evaluation board 7 10 1 In System Monitoring In system parametric and status monitoring is through the I2C interface Protocols are covered in the ZM7300 DPM Programming Manual The GUI uses the published commands In writing software for I2C bus transactions it is important to note that I2C responses are lower in priority in DPM operation than SD bus transactions If an I2C transaction overlaps an SD bus transaction the DPM will put the I2C bus on hold until it completes its SD activity The GUI is aware of this and such delays are transparent When directly polling dPOLs for information setting I
12. 0x09 R IW 1 R W 1 RW 1 RIW 0 RIW 1 RW 0 DCL5 DCL4 DCL3 DCL2 DCL1 DCLO XE Bit 7 Bit 0 Bit7 2 DCL 5 0 Duty Cycle Limitation 0x00 0 0x01 1 64 0x02 2 64 Ox1F 63 64 Bit 1 0 Unimplemented Read as 0 Figure 51 Duty Cycle Limit Register 7 7 6 Feedback Loop Compensation Programming feedback loop compensation allows optimizing dPOL performance for various application conditions For example increase in bandwidth can significantly improve dynamic response The dPOL implements a programmable PID Proportional Integral and Derivative digital controller to shape the open loop transfer function for desired bandwidth phase gain margin Feedback loop compensation can be programmed in the GUI PWM Controller window by setting Kr Proportional Ti Integral Td Derivative and Tv Derivative roll off parameters or directly writing into the respective registers CP Cl CD B1 Note that the coefficient Kr and the timing parameters Ti Td Tv displayed in the GUI do not map directly to the register values It is therefore strongly recommended to use only the GUI to set the compensation values The GUI offers 3 ways to compensate the feedback WO Page 26 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output AN POWET ONE VJ C hanging the Shape of Power Auto Compensation The GUI will calculate compensation settings from either informat
13. 7 Bit 0 Bit 7 6 Unimplemented Read as 0 Bit 5 TRP Tracking Protection Propagation 0 7 disabled 1 enabled Bit 4 OTP Over Temperature Protection Propagation 0 disabled 1 enabled Bit 3 OCP Over Current Protection Propagation 0 disabled 1 enabled Bit 2 UVP Under Voltage Protection Propagation 0 disabled 1 enabled Bit 1 OVP Over Voltage Protection Propagation 0 disabled 1 enabled Bit 0 PVP Reserved Figure 39 Protection Configuration Register PC3 WO Page 21 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POUWEI lfe WP C hanging the Shape of Power 7 5 9 Front End and Crowbar the undervoltage is removed The 130ms hiccup As shown in the propagation dialog if an error is interval is guaranteed regardless of the turn off delay propagated the DPM can be configured to generate setting commands to turn off a front end a DC DC x converter generating the intermediate bus voltage or trigger crowbar protection to accelerate removal of the IBV voltage The two options are independent of inter group propagation and may require some external hardware to interface to the front end supply or crow bar SCR device mh Pile dd 7 5 10 Propagation Examples Understanding Fault and Error propagation is easier with the following examples The First example is of of non propagation from a 1 dPOL as shown in Figu
14. Programmable to 500 1 000 Duty Cycle Limit Default 90 5 Programmable 1 56 steps 3 125 100 d At negative sink output current bus terminator mode the efficiency of the DP7120 degrades resulting in increased internal power dissipation and switching noise Therefore maximum allowable negative current under specific conditions is lower than the current determined from the de rating curves shown in paragraph Dynamic Regulation Peak Deviation Settling Time WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 3 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet AN 8V to 14V Input e 0 7V to 5 5V Output POWET ONE VIC hanging the Shape of Power I 3 Protection Specifications Parameter Condiio Descripion Min Nom Max Unis Output Overcurrent Protection Tvpe Default Non Latching 130ms period yP Programmable Latching Non Latching Default 132 9olOUT Output Overvoltage Protection Tura Default Non Latching 130ms period yp Programmable Latching Non Latching Default 130 9o VOo SET KORADE Programmable in 10 steps 110 BAPI 7oVo sET Threshold Accuracy Measured at Vo ser 2 5V Dela From instant when threshold is exceeded until y the turn off command is generated M Default Emergency Off Turn Off Behavior 7 Programmable to Critical Off Emergency Off Output Undervoltage Protection Tvpe Default Non Latching 130ms period yp Programmable Latching Non Latching Default Threshold Progra
15. Where locp is the overcurrent protection threshold of the dPOL If the condition is not met then the overcurrent protection will be triggered during the turn on process To avoid this dVg dt and the overcurrent protection threshold should be programmed to meet the condition above 7 3 2 Delay and Slew Rate Combination The effect of setting slew rates and turn on off delays is illustrated in the following sets of figures Tek Prevu u Trig Ac UE Se RENE ce er ee EE EL EE D E i l 4 Ch1 High l 1 j 4 1 850 V Ch3 High 4 1 510 V merrier i wonsincnninneninnenisnenienssinnnsinensinensincnninssnisnenisnanicnceionnescencinenciocsninnsnisnsnienesianesisensicensinsncinsnnincenicrenicnssiancesesnsinensinencinaenionenienenieneicnneicencinennsnenvincsnionenicncnienscconsinscsinensinceninneel chi So0mv Say S00mV LII 00ms A Chl 220mV IE 500mV 5 i3 24 60 Figure 25 Tracking Turn On Rising Slew Rate is Programmed at 0 5V ms for each output WO Page 15 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN POWET ONE NS Changing the Shape of Power Tek Run Trig EE EOM H 1 Ch1 High PL EP NE R R RAUS 2 050 V i l 1 860 V ch3High 1 520V Ry Do Pe ete oh ae se Oh c C eo wees wae e chi So0mv Scns S00mV ur dooms A Chi 7 220mV IE 500mV 5 is 12 00 Figure 26 Turn On with Different Rising Slew Rates
16. classified into three groups based on their effect on system operation warnings faults and errors These are warnings errors and faults Warnings include Thermal Overtemperature limit near and Power Good a warning in a negative sense Faults in DP7xxx and DP8xxx series dPOLs include overcurrent protection overvoltage overtemperature and tracking failure detection Errors include only undervoltage Control of responses to Faults and Errors are distributed between different dPOL registers and are configurable in the GUI BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Thresholds of overcurrent over and undervoltage detection and Power Good limits can be programmed in the GUI Output Configuration window Figure 15 or directly via the I C bus by writing into the PC2 registers shown in Figure 32 Note that the overvollage and undervoltage protection thresholds and Power Good limits are defined as percentages of the output voltage Therefore the absolute levels of the thresholds change when the output voltage setpoint is changed either by output voltage adjustment or by margining PC2 Protection Configuration Register 2 1 Address 0x01 RIW O RW 0 RW 1 RW 0 RAW 0 R W 0 MN NEG PGHL PGLL OVPL1 OVPLO UvPL1 UVPLO Bit 7 Bit 0 Bit7 6 Unimplemented read as 0 Bit 5 PGHL Power Good High Level 1 105 of Vo 0 110 of Vo default Bit 4 PGLL Power Good Low Level 1 95 of Vo 0 90 of V
17. output voltage in response to alternating 25 75 step loads applied at 2 5A us The dPOL converter switching at 500KHz and had 10 x 22uF ceramic Capacitors connected across the output pins Bandwidth of the feedback loop was programmed for faster transient response BCD 00259 Rev 1 0 12 Feb 2013 www power one com Tek Run lt lt lt Trig d poe SO S Mi 00ms A Ch3 X 37 0mV 50 0mV 8j 70 00 Figure 52 Transient Response with Regulation set to 0 0 mV A Increasing the Load Regulation parameter induces a droop or offset in the output at the higher current load Tek Run p dDB Trig d beter bite betel MR E E RET PERENNEM PNE TI GE 50 0mV v5j 15 70 00 Figure 53 Transient Response with Regulation set to 0 74 mV A 7 9 Load Current Sharing The DFP7120 is equipped with a patented active digital current share function Setting up for current sharing requires both hardware and software configuration actions To set up for the current sharing interconnect the CS pins of the dPOLs that are to share the load in parallel This pulse width modulated digital signal drives the output currents of all dPOLs to WO Page 27 of 37
18. registers 00h through 14h are programmed at the system power up When the user programs new performance parameters the values in the registers are overwritten Upon removal of the input voltage the default values are restored DP7120 converters can be programmed using the Graphical User Interface or directly via the I C bus by using high and low level commands as described in the DPM Programming Manual DP7120 parameters can be reprogrammed at any time during the system operation and service except for the digital filter coefficients the switching frequency and the duty cycle limit that can only be changed when the dPOL output is turned off CONFIGURATION REGISTERS Name Register Address Protection Configuration 1 Protection Configuration 2 Protection Configuration 3 Tracking Configuration Interleave and Frequency Configuration Turn On Delay Turn Off Delay Voltage Loop Configuration Current Limit Set point Duty Cycle Limit Protection Configuration 4 Output Voltage Setpoint 1 Low Byte Output Voltage Setpoint 1 High Byte Output Voltage Setpoint 2 Low Byte Output Voltage Setpoint 2 High Byte Output Voltage Setpoint 3 Low Byte Output Voltage Setpoint 3 High Byte Controller Proportional Coefficient Controller Integral Coefficient Controller Derivative Coefficient Controller Derivative Roll Off Coefficient STATUS REGISTERS Name Register O Addrss 0x15 0x1
19. tracking of output voltages in the system And when fault propagation is set to go from one group to another the encoding is passed along un changed 7 7 Switching And Compensation dPWER dPOLs utilize the digital PWM controller forced to use the same frequency by the GUI Working around this restriction is not recommended The controller enables users to program most of the performance parameters such as switching frequency PWM duty cycle and limiting interleave and feedback loop compensation 7 7 1 Switching Frequency The switching frequency of the DP7120 can be Type Fault Output Sequencing Controller Circuit System ID Compensation Display Calculations are based on mos NN Step Response AC Simulation Magnitude Phase Loop Gain C Power Train C Controller Magnitude dB Phase 200 hy d n emi 100 1000 10000 100000 programmed to either 500KHz or 1MHz in the GUI Frequency IH ane r Auto Compensation Manual Compensation PWM andwidth 23 z PWM Controller window shown in Figure 45 or recency BERE muse directly via the I2C bus by writing into the INT Mencia dapor neteve 0 onmis Opt fte o automatica nsate the voltage feedback loop based on Duty Cycle CP 29 the device settings In some Cl 2 cases a manual post optimization CD 18 of pole zero placement might be CV 4 register shown in Figure 46 Note that the content of the register can be changed only when
20. 0 C 7 5 2 4 Tracking Protection Tracking protection is active only when the output voltage is ramping up The purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mV This protection eliminates the need for external Vo clamping diodes between different voltage rails which are frequently recommended by ASIC manufacturers When the tracking protection is enabled the dPOL continuously compares actual value of the output voltage to its programmed value as defined by the output voltage and its rising slew rate If absolute value of the difference exceeds 250mV the tracking fault signal is generated the dPOL turns off and the TR bit in the register ST is changed to 0 Both high side and low side switches of the dPOL are turned off instantly fast turn off The tracking protection can be disabled if it contradicts requirements of a particular system for example turning into high capacitive load where rising slew rate is not important It can be disabled in the dPOL Configure Fault window or directly via the I C bus by writing into the PC1 register 7 5 3 Faults and Margining As noted earlier UV and OV protection settings are a percentage of Vout As Vout ramps between nominal low or high margin values UVP and OVP limits adjust accordingly This is illustrated in Figure 34 The middle Vo Vout level is the result of a Low Margining command It shuts
21. 0 dPOL Although only one dPOL is shown other additional dPWER series dPOLs Note SD and OK dashed lines TO OTHER dPOLS may be connected In this case the DP7120 is connected to OK A Shown connected to the dP7015 OK pin is an optional low value resistor helpful in some cases for fault isolation The type value and the number of output capacitors shown in the schematic are required to meet the specifications published in the data sheet However all dPWER dPOLs are fully operational with different configurations of output capacitors The supervisory reset circuit in the above diagram U2 is recommended for systems where the 3 3V supply to the DPM does not turn on faster than 0 5 V ms The DPM does require some passive components which are located close to that part but not shown in the diagram above Note The DP7120 is footprint compatible with the ZY7120 No change in PCB is needed to upgrade to dPWER parts However configuration data must be altered through the Power One I2C GUI and programmed into the DPM When upgrading to dPWER mixing ZY and DP series devices is not recommended All parts must be upgraded WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 33 of 37 PN POWET ONE DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output Changing the Shape of Power IEW SUL SDA NCP3U3LSNZT MN TOOTHER dPOLS Oo e R3 CT R4 ORO 10K Tin co IMOLT O
22. 0 mV A As the Load Regulation parameter is increased step offsets in output voltage begin to appear as shown in Figure 19 with non zero Regulation Tek Stop a Chl Pk Pk 57 6mV 1 GI 20 0mMVv Mi00gs A Chl S 10 0mV Figure 19 Transient response with Regulation set to 074 mV A The Load Regulation parameter is an important part of Current Sharing It is used to set one dPOL as a master and all others sharing the load as slaves The dPOL with the lowest Regulation parameter sets the effective overall regulation See Current Sharing elsewhere in this document WO Page 13 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet PN PUWEI lfe 8V to 14V Input e 0 7V to 5 5V Output VIG hanging the Shape of Power 7 2 Sequencing and Tracking Turn on delay turn off delay and rising and falling output voltage slew rates can be programmed in the dPOL Configure Sequencing window shown in Figure 20 or directly via the I2C bus by writing into the DON DOF and TC registers respectively The registers are shown in Figure 21 Figure 23 and Figure 24 Configure v Device DP7007 GrupA Addr 00 Type Fault Output Sequencin g Controller Delays Slew Rates Power Good Display V Show other POLs io daplay ts abe Figure 20 dPOL Configure Sequencing Window 7 2 1 Turn On Delay Turn on delay is defin
23. 29 Turn On into Prebiased Load V3 is Prebiased by V2 via a Diode This figure was captured with an actual system where a diode was added to pre bias a 1 5V bus from a 1 85V bus in order to simulate the effect of current leakage through protection circuits of unpowered logic connected to powered logic outputs a common source of pre bias in power systems T 4 Turn Off Characteristics Turn of captures show that combining turn off delays and ramp rates Note that while turnoff delays have a lower upper time limit as compared to turn on delays all ramp down rates are available independently to turn on and off WT Page 16 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN PUWEI lfe Www C hanging the Shape of Power Tek Prevu Ch1 High 2 022 V H i 1 835 V Ch3 High 1 507 V Ci simy cha SH Ls CWUUSURS iml n Es ins x V Gig 500mV 5 i5 23 00 Figure 30 Tracking Turn Off Falling Slew Rate is Programmed at 0 5V ms Tek Run EE Ch1 High 2 040 V Ch2 High 1 845 V Ch3 High 1 510V PETER UT RT D T C TYPE CUN UT NRI LT BASE VE MMC chit 500mV epo 500mV ETIN 00ms rn Chi X 1 84V Giz 500mV 4 62 80 Figure 31 Turn Off with Tracking and Sequencing Falling Slew Rate is Programmed at 0 5V ms 7 5 Faults Errors and Warnings All dPOL series converters have a comprehensive set of programmable fault and error protection functions that can be
24. 2C bus timeouts too low can cause hangups where WO Page 28 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POWET ONE NS Changing the Shape of Power the DPM is waiting for the I2C master to complete a transaction and the master has timed out To avoid such timeout related problems set l2C interface timeout to greater than the time required for polling all dPOLs or 150ms whichever is greater See the programming manual referenced above for the Power One I2C 71 K1 Evaluation Baard z1c File Edit View Tools Window Help equation used to calculated worst case polling duration E ied cd du ed I LH 7 2 Bd AL MY Bal E D Cr Es 2 B zM 368 E Group 00 DP 115 ul 0P7115 04 AusDevo m Group B ad Signals E vents ors 2Me cae Q O05 amp uxDev Group C 3 Crowbar L3 RES Min ux OPO d FE Enable 2 AC FAlLin IBV high 3 IBY low IB Z65W Run Time 480 4 h Pol 00 v Vo 20V Paimiar Mna T 15 A AT Simulate Cook 2 a 5 PAG Gal Ga Ga Ga Ga Ga HUM Gal Ga Ga Ga Ga Ge Device Monitoring Monitoring A Status Parametric Display Controls gt uJ Log to File 2 Controls On Off Controls System Margining Low Mam High Gop 9 O Goupb O 9 O Time s Gop O e pay i2c HER OCC CLR HLP Command Log Pragram IE CUP PME UMTAMUS Monitoring step on lz Sep z lz 03 05 12 o
25. 30 ES i X Mo Error Figure 55 Evaluation Board Configuration showing Current Share Bus Assignment WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 30 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output lan POWET ONE VIG hanging the Shape of Power 9 Testing Fault and Error Response Included in the architecture of dPWER dPOLs is a mechanism for simulating errors and faults This allows the designer to test their response configuration without actually needing to induce the The Power One GUI supports this feature in the Monitor window when monitoring is active See Figure 56 When monitoring is off the Fault Injection control boxes are disabled and grayed out fault Ld Signals E vents 34 IM in LINZ in a IN in INS in Crowbar RES_N in FE Enable AC_FAIL in 4 BV high a IBY low IBY 12 17 V Run Time 110 1 h Ld Group Status x Tw PG TR OT OC uv ev ry A La La Ga Ga God Go a BL Ga Gal Gal Ga God Go Ge CL La La Ga a Pol 00 Pol o0 v Yol 1 80V DP7115 lo 11 84 Power One T 25 8 C Tw PG TROT OC Uy DV Pv Lad L3 L3 Lo L3 2 L4 Ld Fault Injection did odi dod lll al oid Current A Temperature C Device Monitoring 1 20 3n 40 n 60 a B 40 20 D 10 20 3n 40 50 Bn Time s rFmrrrrrr Figure 56 Fault Injection Controls In Monitor Window Monitoring amp Statu
26. 6 Name Register Addrss RUN Run enable status ST Status MONITORING REGISTERS VOH Output Voltage High Byte Monitoring Output Voltage Low Byte Monitoring Output Current Monitoring Temperature Monitoring Table 1 DP7120 Memory Registers BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com 7 1 Output Voltage The output voltage can be programmed in the GUI Output Configuration window shown in the Figure 15 or directly via the lC bus by writing into the VOS register shown in Figure 16 Configure v Device DP7115 Group A Addr 03 Type Faut Output Sequencing Controller r ST Voltage 15V i Current Limit 198A Load Regulation 0 0 mV A Monitoring Thresholds Over Voltage 1 95 V 130 PG High 1 65V 110 PG Low 1 35 V 907 Under Voltage 1 125V 75 i High 1 575 V 5 i Low 14V 7 2nd Vo Loop V Enable 2nd Vo Loop T i u i Curren t A Figure 15 Output Configuration Window Note that the GUI shows the effect of setting PG OV and UV limits as both values and graphical limit bars Vertical hashed lines are error bars for the Overcurrent OC limit 7 1 1 Output Voltage Setpoint The output voltage programming range is from 0 7 V to 5 5 V The resolution is constant across the range and is 2 5 mV A Total of 3 registers are provided one should be used for the normal setpoint voltage the other two can be used to d
27. DP7120 20A DC DC Intelligent dPOL Data Sheet N j 8V to 14V Input e 0 7V to 5 5V Output POWETr ONE NS Changing the Shape of Power Features e Input voltage range 8V 14V e High continuous output current 20A e Wide digitally programmable output voltage range 0 7V 5 5V e Active patented current sharing e Single wire serial communication bus between dPOL and Digital Power Manager DPM e Programmable dynamic output voltage positioning for better load transient response e Overcurrent overvoltage undervoltage and overtemperature protections with programmable thresholds and hiccup or latching modes e Programmable fixed switching frequency 500KHz or 1 0MHz e Programmable switching phase delay e Programmable turn on and turn off delays Compliant Applications e Low voltage high density systems with Intermediate Bus Architectures IBA e Point of load regulators for high performance DSP FPGA ASIC and microprocessor applications e Programmable turn on and turn off output voltage e Desktops servers and portable computing slew rates with tracking protection e Broadband networking optical and e Auto Compensation communications systems e n System Loop Identification SysID through pseudo random noise injection Benefits e Power Good signal with programmable threshold and e Integrates digital power conversion with intelligent delay power management e Advanced fault management and propagation e Eliminates t
28. G bit of the status register ST to O When the output voltage returns within the Power Good window the PG pin is released high the PG bit is cleared and the Power Good Warning is removed The Power Good pin can also be pulled low by an external circuit to initiate the Power Good Warning At turn off the PG pin can be programmed to either be pulled low immediately following the turn off command or then when the voltage actually starts to ramp down Reset vs Power Good functionality in Figure 20 Note To retrieve status information Status Monitoring in the GUI DPM Configure Devices window should be enabled refer to Digital Power Manager Data Sheet The DPM will retrieve the status information from each dPOL on a continuous basis 7 5 2 Faults This group includes overcurrent overtemperature undervoltage and tracking protections Triggering any protection in this group will turn off the dPOL For UV and OT faults the turn off can be programmed to sequenced or critical turn off behavior 7 5 2 1 Overcurrent Protection Overcurrent protection is active whenever the output voltage of the dPOL exceeds the prebias voltage if any When the output current reaches the OC threshold the POL control chip asserts an OC fault The dPOL sets the OC bit in the register ST to O Both high side and low side switches of the dPOL are turned off instantly fast turn off Current sensing is across the dPOLs choke To compensate for coppe
29. RI cs Cid 3x S30uF zzuF lt _ WRTN RESN ACFAIL HRES M WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 34 of 37 ERROR stackunderflow OFFENDING COMMAND STACK Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Power One DP7120G R100
30. S 7 5 1 Warnings This group includes Overtemperature Warning and Power Good Signal Warnings do not turn off dPOLs but rather generate signals that can be transmitted to a host controller via the I C bus 7 5 1 1 Overtemperature Warning The Overtemperature Warning is generated when temperature of the controller exceeds 120 C The Overtemperature Warning changes the TW bit of the status register ST When the temperature falls below 117 C the PT bit is cleared and the Overtemperature Warning is removed 7 5 1 2 Power Good Power Good PG is an open collector output that is pulled low if the output voltage is outside of the Power Good window The window is formed by the Power Good High threshold that is programmable at 105 or 110 of the output voltage and the Power Good Low threshold that can be programmed at 90 or 95 of the output voltage Power Good protection is only enabled after the output voltage reaches its steady state level A programmable delay can be set between 0 and 150ms to delay the release of the PG pin after the voltage has reached the steady state level see BCD 00259 Rev 1 0 12 Feb 2013 www power one com Figure 20 This allows using the PG pin to reset load circuits properly The Power Good protection remains active during margining voltage transitions The threshold will vary proportionally to the voltage change see Figure 34 The Power Good Warning pulls the PG pin low and changes the P
31. S OW Ow ATE Pr WM L410mV eC donnes n ES den T MITT GE 5 00 mV 29 Sep 2004 i3 19 40 12 46 13 Figure 50 Output Voltage Noise Full Load 180 Interleave 7 7 5 Duty Cycle Limit The DP7120 is a step down converter therefore Vout is always less than Vw The relationship between the two parameters is characterized by the duty cycle and can be estimated from the following equation DC Vout VIN MIN Where DC is the duty cycle Voyr is the required maximum output voltage including margining Vinmin S the minimum input voltage The dPOL controller sets PWM duty cycle higher or lower than the above to compensate for drive train losses or to pull excess charge out of the output filter BCD 00259 Rev 1 0 12 Feb 2013 www power one com to keep the output voltage where it is supposed to be A side effect of PWM duty cycle is it also sets the rate of change of current into the output filter A high limit helps deal with transients However if this is too high an overcurrent alarm can be tripped Thus DC limiting must be a compromise between supplying drive train losses and avoiding nuisance trips from transient load responses The duty cycle limit can be programmed in the GUI PWM Controller window Figure 45 or directly via the IC bus by writing into the DCL register shown in Figure 51 The GUI will supply its own estimate of the best DC limit if the Propose button is clicked DCL Duty Cycle Limitation Address
32. Type When Active Turn Low Side Propagation Disable Off sA Temperature Warning Whenever Vin is applied BENE Status Bit Warning During steady state 13 1 Bal Critical When Vour exceeds prebias Critical OV Overvoltage Error When Vour exceeds prebias Fast On Emergenc WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 23 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output LA P MCI UE VIG hanging the Shape of Power 7 6 OK Coding of Faults and Errors dPWER dPOLs have an additional functionality added to the OK line signal The OK line is used to propagate and receive information from other devices in the power system belonging to the same group as to the kind of turn off procedure a device has initiated because of a fault Figure 44 shows the three types of OK encoding The bubbles show when the SD and OK line logic levels are sampled by dPOL and the DPM logic s s Sequenced Off Fast Off Error Off Figure 44 OK Severity Encoding Waveforms Note that the OK line state changes are always executed by dPOLs at the negative edge of the SD line The chart shows shut down response types as the user can select the kind of response desired for each type of Fault or Error within the limits of choice provided for each type of Fault or Error All dPOL devices in the same Group are expected to trigger the same turn off procedure in order to maintain overall
33. condition If the falling slew rate control is not utilized the turn off delay only determines an interval from the application of the Turn Off command until both high side and low side switches are turned off In this case the output voltage ramp down process is determined by load parameters DOF Turn Off Delay Configuration Address 0x06 U U R IW 0 R W 0 RW 1 RW 0 RIW 1 RIW 1 Bit 7 Bit 0 Bit 7 6 Unimplemented read as 0 Bit 5 0 DOF 5 0 Turn Off delay in ms 0x00 Oms 0x01 1ms OxOB 11ms default Ox3F 63ms Figure 23 Turn Off Delay Register DOF 7 0 Turn On Off Control Once delays are accounted for turn on and turn off characteristics are simply a function of slew rates which are selectable oper Page 14 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POWET ONne VJ C hanging the Shape of Power 7 3 1 Rising and Falling Slew Rates Output voltage ramp up and down control is accomplished by programming the rising and falling slew rates of the output voltage supported in the GUI as shown in Figure 20 which is implemented by the DPM through writing data to the TC register Figure 24 To achieve programmed slew rates the output voltage is being changed in 10mV steps where duration of each step determines the slew rate For example ramping up a 1 0V output with a slew rate of 0 5V ms will require 100 steps duration of 20us each
34. d click the Off button of the dPOL or Group clears the fault status LEDs turn back to green and then the On button of the dPOL or Group to re enable it WO Page 32 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN PUWEI HE VIC hanging the Shape of Power 10 Typical Application Figure 58 is a block diagram of a multiple dPOL power system The key interconnections needed between the DPM and the dPOLs are Intermediate Voltage Bus IBV SD OK A C and between the first two dPOLs which share a bus load their CS connections Each dPOL has its own output bulk filter capacitors This illustrates how simple a dPOL based system is to implement in hardware SD provides synchronization of all dPOLs as well as communication PG not shown is optional though this is usually used with auxiliary power supplies that are not digitally controlled IBS jpnencuen necis Intermediate Voltage Bus Crowbar Optional 1 u i For H 23 l 1 f 1 1 1 1 1 6 25 42 57 60 e e e I R VDD VDD VDD VDD VDD IBVS CB 1 48 44 AREF R2 e DM7332 VSS VSS VSS VSS VSS VSS 8 9 26 38 43 58 Figure 58 Multi dPOL Power System Diagram Shown in Figure 59 is a schematic of a typical application using at least one DP7120 point of load converter dPOL The system includes a DM7300 series Digital Power Manager DPM a DP712
35. duction Tek stop M i a a E TA 240mv dA 1 00us je 136ns i1 1 Ch4 Pk Pk Ch4 RMS 6 89mV PO Peet Peet IER BN a 1E WOT SRO ES EE S EN E I EA A SIT QI ON O EEA AA DE AE DE ES EA O IEE INCUN 1 M 400ns r Cha 16 8mV ie 10 0mV v amp 27 00 Figure 48 Input Voltage Noise with Interleave 7 7 4 Interleave and Current Sharing Noise Similar noise reduction can be achieved on the output of dPOLs connected in parallel Figure 49 and Figure 50 show the output noise of two dPOLs connected in parallel without and with a 180 interleave respectively Resulting noise reduction is more than 2 times and is equivalent to doubling WO Page 25 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN PUWEI lfe VIG hanging the Shape of Power switching frequency or adding extra capacitance on the output of the dPOLs Tek e T9 4 9 J V 9 9 9 34 9 5 4 9 1 J V J 4 9 4 4 9 J M 9 v 1 1 Ch3 Pk Pk Ov wu NC UMEN 1 21 62mV 01 mM ii ME x OPES V a 97mv w MAG I AINA p miniinnnindnbinindnaneeteindeiy denos ia ES ene T METTI E 5 00mV 5 29 Sep 2004 19 40 12 47 22 Figure 49 Output Voltage Noise Full Load No Interleave Tek P ct V 5 9 4 49 39 E W V 1 9 9a V M wow D H 1 Ch3 Pk Pk ELEME ENTRE RERO EEEE ADU 9 684mV 3 0 n QUAL MUN LHR ME ml te ae aay i ANLE Ch3 RM
36. e in 8 steps 0 05 95 ae vm Optimal Voltage Positioning Load Regulation Default mV A Programmable in 7 steps 2 45 mV A Feedback Loop Compensation Proportional Kr Programmable 0 01 Integral Ti Programmable 1 aa 100 Differential Td Programmable 1 9 o as Differential Roll Off Tv Programmable 1 o Us Voltage Monitoring Accuracy 12 Bit Resolution over 0 5 5 5V 0 5 Current Monitoring Accuracy 20 lout nom lt lout lt lour Nom 20 5 Temperature Monitoring Accuracy Junction Po of dPOL Remote Voltage Sense VS and VS pins 300 mV mV Voltage Drop Compensation Between VS and VOUT Voltage Drop Compensation Between VS and PGND L Timing based on SD clock and subject to tolerances of SD Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment See Rising and Falling Slew Rates For remote sense it is recommended to place a 0 01 0 1uF ceramic capacitor between VS and VS pins as close to the dPOL converter as possible WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 6 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet AN 8V to 14V Input e 0 7V to 5 5V Output POWET ONE VIC hanging the Shape of Power I 5 Signal Specifications Parameter Conditions Description Co z Co Co 3 45 VDD 5 VDD Internal supply voltage Logic In Max Pull Up Logic max safe input SYNC DATA Line SD pin vss owen
37. ed as an interval from the application of the Turn On command until the output voltage starts ramping up DON Turn On Delay Configuration Address 0x05 R W 0 R W 0 RW 0 RW 0 RW 0 RWO0 RIW 0 RW 0 DON7 DONG DONS DON4 DON3 DON2 DON1 DONO Bit 7 Bit 0 Bit 7 0 DON 7 0 Turn On delay in ms 0x00 Oms default 0x01 1ms OxFF 255ms Figure 21 Turn On Delay Register DON 7 2 2 Turn Off Delay Turn off delay is defined as an interval from the application of the Turn Off command until the output voltage reaches zero if the falling slew rate is programmed or until both high side and low side switches are turned off if the slew rate is not BCD 00259 Rev 1 0 12 Feb 2013 www power one com programmed Therefore for the slew rate controlled turn off the ramp down time is included in the turn off delay as shown in Figure 22 User programmed turn off delay Tpr OO Turn Off Command Calculated Internal delay Tp Ramp down time Te 4 ramp down command Vout Falling slew rate dV dT Time Figure 22 Relationship between Turn Off Delay and Falling Slew Rate As it can be seen from the figure the internally calculated delay Tp is determined by the equation below V T mL OUT D DF di dT For proper operation Tp shall be greater than zero The appropriate value of the turn off delay needs to be programmed to satisfy the
38. efine a low high margining voltage setpoint Note that each register is 16bit wide and that the high byte needs always to be written read first The writing of the low byte triggers the refresh of the whole 16bit register the high byte is written to a shadow register Unlike other configuration registers the dPOL controller s VOS registers are dynamic Changes to VOS values can be made while the output is enabled over the 12C bus through register bypass commands and the dPOL will change its output immediately WO Page 12 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output AN PUWEI HE WP C hanging the Shape of Power bus In the DP7007 Load Regulation can be set to one of eight values 0 0 37 0 74 1 11 1 48 1 85 2 23 or 2 6 mV A Figure 18 shows a DP7120 dPOL with 0 mV A load current regulation Alternating high and low output load currents causes large transients in Vout to appear with each change VOS Output Voltage Set Point Address OxOB 0x10 Coefficient Addr Bits Default VIH First Vo Setpoint High Byte B 8 VIL First Vo Setpoint Low Byte 0c 8 V2H Second Vo Setpoint High Byte D 8 Second Vo Setpoint Low Byte OQE 8 V3H Third Vo Setpoint High Byte Oxo 8 V3L Third Vo Setpoint Low Byte 0x10 8 Tek Stop Mapping U 12 bit data word left aligned 1LSB 2 5mV Note all register
39. ge ramping up NEM mVDC Dela From instant when threshold is exceeded until us y the turn off command is generated Overtemperature Warning Threshold Always enabled face Status register TW NEN 110 Threshold Accuracy From Nominal Set Point Power Good Signal PG pin g Vour is outside the PG window Low Default JoVO sET Default 110 Upper Threshold Programmable in 5 steps VOSET Threshold Accuracy Measured at Vo set 2 5V 2 9oVOo sET 6 Default EE EON elay Programmable at 0 10 50 150 me Default PG iid cd lt Vuv PG Off Delay iniesuo PG disabled at turn off command Programmable same as PG On Delay Pesar incon i Temp Warning error same sign and proportional with OTP error From instant when threshold is exceeded until status of PG signal changes high WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 5 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet AN 8V to 14V Input e 0 7V to 5 5V Output POWET ONE VIC hanging the Shape of Power I 4 Feature Specifications Current Share a Active Single Line Maximum Number of Modules 5 Current Share Accuracy lout 2 2096 lout nom 20 ow Interleave l Default Degree Sequencing Default ms Turn ON Delay Programmable in 1ms steps Cli X ms 63 ms Tracking Default Turn OFF Delay Programmable in 1ms steps Default 0 05 V ms Turn ON Slew Rate Programmable in 8 steps 0 05 Lara vem Default 0 05 V ms Turn OFF Slew Rate Programmabl
40. he dPOL will attempt to restart every 130 ms repeating the Since both Vo1 and Vo2 have the same delay and process described above until the condition causing slew rate settings they will continue to turn off and on WO DP7115 DP7120 DP7120 BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 22 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN POWET ONne VJ C hanging the Shape of Power synchronously every 130ms as shown in Figure 43 The turn off type of a dPOL fault error as propagated until the condition causing the undervoltage is by the faulty dPOL via the OK line is propagated removed through the DPM to other dPOLs connected to other Groups through its connection to their OK line or Note that the dPOL powering the output Vo2 Ch3 lines actually reaches its voltage set point before the error in Vo1 is detected This behavior assures that all dPOLs configured to be affected through Group linkages will switch off leCroy with the same turn off type 7 5 11 Protection Summary A summary of protection support their parameters and features are shown in Table 2 i 58 ms 0 50 V 2 50 ms 8 50 V S 50 ms 0 50 V STOPPED Figure 43 Turn On into UVP on V3 The UV Fault Is Programmed To Be Non Latching and Propagate From Group C to Group A Ch1 V3 Group C Ch2 V2 Ch3 V1 Group A Table 2 Summary of Protection Parameters and Features
41. he need for external power e Start up into pre biased load manag IIO CBHTBONORES e Real time voltage current and temperature e Programmable via industry standard l C measurements monitoring and reporting communication bus dud required u e Small footprint Vertical oriented SMT package e Reduce the number of discrete parts within a 8x32mm power system e Reduces board space system cost complexity and time to market e ow profile of 14mm e Compatible with conventional pick and place equipment e Wide operating temperature range 40 C 85 C e UL 60950 1 CSA 22 2 No 60950 1 07 Second Edition IEC 60950 1 2005 and EN 60950 1 2006 pending Description Power One s DP7120 is an intelligent fully programmable step down point of load DC DC converter integrating digital power conversion and intelligent power management The dPOL is used in conjunction with DM73xx Series Digital Power Manager DPM and completely eliminates the need for external components for output voltage setting sequencing tracking protection monitoring error amplifier compensation and reporting All performance parameters of the DP7120 are programmable and managed through Digital Power Manager via the industry standard IC communication bus and can be changed by a user at any time during product development and operation Telemetry data is available in real time and can be accessed over the l C bus Lwe BCD 00259 Rev 1 0 12 Feb 2013 www power one c
42. in the part number printed on the dPOL converter label WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 2 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POUWEI lfe VIC hanging the Shape of Power 4 Electrical Specifications Specifications apply at the input voltage from 8V to 14V output load from 0 to 20A ambient temperature from 40 C to 85 C Test conditions include an output filter with 3 x 330uF 20mQ solid electrolytic plus 2 x 22uF X7R ceramic output capacitors unless otherwise noted 4 1 Input Specifications Input Current at no load Vin 14 0V Vout 3 3V 5 mADC Ramping Up VDC Midi Hin Ramping Down GUY Current drawn from the external low e voltage supply at VLDO 8V e inn 4 2 Output Specifications Output Voltage m 2 5mV 1LSB Resolution Output Voltage Setpoint Accuracy a Vo Loop Enabled 0 6 5mV Output Current lou VwwntoVwm 88 AD Line Regulation Vambo 0 303 or Load Regulation Obom e Vou Slew rate 1A us 50 75 load step Fsw 500kHz to 10 of peak deviation See Output Load Transient Section Vin 8 0V Vout 0 7V Output Voltage Peak to Peak Vin 8 0V Vout 2 5V Ripple and Noise Vin 8 0V Vour 5 5V Scope BW 20MHz Vin 14V Vout 0 7V Full Load Vin 14V Vout 2 5V Vin 14V Vour 5 5V Temperature Coefficient Vin 12V lout 0 5x lout max a C Default 500 Switching Frequency
43. ion entered as to output capacitors in the application circuit or if the SysID function has been run the frequency response measured through the SysID function in the target dPOL This method is usually sufficient but is sensitive to accurate accounting of capacitor values and esr The GUI displays the results of running Auto Compensation as a set of graphs and compensation values Manual Compensation The GUI supports manually adjusting feedback compensation parameters As the parameters are changed the GUI recalculates expected frequency and phase performance System Identification SysID and Auto Compensation Hardware built into the dPOL controller that injects pseudo random bit sequence PRBS noise into PWM calculations and observes the response of the output voltage The GUI collects this data and calculates actual system frequency response Having frequency response data allows the Auto Compensation function to have a better idea of actual output filter characteristics when it calculates feedback coefficients Using noise to plumb the output filter requires current values for compensation be good enough that injected signal can be extracted from system noise and the added noise does not trip a fault or error response A modestly accurate solution for compensation must be obtained by calculating from assumed system component values before invoking SysID 7 8 Transient Response The pictures below show the deviation of the
44. mbient Temperature C Figure 3 Available output current vs ambient air temperature and airflow rates for converter DP7120 mounted horizontally with air flowing from input to output MOSFET temperature O 120 IC Vin 12 V Vout 5 V and Fsw 500KHz 500 LFM 2 5 m s 400 LFM 2 0 m s t 300 LFM 1 5 m s 200 LFM Load Current Adc 100 LFM 0 5 m s 30LFM 0 15 m s 20 30 40 50 60 70 80 90 Ambient Temperature C Figure 4 Available output current vs ambient air temperature and airflow rates for converter DP7120 mounted horizontally with air flowing from input to output MOSFET temperature O 120 iC Vin 12 V Vout 5 V and Fswz 1MHz WO Page 9 of 37 PN POWET ONE DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output S Changing the Shape of Power 6 2 100 90 eo e Efficiency gt Efficiency Curves 7T Vo 0 7V Vo 1 2V VO 1 8V Vo 2 5V 5 10 15 Load Amps 20 Vo 3 3V 25 Figure 5 Efficiency vs Load Vin 12V Fsw 500kHz 100 95 4 9096 4 8596 4 8096 7596 4 7096 4 6596 6096 Efficiency 55 50 Vo 0 7V Vo 1 2V Vo 1 8V Vo 2 5V Vo 3 3V
45. mmable in 596 steps 75 75 Threshold Accuracy Measured at Vo ser 2 5V 2 2 Dela From instant when threshold is exceeded until y the turn off command is generated Turn Off Behavior Default Sequenced Off urn ehavior Programmable to Sequenced Critical Off Overtemperature Protection Tvpe Default Non Latching 130ms period yp Programmable Latching Non Latching Turn Off Threshold Temperature is increasing Temperature is decreasing after the module was EM Turn On Threshold shut down by OTP 110 Dela From instant when threshold is exceeded until EN y the turn off command is generated E Default Sequenced Off TUOI Denavir Programmable to Sequenced Critical Off Tracking Protection when Enabled Sequenced Off The turn off follows the turn off delay and slew rate settings Critical Off At turn off both low and high switches are immediately disabled Catastrophic Off At turn off the high side switch is disabled and the low side switch is enabled OTP clears when Overtemp Warning Status Register TW bit turns off NO YV ovP SET US YV 0 SET YV 0 SET Yo V UVP SET US m xv o qoue d o Je WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 4 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POUWEI lfe VIC hanging the Shape of Power coe Default Disabled yp Programmable Latching Non Latching 130ms Threshold Enabled during output volta
46. o default Bit 3 2 OVPL Over Voltage Protection Level 00 110 of Vo 01 120 of Vo 10 130 of Vo default 11 130 of Vo Bit 1 0 UVPL Under Voltage Protection Level 00 75 of Vo default 01 80 of Vo 10 85 of Vo 11 90 of Vo 1 This register can only be written when PWM is not active RUN RUN is 0 Figure 32 Protection Configuration Register PC2 Overcurrent limits are set either in the GUI dPOL Output configuration dialog or in the dPOL s CLS register as shown in Figure 33 Note that the CLS register includes bits which control the Regulation option settings When writing into this register be careful to not change Regulation by accident WO Page 17 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output AN PUWEI HE WP C hanging the Shape of Power CLS Current Limit Setting Address 0x08 R W 0 R W 0 RW 0 RW 1 RW 1 RIW 0 RIW 1 RIW 1 B Bit 7 it 0 Bit 7 5 LR 2 0 Load Regulation setting 0 0 V A Q default 1 0 39 V A O 2 0 78 VIAIO 3 1 18 V A Q 4 1 57 VIAIQ 5 1 96 V A O 6 2 35 VIAIO 7 2 75 VINIQ Bit 4 TCE Temperature Compensation for Current Limitation Enable 0 disabled 1 enabled default Bit3 0 CLS 3 0 Current Limit set point when Vo Stationary or Falling 0x0 37 0x1 47 0xB 140 default values higher than OxB are translated to OxB 140 Figure 33 Current Limit Setpoint Register CL
47. off when PG is asserted RUN OC enabled PG enabled Vo Rise Vo Stable Vo Fall Vo Rise Vo Stable Vo Fall 1 0V pre biased output Time Figure 34 Protection Enable Conditions BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com WO Page 19 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output AN POWET ONE VJ C hanging the Shape of Power 7 5 4 Errors The group includes overvoltage protection 7 5 4 1 Overvoltage Protection The overvoltage protection is active whenever the output voltage of the dPOL exceeds the pre bias voltage if any If the output voltage exceeds the overvoltage protection threshold the overvoltage error signal is generated the dPOL turns off and the OV bit in the register ST is changed to 0 The high side switch is turned off instantly and simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads The low side switch provides low impedance path to quickly dissipate energy stored in the output filter and achieve effective voltage limitation The OV threshold can be programmed from 110 to 130 of the output voltage setpoint but not lower than 0 5V Also the OV threshold will always be at least 0 25V above the setpoint 7 5 5 Fault and Error Latching The user has the option of setting up any protection option as either latching non latching and propaga
48. om Page 1 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POWET ONE VIC hanging the Shape of Power Reference Documents e DM7300 Digital Power Manager Data Sheet e DM7300 Digital Power Manager Programming Manual e Power One I2C GEN II Graphical User Interface e DMO00056 KIT USB to IC Adapter Kit User Manual 1 Ordering Information Packaging Option R100 100pcs T amp R Product les RoHS compliance family Intelligent dPOL Current G RoHS compliant for all six 20A dPWER Converter substances Q1 1pc sample for evaluation only Example DP7120G R100 A 100 piece reel of RoHS compliant dPOL converters Each dPOL converter is labeled DP7120G Larger reel sized not available 2 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings may cause performance degradation adversely affect long term reliability and cause permanent damage to the converter Inductor or Printed Circuit Board PCB Input Voltage applied Temperature Output Current See Output Current De rating Curves 3 Environmental and Mechanical Specifications Parameter ConaionsDesorpton Mm Nom Me Unie Ta fe s ls D Sowewwemen 1 w o wm 0 O O wm wrr oau Per Tesora Temos srao 628 Me Peak RetowTemperaure mm O 39 m Packaging option is used only for ordering and not included
49. on latching Bit 3 OCC Over Current Protection Configuration 1 latching 0 non latching Bit 2 UVC Under Voltage Protection Configuration 1 latching 0 non latching Bit 1 OVC Over Voltage Protection Configuration 1 latching 0 non latching Bit 0 PVC Phase Voltage Protection Configuration 1 latching 0 non latching Figure 36 Protection Configuration Register PC1 7 5 6 Fault and Error Turn Off Control In the GUI dPOL Fault dialog is a column of spin controls which set the Turn Off style OT UV and OV events The choices are defined as Sequenced Outputs shut down according to ramp down rate control settings Critical Both high side and low side switches of the dPOL are turned off instantly Emergency The high side switch is turned off instantly and simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads 7 5 7 Fault and Error Status otatus of dPOL protection logic is stored in the dPOL s ST register shown in Figure 37 When Status monitoring is enabled for a group the DPM will read this register and make the information available for uses such as GUI Monitor display WO Page 20 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN POWET ONne VJ C hanging the Shape of Power ST Status register Address 0x16 R 0 RIW 19 RIW 1 RIW 19 RIW 19 RIW 19 R W 1 cw ee m or oc
50. put lan POWET ONE VIG hanging the Shape of Power 6 Typical Performance Characteristics 6 1 Thermal De rating Curves 500 LFM 2 5 m s 8 400 LFM 2 0 m s t 300 LFM 1 5 m s Load Current Adc 200 LFM v 100 LFM 0 5 m s 30 LFM 0 15 m s 20 30 40 50 60 70 80 90 Ambient Temperature C Figure 1 Available output current vs ambient air temperature and airflow rates for converter DP7120 mounted horizontally with air flowing from input to output MOSFET temperature lt 120 C Vin 8 V Vout 5 V and Fsw 500KHz 500 LFM 2 5 m s E 400 LFM t 300 LFM Load Current Adc 1 5 m s 200 LFM 1 0 m s 100 LFM 30LFM 0 15 m s 20 30 40 50 60 70 80 90 Ambient Temperature C Figure 2 Available output current vs ambient air temperature and airflow rates for converter DP7120 mounted horizontally with air flowing from input to output MOSFET temperature lt 120 C Vin 8 V Vout 5 V and Fsw 1MHz BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com 500 LFM 2 5 m s s amp 400 LFM 2 0 m s 300 LFM 1 5 m s Load Current Adc 200 LFM 1 0 m s v 100 LFM 0 5 m s 30LFM 0 15 m s 20 30 40 50 60 70 80 90 A
51. r winding Tc compensation is added to keep the OC threshold approximately constant at temperatures above room temperature Note that the temperature compensation can be disabled in the dPOL Configure Output window or directly via the IC by writing into the CLS register However it is recommended to keep the temperature compensation enabled WO Page 18 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN POUWEI lfe WP C hanging the Shape of Power 7 5 2 2 Undervoltage Protection The undervoltage protection is only active during steady state operation of the dPOL to prevent nuisance tripping If the output voltage decreases below the UV threshold and there is no OC fault the UV fault signal is generated the dPOL turns off and the UV bit in the register ST is changed to 0 The output voltage is ramped down according to sequencing and tracking settings regular turn off 7 5 2 3 Overtemperature Protection Overtemperature protection is active whenever the dPOL is powered up If temperature of the controller exceeds 120 C the OT fault is generated dPOL turns off and the OT bit in the register ST is changed to 0 The output voltage is ramped down according to sequencing and tracking settings regular turn off If non latching OTP is programmed the dPOL will restart as soon as the temperature of the controller decreases below the Overtemperature Warning threshold of 11
52. re Devices dialog and implemented in hardware by connecting the OK pins of each dPOL in the group to the matching OK input on the DPM In order for a particular Fault or Error to propagate through the OK line Propagation needs to be checked in the GUI dPOL Configure Fault Management Window This read in the dPOLs PC3 register shown in Figure 39 BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Configure v Device ZM7332 Addr 0x5e ID 65535 Type Bus Voltages Devices Faults User Memory Turn On Fault Propagation All correctly programmed Devices will start up Only Groups with no programming error will start up System doesn t start if there is a programming error This setting affects the Group auto turn on feature and also the Group System I2C turn on commands Changing this option requires the DPM to be power cycled after programming Group Fault Propagation To On Error FE Crow off Bar Ge OOO 9 From Soe m OOO OO O QO O O B OOOO OOOO Interrupt Propagation M Figure 38 DPM Configure Faults Window Note that the turn off type of the fault as it propagates through the DPM will remain unchanged Propagation options for dPOLs can be read or set in the dPOL PC3 register shown in Figure 38 PC3 Protection Configuration Register 3 Address 0x02 RIW 1 RIW 1 RW 1 RIW 1 R IW 1 RW 1 L T TT om oce uve Ove PV Bit
53. re 40 An undervoltage error shuts down the Vo but since propagation was not i enabled OK A is not pulled down and Vo2 stays up gne ENEN jgueseniien E dim Figure 41 Turn On into UVP on V3 The UV Fault Is Programmed To Be Non Latching Ch1 Vo1 Ch2 Vo2 Group A Ch3 Vo3 Group B Vo4 not shown The next example is intra group propagation the dPOL propagates its fault or error events Here fault propagation between dPOLs is enabled In Figure 42 the dPOL powering output Vo1 again encounters an undervoltage error It pulls its OK line low Since the dPOL powering output Vo2 Ch3 in the picture belongs to the same group A in this DP7115 case pulling down OK A tells that dPOL to execute a regular turn off Vo1 Voz Vo3 Vo4 x v v v Figure 40 No Group Fault Propagation DPM DM7300 Figure 41 shows a scope capture an actual system i Group B when undervoltage error detection is set to not propagate In this example the dPOL connected to scope Ch 1 encounters the undervoltage fault after turn on Because fault propagation is not enabled for this dPOL it alone turns off and generates the UV fault signal Because a UV fault triggers the sequenced turn off the dPOL meets its turn off delay and falling Vo1 Vo2 Vos Vo4 slew rate settings during the turn off process as x x v v shown in the trace for Ch1 Since the UV fault is Figure 42 Intra Group Fault Propagation programmed to be non latching t
54. riptions Buffer Pin Description ais mm NotUsed Used Nointemalconecio internal connection ee 1 O O O e 3 wwe O een Cw fe fetuses Contr O D s p wwe fC ating Cw s wwe een O Cw 3 p wwe deme am Cw s wwe iemetam O ee AERE 5 5 Jm 0 EBEBLIEEE couUSmius Condition connect to OK pin of the DPM and any other dPOLs of the same group ere Sync DataLine Line Connect to SD pin of DPM TRM cL I NotUsed Used Leave Leavefloaing o Connect to CS pins of other dPOLs connected in 15 Current Share parallel Leave floating if not on shared bus ADDR4 XCTI dPOL Address Bit 4 Tie to PGND for 0 or leave floating for 1 ADDR3 o i PR dPOL Address Bit 3 Tie to PGND for 0 or leave floating for 1 ADDR2 38 0 PU dPOL Address Bit 2 Tie to PGND for 0 or leave floating for 1 ADDR1 ERE MEN dPOL Address Bit 1 Tie to PGND for 0 or leave sane conse UNE for 1 ADDRO Lom zo 1 pu dPOL Address BitO Address Bit 0 Tie to PGND for 0 or leave Tie to PGND for 0 or leave floating for 1 for 1 ES3ERERENET GR DA Cw mmm roo a e Pm Cw a fe mme Legend l input O output l O input output P2power A analog PU internal pull up NC No Connection WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 8 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Out
55. s j Parametric Display Controls w Qg Log ta File Controls On Off Controls System Group v Pao wj Margining Low Nom High Goudt O GmupB Gop O 9 Group D Front End Send Cmd Cmd Fault injection into a dPOL requires selecting that dPOL in the POL status dialog in the left column of the Monitoring dialog window As long as the checkbox is checked the fault trigger is present in the dPOL An injected fault is handle by the dPOL in the same fashion as an actual fault It therefore gets BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com propagated to the other dPOLs Groups and shuts down in the programmed Way the dPOL Group System as programmed for that fault WO Page 31 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output AN POWET ONE VJ C hanging the Shape of Power Monitor L Signals E vents gt INO in La IMzin INT in INS in E sees Crowbar 14 RES Hin La FE Enable AC FAIL in E gt 2 IBY high 3 IBY low IBY 12 15 V i 40 50 Run Time 110 1 h Current A Pol 00 amp 40 Atl B Paon s wo Cuon DP7115 lo DEEA P an Power One T 288 C 5 B TwPG TR OT OC Uv Ov py amp a To fell 2 La LM La Ld L 20 Fault Injection T ddd d d id d 40 50 B Time s Device Monitoring Monitoring Status i Parametric Display Controls w H Log ta File
56. s are readable and writeable always write and read the high byte first Figure 16 Output Voltage Setpoint Register VOS 7 1 2 Output Voltage Margining If the output voltage needs to be varied by a certain percentage the margining function can be utilized The margining can be programmed in the dPOL Configuration window or directly via the I C bus using high level commands as described in the DM7300 Digital Power Manager Programming Manual In order to properly margin dPOLs that are connected in parallel the dPOLs must be members of one of the Parallel Buses Refer to the GUI System Configuration Window shown in Figure 55 Vour Upper Regulation Limit Operating VI Curve Without Point Load Regulation VI Curve With Load Regulation Headroom without Load Regulation Headroom with Load Regulation Light Heavy Load ad Load Lower Regulation Limit Figure 17 Optimal Voltage Positioning Concept 7 1 3 Output Load Regulation Control When Load Regulation is programmed to be non zero the output voltage will decrease as the output current increases so the VI characteristic will have a negative slope at the point of regulation This can be programmed in the GUI Output Configuration window shown in Figure 15 or directly via the I C BCD 00259 Rev 1 0 12 Feb 2013 www power one com Ch1 Pk Pk 94 2mV BUX und se AO cow Figure 18 Transient Response with Regulation set to
57. the dPOL is turned off Default Each dPOL is equipped with a PLL that locks to the 500 KHz SD signal which is generated by the DPM This sets up for switching actions to be synchronous to the falling edge of SD by all dPOLs which are thereby kept coordinated to each other Figure 45 PWM Controller Window In some applications switching at higher frequencies is desirable even though efficiency is lower because it allows for better transient response or lower Although synchronized to SD switching frequencies application system noise of each dPOL in a system is independent of every other dPOL with the exception of shared load bus groups where are dPOLs sharing the load are WO BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com Page 24 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input 0 7V to 5 5V Output PN POWET ONE NS Changing the Shape of Power 7 7 2 Interleave Selection Within the same PWM dialog is the switching Interleave control Interleave is defined as a phase delay between the synchronizing slope of the master clock on the SD pin and the start of each dPOL PWM cycle This parameter can be programmed in the dPOL Controller Configure Compensation window or directly via the I C bus by writing into the INT register in 22 5 steps INT Interleave Configuration Address 0x04 R W 0 U R IW 0 RW 0 R W 0 R W 0 PRST PRS J FRO WW Wn WI T NTO Bit 0 Bit7 6
58. ting or non propagating Propagation and Latching for each dPOL is set in the GUI Figure 35 below or directly via the lC by writing into the PC1 register shown in Figure 36 Type Faut Output Sequencing Controller Trigger Enable Latching Propagate Tum Off Tracking Differential Critical OverTemperature v sequenced Over Curent V Critical Under Voltage gt Fal Sequenced Over Voltage v v Emergency Figure 35 GUI dPOL Fault Propagation Option Window If the non latching protection is selected a dPOL will attempt to restart every 130ms until the condition that triggered the protection is removed When restarting the output voltages follow tracking and sequencing settings If the latching type is selected a dPOL will turn off and stay off The dPOL can be turned on after 130ms if the condition that caused the fault is removed and the respective bit in the ST register was cleared or the Turn On command was recycled or the input voltage was recycled BCD 00259 Rev 1 0 12 Feb 2013 WWW power one com PC1 Protection Configuration Register 1 Address 0x00 R W 0 R IW 1 RW 0 R W 0 R W 0 RW 0 R W RW 1 Bit 7 Bit 0 Bit 7 TRE Tracking fault enable 1 enabled 0 disabled Bit 6 PVE Phase voltage error enable 1 enabled 0 disabled Bit 5 TRC Tracking Fault Protection Configuration 1 latching 0 non latching Bit 4 OTC Over Temperature Protection Configuration 1 latching 0 n
59. w Monitoring step on lz Sep z lz 03 05 13 Monitoring step on lz Sep z lz 03 05 14 Ready COO jJ CX Noor Figure 54 DPM Monitoring Window 8 Adding dPOLs to the System The dPOL converters are added to a dPWER system through the DPM Configuration Devices dialog Clicking on an empty address location brings up a menu which allows specifying which dPOL type is needed Figure 55 below is an example using all of the DP7000 series devices currently offered Note that Auto On P Monitor and S Monitor options are only configurable by Group and not by individual dPOL configuration These options affect only DPM behavior Enabling them does not burden a dPOL BCD 00259 Rev 1 0 12 Feb 2013 www power one com Auto On sets a group to turn on once all IBV power is available and dPOLs are configured P Monitor enables periodic query of Vout lout and Temp values from each dPOL in the group where it is enabled dPOLs will always measure these parameters in an ongoing basis even if Vout is not enabled S Monitor enables periodic query of dPOL Status While a DPM will always be able to detect a low OK condition it requires this option enabled for Monitor function to query status registers WO Page 29 of 37 DP7120 20A DC DC Intelligent dPOL Data Sheet 8V to 14V Input e 0 7V to 5 5V Output PN POWET ONE Changing the Shape of Power a Power ne LC 1 K1 Evaluation Hoard z1c Se L M ial LLL LI PRI
60. w ov pv Bit 7 Bit 0 Bit 7 TW Temperature Warning Bit 6 PG Power Good Warning high and low Bit 5 TR Tracking Fault Bit4 OT Over Temperature Fault Bit 3 OC Over Current Fault Bit 2 UV Under Voltage Fault Bit 1 OV Over Voltage Error Bit 0 PV Reserved Note an activated fault is encoded as 0 Writing a 1 into a fault error bit clears a latching fault error Figure 37 Protection Status Register ST 7 5 8 Fault and Error Propagation The feature adds flexibility to the fault management scheme by giving users control over propagation of fault signals within and outside of the system The propagation means that a fault in one dPOL can be programmed to turn off other dPOLs and devices in the system even if they are not directly affected by the fault 7 5 8 1 Fault Propagation When propagation is enabled a faulty dPOL propagates declaration of that even through pulling its OK pin low This signals to the DPM and any other dPOL connected to that signal that the dPOL has a Fault or Error condition A low OK line initiates turn off of other dPOLs connected to the same OK line with the same turn off behavior as the faulty dPOL The turn off type is encoded into the OK line when it transitions from high to low 7 5 8 2 Grouping of dPOLs dPWER dPOLs can be arranged in groups of up to 4 8 16 or 32 dPOLs depending upon the DPM model used Membership in a group is set in the GUI in the DPM Configu
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