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Altro User Manual

1. P XA gt BOs el pe TA gt Ra BG ri lL Figure 1 4 Tail Cancellation scheme The use of the Tail Cancellation Filter in the processing chain can be optional 13 1 5 Baseline Correction and Subtraction Il The second level of baseline correction is apply to the signal during the PTW and corrects signal perturbations created by non systematic effects which affect the signal This level of correction is based on a moving average filter This functionality is performed in two different levels one is the generation of the window to perform the average of the baseline acceptance window and the other is the correction itself The correction of the baseline is based on a Moving Average Filter The acceptance window is based on a double threshold scheme that follows the slow variations of the signal fig 1 5 Inside the acceptance window the baseline is corrected subtracting to a given sample the value done by the following equation Yxn M 7 6 k 0 J This value is the result of the moving average of a signal x n in the former case for a given sample is the average of this sample and the previous 7 When there is a fast variation in the signal like a cluster the samples are out of the acceptance window and therefore excluded from the baseline calculation In this case the value of the samples is corrected with the value calculated by the Average Filter for the last sample
2. exp T at z Is Z B3 i R z 2 The signal is passed through a linear network that cancels all but the fastest of the exponential terms The n 1 pole zero network has a transfer function that expressed in the Z domain is 1 exp T at 2 1 exp T at z F z 1 L z L z L z7 3 The numerator of F z will perfectly cancel all the poles of Is z except one The constants L1 L2 and L3 are chosen such that the numerator of the expanded form of Is z disappears The response of this linear network to the incoming signal is the convolution in the time of the impulse response function of the filter and the signal itself t is t f t e TF r t f t 4 One can easily observe from this expression that the performance of the tail cancellation is strongly related to r t The remaining fast exponential is a constraint of the system and can be chosen such that t e lt 0 1 t gt 1us 5 12 The filter considered is an IIR filter of order 3 The filter is composed of 3 first order filters in cascade The filter is flexible in the configuration of the digital signal processing operation by changing 6 programmable and accessible coefficients K1 K2 K3 L1 L2 and L3 for each filter The processing performed is shown in fig 1 4 ADC quantized n exponential Pole Zero Transfer Output of the input signal aproximation function in the Z Domain Digital Filter Result
3. SCpn 1 While the fixed mode and time dependent mode are exclusive any of them can be combined with the self calibrated mode as shown in table1 1 Conversion mode The circuit can perform a memory static conversion of the input signal of the type Yn F x At any cycle n the output yn depends at most on the input sample x at the same time but not on past or future samples of the input The output values y are stored in the baseline memory addressed in this case by the input values x The conversion mode can work concurrently to the self calibrated subtraction mode and to the fixed subtraction mode Test mode The LUT can be used to generate a pattern to be injected into the processing chain for test purposes On this test pattern which is replacing the input signal samples can be performed the subtraction of a constant value In the latter case the pattern generated is a stream of zeros Finally the BC1 circuit provide also the possibility of inverting the input signal polarity 1 s complement The pedestal memory is accessible in write and read mode throughout three registers Main Configurations din fod din ft cin scp fod din scp ft in foal ficin scp fpa te fa Fixed v NA Subtraction a v NA Mode Time dependent Self calibrated Conversion Mode NA Test Mode v Note din data input samples f t LUT data fpd fixed pedestal data value scp self calibrated pede
4. The price to pay is that the execution speed of the instructions depends on the frequency of the sampling clock Moreover if there is no sampling clock supplied to the chip the execution of the command will never be achieved and the interface will remain blocked In the following paragraphs the clock signal involved by default is the readout clock unless otherwise stated The Asynchronous Handshake Protocol All the instructions of the ALTRO are transmitted using a very simple protocol based on three control lines Command Strobe CSTB Write WRITE and Acknowledge ACKN The transaction is paced with the handshake of CSTB and ACKN The RCU holds the CSTB line low until the ALTRO asserts the ACKN line ACKN stays low until CSTB is de asserted In principle data and control lines can switch at any time although it is recommended to keep some distance from the rising edge of the clock to avoid metastability problems For any type of instruction the upper bits of the bi directional bus 39 20 must contain the addressing of the chip and the instruction code as shown in the table below 39 38 37 36 29 28 25 24 20 Parity BCAST BC AL Chip Address Channel Address Instruction Code The description of each field is presented in section 2 2 Register Write Instructions When writing a register the bits 39 20 of the bi directional bus must contain the address and the instruction code The argument is pla
5. It measures the difference Va between the ADC inputs V positive analogue input and V negative analogue input while it is insensitive to the absolute values of V and V provided within the ALTRO supply voltages Two reference voltages V top reference voltage and V bottom reference voltage define the dynamic range and the conversion gain accordingly We introduce hereafter some definition and the relationship between the input signal and the digital output code m Reference Range RR Vi Vpb m Dynamic Range DR RR RR m Conversion Gain CG 2 x DR 1024 m Digital Output Code Vyx CG 512 7 ADC Input VREF iv counts ADC Output ALICE TPC External Reference Vrern OV Veere Inom 1V Dynamic Range Veere Vrerm 2V Figure 1 3 A D converter signals and configuration Different configurations for driving the analogue inputs and connecting the reference voltages are discussed in section 2 1 As an example figure 1 3 shows the configuration that will be used in the ALICE TPC application 1 3 First Baseline Correction The first stage in the digital processing chain is the First Baseline Correction Unit BC1 The main task of the BC1 is to prepare the signal for the tail cancellation that takes place in the subsequent stage To this purpose the signal is corrected in order to remove perturbations of different nature The perturbations affecting the signal from th
6. chain to allow the testing of all the logic downstream without the need of an external analogue signal 10 The two aforesaid circuits allow for 3 different modes of operation subtraction mode conversion mode and test mode Some of these modes of operation can be combined allowing numerous configurations of the BC1 circuit The most relevant configurations have been summarised in table 1 1 while the complete list is reported in table 2 x Hereafter we describe the main modes of operation Subtraction mode In this mode of operation the BC1 performs the subtraction of spurious signals from the input signal values The subtracted signal can be fixed fixed subtraction mode time dependent time dependent subtraction mode or self calibrated self calibrated subtraction mode e In fixed subtraction mode the value to be subtracted from the input signal is constant and stored in a configuration register e In time dependent subtraction mode the time dependent pedestal values to be subtracted are stored in a memory pedestal memory that in this configuration is addressed by a time counter started by the trigger signal e In self calibrated subtraction mode the value to be subtracted is computed as cumulative average scp self calibrated pedestal of the input signal outside the processing time window _ SCPn 1 din 2 Upon the arrival of the first level trigger the value of the self calibrated pedestal is frozen in a register
7. 38 is set high The instruction will be executed by all the chips seeing that line high but it will not be acknowledged by any of them Per Channel Registers Reg Access Allo Name Add Type Bcas K1 1 o 16 6 Filter Coefficient K1 K2 01 16 Filter Coefficient K2 K3 02 16 Filter Coefficient K3 L1 03 16 Filter Coefficient L1 L2 04 16 Filter Coefficient L2 L3 05 16 Filter Coefficient L3 VFPED 06 20 Variable Fixed Pedestal Data PMDTA 07 10 Ped Mem Data for a given address ADEVL 11 16 Chip Address Event Length Meaning Nees s ZSTHR Offset Threshold ZS BCTHR Threshold HI Threshold LO MAU TRCFG Trigger Delay N Samples Event DPCFG ZSU MAU BSU configuration BFNPT 0C Filter Enable Buffer N Pre trigge Error Status Register ERSTR 10 20 TRCNT 12 16 R Trigger Counter PMADD oD 10 RW Pedestal Memory Address Table 2 3 Register set of the ALTRO Global registers contain parameters that are common to all the channels or relate to the common logic of the chip Channel registers contain parameters that are specific for every channel Command Set Y Clear Error Flags Table 2 4 Command set ERCLR 1D A detailed description of the register set is given in section 2 4 27 2 4 Register set The total number of registers implemented in the ALTRO chip is 137 Out of these 128 are channel specific that is a different version exists for each channel Th
8. DATA SS Es Ss eee 10 bit Words 10 S11 S12 T12 05 From a 10 bit word format to a 40 bit words format FORMAT DATA 40 bit Words 7 S10 S11 S12 T12 05 MEMORY O OSTE J f WRITE EN Figure 1 11 Data formatting procedure S11 S12 S13 S14 As it is shown in the fig 1 11 and fig 1 12 the 10 bit words are packed in 40 bit words If some data is missing to complete a 40 bit word an A hexadecimal pattern is used A 18 trailer completes the data packet which is the last 40 bit word of the data structure The trailer is composed of different relevant data The total number of 10 bit words in the packet 10 bits indeed this word provides the position of the last 10 bit word in the data packet and the hardware and channel address 8 and 4 bits respectively this address represents a sort of geographical address and is used in the data packet to identify unambiguously to which channel the data packet is associated The rest of the information is filled with a pattern A hexadecimal and it is made to have the information available in bytes 40 bit data words Trailer word 2AAA 10 bit w A Hard Add Figure 1 12 Back linked data block 19 1 8 Multi Event Buffer The dead time generated by a gaseous detector has two contributions detector dead time e g the drift time and front end electronics dead time readout dead time The multi event buffer scheme
9. The chip will drive the lower part to return the value All the 20 bits will be driven therefore if the value to be returned is less than 20 bits wide the remaining bits will be set to 0 Basic timing The CSTB line must be held low and the WRITE line high until ACKN is asserted The upper data lines must be valid during the assertion of CSTB The output data will be valid during the assertion of ACKN One clock cycle following the de assertion of ACKN the lower part of the data bus will be in high impedance ROHA PA AA E ah a E a tstsu 4 18TH tsTL gt CSTB tavsu 4 tADH gt BD 39 20 gt I tcHov gt l tcHoz BD 19 0 bh twrsu gt tWRH gt WRITE tcHkL tkLsH gt toHKH ACKN Figure x Read Instruction Chronogram Relaxed timing The set up time for CSTB can be zero The read cycle starts on the rising edge on which CSTB is sampled low The WRITE line and the data lines must be valid at least 2 ns before the next rising clock edge and kept valid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If CSTB is removed before ACKN is asserted the duration of ACKN will be only one clock cycle but output data will be available also just one cycle Deferring the de assertion of CSTB allows extending the time of valid output data The chip is ready for a new command one clock cy
10. inside the window ipii of h titer Bcoepiaoe mMm HO R B Data excluded from baseline calculation a t 2 PA Lt GNG i L 1 L i i L pi pmi Se srp eii mot Se a i aoe Figure 1 5 Moving Average Principle Next figure shows the effect over the baseline of the Adaptive Baseline Correction scheme 14 Adaptis Basa no Goreston culpa Tere supansion Iha hdd em as i H OM Am so 0 I0 na SO O HO HO Figure 1 6 Data after Adaptive Baseline Correction The use of pre sample and post samples to determine the exclusion window for the baseline calculation is foreseen 15 1 6 Zero Suppression One obvious way to compress the data stream is to discard zero data e g samples so close to the reference level pedestal that contain no useful information and can be considered as noise We are only concerned here with the elimination of the samples with no information the ones outside the pulses not with the removal of noise superimposed on the kept samples The basic pulse detection scheme is fixed thresholding samples of value smaller than a constant decision level threshold are rejected When a sample is found above the threshold it is considered the start of a pulse fig 1 7 THRESHOLD 0 Oo O O O O O O FLAG BIT Figure 1 7 Basic detection scheme To reduce the impulsive noise sensitivity a glitch filter checks for a consecutive number of samples above threshold confirming the existenc
11. manager config trg addr data trigger trg ctrl manager addr ctrl ADCO gt ADC Block o ADC7 16 CHROL analog pads ADC8 ds a output pa vm ADC Block 1 NP registers ADC15 digital ADC clock digital Readout clock Other main feature of the chip is the protection against the radiation effects Single Events of the most important state machines This protection is based on self detecting and correcting codes The purpose of this chapter is to give a short description of the most relevant circuits that are integrated in the ALTRO chip Most of the circuits presented in this section are functionally described in Chapter 1 3 2 Analog to digital conversion circuit The A D converter is a 10 bit up to 25 Msps sampling frequency combining high performances and low power consumption It is based on a pipeline architecture and consists of 9 internal stages in which the analog signal is fed and sequentially converted into digital data Each of the 8 first stages consist of an A D converter a D A converter a sample and hold and a gain of 2 amplifier The last stage is a comparator To recover from the conversion delay each resulting couple of LSB MSB of different stages is shifted An additional data correction stage completes the processing by recovering from the redundancy given in the previous stages Finally the data is outputted through digital buffers fig 3 2 Ea
12. we ne a 119 VINB10 PO_ANA Channel 10 Differential Input 120 Vinio PO_ANA Channel 10 Differential Input Le we sd 7 VSSCO ADC analog ground Channel 9 Differential Input 122 AVpp VDDIOCO ADC analog supply ADC analog ground Channel 8 Differential Input ADC analog ground ADC analog supply ADC analog ground ADC P well isolation ring bias Description Command Strobe Control Signal Write Control Signal Dedicated L1 Trigger Line Digital Ground Digital Voltage Supply BD2 O BD4CR Bi directional Data Line 2 DVpp VDDIOCO Digital Voltage Supply RDOCLK IBUF Readout Clock Input t4 naw 146 DGND VSSIOCO Digital Ground 16 15 DVop 156 ADCCLK DGND 158 BD15 i5 BDi7 160 BDis 161 BDis e2 BD BD BD DVpp 166 DGND 167 BDs 168 BD to BD 170 DOLO_EN 171 TRSF_EN 172 ACK_EN Bi directional Data Line 4 a Bi directional Data Line 8 Bi directional Data Line 10 Bi directional Data Line 14 Bi directional Data Line 16 Bi directional Data Line 18 VDDIOCO Digital Voltage Supply l IBUF ADC Clock Input VSSIOCO Digital Ground O BD4CR Bi directional Data Line 19 O BD4CR Bi directional Data Line 17 O BD4CR Bi directional Data Line 15 O BD4CR Bi directional Data Line 13 O BD4CR Bi directional Data Line 11 O BD4CR Bi directional Data Line 9 O BD4CR
13. 1 K zT 1 K z F z YOsK L c1 The input and output of the filter is in 11 bit 2 s complement format The filters use 18 bit fix point format to reach a higher accuracy 62 3 5 Adaptive Baseline Correction circuit The Active Baseline Correction circuit is integrated in the data path This circuit has two main blocks a double threshold scheme and a moving average filter fig 3 6 The double threshold scheme is composed of two comparators and two adders The value of the thresholds follows the baseline by adding the output value of the moving average filter It is important to remark that this added value corresponds to the one calculated for a sample 4 cycles before this allows to have post samples and pre samples in the generation of the exclusion window fig 1 5 This circuit enables the moving average filter and therefore determines the window for the adaptive baseline correction The input signal is converted to an unsigned signal by adding 1024 this simplifies the architecture of the moving average filter 1024 clip Z gt dout 4zi din MA 8 avg control plen Filter logic config Figure 3 6 Adaptive Baseline Correction circuit At the output the signal is clipped to a range between O and 1023 The values above zero are set to O The offset can be useful to keep the information above O which is lost when cli
14. 18 153 BD16 152 BD14 151 BD12 TQFP176 ALTRO GND 58 BD33 59 BD34 60 BD35 61 BD36 62 BD37 63 BD38 64 BD39 65 VDD 66 GND 67 TSTOUT 88 VDD Pin AnDosenpuon AGND AVop GND 69 BD20 70 BD21 71 BD22 72 BD23 73 BD24 74 BD25 75 BD26 76 150 BD10 149 BDos 148 BDos 147 BD04 141 ACKN WRITE 145 RDOCLK 144 VDD 143 BD02 142 BDoo 140 DSTB 139 TRSF 138 VDD 137 GND 136 GND 135 LVLi 134 146 GND VDD 7 GND 78 BD27 79 BD28 80 BD29 81 82 VDDJ 83 GND 84 HADD4 85 HADD5 86 HADD6 87 HADD7 88 ERROR 133 CSTB SHIELD AGND AVCC AGND VIN8 VINB8 AGND VIN9 VINB9 AGND AVCC NG VIN10 VINB10 NG AGND AVCC VINI VINB11 AVCC INCM REFP AGND 109 REFM 103 Nc AVCC 106 VIN12 VINB12 AVCC AGND NG VIN13 100 VINB13 99 _ avcc 98 AGND NG 1 96 VIN14 VINB14 AGND VIN15 VINB15 191 J AGND 90 avcc 89 SHIELD ADC P well isolation ring bias ADC analog ground ADC analog supply nail ran lan ba VSSCO ADC analog ground PO_ANA Channel 0 Differential Inout PO_ANA Channel 0 Differential Input VSSCO ADC analog ground PO_ANA Channel 1 Differential Inout PO_ANA Channel 1 Differential Input VSSCO ADC analog ground VDDIOCO ADC ana
15. 19 7 6 5 4 3 0 X PWSV FLT_EN NBUF PTRG Description Parameter Description Range PTRG Number of Pretrigger Samples 0 F NBUF Number of Buffers in Data Memory 4 8 0 1 FLT_EN Enable the Digital Filter 0 1 PWSV Power Save When set stops data processing outside trigger windows 0 1 Notes e The Power Save bit may reduce the power consumption dramatically under certain data path configurations 38 Pedestal Memory Address PMADD Instruction Code OD h Width 10 Register Type Global Access Type Read Write Allow Broadcast Yes Instruction Coding 39 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS x oD 19 10 9 0 X PMA Description Parameter Description Range PMA Address of the Pedestal Memory to be read written 0 3FF Notes The value set in PMA is common for all the channels Therefore the recommended strategy to fill up the Pedestal Memories is to write the PMA first and then the corresponding data across all the 16 channels This sequence is repeated until all the memories all filled up Before writing or reading the Pedestal Memory make sure that the First Baseline Correction is in a mode that does not access the memory otherwise data will be corrupted The recommended operation mode is din fpd 39 ERSTR Error and Status Register Instruction Code 10h Width 20 R
16. Bi directional Data Line 7 VDDIOCO Digital Voltage Supply vssioco Digital Ground O BD4CR Bi directional Data Line 5 O BD4CR Bi directional Data Line 3 O BD4CR Bi directional Data Line 1 O BT4CR External Driver Output Enable O BT4CR External Driver Output Enable External Driver Output Enable refer to section 4 X for implementation details 4 5 Recommended PCB Design The layout of the chip has been optimised to minimise the influence of the digital circuitry on the integrated ADCs ETT PTE TT 4 6 Chip Layout 7 7mm ADC Channel 0 WW 8 ADC Channel 7 Data Memory Processing Pedestal Memory Logic 19 20
17. CERN EP ED ALICE TPC Readout Chip User Manual CERN June 2002 DRAFT 0 2 INDEX Introduction Chapter 1 11 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 Introduction Analogue to digital conversion Baseline Correction and Subtraction Tail Cancellation Filter Baseline Correction and Subtraction Il Zero Suppression Data Format Multi Event Buffer Trigger Handling Chapter 2 2 1 2 2 2 3 2 4 2 5 2 6 2 7 Introduction ALTRO bus Signals Instruction set Registers set Command Set Control Protocol Modes of Use and Operation Chapter 3 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 Introduction Analog to digital conversion circuit Baseline Subtraction circuit Tail Cancellation Filter circuit Adaptive Baseline Correction circuit Zero Suppression circuit Data Format circuit Multi Event Buffer circuit 5 6 10 12 14 16 18 20 21 22 22 23 26 50 53 54 57 58 58 59 60 62 63 65 66 67 3 9 Hamming State Machines Introduction Functional Description 1 1 Introduction The ALTRO ALICE TPC Read Out chip is a mixed analogue digital custom integrated circuit dedicated to the digitisation and processing of gaseous detector signals It contains 16 channels operating concurrently on the analogue signals coming from 16 independent inputs Upon arrival of a first level trigger each input signal is sampled processed and stored in a data memory The
18. Code 08h Width 20 Register Type Global Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS X 08 19 10 9 0 OFFSET ZS THR Description Parameter Description Range OFFSET Offset to be added to the signal 0 3FF ZS_THR Zero Suppression Threshold 0 3FF Notes Before the zero suppression any negative value of the signal is coerced to O If there is the need to explore these negatives values an offset must be added so that they become positive 33 BCTHR Second Baseline Correction Thresholds Instruction Code 09h Width 20 Register Type Global Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS X 09 19 10 9 0 THR HI THR_LO Description Parameter Description Range THR_LO Upper threshold of the acceptance window 0 3FF THR_HI Lower threshold of the acceptance window 0 3FF Notes 34 TRCFG Trigger Configuration Instruction Code OA h Width 20 Register Type Global Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS X OA 19 10 9 0 ACQ START ACQ_END Description Parameter Description Ran
19. DH gt WRSU Na tWRH gt tkLsH gt toHKL gt toHKH ACKN Figure x Command chronogram The dumping of the data memory commonly named readout is the only operation that is executed synchronously During the readout the ALTRO becomes master of the bus and no other operation can take place in between The readout is initiated by the RCU sending the readout command to the chip This is done using the asynchronous protocol like for any other instruction A few clock cycles after the acknowledging of the readout command the ALTRO asserts the TRSF line to indicate that it has the control of the bus and the data dump starts one clock cycle later The execution of this command does not involve the sampling clock at all therefore the timing if fixed relative to the readout clock Basic timing The CSTB and WRITE lines must be held low until ACKN is asserted The upper data lines must be valid during the assertion of CSTB Three clock cycles after the de assertion of ACKN the chip will start driving the 40 data lines On the following clock cycle TRSF will be asserted and output data will be valid on each falling edge of DSTB One clock cycle after the de assertion of TRSF the data bus will be in high impedance Relaxed timing The set up time for CSTB can be zero The command cycle starts on the rising edge on which CSTB is sampled low The WRITE line and the BD 39 20 lines must be v
20. Data Format B circuits In the former circuit the timing information and the number of samples per cluster are added In the latter circuit all the information is packed in 40 bit words and the trailer added with additional information The Data Format A block corresponds in fig 3 9 to the logic controlled by the Control A finite state machine This state machine controls the insertion of the time stamp and the number of 10 bit words in each cluster cluster length cnt The samples in a cluster are validated by the flag and twx signal The Control B finite state machine controls the Data Format B block The state machine controls the placement of 10 bit data words to complete the new 40 bit data words with the possibility of adding a pattern 2AA hexadecimal when needed It also controls the insertion of the trailer word The event length counter calculates the total number of 10 bit word in the 40 bit data packet This value is a part with the hardware and channel address of the trailer word A pattern A hexadecimal fills the unused bits of the trailer word event length Ti en Gu clr gt Control B FSM Control A gt FSM cluster length st gt en ent A 10 en 40 p dout A Figure 3 9 Data Format circuit 66 3 8 Multi Event Buffer circuit The Multi Eve
21. Fixed Pedestal per Channel Variable and Fixed Pedestal used in the baseline unit First baseline correction unit If the correct mode is used the input signal coming from the ADC will be subtracted to FPD or VPD Both are coded in 10bit each The variable pedestal can only be read the fixed one can be both read and written PMDTA Pedestal Memory Data per Channel Data to be stored in the Pedestal Memory of each one of the 16 channels The memories are cuts of 1Kx1 Obit and can be used in different modes see register DPCFG ADEVL Chip address and Event Length Read only The 8bit channel address can be read from AD 15 8 The Event Length for a given channel is coded in the lower 8 bit of the address space ZSTHR Offset and relative threshold of the Zero Suppression Global The Offset higher 10bit enables the signal to sit in a higher baseline so that negative variations can be seen The samples below the threshold lower1 Obit are suppressed This register has a direct influence on the amount of data transmitted and the number of samples event stored in the memory BCTHR Double threshold of the Moving Average Filter Global The higher 10bit correspond to the upper threshold and the lower 10bit to the bottom threshold The range in between these two levels is indeed an estimation of where the baseline really is The average baseline is calculated whenever the input signal lies in that range TRCFG Trigger delay and Nu
22. REFp Dir Pad Type VSSIOCO Digital Ground O BD4CR Bi directional Data Line 27 O BD4CR Bi directional Data Line 28 O BD4CR Bi directional Data Line 29 O BT4CR Error Output Line VDDCO Digital Voltage Supply VSSCO Digital Ground BUF ALTRO Hardware Addressbit4 IBUF ALTRO Hardware Address bit 5 IBUF ALTRO Hardware Address bit 6 l IBUF ALTRO Hardware Address bit 7 VSSCO ADC P well isolation ring bias VDDCO ADC analog supply VSSCO ADC analog ground PO_ANA Channel 15 Differential Input PO_ANA Channel 15 Differential Input VSSCO ADC analog ground PO_ANA Channel 14 Differential Input PO_ANA Channel 14 Differential Input VSSCO ADC analog ground VDDIOCO ADC analog supply PO_ANA Channel 13 Differential Input PO_ANA Channel 13 Differential Input VSSCO ADC analog ground VDDIOCO ADC analog supply PO_ANA Channel 12 Differential Input PO_ANA Channel 12 Differential Input VDDCO ADC analog supply PO_ANA Positive rail reference VSSCO ADC analog ground PO_ANA Negative rail reference PO_ANA Common Mode Bias 15 Pin Numbe Pin Name Pad Type Description 113 AVpp VDDCO ADC analog supply ita Vien PO ANA Channel 11 Differential Input 115 Vina PO_ANA Channel 11 Differential Input AVpp VDDIOCO ADC analog supply 117 AGND VSSCO ADC analog ground
23. STS 0 o o o o O HRD o oo oo o o FLAG BIT Figure 1 10 Merging of close clusters 17 1 7 Data Format The stream of zero suppressed data must be formatted by adding to each set of samples two extra words and encoding the 10 bit words and hardware address into a 40 bit set of words As it was mentioned in the previous paragraph due to the removal of a variable number of samples between accepted clusters the timing information would be lost during the zero suppression process This requires the addition of a time data to each accepted set of samples Since 1000 is the maximum length of the data stream that can be processed by the ALTRO chip the time information can be encoded in a 10 bit word The principle is to label each sample with a time stamp that defines the time distance from the trigger signal So the samples of the processed data stream are numbered starting from 0 to 1000 The time information added to each cluster during the formatting phase corresponds to the time stamp of the last sample in the cluster The ALTRO data format does not make use of extra flag bits to distinguish the samples data from the time data but introduces a further word for each accepted cluster which represents the number of words in the cluster without counting the time data These new 10 bit words time data and number of samples per cluster are introduced at the end of the cluster fig 1 11 ADC SAMPLES THRD SAMPLES FORMAT
24. The VPD is calculated by the Self Calibration circuit when the ALTRO is not processing a trigger This value can be read out for monitoring purposes but not written The FPD can be written and read back Either or both of them can be subtracted from the ADC data stream if the proper configuration is selected in register DPCFG 31 PMDTA Pedestal Memory Data Instruction Code 07h Width 10 Register Type Channel Local Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS CHANNEL ADDRESS 07 19 10 9 0 X Data Description Parameter Description Range Data Data to be written to or read from the Pedestal Memory 0 3FF Notes Data written to or read from this register is routed to from the Pedestal Memory of the corresponding channel at the address specified in the global register PMADD PMADD is common for all the channels Therefore the strategy to fill up the Pedestal Memories is first to write the address and then the data for that address across all the 16 channels The procedure is repeated again for each address Before writing or reading the Pedestal Memory make sure that the First Baseline A Correction is in a mode that does not access the memory otherwise data will be corrupted The recommended operation mode is din fpd 32 ZSTHR Zero Suppression Threshold and Offset Instruction
25. Type Global Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS Xx 18 19 0 XorZ Description This command is equivalent to the Level 2 Trigger Accept The effect of this command is to freeze in one of the buffers of the data memory the data taken after the last Level 1 Trigger This is done by increasing the Write Pointer that points to the memory position where data is to be written when a L1 is received Notes WPINC must be issued only after the acquisition of the event is achieved Data will A be corrupted and not retrievable if the WPINC is issued while the chip is still recording data Refer to Chapter 4 for timing specifications ii If an event is to be kept in memory the WPINC command must be issued before the next L1 trigger arrives 44 RPINC Read Pointer Increment Instruction Code 19h Command Type Global Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS X 19 19 a XorZ Description This command releases a buffer of the Data Memory making it available for writing new data Buffers are used and released on a FIFO basis therefore this command will free the first read or unread buffer Notes done Once the command is executed there is no way to recover the data stored RPINC is intended to be issued after the readout of all the channels has been in the release
26. alid at least 2 ns before the next rising clock edge and kept valid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If CSTB is removed before ACKN is asserted the duration of ACKN will be only one clock cycle Three clock cycles after the de assertion of ACKN the chip will start driving the 40 data lines On the following clock cycle TRSF will be asserted and output data will be valid on each falling edge of DSTB One clock cycle after the de assertion of TRSF the data bus will be in high impedance On Nf a TA AA UA ae Ne SE A A Ny tsTSU fe STH tsTL gt CSTB lt twasu gt tWwrH gt WRITE toHKL tkLsH gt toHKH ACKN tansu gt I tADH gt gt tcHoL itdHov gt i tcHoz gpjs0 0 TH HTH a tn Lol tero gt toHDH PETE Ga NGAY Nash NY sl tour gt toHTH TRSF N Am yjdcdLdL5J5iV er Figure x Chronogamof the redout conmand Digital Logic Timing Parameters Test J 5 Symbol Parameter Conditions Min Typ Max Unit froo Readout clock frequency 40 50 MHz Readout clock period 20 25 ns ADC clock period 40 100 ns tonk Clock high to ACKN low 6 ns tcHKH Clock high to ACKN high Clock high to TRSF low tcHTH Clock high to TRSF high tcHOL Clock high to Output Data low Z tcHov Clock high to Output Data valid tcHo
27. alid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If CSTB is removed before ACK is asserted the duration of ACK will be only one clock cycle Three clock cycles after the de assertion of ACK the chip will start driving the 40 data lines On the following clock cycle TRSF will be asserted and output data will be valid on each falling edge of DSTB One clock cycle after the de assertion of TRSF the data bus will be in high impedance Broadcast instructions As we have seen the chip is controlled by a set of 6 commands and Read and Write Registers operations In general a command is issued by the Control Unit and executed by a single ALTRO chip single chip cycle however the writing in a register and send an instruction can be executed by several ALTROs simultaneously broadcast cycle The BROADCAST instructions which are executed by several ALTROs concurrently are not acknowledged and are enabled by setting the bit AD 38 to 1 when sending an instruction The RCU waits a sufficient amount of time to all the ALTROs execute the instruction Not all instructions are allowed in broadcast mode tables 2 3 and 2 4 show which ones can be transmitted to all the ALTROs 56 2 8 Modes of Use and Operation There are two modes of operation Test Mode and Run Mode The line TMS controls the mode TMS 0 Test Mode TMS 1 Run Mode The Run Mode can be divided in different and non over
28. amples event value 1024 samples event 3FF 3FF 111 370 36F 1g 110 300 300 2FF 2FF 101 270 26F 100 100 200 200 1FF 1FF 011 170 16F 010 010 100 100 OFF OFF 001 070 06F 000 000 000 000 Figure 3 10 Multi Event buffer structure LVL1 LVL2 LVL1 LVL2 readout a a a d B d E pi a wr we rd rd rd inc LVL1 LVL1 LVL2 rd inc a af a a a wr wr wr wr wr rd rd rd rd rd non secured data secured data Figure 3 10 Multi E vent Buffer operation The above figure shows the Multi Event Buffer operation and pointer management and the trigger handling When a LVL1 signal is receive 1 2 the data is stored in the memory 2 but it must be validated by a LVL2 signal 2 3 A CHRDO command is needed to read the data 5 6 but to free the buffer it is necessary an extra command RPINC 6 7 It is also possible to discard data even when it was validated using the RPINC command 10 11 68 3 9 Hamming State Machines The most important state machines of the ALTRO chip the Memory Management State Machine and the Interface State Machine are protected against the radiation effects as Single Event Upset SEU effects These effects can cause an erroneous behaviour on the circuit state and therefore on the outputs The methodology adopted is base on a constant Hamming distance between the present and next state assignments The symbols to code the states are based on a single er
29. and and only the bits 39 20 of the bi directional bus are driven the rest being left in high impedance When an argument is to be supplied this is placed in the lower 19 0 bits of the bi directional bus This difference however does not affect the timing of the signals Basic timing The WRITE and CSTB lines must be held low until ACK is asserted Data lines must be valid during the assertion of CSTB Relaxed timing The set up time for CSTB can be zero The write cycle starts on the rising edge of RDOCLK on which CSTBis sampled low The WRITE line and the data lines must be valid at least 2 ns before the next rising clock edge and kept valid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If CSTB is removed before ACK is asserted the duration of ACK will be only one clock cycle The chip is ready for a new instruction one clock cycle after ACK is high For the ALTRO chip all write instructions except the readout command involve an internal transaction at the SCLK speed Therefore the duration of an instruction from CSTB asserted to ACK de asserted will depend on the frequency of the SCLK If no SCLK is supplied to the chip the command will never be accomplished and the interface will remain blocked 54 RDOCLK JN eS a Mee ee AN tstsu ka tsTH gt tsTL gt CSTB NN ke tapsu na tADH gt BD 39 0 AF
30. aster controller and FEC as a carrier of 8 ALTROs 22 2 2 ALTRO bus Signals The most relevant ALTRO bus signals are summarized in table 2 1 A more detailed description of the bus signals is given hereafter ALTRO BUS Signal Name AD Address Data 4o Bi directional H WRITE Write Read a input L CSTB Command Strobe 1 ACKN Acknowledge 4 L ERROR Error 1 L TRSF Transfer 1 L DSTB Data Strobe 1 Output L LVL1 Level 1 Trigger Input L LVL2 Level 2 Trigger Input L GRST Global Reset 1 mme L SCLK Sampling Clock 1 Input RCLK Readout Clock 1 Table 2 1 Signal summary AD 39 0 bi directional This is a 40 bit bi directional Address Data bus table 2 2 It consists of three main fields that starting from the least significant bit are organised as follows the data field 20 bits the instruction field 5 bits and the address field 14 bits The most significant bit is a parity bit It should be noted that with a 14 bit address field the ALTRO bus space sizes 16384 This addressable space is divided in two equal size partitions the ALTRO chips partition AL partition and the Board Controller partition BC partition 39 38 37 36 29 28 25 24 20 19 0 Bag Table 2 2 40 bit bi directional Address Data bus AD 39 PAR is the parity bit of the 20 most significant bits It is set such that the parity of the 20 most significant bits is alwa
31. before ACK is asserted the duration of ACK will be only one clock cycle but output data will be available also just one cycle Deferring the de assertion of CSTB allows extending the time of valid output data The chip is ready for a new command one clock cycle after ACK is high 55 Readout Command The data dump takes place immediately after the acknowledging of the readout command The execution of this command does not involve the SCLK at all therefore the timing if fixed relative to the readout clock Fig 2 3 sketches the timings for the Readout command Basic timing The CSTB and WRITE lines must be held low until ACK is asserted The upper data lines must be valid during the assertion of CSTB Three clock cycles after the de assertion of ACK the chip will start driving the 40 data lines On the following clock cycle TRSF will be asserted and output data will be valid on each falling edge of DSTB One clock cycle after the de assertion of TRSF the data bus will be in high impedance Lofton laosu gt taDH L Hov gt tcHoz eocen o OO Lote Lion Lto Lofton Figure 2 3 Readout chronogram Relaxed timing The set up time for CSTB can be zero The command cycle starts on the rising edge on which CSTB is sampled low The WRITE line and the AD 39 20 lines must be valid at least 2 ns before the next rising clock edge and kept v
32. can reduce the second contribution The system dead time depends on the dimensions of the front end multi event buffer The processed data stream is stored in a memory to be eventually read out This memory 1024x40 bits wide is partitioned in a programmable number N of blocks Each data stream will be stored in the next available memory block When all the memory blocks are occupied a full signal is generated to ignore the commands to process new data streams The number N of blocks can take the following 2 values 4 and 8 The size of the memory allows storing 4 complete events without zero suppressed data The way the data streams are sorted and recovered from the memory is completely transparent to the user In any case the status of the memory empty and full is available in the chip status register 20 1 9 Trigger Handling In a high energy physics experiment only a fraction of occurring events provides useful information The trigger system evaluates the event on line and provides an accept signal when the event is relevant Only those events are recorded and are available for later off line analysis The trigger information is received in the Readout Control Unit RCU and then distributed to the ALTRO chips by means of two signals The first one LVL1 starts the data processing the event triggered is also stored in the multi event buffer The second signal LVL2 validates the data stored this signal always refers to the pr
33. ced in the lower 19 0 bits of the bus Basic timing The WRITE and CSTB lines must be held low until ACKN is asserted Data lines must be valid during the assertion of CSTB Relaxed timing The set up time for CSTB can be zero The write cycle starts on the rising edge on which CSTB is sampled low The WRITE line and the data lines must be valid at least 2 ns before the next rising clock edge and kept valid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If CSTB is removed before ACKN is asserted the duration of ACKN will be only one clock cycle The chip is ready for anew command 1 clock cycle after ACKN is high All write instructions and commands except the readout command involve an internal transaction at the ADC clock speed Therefore the duration of a command from CSTB asserted to ACKN de asserted will depend on the frequency of the ADC clock If no ADC clock is supplied to the chip the command will never be accomplished and the interface will remain blocked BOG ye Nese a NL Nag Nd NL Nee ey tapsu pa TADH gt BD 39 20 ke twrsu sh twrH gt WRITE tkLsH gt tCHKL gt toHkH ACKN Figure x Write Instruction Chronogram Register Read Instructions During a read instruction the master must drive the upper half of the data bus bits 39 to 20 and leave the lower half in high impedance
34. ch block of 8 A C converters has an internal reference It is possible to use an external reference voltage instead of the internal one VREFP VREFM The power consumption can be optimised according to the sampling frequency by placing a resistor between IPOL and the analog ground pin VREFP a NG wan Reference om fh G m VINB ae arenes E VREFM Sequencer phase shifti ng pn KN gt Digital data correction aaa gt gt DO Buffers TO gt bao D9 Figure 3 2 A D converters block diagram 59 3 3 Baseline Subtraction circuit As it is shown in fig 3 3 the baseline subtraction circuit is based on a LUT Pedestal Memory of 1kx10 bits wide the Autocal circuit a set of multiplexers which control the modes of operation described in table 1 1 and a 10 bit adder vpd sample ee S 1K x 10 autocal j twx Figure 3 3 Baseline Subtraction circuit A set of bits controls the circuit bo b4 control the modes of operation control of the multiplexers These bits are decoded from a Configuration Register BSU Mode DATAPATH_CFG Register bs allows the user to control the polarity 1s complement of the signal Polarity DATAPATH_CFG Register be allows the user to set the data path to zero in between events to avoid high activity in the Tail Cancellation F
35. cle after ACKN is high All write instructions and commands except the readout command involve an internal transaction at the ADC clock speed Therefore the duration of a command from CSTB asserted to ACKN de asserted will depend on the frequency of the sampling clock If no sampling clock is supplied to the chip the command will never be accomplished and the interface will remain blocked Commands A command is very similar to a register write operation the only difference being that there is no argument to be transmitted in the lower 20 bits of the data bus The RCU must only drive the upper 20 bits to supply the address and the command code Basic timing The WRITE and CSTB lines must be held low until ACKN is asserted Data lines must be valid during the assertion of CSTB Relaxed timing The set up time for CSTB can be zero The write cycle starts on the rising edge on which CSTB is sampled low The WRITE line and the data lines must be valid at least 2 ns before the next rising clock edge and kept valid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If 5 BD 39 20 I WRITE Readout CSTB is removed before ACKN is asserted the duration of ACKN will be only one clock cycle The chip is ready for anew command 1 clock cycle after ACKN is high POU ade ay ee A ed AA AA tstsu 4 tsTH gt tsTL gt CSTB tapsu gt lt ta
36. d buffer 45 CHRDO Channel Readout Instruction Code 1Ah Command Type Per Channel Allow Broadcast No Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS CHANNEL ADDRESS 1A 19 0 XorZ Description This command produces the readout of the specified channel The readout starts immediately after the command is acknowledged During the readout the ALTRO becomes the owner of the bus Notes After CHRDO is acknowledged the RCU should not issue any further instructions and must wait for the TRSF line to go low i The readout may be interrupted if a L1 trigger is received on its dedicated line Therefore the RCU must wait for the completion of the acquisition and then continue to store the readout 46 SWTRG Software Trigger Instruction Code 1Bh Command Type Global Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS x 1B 19 y XorZ Description This command sends a Level 1 trigger to the processing chain of the chip It is entirely equivalent to the dedicated L1 line except that the timing depends on both the readout and the sampling clocks Notes This command is provided for testing purposes In normal operation mode the dedicated L1 line should be used 47 TRCLR Clear Trigger Counter Instruction Code 1Ch Command Type Global Allow Broadcast Yes In
37. e interface to the external bus sticky bit INT 2 SEU Two Single Event Upsets have been detected in the state machine that controls the interface to the external bus sticky bit RDO Error A readout command has been received when there was nothing to read out sticky bit Notes Single Event Upsets SEU will only occur in the presence of radiation If a SEU happens the affected state machine will recover automatically If a double SEU is detected the corresponding state machine has interrupted its logical sequence and gone to idle state The chip must therefore be reset when possible All of the error bits are sticky that is they remain in the 1 state after they are set The error bits are reset when the chip is reset or powered off or the ERCLR command is issued When running in 4 buffer mode the Write Pointer and Read Pointer can only take the values 0 2 4 or 6 In the 8 buffer mode they take all values between 0 and 7 The number of remaining buffers ranges from 0 to 4 in the 4 buffer mode and from 0 to 8 in the 8 buffer mode Valid instructions can produce an instruction error if they are issued in the wrong mode e g broadcasting a register read or writing a read only register When the FULL flag is set any further L1 or L2 triggers will be ignored The Readout Controller Unit must take care of filtering the triggers and avoiding this situation Nevertheless if a lost L1 trigger was to be identified the user can chec
38. e a programmable number of samples before the trigger pre trigger samples can be stored by enlarging the PTW This feature allows the compensation of the trigger latency to the extent of 15 times the sample clock period The ALTRO chip interfaces to the external world through 16 analogue inputs a 40 bit bi directional bus and 8 control signals The bus protocol is asynchronous for instructions with a 2 line handshake The readout however is a synchronous block transfer that allows a rate of up to 300 MBytes s 1 2 Analogue to digital conversion The Analogue to Digital Converter is based on a commercial ADC the ST Microelectronics TSA1001 4 slightly modified to suit the ALTRO application It has a 10 bit dynamic range and up to 25 MHz sampling rate The ADC has a pipelined architecture consisting of 9 internal conversion stages in which the analogue signal is fed and sequentially converted into a digital code The input analogue signal is sampled on the clock rising edge while the output digital code is issued on the clock s falling edge As sketched in figure 1 2 the delay between the initial sample of the input signal and the corresponding output code data latency is 5 5 clock cycles UWUUVUUVUW Tpd Tod OEB A U S SE AA HZ state Figure 1 2 ADC timing diagram As it will be described in more detail in section 2 1 and 3 1 the ADC is based on a fully differential circuit
39. e gas chamber can be m Low frequency spurious signals in the range of less than one kilohertz They perturb the detector signal by shifting its baseline by an amount that inside the processing time window PTW is almost constant less than one ADC count This type of signal perturbation could be for instance the one produced by a temperature variation of the electronics components acq 1 acq 2 acq 3 acq 4 acq 5 long term perturbation m Signal perturbations created by systematic effects like those related to the triggering of the detector which affect the signal in terms of a superimposed noise pattern useful signal perturbation To cope with the first effect a self calibration circuit is implemented right at the output of the ADC It tracks continuously the signal outside the PTW computing its cumulative average Upon the arrival of the first level trigger the averaging process is interrupted and its last value used as self calibrated offset to be subtracted to all the samples inside the PTW To remove systematic effects a pattern memory is used Every time the chip starts an acquisition the values stored in this memory are subtracted from the input signal thus removing systematic perturbations Alternatively this memory can be used as a Look Up Table LUT to perform non linear conversion or to equalise the response across different channels As a test feature this memory can inject a pattern in the processing
40. e instruction does not imply a data transfer from to the addressed unit thus the data field of the AD bus is not used The data field AD 19 0 carries the data in the WRITE or READ instructions WRITE Input The write read signal is driven by the master RCU and defines whether the access to the addressed unit is in write read mode low high CSTB Input The master RCU drives the command strobe CSTB signal When asserted it indicates that a valid word has been placed in the AD bus The signal also qualifies the WRITE signal The master only releases the CSTB signal after the slave has asserted the ACKN signal The only exception is represented by the broadcast Instruction cycles for which there is no acknowledge In the latter case the master will keep the information on the bus and will validate it with the CSTB signal for at least 2 RCLK cycles ACKN ACKN EN Output On a WRITE or COMMAND cycle the addressed unit asserts the ACKN signal to indicate that is has successfully latched the bus content and executed the requested instruction On a READ cycle the addressed unit asserts the ACKN to indicate that it has placed the requested data on the bus The only exception is represented by the broadcast instruction that does not have to be acknowledged A signal ACKN_EN frames ACKN enabling the intrinsic capacitor in the transceiver ERROR Output The ERROR line is asserted by the slave units to signal the occurrence of an err
41. e of a real pulse fig 1 8 The minimum sequence of samples above the threshold MINSEQ which defines a pulse can vary from 1 to 3 MINSEQ 2 e THRESHOLD Figure 1 8 Glitch filter In order to keep enough information for further feature extraction the complete pulse shape must be recorded Therefore a sequence of samples pre samples before the signal overcome the threshold and a sequence of samples post samples after the signal returns below the threshold are also recorded fig 1 9 The number of pre samples PRES and the number of post samples POSTS can vary independently in the range between 0 and 4 16 PRES 2 POSTS 3 o THRESHOLD oO Oo O QO O O O O FLAG BIT Figure 1 9 Feature extraction The pulse thus identified and isolated must be tagged with a time stamp in order to be synchronised with the trigger decision for validation Otherwise the timing information would be lost by the removal of a variable number of samples between accepted pulses This requires the addition of a time data to the set of sample data Besides that in a data format where the addition of flag bits is not allowed a further word is needed to distinguish the sample data from the time data This extra word represents the number of words in the set Since for each new set of data we have two extra words the merging of two consecutive sets which are closer than 3 samples is performed fig 1 10 PRES 2 PO
42. egister Type Global Access Type Read Only Allow Broadcast No Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS x 10 19 18 17 16 15 RDO Error INT 2 SEU INT 1 SEU MMU2SEU MMU1SEU 14 13 le Trigger Overlap Instruction Error Parity Error 11 10 9 6 5 3 2 0 EMPTY FULL Remaining Buffers Write Pointer Read Pointer Description Parameter Description Read Pointer Pointer to the buffer that is to be read out Write Pointer Pointer to the buffer that is to be written on next trigger Remaining Buffers Number of empty buffers remaining in the Data Memory FULL Flag signalling that all the buffers of the memory are filled with valid event EMPTY Flag signalling that all the buffers of the memory are available for writing Parity Error A parity error has been detected while decoding an instruction sticky bit Instruction Error An illegal instruction has been received sticky bit 40 Trigger Overlap A trigger pulse has been received during the processing window of a previous trigger sticky bit MMU 1 SEU One Single Event Upset has been detected in the state machine that controls the buffers of the Data Memory sticky bit MMU 2 SEU Two Single Event Upsets have been detected in the state machine that controls the buffers of the Data Memory INT 1 SEU One Single Event Upset has been detected in the state machine that controls th
43. ere are 8 channel specific registers for each of the 16 channels 8 x 16 128 The remaining 9 registers contain parameters that are either common for all the channels or relative to the common logic of the chip The PMD register is not a true register but a gateway to access the pedestal memories Writing to or reading from this register 28 Filter Coefficient K1 Instruction Code 00h Width 16 Register Type Channel Local Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS CHANNEL ADDRESS 00 19 16 15 0 X K1 coefficient Description Parameter Description Range K1 is the filter coefficient defining the position of the zero for the first 0 FFFF KI stage Notes The relation between the binary value and the corresponding floating point value is given by the formula K1 2M 65535 30 First Baseline Subtraction Pedestals VFPED Instruction Code 06h Width 20 Register Type Channel Local Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS CHANNEL ADDRESS 06 19 10 9 0 VPD Read Only FPD Read Write Description Parameter Description Range VPD Self Calibrated Variable Pedestal 0 3FF FPD Fixed Pedestal 0 3FF Notes
44. evious LVL1 signal If the LVL2 is not received the buffer with the last LVL1 related data is considered empty and this buffer occupied with data related to the next LVL1 signal as it is shown in figure 1 13 a a _ a a LVL1 LVL2 LVL1 LVL1 LVL1 LVL2 LVI1 LVL2 StS 1 1 Figure 1 13 Evolution of the multi event buffer for different triggers signals To read a validated event and therefore to empty the buffer occupied a Channel Readout Command must be performed for each channel 21 Mode of Use and Operation 2 1 Introduction The ALTRO chip is interfaced to the readout system through a digital bus composed of 40 bi directional lines and 8 control lines The 40 bit bus contains 20 address bits that define the ALTRO address space and 20 data bits This address able space contains the pedestal memories the configuration status registers as well also a set of commands which start internal finite state machines for the execution of sequences of micro instructions The ALTRO signals are described in detail in the section 2 2 The section 2 3 is dedicated to a global view on the ALTRO Instruction Set The instructions can be divided in Register Access section 2 4 and Commands section 2 5 The Control Protocol for the configuration and to run the chip is described in section 2 6 The modes of operation of the chip and setup of the ADCs are analyzed in section 2 7 In this chapter RCU is defined as the m
45. ge ACQ_START Number of cycles to wait before acquisition starts 0 3F0 ACQ_END Number of cycles elapsed from trigger to acquisition end 0 3F0 Notes ACQ_START must be less or equal than ACQ_END When Pretrigger is used ACQ_START is ignored Pretrigger and ACQ_START are mutually exclusive features To avoid overflowing the data memory when it is divided in 8 buffers ACQ_END should not exceed 506 1FA 35 DPCFG Data Path Configuration 1 Instruction Code OB h Width 20 Register Type Global Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS 0B 19 12 11 5 4 0 ZS CFG BC2_CFG BC1_CFG Description Parameter Bits Description Range 3 0 First Baseline Correction Mode table 2 6 O F BC1_CFG 4 Polarity When set the ADC data is inverted 1 s C 0 1 6 5 Number of Presamples excluded from 2 Baseline Correction 0 3 BC2_CFG 10 7 Number of Postsamples excluded from 2 Baseline Correction O F 11 Enable Second Baseline Correction 0 1 ZS CFG 36 13 12 Glitch Filter Configuration for Zero Suppression table 2 7 0 3 16 14 Number of Postsamples excluded from suppression 0 7 18 17 Number of Presamples excluded from suppression 0 3 19 Enable Zero Suppression 0 1 Notes 0000 0001 din f t 0010 din f din 0011 din f din vpd 0100 din v
46. iability This has a direct impact on the PCB design which must observe certain rules in the routing of the analogue lines and the splitting of the ground planes Also the pinout of the digital part is optimised to allow the connection of 8 ALTROs to the same bus without increasing dramatically the complexity of the PCB a factor that affects price and yield 4 2 Timing Specifications 4 2 1 Analog to Digital converter Special attention must be paid to the duty cycle of the ADC sampling clock Proper functioning is only guaranteed in a narrow band around 50 Therefore the distribution of the sampling clock on the board and on the backplane must be designed carefully to avoid undesired effects leading to modifications in the duty cycle The distribution of the clock inside the chip is such that the signal will reach the ADC first and the digital logic some 600 ps later as shown in figure x This artefact allows for a cleaner noise environment during the aperture time of the ADC since all the digital noise derived from gate switching will occur when the clock reaches the flip flops The clock signal is first split in two clock trees one for the digital logic and another for the ADCs The two signals are brought to the centre of the chip from where they are 1 distributed to all the cells This strategy minimises the skew The ADC clock is again split in two branches to supply the two ADC blocks on each side The signals are manually r
47. ilter Power Save MISC_CFG register The pedestal memory is addressed either by the input data sample in Conversion mode or by an internal counter in Subtraction and Test mode time The Autocal block estimates the value of the baseline when the gate is closed and defines the self calibrated subtraction mode This circuit calculates the cumulative average of the baseline and subtracts the value to the input samples as it is shown in fig 3 4 The baseline estimated vpd is available in a configuration register The twx signal is set when the system is in processing mode gate open and therefore controls the window time to calculate the baseline vpd dout Figure 3 4 Self Calibration circuit The transfer function of the Autocal circuit in the Z domain is 60 1 z H z _ _ z 1 0 52 The Baseline Subtraction circuit is control by the Pedestal Memory Manager fig 3 1 61 3 4 Tail Cancellation Filter circuit Input Output 11 bit 11 bit 18 bit Figure 3 5 Tail Cancellation Filter architecture The architecture of the Tail Cancellation filter is implemented as 3 first order IIR digital filters in cascade as it is shown in the picture above Each stage of the filter is controlled by means of 2 coefficients Li and Kj which are programmed independently This implementation corresponds to the function in the Z domain 14L 27 1 L z 14L z2 1 K z
48. is due to non systematic effects The second baseline correction computes a moving average on certain samples and then subtracts this value from the signal m The zero suppression is based on a fixed threshold pulse detection scheme where samples of value smaller than a constant decision level threshold are rejected To reduce the noise sensitivity a glitch filter checks for a consecutive programmable number of samples above the threshold In order to keep enough information for further feature extraction a programmable sequence of pre samples and post samples is also recorded Eventually the merging of two subsequent sets closer than 3 samples is foreseen m The zero suppressed data is formatted in 40 bit words Every block of samples is labelled with its time and length to allow posterior reconstruction At the end of the acquisition period the data block is labelled with a trailer word The whole structure is back linked that is each trailer word points to the end of the previous data block m Trigger related data is stored in a multiple event buffer The Multiple Event Buffer is a 1024x40 RAM partitioned in a programmable number 4 or 8 of fixed length buffers The data is continuously processed when a trigger is received a window Processing Time Window PTW defines the stream of data to be formatted and stored in the multi event memory The implementation of the processing chain requires 18 pipeline stages With this pipelin
49. ital Converter ADC with 10 bit dynamic range and up to 40 MS s sampling rate m The first baseline correction corrects the systematic instability of the signal baseline allowing the subtraction of time dependant pedestal values taken from the pedestal memory At this step the variations of the pedestal in between triggers are also self corrected Alternatively the pedestal memory can act as a look up table addressed by the input data that can be used to perform a conversion of the input signal during the pedestal subtraction Finally the pedestal memory can also be used to generate a test pattern an important feature that allows a complete test of the overall processing chain without input signal m The signal of a gas detector is often characterised by a long tail with a rather complex shape An accurate cancellation of the signal tail is required in order to perform efficiently the zero suppression The tail cancellation filter is based on the approximation of the tail by the sum of exponential functions Flexibility for the different 16 channels is also given by the possibility to re configure channel by channel the digital signal processing by changing programmable coefficients m After the tail cancellation a second baseline correction corrects the perturbation of the baseline produced by non systematic effects Assuming that systematic and tail dependant perturbations have been removed in the previous two stages any remaining deviation
50. ition Vio Digital Input High Voltage 2 0 Vpp 0 2 V Vi Digital Input Low Voltage 0 3 0 8 V VssuB Guard Ring Ground 0 V V V Analog Inputs Parameter Test Condition Vin Vina Full Scale Reference Voltage 2 0 V a AnalogBiasCurent IPOL Analog Bias Current 5 o o ma Vow Input Common Mode Vottage Vicen Input Common Mode Voltage 048 057 0 65 a Power Consumption Symbol Parameter Analog Supply Current ADC Performance Parameter Test Condition Fs 25 MHz Vin full scale Effective Resolution Bandwidth Offset Error Integral Non Linearity Fin 5 MHz Fin 5MHz 805 66 dB SFDR Spurious Free Dynamic Range eee Fin 10MHz 7 6 s B 10 Symbol Parameter Test Condition SNR Signal to Noise Ratio goma se 3 Total Harmonic Distortion 4 4 Package Description and Pinout The ALTRO 16 chip is packaged in a 176 pin Thin Quad Flat Pack TQFP 176 with pin stubs spaced at a pitch of 0 5 mm 0 019 The package body dimensions are 24 x 24 x 1 4mm The cavity for the silicon die is 12 x 12 mm A view of the part is shown below The benefits of using a classical SMD package are the soldering reliability and the manipulation simplicity ALTRO 16 Q 03788 5001 Figure X ALTRO chip package Much of the internal layout of the chip is reflected in the pinout distrib
51. k the value of the Trigger Counter Register TRCNT 41 ADEVL Chip Address and Event Length Instruction Code 11h Width 16 Register Type Channel Local Access Type Read Only Allow Broadcast No Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS CHANNEL ADDRESS 11 19 16 15 8 7 x HADD EVL Description Parameter Description Range EVL Length in 40 bit words of the last event stored in the data memory 0 FF HADD Hard wired Chip Address fixed through pins HADD 7 0 O FF Notes e EVL provides the event length of the last stored event It is updated after each L2 accept command WPINC Note that if the zero suppression is enabled EVL might have a different value for each channel 42 Trigger Counter TRCNT Instruction Code 12h Width 16 Register Type Global Access Type Read Only Allow Broadcast No Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS x 12 19 16 15 8 7 0 X TRCNT Description Parameter Description Range TRCNT Number of L1 triggers received 0 FFFF Notes e This counter is set to O when the chip is reset or when the command TRCLR is issued The count includes also the triggers that are ignored when the memory is full 43 WPINC Write Pointer Increment Instruction Code 18h Command
52. ke twrsu pa tWRH gt WRITE Boeri gt toHKL gt tonKH Figure 2 1 Write Instruction Chronogram Read Instructions During a read instruction the master must drive the upper half of the data bus bits 39 to 20 and leave the lower half in high impedance The chip will drive the lower part to return the value All the 20 bits will be driven therefore if the value to be returned is less than 20 bits wide the remaining bits will be set to 0 Basic timing The CSTB line must be held low and the WRITE line high until ACK is asserted The upper data lines must be valid during the assertion of CSTB The output data will be valid during the assertion of ACK One clock cycle following the de assertion of ACK the lower part of the data bus will be in high impedance RDOOLK Pee Te AN RA AN tstsu a STH gt tsTL gt CSTB tansu gt TADH gt BD 39 20 AF gt tcHov gt l tcHoz BD 19 0 e twrsu gt I twRH gt WRITE toHKL ghee gt gt tcHkH Figure 2 2 Read Instruction Chronogram Relaxed timing The set up time for CSTB can be zero The read cycle starts on the rising edge on which CSTB is sampled low The WRITE line and the data lines must be valid at least 2 ns before the next rising clock edge and kept valid for at least one complete clock cycle CSTB must be asserted for at least 2 complete clock cycles If CSTB is removed
53. lapping phases Configuration Processing and Readout The chip can be in a standby state where none of these phases are active Test Mode e This Mode corresponds to the test of the ADC The output of 4 ADCs is the bi directional bus BD 89 0 There are two selection lines ADCADDO and ADCADD1 that chose which set of 4 ADCs among the 16 would be at the output Run Mode e Configuration Phase Before running the chip it should be configured and the correct parameters should be set Some parameters are global and the broadcast option can be used ex Number of buffers Others should be tuned channel by channel depending on the shape of the input signal ex Filter coefficients position of the pad in the chamber ex Number of samples per event or user choices as the number of buffers In practical terms this phase consists of writing and reading configuration registers This step is fundamental to insure a good and effective functioning of the chip The default parameters enable the user to run the chip with the minimal options e Processing Phase On the aftermath of the issue of the trigger the data processing chain receives data from the ADC processes it and saves it in the data memory This phase starts with a trigger and ends by itself after counting the Number of samples per event given in the register NS E Typically it lasts 880s It is the phase of peak power consumption even if it runs mostly on 10MHz SCLK e Readou
54. ll remaining buffers and the position of the Read and Write pointers Table 2 8 summarizes the error and status register 19 18 17 16 15 RDO Error Int 2SEU Int 1SEU MMU 2 SEU MMU 1 SEU 51 14 13 12 Trigger Overlap Instruction Error Parity Error 11 10 9 6 5 3 2 0 EMPTY FULL Remaining Buffers Write Pointer Read Pointer Table 2 8 ERSTR register details 14 TRCNT Trigger Counter Read only The 16 lower bits code the number of level 1 triggers received by the ALTRO chip 15 PMADD Pedestal Memory Address per Channel lt contains the value of the pedestal memory address 52 2 6 Command Set The ALTRO chip recognizes a set of 6 commands Two of them WPINC and RPINC are used to increase the multi event buffer read and write pointers the following 4 commands control the operation of internal finite state machines in normal and broadcast mode The ALTRO chip acknowledges the execution of any command except when the broadcast option is used The instruction cycle takes place between a Control Unit MASTER and the ALTRO chip SLAVE A special case is represented by the data readout procedure activated by the CHRDO instruction where the ALTRO acts as MASTER and the Control Unit as SLAVE The protocol and the timing of the signals for the execution of an instruction are graphically depicted in figs 2 1 and 2 2 Hereafter follows a short description of the ALTRO Co
55. log supply PO ANA Channel 2 Differential Input PO ANA Channel 2 Differential Input VSSCO ADC analog ground VDDIOCO ADC analog supply PO_ANA Channel 3 Differential Inout PO_ANA Channel 3 Differential Input VDDCO ADC analog supply PO_ANA Common Mode Bias PO_ANA Positive rail reference VSSCO ADC analog ground PO_ANA Negative rail reference VDDCO ADC analog supply PO_ANA Channel 4 Differential Input PO_ANA Channel 4 Differential Input VDDIOCO ADC analog supply VSSCO ADC analog ground PO_ANA Channel 5 Differential Inout PO_ANA Channel 5 Differential Input VDDIOCO ADC analog supply VSSCO ADC analog ground PO_ANA Channel 6 Differential Input PO_ANA Channel 6 Differential Input VSSCO ADC analog ground 4o Vin PO ANA Channel 7 Differential Input 41 VINB7 PO ANA Channel 7 Differential Input 42 AGND VSSCO ADC analog ground 43 AVpp VDDCO ADC analog supply a SHIELD VSSCO ADC P well isolation ring bias 45 TSM IBUFD Test Mode Select ADC_ADDo IBUFD ADC Select in Test Mode ADC_ADD IBUFU ADC Select in Test Mode HADDo l IBUF ALTRO Hardware Address bit 0 HADD l IBUF ALTRO Hardware Address bit 1 HADD2 l IBUF ALTRO Hardware Address bit 2 HADD l IBUF ALTRO Hardware Address bit 3 52 DVop Vppco Digital Voltage Supply 53 DGND VSSCO Digital G
56. maximum number of samples that can be continuously processed for each trigger data stream is 1008 When a second level trigger accept is received the data stream is either frozen in the data memory till its complete readout takes place or discarded The data memory has the capacity to store 8 data streams As shown in figure 1 1 after the analogue to digital conversion the signal processing is performed in 5 steps a first correction and subtraction of the signal baseline the cancellation of long term components of the signal tail a second baseline correction the suppression of the samples so close to the baseline that contain no useful information zero suppression and formatting The data processing and the readout of the data memory are performed at different frequencies different colour in figure 1 1 ACQUISITION CHANNEL x16 DATA PROCESSOR First Baseline Multi Event Correction i Buffer 3rd Order Second Zero ER z Baseline A 7 Pedestal Digital Filter 3 a Supression i Correction i i Data Memory i Memory m i COMMON CONTROL nt Bus Trigger LOGIC Registers Interface Manager Runs with Sampling Clock E Runs with Readout Clock BD CTRL Figure 1 1 ALTRO Processing Chain Every single ALTRO channel is comprised of 7 main building blocks described hereafter m The analogue input signal is converted into a digital stream by an Analogue to Dig
57. mber of Samples Event Global The higher 10bit code for the trigger delay The delay between the global trigger and the arrival of data to the pads depends on the position of the pads themselves in the chamber For specific chips the delay can be adjusted in order to compensate for this NS E codes the number of samples event to be processed and it ranges from 0 to 1000 DPCFG Datapath configuration register Global Register containing configuration parameters for the BSU MAU and ZSU Table 2 5 shows in detail the function of each bit 50 19 12 11 5 4 0 ZSU_CFG MAU CFG BSUCFG 4 3 0 Polarity BSU Mode 11 10 7 6 5 MAU Enable Postsamples Presamples 19 17 14 13 12 18 16 ZSU Enable Presamples Postsamples Seq Mask Table 2 5 Dpcfg register details 9 ZSU CFG It contains the configuration for the zero suppression circuit The most significant bit enables the zero suppression The subsequent 4 bits set the number of pre samples and the number of the post samples The last 2 bit set the minimum number of consecutive samples above the threshold to consider it to be a cluster This Seq Mask ranges from 0 to 3 10 MAU CFG The MSB enables the moving average filter according to the post samples and pre samples set in bits 10 to 7 and 6 to 5 respectively 11 BSU CFG The MSB of the BSU CFG is used to select the polarity of the input it is O if the input is positi
58. mmands WPINC Increase the Write pointer This command corresponds to a PUSH instruction in a circular buffer of the multi event memory RPINC Increase the Read pointer This command corresponds to a POP instruction in a circular buffer of the multi event memory CHRDO Channel Readout As it is shown in Fig 2 1 a few cycles after the command has been issued the ALTRO asserts the TRANSFER signal and then starts to transfer the 40 bit words each one being validated by the DSTB signal SWTRG Software Trigger The RCU Readout Control Unit issues a trigger that is interpreted by the ALTRO as a level 1 trigger This command is used only for test purposes TRCLR Trigger Counter Clear This Command resets the TRCFG register ERCLR Error Clear This Command resets the higher 8 bits of the ERSTR register i e the Error register 53 2 7 Control Protocol Basic Protocol The ALTRO protocol is asynchronous for all the operations except the readout When an instruction is issued the CSTB line must be held low until the ALTRO asserts the line ACK ACK keeps low until CSTB is de asserted In principle data and control lines can be asserted at any time although it is recommended to keep some distance from the rising edges of the readout clock to avoid metastability problems Write Instructions A write instruction may or may not require an argument When no argument is required the instruction is called a comm
59. nt Buffer circuit contains the readout memory and the auxiliary memory fig 3 9 The rd pt and wr pt signals are related to the signals LVL2 and LVL2 trigger respectively and give the first address of the buffer to readout or to write In combination with this information two counters address the readout memory in read mode the counter is contained in the Data Memory Manager see fig 3 1 When an event has been processed and store in the memory the cnt8 contains the 40 bit word length of each processed event Every time there is a L1 trigger signal the write counter is reset and ready to start the counting of the new event The auxiliary memory is a circular FIFO which stores the length of the events associated to a LVL2 trigger enable of the FIFO This information is needed to readout the events The output multiplexer of the FIFO allows the user to access the event length information from the outside auxiliary memory 3 rd_pt L2Y Wr pt stored evl radd write 1K x40 Q oe wr clk oe logic read ___________ Figure 3 9 Multi E vent Buffer circuit In fig 3 10 is shown the possible values of the pointer for the two possible modes of use of the readout memory 4 and 8 buffers The pointer value corresponds to the three most significant bits of the memory address 67 pointer 8 buffers pointer 4 buffers value 512 s
60. or condition If the error condition has occurred in an instruction cycle parity error or instruction code error the slave does not acknowledge the instruction cycle and asserts the ERROR signal TRANSFER TRANSFER EN DOLO EN DSTB Output The readout of the ALTRO chip data memory is performed in two steps The first one is a normal instruction cycle where the RCU issues the command with the instruction code CHRDO channel readout The ALTRO chip that after a number of cycles takes the control of the bus by asserting the TRANSFER signal acknowledges this instruction cycle TRANSFER is kept asserted till the data block has been completely transferred The data transfer is not necessarily continuous and for this reason each single word being transferred is validated by the signal DSTB Data Strobe TRANSFER EN and DOLO EN are used to drive the bi directional bus AD when transferring an event for the former and for reading a register for the later LVL1 LVL2 Input 24 The LVL1 and LVL2 signals are broadcasted by the RCU to all the FECs They are used for the distribution of the Level 1 and Level 2 trigger information The LVL1 signal is synchronous with the SCLK signal and lasts for at least two clock cycles The LVL2 signal is synchronous with the RCLK and lasts also for two clock cycles GRST SCLK RCLK Input The GRST Global Reset is an active low global rest It initialises all the internal registers counters and s
61. outed to guarantee a difference between arrivals of less than 1 3 ps The digital clock tree starts from the centre and splits in several levels to reach all the flip flops and the memories Inside the ADC macro the clock tree is passive therefore requiring a strong driver at the input digital clock tree v ADC passive clock tree skew lt 1 3 ps Figure x ADC clock distribution inside the chip Timing Characteristics 4 2 2 Digital Logic As it was stated before the ALTRO chip works on two clocks one lower frequency clock for the ADC and the processing chain SCLK and another higher frequency clock for the bus interface and the readout RCLK In order to reduce the noise induced in the ADCs by the switching of the gates as much of the logic as possible works on the sampling clock SCLK A special arrangement of the layout allows the ADCs to perform the conversion before the clock edge reaches the digital logic A much smaller part of the logic works on the readout clock RCLK This concerns mainly the interface to the data bus and some memory control logic Instructions are issued by the Readout Controller Unit RCU based on the readout clock The ALTRO decodes the instruction and launches its execution based on the sampling clock finally acknowledging it back on the data bus with the readout clock Only the readout instruction executes without the intervention of the sampling clock
62. overy can be done even changing state If there is no need of changing state the related coding state is recovered The recovery takes always place in the next rise edge of the clock If there is a double bit flip the Hamming State Machine can fail because the jump can be done to a halo of the other coding state or to an abort state in the latter case the sequence is aborted and the state machine goes to idle state The status of the Hamming State Machines is reported in a Status Register there are two types of status bits m Error if there is a transition to a derived state m Abort if there is a transition to an abort state and the sequence of the machine is stopped and set to the idle state A Physical Description 4 1 Introduction This section describes the technical details that are directly related to the physical implementation of the chip layout timing and electrical specifications and packaging The ALTRO 16 chip is manufactured in the ST 0 25 u technology operating at 2 5 V The reason for using this technology is directly related to the choice of the ST TSA 1001 as the ADC to be integrated with the digital logic The logic must therefore be in the same feature size as the ADC and eventually run at the same voltage to simplify the design The integration of the ADC imposes certain restrictions to the layout and the pinout of the chip in order to guarantee a good performance in terms of noise and conversion rel
63. pd fpd 0101 din vpd f t 0110 din vpd f din 0111 din vpd f din vpd 1000 f din fpd 1001 f din vpd fpd 1010 f t fod 1011 f t f t 1100 f din f din 1101 f din vpd f din vpd 1110 din fpd 1111 din fpd Table 2 6 Operating Modes of the First Baseline Correction 00 01 din f t 10 din f din 11 din f din vpd Table 2 7 Operating Modes of the Zero Suppression din stands for the data stream coming from the ADC f t stands for the data of the Pedestal Memory played back as a function of time for the duration of the acquisition after a L1 trigger is received Pattern Generator Mode f din stands for the data of the Pedestal Memory played back a function of the ADC data at any time Look up Table Mode vpd stands for the self calibrated pedestal value that is the average DC level that the ADC sees outside the acquisition window i e when there is no signal from the gas chamber fpd stands for the fixed pedestal a constant value stored in register VFPED that is to be subtracted from the ADC data stream 37 DPCF2 Data Path Configuration 2 Instruction Code OCh Width 6 Register Type Global Access Type Read Write Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS xX 0C
64. pping When the input signal is out of the margin given by the double threshold the value given for the moving average filter is frozen The Moving Average Filter is based on a FIR system The function of the filter for 8 following samples in the Z domain is given by the following formula Pa 2z 1 264 z2 42 z2 42 z9 4z tz The circuit implemented fig 3 7 is a recursive realisation of the FIR system described above 63 Figure 3 7 Moving Average Filter circuit The block gt gt 3 performs a 3 bit right shift which is equivalent to 1 8 term in the above equation 64 3 6 Zero Suppression circuit The Zero Suppression circuit is based on a fix threshold to generate a flag signal which is aligned with the data by using a pipeline of 11 clock cycles This is the same number of delay cycles introduced by the blocks implicated in the generation of the flag the glitch filter the pre sample and post samples circuit and the cluster merger fig 3 8 The data is in a 10 bit unsigned format 11z a gt din Dheizabizeizelzbizbiz BZ Z SZ BZ Bo aout 10 a See glitch pre samples cluster gt flag thro gt p filter post samples merger 10 4z 4z 3z Figure 3 8 Zero Suppression circuit 65 3 7 Data Format circuit The Data Format circuit is composed of two main circuits Data Format A and
65. ror correcting code that implies to add at the minimum code applied at the state machine a number of additional bits The Hamming State Machines are conceived as a normal state machine taking into account all the possible states given for the encoding but there are three types of states fig 3 11 m Coding states The symbols used to code these states are considered free of error and are used to codify the states The Hamming distance in between these symbols is three m Derived states The symbols used are considered erroneous Each group of derived states is associated with the related coding state that has a Hamming distance of one A group of derive states is an image of their related coding state m Abort states Those symbols are also considered erroneous but the Hamming distance from a coding state is two These states are not associated to a coding state double bit flip 001011 Normal transition Single bit flip Recover preserving the sequence Coding states Derived states Abort states Halo of derived states Figure 3 11 Hamming State Machine principles The state machines are protected against effects of one bit bit flip which affects the memory cells As it is shown in the above figure a single bit flip in a coding state makes the state machine jump to a derived state associated to this coding state halo of derive states No cycle is lost since the rec
66. round 54 BD30 O BD4CR Bi directional Data Line 30 55 BDs vo sBoscr Bi directional Data Line 31 56 BD32 O BD4CR Bi directional Data Line32 DVpp VDDIOCO Digital Voltage Supply DGND VSSIOCO Digital Ground 59 BDs vo Bao Bi directional Data Line 33 60 BD3 O BD4CR Bi directional Data Line 34 61 BD35 O BD4CR Bi directional Data Line 35 e BDsg vo Bao Bi directional Data Line 36 BD37 O BD4CR Bi directional Data Line 37 BD33 O BD4CR Bi directional Data Line 38 BD3g O BD4CR Bi directional Data Line 39 66 DVpp VDDIOCO Digital Voltage Supply 67 DGND VSSIOCO Digital Ground 68 TSTOUT O BT2CR Test Signal Output reserved 6 DGND vssioco Digital Ground BDz O BD4CR Bi directional Data Line 20 BDo O BD4CR Bi directional Data Line 21 BDo2 O BD4CR Bi directional Data Line 22 73 BDz vo Bao Bi directional Data Line 23 74 BDz O BD4CR Bi directional Data Line 24 75 BDo5 VO BD4CR Bi directional Data Line 25 BDz O BD4CR Bi directional Data Line 26 DVpp VDDIOCO Digital Voltage Supply 14 Pin Name DGND BDo7 BDo3 BDz Pin Numbe ERROR DVpp DGND HADD HADDs HADDe HADD7 Pin Name 89 SHIELD AVoo 91 AGND Ving15 Vinis a AGND 95 Ving14 96 Vinta o NC 98 AGND AVpp 100 Ving13 tot Vinis 102 NC 103 AGND tos AVoo Ving12 Vim12 AVpp tos NC 109 REFm 110 AGND in
67. stal data value f din converted data Table 1 1 ALTRO Baseline Correction and Subtraction Modes 11 1 4 Tail Cancellation Filter Although suited for a wider class of applications the ALTRO chip has been designed for the readout of the cathode pad plane of a conventional multi wire proportional chamber In this detector the necessary signal amplification is provided by an ionisation avalanche created in the vicinity of the anode wires Moving from the anode wire towards the surrounding electrodes positive ions created in the avalanche induce a positive current signal on the pad plane This current signal is characterized by a fast rise time less than 1 ns and a long tail with a rather complex shape which depend on the details of the wires and pad geometry The signal tail increases the superimposition of subsequent pulses pile up rendering the zero suppression quite inefficient In order to minimize such effect the ALTRO chip incorporates a filter for the cancellation of the signal tail The algorithm used for the tail cancellation is explained hereafter The signal is approximated by the sum of 4 exponential functions i nuke eee Tp lt lt T3 lt lt T4 is t l x A xe 7 r t i 1 YA 1 i 1 Where r t is a residual function due to the approximation error The sum of the gains A should be equal to 1 so that input and output have the same amplitude The time function 1 can be expressed in the Z domain as A
68. struction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS Xx 1C 19 0 XorZ Description This command sets the trigger counter TRCNT to 0 Notes 48 ERCLR Clear Error Register Instruction Code 1Dh Command Type Global Allow Broadcast Yes Instruction Coding 39 38 37 36 29 28 25 24 20 PAR BCAST 0 CHIP ADDRESS x 1D 19 y XorZ Description This command resets the sticky bits of the Status and Error Register ERSTR Notes 49 2 5 Registers set A set of 16 addressable sets of Configuration Status Registers CSR allows the access to the ALTRO s configuration status and memories Out of these registers 13 can be accessed in WRITE and READ mode the remaining 3 only in READ mode To define the mode there is an additional WRITE line The access mode for all the registers are given in the forth column of the tables 2 3 and 2 4 Hereafter a detailed description of the information stored in the CSR s is given 1 2 3 4 5 6 7 8 K1 K2 K3 L1 L2 L3 Digital Filter Coefficients per Channel There is a set of 6 16bit registers for each channel independently The Ki correspond to the poles of each stage of the tail Cancellation Filter and the Li are similarly the zeros of the Filter A broadcast of the Coefficients will give the same Tail Cancellation Filter settings to all the channels and indeed all the ALTROs VFPED
69. t Phase After one or more level 1 LVL1 and level 2 LVL2 triggers were acknowledged the content of the data memories should be read By sending a CHRDO instruction to a specific channel of a specific chip the content of that buffer is read through the full bi directional bus AD 39 0 at RCLK It is the only moment when the ALTRO is the master of the bus Typically it lasts around 10 Os and it stops when the event stored in the data memory of the specified channel is fully read If a trigger occurs during this phase the ALTRO stops the Readout gets into the Processing Phase until it is finished and returns to complete the Readout The MMU module manages this process and it is transparent to the user 57 Circuit Description 1 Introduction As it is mentioned in Chapter 1 the ALTRO chip is composed of several circuits dedicated to the digitalisation and processing of signals for the readout of trigger related data It contains fig 3 1 16 A C converters ADC Block 0 1 a set of configuration and status registers register block interface interface and control logic pedestal memory data memory and trigger manager and a basic channel structure fig 1 1 which is replicated 16 times 16 CHROL Figure 3 1 ALTRO chip block diagram data l HP pedestal data pads y interface sa register block e y memory memory manager
70. tate machines The SCLK Sampling Clock is the ALTRO sampling clock and can have a maximum frequency of 20MHz All the data ALTRO processing is done synchronously with the SCLK signal The RCLK is the ALTRO readout clock and can have a maximum frequency of 40MHz The latter is the clock engine for the ALTRO bus master and slave interfaces Other signals of the ALTRO chip are further described in this chapter The signal TMS controlling the mode of operation is described in section 2 7 The pin TSTOUT is an output of the chip ORing some important internal signals and it is used for debug purposes only 25 An instruction can be either an access to the Configuration Status Register CSR or a Command In the former case the instruction involves reading or writing data according to the value of the WRITE signal to one of the CSR s In the latter case the instruction does not imply a data transfer from to the chip thus the data field of the bi directional AD lines is not used The nature of the instruction CSR access or COMMAND is defined by the address bits AD 24 20 Some of the CSR and instructions are global to all the 16 channels and others are for each individual channel A detailed description of the parameters stored in the ALTRO register set is given in the next section The tables 2 3 and 2 4 describe the register set and the command set All write instructions register access or command can be issued in broadcast mode if the bit AD
71. ution As it will be shown in section 4 6 8 ADCs are placed on the top side of the chip while other 8 are in the bottom side The digital logic is in the middle thus leaving the left and right sides for digital pinout In addition to this the location of the digital pins has been optimised to minimise the number of vias in the PCB when connecting several ALTROs to the same bus on both sides of the board Additional details on routing the data bus can be found in section 4 5 The comprehensive pinout of the chip is presented in figure x 11 SHIELD AGND AVCC AGN6D VINO VINBO AGND VIN1 VINB1 AGND AVCC NG VIN2 VINB2 NC AGND AVCC VIN3 VINB3 AVCC NG AVCC VIN4 VINB4 AVCC AGND NG VINS VINB5 AVCC AGND NC VING VINB6 AGND VIN7 VINB7 AGND AVCC SHIELD ft 5 5 9 E E E E E ma E E CHI CI CI CI CI CI EE 3 o Ko Ka a eo all nl gt l gt col l ES ll S 1 bal DOLO EN 176 Ivi2 175 GRST 174 GND 173 VDD 172 ACK EN 171 TRSF EN 170 169 BD01 168 BD03 TSM 45 46 47 HADDo 48 HADD1 49 HADD2 50 HADD3 51 VDD 52 GND 53 BD30 54 BD31 55 BD32 56 ADC ADD1 ADC_ADDO 167 BDO5 166 GND 165 VOD BD07 163 BD09 162 BD11 161 BD13 160 BD15 159 BD17 158 BD19 157 GND 156 ADCCLK 155 VDD 154 BD
72. ve and 1 if negative The BSU Mode sub register is shown in table 2 6 12 BFNPT Buffer Number and Pre trigger number Global Miscellaneous cancellation filter is disabled when there is no event to process i e in between triggers There also a 1bit register that enables bit 1 or disables bit 0 the filter regardless of the arrival of the triggers The following bit sets the option for the number of buffers in the data memories 4 buffers gt Nb Buff 0 8 buffers gt Nb Buff 1 The final 4 bit set the number of samples to process before the arrival of the trigger Owing to its internal pipeline the chip always holds simultaneously 14 consecutive samples This feature gives the possibility to process samples that anticipate the trigger The number of the pre trigger samples can vary between 0 and 14 The value 15 in the register corresponds to 14 pre trigger samples Table 2 7 summarizes the BFNPT register 6 5 4 3 0 PowerSave FilterEnable Nb Buffers Pretrigger Table 2 7 BFNPT register details 13 ERSTR Error Register and status register Read only It contains 8 bit for coding errors in the circuit Readout error single and double event upsets SEU in the MMU and Interface modules trigger overlap and instruction error This last error embraces the cases of writing or reading in the wrong or non existent address The lower 12 bits give information on the state of the multi event buffer empty fu
73. ys even The parity bit allows the detection of a single bit error in the transmission between the RCU and the FEC When the bit AD 38 BCAST broadcast is set to 1 the bus write cycle initiated by the RCU master is addressed to an entire partition of the address space AL or BC partition In this case the slave units ignore the channel address field The bit AD 37 BC AL defines the address space partition 1 for the BC partition O for the AL partition The following 8 bits AD 36 25 CHANNEL ADDRESS specify the channel address and during an instruction cycle are compared with the hard wired address From the most significant bit the channel address consists of a branch address 1 bit the FEC address 23 4 bits the ALTRO chip address 3 bits and the ALTRO s internal channel address 4 bits This allocations of addresses is the recommended one and it corresponds to the case of a board containing 8 ALTROs FEC and an RCU with two branches each one with 16 FECs The bits AD 24 20 INSTRUCTION CODE carry the instruction code As it will be detailed in the next section the ALTRO chips and the BC are controlled by a set of instructions The instruction can be either an access to a Configuration Status Register CSR whose address is part of the instruction code or a Command In the former case the instruction involves a WRITE or READ cycle according to the value of the WRITE signal to one of the CSRs In the latter case th
74. z Clock high to Output Data in high Z tcHDH Clock high to DSTB high toot Clock low to DSTB low tcHAEL Clock high to ACK EN low tcHAEH Clock high to ACK EN high tcHDEL Clock high to DOLO_EN low tcHDEH Clock high to DOLO EN high tcHTEL Clock high to TRSF_EN low tcHTEH Clock high to TRSF_EN high tstsu CSTB set up time tsTH CSTB hold time tsLav CSTB low to Address valid tstwv CSTB lowto WRITE valid tkLsH ACKN lowto CSTB high tsr CSTB active duration WRITE set up time WRITE hold time Address set up time Address hold time LVL1 active duration LVL2 active duration tRsL GRST active duration 4 3 Electrical Specifications Absolute Maximum Ratings Parameter Conditions Vo Digital Supply Voltage Supply Voltage 0 5 Low Level Threshold High Level Threshold ag Low Level Input Current oi High Level Input Current 7 Low Level Output Voltage lo 100 pA High Level Output Voltage lon 100 HA Vpp 0 2 loz Tri state Output Leakage Current Vo 0 V or Vpop Ipu Input Pull Up Current Vi 0V lpp Input Pull Down Current Vi Vpop Equivalent Pull Up Resistance 0V EE Equivalent Pull Down Resistance I O Latch up Current Vo lt OV Vo gt Vpop ESD Protection Leakage lt 1 uA 2000 Vs __DigitalGround Ground AVpp Analog Supply Voltage 2 25 2 5 2 7 V AVss Analog Ground 0 0 0 V Parameter Test Cond

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