Home

M16C/6B Group User`s Manual: Hardware

1. DMA2 Destination Pointer DMA Transfer Counter DMA2 Control Register DM2CON Timer B Count Source Select Register 2 Timer B Count Source Select Register 3 DMAS Source Pointer DMAS Destination Pointer DMAS Transfer Counter DMA3 Control Register DM3CON oj o oj oj o oj oj oj o A oj oj AJ oj oj o oj oj o o A oj o AJ oj oj o oj o o o oj o oj oj oj oj o o Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Interrupt Source Select Register 2 IFSR2A Interrupt Source Select Register IFSR Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2 Blank columns are all reserved space No access is allowed B 3 dress Match Interrupt Regis Register Register RT Transmit Receive Control Register 2 dress Match Interrupt Regis RT1 Special Mode Register 4 RT1 Special Mode Register 3 RT1 Special Mode Register 2 RT1 Special Mode Register dress Match Interrupt Regis RT1 Transmit Receive Mode Register RT1 Bit Rate Register RT1 Transmit Buffer Register dress Match Interrupt Regis RT1 Transmit Recei
2. 68 WOBRG to U2BRG fe tene nena itte 131 UO0CO to 2 nentes 132 U0C1 U1C1 133 UOMR to U2MR E we 131 UORB to U2RB we 130 UOSMR to U2SMR 136 UOSMR2 to U2SMR2 ss 137 UOSMRS to U2SMRS we 138 UOSMR4 to U2SMRA 189 UOTB to U2TB zs 130 o EET 134 oo R 135 DF M 105 R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 331 of 331 Jul 21 2011 REVISION HISTORY M16C 6B Group User s Manual Hardware Description Summary 0 10 Jul 31 2008 First Edition issued 0 20 Feb 10 2009 Revised Edition issued 0 30 Sep 18 2009 Revised Edition issued 1 00 Apr 21 2010 All pages PRELIMINARY and Under development deleted 53 to 54 7 4 4 1 FMRO1 CPU rewrite mode select bit b1 and FMSTP Flash memory stop bit b3 revised 177 Table 14 1 Operating clock AD revised 180 Figure 14 3 revised 256 Table 18 8 ALeRASE revised 260 to 261 18 3 3 1 FMROO RY BY status flag b0 FMRO2 Lock bit disable select bit b2 and FMSTP Flash memory stop bit b3 revised 264 18 3 3 4 FMR60 EW1 mode select bit bO revised 265 to 266 Figure 18 5 and Figure 18 7 revised 267 to 268 18 3 4 Precautions on CPU Rewrite Mode deleted 267 Table 18 10 revised 268 18 3 4 4 revise
3. Timer B1 interrupt 0 1 01 Event counter mode TMOD1 to TMODO 00 Timer mode Timer 2 interrupt 01 Event counter mode TMOD1 to TMODO 00 Timer mode Timer B3 interrupt Timer B3 01 Event counter mode TMOD1 to TMODO 00 Timer mode Timer B4 interrupt Timer B4 01 Event counter mode TMOD1 to TMODO 00 Timer mode Timer B5 interrupt 01 Event counter mode TCK1 to TCKO TMOD1 to TMODO bits in the TBiMR register i 0 to 5 TCSO to TCS7 bits in registers TBCSO to TBCS3 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 100 of 331 M16C 6B Group 12 Timers 121 Timer A Figure 12 4 shows a Timer A Block Diagram Figures 12 5 to 12 11 show registers related to Timer A Timer A supports the following four modes Except in event counter mode Timers AO to A4 all have the same function Use bits TMODI to TMODO in the TAiMR register i 0 to 4 to select the desired mode Timer Mode Event Counter Mode One shot Timer Mode Pulse Width Modulation PWM Mode fC32 fOCO S f64TIMAB fS2TIMAB f8TIMAB f1TIMAB or f2TIMAB TCK1 to 53 r TCS7 TCS2 to TCSO m TCS6 to TCS4 Polarit O 2 TB2 underflow TAj overflow TAk overflow Timer One shot timer Pulse width modulation TMOD1 t
4. 10 1 stop mode d O bic Divider Main CPU clock clock Main clock 0 BCLK 05080 lation circuit WAIT instruction RE Er 4dib 3 1 32 Software reset 1 8 1 16 NMI CMO06 0 17 to CM16 11b PM24 Interrupt request level CMO6 1 selection output CM06 0 Watchdog timer reset CM17 to CM16 10b Oscillation stop detect reset CM02 CM04 CMO05 CMO06 CMOT7 bits in the register CM06 0 CM10 14 16 17 bits in the CM1 register CM17 to CM16 016 PCLKO PCLK1 bits in the PCLKR register CM21 CM27 bits in the CM2 register CM06 0 CM17 to CM16 00b Reset Pulse generation d Oscillation stop circuit for clock detection reset edge detection ischarge ao and charge circuit Oscillation stop Oscillation stop illati re oscillation discharge control re oscillation detection int t detection interrupt Sa Inter Up generating circuit signa CM21 switch signal Figure 7 1 System Clock Generation Circuit R01UHO197EJ0120 Rev 1 20 ztENESAS Page 37 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset CMO 0006h 01001000b Bit Symbol Bit Name Function b1 bO Cl
5. M SS 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 b Reserved bits NOTES 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enabled 2 Bits PMO1 and PMOO do not change at software reset watchdog timer reset and oscillation stop detection reset Figure 6 1 PMO Register R01UH0197EJ0120 Rev 1 20 ztENESAS Page 33 of 331 Jul 21 2011 M16C 6B Group 6 Processor Mode Processor Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 lojojo jo Symbol Address After Reset 1 if 1 1 0005 000010006 Data flash enable bit 2 RW Reserved bit Set to 0 Watchdog timer function select 0 Watchdog timer interrupt bit 1 Watchdog timer reset R Reserved bit Set to 1 RW Reserved bits Set to 0 RW Rane 0 No wait state 4 Wait bit 1 Wait state 1 wait Write to this register after setting the PRC1 bit in the PRCR register to 1 write enabled PM10 bit is automatically set to 1 while the FMRO 1 bit in the FMRO register is set to 1 CPU rewrite mode The PM12 bit is set to 1 by writing a 1 in a program writing a O has no effect The PM12 bit is automatically set to 1 when the CSPRO bit in the CSPR register is 1 count source protection mode enabled When the PM17 bit is set to 1 wait state one wait state is inserted when accessing the inte
6. BBANTSWTIMG m BBBOFFPROD FMA FMR2 BBCCAVTH B a n o REPRE ERR ERE RERO BBGREGIC 1 BBCSMACONO 76 BBCSMACON1 IFSR2A T76 BBCSMACON2 INTOIC INT1IC 69 BBEVAREG BBEXTENDADO to BBEXTENDADS 225 BBIDLEIC ceeecececccseccecesecsececcecsceesecercececeevaceecevaeeecareesaeesavanees 68 K BBIDLEWAIT 294 quss c 79 BBLVLVTH 218 KICON1 79 BBPANID 224 m 68 BBPLLDIVH wa 230 BBPLLDIVL wenn 230 BBPLLEIG 68 L BBRFCON mn 221 LEDCON ansassasaaasasasaasanachauaonaonaaneassanansansanacnauasosansensenaansannaeaoo 249 BBRFINI wens 235 BBRSSICCARSLT se 213 BBRSSIOFS s 232 BBRXUIC BBRXIIC sees o DE BBRXCOUNT 212 BBRXELBEN 212 BBRXOROIC BBRXOR 1IC eene 68 P BBSHORTAD m P5 to P8 P10 BBTCOMPOREGO to BBTCOMP2REQ9O 227 PCLKR BBTCOMPOREG to BBTCOMP2REG1 227 PD5 to PD8 PD10 BBTIMOIC to BBTIM2C PMO 1 1 BBTIMEREADO BBTIMEREAD1 226
7. bit can be used to automatically transit to reception status after transmission is completed The AUTORCV I bit can be used to automatically transit to reception status after reception is completed However ACK response takes priority when ACK response conditions are met while the AUTOACKEN bit is automatic ACK enabled The BATLIFEEXT bit can be used to enable the battery life extension mode for the branch conditions used in CSMA CA processing shown in Figure 15 7 The BEACON bit can be used to specify the operating mode for ACK frame response or CSMA CA timing Transmit Receive Mode Register 0 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address 0 0102h 0 Normal 1 CCA ED Set to 0 0 Automatic ACK disabled AUTOACKEN Auto ACK mode enable bit 1 Automatic ACK enabled Auto receive switch mode 0 0 Automatic reception switching disabled AUTORCVO enable bit TX gt RX 1 Automatic reception switching enabled Auto receive switch mode 1 0 Automatic reception switching disabled enable bit RX RX 1 Automatic reception switching enabled BATLIFEEXT life extension mode 0 Disabled 1 Enabled BEACON mode bit 0 mode 1 Beacon mode b7 Reserved bit Set to 0 Figure 15 12 Transmit Receive Mode Register 0 Configuration AUTORCV1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 210 of 331 Jul 21 2011 M16C 6B Group 1
8. 315 20 7 2 eR Ce UGE NEUE 319 20 8 Serial Interface on e eet b edocti a a 321 20 8 1 Clock Synchronous Serial T O tenete eto leet eder Het Ha tete 321 20 8 2 UART Clock Asynchronous Serial I O Mode nne 323 20 8 3 Special Mode 1 I2C Mode cscsesssssscssssssessssssssesescescscscssssescscsssussssescecesessassnsussescscsesssecececenesessseeesees 323 20 8 4 Special Mode 4 SIM 323 20 8 5 Common Items for Multiple Modes essent rennen rene en nennen trennen 323 20 9 A D Converter 64 Pin Version Only 222 324 20 10 Notes on Flash Memory i a eE EE 326 20 10 1 Functions to Prevent Flash Memory from Being Rewritten esses 326 20 10 2 Reading Data Fl sh IRE pe Eie iir ure eee 326 20 103 CPU RewrteMOde ertt ettet EO m mittet tet re Hee toties ee eet 326 20 I0 4 Us r Boot Mode iis sauces ee io he Re Eat die n ede 327 20 11 6 esaa 328 Appendix 12 Package Dimensions i ine eget tte 329 uq 330 SFR Page Reference The following tables only indicate where registers first appear Refer to the index for registers
9. SP No Reverse 2 When the IOPOL Bit in the UIMR Register 1 Reverse Transfer LELILILILILILILI LILI LILI LI Clock TXDi hi sT Di D2 D3 A D5 ADe A D7 A P ASP Reverse aa gt VDO Dt D2 D3 D5 DG D7 A P A SP everse 47 ST start bit P parity bit SP stop bit i Oto2 The above applies to the case where the UFORM bit in the UiCO register 0 LSB first the STPS bit in the UiMR register 0 1 stop bit and the PRYE bit in the UiMR register 1 parity enabled Figure 13 25 TXD and RXD I O Polarity Reverse RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 154 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 2 6 CTS RTS Function The CTS function is used to start transmit operation when L is applied to the CTSi RTSi i 0 to 2 pin Transmit operation begins when the CTSi RTSi pin is held L If the L signal is switched to during transmit operation the operation stops after the ongoing transmit receive operation is completed When the RTS function is used the CTSi RTSi pin outputs L when the microcomputer is ready to receive The output level becomes H on the first falling edge of the CLKi pin The CRD bit in the UiCO register 1 disable CTS RTS function CTSi RTSi pin is programmable I O function The CRD bit 0 CRS bit 0 CTS function is selected CTSi RTSi pin is CTS function
10. sese 211 15 2 5 Receive Frame Length Register eene te eee tecede pepe ciiin iR Re 212 15 2 6 Receive Data Counter Register rennen entren nennen nennen 212 15 2 7 CRSSYUCCA Result Register eerte oe et ERIS UN Eos E E 213 15 2 8 Transmit Receive Status Register 0 214 15 2 0 Transmit Frame Length Register sess enne nennen nennen nennen 215 15 2 10 Transmit Receive Mode Register 2 216 15 2 11 Transmit Receive Mode Register 3 2 217 15 2 12 Receive Level Threshold Set Register iiec eser ee eerte encre ree ro 218 15 2 13 Transmit Receive Control Register sese enne eere nennen nennen 218 15 2 14 CSMA Control Register Eie Ute deca i bep estet teet 219 15 2 15 CCA Threshold Level Set Register etie e PEU geass 219 15 2 16 Transmit Receive Status Register 1 essere ene nee nennen nennen ene 220 15 2 17 RF Control ete D RD et eee pe ERR erbe 221 15 2 18 Transmit Receive Mode Register 4 nnne 222 15 219 CSMA Control Register 1 2 retard tene diiit ep eed nee dos 223 15 2 20 CSMA Control Register 2 ete He ERI HR RETRO IEEE SEU east II ener de eene 223 152 21 PAN Identifier Register 15er remettre Un
11. RO1UH0197EJ0120 Rev 1 20 2tENESAS Jul 21 2011 Page 290 of 331 M16C 6B Group 19 Electrical Characteristics Recommended td P R operation voltage Time for internal power EN supply stabilization during 1 1 powering on CPU clock Interrupt for a Stop mode release or b Wait mode release td R S STOP release time td W S Low power consumption mode CPU clock wait mode release time Figure 19 3 Power Supply Circuit Timing Diagram RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 291 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 8 Electrical Characteristics 1 1 H output voltage Parameter P5 5 P5 7 P6_0 to P6 7 P7 2 P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 6 P8 7 P10_0 to P10 7 2 Measuring Condition 1 mA VCC VCCRF 8 3 V Standard Min Typ Max ANTSWCONT IOH 1 mA VCCRF 0 5 VCCRF XOUT HIGHPOWER 0 1 mA VREGOUTS VREGOUT3 0 5 LOWPOWER 50 pA VREGOUTS VREGOUT3 0 5 HIGHPOWER With no load applied LOWPOWER With no load applied L output voltage P5 5 P5 7 P6 Oto P6 7 P7 0to P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 5to P8 7 P10_0 to P10 7 2 IOL 1 mA ANTSWCONT IOL 1 mA XOUT HIGHPOWER IOL 0 1 mA LOWPOWER IOL
12. i20to2 NOTES 1 If an overrun error occurs the receive data of the UiRB register will be indeterminate The IR bit in the SiRIC register does not change 2 Bits UOIRS and U1IRS are bits 0 and 1 in the register U2IRS bit is in U2C1 register 3 The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 148 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Table 13 6 Register Registers Used and Settings in UART Mode 0 to 8 Function Set transmission data 1 0 to 8 Reception data can be read 1 OER FER PER SUM Error flag 0 to 7 Set a bit rate SMD2 to SMDO Set these bits to 100b when transfer data is 7 bits long Set these bits to 101b when transfer data is 8 bits long Set these bits to 110b when transfer data is 9 bits long CKDIR Select the internal clock or external clock STPS Select the stop bit PRY PRYE Select whether parity is included and whether odd or even IOPOL Select the TXD RXD input output polarity CLKO CLK1 Select the count source for the UiBRG register CRS Select CTS or RTS to use functions TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode 3 CKPOL Set to
13. Timer Compare 0 Register 0 BBTCOMPOREGO Verification Mode Set Register BBEVAREG Timer Compare 0 Register 1 BBTCOMPOREG Timer Compare 1 Register 0 BBTCOMP1REGO Timer Compare 1 Register 1 BBTCOMP1REG Timer Compare 2 Register 0 BBTCOMP2REGO Timer Compare 2 Register 1 BBTCOMP2REG Time Stamp Register 0 BBTSTAMPO Time Stamp Register 1 BBTSTAMP1 IDLE Wait Set Register BBIDLEWAIT Timer Control Register BBTIMECON Backoff Period Register BBBOFFPROD ANTSW Output Timing Set Register BBANTSWTIMG RF Initial Set Register BBRFINI PLL Division Register 0 BBPLLDIVL PLL Division Register 1 BBPLLDIVH Transmit Output Power Register BBTXOUTPWR RSSI Offset Register BBRSSIOFS DMAO Source Pointer DMAO Destination Pointer Blank columns are all reserved space No access is allowed Register DMAO Transfer Counter Register DMAO Control Register DMOCON Source Pointer Destination Pointer Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Timer A Count Source Select Register 2 Timer A Waveform Output Function Select Register TAPOFS Transfer Counter Control Register DM1CON DMA2 Source Pointer
14. R01UH0197EJ0120 Jul 21 2011 Rev 1 20 ztENESAS Page 304 of 331 M16C 6B Group 20 Precautions 20 1 SFR 20 1 1 Register Settings Table 20 1 lists Registers with Write Only Bits Set these registers with immediate values When establishing a next value by altering the existing value write the existing value to the RAM as well as to the register Transfer the next value to the register after making changes in the RAM Table 20 1 Registers with Write Only Bits Register Watchdog timer reset register 20 Precautions Address 037Dh Watchdog timer start register 037Eh UARTO bit rate register 0249h UARTI bit rate register 0259h UART2 bit rate register 0269h UARTO transmit buffer register 024Bh to 024Ah UART1 transmit buffer register 025Bh to 025Ah UART2 transmit buffer register 026Bh to 026Ah Timer AO register 0327h to 0326h Timer A1 register 0329h to 0328h Timer A2 register 032Bh to 032Ah Timer A3 register 032Dh to 032Ch Timer A4 register R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS 032Fh to 032Eh Page 305 of 331 M16C 6B Group 20 Precautions 20 2 Reset 20 2 1 VCC When supplying power to the microcomputer the power supply voltage applied to the VCC pin must meet the conditions of SVCC Standard Symbol Parameter MT p Max SVCC Power supply rising gradient VCC Voltage range 0
15. Timer AO Mode Register 00h Timer A1 Mode Register 00h Timer A2 Mode Register 00h Timer A3 Mode Register 00h Timer A4 Mode Register 00h Timer BO Mode Register 00XX0000b Timer B1 Mode Register 00XX0000b Timer B2 Mode Register 00XX0000b NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UH0197EJ0120 Rev 1 20 ztENESAS Page 25 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 11 SFR Information 11 1 Address Register After Reset Pull Up Control Register 1 00000000b Pull Up Control Register 2 00h NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 26 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 12 Address SFR Information 12 1 Register After Reset Count Source Protection Mode Register 00h 2 Watchdog Timer Reset Register XXh Watchdog Timer Start Register XXh Watchdog Timer Control Register 00XXXXXXb DMA2 Source Select Register DMA3 Source Select Register DMAO S
16. oO c gt c oO 2 o es 3 pun z o c a wn a e 2 c 2 o c e amp c 5 WR signal Data bus 2 When the transfer unit is 16 bits and the source address of transfer is an odd address or when the tis 16 bits and an 8 bit bus is used transfer un RD signal WR signal Destination Data bus 3 When the source read cycle under condition 1 has one wait state inserted RD signal WR signal Destination Data bus 4 When the source read cycle under condition 2 has one wait state inserted WR signal Destination Data bus NOTE 1 The same timing changes occur with the respective conditions at the destination as at the source Figure 11 7 Example of Transfer Cycles for Source Read Page 94 of 331 ztENESAS R01UH0197EJ0120 Rev 1 20 Jul 21 2011 M16C 6B Group 11 DMAC 11 2 DMA Transfer Cycles The number of DMA transfer cycles can be calculated as follows Table 11 2 lists the DMAC Transfer Cycles Table 11 3 lists the Coefficients j and k Number of transfer cycles per transfer unit Number of read cycles x j Number of write cycles x k Table 11 2 DMAC Transfer Cycles Transfer Unit 8 bit transfers DMBIT 1 Bus Width
17. Set the AUTORCV1 bit in the BBTXRXMODEO register 1 automatic reception switching enabled IDLE TX ACK IDLE ACK requested RX IDLE No ACK request Set the ACKRCVEN bit in the BBTXRXMODE register 1 automatic ACK reception enabled Set the AUTORCVO bit in the BBTXRXMODEO register 1 automatic reception switching enabled TX IDLE RX ACK IDLE ACK requested 15 3 7 4 CSMA CA Set the CSMATRNST bit in the BBCSMACONO register 1 transmit processing after CSMA CA IDLE CSMA CA IDLE IDLE Result TRUE IDLE CSMA CA IDLE Result FALSE Set the CSMATRNST bit in the BBCSMACONO register 1 transmit processing after CSMA CA Set the AUTORCVO bit in the BBTXRXMODEO register 1 automatic reception switching enabled IDLE IDLE IDLE Result TRUE IDLE IDLE Result FALSE RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 239 of 331 Jul 21 2011 M16C 6B Group 16 CRC Operation 16 CRC Operation The Cyclic Redundancy Check CRC operation detects an error in data blocks The microcomputer uses a generator polynomial of CRC_CCITT X16 X12 X5 1 to generate CRC code The CRC code consists of 16 bits which are generated for each data block in given length separated in 8 bit units After the initial value is set in the CRCD register the CRC code is set in that register each time one byte of data is written to the CRCIN register CRC code generation for one byte data is finished in two cycles F
18. b10 b9 0 Not detected LE Arbitration lost detect flag 2 1 Detected OER Overrun error flag Or overrun error 9 1 Overrun error found 0 No framing error 1 3 Framing error flag 1 Framing error found 0 No parity error 1 3 pe Parity error flag 1 Parity error found 0 No error 1 3 Error eum flag 1 Error found 1 When bits SMD2 to SMDO in the UiMR register 000b serial interface disabled or the RE bit in the UiC1 register 0 reception disabled all of bits SUM PER FER and OER are set to 0 no error The SUM bit is set to 0 no error when all of bits PER FER and OER 0 no error Bits PER and FER are set to 0 by reading the lower byte of the UiRB register The ABT bit is set to 0 by writing 0 in a program Writing a 1 has no effect These error flags are disabled when bits SMD2 to SMDO are set to 001b clock synchronous serial I O mode or to 010b 1 C mode Read as undefined values Figure 13 5 Registers UOTB to U2TB and UORB to U2RB RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 130 of 331 Jul 21 2011 M16C 6B Group Bit Rate Register b7 bo i 0 to 2 2 9 Symbol UOBRG U1BRG U2BRG Function 0249h 0259h 0269h 13 Serial Interface Address After Reset Indeterminate Setting Range If set value n divides the count source by n 1 00h to FFh 1 Write to this register while serial interface is neither transmitting nor receiving
19. f BCLK 32 kHz Wait mode 2 Oscillation capability Low RF off NOTES Stop mode Topr 25 C 1 Referenced to VCC 2 2 to 2 7 V VSS 0 V at 20 to 85 C 40 to 85 C f BCLK 16 MHz unless otherwise specified 2 With one timer operated using fC32 RO1UH0197EJ0120 Rev 1 20 RENESAS Jul 21 2011 Page 299 of 331 M16C 6B Group 19 Electrical Characteristics VCC 2 2 V Timing Requirements VCC 2 2 V VSS 0 V at 20 to 85 C 40 to 85 C unless otherwise specified Table 19 20 Timer A Input Counter Input in Event Counter Mode te TA Parameter input cycle time Standard Min Max tw TAH input H pulse width tw TAL Table 19 21 tc TA input L pulse width Timer A Input Gating Input in Timer Mode Parameter input cycle time Standard Min Max tw TAH input H pulse width tw TAL Table 19 22 tc TA TAIIN input L pulse width Parameter input cycle time Timer A Input External Trigger Input in One Shot Timer Mode Standard Min Max tw TAH input H pulse width tw TAL Table 19 23 input L pulse width Parameter input pulse width Timer A Input External Trigger Input in Pulse W
20. M A transmission complete interrupt is generated on completion of ACK reception 5 TX CSMA CA RX ACK Transmission with ACK request Retransmit processing Figure 15 6 ACK Reception Timing RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 203 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 12 Automatic Reception Switching Function 15 1 12 1 From Transmission to Reception By setting the AUTORCVO bit in the BBTXRXMODEO register to 1 automatic reception switching function enabled reception status is automatically selected after frame transmission is completed Reception status is enabled 184 us after transmission is completed However reception status is not entered but IDLE status is entered if CSMA CA is in busy status during CSMA CA transmission or if no ACK has been received during transmission with an ACK request 15 1 12 2 From Reception to Reception By setting the AUTORCV1 bit in the BBTXRXMODEO register to 1 automatic reception switching enabled reception status is automatically selected after frame reception is completed Reception status is enabled 184 us after reception is completed However ACK response takes priority when ACK response conditions are met while the AUTOACKEN bit in the BBTXRXMODEO register is 1 automatic ACK enabled NOTE 1 After reception is switched while automatic reception switching mode is enabled reception status remains the same until receive op
21. Oscillation stop and re oscillation detect interrupt request occurs e CM14 bit 0 125 kHz on chip oscillator clock oscillates e CM21 bit 1 125 kHz on chip oscillator clock for CPU clock source and clock source of peripheral function CM22 bit 1 main clock stop detected e CM23 bit 1 main clock stopped When the CM20 bit is 1 the system is placed in the following state if the main clock re oscillates from the stop condition Oscillation stop and re oscillation detect interrupt request occurs e CM14 bit 0 125 kHz on chip oscillator clock oscillates CM22 bit 1 main clock re oscillation detected CM23 bit 0 main clock oscillation e CM21 bit remains unchanged R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 59 of 331 M16C 6B Group 7 Clock Generation Circuit 7 6 3 Howto Use Oscillation Stop and Re Oscillation Detect Function The oscillation stop and re oscillation detect interrupt shares the vector with the watchdog timer interrupt If the oscillation stop re oscillation detection and watchdog timer interrupts both are used read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt When the main clock re oscillated after oscillation stop the clock source for the CPU clock and peripheral functions must be switched to the main clock in a program Figure 7 12 shows the Procedure to Switch Clock Source from 125 kHz On Chip Oscillat
22. esee 53 7 5 System Clock Protection Eunction 5 RR UU e qon v dit m ee Ces 58 7 6 Oscillation Stop and Re Oscillation Detect Function eese eene emen nens 59 7 6 1 Operation When CM27 bit 0 Oscillation Stop Detection Reset sse 59 7 6 2 Operation When CM27 bit 1 Oscillation Stop and Re oscillation Detect Interrupt 59 7 6 3 How to Use Oscillation Stop and Re Oscillation Detect Function esse 60 8 Protection i ires eque eite dida te ui nter 61 9 Wo EU 62 9 1 Type of Intert pts 5 rtp ee Leb bane deba EUR EUR EHE EE ab utn 62 9 2 Software Interrupts pere pere erbe 63 9 2 1 Undefined Instruction Interrupt eese ener 63 9 2 2 Overflow Interrupt per em eec aut ire e ete tns 63 9 2 3 Interr pt ons BERE Men er peu EPI E ge DO RETE RE atest 63 9 2 4 INT Instruction Interrupt 2 ect recte ctn ete e eae Mace Saeed oon 63 9 3 Hardware Interrupts ineo enit ei te reto EHE HERO IRR 64 9 3 1 Special Interr pts ates Sieh oh cinco ER EURO Eee meis e vita a 64 9 3 2 Peripheral Function Interrupts 3er eU EGRE RUE RETO SHE E etes nee Den 64 9 4 Interrupts and Interrupt Vector nennen nennen nennen nennen 65 9 4 1 Fixed Vector Tables reesei
23. 0 Not pulled high P8 6 and P8 7 pull up 1 Pulled high Reserved bits Set to 0 P10_0 to P10 3 pull up 0 Not pulled high PU25 P10 410 P10 7 pull up 1 Pulled high b7 b6 No register bits If necessary set to 0 Read as 0 1 To enable the pull up registers the corresponding bit in the register should be set to 1 pulled high and the respective bits in the direction register should be set to 0 input mode 2 The P8 5 pin does not have pull up 3 P8 and P8 1 are not available in the 48 pin version 4 Reserved bit in the 48 pin version Set to 0 Figure 17 7 Registers PUR1 and PUR2 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 248 of 331 Jul 21 2011 M16C 6B Group 17 Programmable I O Ports LED Port Switch Register Symbol Address After Reset LEDCON 0080h 00h 10 Normal P55PWRO 55 drive capacity switch bit 1 Drive capacity high 0 Normal 1 Drive capacity high 4 P57PWR1 P57 drive capacity switch bit Reserved bits Set to 0 Figure 17 8 LEDCON Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 249 of 331 Jul 21 2011 M16C 6B Group 17 Programmable I O Ports Table 17 1 Unassigned Pin Handling in Single Chip Mode Pin Name Connection 2 Ports P5 5 P5 7 P6 One of the followings P7 0to P7 3 P7 4toP7 7 9 Setfor input mode and connect a pin to VSS via resistor pull down P8 0 5 P8 1 5 P8 2 P8 3 Set for input mode and conn
24. 03DCh 03DDh O03DEh 03DFh 03E0h O3E1h 03E2h 03E3h 03E4h 03E5h O3E6h 03E7h 03E8h 03E9h Port P5 Register XXh O3EBh Port P5 Direction Register 00h 03ECh Port P6 Register XXh 03EDh Port P7 Register XXh O3EEh Port P6 Direction Register 00h O3EFh Port P7 Direction Register 00h 0 Port P8 Register U U U XXh O3F ih 03F2h Port P8 Direction Register 00h 03F3h 03F4h Port P10 Register 2 P10 XXh O3F5h O3F6h Port P10 Direction Register 2 PD10 00h 03F7h 03F8h O3F9h O3FAh O3FCh 03FDh O3FEh O3FFh D000h to DO9Fh Transmit RAM TRANSMIT_RAM_START TRANSMIT_RAM_END Receive RAM RECIEVE_RAM_START RECIEVE_RAM_END D1FFh to D7FFh FFFFFh NOTES Option Function Select Address 1 The blank areas are reserved and cannot be accessed by users 2 Reserved area in the 48 pin version No access is allowed 3 OFS1 address is set to FFh when a block including the OFS1 address is erased OFS1 NOTE 3 X Undefined R01UHO0197EJ0120 Rev 1 20 RENESAS Jul 21 2011 Page 29 of 331 M16C 6B Group 5 Reset 5 Reset Hardware reset software reset watchdog timer reset and osc
25. 6 1 UART1 bus collision detection ny 1 Timer B3 and UARTO bus collision detection share the vector and interrupt control register When using Timer B3 interrupt clear the IFSR26 bit to 0 Timer B3 When using UARTO bus collision detection set the IFSR26 bit to 1 2 Timer B4 and UART1 bus collision detection share the vector and interrupt control register When using Timer B4 interrupt clear the IFSR27 bit to 0 Timer B4 When using UART1 bus collision detection set the IFSR27 bit to 1 Figure 9 12 IFSR2A Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 76 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 7 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low The NMI interrupt is a non maskable interrupt To use the NMI interrupt set the PM24 bit in the PM2 register to 1 NMI function 9 8 Key Input Interrupt Of bits P10_4 to P10_7 64 pin version only and P7_0 to P7_3 a key input interrupt is generated when input on any of the pins which has had bits KIENO to KIEN7 in registers KICONO and KICONI set to 1 enabled goes low Key input interrupts can be used as a key on wake up function the function which gets the microcomputer out of wait or stop mode However if using the key input interrupt do not use P10 4 to P10_7 as analog input pins Set 0 input in the port direction register bits PIO 4 to P10 7 64 pin version only and P7 0 to P7 3 of the por
26. A start condition is generated by setting the STAREQ bit in the UiSMR4 register i 0 to 2 to 1 start A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 start A stop condition is generated by setting the STPREQ bit in the UISMRA register to 1 start The output procedure is described below 1 Setthe STAREQ bit RSTAREQ bit or STPREQ bit to 1 start 2 Set the STSPSEL bit in the UiSMR4 register to 1 output The function of the STSPSEL bit is shown in Table 13 14 and Figure 13 30 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 162 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Table 13 14 STSPSEL Bit Functions Function STSPSEL 0 STSPSEL 1 Output of pins SCLi and Output of transfer clock and data Output of a start stop condition SDAi Output of start stop condition is according to bits STAREQ accomplished by a program using RSTAREQ and STPREQ ports not automatically generated in hardware Start stop condition Detect start stop condition Complete generating start stop interrupt request condition generation timing 1 When Slave CKDIR 1 external clock STSPSEL bit 0 ist 2nd 3rd Sth 6th 7th 8th 9th bit bit bit bit bit bit bit bit SCLi LEEFH UU SDAi Start condition Stop condition detection interrupt detection interrupt 2 When Master CKDIR 0 internal clock CKPH 1 clock delayed Setto1in 0 1 Sett
27. Data is set in the UiTB register 1 TI bit in i UiC1 register Data is transferred from the UiTB register to the UARTI transmit register 1 Stop Stop 1 Start bit bit bit mo s Toe En r i N IR bit in SITIC register Set to 0 by an interrupt request acknowledgement or by program i20to2 The above timing diagram applies to the case where the register bits are set as follows i The PRYE bit in the UIMR register 0 parity disabled 16 for 18 EXT The STPS bit in the UiMR register 1 2 stop bits fj frequency of UiBRG count source f1SIO f2SIO f8SIO 132510 The CRD bit in the UiCO register 1 CTS RTS disabled fEXT frequency of UiBRG count source external clock The UiIRS bit in the UiC1 register 0 an interrupt request occurs when transmit buffer n value set to becomes empty Figure 13 21 Transmit Timing UART Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 151 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Example of Receive Timing When Transfer Data is 8 Bits Long Parity Disabled One Stop Bit UiBRG count Source RE bit in UiC1 register Stop bit RXDi Transfer clock Reception triggered when transfer clock 4 Transferred from UARTI receive register is generated by falling edge of start bit 1 RI bit in to UiRB register UiC1 register RTSi IR bit in SiRIC register Set to 0
28. Figure 19 5 Timing Diagram 2 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 297 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 18 Electrical Characteristics 1 1 H output voltage Parameter P5 5 P5 7 P6_0 to P6 7 P7 2 P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 6 P8 7 P10_0 to P10 7 2 Measuring Condition 1 mA VCC VCCRF 2 2 V Standard Min Typ Max ANTSWCONT IOH 1 mA VCCRF 0 5 VCCRF XOUT HIGHPOWER 0 1 mA VREGOUTS VREGOUT3 0 5 LOWPOWER 50 pA VREGOUTS VREGOUT3 0 5 HIGHPOWER With no load applied LOWPOWER With no load applied L output voltage P5 5 P5 7 P6 Oto P6 7 P7 0to P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 5to P8 7 P10_0 to P10 7 2 IOL 1 mA ANTSWCONT IOL 1 mA XOUT HIGHPOWER IOL 0 1 mA LOWPOWER IOL 50 pA XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied Hysteresis TAOIN TA1IN TA2IN to TA4IN 2 INTO INT1 CTSO to CTS2 SCLO to SCL2 SDAO to SDA2 TAOOUT TA10OUT TA2OUT to TA4OUT 2 KIO to 2 KI4 to KI7 RXDO to RXD2 Hysteresis RESET H input current P5 5 P5 7 P6 0 to P6 7 P7 2 P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 6 P8 7 P10 0to P10 7 2 XIN RESET
29. Figure 9 8 Operation of Saving Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 73 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 5 8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine Thereafter the CPU returns to the program which was being executed before accepting the interrupt request Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction 9 5 9 Interrupt Priority If two or more interrupt requests are sampled at the same sampling points a timing to detect whether an interrupt request is generated or not the interrupt with the highest priority is acknowledged For maskable interrupts peripheral functions interrupt any desired priority level can be selected using bits ILVL2 to ILVLO However if two or more maskable interrupts have the same priority level their interrupt priority is resolved by hardware with the highest priority interrupt accepted The watchdog timer and other special interrupts have their priority levels set in hardware Figure 9 9 shows the Hardware Interrupt Priority Software interrupts are not affected by the i
30. In inverse format set the PRYE bit to 1 the PRY bit to O odd parity the UFORM bit to 1 MSB first and the U2LCH bit to 1 inverted When data are transmitted values set in the U2TB register are logically inversed and are transmitted with the odd numbered parity starting from D7 When data are received received data are logically inversed to be stored in the U2RB register starting from D7 The odd numbered parity determines whether a parity error occurs Figure 13 39 shows the SIM Interface Format 1 Direct format Transfer clock d Txp2 P Even parity 2 Inverse format Transfer clock qx TXD2 H P Odd parity Figure 13 39 SIM Interface Format RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 176 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 A D Converter 64 Pin Version Only The microcomputer contains one A D converter circuit based on 10 bit successive approximation method The analog inputs share the pins with P10_0 to P10_7 Therefore when using these inputs make sure the corresponding port direction bits are set to 0 input mode When not using the A D converter set the ADSTBY bit to 0 A D operation stop standby so that no current will flow for the A D converter helping to reduce the power consumption of the chip The A D conversion result is stored in the ADi register for pins ANi i 0 to 7 Table 14 1 lists the A D Converter Specifica
31. M16C 6B Group 7 Clock Generation Circuit The following describes the clocks generated by the clock generation circuit 7 1 1 Main Clock This clock is provided by the main clock oscillation circuit It is used as the reference clock source for the CPU and peripheral function clocks and the transceiver The main clock oscillation circuit is configured by connecting a resonator between pins XIN and XOUT The main clock oscillation circuit contains a feedback resistor which is disconnected from the oscillation circuit during stop mode in order to reduce the amount of power consumed in the chip Figure 7 6 shows the Examples of Main Clock Connection Circuit The power consumption in the chip can be reduced by setting the CMO5 bit in the register to 1 main clock oscillation circuit turned off after switching the clock source for the CPU clock to a subclock or 125 kHz on chip oscillation clock In this case XOUT goes H During stop mode all clocks including the main clock are turned off Refer to 7 4 Power Control for details Microcomputer Built in feedback resistor Oscillator LI NOTE 1 Place a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by each oscillator manufacturer When the oscillation drive capacity is set to low check if oscillation is stable at low Also place a feedback resistor between XIN and
32. S TMOD1 to TMODO 00 Timer mode 10 One shot timer mode 9 11 PWM mode 1 Timer interrupt 01 Event counter mode 2 o Is lo iS gt Noise filter TCK1 to TCKO TMOD1 to TMODO 00 Timer mode 10 One shot timer mode 3 11 PWM mode Timer A4 interrupt 01 Event counter mode 2 TA4TGH to TA4TGL S S S S Q Timer B2 underflow TCK1 to TCKO TMOD1 to TMODO bits in the TAiMR register i 0 to 4 TAIGH to TAiGL bits in the ONSF register or TRGSR register i 0 to 4 TCSO to TCS7 bits in registers TACSO to TACS2 NOTES 1 64 pin version only 2 In the 48 pin version external pin input cannot be used as a count source 3 In the 48 pin version external pin input or output cannot be used as a count source Figure 12 2 Timer A Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 99 of 331 Jul 21 2011 M16C 6B Group fC32 fOCO S f64TIMAB f32TIMAB f8TIMAB fI TIMAB or f2TIMAB Figure 12 3 Timer B Configuration 12 Timers Timer B2 underflow to a count source of Timer A TCK1 to TCKO o E4 TMOD1 to TMODO 00 Timer mode gt s S E Timer BO interrupt Timer BO 09 01 Event counter mode TMOD1 to TMODO 00 Timer mode
33. Transmission overrun A transmission overrun interrupt is generated when the internal transmit counter value is equal to or greater than the write address after transmission starts 50 Reception overrun 0 A reception overrun 0 interrupt is generated when data reception restarts at bank 0 while the RCVBANKO bit in the BBTXRXSTO register is set to 1 received data present 51 Reception overrun 1 A reception overrun 1 interrupt is generated when data reception restarts at bank 1 while the RCVBANK 1 bit in the BBTXRXSTO register is set to 1 received data present 44 1 IDLE An interrupt request is generated after the IDLE startup time has elapsed 45 2 NOTES Clock regulator An interrupt request is generated when the clock regulator startup time has elapsed 1 Switchable by using the BANKOINTSEL bit in the BBTXRXMODE4 register 2 Switchable by using the BANK1INTSEL bit in the BBTXRXMODE4 register R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 199 of 331 M16C 6B Group 15 Baseband Functionality 15 1 9 CRC Circuit The CRC circuit automatically performs operations for transmit frames and receive frames A generator polynomial X16 X12 X5 1 is used to generate CRC code 8 bit data is input beginning with the start of the payload data and 16 bit code is generated For transmission the CRC circuit starts CRC operation from the start address of transmit RAM
34. Transmit buffer empty flag Transmit buffer empty flag RE Set this bit to 1 to enable reception Set this bit to 1 to enable reception RI Reception complete flag Reception complete flag UilRS 1 Invalid Invalid UiRRM 1 UiLCH UiERE Set to 0 Set to 0 Set to 1 Set to 1 ABC Select the timing at which arbitration lost is detected Invalid BBS Bus busy flag Bus busy flag 3to7 Set to 0 Set to 0 i Oto2 NOTES 2 Refer to Table 13 13 12C Mode Functions Refer to Table 13 13 I2C Mode Functions CSC Set this bit to 1 to enable clock synchronization Set to 0 SWC Set this bit to 1 to have SCLi output fixed to L at the falling edge of the 9th bit of clock Set this bit to 1 to have SCLi output fixed to L at the falling edge of the 9th bit of clock ALS Set this bit to 1 to have SDAi output stopped when arbitration lost is detected Set to 0 STAC Set to 0 Set this bit to 1 to initialize UARTI at start condition detection SWC2 Set this bit to 1 to have SCLi output forcibly pulled low Set this bit to 1 to have SCLi output forcibly pulled low SDHI Set this bit to 1 to disable SDAi output Set this bit to 1 to disable SDAi output 7 Set to 0 Set to 0 1 Set the bit 4 and bit 5 in registers UOC1 and U1C1 to 0 Bits UOIRS U1IRS UORRM and U1RRM are
35. ne a Pet Ur aee pe 31 54 Oscillation Stop Detection Reset 31 5 5 Internal Space mitem iie e tert 32 6 MOC C M 33 6 1 Types ob Processor MOGe i ee ert ete e ee sie tack e i E eed 33 6 2 Setting Processor Modes geras eee eite mier tete iere een 33 6 3 Internal MemOoty uester cte eife ttd tee etie eve tees dus doeet oet ene aede es 35 7 Clock Generation Circuit e ai a a a a a aa re a aa a EL EE 36 7 1 Type of the Clock Generation Circuit esses ener nennen treten en nennen nenne 36 7 1 1 Man Clock dcc 42 7 1 2 kiled odqu m c Sa gs MS Te ay 43 7 1 3 125 kHz On Chip Oscillator Clock fOCO S enne nennen ene 43 7 2 CPU Clock and Peripheral Function Clock 44 7 2 1 CPU Clock and BCLR dee En ree Ute 44 7 2 2 Peripheral Function Clock 1 1032 ere cei Heri hte e bee euin eet 45 7 3 Clock Output F nction te oe eolit eee a Re 45 7 4 Power Control fot eere o ee te e Hen o Mb catia ip or en dee Fs 46 7 4 1 Normal Operating Mode ine dete teret Re eb deep tt r r 46 7 4 2 bii 48 7 4 3 Stop Mode esee teme sak Bisons since Hepes E RED pee e Sete ate DR 50 7 4 4 Power Control of Flash Memory
36. transferred to counter when reloaded next 1 Bits TBOS to TB2S are assigned to bits 5 to 7 in the TABSR register and bits TB3S to TB5S are assigned to bits 5 to 7 in the TBSR register Timer Bi Mode Register i 0 to 5 b7 b6 b5 b4 b3 b2 b1 bO 11 Xojo o o Symbol Address After Reset TBOMR to TB2MR 033Bh to 033Dh 00XX0000b TB3MR to TBSMR 031Bh to 031Dh 00XX0000b Bit Name Function Operation mode select bit 0 0 Timer mode TMOD1 RW Ww b3 b2 Reserved bits Set to 0 b4 No register bit If necessary set to 0 Read as undefined value MR3 Write 0 in timer mode Read as undefined value in timer mode b7 b6 0 0 f1TIMAB or f2TIMAB Count source select bit 9 0 1 fSTIMAB 1 0 fS2TIMAB R 1 1 fC32 1 Selected by the PCLKO bit in the PCLKR register 2 Valid when the TCS3 bit or TCS7 bit in registers TACSO to TACS2 is set to 0 TCKO TCK1 enabled Figure 12 23 TBiMR Register in Timer Mode RO1UH0197EJ0120 Rev 1 20 24 N SAS Page 124 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 2 2 Event Counter Mode In event counter mode the timer counts underflows of other times refer to Table 12 8 Figure 12 24 shows the TBiMR Register in Event Counter Mode Table 12 8 Specifications in Event Counter Mode Item Specification Count source Timer Bj underflow j 2i 1 exceptj22ifi20 j25ifi 3 Count operation Decrement When the timer underflows it reloads the reload regi
37. 2 Valid when bits TAITGH and TAiTGL in the ONSF register or TRGSR register are set to 00b TAIIN pin input 3 Set the port direction bit for the TAiIN pin to 0 input mode 4 Selected by the PCLKO bit in the PCLKR register 5 Valid when the TCS3 bit or TCS7 bit in registers TACSO to TACS2 is set to 0 TCK0 TCK1 enabled 6 Only i 0 or 1 in the 48 pin version Figure 12 15 TAiMR i 0 to 4 Register in One Shot Timer Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 116 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 1 5 Pulse Width Modulation PWM Mode Only i 0 or 1 in the 48 Pin Version In PWM mode the timer outputs pulses of a given width in succession refer to Table 12 6 The counter functions as either 16 bit pulse width modulator or 8 bit pulse width modulator Figure 12 16 shows the TAiMR 1 0 1 Register in PWM Mode Figures 12 17 and 12 18 show an Example of 16 Bit Pulse Width Modulator Operation and 8 bit Pulse Width Modulator Operation respectively Table 12 6 Specifications in PWM Mode Item Specification Count source f1TIMAB f2TIMAB f8TIMAB f32TIMAB fe4TIMAB fOCO S fC32 Count operation Decrement operating as an 8 bit or a 16 bit pulse width modulator The timer reloads a new value at a rising edge of PWM pulse and continues counting The timer is not affected by a trigger that occurs during counting 16 bit PWM Pulse width n fj n set value of the TAi re
38. 8 MHz 8 5 mA RF off MCU f BCLK 8 MHz 6 5 mA Tx MCU f BCLK 16 MHz 41 mA Rx MCU f BCLK 16 MHz 52 mA RF idle MCU f BCLK 16 MHz 12 mA RF off MCU f BCLK 16 MHz 10 mA RF off MCU f BCLK 32 kHz low power consumption mode 70 pA RF off MCU f BCLK stop stop mode 3 uA Operating temperature 20 C to 85 C 40 C to 85 C Package PVQNOO064KA A PVQNO048KB A R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 3 of 331 M16C 6B Group 1 Overview 1 3 Product List Table 1 3 lists product information Figure 1 1 shows part numbers memory sizes and packages Table 1 3 R5F36BSENNP Product List ROM Capacity Program ROM1 256 Kbytes Program ROM2 R5F36B4BNNP 192 Kbytes 16 Kbytes Data Flash 4 Kbytes x 2 blocks RAM Capacity 20 Kbytes Package Code PVQNO0064KA A PVQNO0048KB A As of July 2011 Remarks Operating temperature 20 C to 85 C R5F36BSEDNP 256 Kbytes R5F36B4BDNP D 192 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 20 Kbytes PVQNO0064KA A PVQNO0048KB A Operating temperature 40 C to 85 C D Under development PartNo 5 F36B3EN NP E Package type NP Package PVQN0064KA A PVQN0048KB A Property code N Operating temperature 20 C to 85 C D Operating temperature 40 C to 85 C Memory capacity Program ROM 1 RAM B 192 Kbytes 2
39. 9 2 2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to 1 the operation resulted in an overflow The followings are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB 9 2 3 BRK Interrupt A BRK interrupt occurs when executing the BRK instruction 9 2 4 INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction Software interrupt Nos 0 to 63 can be specified for the INT instruction Because software interrupt Nos 5 to 31 and 41 to 51 are assigned to peripheral function interrupts the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction In software interrupt Nos 0 to 31 the U flag is saved to the stack during instruction execution and is cleared to 0 ISP selected before executing an interrupt sequence The U flag is restored from the stack when returning from the interrupt routine In software interrupt Nos 32 to 63 the U flag does not change state during instruction execution and the SP selected at the time is used R01UH0197EJ0120 Rev 1 20 24 NC SAS Page 63 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 3 Hardware Interrupts Hardware interrupts are classified into two types special interrupts and peripheral function interrupts 9 3 1 Special Interrupts Special interrupts
40. CNVSS L input current P5 5 P5 7 P6 Oto P6 7 P7 0to P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 5to P8 7 P10 Oto P10 7 2 XIN RESET CNVSS Pull up resistance P5 5 P5 7 P6_0 to P6 7 P7 2 P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 6 P8 7 P10_0 to P10 7 2 Feedback resistance XIN Feedback resistance XCIN NOTES RAM retention voltage At stop mode 1 Referenced to VCC 2 2 to 2 7 V VSS 0 V at 20 to 85 C 40 to 85 C f BCLK 16 MHz unless otherwise specified 2 64 version only R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 298 of 331 M16C 6B Group 19 Electrical Characteristics Table 19 19 Electrical Characteristics 2 1 Parameter Power In single chip Flash memory supply mode the current output pins are open and other pins are VSS VCC VCCRF 2 2 V Measuring Condition f BCLK 4 MHz RF off Standard Min Typ Max divided by 4 RF idle RF Tx RF Rx BCLK 8 MHz RF off divided by 2 RF idle RF Tx RF Rx 125 kHz On chip oscillation No division RF off f BCLK 32 kHz Low power consumption mode RF off 125 kHz On chip oscillation wait mode RF off f BCLK 32 kHz Wait mode 2 Oscillation capability High RF off
41. Preamble Sequence Frame control number Address information Figure 15 3 Transmit Frame Structure SHR Synchronization Header PHR PHY Header MPDU MAC Protocol Data Unit SFD Start of Frame Delimiter FL Frame Length MSDU MAC Service Data Unit CRC Cyclic Redundancy Check 1 Preamble 4 bytes 8 symbols 00000000h 2 SFD 1 byte 2 symbols A7h 3 FL 1 byte 2 symbols MPDU length value written into the BBTXFLEN register 4 MPDU Maximum 127 byte data Data written into transmit RAM is sequentially output When the NOCRC bit in the BBTXRXMODE2 register is set to 0 automatic CRC enabled CRC data generated in the CRC circuit is automatically added to the last 2 bytes Frame control 2 bytes 4 symbols Frame types bits 2 to 0 000b Beacon frame 001b Data frame 010b ACK frame 011b MAC command frame 100b 111b Reserved Security enabled or disabled bit 3 transmit pending bit bit 4 ACK request bit 5 transmission within a PAN bit 6 Source address mode bits 10 and 11 destination address mode bits 14 and 15 Sequence number 1 byte 2 symbols Address information PANID and addresses of the destination and source MSDU MAC payload Frame payload CRC Frame CRC queue RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 197 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 7 Filter Function 15 1 7 Address Filter The ADRSFILEN bit in BBTXRXMODES3 register c
42. RFIOP 4 94 RFION lt 8 top view VSSRF4B ANTSWCONT 10 VREGOUT2 11 VSSRF5 12 VREGOUT3 NOTES 1 N channel open drain output 2 Confirm the position of pin 1 by referring to Package Dimensions Figure 1 4 48 Pin Assignment Top View R01UH0197EJ0120 Rev 1 20 ztENESAS Page 7 of 331 Jul 21 2011 M16C 6B Group 1 Overview Table 1 4 Pin Names 1 1 VSSRF2 Interrupt Pin Timer Pin UART Pin Clock Pin control Pin VREGIN1 VSSRF3 VREGIN2 VSSRF1 VREGOUT1 VREGIN3 CO A Aj VSSRF4A VSSRF4B TESTION TESTIOP ANTSWCONT VREGOUT2 VSSRF5 VSSRF6 VREGIN4 TASIN TA3OUT TA2IN TA20UT TXD1 SDA1 RXD1 SCL1 CLK1 CTS1 RTS1 CTSO CLKS1 TA4IN TA4OUT TXDO SDAO RXDO SCLO CLKO CTSO RTSO VREGOUT3 XIN VSS2 XOUT TA11OUT CLKOUT TAO1OUT TA1N CTS2 RTS2 NOTE TA100UT CLK2 1 Some pins are used for communication with the debugger during debugging R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 8 of 331 M16C 6B Group 1 Overview Table 1 5 Pin Names 2 1 EU e TimerPin U
43. Timer A3 Timer A3 Timer A4 Both edges of INTO pin Timer A4 Timer BO Timer B3 Timer BO Timer B3 Timer B1 Timer B4 Timer B1 Timer B4 Timer B2 UARTO transmission Timer B5 Timer B2 UARTO transmission Timer B5 UARTO reception UARTO reception UART2 transmission UART2 transmission UART2 reception UART2 reception A D conversion 64 pin version only A D conversion 64 pin version only UART1 transmission UART1 reception 0000b UART1 transmission UART1 reception 0001b 0010b 0011b 0100b 0101b 0110b 0111b X indicates 0 or 1 indicates no setting DMA1 DSEL4 to DSELO DMS 0 Basic Factor of Request Falling edge of INT1 pin DMS 1 Extended Factor of Request 11XXXb X indicates 0 or 1 indicates no setting DMAS3 DSEL4 to DSELO 00000b DMS 0 Basic Factor of Request DMS 1 Extended Factor of Request Software trigger 00001b Software trigger Timer AO 00010b Timer AO Timer A1 00011b Timer A1 Timer A2 00100b Timer A2 Timer A3 00101b Timer A3 Timer A4 Both edges of INT1 pin 00110b Timer A4 Timer BO 00111b Timer BO Timer B1 000b Timer B1 Timer B2 001b Timer B2 UARTO transmission 010b UARTO transmission UARTO reception ACKO 011b UAR
44. UiRB register UiRB register i Oto2 This diagram applies to the case where the following condition is met The CKDIR bit in the register 0 slave selected Figure 13 28 Transfer to UiRB Register and Interrupt Timing RO1UH0197EJ0120 Rev 1 20 zeENESAS Page 161 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 3 1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined A start condition detect interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state A stop condition detect interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state Because the start and stop condition detect interrupts share the interrupt control register and vector check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt to 6 cycles lt duration for setting up to 6 cycles lt duration for holding Duration for Duration for setting up holding SCLi SDAi Start condition I 1 SDA i 1 Stop condition i Oto2 The above applies to the case where the PCLK1 bit in the PCLKR register 1 this is the cycle number of f1SIO and the PCLK1 bit 0 the cycle number of f2SIO Figure 13 29 Detection of Start and Stop Condition 13 1 3 2 Output of Start and Stop Condition
45. bit 2 0 transmit buffer empty when transferring data from the UiTB register to the UARTI transmit register at start of transmission The UiIRS bit 1 transfer completed when the serial interface completes sending data from the UARTi transmit register For reception When transferring data from the UARTi receive register to the UiRB register at completion of reception Error detection Overrun error 1 This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data Framing error 3 This error occurs when the number of stop bits set is not detected Parity error 3 This error occurs when if parity is enabled the number of 1 in parity and character bits does not match the number of 1 set Error sum flag This flag is set to 1 when any of the overrun framing or parity errors occur Select function LSB first MSB first selection Whether to start sending receiving data beginning with bit O or beginning with bit 7 can be selected Serial data logic switch This function reverses the logic of the transmit receive data The start and stop bits are not reversed TXD I O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input The logic levels of all I O data are reversed Separate CTS RTS pins UARTO CTSO and RTSO input output from separate pins
46. edere eta 256 18 2 4 Standard Serial I O Mode Disable Function essent rennen enne 256 18 3 CPU Rewrite Mode bn eto prete ite Uie aif ipse tate 258 18 3 I Gated eem dni 259 18 3 2 SEW Mode m 259 18 3 3 Flash Memory Control Register Registers FMRO FMR1 FMR2 and FMR6 260 18 3 4 Software Commands oireisiin teet aces te nr 267 18 3 5 Data Protect FUNCIO eio eee eie ferie ne n Fuerte tdeo Rosie con e eds 273 18 3 6 Status Register eter e tis ER RED Het OE He PR 273 18 3 7 FullStatus Check e eoi Ete t eU pu teris Op bt e ea 275 18 4 Standard Serial I O Mode 5 iet a Dor itte opp EI tr pH 277 18 41 ID Code Check Function i IRR teen rp bien tition eed 277 18 4 2 Example of Circuit Application in the Standard Serial I O Mode sese 281 18 5 Parallel VO Mode a neret Bee aah Pepe A a a enge 283 18 51 ROM Code Protect Function e tte e eerte ete edere deer enirn 283 18 6 Notes on Flash Memory eee a restent ee E eee Porte e te be pede dod 284 18 6 1 Functions to Prevent Flash Memory from Being Rewritten esee 284 18 6 2 Reading Data QUID UID Ud exuit 284 18 6 3 CPU Rewrite Mode tei Ro eite iie ah eas 284 18 6 4 User Boot Mode oce D rere pite be eie tee une apte itta RAY 285
47. 16 bit BYTE L Access Address Single Chip Mode No of Read Cycles No of Write Cycles 16 bit transfers DMBIT 0 16 bit BYTE L indicates that no condition exists Table 11 3 Coefficients j and k Internal Area Internal ROM RAM No Wait With Wait R01UH0197EJ0120 Rev 1 20 Jul 21 2011 zeENESAS Page 95 of 331 M16C 6B Group 11 DMAC 11 3 DMA Enabled When a data transfer starts after setting the DMAE bit in the DMiCON register i 0 to 3 to 1 enabled the DMAC operates as follows a Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is 1 forward or the DARi register value when the DAD bit in the DMiCON register is 1 forward b Reload the DMAi transfer counter with the DMAi transfer counter reload register value If the DMAE bit is set to 1 again while it remains set the DMAC performs the above operation However if a DMA request may occur simultaneously when the DMAE bit is being written follow the steps below 1 Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously 2 Make sure that the DMAi is in an initial state as described above 1 and 2 in a program If the DMAi is not in an initial state the above steps should be repeated 11 4 DMA Request The DMAC can generate a DMA request as triggered by the factor of request that is sele
48. 19 Electrical Characteristics ennemi ideerne aiian 286 19 1 Electrical Characteristics ec eemper drei re ei eene ERR enr 286 205 1 asst tieu oct bade dea hie AA er cat poets aca shades Teneo 305 20 1 SPER snenntueeatUpener ede edere o eene aen te 305 20 1 1 Register Settings deese comete eie eere i lect dye tec es atto d eie 305 20 2 Reset iSo PREIS ERREUR IDEE 306 202 1 WCG xen bee dT e ee dade itc ica onte ite eoe 306 20 2 2 CGNWSS E eee en pU hne e pepe COR 306 20 3 Baseband Functions cet end ep Herb Ie PE EEES SE epe de reges os cone 307 20 4 Power Control tec pe RA outing tei os e etti ite aite 308 20 5 Int rr pt asesores URNA den ERERAD Race RA 310 2055 1 R admngaddress 00000h inre tte eaten eee e tees 310 20 5 2 SP Set ng seen Ier DOO ERR rere OH REO Oa RFE 310 20 53 n dl o ota adt ea tiis CUm ad 310 20 5 4 Changing an Interrupt Generate Factor sesessesseeseeeeeeeeeneen 311 DOSS INT Intercept odi NU IRE EI 311 20 5 6 Rewriting the Interrupt Control Register ener ener nre 312 20 5 7 Watchdog Timer Interrupt sese enr en nennen treten nennen 313 20 6 E 314 20 6 1 Write to the DMAE Bit in the DMiCON Register 1 0 0 3 esset 314 20 7 TIMET Seo M D ES 315 20 713 S mu P
49. 2 Use MOV instruction to write to this register 3 Write to this register after setting bits CLK1 to CLKO in the UiCO register UARTi Transmit Receive Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol UOMR U1MR U2MR Address After Reset 0248h 0258h 0268h Bit Name Function RW SMDO SMD1 SMD2 CKDIR STPS PRYE Serial I O mode select bit Internal external clock select bit Stop bit length select bit Odd even parity select bit Parity enable bit TXD RXD I O polarity reverse bit 20160 Serial interface disabled Clock synchronous serial mode mode 9 UART mode transfer data 7 bits long UART mode transfer data 8 bits long UART mode transfer data 9 bits long not set except above 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 n 1 1 1 D 0 Internal clock 1 External clock 0 1 stop bit 1 2 stop bits Valid when PRYE 1 0 Odd parity 1 Even parity 0 Parity disabled 1 Parity enabled 0 No reverse 1 Reverse 1 Set the corresponding port direction bit for each CLKi pin to 0 input mode 2 To receive data set the corresponding port direction bit for each RXDi pin to 0 input mode 3 Set the corresponding port direction bit for pins SCL and SDA to 0 input mode Figure 13 6 Registers UOBRG to U2BRG and UOMR to U2MR R01UH0197EJ0120 Rev 1 20 Page 131 of 331 Jul 21 2011 ztENESAS M16C 6B Group 13 Serial Interface UARTi
50. KIEN4 bit KICON1 register K7 O Direction register Pull up KIENS bit in KICONO register transistor ot 2 EK Direction register Pull up KIEN2 bit in KICONO register transistor m ot aW Direction register Pull up KIEN1 bit in KICONO register transistor Direction register Pull up KIENO bit in KICONO register transistor 1 to in the 48 pin version cannot be used Figure 9 13 Block Diagram of Key Input Interrupt RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 78 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt Key Input Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset KICONO 0082h 00h Key input 0 interrupt enable 0 Disabled bit Enabled KIENO KIEN1 Key input 1 interrupt enable 0 Disabled bit Enabled Key input 2 interrupt enable 0 Disabled KIEN2 Enabled Key input 3 interrupt enable 0 Disabled KIENS Enabled 1 When the 48 pin version is used make sure to set 00h key input 0 to 3 interrupt disabled Figure 9 14 KICONO Register Key Input Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset KICON1 0083h 00h Key input 4 interrupt enable 0 Disabled Key input 5 interrupt enable 0 Disabled KIENS eit Enabled Key input 6 interrupt enable 0 Disabled bit Enabled KIEN6 RW Key input 7 inter
51. Key Input Control Register 1 KICON1 Timer A I O Control Register TAICON Blank columns are all reserved space No access is allowed Register Baseband Control Register BBCON Register Transmit Receive Reset Register BBTXRXRST Transmit Receive Mode Register 0 BBTXRXMODEO Transmit Receive Mode Register 1 BBTXRXMODE1 Receive Frame Length Register BBRXFLEN Receive Data Counter Register BBRXCOUNT RSSI CCA Result Register BBRSSICCARSLT Transmit Receive Status Register 0 BBTXRXSTO Transmit Frame Length Register BBTXFLEN Transmit Receive Mode Register 2 BBTXRXMODE2 Transmit Receive Mode Register 3 BBTXRXMODE3 Receive Level Threshold Set Register BBLVLVTH Transmit Receive Control Register BBTXRXCON CSMA Control Register 0 BBCSMACONO CCA Threshold Level Set Register BBCCAVTH Transmit Receive Status Register 1 BBTXRXST1 RF Control Register BBRFCON Transmit Receive Mode Register 4 BBTXRXMODE4 CSMA Control Register 1 BBCSMACON1 CSMA Control Register 2 BBCSMACON2 PAN Identifier Register BBPANID Short Address Register BBSHORTAD Expansion Address Register BBEXTENDADO BBEXTENDAD1 BBEXTENDAD2 BBEXTENDAD3 Timer Read Out Register 0 BBTIMEREADO Timer Read Out Register 1 BBTIMEREAD1
52. Page 160 of 331 M16C 6B Group 13 Serial Interface 1 IICM2 0 ACK and NACK interrupts CKPH 0 no clock delay 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit sw spai 07 X De X D5 X X_D2 D X DO X D8 ACK NACK ACK interrupt DMA1 request NACK interrupt 4 Transfer to UiRB register b15 b9 b8 b7 b0 O Cee ees Tos e Too UiRB register 2 2 0 CKPH 1 clock delay 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit seu LLL ET TET El 1L spai A D7 X De Xs X X X D2 X X DB ACK NACK 4 ACK interrupt DMA1 DMA3 request NACK interrupt Transfer to UiRB register b15 b9 b8 b7 bo gt os os 020 oo UiRB register 3 2 1 UART transmit receive interrupt CKPH 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit spai X07 X De X D5 X D4 X D1 X Do X D8 ACK tt Receive interrupt Transmit DMA1 DMA3 interrupt request 4 Transfer to UiRB register b15 b9 b8 b7 2 UiRB register 4 IICM2 1 CKPH 1 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi sow CET Coe Cos Cor Cos X bE NAOH TE Receive interrupt Transmit interrupt DMA1 DMA3 request Transfer to UiRB register Transfer to UiRB register b15 b9 b8 b7 b0 b15 b9 b8 b7 b0 O O
53. Resetting procedure Return to the prior frequency of the CPU clock Slow read mode is completed Figure 7 10 Setting and Resetting of Slow Read Mode R01UH0197EJ0120 Rev 1 20 ztENESAS Page 56 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 4 4 _Low Current Consumption Read Mode This mode can be used when the CMO07 bit in the register is set to 1 subclock used as CPU clock Figure 7 11 shows Setting and Resetting of Low Current Consumption Read Mode Low current consumption read mode Write 1 to the CMO7 bit to select the subclock in CPU clock Set the CMO5 bit to 1 main clock oscillation stop Setting d procedure After writing 0 write 1 enabled to the FMR22 bit After writing O write 1 enabled to the FMR23 bit Process in low current consumption mode Write 0 to the FMR23 bit Resetting he FMR22 bit Write 0 to the bit gt Return to the prior CPU clock Slow read mode is completed NOTE 1 Do not write the FMR22 bit and FMR23 bit at the same time Figure 7 11 Setting and Resetting of Low Current Consumption Read Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 57 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 5 System Clock Protection Function The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is selected as the CPU clock source This is to prevent the CPU
54. Therefore a transmit timing and receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting side The RTS function is disabled when an internal clock is selected RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 321 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 8 1 2 Transmission If an external clock is selected the following conditions must be met while the external clock is held H when the CKPOL bit in the UiCO register i 0 to 2 is set to 0 transmit data output at the falling edge and receive data input at the rising edge of the serial clock or while the external clock is held when the CKPOL bit is set to 1 transmit data output at the rising edge and receive data input at the falling edge of the serial clock The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in the UiTB register If CTS function is selected input on the CTSi pin L 20 8 1 3 Reception In clock synchronous serial I O mode the shift clock is generated by activating a transmitter Set the UARTi associated registers for a transmit operation even if the MCU is used for receive operation only Dummy data is output from the TXDi pin i 0 to 2 while receiving When an internal clock is selected the shift clock is generated by setting the TE bit in the UiC1 register to 1 transmission enabled and placing dummy data in the UiTB r
55. edge and the receive data taken in at the rising edge of the transfer clock e AI ES BE LI Ede eee during no transmission TXDi RXDi po X D4 X ps X pe X v7 2 When the CKPOL bit 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock L is output from the CLKi pin during no transmission CLKi LL LY Ele TXDi RXDi Do X ba X ps X D4 X ps X pe The above applies to the case where the UFORM bit in the UiCO register 0 LSB first and the UiLCH bit in the UiC1 register 0 no reverse i Oto2 Figure 13 16 Transfer Clock Polarity R01UH0197EJ0120 Rev 1 20 ztENESAS Page 144 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 1 3 LSB First MSB First Select Function Use the UFORM bit in the UiCO register i 0 to 2 to select the transfer format Figure 13 17 shows the Transfer Format 1 When the UFORM Bit in the UiCO Register 0 LSB First CLKi TXDi DO X D D4 X 05 X De X D7 RXDi bo X D X X X 05 X D6 X_D7 2 When the UFORM Bit in the UiCO Register 1 MSB First CLKi 07 X D5 X02 X D1 X Do RXDi D7 X D6 X D5 X X D2 X D X DO The above applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clo
56. instruction is completed a on Figure 9 6 and a time during which the interrupt sequence is executed b on Figure 9 6 Interrupt request Interrupt request generated acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine a b Interrupt response time a A time from when an interrupt request is generated till when the instruction at the time executing is completed The length of this time varies with the instruction being executed The DIVX instruction requires the longest time which is equal to 30 cycles without wait state the divisor being a register b A time during which the interrupt sequence is executed For details refer to the table below Note however that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single step interrupts Interrupt Vector Address SP Value 16 Bit Bus Without Wait 8 Bit Bus Without Wait 18 cycles 20 cycles 19 cycles 20 cycles 19 cycles 20 cycles 20 cycles 20 cycles Figure 9 6 Interrupt Response Time 9 5 6 Variation of IPL When Interrupt Request IS Accepted When a maskable interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL When a software interrupt or special interrupt request is accepted one of the interrupt priority levels listed in Table 9 6 is set in the IPL Table 9 6 lists the IPL Level That is Set to IP
57. 0 UFORM LSB first or MSB first can be selected when transfer data is 8 bits long Set this bit to 0 when transfer data is 7 or 9 bits long TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag UiIRS 2 Select the source of UARTi transmit interrupt UiRRM 2 Set to 0 UiLCH Set this bit to 1 to use reversed data logic UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 i 0to2 NOTES UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set to 0 CLKMDO Invalid because CLKMD1 0 CLKMD1 Set to 0 RCSP Set this bit to 1 to accept as input CTSO signal of UARTO from the P6_4 pin 7 Set to 0 1 The bits used for transmit receive data are as follows bit 0 to bit 6 when transfer data is 7 bits long bit O to bit 7 when transfer data is 8 bits long bit 0 to bit 8 when transfer data is 9 bits long 2 Set the bit 4 and bit 5 in registers UOC1 and U1C1 to 0 Bits UOIRS U1IRS UORRM U1RRM are included in the UCON register 3 TXD2 pin is N channel open drain output Set the NCH bit in the U2CO register 0 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 34 NC SAS Page 149 of 331 M16C 6B Group 13 Serial Interface Table 13 7 lists the
58. 1 TCKO TCK1 enabled TCSO to TCS2 TBi count source option disabled specified bit 0 TCKO TCK1 disabled TCSO to TCS2 enabled No register bits If necessary set to 0 Read as undefined value TBCS1 register i 2 TBCS3 register i 5 NOTE 1 Set this value at the PCLKO bit in the PCLKR register Figure 12 22 Registers TBCSO to TBCS3 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 123 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 2 1 Timer Mode In timer mode the timer counts a count source generated internally refer to Table 12 7 Figure 12 23 shows the TBiMR Register in Timer Mode Table 12 7 Specifications in Timer Mode Item Specification Count source f1TIMAB f2TIMAB f8TIMAB f32TIMAB fe4TIMAB fOCO S fC32 Count operation Decrement When the timer underflows it reloads the reload register contents and continues counting Divide ratio 1 n 1 n set value of the TBi register 0000h to FFFFh Count start condition Set the TBiS bit 1 to 1 start counting Count stop condition Set the TBiS bit to 0 stop counting Interrupt request generation timing Timer underflow Read from timer Count value can be read by reading the TBi register Write to timer i 0to5 NOTE When not counting Value written to the TBi register is written to both reload register and counter When counting Value written to the TBi register is written to only reload register
59. 1 n41 fordecrement n set value of the TAi register 0000h to FFFFh Count start condition Set the TAIS bit in the TABSR register to 1 start counting Count stop condition Set the TAIS bit to 0 stop counting Interrupt request generation timing Timer overflow or underflow pin function 1 I O port or count source input TAiOUT pin function 1 I O port pulse output Read from timer Count value can be read by reading the TAi register Write to timer When not counting Value written to the TAi register is written to both reload register and counter When counting Value written to the TAi register is written to only reload register transferred to counter when reloaded next Select function i 0to4 NOTE Free run count function Even when the timer overflows or underflows the reload register content is not reloaded to it Pulse output function 1 Whenever the timer underflows or underflows the output polarity of the TAiOUT pin is inverted When the TAIS bit is set to 0 stop counting the pin outputs low Output polarity control 1 While the output polarity of the TAiOUT pin is inverted the TAIS bit is set to 0 stop counting the pin outputs high 1 Only i O or 1 in the 48 pin version R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 111 of 331 M16C 6B Group 12 Timers Timer Ai Mode Register i 0 to 4 When Not Using Two Phas
60. 136 us TX mode RX mode Transition time for automatic transmission and reception System clock XIN Transmission 192 us Reception 184 us System clock XIN Figure 15 9 State Transitions RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 207 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 Baseband Associated Registers Baseband associated registers are shown below 15 2 1 Baseband Control Register This register controls the enabling or disabling of the baseband functions Setting the BBEN bit to 1 enables the baseband functions Access to the baseband associated registers when this bit is 1 Setting the BBEN bit to 0 initializes any processing during communication but the setting value of each register is retained Other processing such as the automatic ACK response and automatic reception switching functions are also cancelled Make sure to set the RFPWRON bit in the BBRFCON register to 0 RF power OFF before setting the BBEN bit to 0 Baseband Control Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset BBCON 0100h 00h Bit Symbol Bit Name Function BBEN Baseband enable bit Baseband functions enabled No register bits If necessary set to 0 Read as 0 Figure 15 10 Baseband Control Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 208 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 2 Transmit Receive Reset Register
61. 13FF9h and the start level with the address 13FFBh After starting boot mode user boot mode or standard serial I O mode is selected in accordance with the level of the selected port In addition if addresses 13FFOh to 13FF7h are set to UserBoot in ASCII code and address 13FF8h to 13FFBh are set to 00h user boot mode is selected In user boot mode the program of address 10000h the start address of program 2 is executed Figure 18 2 shows the User Boot Code Area Table 18 4 lists the Start Mode Table 18 5 lists the UserBoot in ASCII Code Table 18 6 lists the Addresses of Selectable Ports for Entry Program ROM 2 User Boot Start Address 13FFOh User Boot Code Area Boot Code 13FF8h Address 13FFAh Bit Port information for entry 13FFBh 13FFCh Start Level Select Reserved Space On Chip Debugger Monitor Area User Boot Code Area 13FFFh Figure 18 2 User Boot Code Area RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 253 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory Table 18 4 Start Mode When the Port Pj j is Selected for Entry 1 Port information for entry Address Bit Start level Port Pi j Start Mode 13FF7h 13FF8h to 13FFAh Select input level 13FFQh 13FFBh UserBoot in 0000h 00h 00h User boot mode ASCII code 2 Pi register 00h to 07h 00 H Standard serial I O mode address 3 value of j L User boot mod
62. 2 2 Figure 14 6 Registers ADCONO and ADCONI in Single Sweep Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 186 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 1 4 Repeat Sweep Mode 0 In repeat sweep mode 0 analog voltage applied to selected pins is repeatedly converted to a digital code Table 14 5 lists the Repeat Sweep Mode 0 Specifications Figure 14 7 shows Registers ADCONO and ADCONI in Repeat Sweep Mode 0 Table 14 5 Repeat Sweep Mode 0 Specifications Item Specification Function Bits SCAN1 and SCANO in the ADCON1 register select pins Analog voltage applied to the pins is repeatedly converted to a digital code A D conversion start The ADST bit in the ADCONO register is set to 1 A D conversion start condition A D conversion stop Set the ADST bit to 0 A D conversion stop condition Interrupt request No interrupt requests generated generation timing Analog input pin Select from ANO and AN1 2 pins ANO to AN3 4 pins ANO to AN5 6 pins and ANO to AN7 8 pin Reading of result of A D Read one of the registers ADO to AD7 that corresponds to the selected converter RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 187 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset Lr gon ll ADCONO 03D6h 00000XXXb ryt 1 I Analog input pin select
63. 2 value match An interrupt request is generated when frame transmission is completed However while automatic ACK receive mode is enabled if an ACK is requested for the transmit frame no interrupt request is generated when reception is completed an interrupt request is generated when ACK reception is completed or timed out Bank 0 reception complete An interrupt request is generated when the frame reception at bank 0 is completed However while automatic ACK response mode is enabled if an ACK is requested for the receive frame no interrupt request is generated when reception is completed an interrupt request is generated when ACK response is completed 45 2 Bank 1 reception complete An interrupt request is generated when the frame reception at bank 1 is completed However while automatic ACK response mode is enabled if an ACK is requested for the receive frame no interrupt request is generated when reception is completed and an interrupt request is generated when ACK response is completed 46 Address filter An interrupt request is generated when an address match is recognized 47 CCA complete An interrupt request is generated when a CCA sequence is completed or a CSMA CA sequence is completed 48 PLL lock detection An interrupt request is generated when a PLL lock or unlock is detected A lock or unlock can be switched by using the PLLINTSEL bit in the BBTXRXMODE4 register 49
64. 32 Lo E E Clo wl ao wo wo BR RIT RR RT BT OPA al a NI oO Mode setup method Value VCC VSS VSS gt VCC Package PVQN0064KA A 64VQFN Figure 18 14 Pin Connections in Standard Serial I O Mode 1 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 279 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 47 46 45 4 42 41 40 so se v Connect an oscillation circuit Mode setup method VCC VSS VSS gt VCC Package PVQN0048KB A 48VQEN Figure 18 15 Pin Connections in Standard Serial I O Mode 2 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 280 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 4 2 Example of Circuit Application in the Standard Serial I O Mode Figures 18 16 and 18 17 show an Example of Circuit Application in Standard Serial I O Mode 1 and Mode 2 respectively Refer to the user s manual of your serial programmer to handle pins controlled by the serial programmer Microcomputer SCLK input P6_5 CLK1 vC CA TXD output BUSY output RXD input Pe 7 TXD1 Pe A RTS1 P6 6 RXD1 Reset input dr User reset signal 1 Control pins and external circuitry will vary according to a programmer For more information refer to the programmer manual 2 In this example modes are switched between single chip mode and standard serial
65. 32 us a 144 us 128 us 32 us a lt lt i lt lt SS 1 gt CCA start ccastart CCA completion ccafin CCA check ccaresult CSMA check csmaresult CSMA interrupt csmafinint 320 us W UP i 2 144 usi Transmission m m 1 each CCA operation However if the m 1 value is greater than macMaxCSMABackoff when compared the operation is terminated i i 1 each CCA operation However the 1 value or macMaxBE whichever less is new n value when compared SENE Figure 15 8 CSMA CA Timing Chart Beacon Mode Example RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 206 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 15 State Transitions Figure 15 9 shows State Transitions RF and clock regulator OFF 125 kHz on chip oscillator mode System clock OCO 125 kHz on chip oscillator mode Low power consumption mode Low speed mode System clock XCIN High speed middle speed mode Low speed mode System clock XIN Low power consumption mode Transition time 1 ms NOTE 1 ms is required for starting up the RF and clock regulator each 1 ms is counted with the count source XIN Make sure the RF and clock regulator are started up at the same time After the clock regulator is started up the XIN clock must be connected to it RF and clock regulator ON IDLE mode Transition time 144 us System clock XIN Transition time
66. 50 pA XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied Hysteresis TAOIN TA1IN TA2IN to TA4IN 2 INTO INT1 CTSO to CTS2 SCLO to SCL2 SDAO to SDA2 TAOOUT TA10OUT TA2OUT to TA4OUT 2 KIO to 2 KI4 to KI7 RXDO to RXD2 Hysteresis RESET H input current P5 5 P5 7 P6 0 to P6 7 P7 2 P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 6 P8 7 P10 0to P10 7 2 XIN RESET CNVSS L input current P5 5 P5 7 P6 Oto P6 7 P7 0to P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 5to P8 7 P10 Oto P10 7 2 XIN RESET CNVSS Pull up resistance P5 5 P5 7 P6_0 to P6 7 P7 2 P7 3 P7 4to P7 7 2 P8 0 2 P8 1 2 P8 2 P8 3 P8 6 P8 7 P10_0 to P10 7 2 Feedback resistance XIN Feedback resistance XCIN NOTES RAM retention voltage At stop mode 1 Referenced to VCC 2 7 to 3 6 V VSS 0 V at 20 to 85 C 40 to 85 C f BCLK 16 MHz unless otherwise specified 2 64 version only R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 292 of 331 M16C 6B Group 19 Electrical Characteristics VCC VCCRF 3 3 V Table 19 9 Electrical Characteristics 2 1 Standard Min Typ Max Parameter Measuring Condition Power In single chip Flash memory f BCLK 4 MHz RF off supply m
67. CRC match Within 54 symbols after transmission is completed When all the above conditions are met a transmission complete interrupt is generated when ACK reception is completed Regardless of the address filter enabled or disabled receive RAM the BBRXFLEN register and the CRC bit in the BBTXRXSTO register are not updated After transmission is completed retransmit processing can be performed again from CSMA CA operation if ACK reception is not confirmed within 54 symbols After retransmit processing the same operation is performed again Repeat transmit processing for the number of times set in the RETRN bit in the register default 3 times If transmit processing is not required set 000b in the RETRN bit in the BBTXRXMODEI register To perform retransmit processing make sure to set the CSMATRNST bit in the BBCSMACONO register to 1 transmit processing after CSMA CA and the CSMAST bit in the BBCSMACONO register to 1 automatic CSMA CA start before starting transmit operation When ACK reception is completed or when ACK reception is not confirmed and no ACK is received after retransmit processing is performed for the set number of times time out a transmission complete interrupt request is generated The TRNRCVSQC bit in the BBTXRXSTO register can be used to confirm whether an ACK has been successful received or no ACK has been received even after repeating retransmission 54 symbols CSMA CA RX ACK
68. Clock Control Register 1 CM1 00100000b 0008h 0009h 000Ah Protect Register PRCR 00h 000Bh 000Ch Oscillation Stop Detection Register CM2 0X000010b 3 000Dh 000Eh 000Fh 0010h Program 2 Area Control Register PRG2C XXXXXXX0b 0011h 0012h Peripheral Clock Select Register PCLKR 00000011b 0013h 0014h 0015h Clock Prescaler Reset Flag CPSRF OXXXXXXXb 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh Processor Mode Register 2 PM2 XX000X01b 3 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002bEh 002Fh NOTES 1 The blank areas are reserved and cannot be accessed by users 2 Software reset watchdog timer reset and oscillation stop detection reset do not affect the following Bits 1 and PMOO in the PMO register 3 Oscillation stop detection reset do not affect bits CM20 CM21 and CM27 X Undefined R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 16 of 331 M16C 6B Group 4 Special Function Registers SFRs Table 4 2 SFR Information 2 1 Address Register After Reset Timer B5 Interrupt Control Register 5 XXXXX000b Ti
69. I O Pin Functions in UART Mode Table 13 8 lists the P6_4 Pin Functions in UART Mode Note that for a period from when the operating mode is selected to when transfer starts the TXDi pin outputs H If the N channel open drain output is selected this pin is in high impedance state Table 13 7 Pin Functions in UART Mode Pin Name Function Method of Selection Serial data output H output when performing reception only RXDi Serial data input Set the port direction bit corresponding to the RXDi pin to 0 can be used as an input port when performing transmission only CLKi Input output port The CKDIR bit in the UiMR register 0 Transfer clock input The CKDIR bit in the UiMR register 1 Set the port direction bit corresponding to the CLKi pin to 0 CTSi RTSi CTS input The CRD bit in the UiCO register 0 The CRS bit in the UiCO register 0 Set the port direction bit corresponding to the CTSi pin to 0 RTS input The CRD bit in the UiCO register 0 The CRS bit in the UiCO register 1 The CRD bit in the UiCO register 1 Input output port i 0to2 Table 13 8 P6 4Pin Functions in UART Mode Bit Set Value Pin Function U1CO0 Register UCON Register PD6 Register CRS RCSP CLKMD1 PD6_4 Input 0 Output 1 indicates either 0 or 1 NOTE 1 In addition to this set the CRD bit in the register to 0 CTSO RTSO enabled and the CRS bit
70. O mode 100b UART mode 7 bit transfer data or 101b UART mode 8 bit transfer data Set this bit to 0 when bits SMD2 to SMDO are set to 010b I C mode or 110b UART mode 9 bit transfer data Figure 13 9 U2C1 Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 134 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface UART Transmit Receive Control Register 2 57 D6 b5 04 b3 b1 bO Symbol Address After Reset UCON 0250h X0000000b Bit symbol Bit Name Function UARTO transmit interrupt 0 Transmit buffer empty TI 1 5 source select bit 1 Transmission completed TXEPT 1 UART1 transmit interrupt 0 Transmit buffer empty TI 1 source select bit 1 Transmission completed TXEPT 1 UARTO continuous receive 0 Continuous receive mode disabled SORAM mode enable bit 1 Continuous receive mode enabled U1RRM UART1 continuous receive 0 Continuous receive mode disabled mode enable bit 1 Continuous receive mode enabled Valid when CLKMD1 1 GLKMDo UARTICLK CLKS select er Glock output from CLK1 me 1 Clock output from CLKS1 0 CLK output is only from CLK1 CLKMD1 VARTI CLK CLKS select 1 Transfer clock output from multiple pin 1 p output function selected 0 CTS RTS shared pin 1 CTS RTS separated CTSO supplied from the P6 4 pin Separate UARTO CTS RTS bit When using multiple transfer clock output pins make sure the following conditions are met the C
71. P8 1 4 P8 2 8 3 P8 6 P8 7 VCC 2 2 P10 0 to P10 7 4 ANTSWCONT to 2 7 V lOL peak L peak output P5 5 P5 7 P6_0 to P6 7 VCC 2 7 current P7_0 to P7_3 P7_4 to P7_7 4 to 3 6 V P8 0 4 8 1 4 P8 2 P8 3 VCC 2 2 P8 5to P8 7 P10 Oto P10 7 4 to 2 7 V ANTSWCONT L average output P5 5 P5 7 P6 Oto P6 7 VCC 2 7 current P7_0 to P7_3 P7_4 to P7_7 4 to 3 6 V P8 0 4 P8 1 4 P8 2 P8 3 VCC 2 2 P8 5to P8 7 P10 Oto P10 7 0 to2 7 V ANTSWCONT Main clock input oscillation frequency Subclock oscillation frequency 125 kHz on chip oscillation frequency CPU operation clock VCC 2 2 to 2 7 V VCC 2 7 to 3 6 V NOTES 1 Referenced to VCC 2 2 to 3 6 V at 20 to 85 C 40 to 85 C unless otherwise specified 2 The Average Output Current is the mean value within 100 ms 3 The total lOL peak for the following ports must be 40 mA max VCC 2 7 to 3 6 V or 4 mA max VCC 2 2 to 2 7 V ports P7 Oto P7 3 P8 2 P8 3 P8 5to P8 7 and P10 The total IOL peak for the following ports must be 40 mA max VCC 2 7 to 3 6 V or 4 mA max VCC 2 2 to 2 7 V ports P5 5 P5 7 P6 P7 4 to P7 7 P8 0 and P8 1 The total IOH peak for the following ports must be 40 mA max VCC 2 7 to 3 6 V or 4 mA max VCC 2 2 to 2 7 V ports P7 2 P7 3 P8 2 P
72. PLL lock detection interrupt Usable Do not use Transmission overrun interrupt Usable Do not use Reception overrun 0 1 interrupt Usable Do not use IDLE interrupt Usable Do not use Clock regulator interrupt Usable Do not use Hardware reset Usable Watchdog timer reset Usable when count source protection mode is enabled CSPRO 1 Table 7 4 lists the Resets and Interrupts to Exit Wait Mode and Use Conditions If the microcomputer is to be moved out of wait mode by a peripheral function interrupt set up the following before executing the WAIT instruction 1 Set bits ILVL2 to ILVLO in the interrupt control register for peripheral function interrupts used to exit wait mode Bits ILVL2 to ILVLO in all other interrupt control registers for peripheral function interrupts not used to exit wait mode are set to 000b interrupt disabled 2 Setthe I flag to 1 3 Start operating the peripheral functions used to exit wait mode When the peripheral function interrupt is used an interrupt routine is performed after an interrupt request is generated and then the CPU clock is supplied again When the microcomputer exits wait mode by the peripheral function interrupt the CPU clock is the same clock as the CPU clock executing the WAIT instruction R01UH0197EJ0120 Rev 1 20 24 NC SAS Page 49 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 8 Stop Mode In stop mo
73. Pulse Signal Processing with Timers A2 A3 and A4 Table 12 4 Specifications in Event Counter Mode When Using Two Phase Pulse Signal Processing with Timers A2 A3 and A4 2 Item Specification Count source Two phase pulse signals input to or TAiOUT pin Count operation Increment or decrement can be selected by two phase pulse signal When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without reloading Divide ratio 1 FFFFh n 1 for increment 1 n 1 fordecrement n set value of the register 0000h to FFFFh Count start condition Set the TAIS bit in the TABSR register to 1 start counting Count stop condition Set the TAIS bit to 0 stop counting Interrupt request generation timing Timer overflow or underflow pin function Two phase pulse input TAiOUT pin function Two phase pulse input Read from timer Count value can be read by reading Timer A2 A3 or A4 register Write to timer When not counting Value written to the TAi register is written to both reload register and counter When counting Value written to the TAi register is written to only reload register transferred to counter when reloaded next Select function 1 2104 2 3 3 4 NOTES Normal processing operation Timer A
74. Read as undefined value 1 64 pin version only Figure 12 11 Registers TACS2 and TAPOFS RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 108 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 1 2 Timer Mode In timer mode the timer counts a count source generated internally refer to Table 12 2 Figure 12 12 shows the TAiMR i 0 to 4 Register in Timer Mode Table 12 2 Specifications in Timer Mode Item Specification Count source f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S fC32 Count operation Decrement When the timer underflows it reloads the reload register contents and continues counting Divide ratio 1 1 set value of TAi register 0000h to FFFFh Count start condition Set the TAIS bit in the TABSR register to 1 start counting Count stop condition Set the TAIS bit to 0 stop counting Interrupt request generation timing Timer underflow pin function 1 I O port or gate input TAiOUT pin function 1 I O port or pulse output Read from timer Count value can be read by reading the TAi register Write to timer When not counting Value written to the TAi register is written to both reload register and counter When counting Value written to the TAi register is written to only reload register transferred to counter when reloaded next Select function 1 i 0to4 NOTE 1 R01UH0197EJ0120 Rev 1
75. Receive Mode Register 3 BBTXRXMODE3 010Bh Receive Level Threshold Set Register BBLVLVTH 010Ch Transmit Receive Control Register BBTXRXCON 010Dh CSMA Control Register 0 BBCSMACONO 010Eh CCA Threshold Level Set Register BBCCAVTH 010Fh Transmit Receive Status Register 1 BBTXRXST1 0110h RF Control Register BBRFCON 0111h Transmit Receive Mode Register 4 BBTXRXMODE4 0112h CSMA Control Register 1 BBCSMACON1 0113h CSMA Control Register 2 BBCSMACON2 0114h 0115h PAN Identifier Register BBPANID 0116h 0117h Short Address Register BBSHORTAD 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh Expansion Address Register BBEXTENDADO BBEXTENDAD1 BBEXTENDAD2 BBEXTENDADS 0120h 0121h Timer Read Out Register 0 BBTIMEREADO 0122h 0123h Timer Read Out Register 1 BBTIMEREAD1 0124h 0125h Timer Compare 0 Register 0 BBTCOMPOREGO 0126h 0127h Timer Compare 0 Register 1 BBTCOMPOREG1 0128h 0129h Timer Compare 1 Register 0 BBTCOMP1REGO 012Ah 012Bh Timer Compare 1 Register 1 BBTCOMP1REG1 012Ch 012Dh Timer Compare 2 Register 0 BBTCOMP2REGO 012bEh 012Fh Timer Compare 2 Register 1 BBTCOMP2REG1 0130h 0131h Time Stamp Register 0 BBTSTAMPO 0132h 0133h Time Stamp Register 1 BBTSTAMP1 0134h Timer Control Regis
76. Register i 0 to 4 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset TAOMR to TA4MR 0336h to 033Ah 00h Bit Symbol Bit Name Function b1 bO 0 0 Timer mode 0 1 Event counter mode 1 1 TMODO Operation mode select bit One sh t timer ode 1 Pulse width modulation PWM mode Function varies with each operation mode Count source select bit Function varies with each operation mode 1 Valid when the bit 3 or the bit 7 in registers TACSO to TACS2 is set to 0 TCKO TCK1 enabled 2 Set only TAO and TA1 the 48 pin version Figure 12 6 Registers TAOMR to TA4MR RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 103 of 331 Jul 21 2011 M16C 6B Group 12 Timers Timer Ai Register i 0 to 4 b15 b8 07 29 br 20 Symbol Address After Reset TAO 0327h to 0326h Indeterminate TA1 0329h to 0328h Indeterminate TA2 032Bh to 032Ah Indeterminate 032Dh to 032Ch Indeterminate TA4 032Fh to 032Eh Indeterminate Mode Function Setting Range E ied the count source by n 1 where 0000h to FFFFh set value Timer mode Divide the count source by FFFFh n Event counter mode 1 where n set value when counting up 0000h to FFFFh or by 1 when counting down 9 One shot timer mode Divide the count source by n where n 0000h to FFFFh 24 WO set value and the counter stops Modify the pulse width as follows Pulse width PWM period 216 1 fj modulation mode PWM pulse wi
77. Serial I O Mode Multiple Transfer Clock Output Pin Function Not Selected Table 13 4 lists the P6_4 Pin Functions in Clock Synchronous Serial I O Mode Note that for a period from when UARTi operating mode is selected to when transfer starts the TXDi pin outputs H If the N channel open drain output is selected this pin is in high impedance state Table 13 3 Pin Functions in Clock Synchronous Serial I O Mode Multiple Transfer Clock Output Pin Function Not Selected Pin Name Function Serial data output Method of Selection Outputs dummy data when performing reception only RXDi Serial data input Set the port direction bit corresponding to the RXDi pin 0 can be used as an input port when performing transmission only CLKi Transfer clock output Transfer clock input The CKDIR bit in the UiMR register 0 The CKDIR bit in the UiMR register 1 Set the port direction bit corresponding to the CLKi pin 0 CTSi RTSi i Oto2 Table 13 4 Pin Function CTS input RTS output I O port The CRD bit in the UiCO register 0 The CRS bit in the UiCO register 0 Set the port direction bit corresponding to the CTSi pin 0 The CRD bit in the UiCO register 0 The CRS bit in the UiCO register 1 The CRD bit in the UiCO register 1 P6_4 Pin Functions in Clock Synchronous Serial I O Mode Bit Set Value U1CO Register UCON Register PD
78. Then when the interrupt request is accepted the IR bit is cleared to 0 interrupt not requested The IR bit can be cleared to 0 in a program Do not write a to this bit 9 5 3 Bits ILVL2 to ILVLO and IPL Interrupt priority levels can be set using bits ILVL2 to ILVLO Table 9 4 lists the Settings of Interrupt Priority Levels and Table 9 5 lists the Interrupt Priority Levels Enabled by IPL The followings are conditions under which an interrupt is accepted eI flag 1 e IR bit 1 Interrupt priority level gt IPL The I flag IR bit bits ILVL2 to ILVLO and IPL are independent each other In no case do they affect one another Table 9 4 Settings of Interrupt Priority Levels Table 9 5 Interrupt Priority Levels Enabled by IPL Bits ILVL2 to ILVLO Interrupt Priority Level Priority Order Enabled Interrupt Priority Levels Level 0 interrupt disabled Interrupt levels 1 and above are enabled Level 1 Interrupt levels 2 and above are enabled Level 2 Interrupt levels 3 and above are enabled Level 3 Interrupt levels 4 and above are enabled Level 4 Interrupt levels 5 and above are enabled Level 5 Interrupt levels 6 and above are enabled Level 6 Interrupt levels 7 and above are enabled Level 7 All maskable interrupts are disabled RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 70 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 5 4 Interrupt Sequence An interrupt sequence wha
79. Therefore we recommend using the watchdog timer to improve reliability of a system The watchdog timer contains a 15 bit counter and count source protection mode enabled disabled is set here Table 10 1 lists the Watchdog Timer Specification Refer to 5 3 Watchdog Timer Reset for details of watchdog timer reset Figure 10 1 shows the Watchdog Timer Block Diagram Figure 10 2 shows the Registers WDTR WDTS and WDC Figure 10 3 shows the CSPR Register and OFS1 Address Table 10 1 Watchdog Timer Specification When count source protection mode is When count source protection mode is disabled enabled Count source CPU clock 125 kHz on chip oscillator clock Count operation Decrement Count start condition Either of the followings can be selected Count automatically starts after reset Count starts by writing to the WDTS register Count stop condition Stop mode wait mode hold state None Watchdog timer Reset reset condition Write 00h and then FFh to the register Underflow Operation when the Watchdog timer interrupt or watchdog Watchdog timer reset timer underflows timer reset Select function Prescaler divide ratio Set the WDC7 bit in the WDC register to select this mode Count source protection mode Set the CSPROINI bit flash memory in the OFS1 address to select whether this mode is enabled or disabled after reset If this mode is set to disabled after reset set the CSPRO bit program in t
80. Transmit Receive Control Register 0 i 0 to 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset UOCO U1C0 U2CO 024Ch 025Ch 026Ch 00001000b Bit Symbol Bit Name Function b1 b0 0 0 f1SIO or f2SIO is selected 9 0 1 f8SIO is selected 1 0 f32SIO is selected 1 1 Do not set to this value Valid when CRD 0 0 CTS function selected 1 RTS function selected 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed 0 CTS RTS function enabled 1 CTS RTS function disabled 0 P6 4 and P7 can be used as I O ports 0 Pins TXDi SDAi and SCLi are CMOS output 1 Pins TXDi SDAi and SCLi are N channel open drain output 0 Transmit data is output at the falling edge of transfer clock and receive data is input at the rising edge CKPOL EUIS polarity select bit 1 Transmit data is output at the rising edge of transfer clock and receive data is input at the falling edge 0 LSB first 3 UFORM Transfer format select bit 1 MSB first RW Set the corresponding port direction bit for each CTSi pin to 0 input mode TXD2 SDA2 and SCL2 are N channel open drain output Cannot be set to the CMOS output No NCH bit in the U2CO register is assigned If necessary set to 0 The UFORM bit is enabled when bits SMD2 to SMDO in the UiMR register are set to 001b clock synchronous serial mode or 101b UART mode 8 bit transfer data Se
81. V to 2 V Power supply rising gradient VCC Voltage range 2 0 V to 3 6 V 3 6V SVCC Power supply rising gradient VCC Figure 20 1 Timing of SVCC 20 2 2 CNVSS Connect to VSS via resistor The internal pull up of the CNVSS pin is on immediately after hardware reset 1 is released in single chip mode Therefore the CNVSS pin level becomes H for two cycles of fOCO S maximum RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 306 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 3 Baseband Functions RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 307 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 4 Power Control When exiting stop mode by hardware reset 1 set the RESET pin to L until a main clock oscillation is stabilized Set the MRO bit in the TAiMR register i 0 to 4 to 0 pulse is not output to use the timer A to exit stop mode After the WAIT instruction insert at least four NOP instructions When entering wait mode the instruction queue reads ahead the instructions following WAIT and depending on timing some of these may execute before the microcomputer enters wait mode Program example when entering wait mode is shown below Program Example FSET I A WAIT Enter wait mode NOP More than four NOP instructions NOP NOP NOP e When entering stop mode insert a JMP B instruction immediately after executing an instruction which sets the CM10 bit in the re
82. XOUT if the oscillator manufacturer recommends placing the resistor externally Figure 7 6 Examples of Main Clock Connection Circuit RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 42 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 1 2 Subclock The subclock is generated by the subclock oscillation circuit This clock is used as the clock source for the CPU clock as well as the timer A and timer B count sources In addition an fC clock with the same frequency as that of the subclock can be output from the CLKOUT pin The subclock oscillation circuit is configured by connecting a crystal resonator between pins XCIN and XCOUT The subclock oscillation circuit contains a feedback resistor which is disconnected from the oscillation circuit during stop mode in order to reduce the amount of power consumed in the chip The subclock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin Figure 7 7 shows the Examples of Subclock Connection Circuit After reset the subclock is turned off At this time the feedback resistor is disconnected from the oscillation circuit To use the subclock for the CPU clock set the CM07 bit in the register to 1 subclock after the subclock becomes oscillating stably During stop mode all clocks including the subclock are turned off Refer to 7 4 Power Control for details Microcomputer Microcomputer Built in feedback resistor Built in
83. and Destination Addresses sss eene enne enne nnne nne 93 11 1 2 Effect of Software Walt ose eee tn re eter d tee cde iere nts 93 11 2 DMA Transfer Cycles eene miu e ORE eret 95 11 3 Enabled eint ated tees tesa cob e AN te ke EXE ERR 96 11 4 DMA Request eet eed HE RERO eam ie eee 96 11 5 Channel Priority and DMA Transfer enne enne nenne 97 DEIN ICE 98 12 1 SPAMS TAS MI Em 101 12 11 TumercA T O Function Ae eet Aes 102 12 1 2 Timer essei ener ente dele tee eee e ir bep e IER REUS QR 109 12 1 3 Bvent Counter Mode 5i Ub a Mete ee ete coe eats 111 12 1 4 One Shot Timer Mode 2 115 12 1 5 Pulse Width Modulation PWM Mode Only i 0 or 1 in the 48 Pin Version 117 12 2 Timer Bz oseSwtutom hens ET ENTERS 120 12 221 Pee ModE ui Idas einen eee 124 12 2 2 Event Counter Mode eie nete a te eco e dd e e ets 125 13 2 Serial oir eoe dd dece etd e eite esee Hd PUE had 126 13 1 DAR TY 5 0419 2 mt tents t titt Me RE En 126 13 1 1 Clock Synchronous Serial I O Mode essere enne entente 140 13 1 2 Clock Asynchronous Serial I O UART Mode eese nennen 148 13 1 3 Special Mode 1 I2 mode se TEES REED URBIS
84. are non maskable interrupts 9 3 1 1 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low For details about the NMI interrupt refer to 9 7 NMI Interrupt 9 3 1 2 DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development tools 9 3 1 3 Watchdog Timer Interrupt Generated by the watchdog timer Once a watchdog timer interrupt is generated be sure to initialize the watchdog timer For details about the watchdog timer refer to 10 Watchdog Timer 9 3 1 4 Oscillation Stop and Re Oscillation Detection Interrupt Generated by the oscillation stop and re oscillation detection function For details about the oscillation stop and re oscillation detection function refer to 7 Clock Generation Circuit 9 3 1 5 Single Step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development tools 9 3 1 6 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by registers RMADO to RMAD3 that correspond to one of the AIERO or AIERI bit in the ATER register or the AIER20 or AIER21 bit in the AIER2 register which is 1 address match interrupt enabled For details about the address match interrupt refer to 9 9 Address Match Interrupt 9 3 2 Peripheral Function Interrupts The peripheral function interrupt occurs
85. before A D conversion starts For multiple pins or A D conversion repeat mode for each pin between execution dummy time is inserted between A D conversion execution time and the next A D conversion execution time The ADST bit is set to 0 during the end dummy time and the last A D conversion result is set to the ADi register in one shot mode and single sweep mode While in one shot mode Start dummy time A D conversion execution time end dummy time When two pins are selected while in single sweep mode Start dummy time A D conversion execution time between execution dummy time A D conversion execution time end dummy time Start dummy time Refer to Table 14 7 Start Dummy Time A D conversion execution time 40 cycles per pin Between execution dummy time 1 AD cycle End dummy time 2 to 3 cycles of fAD Table 14 7 Start Dummy Time fAD 1 to 2 cycles of fAD fAD divided by 2 2 to 3 cycles of fAD fAD divided by 3 3 to 4 cycles of fAD fAD divided by 4 3 to 4 cycles of fAD fAD divided by 6 4 to 5 cycles of fAD fAD divided by 12 7 to 8 cycles of fAD 14 3 Current Consumption Reducing Function When not using the A D converter power consumption can be reduced by setting the ADSTBY bit in the ADCONI register to 0 A D operation stopped standby to shut off any analog circuit current flow To use the A D converter set the ADSTBY bit to 1 A D operation enabled after operating longer than one cycle
86. bi b0 Symbol Address After Reset fafa FFFFFh FFh 1 1 1 1 Bit Symbol Funetion 0 Watchdog timer starts automatically Watchdog timer start select after reset bit 9 1 Watchdog timer is in a stopped state after reset 0 ROM code protection enabled ROMCP1 ROM code protection bit 1 ROM code protection disabled RW 0 Count source protection mode enabled After reset count source after reset protection mode select bit 9 1 Count source protection mode disabled after reset p E 1 1 1 1 1 1 1 1 1 1 1 1 L 1 1 1 L 1 1 1 1 1 1 1 L 1 1 1 1 1 L CSPROINI 1 The OFS1 address exists in flash memory Set the values when writing a program 2 The OFS1 address is set to FFh when the block including the OFS1 address is erased 3 Set the WDTON bit to 0 watchdog timer starts automatically after reset when setting the CSPROINI bit to 0 count source protection mode enabled after reset Figure 18 3 OFS1 Address Address OFFFDFh to OFFFDCh OFFFE3h to OFFFEOh OFFFE7h to OFFFE4h BRK instruction vector OFFFEBh to OFFFE8h OFFFEFh to OFFFECh OFFFF3h to OFFFFOh OFFFF7h to OFFFF4h OFFFFBh to OFFFF8h OFFFFFh to OFFFFCh T Figure 18 4 Address for ID Code Stored R01UH0197EJ0120 Rev 1 20 ztENESAS Page 257 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 CPU Rewrite Mode In CPU rewrite mode the flash memory can be rewritten when the CPU executes softw
87. bi bd Symbol Address After Reset 1010 FMR2 0222h XXXX0000b i Bit Symbol Bit Name Function 1 61 60 Reserved bits Set to 0 Slow read mode enable 0 Disabled mnes bit 1 Enabled Low current consumption 0 Disabled Mies read mode enable bit 1 Enabled No register bits If necessary set to 0 Read as undefined value FMR22 Slow read mode enable bit b2 This bit enables mode which reduces the amount of current consumption when reading the flash memory When rewriting the flash memory CPU rewrite mode set the FMR22 bit to 0 slow read mode disabled To set the FMR22 bit to 1 write 0 and then in succession Make sure no interrupts or DMA transfers occur before writing 1 and after writing 0 Set the FMR23 bit to 1 low current consumption read mode enabled after the FMR22 bit is set to 1 slow read mode enabled Also set the FMR22 bit to 0 slow read mode disabled after the FMR23 bit is set to 0 slow read mode disabled Do not change bits FMR22 and FMR23 at the same time FMR23 Low current consumption read mode enable bit b3 When this bit is set the slow read mode reduces the amount of current consumption when reading the flash memory When rewriting the flash memory CPU rewrite mode set the FMR23 bit to 0 low current consumption read mode disabled Low current consumption read mode can be used when the CMO7 bit in the register is 1 sub clock used as CPU clock When t
88. bit Invalid in repeat sweep mode 0 b4 b3 1 1 Repeat sweep mode 0 or repeat sweep mode 1 A D operation mode select bit 0 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset V ojoj ADCON1 03D7h 0000X000b Bit Symbol Bit Name Function b1 bO 0 0 ANO to AN1 2 pins 2 A D sweep pin select bit 0 1 ANO to AN3 4 pins 1 0 ANO to AN5 6 pins 1 1 ANO to AN7 8 pins I 1 1 When repeat sweep mode 0 is selected 1 1 1 1 I A D operation mode select Set to 0 when repeat sweep mode 0 is bit 1 selected No register bit If necessary set to 0 Read as undefined value Frequency select bit 1 RW NOTES 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the ADSTBY bit is changed from 0 A D operation stopped to 1 A D operation enabled wait for 1 9AD cycle or more before starting A D conversion p 2 2 22222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Figure 14 7 Registers ADCONO and ADCON t in Repeat Sweep Mode 0 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 188 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 1 5 Repeat Sweep Mode 1 In repeat sweep mode 1 analog voltage selectively applied to all pins is rep
89. bit in the BBCSMACONI register is set to 000b processing starts from transmission without performing CSMA CA operation When the automation ACK reception function is enabled if ACK reception is not confirmed within 54 symbols after transmission is completed retransmit processing is performed from transmit operation for the number of times set in the RETRN bit in the BBBBTXRXMODEI register When the bit in the BBTXRXMODEI register is set to 0006 retransmit processing is not performed Battery life BE lesser of Backoff periods NB 0 extension 2 macMinBE BE macMinBE BE value Delays After automatic macMin d CSMA CA Oor1 ransmit bit 17 0to3 0107 BE macMinBE 01015 0 to 31 0 to 63 Delay for next backoff 0 to 127 period boundary Delay for backoff Transmit processing periods Delay for backoff v periods Perform CCA Perform CCA on backoff period boundary N NB 1 BE min BE 1 macMaxBE NB macMaxCSMABack X offs NB gt macMaxCSMABack Y offs Y NOTE 1 CCA is not performed when BE 000b Figure 15 7 CSMA CA Flowchart RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 205 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality Automatic CSMAEN 320 us 320us 320us _ 320 ps Backoff period NB BE 2 Default i i i i W UP CCA f F W UP W UP CCA 1 1 144 us 1128 us 32 us a H 144 us 128 us
90. by 2 A D Register i i 0 to 7 Symbol Address After Reset a m ADO 03C1h to 03COh 000000XXb XXXXXXXXb AD1 03C3h to 03C2h 000000XXb XXXXXXXXb AD2 03C5h to 03C4h 000000XXb XXXXXXXXb AD3 03C7h to 03C6h 000000XXb XXXXXXXXb AD4 03C9h to 03C8h 000000XXb XXXXXXXXb AD5 O3CBh to 03CAh 000000XXb XXXXXXXXb AD6 03CDh to 03CCh 000000XXb XXXXXXXXb AD7 O3CFh to O3CEh 000000XXb XXXXXXXXb Function Eight low order bits of A D conversion result Reserved bit Set to 0 1 Use the MOV instruction to write to this register Figure 14 3 Registers ADCON2 and ADO to AD7 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 180 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 4 Mode Description 14 1 1 One Shot Mode In one shot mode analog voltage applied to a selected pin is converted to a digital code once Table 14 2 lists the One Shot Mode Specifications Figure 14 4 shows the Registers ADCONO and ADCONI in One Shot Mode Table 14 2 One Shot Mode Specifications Item Specification Function Bits CH2 to CHO in the ADCONO register select a pin Analog voltage applied to the pin is converted to a digital code once A D conversion start condition When the TRG bit in the ADCONO register is O software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts A D conversion stop condition Completion of A D conversion The ADST bit is cleared to 0 A D conve
91. cause more increase in power consumption to AN4 to AN7 than to other analog input pins ANO to AN3 since to AN7 are used with KIO to When A D conversion is stopped in one shot mode or single sweep mode the ADST bit in the ADCONO register becomes 0 A D conversion stop Therefore set the ADST bit to 1 A D conversion start by a program if there is a possibility that a trigger is input subsequently Connect the VREF pin to VCC pin Because the VREF pin is connected to VCC pin inside current flows if potential difference occurs between the pins RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 325 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 10 Notes on Flash Memory 20 10 1 Functions to Prevent Flash Memory from Being Rewritten Addresses OFFFDFh OFFFE3h OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh store ID codes When the wrong data is written to these addresses the flash memory cannot be read or written to in standard serial I O mode OFFFFFh is OFS1 address When the wrong data is written to this address the flash memory cannot be read or written to in parallel I O mode These addresses correspond to the vector address H in fixed vector 20 10 2 Reading Data Flash When 2 2 V VCC lt 2 7 V one wait must be inserted to execute the program on the data flash and read the data Set the PM17 in the PM1 register or FMR17 bit in the FMRI register to insert one wait 20 10 3 CPU Rewrite Mode 20 10 3
92. data flash Data flash Lock bit program time VCC 3 3 V at Topr 25 C Other than data flash Data flash Block erase time VCC 3 3 V at Topr 25 C 4 Kbyte block 16 Kbyte block 64 Kbyte block Flash memory circuit stabilization wait time Data hold time 3 NOTES 1 2 Definition of program and erase endurance The program and erase endurance refers to the number of per block erasures Referenced to VCC 2 7 to 3 6 V at Topr 0 to 60 C unless otherwise specified If the program and erase endurance is n n 100 each block can be erased n times For example if a 4 Kbyte block is erased after writing two word data 1 024 times each to a different address this counts as one program and erase endurance Data cannot be written to the same address more than once without erasing the block Rewrite prohibited 3 20 to 85 C 40 to 85 C Table 19 6 Flash Memory Program Erase Voltage and Read Operation Voltage Characteristics at Topr 0 to 60 C Flash Program Erase Voltage Flash Read Operation Voltage VCC 2 7 to 3 6 V VCC 2 2 to 3 6 V Table 19 7 Power Supply Circuit Timing Characteristics Parameter Time for internal power supply stabilization during powering on VCC 2 2 to 3 6 V Stop release time Low power consumption mode wait mode release time Standard Measuring Condition Typ
93. delay for the CCA complete interrupt Use the CCA bit in the BBTXRXSTO register to check the CCA result NOTE 15 3 4 1 2 7 8 1 Steps 2 and 3 can be interchanged CSMA CA Procedure Example Set 1 baseband functions enabled in the BBEN bit in the BBCON register Set Olh 1 ms in the BBIDLEWAIT register Set 1 IDLE interrupt in the BANKOINTSEL bit in the BBTXRXMODEF4 register Set 1 RF power ON in the RFPWRON bit in the BBRFCON register and 1 XIN power ON in the XINPWRON bit Use registers BBPLLDIVL and BBPLLDIVH for channel setting Set the BEACON bit in the BBTXRXMODEO register Set the initial value in bits BOFFPRODO to BOFFPROD6 in the BBBOFFPROD register Set 1 backoff period automatic random enabled in the BOFFPRODEN bit in the BBBOFFPROD register After the IDLE interrupt is generated after the wait time set in the BBIDLEWAIT register has elapsed from step 2 Set 1 clock regulator in the XINREGSEL bit in the BBRFCON register Set the setting value in the BBRFINI register Set 1 automatic CSMA CA start in the CSMAST bit in the BBCSMACONO register At the same time if transmit processing is to be proceeded after CSMA CA is completed set 1 transmit processing after CSMA CA in the CSMATRNST bit in the BBCSMACONDO register Allow a delay for the CSMA CA complete interrupt Confirm the CSMA CA result by using the CSMACA bit in the BBTXRXSTO register NOTE 1 Steps 2 to 5 c
94. executing one of these commands Figure 18 13 Full Status Check and Handling Procedure for Each Error RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 276 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 4 Standard Serial I O Mode In standard serial I O mode the serial programmer supporting the M16C 6B Group can be used to rewrite the program ROM 1 program ROM 2 and data flash in the microcomputer mounted on a board For more information about the serial programmer contact your serial programmer manufacturer Refer to the user s manual included with your serial programmer for instructions Table 18 13 lists Pin Functions Flash Memory Standard Serial I O Mode Figures 18 14 and 18 15 show Pin Connections in Standard Serial I O Mode 18 4 4 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer match those written in the flash memory Refer to 18 2 Functions to Prevent Flash Memory from Rewriting R01UH0197EJ0120 Rev 1 20 ztENESAS Page 277 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory Table 18 13 Pin Functions Flash Memory Standard Serial I O Mode VCC VCC1 VSS2 Power input Description Apply the flash program and erase voltage to the VCC pin and 0 V to pins VSS1 VSS2 AVCC 1 AVSS 1 AD power input Connect the AVCC pin to VCC Connect the AVSS pin to VSS CNVSS CNVSS Connect to VCC RESET Res
95. function NCH Select TXDi pin output mode 2 CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first UiC1 TE Set this bit to 1 to enable transmission reception TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag UiIRS 1 Select the source of UARTi transmit interrupt UiRRM 1 Set this bit to 1 to use continuous reception mode UiLCH Set this bit to 1 to use inverted data logic UiERE Set to 0 UiSMR 0 to 7 Set to 0 UiSMR2 007 Set to 0 UiSMR3 002 Set to 0 NODC Select clock output mode 4 to 7 Set to 0 UiSMR4 0to7 Set to 0 UCON UOIRS U1IRS Select the source of UARTO UART 1 transmit interrupt UORRM U1RRM Set this bit to 1 to use continuous reception mode CLKMDO Select the transfer clock output pin when CLKMD1 1 CLKMD1 Set this bit to 1 to output UART1 transfer clock from two pins RCSP Set this bit to 1 to accept as input the CTSO signal of UARTO from the P6 4 pin 7 Set to 0 i Oto2 NOTES 1 Set bits 4 and 5 in registers UOC1 and U1C1 to 0 Bits UOIRS U1IRS UORRM and U1RRM are in the UCON register 2 The TXD2 pin is N channel open drain output Set the NCH bit in the U2CO register to 0 3 Set bits not listed above to 0 when writing to the registers in clock synchronous serial I O mode R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 141 of 331 M16C 6B Group 13 Serial Interface Table 13 3 lists the I O Pin Functions in Clock Synchronous
96. had entered stop mode When the subclock is the CPU clock before entering stop mode subclock When the main clock is the CPU clock source before entering stop mode main clock divided by 8 When the 125 kHz on chip oscillator clock is the CPU clock source before entering stop mode 125 kHz on chip oscillator clock divided by 8 R01UHO197EJ0120 Rev 1 20 24 NC SAS Page 51 of 331 Jul 21 2011 M16C 6B Group Figure 7 9 shows the Power Control Transition Power Control Mode State Transition Normal Operation Mode 7 Clock Generation Circuit 125 kHz on chip oscillator mode CM07 0 CM21 1 CM14 0 CM05 0 125 kHz on chip oscillator low power consumption mode CMO5 1 07 0 CM14 0 21 1 High speed mode medium speed mode CMO05 0 CM07 0 21 0 Interrupt WAIT instruction Wait mode CPU operation stopped CM04 CM05 CM06 CM07 bits in the CMO register CM14 CM16 CM17 bits in the CM1 register CM21 bits in the CM2 register Figure 7 9 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 Power Control Transition ztENESAS Low speed mode CM04 1 5 0 CMO7 1 Low power consumption mode CM04 1 CM05 1 CMO7 1 Interrupt Stop mode All the oscillations stopped Page 52 of 331 M16C 6B Group 7 Clock Generation Circuit 7 4 4 Power Control of Flash Memory 7 4 4 1 Flash Memory Control Register 0 FMRO Flash Memory Control R
97. in the UiC1 Register 1 Reverse Transfer Clock TXDi H Reverse This applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge of the transfer clock and the UFORM bit in the UiCO register 0 LSB first i Oto2 Figure 13 18 Serial Data Logic Switching 13 1 1 6 Transfer Clock Output from Multiple Pins UART1 Use bits CLKMD1 to CLKMDO in register to select one of the two transfer clock output pins refer to Figure 13 19 This function can be used when the selected transfer clock for UARTI is an internal clock Microcomputer TXD1 P6_7 CLKS1 P6_4 CLK1 P6 5 Transfer enabled when the CLKMDO Transfer enabled when the CLKMDO bit in the UCON register 0 bit in the UCON register 1 The above applies to the case where the CKDIR bit in the U1MR register 0 internal clock and the CLKMD1 bit in the register 1 transfer clock output from multiple pins Figure 13 19 Transfer Clock Output from Multiple Pins RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 146 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 1 7 CTS RTS Function The CTS function is used to start transmit and receive operation when L is applied to the CTSi RTSi i 0 to 2 pin Transmit and receive operation begins when the CTSi RTSi pin is held L If the L signal is switched to H during a t
98. input output mode by controlling the CNVSS input with a switch 3 If in standard serial input output mode 1 there is a possibility that the user reset signal will go low during serial input output mode break the connection between the user reset signal and RESET pin by using for example a jumper switch Figure 18 16 Example of Circuit Application in Standard Serial I O Mode 1 RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 281 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory Microcomputer P6_5 CLK1 TXD output P6_7 TXD1 Monitor output P6_4 RTS1 RXD input P6_6 RXD1 Reset input User reset signal 1 In this example modes are switched between single chip mode and standard serial input output mode by controlling the CNVSS input with a switch Figure 18 17 Example of Circuit Application in Standard Serial I O Mode 2 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 282 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 5 Parallel Mode In parallel I O mode the program ROM and program ROM 2 can be rewritten by a parallel programmer supporting the M16C 6B Group Contact your parallel programmer manufacturer for more information on the parallel programmer Refer to the user s manual included with your parallel programmer for instructions 18 5 1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read and rewritten Refer to 18 2 Functions to Prevent Flash Memo
99. interrupts Reset NMI watchdog timer oscillation stop restart detect 18 6 4 User Boot Mode 18 6 4 1 Location of User Boot Mode Program Allocate a program which is invoked and executed in user boot mode only in program ROM 2 do not execute the program which is allocated in data flash or program ROM 1 in user boot mode 18 6 4 2 Entering User Boot Mode After Standard Serial I O Mode To use user boot mode after standard serial I O mode turn off the power when exiting standard serial I O mode and then turn on the power again cold start The MCU enters user boot mode under the right conditions R01UHO197EJ0120 Rev 1 20 ztENESAS Page 285 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics 19 Electrical Characteristics 19 1 Table 19 1 Electrical Characteristics Absolute Maximum Ratings Parameter Digital supply voltage Condition Rated Value 0 3 to 3 8 Analog supply voltage 0 3 to 3 8 Input voltage RESET CNVSS P5 5 P5 7 P6 Oto P6 7 P7 2 P7 3 P7 4to P7 7011 P8 0 1 P8_1 1 P8 2 P8 3 P8 6 P8 7 P10 0 to P10 7 1 0 3 to 0 3 7 0 7 1 P8_5 0 3 to 0 3 Output voltage P5_5 P5_7 P6_0 to P6_7 P7 2 P7 3 P7 4to P7_7 1 8 0 1 P8_1 1 P8 2 P8 3 P8 6 P8 7 P10_0 to P10 7 1 0 3 to 0 3 ANTSWCONT P7 0 P7 1 P8 5 0 3 to
100. is generated 20 5 2 SP Setting Set any value in the SP USP ISP before accepting an interrupt The SP USP ISP is cleared to 0000h after reset Therefore if an interrupt is accepted before setting any value in the SP USP ISP the program may go out of control Especially when using the NMI interrupt set a value in the ISP at the beginning of the program Only for the first instruction after reset all interrupts including the NMI interrupt are disabled 20 5 3 NMI Interrupt The NMI interrupt cannot be disabled If this interrupt is not used set the PM24 bit in the PM2 register to 0 port P8 5 function Stop mode cannot be entered into while input the NMI pin 15 L because the CM10 bit in the register is fixed to 0 Do not enter wait mode while input on the NMI pin is L because the CPU clock remains active even though the CPU stops and therefore the current consumption in the chip does not drop In this case normal condition is restored by a subsequent interrupt generated Set the L and H level durations of the input signal to the NMI pin to 2 CPU clock cycles 300 ns or more RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 310 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 5 4 Changing an Interrupt Generate Factor If the interrupt generate factor is changed the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 interrupt re
101. is retained until the next frame reception starts However the value is updated when an address match is recognized while the address filter is enabled If the receive frame length is less than 04h the frame reception is not accepted In this case the receive frame length value is not updated Also no reception complete interrupt is generated Receive Frame Length Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBRXFLEN 0104h 00h iiia icc RXFLEN Receive frame length Indicates the frame length value for 9 reception No register bit If necessary set to 0 Read as 0 07 1 This bit corresponds to the receive RAM bank Figure 15 14 Receive Frame Length Register Configuration 15 2 6 Receive Data Counter Register This register indicates the receive data counter value for reception It can be used to confirm what bytes of data has been received The value is cleared to 00h when frame reception stops Receive Data Counter Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBRXCOUNT 0105h 00h Bit Symbol Bit Name Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ji I 1 bet Indicates the data counter value for reception Figure 15 15 Receive Data Counter Register Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 212 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 7 RSSI CCA Result Register This register stores the result data of C
102. manual Overflow INTO instruction FFFEOh to FFFE3h BRK instruction 2 FFFE4h to FFFE7h Address match FFFE8h to FFFEBh 9 9 Address Match Interrupt Interrupt Source Reference Single step 1 FFFECh to FFFEFh Watchdog timer FFFFOh to FFFF3h 10 Watchdog Timer oscillation stop and 7 Clock Generation Circuit re oscillation detection DBC 1 FFFF4h to FFFF7h NMI FFFF8h to FFFFBh 9 7 NMI Interrupt Reset FFFFCh to FFFFFh 5 Reset NOTES 1 Do not normally use this interrupt because it is provided exclusively for use by development tools 2 If the contents of address FFFE7h is FFh program execution starts from the address shown by the vector in the relocatable vector table R01UH0197EJ0120 Rev 1 20 ztENESAS Page 65 of 331 Jul 21 2011 M16C 6B Group 9 4 2 Relocatable Vector Tables 9 Interrupt The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area Tables 9 2 and 9 3 list the Relocatable Vector Tables Setting an even address in the INTB register results in the interrupt sequence being executed faster than setting an odd address Table 9 2 Interrupt Source INT instruction interrupt Relocatable Vector Table 1 Vector Address 1 Address L to Address H 0 to 3 0000h to 0003h to 252 to 255 00FCh to OOFFh Software Interrupt Number BRK instruction 4 0 to 3 0000h
103. of 3 left in the CRCD register to perform the modulo 2 division 0000 1010 0100 0001b 0A41h the remainder with reversed bit position can be read from the CRCD register Figure 16 3 Example of Using the CRC Operation R01UH0197EJ0120 Rev 1 20 ztENESAS Page 241 of 331 Jul 21 2011 M16C 6B Group 17 Programmable I O Ports 17 Programmable I O Ports 33 19 in the 48 pin version programmable input output ports I O ports are available The direction registers determine individual port status input or output The pull up control registers determine whether the pots divided into groups of four ports are pulled up or not P8 5 is an input port and no pull up is allowed Port P8 5 shares the pin with NML so that the NMI input level can be read from the P8 5 bit in the P8 register Figures 17 1 to 17 3 show the I O ports Figure 17 4 shows the I O Pins Each pin functions as an I O port or a peripheral function input output To set peripheral functions refer to the description for individual functions If any pin is used as a peripheral function input set the direction bit of the corresponding pin to 0 input mode Any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set 17 1 Port Pi Direction Register PDi Register i 5 to 8 10 Figure 17 5 shows the Pi Direction Registers This register selects whether the I O port is to be used for input or
104. of the ADCON2 Register 0 A D operation stopped standby it 2 AD stangoy bit 1 A D operation enabled fee ee ee ee ee ee ee eee ee Reserved bits Set to 0 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the ADSTBY bit is changed from 0 A D operation stopped to 1 A D operation enabled wait for 1 AD cycle or more before starting A D conversion Figure 14 2 Registers ADCONO and ADCON1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 179 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 2 b7 b6 b5 b4 55 b2 bi X Symbol Address After Reset ADCON2 03D4h 0000X00Xb Bit Symbol Bit Name Function No register bit If necessary set to 0 Read as undefined value Reserved bits Set to 0 No register bit If necessary set to 0 Read as undefined value 0 Selects fAD fAD divided by 2 or fAD Frequency select bit 2 2 divided by 4 1 Selects fAD divided by 3 fAD divided by 6 Lll A Reserved bits Set to 0 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 AD frequency is selected by a combination of the CKSO bit in the ADCONO register the CKS1 bit in the ADCON1 register and the CKS2 bit in the ADCON2 register o 0o mp 3x3 by 4 a TAD divided
105. or below 4 td P R x 20 or above 1 fOCO S Figure 5 1 Example Reset Circuit RO1UH0197EJ0120 Rev 1 20 RENESAS Page 30 of 331 Jul 21 2011 M16C 6B Group 5 Reset Table 5 1 Pin Status When RESET Pin Level is L Pin Status 64 Pin Version 48 Pin Version 5 5 Input port Input port P5 7 Input port Input port P6 Input port Input port P7 0to P7 3 Input port Input port P7 4to P7 7 Input port P8 0 P8 1 Input port P8 2 P8 3 P8 5to P8 7 Input port Input port P10 Input port Pin Name 20 or more Single chip mode FFFFCh Content of reset vector necessary Address Figure 5 2 Reset Sequence 5 2 Software Reset The microcomputer resets pins the CPU and SFRs when the PMO3 bit in the PMO register is set to 1 microcomputer reset Then the microcomputer executes the program in an address determined by the reset vector The 125 kHz on chip oscillator clock divided by 8 is automatically selected as a CPU clock after reset In the software reset the microcomputer does not reset a part of the SFRs Refer to 4 Special Function Registers SFRs for details The internal RAM is not reset 5 3 Watchdog Timer Reset The microcomputer resets pins the CPU and SFRs when the PM12 bit in the PMI register is set to 1 reset when watchdog timer underflows and the watchdog timer underflows Then the microcomputer executes the program
106. phase are the same for the master and salves to be communicated Figure 13 32 shows the Transmission and Reception Timing in Master Mode Internal Clock Figure 13 33 shows the Transmission and Reception Timing CKPH 0 in Slave Mode External Clock Figure 13 34 shows the Transmission and Reception Timing CKPH 1 in Slave Mode External Clock Clock output CKPOL 0 CKPH 0 Clock output i CKPOL 1 CKPH 0 Clock output l CKPOL 0 CKPH 1 Clock output CKPOL 1 CKPH 1 Data output timing Data input timing Figure 13 32 Transmission and Reception Timing in Master Mode Internal Clock RO1UH0197EJ0120 Rev 1 20 zeENESAS Page 168 of 331 Jul 21 2011 M16C 6B Group Slave control input Clock input CKPOL 0 CKPH 0 1 Clock input H CKPOL 1 0 4 Data output timing Data input 1 UART2 output is an N channel open drain and must be pulled up externally Figure 13 33 Transmission and Reception Timing CKPH 0 in Slave Mode External Clock Slave control input Clock input H CKPOL 0 CKPH 1 q Clock input H CKPOL 1 CKPH 1 4 Data output timing 1 UART2 output is an N channel open drain and must be pulled up externally I 1 D Figure 13 34 Transmission and Reception
107. reet te iter ee eere here e oi ete eere 65 9 4 2 Relocatable Vector Tables oett ende edet ber roO prete 66 9 5 Interrupt Control n ete rte Roe aeo n e BA Aiea hate 68 9 5 1 PM 70 9 5 2 IR BIU snes Stele ae es E ES ep EE ec 70 9 5 3 Bits IEVE2 t0 IE VEO and IRD Xie weet Bi et Opere eo iter e re ER PUER eect 70 9 5 4 Interrupt Sequence oce haa Rep bard ete 71 9 5 5 Interrupt Response ee hp eee Ere En HT E RR ge Dre CHER 72 9 5 6 Variation of IPL When Interrupt Request IS Accepted essen 72 9 5 7 SAVING REGISELS MEE 73 9 5 8 Returning from an Interrupt Routine oo ee eee eene ener enne teer 74 9 5 9 Interr pt Priority iere Rp OUI OI Rut ate 74 95 10 Interrupt Priority Level Select Circuit rr CHE Ee ers 74 9 6 Ib Wires e es TD RAM 76 9 7 WME interrupt d ege ae vdd Ne ae Me ME TI 9 8 Key Input Interr pt 2 2 50 o oit aene eec d eror edd 77 9 9 Address Match Interrupt ossessione rener asor etr p tp Er pee ree ea hier etie ch scenes 80 10 Watchdog Timer urea Hebe tte inr b e ee qct ora cba dete ea 82 10 1 Count Source Protection Mode Disabled eene eene nennen enne 85 10 2 Count Source Protection Mode Enabled esses eene eene ener enne 86 112 87 11 1 Transfer CYCLES eie eie Dedi iin niim xy ee boa esu gne 93 11 1 1 Effect of Source
108. register 2 The selectable factors of DMA requests differ with each channel 3 Make sure that no DMAC related registers addresses 0180h to 01BFh are accessed by the DMAC R01UH0197EJ0120 Rev 1 20 ztENESAS Page 88 of 331 Jul 21 2011 M16C 6B Group 11 DMAC DMAi Source Select Register i 0 to 3 b7 b6 b5 b4 b2 bi bO Symbol Address After Reset DMOSL 0398h 00h DMI Br 039Ah 00h 0390h 00h DM3SL 0392h 00h DSELO DMA request source select bit b5 No register bit If necessary set to 0 Read as 0 DMA request source 0 Basic request source OMS expansion select bit 1 Extended request source A DMA request is generated by setting this bit to 1 when the DMS bit is 0 basic Software DMA request bit source and bits DSEL4 to DSELO are 00001b software trigger Read as 0 1 The sources of DMAi requests can be selected by a combination of the DMS bit and bits DSEL4 to DSELO in the manner described in Figure 11 3 Figure 11 2 Registers DMOSL to DMSSL 1 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 89 of 331 Jul 21 2011 M16C 6B Group DSEL4 to DSELO DMS 0 Basic Factor of Request Falling edge of INTO pin DMS 1 Extended Factor of Request DSEL4 to DSELO DMS 0 Basic Factor of Request 11 DMAC DMS 1 Extended Factor of Request Software trigger Software trigger Timer AO Timer AO Timer A1 Timer A1 Timer A2 Timer A2
109. register 3 Read Received Data i Oto2 NOTES The UiRB register status is read Bits 6 to 0 in the UiRB register are read as bits 7 to 1 Bit 8 in the UiRB register is read as bit 0 4 1 If the source or factor of any interrupt is changed the IR bit in the interrupt control register for the changed interrupt may inadvertently be Set to 1 interrupt requested Refer to 20 5 Interrupt If one of the bits shown below is changed the interrupt source the interrupt timing etc change Therefore always be sure to clear the IR bit to O interrupt not requested after changing those bits Bits SMD2 to SMDO in the UiMR register the IICM bit in the UiSMR register the IICM2 bit in the UISMR register and the CKPH bit in the UiSMRS register NORD Set the initial value of SDAi output while bits SMD2 to SMDO in the UiMR register 000b serial interface disabled Second data transfer to the UiRB register rising edge of SCLi 9th bit First data transfer to the UiRB register falling edge of SCLi 9th bit Refer to Figure 13 30 STSPSEL Bit Functions Refer to Figure 13 28 Transfer to UiRB Register and Interrupt Timing When using UARTO be sure to set the IFSR26 bit in the IFSR2A register to 1 factor of interrupt UARTO bus collision When using UART1 be sure to set the IFSR27 bit in the IFSR2A register to 1 factor of interrupt UART1 bus collision R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS
110. register to 001b 101b and 110b 3 1 15 written to the RE bit in the UiC1 register transmission enabled regardless of the TE bit in the UiC1 register 13 1 2 3 LSB First MSB First Select Function As shown in Figure 13 23 use the UFORM bit in the UiCO register to select the transfer format This function is valid when transfer data is 8 bits long 1 When the UFORM Bit in the UiCO Register 0 LSB First CLKi TXDi ST X D X D2 X D4 X D5 X D6 A D7 A SP RXDi st Do X D1 A D2 X D4 X D5 X D6 X D7 A P SP 2 When the UFORM Bit in the UiCO Register 1 MSB First CLKi st 07 X D5 X D4 X D3 X D2 X D1 X Do X P SP RXDi ST D7 X De X D5 X D4 X D2 X D1 X DO X P_Y SP ST start bit P parity bit SP stop bit i 0to2 The above applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the UiLCH bit in the UiC1 register 0 no reverse the STPS bit in the UiMR register 0 1 stop bit and the PRYE bit in the UiMR register 1 parity enabled Figure 13 23 Transfer Format RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 153 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 2 4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted Similarly the received data has i
111. retransmission gt ACK reception If no ACK is received after repeating retransmission for the number of the set times the TRNRCVSQC bit is set to 1 false Bits RCVBANKO and are used as the flags for capturing a frame in receive banks 0 and 1 respectively These bits are automatically set to 1 when frame reception starts When the address filter is enabled these bits are set to at the same time an address filter interrupt is generated Then they are cleared to 0 by software after the data in the receive RAM is read Only 0 can be written to If reception is performed again while these bits are 1 and data is written to each receive RAM a reception overrun interrupt is generated The RCVPEND bit is used to store the value of the pending bit when an ACK frame is received The RCVBANKST bit can be used to confirm the receive RAM bank in which the last frame that has been received After a reset this bit indicates 1 once it is initialized Transmit Receive Status Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBTXRXSTO 0107h 80h 2 DUM CCA check result bit ie aba clear 1 Channel busy 0 TRUE CRC check result bit 1 FALSE 0 TRUE CSMACA CSMA CA check result bit 1 FALSE Transmit receive operation 0 TRUE complete check result bit 1 FALSE 0 Reception enabled RCVBANKO Receive bank 0 status bit 1 Received data present 0 Reception enab
112. that appear multiple times Register Register Timer B5 Interrupt Control Register 5 Timer B4 Interrupt Control Register UART1 BUS Oollision Detection Interrupt Control Register TB4IC U1BCNIC Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 Timer B3 Interrupt Control Register UARTO BUS Oollision Detection Interrupt Control Register UOBCNIC System Clock Control Register 1 Timer Compare 0 Interrupt Control Register BBTIMOIC Timer Compare 1 Interrupt Control Register BBTIM1IC UART2 BUS Collision Detection Interrupt Control Register BCNIC Protect Register DMAO Interrupt Control Register DMOIC DMA1 Interrupt Control Register DM1IC Oscillation Stop Detection Register Key Input Interrupt Control Register KUPIC A D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register S2TIC UART2 Receive Interrupt Control Register S2RIC Program 2 Area Control Register UARTO Transmit Interrupt Control Register SOTIC UARTO Receive Interrupt Control Register SORIC Peripheral Clock Select Register UART1 Transmit Interrupt Control Register S1TIC UART1 Receive Interrupt Control Register S1RIC Timer AO Interrupt Control Regis TAOIC Clock Prescaler Reset Flag Timer A1 Interrupt Control Regi
113. to 4 Register in One Shot Timer Mode Table 12 5 Count source Specifications in One Shot Timer Mode Specification f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S fC32 Count operation Decrement When the counter reaches 0000h it stops counting after reloading a new value f a trigger occurs when counting the timer reloads a new count and restarts counting Divide ratio 1 n n set value of the TAi register 0000h to FFFFh However the counter does not work if the divide by n value is set to 0000h Count start condition 1 The TAIS bit in the TABSR register 1 start counting and one of the following triggers occurs External trigger input from the TAiIN Timer B2 underflow Timer Aj j 2i 1 except j 4 if i 0 overflow or underflow Timer Ak 2 i 1 except k 0 if i 4 overflow or underflow The TAiOS bit in the ONSF register is set to 1 timer starts Count stop condition 1 When the counter is reloaded after reaching 0000h The TAIS bit is set to 0 stop counting Interrupt request generation timing 1 When the counter reaches 0000h pin function 1 I O port or trigger input TAiOUT pin function 1 I O port or pulse output Read from timer An indeterminate value is read by reading the TAi register Write to timer When not counting and until the 1st count source is input after counting starts Value written to t
114. to 0003h Reference M16C 60 M16C 20 M16C Tiny series software manual Timer B5 20 to 23 0014h to 0017h 12 Timers Timer B4 UART1 bus collision detect 3 5 24 to 27 0018h to 001Bh Timer B3 UARTO bus collision detect 3 5 28 to 31 001Ch to 001Fh 12 13 Timers Serial Interface Timer compare 0 32 to 35 0020h to 0023h Timer compare 1 36 to 39 0024h to 0027h Baseband Functionality UART2 bus collision detection 5 40 to 43 0028h to 002Bh Serial Interface DMAO DMA1 DMAC Key input interrupt 48 to 51 0030h to 0033h 452 to 455 0034h to 0037h Key Input Interrupt A D 64 pin version only 44 to 47 002Ch to 002Fh 56 to 59 0038h to 003Bh A D Converter 64 Pin Version Only UART2 transmit NACK2 2 60 to 63 003Ch to 003Fh UART2 receive ACK2 2 64 to 67 0040h to 0043h UARTO transmit NACKO 2 68 to 71 0044h to 0047h UARTO receive ACKO 2 72 to 75 0048h to 004Bh UART1 transmit NACK1 2 UART1 receive ACK1 2 80 to 83 0050h to 0053h Serial Interface Timer AO 84 to 87 0054h to 0057h Timer A1 0058h to 005Bh 88 to 91 Timer A2 76 to 79 004Ch to 004Fh 92 to 95 005Ch to 005Fh Timer A3 96 to
115. to select the number of wait states for data flash When setting this bit to 0 one wait is inserted to the read cycle of the data flash The write cycle is not affected RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 262 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 3 3 Flash Memory Control Register 2 FMR2 Flash Memory Control Register 2 b7 b6 b5 b4 b3 b2 bi Symbol Address After Reset WMA XXX 100 FMR2 0222h XXXX0000b roo I i RW b1 b0 Reserved bits Set to 0 M Slow read mode enable 0 Disabled a bit 1 Enabled Low current consumption 0 Disabled read mode enable bit 1 Enabled No register bits If necessary set to 0 Read as undefined value FMR22 Slow read mode enable bit b2 FMR23 Low current consumption read mode enable bit b3 Refer to 7 4 4 Power Control of Flash Memory RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 263 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 3 4 Flash Memory Control Register 6 FMR6 Flash Memory Control Register 6 b7 b6 b5 b4 b3 b2 bi Symbol Address After Reset FMR6 0230h XX0XXX00b 1 Bit Name Function EW1 mode select bit E Ts b4 b2 Reserved bits Read as undefined value o b5 1 I 1 1 1 i 1 1 1 1 Reserved bit Set to 0 b7 b6 Reserved bits Read as undefined value When accessing the FMR6 register set a CPU clock frequency of 8 MHz o
116. use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics p
117. value CRCD register 3 Write 01h CRCIN register Two cycles later the CRC code for 80h i e 9188h has its bit positions reversed to become 1189h which is stored in the CRCD register CRCD register 4 Write 23h CRCIN register Two cycles later the CRC code for 80C4h i e 8250h has its bit positions reversed to become 0A41h which is stored in the CRCD register CRCD register Details of CRC operation As shown in 3 above bit position of 01h 00000001b written to the CRCIN register is reversed and becomes 10000000b Add 1000 0000 0000 0000 0000 0000b as 10000000b plus 16 digits to 0000 0000 0000 0000 0000 0000b as 0000 0000 0000 0000b plus 8 digits as the default value of the CRCD register to perform the modulo 2 division Modulo 2 operation is 1000 1000 operation that complies 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 4 Data with the law given below 1000 1000 0001 0000 1 Generator polynomial 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 zt CRC code Il 0001 0001 1000 1001b 1189h the remainder 1001 0001 1000 10000 9188h with inversed bit position can be read from the CRCD register When going on to 4 above 23h 0010001 1b written in the CRCIN register is reversed and becomes 11000100b Add 1100 0100 0000 0000 0000 0000b as 11000100b plus 16 digits to 1001 0001 1000 1000 0000 0000b as 1001 0001 1000 1000b plus 8 digits as a remainder
118. value of UIBRG register 00h to FFh Slave mode The CKDIR bit 1 external clock selected input from the CLKi pin Transmit receive control Controlled by input output ports Transmission start Before transmission starts satisfy the following requirements 1 condition The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in UITB register Reception start condition Before reception starts satisfy the following requirements 1 The RE bit in the UiC1 register 1 reception enabled The TE bit 1 transmission enabled The TI bit 0 data present in the UITB register Interrupt request While transmitting one of the following conditions can be selected generation timing The UiIRS bit in the UiC1 register 0 transmit buffer empty when transferring data from the UiTB register to the UARTI transmit register at start of transmission The UiIRS bit 21 transfer completed when the serial interface completed sending data from the UARTi transmit register While receiving When transferring data from the UARTi receive register to the UiRB register at completion of reception Error detection Overrun error 2 This error occurs if the serial interface starts receiving the next data before reading the UiRB register and receives the 7th bit of the next data Select function Clock phase setting Selectable from four combinations of transfer clock polaritie
119. 0 P7 1 and P8 5 are N channel open drain output ports No pull up resistor is ___ provided P8 5 is an input port for verifying the NMI pin level and shares a pin with NMI R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 10 of 331 M16C 6B Group 1 Overview Table 1 7 Signal Name Analog power supply input Pin Functions 2 Pin Name VCCRF VSSRF VSSRF1 Description Apply 2 2 V to 3 6 V the VCCRF pin Apply 0 V to pins VSSRF and VSSRF1 VSSRF2 VSS pin for the IF circuit Apply 0 V VSSRF3 VSS pin for the MIX circuit Apply O V VSSRF4A VSSRF4B VSS pin for the LNA PA circuit Apply O V VSSRF5 VSS pin for the VCO circuit Apply 0 V VSSRF6 VSS pin for the PLL circuit Apply 0 V VREGIN1 1 5 V IFVCC pin Connect to the VREGOUT1 pin VREGIN2 1 5 V MIXVCC pin Connect to the VREGOUT1 pin VREGIN3 1 5 V LNA PAVCC pin Connect to the VREGOUT1 pin VREGIN4 1 5 V PLLVCC pin Connect to the VREGOUT1 pin Regulator output VREGOUT1 On chip regulator output 1 5 V pin for the analog circuit Connect only a bypass capacitor between pins VREGOUT1 and VSS Use only as the power supply for pins VREGIN1 VREGIN2 VREGINS and VREGFIN4 VREGOUT2 Regulator output 1 5 V pin for the VCO circuit Connect only a bypass capacitor between pins VREGOUT2 and VSS Do not use as the power supply for other circuits VREGOUT3 Regulato
120. 0 Kbytes E 256 Kbytes 20 Kbytes Number of pins 3 64 pins 4 48 pins M16C 6B Group 16 bit MCU Memory type F Flash memory Renesas MCU Renesas semiconductor Figure 1 1 Correspondence of Part No with Memory Size and Package R01UH0197EJ0120 Rev 1 20 ztENESAS Jul 21 2011 Page 4 of 331 M16C 6B Group 1 Overview 1 4 Block Diagram Figure 1 2 shows a Block Diagram Port P10 Peripheral function eripheral functions URTO clock synchronous serial I O Clock generation circuits Timer 16 bit 3 channels Sea Outputs Timer A 5 On chip oscillator 125 kHz Inputs Timer B 6 DMAC 4 channels CRC calculation circuit Watchdog timer CCITT 15 bits x 1 Polynomial X 9 2 X5 1 A D converter M16C 60 Series CPU 10 bits x 8 channels one On chip debug function RF block Baseband Regulator NOTES 1 ROM size depends on MCU type 2 RAM size depends on MCU type 3 Timer A in the 48 pin version has functional limitations 4 No A D converter is available in the 48 pin version Figure 1 2 Block Diagram RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 5 of 331 Jul 21 2011 M16C 6B Group 1 Overview 1 5 Pin Assignments Figures 1 3 and 1 4 show pin assignments top view 1 KIZ P7_0 TAQOQOUT TXD2 SDA2 KI14 1 P7 1 TAOIN RXD2 SCL2 KI5 P7_2 TA10OUT CLK2 KI6 2 I
121. 000000h The COMPOTRG bit can be used to start RF transmission when the timer compare 0 value and the timer value match Warming up begins right after the match and transmission starts 144 us later Make sure to perform operations in IDLE status Timer Control Register b7 b6 b5 b4 b3 b2 b1 bO Sym Address After Reset ymbol MIXX X10 0134h 00h L 1 1 1 1 1 TIMEEN Timer count enable bit O Timer count stopped COMPO transmit trigger 0 Transmission trigger disabled enable bit 1 Transmission trigger enabled Reserved bit Set to 0 No register bits If necessary set to 0 Read as 0 Figure 15 36 Timer Control Register Configuration 15 2 28 Backoff Period Register The BOFFPROD bit can be used to set the random value of the backoff period when executing CSMA CA By setting the BOFFPRODEN bit to 1 a random value is automatically generated with the value set in the BOFFPROD bit as the initial value and the backoff period value in the CSMA CA circuit is set Make sure to set the BOFFPRODEN bit to 1 after the random value has been set with the BOFFPROD bit The BOFFPROD bit does not need to be set again while the BOFFPRODEN bit is set to 1 Backoff Period Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset BBBOFFPROD 0135h 00h 0 Backoff period automatic random Backoff period auto random disabled enable bit 1 Backoff period automatic random enabled BOFFPRODEN BOFFPROD Ba
122. 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h Timer B3 Register 0355h 0356h Timer B4 Register 0357h 0358h Timer B5 Register 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh Timer B3 Mode Register 0360h Timer B4 Mode Register 0361h Pull Up Control Register 1 PUR1 248 Timer B5 Mode Register 0362h Pull Up Control Register 2 PUR2 248 0363h 0364h Count Start Flag 0365h 0366h One Shot Start Flag 0367h Trigger Select Register 0368h Up Down Flag 0369h 036Ah Timer AO Regis 036Bh 036Ch Timer A1 Regis 036Dh 036Eh Timer A2 Regis 036Fh 0370h Timer A3 Regis 0371h 0372h Timer A4 Regis 0373h 0374h Timer BO Regis 0375h 0376h Timer B1 Regis 0377h 0378h Timer B2 Regis 0379h 037Ah Timer AO Mode Register 037Bh Timer A1 Mode Register 037Ch Count Source Protection Mode Register CSPR 84 Timer A2 Mode Register 037Dh Watchdog Timer Reset Register WDTR 83 Timer A3 Mode Register 037Eh Watchdog Timer Start Register WDTS 83 Timer A4 Mode Register 037Fh Watchdog Timer Control Register WDC 83 Timer BO Mode Re
123. 0_0 to P10 7 1 Input port P10 Input or L level signal or open VCCRF Power input Connect to VCC VSSRF VSSRF1 Power input Apply 0 V VSSRF2 Power input Apply 0 V VSSRF3 Power input Apply 0 V VSSRF4A VSSRF4B Power input Apply 0 V VSSRF5 Power input Apply 0 V VSSRF6 Power input Apply 0 V VREGIN1 Power input Connect to VREGOUT1 VREGIN2 Power input Connect to VREGOUT1 VREGIN3 Power input Connect to VREGOUT1 VREGIN4 Power input Connect to VREGOUT1 VREGOUT1 Power output Connect to VREGIN1 to VREGIN4 VREGOUT2 Power output Connect a bypass capacitor between pins VREGOUT2 and VSS VREGOUT3 Power output Connect a bypass capacitor between pins VREGOUT2 and VSS RFIOP RFION RF I O RF I O TESTIOP TESTION Testing ports Input L or open ANTSWCONT NOTE 1 Not available in the 48 pin version Control output R01UH0197EJ0120 Rev 1 20 Jul 21 2011 Output pin to control the external antenna switch ztENESAS Page 278 of 331 M16C 6B Group 18 Flash Memory 64 61 eo se se sv 56 5 51 50 49 O M16C 6B3 s z s s o Io v 9 aN e Connect an oscillation circuit AB 15 fal Q NU 18 19 20 21 22 28 24 25 26 27 28 29 31
124. 1 Register in PWM Mode R01UHO197EJ0120 Rev 1 20 ztENESAS Page 118 of 331 Jul 21 2011 M16C 6B Group 12 Timers 1 0 x 218 1 Count source Input signal to TAiIN H PWM pulse output from TAiOUT pin When TOFSi 0 waveform output H active not inverted E I When TOFSi 1 waveform output L active inverted Q4 IR bit in register 0 fj count source frequency S p d f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S C32 Set to 0 upon accepting an interrupt Only i 0 or 1 in the 48 pin version request or by writing in program TOFSi bit in the TAPOFS register NOTES 1 n 2 0000h to FFFEh 2 This timing diagram is for the case where the TAi register is 0003h bits TAITGH and in the ONSF register or TRGSR register are 00b input to the pin the MR1 bit in the TAiMR register is 1 rising edge and the 2 bit in the TAiMR register is 1 trigger selected by bits TAITGH and Figure 12 17 Example of 16 Bit Pulse Width Modulator Operation 1 fj x 1 x 28 1 Count source 1 Input signal to TAiIN pin 8 bit prescaler underflow signal PWM pulse output from TAiOUT pin When TOFSi 0 waveform output H active not inverted When TOFSi 1 waveform output L active inverted IR bit in TAiIC register 1 g fj count source frequency X f
125. 1 1 Effect of Source and Destination Addresses When a 16 bit data is transferred with a 16 bit data bus and a source address starts with an odd address source read cycle is incremented by one bus cycle compared to a source address starting with an even address When a 16 bit data is transferred with a 16 bit data bus and a destination address starts with an odd address destination write cycle is incremented by one bus cycle compared to a destination address starting with an even address 11 1 2 Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted the number of bus cycles required for that access increases by an amount equal to software wait states Figure 11 7 shows an Example of Transfer Cycles for Source Read For convenience the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown In reality the destination write cycle is subject to the same conditions as the source read cycle with the transfer cycle changing accordingly When calculating transfer cycles apply each condition to the source read and the destination write cycle respectively For example when data is transferred in 16 bit units using an 8 bit bus 2 on Figure 11 7 two bus cycles are required for source read and destination write each R01UH0197EJ0120 Rev 1 20 24 NC SAS Page 93 of 331 Jul 21 2011 11 DMAC M16C 6B Group o o
126. 1 20 ztENESAS Page 185 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 0 iP Sele Symbol Address After Reset LL goto ADCONO 03D6h 00000XXXb 1 roy Bit Symbol Bit Name Function Analog input pin select bit Invalid in repeat sweep mode 0 A D operation mode select b4 b3 bit 0 1 0 Single sweep mode Reserved bit Set to 0 0 A D conversion stop A D conversion start flag I AD conversion start Frequency select bit 0 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 De DO DADA OE Di DO Symbol Address After Reset eloj ol ADCON1 03D7h 0000X000b Bit Symbol Bit Name Function When single sweep mode is selected b1 bO 0 0 ANO to AN1 2 pins 0 1 ANO to AN3 4 pins 1 0 ANO to AN5 6 pins 1 1 ANO to AN7 8 pins A D sweep pin select bit A D operation mode select Set to 0 when single sweep mode is bit 1 selected No register bit If necessary set to 0 Read as undefined value Frequency select bit 1 RW NOTES 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the ADSTBY bit is changed from 0 A D operation stopped to 1 A D operation enabled wait for 1 9AD cycle or more before starting A D conversion p 2 222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
127. 1 20 ztENESAS Page 216 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 11 Transmit Receive Mode Register The ADRSFILEN bit can be used to enable the address filter for reception The PANCORD bit can use used to set whether or not to receive a receive frame with no destination address whether a PAN coordinator or not as a requirement for the address filter Bits LVLFILENO and LVLFILENI can be used to set the reception of only input frames higher than the threshold level set in the BBLVLV TH register The RCVBANKSEL bit is used to specify the bank for read accesses associated with receive RAM The RCVOVERWREN bit can be used to control the overwriting to receive RAM While this bit is O if bits RCVBANKO and RCVBANKI in the BBTXRXMODEO register are set to 1 received data present received data is not overwritten when a write access occurs to each receive RAM However a reception overrun 0 1 interrupt is generated While the RCVOVERWREN bit is 1 if bits RCVBANKO and RCVBANKI in the BBTXRXMODEO register are set to 1 received data present received data is overwritten when a write access occurs to each receive RAM However a reception overrun 0 1 interrupt is generated Transmit Receive Mode Register 3 7 b6 b5 b4 b3 b2 b1 b0 Symbol Address i dias BBTXRXMODE3 010Ah meet LR 0 Address filter disabled 1 Address filter enabled ADRSFILEN filter enable bit 0 NonPAN co
128. 1 Operating Speed Set a CPU clock frequency of 8 MHz or less by the CMO6 bit in the register and bits CM17 and CM16 in the register before entering CPU rewrite mode EWO or EW1 mode Also set the PM17 bit in the PM1 register to 1 wait state 20 10 3 2 CPU Rewrite Mode Select Change FMRO1 bit in the FMRO register FMR11 bit in the FMR1 register and FMR60 bit in the FMR6 register while in the following state PM24 bit in the PM2 register is 0 NMI interrupt disabled High is input to the NMI pin 20 10 3 3 Prohibited Instructions Do not use the following instructions in EWO mode UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 20 10 3 4 Interrupts EWO Mode and EW1 Mode Do not use an address match interrupt during command execution because the address match interrupt vector is located in ROM Do not use a non maskable interrupt during block 0 erase because the fixed vector is located in block 0 20 10 3 5 Rewrite EWO mode If the power supply voltage drops while rewriting the block where the rewrite control program is stored the rewrite control program is not correctly rewritten This may prevent the flash memory from being rewritten If this error occurs use standard serial I O mode or parallel I O mode for rewriting 20 10 3 6 Rewrite EW1 mode Do not rewrite any blocks in which the rewrite control program is stored R01UHO197EJ0120 Rev 1 20 ztENES
129. 11 M16C 6B Group 9 Interrupt 9 Interrupt 9 1 Type of Interrupts Figure 9 1 shows Type of Interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction Software non maskable interrupt Interrupt DEC 2 Watchdog timer Special _____ Oscillation stop non maskable interrupt and re oscillation detection Low voltage detection Single step Peripheral function Address match maskable interrupt Hardware NOTES 1 The peripheral functions in the microcomputer are used to generate the peripheral interrupt 2 Do not normally use this interrupt because it is provided exclusively for use by development tools Figure 9 1 of Interrupts Maskable Interrupt The interrupt priority can be changed by enabling disabling an interrupt with the interrupt enable flag I flag or by using interrupt priority levels Non Maskable Interrupt The interrupt priority cannot be changed by enabling disabling an interrupt with the interrupt enable flag I flag or by using interrupt priority levels RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 62 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 2 Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts 9 2 1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction
130. 120 Rev 1 20 Jul 21 2011 TACS1 register i 2 TACSO and TACS1 ztENESAS b6 b5 b4 0 HTIMAB or f2TIMAB f8TIMAB f82TIMAB f64TIMAB Do not set fOCO S fC32 Do not set 1 TCKO TCK1 enabled TCS4 to TCS6 disabled 0 TCKO TCK1 disabled TCS4 to TCS6 enabled Page 107 of 331 M16C 6B Group 12 Timers Timer A Count Source Select Register 2 b7 b6 b5 b4 b3 b2 bi bo Symbol Address After Reset TACS2 01D2h XOh Bit Symbol Bit Name Function c f1TIMAB or f2TIMAB fSTIMAB fa2TIMAB f64TIMAB Do not set fOCO S fC32 Do not set 1 TCKO TCK1 enabled TCSO to TCS2 TA4 count source option disabled specified bit 0 TCKO TCK1 disabled TCSO to TCS2 enabled TA4 count source select bit k E l O oOo 0 No register bits If necessary set to 0 Read as undefined value 1 Set this value at the PCLKO bit in the PCLKR register Timer A Waveform Output Function Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset TAPOFS 01D5h XXX00000b POFSO output polar control bit POFS1 TA1OUT output polar control bit 0 Output waveform H active POFS2 TA2OUT output polar control bit 1 Output waveform L active output reversed POFS3 output polar control bit POFS4 TA4OUT output polar control bit 1 b7 b5 No register bits If necessary set to 0
131. 15 2 shows the 26 Bit Timer Configuration Data bus Timer clock Count source Timer 26 bits Time stamp latch 26 bits 16 MHz i Reception complete signal 4 Count enabled RCVFIN GED Timer cdmpare 0 26 bits Transmission trigger ME E Timer compare 0 interrupt COMPOINT CG 794 Timer c mpare 1 26 bits Timer compare 1 interrupt COMP 1INT C DH Timer cdmpare 2 26 bits Timer compare 2 interrupt COMP2INT gt Figure 15 2 26 Timer Configuration 15 1 3 1 Timer Compare i Interrupt A timer compare i interrupt is generated when the timer value and the timer compare i value match Timer compare 0 also functions as a transmission start signal Transmission automatically starts 144 us after a transmission start signal is generated 15 1 3 2 Timer Stamp The timer value when frame reception is completed is stored in registers BBTSTAMPO and BBTSTAMPI These registers are retained until the next frame reception is completed 15 1 3 3 Reading Timer Values Timer values can be read from registers BBTIMEREADO and BBTIMEREAD 1 When reading timer values read the BBTIMEREADO register lower byte first When either bits 7 to 0 or bits 15 to 8 in the BBTIMEREADO register or both are read the count value of all bits is latched The latched value is discarded when bits 25 and 24 in the BBTIMEREADI register highest byte are read If the BBTIMEREADI register is read first note the BBTIME
132. 156 19 4 Special Mode eee i b Oi i p pde ie i eed epo EE pet 166 13 1 5 Special Mode 3 IE mode eret perenne covey ret err redet egt 170 13 1 6 Special Mode 4 SIM Mode UARTO 00 ee ceeceeseeseeseeececeececeseecsaeceaceceeeeeneceeneesaeceaeeceneeeaeeeeeens 172 14 A D Converter 64 Pin Version Only 177 14 1 Mode Description x co eee idem Ett tci Ri Eae cite vernon 181 14 1 1 One Shot Mode ou eee ee epu ale ai he die edet pce yd te te eee et 181 14 12 Repeat Mode ee E P QU E RE IEEE GRE E E UE 183 14 5 3 Single Sweep ict bm Ip RD rr HR TREE DO PEE eb Ree eere ERR 185 14 1 4 Repeat Sweep Mode 0 ete estie sets Wests ie Dee dee orte age Peres aoe 187 T415 Repeat Sweep Mode ois rettet rae Rf tied teer tp d tei eos 189 14 2 Conversion neg eiae nce Rp RI RR pre Eee oek 191 14 3 Current Consumption Reducing Function eese enne 191 14 4 Output Impedance of Sensor under A D Conversion 192 15 Baseband F rictioriality 2 2 55 do dia e a a eR RE 193 15 1 Baseband Functional Description sese enne enne entren trennen nenne erinnere 193 151 Baseband Block Diagr m ete Ant e dtd e e bere uec eti 194 15 1 2 Baseband Terminological Description esessssseesseseeeeeeeennen enne n
133. 16 bits AD7 register 16 bits NM 1 Data bus hig rode SZ Data bus low order Decoder for channel selection Comparator N CH2 to CHO Figure 14 1 A D Converter Block Diagram R01UH0197EJ0120 Rev 1 20 ztENESAS Page 178 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 0 Symbol Address After Reset ENCNNN N ADCONO 03D6h 00000XXXb 1 Bit Symbol Bit Name Function CHO CH1 Analog input pin select bit Function varies with each operation mode b4 b3 0 0 One shot mode A D operation mode select 0 1 Repeat mode bit 0 1 0 Single sweep mode 1 1 Repeat sweep mode 0 or repeat sweep mode 1 Reserved bit Set to 0 0 A D conversion stop A D conversion start flag 1s A D conversion start Frequency select bit 0 Refer to NOTE 2 of the ADCON 2 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi bo Symbol Address After Reset olo XI ADCON1 03D7h 0000X000b 1 Bit Symbol Bit Name Function 1 SCANO A D sweep pin select bit Function varies with each operation mode SCAN1 A D operation mode 0 Any mode other than repeat sweep mode 1 select bit 1 1 Repeat sweep mode 1 No register bit If necessary set to 0 Read as undefined value Frequency select bit 1 Refer to NOTE 2
134. 16C 6B Group 17 Programmable I O Ports Pull up selection P10 0to P10 30 Direction register lt Port latch Analog input Pull up selection 2 Direction P10 4to P10 7 register Data bus Port latch Analog input Input to respective peripheral functions Port control register Pull up selection Direction P5_5 P5_7 P6_0 register P6_4 P7_3 P7 402 6 2 P8_0 Data bus Port latch Input to respective peripheral functions 9 NOTES 1 4 r symbolizes a parasitic diode Make sure the input voltage on each port will never exceed VCC 2 64 pin version only Figure 17 1 Ports 1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 243 of 331 Jul 21 2011 M16C 6B Group 17 Programmable I O Ports Pull up selection Direction P6 1 to P6 3 register Pe 5to P6 7 7 2 CMOS Nch selection Input to respective peripheral functions Pull up selection E Direction p E register Data bus 4 latch Input to respective peripheral functions Direction P7 0 P7 1 register Data bus Port latch Input to respective peripheral functions 4 NOTES 1 4 symbolizes a pa
135. 18 1 Table 18 1 Flash Memory Specifications Item Specification Flash memory rewrite mode 3 modes CPU rewrite standard serial I O parallel 1 0 Erase block Program ROM 1 Refer to Figure 18 1 Flash Memory Block Diagram Program ROM 2 1 block 16 Kbytes Data flash 2 blocks 4 Kbytes each Program method In units of 2 words Erase method Block erase Program and erase control method Program and erase controlled by software command Protect method The lock bit protects each block Number of commands 8 commands Program and erase endurance 100 times 1 Data retention 10 years ROM code protection Parallel I O and standard serial I O modes are supported NOTE 1 Definition of program and erase endurance The program and erase endurance refers to the number of per block erasures For example assume a case where a 4 Kbyte block is programmed in 1 024 operations writing two words at a time and erased thereafter In this case the block is reckoned as having been programmed and erased once If the program and erase endurance is 100 times each block can be erased up to 100 times Table 18 2 Flash Memory Rewrite Mode Function CPU rewrite Mode Program ROM 1 program ROM 2 and data flash are rewritten when the CPU executes software commands EWO mode Rewritable in RAM EW1 mode Rewritable in the flash memory Flash Mem
136. 18Bh 018Ch DMAO Control Register DMOCON 00000X00b 018Dh 018Eh 018Fh 0190h 0191h 0192h DMA1 Source Pointer 0193h 0194h 0195h 0196h DMA1 Destination Pointer 0197h 0198h 0199h Transfer Counter 019Ah 019Bh 019Ch Control Register DM1CON 00000X00b 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h DMA2 Source Pointer 01A3h 01A4h 01A5h 01A6h DMA2 Destination Pointer 01A7h 01A8h 01A9h DMA2 Transfer Counter 01AAh 01ABh 01ACh DMA2 Control Register DM2CON 00000X00b 01ADh 01AEh 01AFh 01BOh 01B1h 01B2h DMAS3 Source Pointer 01B3h 01B4h 01B5h 01B6h DMAS Destination Pointer 01B7h 01B8h 01B9h DMAS3 Transfer Counter 01BAh 01BBh 01BCh DMAS3 Control Register DM3CON 00000X00b 01BDh 01BEh 01BFh NOTE 1 The blank areas are reserved and cannot be accessed by users X Undefined RO1UH0197EJ0120 Rev 1 20 Jul 21 2011 RENESAS Page 21 of 331 M16C 6B Group 4 Special Function Registers SFRs Table 4 7 SFR Information 7 1 Address Register After Reset Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Tim
137. 1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S fC32 Set to 0 upon accepting an interrupt request or by Only i 0 or 1 in the 48 pin version writing in program TOFSi bit in TAPOFS register NOTES 1 The 8 bit prescaler counts the count source 2 The 8 bit pulse width modulator counts underflow signals of the 8 bit prescaler 3 m 00h to FFh n 00h to FEh 4 This timing diagram is for the case where the TAi register is 0202h bits TAITGH and TAiTGL in the ONSF register or TRGSR register 00b input to the the MR1 bit in the TAiMR register is 0 falling edge and the MR2 bit in the TAiMR register is 1 trigger selected by bits TAiTGH and TAiTGL Figure 12 18 Example of 8 Bit Pulse Width Modulator Operation RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 119 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 2 Timer B Figure 12 19 shows a Timer B Block Diagram Figures 12 20 to 12 22 show registers related to Timer B Timer B supports the following two modes Use bits TMOD1 and TMODO in the TBiMR register i 0 to 5 to select the desired mode Timer Mode Select Clock Source TCK1 to TCKO 00 Timer i to Tn 9r 109619 109 01 Event Counter Underflow TCK1 to TCKO TMOD1 to TMODO bits in the TBiMR register TBiS bits in the TABSR register or TBSR register TCSO to TCS7 bits in registers TBCSO to TBCS3 Figure 12 19 Timer B Block Diagram The timer counts an interna
138. 2 and Timer A3 The timer increments rising edges or decrements falling edges on the TAjIN pin when input signals on the TAjOUT pin is TAjOUT A A A Y Y Y Increment Increment Increment Decrement Decrement Decrement Multiply by 4 processing operation Timer A3 and Timer A4 If the phase relationship is such that TAkIN pin goes H when the input signal on the TAKOUT pin is H the timer increments rising and falling edges on pins TAKOUT and TAKIN If the phase relationship is such that the TAKIN pin goes L when the input signal on the TAKOUT pin is the timer counts down rising and falling edges on pins TAKOUT and TAKIN Increment all edges Ara tsrs ese Increment all edges Decrement all edges Decrement all edges 1 Only Timer is selectable Timer A2 is fixed to normal processing operation and Timer A4 is fixed to multiply by 4 processing operation 2 64 version only R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 113 of 331 M16C 6B Group 12 Timers Timer Ai Mode Register i 2 2 to 4 When Using Two Phase Pulse Signal Processing 9 b7 b6 b5 b4 b3 b2 b1 bO 1 1 Symbol Address After Reset 1011 ojo TA2MR to TAAMR 0338h to 033Ah 00h 1 Operation mode select bit I I 1 I 1 1 1 1 i TMOD1 0 1 Event counter mode RW 1 1 1 MRO Set to 0 to use two phase pulse signal processing RW 1 1 I I I 1 I I
139. 20 Jul 21 2011 Gate function Counting can be started and stopped by an input signal to the TAiIN pin Pulse output function Whenever the timer underflows the output polarity of TAiOUT pin is inverted When the TAIS bit is set to 0 stop counting the pin outputs L Output polarity control While the output polarity of the TAiOUT pin is inverted the TAIS bit is set to 0 stop counting the pin outputs H Only i 2 O or 1 in the 48 pin version ztENESAS Page 109 of 331 M16C 6B Group 12 Timers Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset TAOMR to TA4MR 0336h to 033Ah 00h Bit Name Function Operation mode select bit pres 0 0 Timer mode TMOD1 RW 0 No pulse output MRO Pulse output function TAiOUT pin functions as I O port RW select bit 1 Pulse output TAiOUT pin functions as a pulse output pin MR1 LE Gate function not available Gate function select bit pin functions as I O port Counts while input on the pin is low Counts while input on the TAIN pin is high Set to 0 in timer mode 0 0 1 TIMAB or f2TIMAB 9 Count source select bit 0 1 fSTIMAB MR2 1 0 2 1 1 fC32 1 The TAOOUT pin is N channel open drain output 2 Set the port direction bit for the TAiIN pin 0 input mode 3 Selected by the PCLKO bit in the PCLKR register 4 Valid when the TCS3 bit or TCS
140. 3 bit is set to 0 main clock oscillates YES Set the CMO6 bit to 1 divide by 8 Set the CM22 bit to 0 main clock stop re oscillation not detected Set the CM21 bit to 0 main clock Bits CM21 to CM23 bits in the CM2 register Figure 7 12 Procedure to Switch Clock Source from 125 kHz On Chip Oscillator to Main Clock R01UH0197EJ0120 Rev 1 20 ztENESAS Page 60 of 331 Jul 21 2011 M16C 6B Group 8 Protection 8 Protection In the event that a program runs out of control this function protects the important registers so that they will not be rewritten easily Figure 8 1 shows the PRCR Register The following lists the registers protected by the PRCR register e The PRCO bit protects registers CM0 CM1 CM2 and PCLKR e The PRCI bit protects registers PM1 and PM2 The PRC6 bit protects the PRG2C register Protect Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset o o 0 0 000Ah ot i ot Bit Symbol Bit Name Function Enable write to registers CM1 CM2 and PCLKR 0 Write protected 1 Write enabled Protect bit 0 Enable write to registers PMO PM1 and PM2 0 Write protected 1 Write enabled Protect bit 1 Reserved bits Set to 0 Enable write to the PRG2C register Protect bit 6 0 Write protected 1 Write enabled b7 Reserved bit Set to 0 Figure 8 1 PRCR Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 61 of 331 Jul 21 20
141. 48KB A 0 12g S qgunguuUUUUUUO a 1 Reference Dimension in Millimeters Symbol Min Nom Max 1 70 0 90 1 00 by 0 005 0 02 0 04 b 0 17 0 22 0 27 b 0 201 e 1051 Lp 0 35 0 45 0 55 x 0 05 y 0 05 02 t Dimension including the plating thickness Hp 72 Base material dimension He 7 2 Zp 0 75 ZE 0 75 0 12 0 17 0 22 0 15 R01UH0197EJ0120 Rev 1 20 234 NC S AS Page 329 of 331 Jul 21 2011 M16C 6B Group Index A ADO tO ctore bianca feb eene be RR ER RARE 180 ADCONO T BDOGQONT 179 182 184 186 188 190 D De 180 DARO to DARS _ 92 AIER DMOCON to DM3CON 2 91 2 DMOIC to enei eere eere 68 DMOSL to DM3SL eter eee 89 90 B jl BEAD GIG
142. 5 Baseband Functionality 15 2 4 Transmit Receive Mode Register 1 The ACKRCVEN bit can be used to select whether to perform automatic receive operation The RETRN bit can be used to set the number of retransmit processing if there is no ACK response while automatic ACK receive mode is enabled The CCASEL bit can be used to select the CCA ED or RSSI value when reading the RSSI CCA result register The ANTSWEN bit can be used to enable the ANTSW output function Transmit Receive Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset BBTXRXMODE1 0103h 06h Bt Symbol Bt Symbol Binme Name MEET 0 Automatic ACK reception disabled ACKRCVEN Auto ACK receive mode bit 1 Automatic ACK reception enabled I ELI RETRN Retransmit count bit Set 000b to 111b 0 CCA ED CCASEL CCA result select bit 1 RSSI Reserved bit Set to 0 0 Disabled 1 Enabled es I Figure 15 13 Transmit Receive Mode Register 1 Configuration ANTSWEN ANTSW enable bit 0 R01UH0197EJ0120 Rev 1 20 21 NC SAS Page 211 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 5 Receive Frame Length Register This register stores the frame length value for reception When reading this register the frame length value corresponding to the receive RAM bank specified with the RCVBANKSEL bit in the BBTXRXMODE3 register is read The frame length value is stored when frame reception starts and it
143. 6 The interrupt priority level of the acknowledged interrupt in IPL is set 7 The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC After the interrupt sequence is completed an instruction is executed from the starting address of the interrupt routine NOTE 1 Temporary register cannot be modified by users 4 Address bus Address 00000 Indeterminate X vec 2 Data bus Interrupt SP 2 SP 4 y vec vec 2 X NICA Indeterminate X contents X contents contents contents Bi Indeterminate _ LI m NOTES 1 The indeterminate state depends on the instruction queue buffer A read cycle occurs when the instruction queue buffer is ready to accept instructions 2 The WR signal timing shown here is for the case where the stack is located in the internal RAM Figure 9 5 Time Required for Executing Interrupt Sequence RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 71 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 5 5 Interrupt Response Time Figure 9 6 shows the Interrupt Response Time The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed Specifically it consists of a time from when an interrupt request is generated till when the executing
144. 6 Register CRS CLKMD1 CLKMDO PD6 4 Input 0 Output 1 indicates either O or 1 NOTES 1 In addition to this set the CRD bit in the register to 0 CTSO RTSO enabled and the CRS bit in the UOCO register to 1 RTSO selected 2 When the CLKMD1 bit 1 and the CLKMDO bit 0 the following logic levels are output High if the CLKPOL bit in the U1CO register 0 H Low if the CLKPOL bit in the U1CO register 1 L R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 142 of 331 M16C 6B Group 13 Serial Interface 1 Example of Transmit Timing when internal clock is selected Tc e Transfer clock 5 TE bit 1 UiC1 register poe o Data is set in the UiTB register TI bit in UiC1 register TSi Pulse stops because an H signal is applied to Pulse stops because the TE bit is set to 0 nnnnnhn UU HUUU 96090080067 606000069606 606000639 D UCoegser IR bit in SiTIC register Set to 0 by an interrupt request acknowledgement or by program i 20to2 The above timing diagram applies to the case where the register bits are set as follows To 2 Ta 7 2 1 fj The CKDIR bit in the UiMR register 0 internal clock n The CRD bit in the UICO register 0 CTS RTS enabled the CRS bit 0 CTS selected cca oiii M The CKPOL bit in the UiCO register 0 transmit data output at the
145. 6C 60 core processing unit Multiplier 16 bits x 16 bits gt 32 bits multiply and accumulate instruction 16 bits x 16 bits 32 bits 32 bits Number of basic instructions 91 Minimum instruction execution time 62 5 ns f BCLK 16 MHz VCC 2 7 V to 3 6 V Operating mode Single chip mode Memory ROM RAM Refer to Table 1 3 Product List data flash Clock Clock generation circuits Main clock subclock on chip oscillator 125 kHz circuits Oscillation stop detection Main clock oscillation stop and re oscillation detection function Frequency divider circuit Divide ratio selectable from 1 2 4 8 and 16 Low power consumption modes Wait mode stop mode I O ports Programmable I O CMOS I O ports 30 64 pin version ports 16 48 pin version selectable pull up resistor Nch open drain ports 3 Interrupts Number of interrupt vectors 70 External interrupt input 11 NMI INT x 2 key input x 8 64 pin version key input x 4 48 pin version Priority levels 7 levels Watchdog timer 15 bits x 1 with prescaler selectable reset start function DMA DMAC 4 channels cycle steal mode Trigger sources 43 Transfer modes 2 single transfer repeat transfer Timer Timer A 16 bit timer x 5 64 pin version 16 bit timer x 2 48 pin version Timer mode event counter mode one shot timer mode pulse width modulation PWM mode 16 bit timer x 3 48 pin version Timer m
146. 7 6 Pin Status in Stop Mode Single Chip Mode I O ports Retains status just prior to stop mode CLKOUT H RO1UH0197EJ0120 Rev 1 20 RENESAS Page 50 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 8 3 Exiting Stop Mode Stop mode is exited by a hardware reset NMI interrupt or peripheral function interrupt When the hardware reset or NMI interrupt is used to exit stop mode set bits ILVL2 to ILVLO in the interrupt control registers for the peripheral function interrupt to 000b interrupt disabled before setting the CM10 bit to 1 When the peripheral function interrupt is used to exit stop mode set the 10 bit to after the following settings are completed 1 Set bits ILVL2 to ILVLO in the interrupt control registers to decide the peripheral priority level of the peripheral function interrupt Set the interrupt priority levels of the interrupts not being used to exit stop mode to 0 by setting bits ILVL2 to ILVLO to 000b interrupt disabled 2 Setthe I flag to 1 3 Start operation of peripheral function being used to exit stop mode When exiting stop mode by the peripheral function interrupt the interrupt routine is performed after an interrupt request is generated and then the CPU clock is supplied again When stop mode is exited by the peripheral function interrupt or NMI interrupt the CPU clock source is as follows in accordance with the CPU clock source setting before the microcomputer
147. 7 bit in registers TACSO to TACS2 is set to 0 TCKO TCK1 enabled 5 Only i 0 or 1 in the 48 pin version Figure 12 12 TAiMR i 0 to 4 Register in Timer Mode RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 110 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 1 3 Event Counter Mode In event counter mode the timer counts pulses from an external device or overflows and underflows of other timers Timers A2 A3 and A4 can count two phase external signals 64 pin version only Table 12 3 lists Specifications in Event Counter Mode When Not Using Two Phase Pulse Signal Processing Figure 12 13 shows the TAiMR i 0 to 4 Register in Event Counter Mode When Not Using Two Phase Pulse Signal Processing Table 12 3 Specifications in Event Counter Mode When Not Using Two Phase Pulse Signal Processing Item Specification Count source External signals input to the 1 pin i 0 to 4 effective edge can be selected in a program Timer B2 underflows Timer Aj j i 1 except j 4 ifi 0 overflows or underflows Timer Ak k 2 i 1 except k 0 if i 4 overflows or underflows Count operation Increment or decrement can be selected by program When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without reloading Divide ratio 1 FFFFh 1 for increment
148. 7Fh 0080h LED Port Switch Register LEDCON 0081h 0082h Key Input Control Register 0 KICONO 0083h Key Input Control Register 1 KICON1 0084h Timer A I O Control Register TAIOCON 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00AO0h to OOFFh NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 18 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 4 Address 0100h SFR Information 4 1 Register Baseband Control Register Symbol BBCON After Reset 0101h Transmit Receive Reset Register BBTXRXRST 0102h Transmit Receive Mode Register 0 BBTXRXMODEO 0103h Transmit Receive Mode Register 1 BBTXRXMODE1 0104h Receive Frame Length Register BBRXFLEN 0105h Receive Data Counter Register BBRXCOUNT 0106h RSSI CCA Result Register BBRSSICCARSLT 0107h Transmit Receive Status Register 0 BBTXRXSTO 0108h Transmit Frame Length Register BBTXFLEN 0109h Transmit Receive Mode Register 2 BBTXRXMODE2 010Ah Transmit
149. 8 3 P8 6 P8 7 and P10 The total IOH peak for the following ports must be 40 mA max VCC 2 7 to 3 6 V or 4 mA max VCC 2 2 to 2 7 V ports P5 5 P5 7 P6 P7 4to P7 7 P8_0 and P8 1 4 64 version only 5 The main clock input frequency is fixed to 16 MHz for transceiver operation RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 287 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 3 Recommended Operating Conditions 2 2 1 VCC 2 2 to 3 6 V VSS 0 V and 20 to 85 C 40 to 85 C unless otherwise specified The ripple voltage must not excess Vr VCC and or dVr VCC dt Standard Parameter Typ Vr vcc Allowable ripple voltage VCC 3 0 V 0 3 Vp p dVr vcc dt Ripple voltage falling gradient VCC 3 0 V 0 3 V ms NOTE 1 The device is operationally guaranteed under these operating conditions VCC Vr vcc Figure 19 1 Ripple Waveform RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 288 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 4 A D Conversion Characteristics 1 Parameter Measuring Condition Resolution VREF AVCC VCC 10 Bits INL Integral non linearity 10bit VREF AVCC VCC 3 3 V ANO to AN7 3 LSB error input 4 VREF AVCC VCC 2 2 V ANO to AN7 6 LSB input 4 Absolute accuracy 10bit V
150. 99 0060h to 0063h Timer A4 100 to 103 0064h to 0067h Timer BO 104 to 107 0068h to 006Bh Timer B1 108 to 111 006Ch to 006Fh Timer B2 NOTES 112 to 115 0070h to 0073h 1 Address relative to address in INTB RON During 12C mode interrupts NACK and ACK comprise the interrupt source Use bits IFSR26 and IFSR27 in the IFSR2A register to select These interrupts cannot be disabled using the flag Bus collision detection During IE mode this bus collision detection constitutes the interrupt source During 12C Timers mode however a start condition or a stop condition detection constitutes the interrupt source R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 66 of 331 M16C 6B Group 9 Interrupt Table 9 3 Relocatable Vector Table 2 Software Interrupt Reference Number 0074h to 0077h 9 6 INT Interrupt 0078h to 007Bh 007Ch to 007Fh 00A4h to 00A7h 00A8h to 00ABh OOACh to OOAFh 15 Baseband Functionality OOBOh to 00B3h 00B4h to 00B7h Vector Address 1 Address L to Address INTO 116 to 119 INT1 120 to 123 Timer compare 2 124 to 127 DMA2 164 to 167 DMA3 168 to 171 Transmission complete 172 to 175 15 Baseband Functionality 11 DMAC Bank 0 reception complete IDLE 2 176 to 179 Bank 1 reception complete clock 180 to 183 regulator 3 Address fil
151. A D converter 64 pin version only When the WAIT instruction is executed after setting the CMO2 bit in the register to 1 peripheral function clock f1 turned off during wait mode or when the microcomputer is in low power consumption mode the f1 clock is turned off The fC32 clock is produced from the subclock and is used for timers A and B This clock can be used when the subclock is on fOCO S is used for timers A and B fOCO S can be used when the CM14 bit in the register is set to 0 125 kHz on chip oscillator oscillates Figure 7 8 shows the Peripheral Function Clock fC fOCO S Timer A Timer B UARTO to UART2 Main clock A D converter 64 pin version only Figure 7 8 Peripheral Function Clock 7 3 Clock Output Function During single chip mode the f8 32 or fC clock can be output from the CLKOUT pin Use bits 1 and CMOO in the CMO register to select RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 45 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 Power Control Normal operating mode wait mode and stop mode are provided as the power consumption control All mode states except wait mode and stop mode are called normal operating mode in this document 7 4 1 Normal Operating Mode Normal operating mode is further classified into seven modes In normal operating mode because the CPU clock and the peripheral function clocks both are on the CPU and the peripheral functio
152. ARTPin Clock Pin g P71 5 TAOIN RXD2 SCL2 51 39 NOD KIS a5 ag a Kia TAO0OUT TXD2 SDA2 53 P10 7 AN7 54 P10 6 Kip AN6 55 P105 KA AN5 56 P10 4 KIO AN4 57 P10 3 ANS 58 P10 2 AN2 59 P10 1 ANT 60 P10_0 ANO 61 43 P8 3 INTI 62 44 P82 INTO 63 47 64 48 NOTE 1 Some pins are used for communication with the debugger during debugging R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 9 of 331 M16C 6B Group 1 Overview 1 6 Pin Functions Table 1 6 Signal Name Digital power supply input Pin Functions 1 Pin Name VCC VSS1 VSS2 Description Apply 2 2 V to 3 6 V to the VCC pin Apply 0 V to pins VSS1 VSS2 AD power supply input AVCC 1 AVSS 1 Power input pins for the A D converter Connect the AVCC pin to VCC Connect the AVSS pin to VSS Reset input RESET Driving this pin Low resets the MCU CNVSS CNVSS Always input Low Main clock input XIN Main clock output Subclock input XOUT XCIN Subclock output XCOUT I O pins for the main clock oscillation circuit Connect a crystal oscillator between pins XIN and XOUT I O pins for a subclock oscillation circuit Connect a crystal oscillator between pins XCIN and XCOUT Clock output CLKOUT This pin outputs the clock having the same frequency as fC f8 or f32 INT interrupt input INTO INT1 Input pins for IN
153. AS Page 326 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 10 3 7 DMA Transfer In EW1 mode do not generate a DMA transfer while the FMRO0 bit in the FMRO register is set to 0 auto programming or auto erasing 20 10 3 8 Wait Mode To enter wait mode set the FMROI bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction 20 10 3 9 Stop Mode To enter stop mode set the FMROI bit to 0 CPU rewrite mode disabled and then disable DMA transfer before setting the CM10 bit in the register to 1 stop mode 20 10 3 10Software Command Observe the notes below when using the following commands Program Block erase Lock bit program Read lock bit status Block blank check The FMROO bit in the FMRO register indicates the status while executing these commands Do not execute other commands while the FMROO bit is 0 busy b Do not execute these commands while the CMO5 bit in the CMO register is 1 main clock stops c After executing the program block erase or lock bit program command perform a full status check per one command i e do not perform a single full status check after multiple commands are executed d Do not execute the program block erase lock bit program or block blank check command when either or both bits FMR06 and FMRO7 in the FMRO register are 1 completed in error e Do not execute these commands in the low current consumption read
154. BBTXIC BBRXOIC BBIDLEIC BBRX1IC BBCREGIC BBADFIC BBCCAIC BBPLLIC BBTXORIC BBRXOROIC BBRXOR 1IC Address 0045h 0046h 0047h 0048h 0049h 005Fh 004Ah 004Bh 004Ch 0069h 006Ah 004Dh 004Eh 0051h 0053h 004Fh 0052h 0054h 0050h 0055h to 0059h 005Ah to 005Ch 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Bit Symbol Interrupt priority level select bit Bit Name t3200 000 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 s 42 4 00000 Function Level 0 interrupt disabled F 0 Interrupt not requested EB Interrupt request bit 1 Interrupt requested b7 b4 1 The IR bit can only be reset by writing a 0 Do not write a 1 2 To rewrite the interrupt control register do so at a point that does not generate the interrupt request for that register 3 Use the IFSR2A register to select 4 64 pin version only Interrupt Control Register 1 No register bits If necessary set to 0 Read as undefined value RW RW R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 68 of 331 M16C 6B Group 9 Interrupt Interrupt Control Regist
155. Block Diagram MR2 Toggle Flip Flop 0104 1 1 however 41 1 0 i 1 however 0 4 Timer 2 4 Timer 4 Timer Timer AO bits in the registers TACSO to TACS2 bits in the TAPOFS register R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 101 of 331 M16C 6B Group 12 Timers 12 1 1 Timer A I O Function The TAOOUTSEL bit can be used to switch the pulse output of timer AO to the output from port P55 The TA1OUTSEL bit can be used to switch the pulse output of timer A1 to the output from port P57 When using the I O function of timers A2 to A4 in the 64 pin version set bits TA2EN TA3EN and TA4EN to 1 TAi i 2 to 4 I O enabled Timer A I O Control Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset DUCNHNNN TAIOCON 0084h 00h Bit Symbol Bit Name Function C NNNNILI pepe pe TA4IN pin TA4OUT pin 0 Disabled enable bit 1 Enabled eng ee i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cl Reserved bits Set to 0 NOTE 1 Reserved bit in the 48 pin version Set to 0 Figure 12 5 TAIOCON Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 102 of 331 Jul 21 2011 M16C 6B Group 12 Timers Timer Ai Mode
156. C n me lt D k 424 NESAS M16C 6B Group User s Manual Hardware RENESAS MCU M16C Family M16C 60 SERIES All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics www renesas com Rev 1 20 Jul 2011 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted he
157. C 6B Group 13 Serial Interface 13 1 1 Clock Synchronous Serial I O Mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data Table 13 1 lists the Clock Synchronous Serial I O Mode Specifications Table 13 2 lists Registers Used and Settings in Clock Synchronous Serial I O Mode Table 13 1 Clock Synchronous Serial I O Mode Specifications Item Specification Transfer data format Transfer data length 8 bits Transfer clock CKDIR bit in the register 0 internal clock fj 2 n 1 fj 1510 12510 f8SIO f82SIO setting value of UIBRG register 00h to FFh CKDIR bit 1 external clock input from CLKi pin Transmission reception control Selectable from CTS function RTS function or CTS RTS function disable Transmission start condition Before transmission starts satisfy the following requirements 1 The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in UiTB register If CTS function is selected input on the CTSi pin L Reception start condition Before reception starts satisfy the following requirements 1 The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present and dummy written in the UiTB register Interrupt request generation timing Fo
158. CA ED or RSSI The CCA ED or RSSI value can be switched by using the CCASEL bit in the BBTXRXMODEI register When reading the RSSI value the result corresponding the receive RAM bank specified with the RCVBANKSEL bit in the BBTXRXMODES register is read The read data is indicated by two s complement in dBm units example 9Eh is indicated as 98 dBm Also refer to 15 2 31 RSSI Offset Register RSSI CCA Result Register b7 b6 b5 b4 b3 b2 b1 bO T 1 1 NOTE T 1 1 Symbol Address BBRSSICCARSLT 0106h After Reset 00h Bit Symbol Bit Name Function RSSICCARSLT RSSI CCA result data 1 Indicates the result data of RSSI CCA ES 1 This bit corresponds to the receive RAM bank Figure 15 16 RSSI CCA Result Register Configuration R01UH0197EJ0120 Rev 1 20 434 NESAS Jul 21 2011 Page 213 of 331 M16C 6B Group 15 Baseband Functionality 15 2 8 Transmit Receive Status Register 0 This register stores the CCA check result in the CCA bit The CRC check result is stored in the CRC bit When reading this bit the CRC result corresponding to the receive RAM bank specified with the RCVBANKSEL bit in the BBTXRXMODES register is read The CSMA CA check result is stored in the CSMACA bit The TRNRCVSQC bit is used to store the check result on the completion of a transmit receive operation sequence CSMA CA transmission ACK reception
159. CVBANKSEL bit in BBTXRXMODES register is read Received frames are stored each 1 byte beginning with the start address Even if a received frame is less than 127 bytes it is stored beginning with the start address of receive RAM when the next frame reception starts The data in receive RAM can be read during reception In that case the address of the currently receiving data can be confirmed by reading the value of the BBRXCOUNT register Bits ADRSFILEN and LVLFILEN in the BBTXRXMODES3 register can be used to enable or disable the filter for frames to be captured Refer to 15 1 7 Filter Function for details Bits RCVBANKO and RCVBANKI in the BBTXRXSTO register can be used as the flags for transferring data in receive RAM These bits are automatically set to 1 received data present when reception starts After received data has been read by a program these bits are cleared to 0 reception enabled If frame reception restarts while these bits are set to 1 received data present a reception overrun interrupt is generated The RCVBANKST bit in the BBTXRXSTO register can be used to confirm whether the last received frame is in bank 0 or bank 1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 196 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 6 Transmit Frame Generator This function automatically generates and outputs transmit frames Figure 15 3 shows the Transmit Frame Structure PHR MPDU Max 127 bytes
160. EJ0120 Rev 1 20 ztENESAS Page 227 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 26 Time Stamp Registers These registers are for storing the timer value when frame reception is completed The count value on completion of reception is automatically stored in time stamp registers The time stamp value is retained until the next reception is completed When reading these registers the time stamp value corresponding to the receive RAM bank specified with the RCVBANKSEL bit in the BBTXRXMODES register is read Time Stamp Register 0 b15 b8 b7 b0 b7 b0 Symbol Address After Reset BBTSTAMPO 0131h 0130h 0000h Time stamp register 0 BBTSTAMPO Lower bits bits 15 to 0 of the 26 bit stamp value Time Stamp Register 1 b15 b8 b7 b0 b7 b0 Symbol Address After Reset BBTSTAMP1 0133h 0132h 0000h Time stamp register 1 BBTSTAMP1 Lower bits bits 25 to 16 of the 26 bit stamp value No register bits If necessary set to 0 Read as 0 1 These bits correspond to the receive RAM bank Figure 15 35 Timer Stamp Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 228 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 27 Timer Control Register The TIMEEN bit is used to control the count operation of the 26 bit timer Setting this bit to 1 enables the timer count Setting this bit to 0 stops the timer count and also initializes the timer count value to 0
161. ENESAS Page 23 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 9 Address SFR Information 9 1 Register After Reset UARTO Special Mode Register 4 UOSMR4 00h UARTO Special Mode Register 3 UOSMR3 000X0X0Xb UARTO Special Mode Register 2 UOSMR2 X0000000b UARTO Special Mode Register UOSMR X0000000b UARTO Transmit Receive Mode Register UOMR 00h UARTO Bit Rate Register UOBRG XXh UARTO Transmit Buffer Register UOTB XXh XXh UARTO Transmit Receive Control Register 0 uoco 00001000b UARTO Transmit Receive Control Register 1 UOC1 00XX0010b UARTO Receive Buffer Register UORB XXh XXh UART Transmit Receive Control Register 2 UCON X0000000b UART1 Special Mode Register 4 U1SMR4 00h UART1 Special Mode Register 3 U1SMR3 000X0X0Xb UART1 Special Mode Register 2 U1SMR2 X0000000b UART1 Special Mode Register U1SMR X0000000b UART1 Transmit Receive Mode Register U1MR 00h UART1 Bit Rate Register U1BRG XXh UART1 Transmit Buffer Register U1TB XXh XXh UART1 Transmit Receive Control Register 0 U1CO 00001000b UART1 Transmit Receive Control Register 1 U1C1 00XX0010b UART1 Receive Buffer Register U1RB XXh XXh UART2 Special M
162. Equipment Bus Input Output Infrared Data Association Least Significant Bit Most Significant Bit Non Connect Phase Locked Loop Pulse Width Modulation Subscriber Identity Module Universal Asynchronous Receiver Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners Table of Contents SER Page Ref rence uou dece e aec va eas a lactis Ug Le ccd leap uale eR B 1 1 siccata si bed Bed i P ar S er EF do Rete ebbe Aste 1 1 1 rac ES 1 1 1 1 APPHCAtlONS 1 1 2 Specifications esee abet ea and ae hte a ahd eh i ed eee ad 2 1 3 Product Mr 4 1 4 Block Diagram thea sends evassadesten ised sstesdinnd EE E 5 1 5 Pin Assignments ER RE Ba Sek eke ten dui Pm dood 6 1 6 Pin F unclions DR I DH REPERI PER REPERI 10 2 Central Processing Unit CPU 12 2 1 Data Registers RO RT R2 and 4 oec eene tie oerte p ce EEEE 12 2 2 Address Registers A0 and A eenei ne Tee INE E SERA Are HEIN E EET ENT WEE PERPE ERE IR 12 2 3 Frame Base Registers EB 5a PUER RERO BERE ERRARE ERE erben 13 2 4 Interrupt Table Register INTB emet e et eee deer teer tette rtt eme ho 13 2 5 Program Counter PG eei deo dee dedere ee rte 13 2 6 User Stack
163. F R01UH0197EJ0120 Rev 1 20 ztENESAS Page 122 of 331 Jul 21 2011 M16C 6B Group Timer B Count Source Select Register 0 Timer B Count Source Select Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TBCSO 01C8h 00h TBCS2 01E8h 00h Bit Symbol Bit Name Function o m o A c HTIMAB or f2TIMAB faTIMAB f82TIMAB f64TIMAB Do not set fOCO S fC32 Do not set TBi count source select bit 4 4 0000 000 gt 0 1 TCKO TCK1 enabled TCSO to TCS2 TBi count source option disabled specified bit 0 TCKO TCK1 disabled TCSO to TCS2 enabled f1TIMAB or f2TIMAB fSTIMAB fB2TIMAB TBj count source select bit f64TIMAB Do not set fOCO S fC32 Do not set 1 TCKO TCK1 enabled TCS4 to TCS6 TBj count source option disabled specified bit 0 TCKO TCK1 disabled TCS4 to TCS6 enabled TBCSO register i2 0 j2 1 TBCS2 register 3 j 4 NOTE 1 Set this value at the PCLKO bit in the PCLKR register Timer B Count Source Select Register 1 Timer B Count Source Select Register 3 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TBCS1 01C9h TBCS3 01E9h Bit Symbol Bit Name Function o 00 00g o HTIMAB or f2TIMAB f8TIMAB f8a2TIMAB f64TIMAB Do not set fOCO S fC32 Do not set TBi count source select bit 540000
164. Fh is read while reloading If the counter is read before it starts counting after a value is set in the TBi register while not counting the set value is read R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 319 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 7 2 2 Timer B Event Counter Mode The timer is stopped after reset Set the mode count source counter value and others using the TBiMR register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to count starts i 0 to 5 Always make sure the TBiMR register is modified while the TBiS bit is 0 count stops regardless of whether after reset or not While counting is in progress the counter value can be read out at any time by reading the TBi register However if this register is read at the same time the counter is reloaded the read value is always FFFFh If the TBi register is read after setting a value in it while not counting but before the counter starts counting the read value is the value set in the register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 320 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 8 Serial Interface 20 8 1 Clock Synchronous Serial I O 20 8 1 1 Transmission Reception When the RTS function is used with an external clock RTSi pin i 0 to 2 outputs L which informs the transmitting side that the MCU is ready for a receive operation The RTSi pin outputs when a receive operation starts
165. Figure 15 1 shows the Baseband Block Diagram Receive block Demodulation Frame length RF reception block control AGC control Frame control n i 1 storage I Sequence H number storage 1 16 bit CRC Address match detection circuit ACK frame generation Data bus Transmit block Modulation loci Peripheral functions Selector F length RF transmission Control registers BB interrupt control v ee N RE Clock XIN circuit regulator regulator regulator Figure 15 1 Baseband Block Diagram 15 1 2 Baseband Terminological Description Terms used in this chapter are shown below IDLE status Status where the RF regulator which is supplied to the internal RF block has started up stably RF regulator Dedicated on chip regulator for the RF block Clock regulator Dedicated on chip regulator for the XIN circuit to stabilize the reference 16 MHz CLK The power supply for the clock regulator is applied from the VCCRF pin RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 194 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 3 26 Bit Timer Three timer compare functions are implemented in the 26 bit timer When the timer value and the timer compare i i 0 to 2 value matches a timer compare i i 0 to 2 interrupt can be generated The clock which is the count source 16 MHz divided by 256 by using the prescaler is input to the timer Figure
166. GH select bit Input on TAIN is selected C 9 TB2 is selected TAS is selected TAO is selected 1 Set the port direction bits for the pins TA1IN to TA4IN to 0 input mode 2 Overflow or underflow Only underflow for timer B2 3 64 pin version only Figure 12 9 Registers ONSF and TRGSR ztENESAS RW Page 106 of 331 M16C 6B Group Clock Prescaler Reset FI b7 b6 b5 b4 b3 b2 bi b0 Symbol CPSRF Bit Symbol b6 b0 ag Address 0015h No register bits If necessary set to 0 Read as undefined value Clock prescaler reset flag After Reset OXXXXXXXb Function Setting this bit to 1 initializes the clock prescaler Read as 0 Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 After Reset Symbol TACSO TACS1 b7 b6 b5 b4 b3 b2 bi bO Bit Symbol Bit Name TAi count source select bit Address 01D0h 01D1h o N 0000 00 0070 20290292298 00h 00h Function HTIMAB or f2TIMAB f8TIMAB fa2TIMAB fe4TIMAB Do not set fOCO S fC32 Do not set TAi count source option specified bit 1 TCKO TCK1 enabled TCSO to TCS2 disabled 0 TCKO TCK1 disabled TCSO to TCS2 enabled TAj count source select bit TAj count source option specified bit TACSO register i 0 j 1 NOTE 1 Set this value at the PCLKO bit in the PCLKR register Figure 12 10 Registers CPSRF R01UH0197EJ0
167. I MR1 Set to 0 to use two phase pulse signal processing RW MR2 Set to 1 to use two phase pulse signal processing RW MR3 Set to 0 to use two phase pulse signal processing RW 0 Reload type 1 Free run type Two phase pulse signal processing 0 Normal processing operation TCK1 oa RW operation type select bit 1 2 1 Multiply by 4 processing operation TCKO Count operation type select bit RW 1 The TCK1 bit can be set only for Timer A3 mode register No matter how this bit is set Timers A2 and A4 always operate in normal processing mode and multiply by 4 processing mode respectively 2 To use two phase pulse signal processing following the register setting below Set the TAIP bit in the UDF register to 1 two phase pulse signal processing function enabled Set bits TAITGH and TAITGL in the TRGSR register to 00b pin input Set the port direction bits for and TAiOUT to 0 input mode 3 64 pin version only Figure 12 14 Registers TA2MR to TA4MR in Event Counter Mode When Using Two Phase Pulse Signal Processing with Timers A2 A3 and A4 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 114 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 1 4 One Shot Timer Mode In one shot timer mode the timer is activated only once by one trigger refer to Table 12 5 When the trigger occurs the timer starts up and continues operating for a given period Figure 12 15 shows the TAiMR i 0
168. INT1IC XX00X000b Timer Compare 2 Interrupt Control Register BBTIM2IC XXXXX000b NOTES X Undefined 1 The blank areas are reserved and cannot be accessed by users 2 Reserved area in the 48 pin version No access is allowed D o O OF OF OF OF olo RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 17 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 3 SFR Information 3 1 Address Register After Reset h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h Interrupt Control Register DM2IC XXXXX000b 006Ah DMAS3 Interrupt Control Register DMS3IC XXXXX000b 006Bh Transmit Complete Interrupt Control Register BBTXIC XXXXX000b 006Ch Bank 0 Receive Complete IDLE Interrupt Control Register BBRXOIC BBIDLEIC XXXXX000b 006Dh Bank 1 Receive Complete Clock Regulator Interrupt Control Register BBRX1IC BBCREGIC XXXXX000b 006Eh Address Filter Interrupt Control Register BBADFIC XXXXX000b 006Fh CCA Complete Interrupt Control Register BBCCAIC XXXXX000b 0070h PLL Lock Detection Interrupt Control Register BBPLLIC XXXXX000b 0071h Transmit Overrun Interrupt Control Register BBTXORIC XXXXX000b 0072h Receive Overrun 0 Interrupt Control Register BBRXOROIC XXXXX000b 0073h Receive Overrun 1 Interrupt Control Register BBRXOR1IC XXXXX000b 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 00
169. KDIR bit in the UTMR register 0 internal clock Figure 13 10 UCON Register RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 135 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Special Mode Register i 0 to 2 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ZEREQANN UOSMR U1SMR U2SMR 0247h 0257h 0267h X0000000b i i i O ee 2 2 mode select bit Ofer Wan nomode 1 PC mode Arbitration lost detect flag 0 Update per bit control bit 1 Update per byte 0 Stop condition detected 1 Bus busy flag 1 Start condition detected busy Bus collision detect sampling 0 Rising edge of transfer clock clock select bit 1 Underflow signal of Timer Aj ACSE Auto clear function select bit 0 No auto clear function of transmit enable bit 1 Auto clear at occurrence of bus collision SSS Transmit start condition 0 Not synchronized to RXDi select bit 1 Synchronized to RXDi 9 No register bit If necessary set to 0 Read as undefined value The BBS bit is set to 0 by writing a 0 in a program Writing a 1 has no effect Underflow signal of Timer A3 in UARTO underflow signal of Timer A4 in UART1 and underflow signal of Timer AO in UART2 When a transfer begins the SSS bit is set to 0 not synchronized to RXDi Figure 13 11 UOSMR to U2SMR Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 136 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Specia
170. KPOL Clock phases can be set in combination with the CKPH bit in the UiSMRS3 register UFORM Set to 0 TE Set to 1 to enable transmission reception TI Transmit buffer empty flag RE Set to 1 to enable reception RI Reception complete flag UilRS 1 Select UART2 transmit interrupt source UiRRM 1 UILCH UiERE Set to 0 0 to 7 Set to 0 0 to 7 CKPH Set to 0 Clock phases can be set in combination with the CKPOL bit in the UiCO register NODC Set to 0 0 2 4 t0 7 Set to 0 0 to 7 Set to 0 i Oto2 NOTES UOIRS U1IRS Select UARTO and UART1 transmit interrupt source UORRM U1RRM Set to 0 CLKMDO Invalid because CLKMD1 0 CLKMD1 RCSP 7 Set to 0 1 Set bits 4 and 5 in registers and U1C1 to 0 Bits UOIRS U1IRS UORRM and U1RRM are in the UCON register 2 The TXD2 pin is N channel open drain output No NCH bit in the U2CO register is assigned When write set to O 3 Setthe bits not listed above to 0 when writing to the registers in special mode 2 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 167 of 331 M16C 6B Group 13 Serial Interface 13 1 4 1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiCO register Make sure the transfer clock polarity and
171. L When a Software or Special Interrupt is Accepted Table 9 6 IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted Interrupt Sources Level Set to IPL Watchdog timer NMI oscillation stop and re oscillation detection low 7 voltage detection Software address match DBC single step Not changed R01UH0197EJ0120 Rev 1 20 ztENESAS Page 72 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 5 7 Saving Registers In the interrupt sequence the FLG register and PC are saved to the stack At this time the 4 high order bits of the PC and the 4 high order IPL and 8 low order bits in the FLG register 16 bits in total are saved to the stack first Next the 16 low order bits of the PC are saved Figure 9 7 shows the Stack Status Before and After Acceptance of Interrupt Request The other necessary registers must be saved in a program at the beginning of the interrupt routine Use the PUSHM instruction and all registers except SP can be saved with a single instruction Address Stack Address SP Content of previous stack 4 SP value before _ m Content of previous stack interrupt request is accepted SP New SP value PCL 8 low order bits of PC PCM 8 middle order bits of PC Content of previous stack Content of previous stack PCH 4 high order bits of PC FLGL 8 low order bits of FLG Oe FLGH 4 high order bits of FLG Stack status Stack status before interrupt r
172. NESAS Page 96 of 331 Jul 21 2011 M16C 6B Group 11 DMAC 11 5 Channel Priority and DMA Transfer Timing If several channels of DMAO to DMA3 are enabled and DMA transfer request signals are detected active in the same sampling period one period from a falling edge to the next falling edge of BCLK the DMAS bit on each channel is set to 1 DMA requested at the same time In this case the DMA requests are arbitrated according to the channel priority gt DMA1 gt DMA2 gt DMA3 The following describes DMAC operation when DMAO and DMA requests are detected active in the same sampling period Figure 11 8 shows an Example of DMA Transfer by External Factors In Figure 11 8 DMAO request having priority is received first to start a transfer when DMAO DMAI requests are generated simultaneously After one DMAO transfer is completed a bus access privilege is returned to the CPU When the CPU has completed one bus access a transfer starts After transfer is completed the bus access privilege is again returned to the CPU In addition DMA requests cannot be incremented since each channel has one DMAS bit Therefore when DMA requests as in Figure 11 8 occurs more than one time the DMAS bit is set to 0 after getting the bus access privilege The bus access privilege is returned to the CPU when one transfer is completed An example when DMA requests for external factors are detected active at t
173. NTO 3 INT1 P10 4 ANA KIO P10_5 AN5 KIT P7_3 TA1IN CTS2 RTS2 KI P10_0 ANO P10_1 AN1 P10_2 AN2 P10_3 AN3 P10_6 AN6 P ce esee e eo ss es T9 e T9 T5 N VSSRF2 VREGIN1 VSSRF3 VREGIN2 VSSRF1 VREGOUT1 VREGIN3 VSSRF4A RFIOP RFION VSSRF4B TESTION TESTIOP ANTSWCONT VREGOUT2 VSSRF5 P8 5 NMI AVSS VREF AVCC P8 6 XCOUT P8 7 XCIN VCC CNVSS VSS1 P5 5 LEDO TAO1OUT P5 7 CLKOUT LED1 TA11OUT RESET XOUT VSS2 XIN VREGOUT3 BY ART A ojo wy wo BY RT SR Aj gt wo O N A eo M16C 6B3 64VQFN top view wo A EO 8 E ia EI En g G E ES e N 24s 2222 P89 a0 te P6_4 CTST RTST CTSO CLKS1 VSSRF6 VREGIN4 P7 7 TASIN P7 6e TAS3OUT P6 5 CLK1 Pe 1 CLKO Pe O CTSO RTSO P7 5 TA2IN P8 1 TA4IN P7 4 TA2OUT P8 O TA4OUT P6 7 TXD1 SDA1 P6 6 RXD1 SCL1 P6 3 TXDO SDAO Pe 2 RXDO SCLO NOTES 1 N channel open drain output 2 Confirm the position of pin 1 by referring to Package Dimensions Figure 1 3 64 Assignment Top View R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 6 of 331 Jul 21 2011 M16C 6B Group 1 Overview P7_O TAOOOUT TXD2 SDA2Ki4 P5_7 CLKOUT LEDI TAI1OUT 7_1 2915 9 55 2 P8 5 NMI VREGIN1 gt VCC VSSRF3 gt P8_6 XCOUT VREGIN2 gt P8_7 XCIN M16C 6B4 VSSRF4A 48VQFN
174. PAN Coordinator Bit PANCORD Bit in BBTXRXMODE3 Register Automatic ACK Response Conditions Match with destination PANID Short Address BBSHORTAD Match with destination address Extended Address BBEXTENDAD3 0 x Match with destination PANID x Match with destination address Match with destination PANID Match with destination address x Match with x Match with destination PANID destination address Match with destination PANID x Match with destination PANID An ACK frame to be responded is shown in the following figure Frame length FL The length is set to 05h regardless of the setting value Sequence number The received sequence number is transmitted without changes SHR MPDU Preamble 00000000h S F D A7h Frameicontrol sequence number Figure 15 4 ACK Frame R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 201 of 331 M16C 6B Group 15 Baseband Functionality The timing for ACK response varies with nonbeacon mode and beacon mode Nonbeacon and beacon modes are selected by using the BEACON bit in the BBTXRXMODEO register In nonbeacn mode an ACK frame is transmitted 192 us after frame reception is completed In beacon mode period check begins for a 320us backoff period after frame reception starts If reception complete timing takes 192 us or more before the boundary of a ba
175. PM2 BBTSTAMPO BBTSTAMP1 PRCR BBTXFLEN stetit PRG2C PUR1 BBTXORIC PUR2 BBTXRXCON MMEMEMMMCCK R BBTXRXMODEO BBTXRXMODE1 RMADO to RMADOS 81 BBTXRXMODE2 BBTXRXMODES S 222 SORIC to S2RIC 68 EBTXRXBST eie bran eu PU MT n EM 209 SOTIC to S2TIC BBTXRXSTO 214 SARO to SAR3 BBTXRXST1 220 ry 68 T C TAO 104 CMO 38 Rez 68 GMO sss E non E Mp uc s TAOMR TAIMB Lice 118 we M C TA2MR to TAAMR CPSRF 107 122 CROD m 240 TABSR 105 122 TAGSO TACS T o id rn EE Pret rera 107 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 330 of 331 Jul 21 2011 M16C 6B Group TAGS TAIOCON TAPOFS TBO to TBS ii ss TBOG to TB2lG aa oid ert teen mei 68 TBOMR to TBSMR 121 124 125 to 5 TBCSO to TBCSS tern mne erts 123 jl TCRO to TCRS U OBONIG U1BONIG
176. Pointer USP and Interrupt Stack Pointer ISP seesseeseseseeeeeenennennrenne 13 2 7 Static Base Register SB cose qeu peer a i 13 2 8 Flag Register FLG SSPE E ETE Soie 13 2 8 1 Carry Flag C Flag e Eni Ei eR UR EUER 13 2 8 2 Debug Flag D Flag sce inui a ee deir abe He e heaves Uu i e Ed etus 13 2 8 3 Zero Flag Z Flag ut coal ake tial ache ah D Gee an Aen 13 2 8 4 Sign 5 5 1 cousine e tone teen re pee neto 13 2 8 5 Register Bank Select Flag B Flag eter ttbi eie 13 2 8 6 Overflow Flag Q Flag ic repeti ett ce Avoca cess esse ERR Eae db connie 13 2 8 7 Interrupt Enable Flag I Flag oreet rette pere DURER 13 2 8 8 Stack Pointer Select Flag U Flag esee nennen nnne nennen enne erret renes 14 2 8 9 Processor Interrupt Priority Level esee aite tiet bte ce ge EG ee ge ener reps 14 233 10 Reserved Space teens obe is i he Aa ion Sib 14 3 haat el tetti ttt AA tet oe Lecker 15 4 Special Function Registers enne nennen nnns nnns 16 5 nci I C TTE 30 5 1 Hardware Reset 2t aeter REPE REDE e E ER EE I e SERVO S ren Me 30 5 1 1 Reset on a Stable Supply Voltage esses ennemi en nennen tenerent enne 30 3 12 Pow r on Reset iiie cera eU DRE Eti tute em 30 2 2 Software Reset eene RR TRIER Cac oth WR Tee TANE e ER See aT ARE e ete 31 5 3 Waichdos Timer Reset
177. READO register is not latched After reading the BBTIMEREADO register its value is not updated even if this register is read again without reading the BBTIMEREADI register and the previously read value is read RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 195 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 4 Transmit RAM 127 bytes of transmit RAM is implemented exclusively for the baseband block The addresses are D100h to D17Eh Frames are transmitted each 1 byte of transmit RAM data beginning with the start address As the next frame transmission always begins with the start address even if transmit RAM data is less than 127 bytes write transmit RAM data from the start address If the internal transmit counter value is equal to or greater than the written address a transmission overrun interrupt request is generated and transmit processing is cancelled simultaneously The data written into transmit RAM can be read 15 1 5 Receive RAM 127 x 2 bytes banks 0 and 1 is implemented exclusively for the baseband block The addresses are D180h to D1FEh and read only After the baseband functions are enabled the storage of frames begins with receive RAM bank 0 and frames are stored in bank 0 or alternately for each reception The reception complete interrupt request corresponding to the bank is generated each time frame reception is completed When reading receive RAM the receive RAM data of the bank set by the R
178. REF AVCC VCC 3 3 V ANO to AN7 3 LSB input 4 VREF AVCC VCC 2 2 V ANO to AN7 6 LSB input 4 Tolerance level impedance 3 DNL Differential non linearity 4 1 LSB error Offset error 4 3 LSB Gain error 4 3 LSB tCONV 10 bit conversion time VREF AVCC VCC 3 3 V 2 69 us AD 16 MHz tSAMP Sampling time 0 94 us VREF Reference voltage VCC V VIA Analog input voltage 0 VREF V NOTES 1 Referenced to VREF AVCC VCC 3 3 V VSS 0 V at 20 to 85 C 40 to 85 C unless otherwise specified 2 SetfAD frequency as follows When VCC 3 2 to 3 6 V 2 MHz x lt 16 MHz When VCC 3 0 to 3 2 V 2 MHz lt 94AD lt 8 MHz When VCC 2 2 to 3 0 V 2 MHz lt AD x 4 MHz Use when VREF AVCC VCC The flash memory must not be rewritten For the pins other than the analog pin to be measured set them as input ports and connect to VSS Refer to Figure 19 2 A D Accuracy Measure Circuit Boo Analog input P5 to P10 AN One of the analog input pin P5 to P10 I O pins other than AN Figure 19 2 A D Accuracy Measure Circuit R01UHO197EJ0120 Rev 1 20 ztENESAS Page 289 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 5 Flash Memory Electrical Characteristics 1 Parameter Program and erase endurance 2 Other than data flash Standard Typ Data flash 2 word program time VCC 3 3 V at Topr 25 C Other than
179. RI Reception complete flag UilRS 1 Select the source of UARTi transmit interrupt UiRRM 1 UILCH UiERE Set to 0 0to3 7 Set to 0 ABSCS Select the sampling timing at which to detect a bus collision ACSE Set this bit to 1 to use the auto clear function of transmit enable bit SSS Select the transmit start condition 0to7 Set to 0 0107 Set to 0 0107 Set to 0 IFSR26 IFSR27 Set to 1 UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set to 0 CLKMDO Invalid because CLKMD1 0 CLKMD1 RCSP 7 Set to 0 0102 NOTES 1 Set bits 4 and 5 in registers and U1C1 to 0 Bits UOIRS U1IRS UORRM and U1RRM are in the register 2 The TXD2 is N channel open drain output No NCH bit in the U2CO register is assigned When write set to 0 3 Set the bits not listed above to 0 when writing to the registers in IE mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 170 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 1 The ABSCS Bit in the UiSMR Register Bus collision detect sampling clock select 0 to 2 If ABSCS 0 bus collision is determined at the rising edge of the transfer clock N Transfer clock ee 5 5 E ST DO D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi RXDi Trigger signal is applied to the TAjIN pin Timer Aj If ABSCS 1 bus collision is determined when timer Aj one shot timer mode underflows Timer Aj Timer A3 in UARTO Timer A4 in UART1 Timer AO in UA
180. RT A D Regis D17Eh CRC Input Register TRANSMIT_RAM_ END A D Regis 7Fh 80h Receive RAM RECIEVE_RAM_ START A D Regist FEh A D Regis RECIEVE RAM _ END A D Regis D1FFh D7FFh A D Regis FFFFFh Option Function Select Address OFS1 84 Blank columns are all reserved space No access is allowed 24 N SAS M16C 6B Gr 6 Group RO1UH0197EJ0120 RENESAS MCU Rev 1 20 Jul 21 2011 1 Overview 1 1 Features The M16C 6B Group microcomputers MCUs incorporate the M16C 60 Series CPU core and flash memory These MCUs also function as low power consumption transceivers which support near field communication 2 4 GHz band Integrating some of the physical PHY and MAC layers compliant to the IEEE802 15 4 standard the MUCs support various applications ranging from simple communication systems to mesh network systems 1 1 1 Applications Home automation Building automation Factory automation Wireless sensor networks RF remote controllers RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 1 of 331 Jul 21 2011 M16C 6B Group 1 Overview 1 2 Specifications Tables 1 1 and 1 2 list Specifications Outline Table 1 1 Specifications 1 Function Specification RF RF frequency 2405 MHz to 2480 MHz Reception 94 dBm sensitivity Transmission 0 dBm output level CPU Central M1
181. RT2 2 The ACSE Bit in the UiSMR Register Auto clear of transmit enable bit Transfer clock IW LET ESL 5 DO D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi 8 RXDi _ cuo IR bit in UiBCNIC and BCNIC register If ACSE bit 1 automatically clear when bus collision occurs the TE bit is cleared to 0 transmission disabled when the TE bit in UiC1 register IR bit in the UiBCNIC register 1 unmatching detected 3 The SSS Bit in the UISMR Register Transmit start condition select If SSS bit 0 the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met Transfer clock LAL LE LAL LP LL LU ST DO Di D2 D3 D4 05 D6 D7 D8 SP Transmit enable conditions are met If SSS bit 1 the serial interface starts sending data at the rising edge of NOTES 1 The falling edge of RXDi when IOPOL 0 the rising edge of RXDi when IOPOL 1 2 The transmit condition must be met before the falling edge of RXD The above diagram applies to the case where IOPOL 1 reversed i 0 to 2 Figure 13 35 Bus Collision Detect Function Related Bits R01UH0197EJ0120 Rev 1 20 ztENESAS Page 171 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 6 Special Mode 4 SIM Mode UART2 SIM interface devices can communicate in UART mode Both direct and inverse formats are available The TXD2 pin outputs a low level si
182. Register Status Name Reserved Definition Value after Reset Reserved Reserved Reserved Program status Terminated normally Terminated in error Erase status Terminated normally Terminated in error Reserved Sequencer status Busy Ready DO to D7 are the data buses read when the read status register command is executed Bits FMR07 SR5 and FMRO6 SR4 are set to 0 when the clear status register command is executed When the FMR07 SR5 or FMRO6 bit SR4 is set to 1 the program block erase lock bit program block blank check and read lock bit status commands are not accepted R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 274 of 331 M16C 6B Group 18 Flash Memory 18 3 7 Full Status Check If an error occurs when a program or erase operation is completed bits FMR06 and FMRO7 in the FMRO register are set to 1 indicating a specific error Therefore execution results can be confirmed by checking these status full status check Table 18 12 lists Errors and FMRO Register State Figure 18 13 shows a Full Status Check and Handling Procedure for Each Error Table 18 12 Errors and FMRO Register State FMR00 Register Status Register State FMRO7 bit SR5 bit FMRO6 bit SR4 bit Command Sequence error Error Occurrence Conditions Command is written incorrectly A value other than xxDOh or xxFFh is written in the se
183. SP as USP and ISP are each 16 bits wide The U flag is used to switch between USP and ISP 2 7 Static Base Register SB SB is a 16 bit register used for SB relative addressing 2 8 Flag Register FLG FLG is a 11 bit register indicating the CPU state 2 8 1 Carry Flag C Flag The C flag retains a carry borrow or shift out bit that has been generated by the arithmetic logic unit 2 8 2 Debug Flag D Flag The D flag is for debugging purpose only Set it to 0 2 8 3 Zero Flag Z Flag The Z flag is set to 1 when an arithmetic operation results in 0 otherwise to 0 2 8 4 Sign Flag S Flag The S flag is set to 1 when an arithmetic operation results in a negative value otherwise to 0 2 8 5 Register Bank Select Flag B Flag Register bank 0 is selected when the B flag is set to 0 Register bank 1 is selected when this flag is set to 1 2 8 6 Overflow Flag O Flag The O flag is set to 1 when an arithmetic operation results in an overflow otherwise to 0 2 8 7 Interrupt Enable Flag Flag The I flag enables maskable interrupts Maskable interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1 The I flag is set to O when an interrupt request is acknowledged R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 13 of 331 Jul 21 2011 M16C 6B Group 2 Central Processing Unit CPU 2 8 8 Stack Pointer Select Flag U Flag ISP is selected when the U flag is set to 0 USP is selected wh
184. Select the internal clock or external clock STPS Set to 0 PRY Set to 1 in direct format or 0 in inverse format PRYE Set to 1 IOPOL Set to 0 CLKO CLK1 Select the count source for the U2BRG register CRS Invalid because CRD 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Set to 0 CKPOL Set to 0 UFORM Set to 0 in direct format or 1 in inverse format TE Set to 1 to enable transmission TI Transmit buffer empty flag RE Set to 1 to enable reception RI Reception complete flag Set to 1 Set to 0 Set to 0 in direct format or 1 in inverse format Set to 1 Set to 0 Set to 0 Set to 0 NOTE Set to 0 1 Set the bits not listed above to 0 when writing to the registers in SIM mode R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 173 of 331 M16C 6B Group 13 Serial Interface 1 Transmit Timing Transfer clock 28 pd l l j l TE bit in 1 o 1 Data is written to the U2TB register NOTE 1 TI bit in U2C1 register Data is transferred from the U2TB register to the UART2 transmit register Parity bit is s GG GXXGX XY b WESS Parity error signal returned from receiving end RXD2 pin level 9 An L signal is applied from the FN SIM card due to a parity error 3 TXEPT bit in U2CO register IR bit i
185. Setting the RFSTOP bit to 1 enables the cancellation of processing during transmission reception CCA or calibration IDLE status after cancellation Processing such as the automatic ACK response and automatic reception switching functions are also cancelled The RFSTOP bit is automatically cleared to 0 However the setting value of each register is retained Setting the RFRESET bit to 1 initializes all baseband associated registers As all control signals are initialized communication is also cancelled as with the RFSTOP bit The RFRESET bit is automatically cleared to 0 This bit can also be set regardless of the value of the BBEN bit in the baseband control register Transmit Receive Reset Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset 0 BBTXRXRST 0101h 00h Bit Symbol Bit Name Function RW Ww RFSTOP RF communication stop bit Stops RF communication R RFRESET RF reset bit Resets baseband associated registers b3 b2 Reserved bits Set to 0 b7 b4 No register bits If necessary set to 0 Read as 0 Figure 15 11 Transmit Receive Reset Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 209 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 3 Transmit Receive Mode Register 0 To execute CCA or ED set the CCACOND bit to 1 The AUTOACKEN bit can be used to select whether to perform automatic ACK response operation after reception is completed The
186. T Clock Asynchronous Serial I O Mode 20 8 2 1 Transmission Reception When the RTS function is used with an external clock RTSi pin i 0 to 2 outputs L which informs the transmitting side that the MCU is ready for a receive operation The RTSi pin outputs H when a receive operation starts Therefore a transmit timing and receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting side The RTS function is disabled when an internal clock is selected 20 8 2 2 Transmission If an external clock is selected the following conditions must be met while the external clock is held H when the CKPOL bit in the UiCO register i 0 to 2 is set to 0 transmit data output at the falling edge and receive data input at the rising edge of the serial clock or while the external clock is held when the CKPOL bit is set to 1 transmit data output at the rising edge and receive data input at the falling edge of the serial clock The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in the UiTB register If CTS function is selected input on the CTSi pin L 20 8 3 Special Mode 1 I2C Mode When generating start stop and restart conditions set the STSPSEL bit in the UiSMR4 register i 0 to 2 to 0 and wait for more than half cycle of the transfer clock before setting each condition generation bit STAREQ RSTAREQ a
187. T interrupt NMI interrupt input NMI Input pin for NMI interrupt Key input interrupt input KIO to 1 to KI7 Input pins for key input interrupt Timer A TAOOUT to TA1OUT TA2OUT to TA4OUT 1 Timer AO to 4 I O pins TAOOUT is an N channel open drain output pin TAOIN to TA1IN TA2IN to TA4IN 1 Timer 0 to 4 I O input pins Serial interface CTSO to CTS2 Input pins to control data transmission RTSO to RTS2 Output pins to control data reception CLKO to CLK2 Transfer clock I O pins RXDO to RXD2 Serial data input pins TXDO to TXD2 Serial data output pins 2 CLKS1 Output pin for transfer clock multiple pin output function Reference voltage input 1 VREF Reference voltage input pin for the A D converter A D converter 1 ANO to AN7 Analog input pins for the A D converter I O ports NOTES P5 5 P5 7 P6 0to P6 7 P7 0to P7 3 P7_4 to P7 7 1 P8 0 1 8 1 1 P8 2 P8 3 P8 5to 7 P10_0 to P10 7 1 1 Available only in the 64 pin version 2 TXD2 is an N channel open drain output pin TXDO and TXD1 be selected as CMOS output pins or N channel open drain output pins by a program CMOS O ports A direction register determines whether each pin is used as an input port or an output port A pull up resistor may be enabled or disabled for input ports in 4 bit units However P7
188. TO reception ACKO UART2 transmission 100b UART2 transmission UART2 reception ACK2 101b UART2 reception ACK2 A D conversion 64 pin version only 110b A D conversion 64 pin version only UART1 reception ACK1 111b UART1 reception ACK1 UART1 transmission 0000b UART1 transmission 0001b 0010b 0011b 0100b 0101b 0110b 01116 X indicates 0 1 indicates no setting Figure 11 3 Registers DMOSL to DMSSL 2 11XXXb X indicates 0 or 1 indicates no setting R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 90 of 331 M16C 6B Group 11 DMAC DMAi Control Register i 0 to 3 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset DMOCON 018Ch 00000X00b DM1CON 019Ch 00000X00b DM2CON 01ACh 00000X00b DM3CON 01BCh 00000X00b Bit Symbol Bit Name Function 0 16 bits DMBIT Transfer unit bit select bit 1 8 bits Repeat transfer mode select 0 Single transfer bit 1 Repeat transfer 0 DMA not requested 1 DMA requested 0 Disabled DMAE DMA enable bit 1 Enabled Source address direction 0 Fixed select bit 1 Forward Destination address direction 0 Fixed select bit 1 Forward ry No register bits If necessary set to 0 Read as 0 m DMAS DMA request bit b7 b6 1 The DMAS bit can be set to 0 by writing a 0 in a program This bit remains unchanged even
189. Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 JIn Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2011 Renesas Electronics Corporation All rights reserved Colophon 1 1 M16C 6B Group 2 NE S AS Renesas Electronics Corporation R01UH0197EJO120
190. The CRD bit 0 CRS bit 1 RTS function is selected CTSi RTSi pin is RTS function 13 1 2 7 CTS RTS Separate Function UARTO This function separates CTSO RTSO outputs RTSO from the P6 0 pin and inputs CTSO from the P6 4 pin To use this function set the register bits as shown below The CRD bit in the UOCO register 0 enable CTS RTS of UARTO The CRS bit in the register 1 output RTS of UARTO The CRD bit in the U1CO register 0 enable CTS RTS of UART1 The CRS bit in the U1CO register 0 input CTS of UARTI The RCSP bit in the UCON register 1 inputs CTSO from the P6 4 pin The CLKMDI bit in register 0 CLKSI not used Note that when using the CTS RTS separate function CTS RTS of UARTI function cannot be used Microcomputer TXDO P6 3 RXDO P6 2 RTSO P6 0 CTS0 P6 4 Figure 13 26 CTS RTS Separate Function RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 155 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 3 Special Mode 1 I2C mode I2C mode is provided for use as a simplified I2C interface compatible mode Table 13 10 lists the specifications of I2C mode Tables 13 11 and 13 12 list Registers Used and Settings in I2C Mode Table 13 13 lists the I2C Mode Functions Figure 13 27 shows the I2C Mode Block Diagram Figure 13 28 shows Transfer to UiRB Register and Interrupt Timing As shown in Table 13 13 the micro
191. Timing CKPH 1 in Slave Mode External Clock RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 169 of 331 Jul 21 2011 13 Serial Interface M16C 6B Group 13 Serial Interface 13 1 5 Special Mode 3 IE mode In this mode one bit of IEBus is approximated with one byte of UART mode waveform Table 13 17 lists the Registers Used and Settings in IE Mode Figure 13 35 shows the Bus Collision Detect Function Related Bits If the TXDi pin i 0 to 2 output level and pin input level do not match a UARTI bus collision detect interrupt request is generated Use bits IFSR26 and IFSR27 in the IFSR2A register to enable the UARTO UARTI bus collision detect function Table 13 17 Registers Used and Settings in IE Mode Register i Function 0to8 Set transmission data 0 to 8 Reception data can be read OER FER PER SUM Error flag 0107 Set a bit rate SMD2 to SMDO Set to 110b CKDIR Select the internal clock or external clock STPS Set to 0 PRY Invalid because PRYE 0 PRYE Set to 0 IOPOL Select the TXD and RXD input output polarity CLK1 CLKO Select the count source for the UiBRG register CRS Invalid because CRD 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select TXDi pin output format 2 CKPOL Set to 0 UFORM Set to 0 TE Set to 1 to enable transmission TI Transmit buffer empty flag RE Set to 1 to enable reception
192. UTPWR 16 h 0 dBm typ dBm 3rd harmonics TXOUTPWR 16 h 0 dBm typ dBm Spurious emission 30 to 1 000 MHz 1 to 12 75 GHz 1 8 to 1 9 GHz 5 15 to 5 3 GHz TXOUTPWR 16 h 0 dBm typ dBm dBm dBm dBm Error vector magnitude EVM 1 000 chips 35 or less Power spectral density Absolute limit f fc gt 3 5 MHz 30 or less dBm Relative limit f fc gt 3 5 MHz 20 or less dB Frequency tolerance min Within 40 ppm Frequency tolerance max Table 19 29 Transceiver Reception Characteristics Within 40 VCC VCCRF 3 3 V VSS 0 V at 25 C unless otherwise specified Parameter Supply voltage Measuring Condition Standard IEEE802 15 4 Typ standard ppm RF input frequency Receiver sensitivity PER 1 PSDU length 20 octets 85 or less Maximum input level 20 or more Adjacent channel rejection 5 MHz 5 MHz PER 1 Prf 82 dBm 0 or more Alternate channel rejection 10 MHz 10 MHz PER 1 Prf 82 dBm 30 or more Rejection gt 15 MHz lt 15 MHz PER 1 Prf 82 dBm Spurious emission 30 to 1 000 MHz 1 to 12 75 GHz Symbol error tolerance 80 or less RSSI range 40 or more RSSI accuracy Within 6
193. VCC 0 3 V RF I O pins RFIOP RFION 0 3 to 2 1 V VTESTIO Test ports TESTIOP TESTION 0 3 to 2 1 V VANA 1 5 V analog supply VREGIN1 to VREGIN4 0 3 to 2 1 V VXINOUT Main clock I O XIN XOUT 0 3 to 2 1 V Pd Power dissipation 40 C lt lt 85 C 300 mW Topr Operating ambient When the microcomputer is 20 to 85 40 to 85 C temperature operating Flash program erase 0 to 60 Tstg Storage temperature 65 to 150 NOTE 1 64 version only R01UH0197EJ0120 Rev 1 20 ztENESAS Page 286 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 2 Recommended Operating Conditions 1 2 1 Standard P arameter Min Typ Max Digital supply VCC voltage Analog supply VCCRF AVCC 4 voltage Supply voltage VSS1 VSS2 AVSS 4 VSSRF VSSRF1 to VSSRF6 H input voltage RESET CNVSS P5 5 P5 7 P6_0 to P6 7 P7 2 P7 3 P7_4 to P7 7 4 P8 0 4 P8 1 4 P8 2 P8 3 P8 6 P8 7 P10 Oto P10 7 4 P70 P7 1 P8 5 L input voltage RESET CNVSS P5 5 P5 7 P6 0 to P6 7 P7 2 P7 3 P7 4to P7 7 4 P8 0 4 P8 1 4 P8 2 P8 3 P8 6 P8 7 P10 0to P10 7 4 P70 P7 1 P8 5 IOH peak H peak output P5 5 P5 7 P6 0to P6 7 P7 2 VCC 2 7 current P7 3 P7_4 to P7_7 4 8 0 4 to3 6V P8_1 4 P8 2 P8_3 P8 6 P8 7 VCC 2 2 P10 0 to P10 7 4 ANTSWCONT to 2 7 V H average output P5 5 P5 7 P6 0 to P6 7 P7 2 VCC 2 7 current P73 P7 4toP7 70 P8 04 to3 6V
194. XRXRST register CSMA Control Register 0 b7 b6 b5 b4 b2 bi b0 Symbol Address After Reset BBCSMACONO 010Dh 00h TI 0 No action CSMAST Auto CSMA CA start bit 1 Automatic CSMA CA start Auto transmit bit after 0 No action CSMATRNST 5 1 Transmit processing after CSMA CA No register bits If necessary set to 0 Read as undefined value Figure 15 23 CSMA Control Register 0 Configuration 15 2 15 CCA Threshold Level Set Register This register is used to set the threshold level for CCA check Set the value to two s complement in dBm units example 9Eh is indicated as 98 dBm The value set in the CCA level threshold set register is compared with the value to be stored in the RSSI CCA result register the value added with the offset value set in the RSSI offset register CCA Threshold Level Set Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After reset BBCCAVTH 010Eh 00h Bit Symbol Bit Name Function CCAVTH CCA threshold Sets the threshold level of CCA Figure 15 24 CCA Threshold Level Set Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 219 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 16 Transmit Receive Status Register 1 The UNLOCKST bit can be used to check whether a PLL unlock has occurred during recept
195. ag nterrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area NOTE 1 These registers comprise a register bank There are two sets of register banks Figure 2 1 Central Processing Unit Register 2 1 Data Registers R0 R1 R2 and R3 The RO R1 R2 and R3 are 16 bit registers used for transfer arithmetic and logic operations RO and R1 can be split into high order ROH R1H and low order bits ROL R 1L to be used separately as 8 bit data registers RO can be combined with R2 and used as a 32 bit data register R2R0 The same applies to R3R1 2 2 Address Registers A0 and A1 AO and AI 16 bit registers used for AO A1 indirect addressing AO A1 relative addressing transfer arithmetic and logic operations AO can be combined with A1 and used as 32 bit address register A1 AO R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 12 of 331 Jul 21 2011 M16C 6B Group 2 Central Processing Unit CPU 2 3 Frame Base Registers FB FB is configured with 16 bits and is used for FB relative addressing 2 4 Interrupt Table Register INTB INTB is a 20 bit register indicating the start address of an relocatable interrupt vector table 2 5 Program Counter PC PC is 20 bits wide and indicates the address of the next instruction to be executed 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP The stack pointers
196. alling edge of the 9th bit of clock IFSR26 ISFR27 Set to 1 Set to 1 i Oto2 UOIRS U1IRS Invalid Invalid 2 Set to 0 Set to 0 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 159 of 331 M16C 6B Group Table 13 13 Function Factor of interrupt number 6 7 and 10 1 5 7 I C Mode Functions Clock Synchronous Serial Mode SMD2 to SMDO 001b 0 13 Serial Interface 2 Mode SMD2 to SMDO 010b IICM 1 IICM2 0 NACK ACK interrupt IICM2 1 UART transmit receive interrupt CKPH 0 CKPH 1 CKPH 0 No clock delay Clock delay Start condition detection or stop condition Refer to Table 13 14 STSPSEL Bit Fun No clock delay detection ctions CKPH 1 Clock delay Factor of interrupt number 15 17 and 19 1 6 UARTI transmission Transmission started or completed selected by UilRS No acknowledgment detection NACK Rising edge of SCLi 9th bit UARTI transmission Rising edge of SCLi 9th bit UARTI transmission Falling edge of SCLi next to the 9th bit Factor of interrupt number 16 18 and 20 1 6 UARTi reception When 8th bit received CKPOL 0 rising edge CKPOL 1 falling edge Acknowledgment detection ACK Rising edge of SCLi 9th bit UARTI reception Falling edge of SCLi 9th bit Timing for transferring data from the UART reception shift regist
197. an be interchanged RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 237 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 3 5 Baseband Startup Procedure Example Set 1 baseband functions enabled in the BBEN bit in the BBCON register Set Olh 1 ms in the BBIDLEWAIT register Set 1 IDLE interrupt in the BANKOINTSEL bit in the BBTXRXMODEF4 register Set 1 RF power ON in the RFPWRON bit in the BBRFCON register and 1 XIN power ON in the XINPWRON bit Allow a delay until the IDLE interrupt is generated delay until the wait time set in the BBIDLEWAIT register has elapsed from step 2 Baseband Shutdown Procedure Example Set 0 OFF in the RFPWRON bit in the BBRFCON register Set 0 baseband functions disabled in the BBEN bit in the BBCON register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 238 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 3 7 Examples of Automatic Transmit and Receive Operations 15 3 7 1 Transmission Set the AUTORCVO bit in the BBTXRXMODEO register 1 automatic reception switching enabled 15 3 7 2 Reception Set the AUTORCV 1 bit in the BBTXRXMODEO register 1 automatic reception switching enabled RX IDLE 15 3 7 3 Set the AUTOACK bit in the BBTXRXMODEO register 1 automatic ACK enabled RX IDLE TX ACK IDLE ACK requested RX IDLE No ACK request Set the AUTOACK bit in the BBTXRXMODEO register 1 automatic ACK enabled
198. an be used to enable or disable the address filter for frames to be captured While the address filer is enabled frames other than those under the following address filter requirements are not stored in receive RAM Also a bank 0 or reception complete interrupt request is not generated While the address filter is disabled all receive frames are captured When all frames have been received a bank 0 or 1 reception complete interrupt is generated 15 1 7 2 Address Filter Requirements If a destination PAN identifier is included in the frame it should match the BBPANID register or FFFFh If a destination short address is included in the frame it should match the BBSHORTAD register or FFFFh If a destination extended address is included in the frame it should match registers BBENXTENDADO to BBENXTENDAD3 If the frame type is a beacon frame and the BBPANID register is not set to FFFFh the source PAN identifier should match the BBPANID register When this register is set to FFFFh all receive frames are captured If the frame type is a data frame or MAC command frame and only the source addressing filed is included the source PAN identifier should match the BBPANID register when the PANCORD bit in the BBTXRXMODE3 register is set to 1 PAN coordinator If the addressing fields and PAN identifier fields of the source and destination are not included only an ACK frame can be received ACK frame requirements frame type ACK encrypt bit 0 an
199. and codes and data to even addresses Figure 18 11 Flow Chart of the Read Lock Bit Status Command R01UH0197EJ0120 Rev 1 20 ztENESAS Page 271 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 4 8 Block Blank Check The block blank check command checks whether or not a specified block is blank state after erase By writing xx25h in the first bus cycle and xxDOh in the second bus cycle to the highest order even address of a block the check result is stored in the FMRO7 bit in the FMRO register Read the FMRO7 bit after the FMROO bit in the FMRO register is set to 1 ready Do not execute other commands while the FMROO bit is 0 The block blank check command is valid for unlocked blocks If the block blank check command is executed to a block whose lock bit is 0 locked the FMRO7 bit SR5 is set to 1 not blank regardless of the FMRO2 bit state Figure 18 12 shows a Flow Chart of the Block Blank Check Command Programming Write xxDOh to the highest order block address Not blank 1 Write command codes and data to even addresses NOTE Figure 18 12 Flow Chart of the Block Blank Check Command When the block is not blank as a result of the block blank check execute the clear status register command before executing other software commands Do not use the block blank check command to confirm whether the blank erase command has been completed normally If there is a possibility that the blank erase command has
200. and transmits a frame after automatically adding the result which operated up to the BBTXFLEN register value 2 address to the last 2 bytes of the transmit frame By setting the NOCRC bit in the BBTXRXMODE2 register to 1 automatic CRC disabled data in transmit RAM can be transmitted as CRC data instead of the CRC result For reception the CRC circuit starts CRC operation from the start address of receive RAM and stores the result which operated up to the BBRXFLEN register value 2 address and the result which compared with the CRC data of the last 2 bytes of the received frame in the CRC bit in the BBTXRXSTO register The CRC data of the received frame is stored in receive RAM RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 200 of 331 Jul 21 2011 Table 15 2 M16C 6B Group 15 1 10 Automatic ACK Response Function 15 Baseband Functionality After frame reception is completed an ACK can be automatically responded by using the AUTOACKEN bit in the BBTXRXMODEO register The conditions for automatic ACK response is automatically resolved in hardware by using received frame control bits CRC result Address filter enabled Frame control bits Frame types Frame control bit ACK request Frame control bits Frame Control b11 b10 b15 Received frame and the CRC result match b2 b0 001b or 011b data frame or MAC command frame b5 1 Requested b6 b11 b10 b15 and b14 refer to Table 15 2
201. any interrupt after disabling that interrupt be careful with the instruction to be used Changing any bit other than the IR bit When interrupts corresponding to the register occur the IR bit may not become 1 interrupt requested and the interrupts may be ignored If this causes any troubles use any of the following instructions to change registers Instruction AND OR BCLR or BSET Changing the IR bit When the BTSTC instruction is used the IR bit may not always be cleared to 0 interrupt not requested Therefore be sure to use the MOV instruction to clear the IR bit c When using the I flag to disable an interrupt set the I flag while referring to the sample program fragments shown below Refer to b for details about rewriting the interrupt control registers in the sample program fragments Examples 1 through 3 show how to prevent the I flag from being set to 1 interrupt enabled before the interrupt control register is rewritten owing to the effects of the internal bus and the instruction queue buffer Example 1 Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT SWITCHI FCLR I Disable interrupts AND B 00H 0055H Set the TAOIC register to NOP NOP FSET I Enable interrupts The number of the NOP instructions is as follows PM20 1 1 wait 2 PM20 0 2 waits 3 when using the HOLD function 4 Example 2 Using the dummy read to keep t
202. are commands Program ROM 1 program ROM 2 and data flash can be rewritten with the microcomputer mounted on a board without using a ROM programmer The program and block erase commands are executed only in each block area of program ROM 1 program ROM 2 and data flash Erase write 0 EWO mode and erase write 1 EW1 mode are provided as CPU rewrite mode Table 18 9 lists Differences between EWO Mode and EW1 Mode Table 18 9 Differences between EWO Mode and EW1 Mode EWO Mode EW1 Mode Operating mode Single chip mode Single chip mode Rewrite control program allocatable area Program ROM 1 Program ROM 2 Program ROM 1 Program ROM 2 Rewrite control program executable area The rewrite control program must be transferred to internal RAM before being executed 2 The rewrite control program can be executed in program ROM 1 program ROM 2 Rewritable area Program ROM 1 Program ROM 2 Data flash Program ROM 1 program ROM 2 and data flash excluding blocks with the rewrite control program Software command restriction None Program and block erase commands cannot be executed in a block having the rewrite control program Read status register command cannot be used Mode after program or erase Read status register mode Read array mode CPU state during auto write and auto erase Operating Maintains hold state I O ports maintains the state befo
203. as Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equip
204. ate Function The watchdog timer starts counting after a write instruction to this register Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset WDC 037Fh OOXXXXXXb Bit Symbol Bit Name Function i 1 1 4 Higher order bits of watchdog timer L L L L 4 J L No register bit If necessary set to 0 Read as 0 Reserved bit Set to 0 0 Divided by 16 Prescaler select bit 1 Divided by 128 Figure 10 2 Registers WDTR WDTS and WDC R01UH0197EJ0120 Rev 1 20 ztENESAS Page 83 of 331 Jul 21 2011 M16C 6B Group 10 Watchdog Timer Count Source Protection Mode Register b7 b6 b5 b4 b3 b2 bt b0 Symbol Address After Reset jojojoJo o o o csen 037Ch ooh b6 b0 Reserved bits Set to 0 RW CSPRO Count source protection mode 0 Count source protection mode disabled RW select bit 2 1 Count source protection mode enabled 1 When a 0 is written to the CSPROINI bit in the OFS1 address 10000000b is set after reset 2 Write a 0 and then a 1 to set the CSPRO bit to 1 0 cannot be set in a program Option Function Select Address b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset 1 T FFFFFh FFh Bit Symbol Bit Name Function 0 Watchdog timer starts automatically Watchdog timer start select after reset 1 Watchdog timer is in a stopped state after reset 0 ROM code prot
205. be written to the DMAS bit when 1 is written to the DMAE bit In this way the state of the DMAS bit immediately before being written can be maintained Similarly when writing to the DMAE bit with a read modify write instruction 1 should be written to the DMAS bit in order to maintain a DMA request which is generated during execution 2 Read the TCRi register to verify whether the DMAi is in initial state If the read value is equal to a value which was written to the TCRi register before DMA transfer start the is in initial state In the case a DMA request occurs after writing to the DMAE bit the read value is a value written to the TCRi register minus one If the read value is a value in the middle of transfer the DMA i 15 not in initial state RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 314 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 7 Timers 20 7 1 Timer A 20 7 1 1 Timer A Timer Mode The timer is stopped after reset Set the mode count source counter value and others using registers TAIMR TAi TACSO to TACS2 and TAPOFS before setting the TAIS bit in the TABSR register to 1 count starts 1 0 to 4 Always make sure registers TAiMR TACSO to TACS2 and TAPOFS are modified while the TAiS bit is 0 count stops regardless of whether after reset or not While counting is in progress the counter value can be read out at any time by reading the TAi register However if the counter is read at the same time
206. by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set as follows The PRYE bit in the UiMR register 0 parity disabled The STPS bit in the UIMR register 0 1 stop bit The CRD bit in the UiCO register 0 CTSi RTSi enabled and the CRS bit 1 RTSi selected i Oto2 Figure 13 22 Receive Timing in UART Mode 13 1 2 1 Bit Rate In UART mode the frequency set by the UiBRG register i 0 to 2 divided by 16 become bit rates Table 13 9 lists an Example of Bit Rates and Settings Table 13 9 Example of Bit Rates and Settings Bit Rate bps Count Source of UiBRG Peripheral Function Clock 16 MHz Set Value of UiBRG n 193 67 bps 1 33h 5 19h R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 152 of 331 M16C 6B Group 13 Serial Interface 13 1 2 2 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode follow the procedures below Resetting the UiRB register i 0 to 2 1 Set the RE bit in the UiC1 register to 0 reception disabled 2 Set the RE bit in the UiC1 register to 1 reception enabled Resetting the UiTB register i 0 to 2 1 Set bits SMD2 to SMDO in the UiMR register to 000b serial interface disabled 2 Reset bits SMD2 to SMDO in the UiMR
207. c e bec rs leet doeet rin 224 15 2 22 Short Address Register eidem orreee rette Dd ep pee 225 15 2 23 Extended Address Register eee eee ttem nee cio KEE EE E EEEE 225 15 2524 Timer Read Out Registet eco oet pU UR NUR NE geret Semper tests 226 15 2 25 Timer Compare i 1 0 to 2 Register eene nennen nennen nennen 227 15 2 267 Time Stamp Registers 4s eodein a etd e ede ear piede oo eene eis 228 15 2 27 Timer Control Register sinice nisi sese eet IP e ERR p ERE Rp ETHER ERE EORR 229 15 2 28 Backoff Period Register oe ete et e repite Sos chaos tees Ie SE CREE E 229 15 2 29 PLL Division Registers eene eet teeth qum dived ab RR 230 15 2 30 Transmit Output Power Register enr en nein 231 15 22 31 RSSI Offset Register zs teo oe dre enini enu em aeo decte d igo trm trees 232 15 2 32 Verification Mode Set Register cesoie rierren ee eserse nienie erekere seki ecetet trennen nennen 233 15 2 33 IDLE Walt Set Register iecore oE EEEE EEE ia et ette REPRE ERR ES EEE 234 15 2 34 ANTSW Output Timing Set Register eee E EEE EEEO nE EE ESE rs 234 15 235 RF Initial Set Register iecit Hons EIL EEE E R EE 235 15 3 Control Sequence eure epe re qtti Fu eod tete Oeo eden 236 15 3 1 Transmission Procedure Example sese ener nre nre entren nennen en 236 15 3 2 Reception Procedure Pxamiple e epe eee tee ete en te os 236 1533 CCA Procedure Examp
208. ccess to the internal flash memory is disabled when the FMSTP bit is set to 1 flash memory operation stopped Set the FMSTP bit by a program located in the RAM Set the FMSTP bit to 1 under the following condition e A flash memory access error occurs while erasing or programming in EWO mode the FMROO bit does not switch back to 1 ready Use the following steps to rewrite the FMSTP bit To stop the flash memory 1 Setthe FMSTP bit to 1 2 Wait the wait time to stabilize flash memory circuit tps To restart the flash memory 1 Set the FMSTP bit to 0 2 Wait the wait time to stabilize flash memory circuit tps The FMSTP bit is valid when the FMROI bit is 1 CPU rewrite mode If the FMROI bit is 0 although the FMSTP bit can be set to 1 by writing 1 the flash memory is neither placed in low power mode nor initialized When the FMR23 bit is set to 1 low current consumption read mode enabled do not set the FMSTP bit in the FMRO register to 1 flash memory operation stopped Also when the FMSTP bit is set to 1 do not set the FMR23 bit to 1 FMR06 Program status flag b6 This bit indicates the auto program operation state Condition to become 0 Execute the clear status command Condition to become 1 Refer to 18 3 7 Full Status Check The following commands cannot be accepted when the FMROG bit is 1 Program block erase lock bit program read lock bit status and block blank check FMRO7 Erase
209. cimal format Nothing is appended to numeric values given in decimal format Examples Binary 11b Hexadecimal EFAOh Decimal 1234 3 Register Notation The symbols and terms used in register diagrams are described below XXX Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset XXX 00h Bit Symbol y b1 b0 0 1 XXX 1 0 Do not set XXX1 11 XXX Nothing is assigned If necessary set to 0 b2 When read the content is undefined XXX4 XXX bits Function varies according to the operating mode XXX5 XXX6 XXX bit 0 XXX Blank Set to 0 or 1 according to the application 0 Set to 0 1 Set to 1 X Nothing is assigned 2 RW Read and write RO Read only WO Write only Nothing is assigned 3 Reserved bit Reserved bit Set to specified value Nothing is assigned Nothing is assigned to the bit As the bit may be used for future functions if necessary set to 0 Do not set to a value Operation is not guaranteed when a value is set Function varies according to the operating mode The function of the bit varies with the peripheral function mode Refer to the register diagram for information on the individual modes 4 List of Abbreviations and Acronyms Abbreviation Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter
210. ck and the UiLCH bit in the UiC1 register 0 no reverse i Oto2 Figure 13 17 Transfer Format 13 1 1 4 Continuous Reception Mode In continuous reception mode receive operation becomes enabled when the receive buffer register is read It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode However a dummy read of the receive buffer register is required when starting the operating mode When the UiRRM bit i 0 to 2 1 continuous reception mode the TI bit in the UiC1 register is set to 0 data present in the UiTB register by reading the UiRB register In this case i e UiRRM bit 1 do not write dummy data to the UiTB register in a program Bits UORRM and UIRRM correspond to bits 2 and 3 in the register respectively U2RRM bit is in U2C1 register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 145 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 1 5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register i 0 to 2 1 reverse the data written to the UiTB register has its logic reversed before being transmitted Similarly the received data has its logic reversed when read from the UiRB register Figure 13 18 shows Serial Data Logic Switching 1 When the UiLCH Bit in the UiC1 Register 0 No Reverse 8i Transfer Clock O UUUUUUU DO j D1 4 D2 J D3 X J D5 4 06 J D7 2 When the UiLCH Bit
211. ckoff period an ACK frame is transmitted after the boundary is located case 1 If the reception complete timing takes 192 us or less before the boundary of a backoff period transmission does not start even after the boundary is located but transmission starts after a delay for the boundary of the next backoff period case 2 In nonbeacon mode p warmup ACK responce In beacon mode Backoff period 320 us pam ACK response mE ACK response Figure 15 5 ACK Response Timing NOTES 1 Ongoing ACK response processing is not cancelled even if the AUTOACKEN bit in the BBTXRXMODEO register is set to 0 automatic ACK disabled 2 When performing frame transmission including automatic ACK reception disable the automatic ACK response function until the frame transmission is completed 3 A transmission complete interrupt is generated when ACK response is completed RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 202 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 11 Automatic ACK Reception Function After frame transmission is completed ACK receive processing can be automatically performed by using the ACKRCVEN bit in the BBTXRXMODEI register Frames other than ACK are not received The conditions for automatic ACK reception are Frame is transmitted with an ACK request Received frame is an ACK frame The sequence number of the transmitted frame and the one of the received frame match
212. ckoff period bit Sets the backoff period value Figure 15 37 Backoff Period Register Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 229 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 29 PLL Division Registers These registers are used to set the PLL divide ratio The same value is set for both transmission and reception Table 15 3 lists the Correspondence Between Register Setting Values and Channels PLL Division Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBPLLDIVL 013Ah 65h PLLDIV PLL divide ratio bit Refer to Table 15 3 PLL Division Register 1 b15b14b13b12b11b10 b9 b8 Symbol Address After Reset BBPLLDIVH 013Bh 09h Bit Symbol Bit Name Function Soe PLLDIV PLL divide ratio bit Refer to Table 15 3 b15 b13 No register bits If necessary set to 0 Read as undefined value Figure 15 38 PLL Division Register Configuration Table 15 3 Correspondence Between Register Setting Values and Channels Channel IEEE802 15 4 Frequency MHz PLLDIV Setting Value OBh 11 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 230 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 30 Transmit Output Power Register This register is used to set the transmission output power As reference data obtained from a standard sample Table 15 4 lists the Correspondence Between Register Setting Values and Ou
213. clock from stopping by an unexpected program operation When the PM21 bit in the PM2 register is set to 1 clock change disabled the following bits cannot be written to e Bits CM02 5 and CM07 in the register The CM10 bit in the CMI register The CM20 bit in the CM2 register When using the system clock protection function set the CMO5 bit in the CMO register to 0 main clock oscillation and CMO07 bit to 0 main clock as CPU clock source and follow the procedure below 1 Setthe PRCI bit in the PRCR register to 1 write to the PM2 register enabled 2 Set the PM21 bit in the PM2 register to 1 clock change disabled 3 Set the PRCI bit in the PRCR register to 0 write to the PM2 register disabled When the PM21 bit is set to 1 do not execute the WAIT instruction RO1UH0197EJ0120 Rev 1 20 RENESAS Page 58 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 6 Oscillation Stop and Re Oscillation Detect Function The oscillation stop and re oscillation detect function is such that main clock oscillation circuit stop and re oscillation are detected At oscillation stop or re oscillation detection reset oscillation stop or re oscillation detection interrupt are generated Which is to be generated can be selected using the CM27 bit in the CM2 register The oscillation stop and re oscillation detect function can be enabled and disabled by the CM20 bit in the CM2 register Table 7 7 lists a Specificat
214. computer is placed in I2C mode by setting bits SMD2 to SMDO to 010b and the IICM bit to 1 Because SDAi transmit output has a delay circuit attached SDAi output does not change state until SCLi goes low and remains stably Table 13 10 12C Mode Specifications Item Specification Transfer data format Transfer data length 8 bits Transfer clock During master CKDIR bit in the UiMR register 0 internal clock fj 2 n 1 fj f181O f2SIO f8SIO f32SIO n setting value of the UiBRG register 00h to FFh During slave CKDIR bit 1 external clock input from the SCLi pin Transmission start condition Before transmission starts satisfy the following requirements 1 The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present UiTB register Reception start condition Before reception starts satisfy the following requirements 1 The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in the UiTB register Interrupt request generation timing When start or stop condition is detected acknowledge undetected or acknowledge detected Error detection Overrun error 2 This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 8th bit of the next data Se
215. cond bus cycle of the lock bit program block erase block blank check or read lock bit status command 1 NOTES Erase error Program error The block erase command is executed on a locked block 2 The block erase command is executed on an unlocked block but auto erase operation is not completed as expected The block blank check command is executed and the check result is not blank The block blank check command is executed on a locked block The program command is executed on a locked block 2 The program command is executed on an unlocked block but program operation is not completed as expected The lock bit program command is executed but the lock bit is not written as expected 2 1 The flash memory enters read array mode by writing command code xxFFh in the second bus cycle of the commands The command code written in the first bus cycle becomes invalid 2 When the FMRO 2 bit is set to 1 lock bit disabled no error occurs even under the conditions above R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 275 of 331 M16C 6B Group 18 Flash Memory Full status check 1 Execute the clear status register command and set bits FMRO6 and FMRO7 q to 0 completed as expected 2 Rewrite command and execute again 1 Execute the clear status register command and set the FMRO7 bit to 0 2 Execute the read lock bit status command Set the FMRO2 bit to 1 lock bi
216. counting the pin outputs H ztENESAS Page 117 of 331 M16C 6B Group 12 Timers Timer Ai Mode Register i 0 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset tame 0336h to 0337h 00h T1 13 1 1 1 1 Bit Function Operation mode select bit 1 1 PWM mode TMOD1 RW 0 No pulse output TAiOUT pin functions as l O port MRO Bb PAR Pulse output RW TAiOUT pin functions as a pulse output pin MR1 External trigger select Falling edge of input signal to TAiIN pin 9 bit Rising edge of input signal to TAiIN pin 9 RN Write 1 to the TAIS bit in the TABSR register Selected by bits TAITGH and TAITGL RWV Trigger select bit 16 8 bit PWM mode 0 Functions as a 16 bit pulse width modulator select bit 1 Functions as an 8 bit pulse width modulator RUN b7 b6 0 0 1 TIMAB or f2TIMAB 9 Count source select bit 9 0 1 fSTIMAB 1 0 f82TIMAB 1 1 fC32 The TAOOUT pin is N channel open drain output Valid when bits TAiTGH and TAITGL bit in the ONSF register or TRGSR register are set to 00b pin input Set the port direction bit for the TAiIN pin to 0 input mode Set this bit to 1 pulse output to output PWM pulse Selected by the PCLKO bit in the PCLKR register Valid when the TCS3 bit or TCS7 bit in registers TACSO to TACS2 is set to 0 TCKO TCK1 enabled Only i2 O or 1 in the 48 pin version Figure 12 16 TAiMR i 0
217. cted with the DMS bit and bits DSEL4 to DSELO in the DMiSL register i 0 to 3 on either channel Table 11 4 lists the Timing at Which the DMAS Bit Changes State Whenever a DMA request is generated the DMAS bit is set to 1 DMA requested regardless of whether or not the DMAE bit is set If the DMAE bit is set to 1 enabled when this occurs the DMAS bit is set to 0 DMA not requested immediately before a data transfer starts This bit cannot be set to in a program it can only be set to 0 The DMAS bit may be set to 1 when the DMS bit or bits DSEL4 to DSELO change state Therefore always be sure to set the DMAS bit to 0 after changing the DMS bit or bits DSEL4 to DSELO Because if the DMAE bit is 1 a data transfer starts immediately after a DMA request is generated the DMAS bit in almost all cases is 0 when read in a program Read the DMAE bit to determine whether the DMAC is enabled Table 11 4 Timing at Which the DMAS Bit Changes State DMAS Bit in the DMiCON Register Timing at which the bit is set to 1 Timing at which the bit is set to 0 Software trigger When the DSR bit in the DMiSL register Immediately before a data transfer is set to 1 starts Peripheral function When the interrupt control register for the When set by writing a 0 in a program peripheral function that is selected by bits DSEL4 to DSELO and DMS in the DMISL register has its IR bit set to 1 DMA Factor i 0to3 R01UH0197EJ0120 Rev 1 20 ztE
218. ction disabled 3 Set the CMO5 bit to 1 stop During external clock input set the CMO5 bit to 0 oscillate When the CMO5 bit is set to 1 the XOUT pin is held After setting the CM04 bit to 1 XCIN XCOUT oscillator function wait until the subclock oscillates stably before switching the CMO7 bit from 0 to 1 subclock When entering stop mode the CMO6 bit is set to 1 divide by 8 mode The fC32 and fOCO S clock do not stop To use a subclock set this bit to 1 Also make sure ports P8 6 and P8 7 are directed for input with no pull ups When the PM21 bit in the PM2 register is set to 1 disable clock modification this bit remains unchanged even if writing to bits CMO2 CM05 and CMO7 When setting the PM21 bit to 1 set the CMO7 bit to 0 main clock before setting the PM21 bit to 1 To use the main clock as the clock source for the CPU clock set bits as follows 1 Set the 5 bit to 0 oscillate 2 Wait the main clock oscillation stabilizes 3 Set bits CM21 and CMO7 to 0 When the CMO7 bit is set to 1 subclock and the CMO5 bit is set to 1 main clock stops the CMO6 bit is fixed to 1 divide by 8 mode the CM15 bit is fixed to 1 drive capacity high To return from 125 kHz on chip oscillator mode to high speed or middle speed mode set bits CMO6 and CM15 to 1 Figure 7 2 Register R01UH0197EJ0120 Rev 1 20 ztENESAS Page 38 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generatio
219. d 272 18 3 4 8 revised 275 Table 18 12 revised 284 to 285 18 6 Notes on Flash Memory added 287 to 288 Table 19 2 title revised Table 19 3 and Figure 19 1 added 292 Table 19 8 RPULLUP revised 298 Table 19 18 VT VT and HPULLUP 306 20 2 1 revised 326 to 327 20 10 revised 1 10 Jan 28 2011 3 Table 1 2 Operating temperature 40 to 85 C added 4 Table 1 3 Figure 1 1 revised 288 Table 19 1 revised 289 to 292 294 to 297 20 to 85 C gt 20 to 85 C 40 to 85 C 300 to 303 1 20 Jul 21 2011 4 Table 1 3 D Under development added M16C 6B Group User s Manual Hardware Publication Date Rev 0 10 Jul 31 2008 Rev 1 20 Jul 21 2011 Published by Renesas Electronics Corporation 24 NE SAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5444 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany
220. d receive frame length 05h However when the address filter is enabled an ACK frame can be received only within 54 symbols after a frame with an ACK request is transmitted When an ACK frame is received outside this period data is discarded and transmission is awaited again 15 1 7 3 Reception Level Filter The LVLFILEN bit in the BBTXRXMODES3 register is used to enable or disable the filer for frames to be captured While the reception level filer is enabled only frames with the reception level set in the BBLVLVTH register or higher level can be received The value set in the receive level threshold set register or CCA level threshold set register is compared with the value to be stored in the RSSI CCA result register the value added with the offset value set in the RSSI offset register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 198 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 8 Interrupts Table 15 1 lists the interrupt signals from the baseband block Table 15 1 Interrupt No Baseband Interrupt List Interrupt Name Timer compare 0 Interrupt Generation Conditions An interrupt request is generated when the timer value and the timer compare 0 value match Timer compare 1 Timer compare 2 Transmission complete An interrupt request is generated when the timer value and the timer compare 1 value match An interrupt request is generated when the timer value and the timer compare
221. d the bit one before the last stop bit of the next data Framing error 3 This error occurs when the number of stop bits set is not detected Parity error 3 During reception if a parity error is detected parity error signal is output from the TXD2 pin During transmission a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs Error sum flag This flag is set to 1 when one of the overrun framing and parity errors occurs 1 If an overrun error occurs the received data of the U2RB register will be indeterminate The IR bit in the S2RIC register does not change 2 Atransmit interrupt request is generated by setting the U2IRS bit to 1 transmission completed and the U2ERE bit to 1 error signal output in the U2C1 register after reset is canceled Therefore when using SIM mode set the IR bit to O interrupt not requested after setting the bits 3 The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UART2 receive register to the U2RB register R01UH0197EJ0120 Rev 1 20 ztENESAS Page 172 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Table 13 19 Registers Used and Settings in SIM Mode Register 0 to 7 Function Set transmission data 0 to 7 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a bit rate SMD2 to SMDO Set to 101b CKDIR
222. de all oscillator circuits are turned off so are the CPU clock and the peripheral function clocks Therefore the CPU and the peripheral functions clocked by these clocks stop operating The least amount of power is consumed in this mode If the voltage applied to VCC pin is VRAM or greater the internal RAM is retained However the peripheral functions activated by external signals keep operating The following resets and interrupts can be used to exit stop mode Table 7 5 lists Resets and Interrupts to Stop Mode and Use Conditions Table 7 5 Resets and Interrupts to Stop Mode and Use Conditions Reset Interrupt Condition NMI interrupt Usable Key input interrupt Usable INT interrupt Usable Timer A interrupt Usable when counting external pulses in event counter Timer B interrupt mode Serial interface interrupt Usable when external clock is selected Hardware reset 1 Usable 7 4 8 4 Entering Stop Mode The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to 1 all clocks turned off At the same time the CMO6 bit in the register is set to 1 divide by 8 mode and the CM15 bit in the register is set to 1 main clock oscillator circuit drive capability high Before entering stop mode set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection function disabled 7 4 8 2 Pin Status in Stop Mode Table 7 6 lists Pin Status in Stop Mode Table
223. ding or receiving data Clearing the SWC2 bit to 0 transfer clock allows the transfer clock to be output from or supplied to the SCLi pin instead of outputting a low level signal If the SWC9 bit in the UiSMR4 register is set to 1 SCL hold low enabled when the CKPH bit in the UiSMR3 register 1 the SCLi pin is fixed to low level output at the falling edge of the clock pulse next to the 9th Setting the SWC9 bit 0 SCL hold low disabled frees the SCLi pin from low level output 13 1 3 5 SDA Output The data written to bits 7 to 0 D7 to DO in the UiTB register is output in descending order from D7 The 9th bit D8 is ACK or NACK Set the initial value of SDAi transmit output when 1 I2C mode and bits SMD2 to SMDO in the UiMR register 000b serial interface disabled Bits DL2 to DLO in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UIBRG count source clock cycles to SDAi output Setting the SDHI bit in the UISMR2 register 1 SDA output disabled forcibly places the SDAi pin in the high impedance state Do not write to the SDHI bit at the rising edge of the UARTi transfer clock This is because the ABT bit may inadvertently be set to 1 detected 13 1 3 6 SDA Input When the IICM2 bit 0 the 1st to 8th bits D7 to DO of received data are stored in bits 7 to 0 in the UIRB register The 9th bit D8 is ACK or NACK When the 2 bit 1 the 1st to 7th bits 07 to D1 of received data are stored in bit
224. direction bit Functions as an input port 1 Output mode Port Pi 2 direction bit Functions as an output port PDLS Por P e drecion bt 1 The PD10 register in the 48 pin version is a reserved area No access is allowed 2 Only PD5 5 and PD5 7 are available in the PD5 register The bits other than these are reserved Set to 0 3 PD7 4 to PD7 7 in the PD7 register in the 48 pin version are reserved bits Set to 0 4 PD8 4 in the PD8 register is not available It is a reserved bit Set to 0 5 PD8 0 and PD8 1 in the 48 pin version are reserved bits Set to 0 Figure 17 5 Registers PD5 to PD8 PD10 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 246 of 331 Jul 21 2011 M16C 6B Group 17 Programmable I O Ports Port Pi Register i 5 to 8 10 b7 b6 b5 b4 b3 b2 61 bO Symbol Address After Reset P5 9 pe P7 9 03E9h 03ECh O3EDh Indeterminate Pg 69 03F0h Indeterminate P10 2 03F4h Indeterminate Port Pi 0 bit The pin level on any I O port which is set Pi 1 Port Pi 1 bit for input mode can be read by reading the z corresponding bit in this register Port Pi_2 bit The pin level on any I O port which is set Port Pi 3 bit for output mode can be controlled by Port Pi 4 bit writing to the corresponding bit in this register Port Pi 5 bit 0 L level Pi6 Port 6 bit 1 H level 0 Port Pi 7 bit 1 Since P7 0 P7 1 and P8 5 are N cha
225. dog Timer 10 2 Count Source Protection Mode Enabled The 125 kHz on chip oscillator clock is used for the watchdog timer count source when count source protection mode is enabled If the CPU clock stops when a program is out of control the clock can still be supplied to the watchdog timer Table 10 3 lists the Watchdog Timer Specifications When Count Source Protection Mode is Enabled Table 10 3 Watchdog Timer Specifications When Count Source Protection Mode is Enabled Item Specification Count source 125 kHz on chip oscillator clock Count operation Decrement Period Watchdog timer count value 4096 125 kHz on chip oscillator clock example When 125 kHz on chip oscillator clock 125 kHz period approximately 32 8 ms Watchdog timer Reset reset condition Write 00h and then FFh to the register Underflow Count start condition Set the WDTON bit 1 in the OFS1 address FFFFFh to select the watchdog timer operation after reset When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after reset and count starts by writing to the WDTS register When the WDTON bit is set to 0 watchdog timer starts automatically after reset The watchdog timer and prescaler start counting automatically after reset Count stop condition None Count does not stop in wait mode or in hold state once count starts The MCU does
226. dth n fj 0000h to FFFEh 3 9 16 bit PWM 9 where n set value fj count source frequency Modify the pulse width as follows 00h to FEh PWM period 28 1 x m 1 fj High order address PWM pulse width m 1 n fj 00h to FFh where n high order address set value low order address set value now Orgs address fj count source frequency Pulse width modulation mode 8 bit PWM NOTES 1 Access to the register in 16 bit units 2 If the TAi register is set to 0000h the counter does not work and timer Ai interrupt requests are not generated either Furthermore if pulse output is selected no pulses are output from the TAIOUT pin If the TAi register is set to 0000h the pulse width modulator does not work the output level on the TAiOUT pin remains low and timer Ai interrupt requests are not generated either The same applies when the 8 high order bits of the timer TAi register are set to 00h while operating as an 8 bit pulse width modulator Use the MOV instruction to write to the TAi register The timer counts pulses from an external device or overflows or underflows in other timers Only TAO and 1 in the 48 pin version Figure 12 7 Registers TAO to TA4 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 104 of 331 Jul 21 2011 M16C 6B Group Count Start Flag b7 b6 b5 b4 b2 bi bO Symbol Address After Reset TABSR 0320h 00h Bit Symbol Bit Name Function TAOS Timer AO count sta
227. e Pi register 00h to 07h 01 H User boot mode address 3 value of j L Standard serial I O mode Other than Standard serial I O mode UserBoot in ASCII code 5 10 0107 NOTES 1 Do not use another combination of values apart from Table 18 4 2 Refer to Table 18 5 UserBoot in ASCII Code 3 Refer to Table 18 6 Addresses of Selectable Ports for Entry Table 18 5 UserBoot in ASCII Code ASCII code Table 18 6 Addresses of Selectable Ports for Entry Port Address O3E9h NOTE 1 64 version only RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 254 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 2 Functions to Prevent Flash Memory from Rewriting The flash memory has a built in ROM code protect function for parallel I O mode and a built in ID code check function for standard I O mode to prevent the flash memory from reading or rewriting 18 2 1 ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input output mode Figure 18 3 shows the OFS1 Address The OFS1 address is located in block 0 in program ROM The ROM code protect function is enabled when the ROMCPI bit is set to 0 When exiting ROM code protect erase block 0 including the OFS1 address by the CPU rewrite mode or the standard serial I O mode 18 2 2 ID Code Check Function Use the ID code check funct
228. e Pulse Signal Processing b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset 0 0 o 1 TAOMR to TA4MR 0336h to 033Ah 00h Bit Symbol Bit Name Function TMODO b1 b0 Operation mode select bit 0 1 Event counter mode 0 Pulse is not output MRO Pulse output function TAiOUT pin functions as port select bit 1 Pulse is output 9 TAiOUT pin functions as pulse output pin MR1 Count polarity select bit Counts falling edge of external signal 1 Counts rising edge of external signal MR2 Write 0 in event counter mode MR3 Write 0 in event counter mode Count operation type 0 Reload type TCKO select bit 1 Free run type TCK1 Can be 0 or 1 when not using two phase pulse signal processing 1 During event counter mode the count source can be selected using registers ONSF and TRGSR 2 Valid when bits TAiTGH and TAITGL in the ONSF or TRGSR register are 00b pin input 3 The TAOOUT pin is N channel open drain output 4 Only i 0 or 1 in the 48 pin version Figure 12 13 TAiMR i 0 to 4 Register in Event Counter Mode When Not Using Two Phase Pulse Signal Processing R01UH0197EJ0120 Rev 1 20 ztENESAS Page 112 of 331 Jul 21 2011 M16C 6B Group 12 Timers Table 12 4 lists Specifications in Event Counter Mode When Using Two Phase Pulse Signal Processing with Timers A2 A3 and A4 Figure 12 14 shows Registers TA2MR to TA4MR in Event Counter Mode When Using Two Phase
229. e assigned as the user boot code area refer to 18 1 2 User Boot Function Table 6 4 Program ROM 2 Addresses 10000h to 13FFFh PRGCUBHPRGECRegee 8 1 7 Single chip mode Program ROM 2 Figure 6 4 shows the Memory Map in Single Chip Mode Single chip Mode 00000h SFR 00400h Internal RAM XXXXXh 0D000h Internal RAM Internal ROM 0D800h Size Address XXXXXh Size Address YYYYYh Unusable TOR Kova ytes D0000h 20 KI FFh OEO00h QS 256 Kbytes C0000h data flash 10000h Internal ROM 14000h YYYYYh Internal ROM program ROM 1 FFFFFh NOTE 1 Program ROM 2 can be used when the 2 bit in the PRG2C register is 0 program ROM 2 enabled Figure 6 4 Memory Map in Single Chip Mode R01UH0197EJ0120 Rev 1 20 ztENESAS Page 35 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit re 7 1 Clock Generation Circuit Type of the Clock Generation Circuit 3 circuits are incorporated to generate the system clock signal Main clock oscillation circuit e Subclock oscillation circuit 125 kHz on chip oscillator Table 7 1 lists the Clock Generation Circuit Specifications Figure 7 1 shows the System Clock Generation Circuit Figures 7 2 to 7 5 show the clock related registers Table 7 1 Use of clock Main Clock Oscillation Circuit CPU clock source Peripheral function clock source Reference clock source for the transceiver Clock Generation C
230. e mode set the CMO6 bit in the register and bits CM17 and 16 in the CM1 register to CPU clock frequency of 8 MHz or less Set the PM17 bit in the PM1 register to 1 with wait state 2 Set the FMRO 1 bit to 1 immediately after setting it to 0 Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting it to 1 Set the FMRO1 bit in the RAM 3 Exit CPU rewrite mode after executing the read array command 4 When in CPU rewrite mode PM10 bit in the PM1 register is set to 1 The rewrite control program can only be executed in the internal RAM Transfer the rewrite control program in CPU rewrite mode to the RAM Figure 18 5 Setting and Resetting of EWO Mode Procedure to Enter EW1 Mode Program in the ROM Single chip mode Y Set registers CMO CM1 and PM1 Set the FMRO 1 bit to 1 CPU rewrite mode enabled after writing a 0 2 Set the FMR11 bit to 1 FMR6 register rewrite enabled and then set the FMR6 register to O3h EW1 mode and then set the FMR11 bit to 0 FMR6 register rewrite disabled v Execute the software commands v Set the FMRO 1 bit to 0 CPU rewrite mode disabled NOTES 1 In CPU rewrite mode set the CMO6 bit in the register and bits CM17 and 16 in the CM1 register to CPU clock frequency of 8 MHz or less Set the PM17 bit in the PM1 register to 1 with wait state 2 To s
231. e width Timer A Input Gating Input in Timer Mode Parameter input cycle time Standard Min Max tw TAH input H pulse width tw TAL Table 19 12 tc TA input L pulse width Parameter input cycle time Timer A Input External Trigger Input in One Shot Timer Mode Standard Min Max tw TAH input H pulse width tw TAL Table 19 13 input L pulse width Parameter input pulse width Timer A Input External Trigger Input in Pulse Width Modulation Mode Standard Min 150 Max TAIIN input L pulse width 150 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 294 of 331 M16C 6B Group Timing Requirements 19 Electrical Characteristics VCC 3 3V VCC 3 3 V VSS 0 V at 20 to 85 C 40 to 85 C unless otherwise specified Table 19 14 Timer A Input Counter Up Down Input in Event Counter Mode Parameter tc UP TAiOUT input cycle time Standard Min Max tw UPH TAiOUT input pulse width tw UPL TAiOUT input L pulse width tsu UP TIN TAiOUT input setup time th TIN UP TAiOUT input hold time Table 19 15 Timer A Input Two Phase Pulse Input in Event Counter Mode Parameter tc TA input cycle t
232. eatedly converted to a digital code Table 14 6 lists the Repeat Sweep Mode 1 Specifications Figure 14 8 shows Registers ADCONO and ADCONI in Repeat Sweep Mode 1 Table 14 6 Repeat Sweep Mode 1 Specifications The input voltages on pins are A D converted repeatedly with priority given to pins selected by bits SCAN1 and SCANO in the ADCON1 register Example If ANO selected input voltages are A D converted in order of ANO AN1 ANO AN2 ANO ANS and so on A D conversion start The ADST bit in the ADCONO register is set to 1 A D conversion start condition A D conversion stop Set the ADST bit to 0 A D conversion stop condition Interrupt request No interrupt requests generated generation timing Analog input pins to be Select from ANO 1 pin ANO and AN1 2 pins ANO to AN2 3 pins and ANO given priority when A D to AN3 4 pins converted Reading of result of A D Read one of the registers ADO to AD7 that corresponds to the selected pin converter RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 189 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 0 b7 b6 3 b2 b bO Symbol Address After Reset ADCONO 03D6h 00000XXXb Analog input pin select bit Invalid in repeat sweep mode 1 b4 b3 A D operation mode select 1 1 Repeat sweep mode 0 or bit 0 repeat sweep mode 1 Reserved bit Set to 0 0 A D conversion stop A D conver
233. ect a pin to VCC via resistor pull up P8 5 to P8 7 P10 5 Set for output mode and leave the pins open 1 3 XOUT 4 Open XIN Connect to VCC via resistor pull up VREF Connect to VCC 5 NOTES 1 When setting the port for output mode and leave it open be aware that the port remains in input mode until it is switched to output mode in a program after reset For this reason the voltage level on the pin becomes indeterminate causing the power supply current to increase while the port remains in input mode Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins within 2 cm When the ports P7 0 P7 1 and P8 5 are set for output mode make sure a low level signal is output from the pins This applies when external clock is input to the XIN pin or when VCC is connected to via a resistor 64 pin version only Microcomputer Port P5 to P8 P10 Input mode Input mode Output mode XIN XOUT In single chip mode 64 pin version only Figure 17 9 Unassigned Pin Handling RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 250 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 Flash Memory The flash memory can perform in three rewrite modes CPU rewrite mode standard serial I O mode and parallel I O mode Table 18 1 lists the Flash Memory Specifications Refer to Tables 1 1 and 1 2 Specifications for the items not listed in Table
234. ecting Pattern Connecting Pattern Bypass Capacitor Figure 20 4 Bypass Capacitor Connection RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 328 of 331 Jul 21 2011 M16C 6B Group Appendix 1 Package Dimensions Appendix 1 Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the Packages section of the Renesas Electronics website JEITA Package Code RENESAS Code Previous Code MASS Typ P HVQFN64 9x9 0 50 PVQNO064KA A 0 20g Hp D Reference Dimension in Millimeters Symbol Min Nom Max D 90 E 9 0 A2 0 89 A OSS 0 005 0 02 0 04 b 0 17 0 22 0 27 b4 10 20 e Lp 0 35 0 45 0 55 x 0 05 0 07 y1 zn 0 2 t 0 2 Dimension including the plating thickness Hp 9 2 Base material dimension Hg 92 Zp 0 75 26 0 75 c 0 17 0 22 025 C4 11 10 20 JEITA Package Code RENESAS Code Previous Code MASS Typ P HVQFNA8 7x7 0 50 PVQNO00
235. ection enabled ROMCP1 ROM code protection bit 1 ROM code protection disabled b6 b4 p M 4 EURO PRU ee a CE ee ee ce qe Reserved bits Set to 1 0 Count source protection mode enabled After reset count source after reset protection mode select bit 9 1 Count source protection mode disabled after reset CSPROINI 1 The OFS1 address exists in flash memory Set the values when writing a program 2 The OFS1 address is set to FFh when the block including the OFS1 address is erased 3 Set the WDTON bit to 0 watchdog timer starts automatically after reset when setting the CSPROINI bit to 0 count source protection mode enabled after reset Figure 10 3 Register and OFS1 Address RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 84 of 331 Jul 21 2011 M16C 6B Group 10 Watchdog Timer 10 1 Count Source Protection Mode Disabled The CPU clock is used for the watchdog timer count source when count source protection mode is disabled Table 10 2 lists the Watchdog Timer Specifications When Count Source Protection Mode is Disabled Table 10 2 Watchdog Timer Specifications When Count Source Protection Mode is Disabled Item Specification Count source CPU clock Count operation Decrement Period Prescaler divide ratio n x watchdog timer count value 32768 1 CPU clock n 16 or 128 selected by the WDC7 bit in the WDC register example Wh
236. egister When an external clock is selected set the TE bit to 1 transmission enabled place dummy data in the UiTB register and input an external clock to the CLKi pin to generate the shift clock If data is received consecutively an overrun error occurs when the RI bit in the UiC1 register is set to 1 data present in the UiRB register and the next receive data is received in the UARTI receive register And then the OER bit in the UiRB register is set to 1 overrun error occurred At this time the UiRB register is undefined If an overrun error occurs the IR bit in the SiRIC register remains unchanged To receive data consecutively set dummy data in the low order byte in the UiTB register per each receive operation If an external clock is selected the following conditions must be met while the external clock is held H when the CKPOL bit is set to 0 transmit data output at the falling edge and receive data input at the rising edge of the serial clock or while the external clock is held L when the CKPOL bit is set to 1 transmit data output at the rising edge and receive data input at the falling edge of the serial clock e The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register 0 data present in the UiTB register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 322 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 8 2 UAR
237. egister 0 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset MACANTA FMRO 0220h 00000001b Other than user boot mode i 00100000b User boot mode I Bit Symbol Bit Name Function 1 1 1 Dem 0 Busy being written or erased FMROO RY BY status flag 1 Ready m CPU rewrite mode select 0 CPU rewrite mode disabled 1 CPU rewrite mode enabled n 4 10 Lock bit enabled FMRO2 Lock bit disable select bit 1 Lock bit disabled 0 Flash memory operation enabled Flash memory stop bit 1 Flash memory operation stopped low power mode flash memory initialized Reserved bit Set to 0 Reserved bit Set to 0 in other than user boot mode b5 Set to 1 in user boot mode 0 Terminated normally FMRO06 status flag 1 Terminated in error DR 0 Terminated normally FMRO7 Erase Status Flag 1 Terminated in error m FMRO01 CPU rewrite mode select bit b1 Commands can be accepted by setting the FMRO1 bit to 1 CPU rewrite mode enabled To set the FMROI bit to 1 write 0 and then 1 in succession Make sure no interrupts or DMA transfers will occur before writing 1 after writing 0 Change the FMROI bit when the PM24 bit in the PM2 register is 0 NMI interrupt disabled or low is input to the NMI pin While in EWO mode write to this bit from a program in the RAM Enter read array mode and then set this bit to 0 R01UHO197EJ0120 Rev 1 20 RENESAS Page 53 of 331 Jul 21 2011 M16C 6B Group 7 Clock Ge
238. egister is set to 0 main clock and the 125 kHz on chip oscillator clock is used when the CM21 bit is set to 1 125 kHz on chip oscillator clock The fC32 clock can be used as the count source for timers A and B 7 4 1 4 Low Power Consumption Mode In this mode the main clock is turned off after being placed in low speed mode The subclock provides the CPU clock The fC32 clock can be used as the count source for timers A and B If fOCO S is oscillating fOCO S can be used as the count source for timers A and B Simultaneously when this mode is selected the CMO6 bit in the CMO register becomes 1 divided by 8 mode In the low power consumption mode do not change the CMO6 bit Consequently the medium speed divided by 8 mode is to be selected when the main clock is operated next 7 4 1 5 125 kHz On Chip Oscillator Mode The 125 KHz on chip oscillator clock divided by 1 undivided 2 4 8 or 16 provides the CPU clock The 125 kHz on chip oscillator clock is also the clock source for the peripheral function clocks If the subclock is on fC32 can be used as the count source for timers A and B When the operating mode is returned to the high and medium speed modes set the CMO6 bit in the CMO register to 1 divided by 8 mode R01UHO197EJ0120 Rev 1 20 ztENESAS Page 46 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 1 6 125 kHz On Chip Oscillator Low Power Consumption Mode The main clock is turned off after b
239. eing placed in 125 kHz on chip oscillator mode The CPU clock can be selected as in the 125 kHz on chip oscillator mode The 125 kHz on chip oscillator clock is the clock source for the peripheral function clocks If the subclock is on fC32 can be used as the count source for timers A and B Table 7 2 Setting Clock Related Bit and Modes CM2 Register CM1 Register CMO Register CM21 CM14 CM17 CM16 CMO06 5 High speed mode 0 00b 0 0 0 Medium speed divided by 2 0 01b 0 0 0 mode divided by 4 0 10b 0 0 0 divided by 8 0 0 1 0 divided by 16 0 11b 0 0 0 Low speed mode 1 0 1 Low power consumption mode 0 il 10 10 1 125 kHz on chip divided by 1 1 0 00b 0 0 0 oscillator mode divided by 2 1 0 01b 0 0 0 divided by 4 1 0 10b 0 0 0 divided by 8 1 0 0 1 0 divided by 16 1 0 11b 0 0 0 125 kHz on chip oscillator low 1 0 2 0 2 1 power consumption mode indicates that either O or 1 is set NOTES 1 When the CMOS5 bit is set to 1 main clock turned off in low speed mode the mode goes to low power consumption mode and the CMO6 bit is set to 1 divided by 8 mode simultaneously 2 The divide by n value can be selected the same way as in 125 kHz on chip oscillator mode R01UHO197EJ0120 Rev 1 20 24 NC SAS Page 47 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 2 Wait M
240. en CPU clock frequency 16 MHz and prescaler divided by 16 period approximately 32 8 ms Watchdog timer reset condition Reset Write 00h and then FFh to the WDTR register Underflow Count start condition Set the WDTON bit 2 in the OFS1 address FFFFFh to select the watchdog timer operation after reset When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after reset and count starts by writing to the WDTS register When the WDTON bit is set to 0 watchdog timer starts automatically after reset The watchdog timer and prescaler start counting automatically after reset Count stop condition Stop mode wait mode hold state count resumes from the hold value after exiting Operation when the timer underflows NOTES When the PM 12 bit in the PM1 register is set to 0 Watchdog timer interrupt When the PM 12 bit in the PM1 register is set to 1 Watchdog timer reset refer to 5 3 Watchdog Timer Reset 1 Write 00h and then FFh to the WDTR register to initialize the watchdog timer The prescaler is initialized after reset Some errors in the period of the watchdog timer may be caused by the prescaler 2 The WDTON bit cannot be changed by a program Write a 0 to bit 0 of address FFFFFh with a flash programmer to set the WDTON bit R01UH0197EJ0120 Rev 1 20 ztENESAS Page 85 of 331 Jul 21 2011 M16C 6B Group 10 Watch
241. en the U flag is set to 1 The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt number 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7 If a requested interrupt has higher priority than IPL the interrupt is enabled 2 8 10 Reserved Space Only write 0 to bits assigned as reserved bits The read value is undefined R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 14 of 331 Jul 21 2011 M16C 6B Group 3 Memory 3 Memory Figure 3 1 is a memory map of the M16C 6B Group The M16C 6B Group have 1 Mbyte address space from address 00000h to FFFFFh The internal ROM is flash memory Program ROM 1 is allocated from address FFFFFh to lower For example a 64 Kbyte program ROM 1 is addressed from F0000h to FFFFFh An 8 Kbyte data flash is addressed from OE000h to OFFFFh This data flash space is used not only for data storage but also for program storage Program ROM 2 is allocated addresses 10000h to 13FFFh The fixed interrupt vectors are addressed from FFFDCh to FFFFFh They store the starting address of each interrupt routine The internal RAM is allocated from address 00400h to higher For example a 10 Kbyte internal RAM is addressed from 00400h to 02BFFh The internal RAM is used not only for data storage but also for stack area when subroutines are called or when inter
242. ennen nennen nennen 194 15 1 3 26 Bit Timer noe IUe teet ecelesie etl cid cett ec e 195 151 4 Transmit RAM tet eee e eee d petite tte e feo de e E ne he ns 196 15 415 R cewe Ra EHE UU RID E eed 196 15 16 Transmit Frame Generator o eet aem meteo eee EE ome idet 197 15 1 7 Filter Function ics cemere eoe ie rie eiue p OH HR te 198 15 L 8 Interr pts e e ter brin EE E rere ER 199 15 59 CRGO Gireit ied ien eame Bebe E RE REIS a 200 15 1 10 Automatic ACK Response Function eeeesseseeeeeeeeeeennen eene 201 15 1 11 Automatic ACK Reception Function ao rennen entrent 203 15 1 12 Automatic Reception Switching Function eese nennen een ennt nnne 204 15 1 13 ANTSW Output Switching Function ener en 204 15 1 14 Automatic CSMA CA Function scere RH eR ERR s ee IRI her teh ERE e Rp 205 15 115 State Transitions Un E URDU REP Medien 207 15 2 Baseband Associated Reglsters oia n ee ge hue e er aO ge de Oei 208 15 2 4 Baseband Control Resister eene nennen nne R enne enne tentent 208 15 22 Transmit Receive Reset Register 4 oie eden e He e e dete a ete eite 209 15 2 3 Transmit Receive Mode Register 0 enne ethernet i rirni ieres 210 15 2 4 Transmit Receive Mode Register 1
243. equest is acknowledged after interrupt request is acknowledged Figure 9 7 Stack Status Before and After Acceptance of Interrupt Request The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request is even or odd If the SP 1 is even the FLG register and the PC are saved 16 bits at a time If odd they are saved in two steps 8 bits at a time Figure 9 8 shows the Operation of Saving Register NOTE 1l When any INT instruction in software numbers 32 to 63 has been executed this is the SP indicated by the U flag Otherwise it is the ISP 1 SP contains even number 2 SP contains odd number Address Stack Sequence in which order Address Stack Sequence in which order registers are saved registers are saved 5 Odd 4 Even 2 Saved simultaneously 3 Odd all 16 bits Saved 8 bits at a time 2 Even 1 Saved simultaneously 1 Odd all 16 bits Even Completed saving registers Completed saving registers in two operations in four operations PCL 8low order bits of PC PCM 8 middle order bits of PC NOTE PCH 4 high order bits of PC 1 SP denotes the initial value of the SP when interrupt request is acknowledged FLGL 8 low order bits of FLG After registers are saved the SP content is SP minus 4 FLGH 4 high order bits of FLG
244. er 2 b7 b6 b5 b4 b3 b2 61 bO Symbol Address After Reset Xol ENN INTOIC 005Dh XX00X000b XX00X000b 1 1 1 1 1 1 1 1 1 1 1 1 1 INT1IC 005Eh o MN RM NN 8 Level 0 interrupt disabled Level 1 Level 2 Level 3 RW Level 4 Level 5 Level 6 RW Level 7 t3200 000 bit P Interrupt priority level select 00000 Interrupt request bit T Interrupt not requested Interrupt requested 0 Select falling edge 1 Select rising edge E RM 19 Polarity select bit b7 b6 No register bits If necessary set to 0 Read as undefined value 1 The IR bit can only be reset by writing a 0 Do not write a 1 2 To rewrite the interrupt control register do so at a point that does not generate the interrupt request for that register 3 If the IFSRi bit in the IFSR register 1 both edges set the POL bit in the INTiIC register to O falling edge i 0 to 1 Figure 9 4 Interrupt Control Register 2 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 69 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 5 1 Flag The I flag enables or disables the maskable interrupt Setting the I flag to 1 enabled enables the maskable interrupt Setting the I flag to 0 disabled disables all maskable interrupts 9 5 2 IR Bit The IR bit is set to interrupt requested when an interrupt request is generated
245. er A Count Source Select Register 2 Timer A Waveform Output Function Select Register TAPOFS XXX00000b Timer B Count Source Select Register 2 Timer B Count Source Select Register 3 NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UH0197EJ0120 Rev 1 20 ztENESAS Page 22 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 8 SFR Information 8 1 Address Register After Reset Interrupt Source Select Register 2 IFSR2A Interrupt Source Select Register IFSR Address Match Interrupt Enable Register XXXXXX00b Address Match Interrupt Enable Register 2 XXXXXX00b Address Match Interrupt Register 0 00h 00h Address Match Interrupt Register 1 00h 00h Address Match Interrupt Register 2 00h 00h XOh Address Match Interrupt Register 3 00h 00h XOh Flash Memory Control Register 0 00000001b Flash Memory Control Register 1 00X0XX0Xb Flash Memory Control Register 2 XXXX0000b Flash Memory Control Register 6 XX0XXX00b NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UH0197EJ0120 Rev 1 20 zt
246. er case c 45h E 74h lower case t Reserve word for forced erase function A set of reserved characters that match all the ID code addresses in sequence as the combination table listed in Table 18 7 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 255 of 331 Jul 21 2011 M16C 6B Group 18 2 3 Forced Erase Function This function is available only in standard serial I O mode When the reserved characters ALeRASE in ASCII code are sent from the serial programmer as ID codes the content of the user ROM area will be erased at once However if the ID codes stored in the ID code addresses in the user ROM area are set to other than a reserved word ALeRASE other than Table 18 7 Reserved Character Sequence Reserved Word when the ROMCPI bit in the OFS1 address is set to other than 11b ROM code protect enabled forced erase function is ignored and ID code check is executed Table 18 8 lists the Forced Erase Function When both the ID codes sent from the serial programmer and the ID codes stored in the ID code addresses correspond to the reserved word ALeRASE the user ROM area will be erased However when the serial programmer sends other than ALeRASE even if the ID codes stored in the ID code addresses are ALeRASE there is no ID match and any command is ignored The user ROM area remains protected accordingly Table 18 8 Forced Erase Function Condition ID from ROMCP 1 bit
247. er mode as soon as an auto erase operation starts The status register can be read The SR7 bit in the status register is set to 0 at the same time an auto erase operation starts It is set to 1 when an auto erase operation is completed The microcomputer remains in read status register mode until the read array command or read lock bit status command is written If an erase error occurs execute the clear status register command and then block erase command at least 3 times until an erase error is not generated Write the command code xx20h Write xxDOh to the highest order block address Full status check 9 Block erase operation completed NOTES 1 Write command codes and data to even addresses 2 Refer to Figure 18 13 Full Status Check and Handling Procedure for Each Error 3 If an erase error occurs execute the clear status register command and then block erase command at least three times until an erase error is not generated Figure 18 9 Flow Chart of the Block Erase Command RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 269 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 4 6 Lock Bit Program Command The lock bit program command sets the lock bit for a specified block to 0 locked By writing xx77h in the first bus cycle and xxDOh in the second bus cycle to the highest order even address of a block the lock bit for the specified block is set to 0 The address value specified in the first bus cycle
248. er to the UiRB register CKPOL 0 rising edge CKPOL 1 falling edge Rising edge of SCLi 9th bit Falling edge of SCLi 9th bit Falling and rising edges of SCLi 9th bit UARTI transmission output delay Not delayed Delayed Functions of TXDi SDAi TXDi output SDAi input output Functions of RXDi SCLi RXDi input SCLi input output Functions of CLKi CLKi input or output port selected Cannot be used I2C mode Noise filter width 15ns 200 ns Read RXDi and SCLi pin levels Possible when the corresponding port direction bit 0 Always possible no matter how the corresponding port direction bit is set Initial value of TXDi and SDAi outputs CKPOL 0 CKPOL 1 L The value set in the port register before setting 12C mode 2 Initial and end values of SCLi factor 6 reception Acknowledgment detection ACK UARTI reception Falling edge of SCLi 9th bit Store received data 1st to 8th bits of the received data are stored into bits 0 to 7 in the UiRB register 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register register 1st to 7th bits of the received data are stored into bits 6 to 0 in the UiRB register 8th bit is stored into bit 8 in the VIRB 1st to 8th bits are stored into bits 7 to 0 in the
249. eration is completed frame reception is completed even if bits AUTORCVO and AUTORCVI in the BBTXRXMODEO register are set to 0 automatic reception switching disabled 15 1 13 ANTSW Output Switching Function To control the external power amplifier and others this function enables the timing adjustment of the signal which is set to high output when transmitted from the ANTSWCONT pin The timing can be set by using the BBANTSWTIMG register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 204 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 14 Automatic CSMA CA Function By setting CSMAST bit in the BBCSMACONO register 1 automatic CSMA CA start the CSMA CA flowchart can be automatically performed Set the CCA threshold level in the BBCCAVTH register Registers and BBCSMACON can be used to set each variable Upon completion of CSMA CA operation the result can be simultaneously stored in the CSMACA bit in the BBTXRXSTO register and a CSMA CA interrupt can be generated By having set the CSMATRNST bit in the BBCSMACONO register to 1 transmit processing after CSMA CA transmit processing can be automatically proceeded if the CSMA CA check result is TRUE Before performing an automatic CSMA CA start make sure to allow the wait time set in the BBIDLEWAIT register to elapse after setting to IDLE status When setting the CSMAST bit in the BBCSMACONO register to 1 automatic CSMA CA start while the BEMIN
250. erflows of other timers 3 Set it when the TBiS bit in the TABSR or TBSR register is set to 0 count stops 4 Read only RO when the TBiS bit in the TABSR or TBSR register is set to 1 count starts Figure 12 20 Register TBOMR to TB5MR and TBO to TB5 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 121 of 331 Jul 21 2011 M16C 6B Group 12 Timers Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TABSR 0320h 00h Bit Symbol Bit Name Function 0 Stop counting Timer AO count start flag 1 Start counting Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer BO count start flag Timer B1 count start flag Timer B2 count start flag Timer B3 B4 B5 Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TBSR 0300h 000XXXXXb Bit Symbol Bit Name Function No register bits If necessary set to 0 Read as undefined value 0 Stop counting Timer B3 count start flag 1 Start counting Timer B4 count start flag Timer B5 count start flag Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset CPSRF 0015h 0XXXXXXXb Bit Symbol Bit Name Function No register bits If necessary set to 0 Read as undefined value Setting this bit to 1 initializes the clock Clock prescaler reset flag prescaler Read as 0 Figure 12 21 Register TABSR TBSR and CPSR
251. et input Reset input pin While the RESET pin is L level input a 20_cycle or longer clock to the XIN pin XIN Clock input XOUT Clock output I O pins for the main clock oscillation circuit Connect a crystal oscillator between pins XIN and XOUT VREF 1 Reference voltage input Reference voltage input pin for A D converter P55 EPM input Input L level signal P5 7 Input port P5 Input or L level signal or open P6_0 to P6 3 Input port P6 Input or L level signal or open P6_4 RTS1 BUSY output Standard serial I O mode 1 BUSY signal output pin Standard serial I O mode 2 Monitor signal output pin to check the boot program operation 5 CLK1 SCLK input Standard serial I O mode 1 Serial clock input pin Standard serial I O mode 2 Input L P6 6 RXD1 RXD input Serial data input pin P6 6 TXD1 TXD output Serial data output pin P7 0to P7 3 Input port P7 Input or L level signal or open 7 410 P7 7 1 Input port P7 Input or L level signal or open P8 0 1 P8_1 1 Input port P8 Input or L level signal or open P8 2 P8 3 Input port P8 Input or L level signal or open P8 5 NMI NMI input Input or L level signal or open P8 6 P8 7 Input port P8 Input or L level signal or open P1
252. et the FMRO 1 bit to 1 write a 0 and then a 1 to the FMR01 bit Make sure no interrupts or no DMA transfers will occur before writing a 1 after writing a 0 When setting the FMR11 bit to 1 set 1 while the FMRO bit is set to 1 Figure 18 6 Setting and Resetting of EW1 Mode R01UHO197EJ0120 Rev 1 20 ztENESAS Page 265 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory Low power consumption mode or on chip oscillator 1 low power consumption 77T mode program Transfer the low power consumption mode or on chip oscillator low power consumption mode program to the Set the FMR01 bit to 1 after setting to 0 CPU rewrite RAM mode enabled Jump to the low power consumption mode on chip Set the FMSTP bit to 1 The flash memory stops oscillator low power consumption mode program operating In a low power consumption state transferred to the RAM In the following steps use the low power consumption mode or on chip oscillator low power consumption mode program in the RAM Switch clock source of the CPU clock The main clock stops v Process in low power consumption mode or on chip oscillator low power consumption mode v NOTES nee m as 1 Set the FMSTP bit to 1 after the FMRO bit is set to 1 CPU rewrite mode Seth EC DRE ablas enabled Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or subclock Add tPS wait ti
253. et to 0 Read as undefined value Write to this register after setting the PRCO bit in the PRCR register to 1 write enabled Processor Mode Register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbo Address 001Eh After Reset PM2 XX000X01b Xo 0 11 Bit Symbol Bit Name Function Reserved bit Set to 1 System clock protection bit 3 0 Clock is protected by PRCR register 1 Clock modification disabled No register bit If necessary set to 0 Read as undefined value Reserved bit Set to 0 P8 5 NMI function select bit 9 0 Port P8 5 function 1 NMI function Reserved bit Set to 0 No register bits If necessary set to 0 Read as undefined value NOTES Figure 7 5 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enabled 2 Once this bit is set to 1 it cannot be cleared to 0 in a program 3 If the PM21 bit is set to 1 writing to the following bits has no effect 2 bit in CMO register CM05 bit in register main clock does not stop bit in register clock source for the CPU clock does not change CM10 bit in CM1 register stop mode is not entered CM20 bit in CM2 register oscillation stop and re oscillation detection function settings do not change Be aware that the WAIT instruction cannot be executed when the PM21 bit 1 PCLKR Register and PM2 Register R01UH0197EJ0120 Rev 1 20 ztENESAS Page 41 of 331 Jul 21 2011
254. extended addresses It consists of 64 bits 16 bits x 4 and is used to detect a match with the extended address of a receive frame Extended Address Register b15 b8 b7 b7 Symbol Address BBEXTENDADO 0119h 0118h BBEXTENDAD1 011Bh 011Ah BBEXTENDAD2 011Dh 011Ch BBEXTENDAD3 011Fh 011Eh After Reset 0000h 0000h 0000h 0000h Extended address register BBEXTENDADO Extended address bits 15 to 0 BBEXTENDAD 1 Extended address bits 31 to 16 BBEXTENDAD2 Extended address bits 47 to 32 BBEXTENDADS Extended address bits 63 to 48 Figure 15 32 Extended Address Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 225 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 24 Timer Read Out Register This register is for reading the current count value from the 26 bit timer When reading the timer count value read the BBTIMEREADO register lower byte first When bits 7 to O or bits 15 to 8 in the BBTIMEREADO register or both are read the count value of bits 25 to 16 in the BBTIMEREADI register higher byte is latched If the BBTIMEREADI register is read first note the BBTIMEREADO register is not latched After reading the BBTIMEREADO register its value is not updated even if this register is read again without reading the BBTIMEREADI register and the previously read value is read Timer Read Out Register 0 b15 b8 b7 b0 b7 Symbol Address After Reset BBTIMEREADO 0121
255. external bus in 8 bits width no address match interrupts can be used for external areas Figure 9 16 shows Registers AIER AIER2 and RMADO to RMAD3 9 Interrupt Table 9 8 Request is Accepted Instruction at the Address Indicated by the RMADi Register 16 bit op code instruction Instruction shown below among 8 bit operation code instructions ADD B S OR B S STNZ B S IMMB8 dest IMMB8 dest IMM8 dest IMMB8 dest IMM8 JSRS SUB B S MOV B S STZX B S PUSHM IMMB8 dest IMM8 dest STZ B S IMM81 IMM82 dest src POPM dest IMM8 IMM dest However dest AO or A1 AND B S IMM8 dest IMMB8 dest Value of the PC That Is Saved to the Stack Area When an Address Match Interrupt Value of the PC that is saved to the stack area The address indicated by the RMADi register 2 Instructions other than the above Value of the PC that is saved to the stack area Refer to 9 5 7 Saving Registers Table 9 9 The address indicated by the RMADi register 1 Relationship between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Sources Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIERO RMADO Address match interrupt 1 AIER1 RMAD1 Address match interrupt 2 AIER20 RMAD2 Address match interrupt 3 AIER21 RMAD3 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 80 of 331 M16C 6B Gr
256. f UiBRG count source 3 to 4 cycles of UiBRG count source 4 to 5 cycles of UiBRG count source 5 to 6 cycles of UiBRG count source 6 to 7 cycles of UiBRG count source 7 to 8 cycles of UiBRG count source SDAi digital delay setup bit 1 2 aaaaooooS 2o0o022008 2o0o2o020 2098 1 Bits DL2 to DLO are used to generate a delay in SDAi output by digital means during I C mode In other than 12C mode set these bits to 000b no delay 2 The amount of delay varies with the load on pins SCLi and SDAi Also when using an external clock the amount of delay increases by about 100 ns Figure 13 13 UOSMR3 to U2SMR3 Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 138 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface UARTi Special Mode Register 4 i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset UOSMR4 U1SMR4 U2SMR4 0244h 0254h 0264h 00h RW Stop condition generate 0 Clear STPREQ bit 0 1 Start 0 Start and stop conditions output STSPSEL SCL SDA output select bit 1 Start and stop conditions output 0 ACK ACKD ACK data bit 1 NACK ACKC ACK data output enable bit a output SCL output stop enable bit 0 EU T 0 SCL L hold disabled SCL wait bit 3 1 SCL L hold enabled 1 Set to 0 when each condition is generated Figure 13 14 Registers UOSMR4 to U2SMR4 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 139 of 331 Jul 21 2011 M16
257. falling edge and receive data taken in n value set to the UiBRG register at the rising edge of the transfer clock The UiIRS bit in the UiC1 register 0 an interrupt request occurs when the UiTB register becomes empty 2 Example of Receive Timing when external clock is selected RE bit in 1 UiC1 register 0 TE bit in 1 UiC1 regist Ne edite 07 Dummy data is set in the UiTB register 54 TI bit in 1 UiC1 register 0 Data is transferred from the UiTB register to the UARTi transmit register up RTSi L 1 fEXT bins An L signal is applied when the UiRB register is read RXDi 2 Data is transferred from the UARTi RI bitin receive register to the UiRB register UiC1 register IR bit in SiRIC register Set to 0 by an interrupt request acknowledgement or by program OER flag in UiRB register i 20to2 The above timing diagram applies to the case where the register bits are set as follows Make sure the following conditions are met when input The CKDIR bit in the UiMR register 1 external clock to the CLKi pin before receiving data is H The CRD bit in the UiCO register 0 CTS RTS enabled the CRS bit 1 RTS selected The TE bit in the UiCO register 1 transmit enabled The CKPOL bit in the UiCO register 0 transmit data output at the falling edge and receive The RE bit in the UiC1 register 1 receive enabled data taken in at t
258. feedback resistor XCIN External clock Oscillator L oo LL ey VSS XCOUT Open NOTE 1 Place a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by each oscillator manufacturer When the oscillation drive capacity is set to low check if oscillation is stable at low Also place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally Figure 7 7 Examples of Subclock Connection Circuit 7 1 3 125 kHz On Chip Oscillator Clock fOCO S This clock approximately 125 kHz is supplied by 125 kHz on chip oscillator This clock is used as the clock source for the CPU and peripheral function clocks In addition if the CSPRO bit in the CSPR register is 1 count source protection mode enabled this clock is used as the count source for the watchdog timer refer to 10 2 Count Source Protection Mode Enabled After reset the 125 kHz on chip oscillator divided by 8 provides the CPU clock It stops when the CM14 bit in the CM1 register is set to 0 125 kHz on chip oscillator stops If the main clock stops oscillating when the 20 bit in the CM2 register is 1 oscillation stop re oscillation detection function enabled and the CM27 bit is 1 oscillation stop re oscillation detection interrupt the 125 kHz on chip oscillator automatically starts operating and
259. ge 125 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 Serial Interface Serial interfaces consist of three channels UARTO to UART2 13 1 UARTI i 0 to 2 Each has an exclusive timer to generate a transfer clock so it operates independently of each other Figures 13 1 to 13 3 show the block diagrams of UARTI Figure 13 4 shows the UARTi Transmit Receive Unit has the following modes Clock synchronous serial I O mode Clock asynchronous serial I O mode UART mode Special mode 1 I2C mode e Special mode 2 Special mode 3 Bus collision detection function IE mode Special mode 4 SIM mode UART2 Figures 13 5 to 13 14 show the UARTi related registers Refer to tables for each mode for register setting R01UH0197EJ0120 Rev 1 20 ztENESAS Page 126 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface f1SIO or 2510 18510 32510 TXD polarity polarity RXDO eating SET switching circuit UART reception SMD2 to SMDO switching 010 100 101 110 circuit Reception Receive Transmit Clock source selection Clock sync type control clock receive CLK1 to ckpiR 001 circuit unit fiSlOor o0 Internal UOBRG 2510 6510 register 32510 Transmit 010 100 101 110 Transmission clock Clock sync type control circuit External Clock synchronous type when internal clock is selected 0 Clock sync
260. gister 0380h Timer B1 Mode Register 0381h Timer B2 Mode Register 0382h 0383h 0384h 0385h 0386h 0387h Blank columns are all reserved space No access is allowed Register Register 03CCh_ A D Register 6 AD6 03CDh O3CEh A D Register 7 AD7 03CFh 03D0h 03D1h 03D2h 03D3h Source Select Register 03D4h A D Control Register 2 ADCON2 180 03D5h DMA3 Source Select Register 03D6h A D Control Register 0 ADCONO 179 03D7h A D Control Register 1 ADCON1 179 03D8h 03D9h 03DAh 03DBh DMAO Source Select Register 03DCh 03DDh DMA1 Source Select Register O3DEh 03DFh 03E0 03E1 03E2 0 03 4 03 5 0 6 03 7 0 8 0 9 03EAh O3EBh Port P5 Direction Register PD5 246 O3ECh Port P6 Register P6 247 OSEDh Port P7 Register P7 247 O3EEh Port P6 Direction Register PD6 246 O3EFh Port P7 Direction Register PD7 246 O3FOh Port P8 Register P8 247 O3F1h O3F2h Port P8 Direction Register PD8 246 03F3h O3F4h Port P10 Register P10 247 03F5h O3F6h Port P10 Direction Register PD10 246 03F7h 03F8h 03F9h O3FAh O3FBh 03FCh 03FDh O3FEh O3FFh CRC Data Register D000h 180 180 s s s s 5 3 5 5 5 Port P5 Register P5 247 DO9Fh D100h Transmit RAM TRANSMIT_RAM_ o STA
261. gister Cycle time 216 1 fj fixed fj count source frequency 1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S fC32 Pulse width n x m 1 fj n set value of the TAi register high order address m set value of the register low order address Cycle time 28 1 x m 1 fj Count start condition The TAIS bit of the TABSR register is set to 1 start counting The TAIS bit 1 and external trigger input from the pin The TAIS bit 1 and one of the following external triggers occurs Timer B2 underflow Timer Aj j i 1 except j 4 ifi 0 overflow or underflow Timer Ak k 2 i 1 except k 0 if i 4 overflow or underflow Count stop condition The TAIS bit is set to 0 stop counting Interrupt request generation timing On the falling edge of PWM pulse pin function I O port or trigger input TAiOUT pin function Pulse output Read from timer An indeterminate value is read by reading the TAi register Write to timer When not counting Value written to the TAi register is written to both reload register and counter When counting Value written to the TAi register is written to only reload register transferred to counter when reloaded next Select function i 0to4 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 Output polarity control While the output polarity of TAiOUT pin is inverted the TAIS bit is set to 0 stop
262. gister to 1 and then insert at least four NOP instructions When entering stop mode the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit to 1 all clock stop and some of these may execute before the microcomputer enters stop mode or before the interrupt routine for returning from stop mode Program example when entering stop mode Program Example FSET I BSET 0 CM1 Enter stop mode JMP B L2 Insert a JMP B instruction L2 NOP More than four NOP instructions NOP NOP NOP e The CLKOUT pin outputs in stop mode Therefore when the CLKOUT pin changes state from to L and is immediately driven in stop mode the L level width becomes short Stop mode CLKOUT LI Wait until the main clock oscillation stabilizes before switching the clock source for the CPU clock to the main clock Similarly wait until the subclock oscillates stably before switching the clock source for the CPU clock to the subclock Do not stop the externally generated clock when the externally generated clock is input to the XIN pin and the main clock is used as the clock source for the CPU clock RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 308 of 331 Jul 21 2011 M16C 6B Group 20 Precautions Suggestions to reduce power consumption Refer to the following descriptions when designing a system or programming Ports The processor retains the state of each I O port even when it goe
263. gister to 1 stop mode 18 6 3 10 Software Command Observe the notes below when using the following commands Program Block erase Lock bit program Read lock bit status Block blank check The FMROO bit in the FMRO register indicates the status while executing these commands Do not execute other commands while the FMROO bit is 0 busy b Do not execute these commands while the CMO5 bit in the CMO register is 1 main clock stops c After executing the program block erase or lock bit program command perform a full status check per one command i e do not perform a single full status check after multiple commands are executed d Do not execute the program block erase lock bit program or block blank check command when either or both bits FMR06 and FMRO7 in the FMRO register are 1 completed in error e Do not execute these commands in the low current consumption read mode bits FMR22 and FMR23 are both 1 18 6 3 11 Program and Erase Cycles and Execution Time Execution time of the program block erase and lock bit program commands becomes longer as the number of programming and erasing increases 18 6 3 12 Suspending the Auto Erase and Auto Program Operations When the program block erase and lock bit program commands are suspended the blocks for those commands must be erased Execute the program and lock bit program commands again after erasing Those commands are suspended by the following reset or
264. gnal when a parity error is detected Table 13 18 lists the SIM Mode Specifications Table 13 19 lists the Registers Used and Settings in SIM Mode Table 13 18 SIM Mode Specifications Item Specification Transfer data format Direct format Inverse format Transfer clock The CKDIR bit in the U2MR register 0 internal clock fi 16 n 1 fi f181O f2SIO f8SIO f32SIO n setting value of the U2BRG register 00h to FFh The CKDIR bit 1 external clock fEXT 16 n 1 fEXT input from the CLK2 pin n setting value of the U2BRG register 00h to FFh Transmission start condition Before transmission starts satisfy the following requirements The TE bit in the U2C1 register 1 transmission enabled The TI bit in the U2C1 register 0 data present in the U2TB register Reception start condition Before reception starts satisfy the following requirements The RE bit in the U2C1 register 1 reception enabled Start bit detection Interrupt request generation timing 2 While transmitting When the serial interface completed sending data from the UART2 transmit register the U2IRS bit 21 While receiving When transferring data from the UART2 receive register to the U2RB register at completion of reception Error detection NOTES Overrun error 1 This error occurs if the serial interface started receiving the next data before reading the U2RB register and receive
265. h 0120h 0000h Timer read out register 0 BBTIMEREADO Lower bits 15 to 0 in the 26 bit timer Timer Read Out Register 1 b15 b8 b7 b0 b7 b0 Symbol Address After Reset BBTIMEREAD1 0123h 0122h 0000h Function Timer read out register 1 BBTIMEREAD1 Lower bits bits 25 to 16 in the 26 bit timer No register bits If necessary set to 0 Read as 0 Figure 15 33 Timer Read Out Register Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 226 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 25 Timer Compare i i 0 to 2 Register This register is for performing comparisons with the 26 bit timer Three channels are integrated and 26 bit comparison is performed in each channel Timer Compare i Register O b15 b8 b7 b7 b0 Symbol Address BBTCOMPOREGO 0125h 0124h BBTCOMP1REGO 0129h 0128h BBTCOMP2REGO 012Dh 012Ch After Reset 0000h 0000h 0000h Function Timer compare i register 0 BBTCOMPiREGO Lower bits bits 15 to 0 in the 26 bit compare i Oto2 Timer Compare i Register 1 b15 b8 b7 b0 b7 bo Symbol Address BBTCOMPOREG1 0127h 0126h BBTCOMP1REG1 012Bh 012Ah BBTCOMP2REG 1 012Fh 012Eh After Reset 0000h 0000h 0000h Timer compare i register 1 BBTCOMPiREG1 Lower bits bits 25 to 16 in the 26 bit compare i Oto2 No register bits If necessary set to 0 Read as 0 Figure 15 34 Timer Compare i Register Configuration R01UH0197
266. he CM07 bit is 0 set the FMR23 bit to 0 low current consumption read mode disabled To set the FMR23 bit to 1 write 0 and then 1 in succession Make sure no interrupts or DMA transfers occur before writing 1 and after writing 0 Set the FMR23 bit to 1 low current consumption read mode enabled after the FMR22 bit is set to 1 slow read mode enabled Also set the FMR22 bit to 0 slow read mode disabled after the FMR23 bit is set to 0 slow read mode disabled Do not change bits FMR22 and FMR23 at the same time When the FMR23 bit is 1 do not set the FMSTP bit in the FMRO register to 1 flash memory stopped Also when the FMSTP bit is 1 do not set the FMR23 bit to 1 When the FMR23 bit in the FMR2 register is 1 low current consumption read mode enabled do not enter wait mode or stop mode To enter wait mode or stop mode set the FMR23 bit to 0 low current consumption read mode disabled before entering R01UH0197EJ0120 Rev 1 20 ztENESAS Page 55 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 4 3 Slow Read Mode This mode can be used when f BCLK lt 5 MHz and the PM17 bit in the PM register is set to 1 1 wait Figure 7 10 shows Setting and Resetting of Slow Read Mode Slow read mode Set the frequency of CPU clock to 5 MHz or less and the PM 17 bit to 1 1 wait Setting 2 procedure After writing O write 1 enabled to the FMR22 bit Process in slow read mode Write 0 to the FMR22 bit
267. he CSPR register Start up or stop watchdog timer after reset Set the WDTON bit in the OFS1 address to select startup or stop Prescaler SPRO 0 12 0 Watchdog timer interrupt request Watchdog timer o 12 1 fOCO S o Watchdog timer CSPRO 1 reset O CMO07 1 Write to WDTR register Internal reset signal L active CSPRO bit in CSPR register WDCT bit in WDC register PM12 bit in PM1 register CM07 bit in CMO register NOTE 1 OFFFh is set when the CSPRO bit is set to 1 count source protection mode enabled Figure 10 1 Watchdog Timer Block Diagram RO1UH0197EJ0120 Rev 1 20 24 N SAS Page 82 of 331 Jul 21 2011 M16C 6B Group 10 Watchdog Timer Watchdog Timer Reset Register b0 Symbol Address After Reset WDTR 037Dh Indeterminate Setting 00h and then FFh initializes the watchdog timer 9 The watchdog timer is initialized to 7FFFh when count source protection mode is disabled and to OFFFh when count source protection mode is enabled 2 1 Make sure no interrupts or DMA transfers will occur before writing FFh after writing 00h 2 The watchdog timer is set to OFFFh when the CSPRO bit in the CSPR register is set to 1 count source protection mode enabled 3 After the watchdog timer interrupt occurs reset the watchdog timer by setting the WDTR register Watchdog Timer Start Register bo Symbol Address After Reset WDTS 037Eh Indetermin
268. he FSET instruction waiting INT SWITCR2 FCLR I Disable interrupts AND B 00H 0055H Set the TAOIC register to 00h MOV W MEM RO Dummy read FSET I Enable interrupts Example 3 Using the POPC instruction to change the I flag INT SWITCHR3 PUSHC FLG FCLR I Disable interrupts AND B 00H 0055H Set the TAOIC register to 00h POPC FLG Enable interrupts R01UH0197EJ0120 Rev 1 20 ztENESAS Page 312 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 5 7 Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt occurs RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 313 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 6 DMAC 20 6 1 Write to the DMAE Bit in the DMiCON Register i 0 to 3 When both of the conditions shown in a are met follow the steps in shown b a Conditions The DMAE bit is set to 1 DMAi is in active state again while it remains 1 A DMA request may occur simultaneously when the DMAE bit is being written b Steps 1 Write a 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously D 2 Make sure that is in initial state 2 in a program If the DMAi is not in initial state repeat the above steps NOTES 1 The DMAS bit remains unchanged even if a 1 is written However if a 0 is written to this bit it is set to 0 DMA not requested In order to prevent the DMAS bit from being modified to 0 1 should
269. he TAi register bits TAOTGL and TAOTGH in the ONSF register the TRGSR register registers TACSO to TACS2 and the TAPOFS register before setting the TAiS bit in the TABSR register to count starts i 0 to 4 Always make sure the TAiMR register bits TAOTGL and TAOTGH in the ONSF register the TRGSR register registers TACSO to TACS2 and the TAPOFS register are modified while the TAiS bit is 0 count stops regardless of whether after reset or not When setting the TAiS bit to 0 count stops the followings occur A counter stops counting and a content of reload register is reloaded e The TAiOUT pin outputs L when the POFSi bit in the TAPOFS register is 0 outputs H when 1 After one cycle of the CPU clock the IR bit in the TAiIC register is set to 1 interrupt requested Output in one shot timer mode synchronizes with a count source internally generated When an external trigger is selected one and half cycle delay of a count source as maximum occurs between a trigger input to the TAiIN pin and output in one shot timer mode No output from TA2 to TA4 in the 48 pin version The IR bit is set to 1 when timer operating mode is set with any of the following procedures e Select one shot timer mode after reset Change an operating mode from timer mode to one shot timer mode Change an operating mode from event counter mode to one shot timer mode To use the Timer Ai interrupt the IR bit set the IR bit to O after t
270. he TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register transferred to counter when reloaded next Select function 1 i 0to4 NOTE Pulse output function The timer outputs low when not counting and H when counting Output polarity control While the output polarity of TAiOUT pin is inverted the TAIS bit is set to 0 stop counting the pin outputs H 1 Only i O or 1 in the 48 pin version R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 115 of 331 M16C 6B Group 12 Timers Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset 1 0 to TA4MR 0336h to 033Ah 00h Bit Symbol Bit Name Function TMODO b1 bO Operation mode select bit 4 d Onc shotilmarinad No pulse output TAIOUT pin functions as I O port Pulse output TAiOUT pin functions as a pulse output pin External trigger select Falling edge of input signal to TAiIN pin 9 bit 2 Rising edge of input signal to TAiIN pin 9 Pulse output function select bit 9 TAiOS bit enabled um Trigger select bit Selected by bits TAITGH and TAITGL Set to 0 in one shot timer mode b7 b6 0 0 f1TIMAB or f2TIMAB Count source select bit 9 0 1 fSTIMAB 1 0 f82TIMAB 1 1 fC32 1 The TAOOUT pin is N channel open drain output
271. he UiCO register UiERE bit in the UiC1 register Clock sync type 13 Serial Interface UARTi receive register UiRB IT register Logic reverse circuit MSB LSB conversion circuit Data bus high order bits Data bus low order bits SF D7 D6 D5 D4 D3 D2 Dt DO gister UART 8 bits UART 9 bits PC clock sync type 1 0 UARTi transmit register UART 7 bits Error signal output disabled IOPOL No reverse i f TXDi 0 X Error i X TXD data C output reverse UiERE 1 circuit 1 circuit Reverse Error signal output enabled Figure 13 4 UARTi i 0 to 2 Transmit Receive Unit Block Diagram R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 129 of 331 M16C 6B Group 13 Serial Interface UARTIi Transmit Buffer Register i 0 to 2 CO b7 b0 Symbol Address After Reset UOTB 024Bh to 024Ah Indeterminate U1TB 025Bh to 025Ah Indeterminate U2TB 026Bh to 026Ah Indeterminate Function Transmit data No register bits If necessary set to 0 Read as undefined value S 1 Use MOV instruction to write to this register p UARTi Receive Buffer Register i 0 to 2 b8 b0 b7 bO Symbol Address After Reset UORB 024Fh to 024Eh Indeterminate U1RB 025Fh to 025Eh Indeterminate U2RB 026Fh to 026Eh Indeterminate Bit Symbol Bit Name Function b7 b0 No register bits If necessary set to 0 Read as undefined value Receive data D7 to DO
272. he changes listed above are made When a trigger occurs while counting a counter reloads the reload register to continue counting after generating a re trigger and counting down once To generate a trigger while counting generate a second trigger between generating the previous trigger and operating longer than one cycle of a timer count source RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 317 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 7 1 4 Timer A Pulse Width Modulation Mode 64 Pin Version Only The timer is stopped after reset Set the mode count source counter value and others using the TAiMR register the TAi register bits TAOTGL and TAOTGH in the ONSF register the TRGSR register registers TACSO to TACS2 and the TAPOF register before setting the TAiS bit in the TABSR register to 1 count starts i 0 to 4 Always make sure the TAiMR register bits TAOTGL and TAOTGH in the ONSF register the TRGSR register registers TACSO to TACS2 and the TAPOFS register are modified while the TAiS bit is 0 count stops regardless of whether after reset or not The IR bit is set to 1 when setting a timer operating mode with any of the following procedures Select PWM mode after reset Change an operating mode from timer mode to PWM mode Change an operating mode from event counter mode to PWM mode To use the timer Ai interrupt IR bit set the IR bit to 0 by program after the changes listed above are made When setti
273. he rising edge of the transfer clock Write dummy data to the UiTB register fEXT frequency of the external clock Figure 13 15 Transmit and Receive Operation during Clock Synchronous Serial I O Mode R01UHO197EJ0120 Rev 1 20 ztENESAS Page 143 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 1 1 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in clock synchronous serial I O mode follow the procedures below Resetting the UiRB register i 0 to 2 1 Set the RE bit in the UiC1 register to 0 reception disabled 2 Set bits SMD2 to SMDO in the UiMR register to 000b serial interface disabled 3 Set bits SMD2 to SMDO in the UiMR register to 001b clock synchronous serial I O mode 4 Set the RE bit in the UiC1 register to 1 reception enabled Resetting the UiTB register i 0 to 2 1 Set bits SMD2 to SMDO in the UiMR register to 000b serial interface disabled 2 Set bits SMD2 to SMDO in the UiMR register to 001b clock synchronous serial I O mode 3 A lis written to the RE bit in the UiC1 register transmission enabled regardless of the value of the TE bit in the UiCi register 13 1 1 2 CLK Polarity Select Function Use the CKPOL bit in the UiCO register i 0 to 2 to select the transfer clock polarity Figure 13 16 shows the Transfer Clock Polarity 1 When the CKPOL bit in the UiCO register 0 transmit data output at the falling
274. he same time and DMA transfer is executed in the shortest cycle access 5 privilege 22220 Figure 11 8 Example of DMA Transfer by External Factors RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 97 of 331 Jul 21 2011 M16C 6B Group 12 Timers 12 Timers Eleven 16 bit timers each capable of operating independently of the others can be classified by function as either Timer A five and Timer B six The count source for each timer acts as a clock to control such timer operations as counting reloading etc Figure 12 1 shows Timers A and B Count Source and Figures 12 2 and 12 3 show Timer A and Timer B configuration respectively Clock Generation Circuit Main clock generation circuit 125 KHz on chip oscillator Subclock generation circuit Set the CPSR bit in the CPSRF register to 1 prescaler reset Figure 12 1 Timers and Count Source PCLKO 1 f1TIMAB f1TIMAB or f2TIMAB f8TIMAB f82TIMAB f64TIMAB fOCO S fC32 21 bit in the CM2 register PCLKO bit in the PCLKR register TAO to TA4 and TBO to TBS have limitations depending on the mode as shown in the following table Table 12 1 Limitations on Each Mode Timer Mode Event Counter Mode One Shot Timer Mode PWM Mode Pulse Period Measuremen
275. high When transmitting a transmission complete interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit Therefore whether a parity error signal has been returned can be determined by reading the port that shares the RXD2 pin in a transmission complete interrupt routine Transfer clock Lal RXD2 W ST 4 Dif X D4 X D5 X 6X D7 X P SP Tp2 7 NOTE 1 E Ri bitin U2C1 register This timing diagram applies to the case where the direct format is implemented ST Start bit P Even Parity NOTE SP Stop bit 1 The output of microcomputer is in the high impedance state pulled up externally Figure 13 38 Parity Error Signal Output Timing R01UHO197EJ0120 Rev 1 20 ztENESAS Page 175 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 6 2 Format Two formats are available direct format and inverse format In direct format set the PRYE bit in the U2MR register to 1 parity enabled the PRY bit to 1 even parity the UFORM bit in the U2CO register to 0 LSB first and the U2LCH bit in the U2C1 register to 0 not inverted When data are transmitted data set in the U2TB register are transmitted with the even numbered parity starting from DO When data are received received data are stored in the U2RB register starting from DO The even numbered parity determines whether a parity error occurs
276. hronous type when external clock is selected CKDIR Clock synchronous type CLK when internal clock is selected polarity reversing circuit CTS RTS selected CTS RTS disabled TS RTS disabled 50 from UART1 CRD VSS PCLK1 bit in the PCLKR register SMD2 to SMDO CKDIR bits in the UOMR register CLK1 to CLKO CKPOL CRD CRS bits in the UOCO register bit in the register Figure 13 1 UARTO Block Diagram n values set to the UOBRG register f1SIO or f28IO 18510 TXD polarity switching circuit Hanes Receive Transmit Clock source selection Clock sync type eception clock receive ircuit agi 001 0 00 0 circu E 2510 Internal U1BRG 18510 register UART transmission 010 100 101 110 Transmit 32510 Clock sync type 001 Clock synchronous type when internal clock is selected 0 Clock synchronous type CLK CLKMDO when internal clock is selected polarity 0 reversing circuit Clock output CTS RTS selected rS disabled CTST RTS1 P select CTSO CLKS1 0 CLKMD1 1 vss CRD n Values set to the U1BRG register PCLK1 bit in the PCLKR register SMD2 to SMDO CKDIR bits in the U1MR register CLK1 to CLKO CKPOL CRD CRS bits in the U1CO register CLKMDO CLKMD1 RCSP bits in the UCON register Figure 13 2 UART1 Block Diagram R01UH0197EJ0120 Rev 1 20 ztENESAS Page 127 of 331 Jul 21 2011 M16C 6B Group 13 Serial In
277. ided into block A and block B 00E000h OOEFFFh Block 00F000h OOFFFFh Block B 010000h Data flash Program ROM 2 013FFFh 0C0000h Block 3 64 Kbytes OCFFFFh 0D0000h Block 2 64 Kbytes OEDO00h Program ROM 1 Block 1 64 Kbytes OEFFFFh OF0000h Block 0 64 Kbytes OFFFFFh NOTES 1 To specify a block use an even address in that block 2 64 pin version only Figure 18 1 Flash Memory Block Diagram RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 252 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 1 1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an L signal is applied to the P5_5 pin and an H signal is applied to pins CNVSS In boot mode user boot mode or standard serial I O mode is selected in accordance with the data in the user boot code area Refer to 18 4 Standard Serial I O Mode for details 18 1 2 User Boot Function User boot mode can be selected by the status of a port when the MCU starts in boot mode Table 18 3 lists the User Boot Function Specifications Table 18 3 User Boot Function Specifications Item Specification Entry pin None or select a port from P5 to P10 User boot start level Select H or L User boot start address Address 10000h the start address of program ROM 2 Set UserBoot in ASCII code to the addresses 13FFOh to 13FF7h in the user boot code area and select a port for entry from addresses13FF8h to
278. idth 1000 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 301 of 331 M16C 6B Group 19 Electrical Characteristics VCC 2 2 input TAiOUT input TAiOUT input X Up down input During event counter mode input When count on falling th TIN UP tsu UP TIN edge is selected input l When count on rising edge is selected Two phase pulse input in event counter mode TAIIN input tsu TAIN TAOUT tsu TAIN TAOUT lt tsu TAOUT TAIN TAiOUT input tsu TAOUT TAIN Figure 19 6 Timing Diagram 1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 302 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics VCC 2 2 tsu D C k ta c Q su D C dics Figure 19 7 Timing Diagram 2 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 303 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics Table 19 28 Transceiver Transmission Characteristics VCC VCCRF 3 3 V VSS 0 V at 25 C unless otherwise specified Parameter Supply voltage Measuring Condition Standard IEEE802 15 4 Typ standard V Nominal output power 3 or more dBm Transmit bit rate 250 kbps Transmit chip rate 2 000 kchips s Programmable output power range 23 steps dB Harmonics 2nd harmonics TXO
279. idth Modulation Mode Standard Min 400 Max TAIIN input L pulse width R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 300 of 331 M16C 6B Group Timing Requirements 19 Electrical Characteristics VCC 2 2 V VCC 2 2 V VSS 0 V at 20 to 85 C 40 to 85 C unless otherwise specified Table 19 24 Timer A Input Counter Up Down Input in Event Counter Mode Parameter tc UP TAiOUT input cycle time Standard Min Max tw UPH TAiOUT input pulse width tw UPL TAiOUT input L pulse width tsu UP TIN TAiOUT input setup time th TIN UP TAiOUT input hold time Table 19 25 Timer A Input Two Phase Pulse Input in Event Counter Mode Parameter tc TA input cycle time Standard Min Max tsu TAIN TAOUT TAiOUT input setup time tsu TAOUT TAIN TAiIN input setup time Table 19 26 Serial Interface Parameter tc CK CLKi input cycle time Standard Min Max tw CKH CLKi input H pulse width tw CKL CLKi input L pulse width td C Q TXDi output delay time th C Q TXDi hold time tsu D C RXDi input setup time th C D RXDi input hold time Table 19 27 External Interrupt INTi Input Parameter INTi input H pulse width Standard Min 1000 Max INTI input L pulse w
280. if 1 is written 2 Set at least either the DAD bit or DSD bit to 0 address direction fixed Figure 11 4 Registers DMOCON to DM3CON Source Pointer i 0 to 3 b23 b19 b16 b15 b8 b7 b3 b7 b0 b7 bo Address After Reset 0182h to 0180h OXXXXXh 0192h to 0190h OXXXXXh 01A2h to 01A0h OXXXXXh 01B2h to 01BOh OXXXXXh Function Setting Range 00000h to FFFFFh p Lemme ee meee mee eee eee eee 1 If the DSD bit in the DMiCON register is 0 fixed write to this register when the DMAE bit in the DMiCON register is 0 DMA disabled If the DSD bit is 1 forward direction this register can be written to at any time If the DSD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written to it can be read Figure 11 5 Registers SARO to SAR3 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 91 of 331 Jul 21 2011 M16C 6B Group 11 DMAC Destination Pointer i 0 to 3 b23 b19 b16 b15 b8 b7 b3 b7 b0 b7 bo Symbol Address After Reset DARO 0186h to 0184h OXXXXXh DAR1 0196h to 0194h OXXXXXh DAR2 01A6h to 01A4h OXXXXXh DAR3 01B6h to 01B4h OXXXXXh Function Setting Range 00000h to FFFFFh pr sss L an a m a am an a s a aa aa an n e e n m m e a n m m NOTE 1 If the DAD bit in the DMiCON register is 0 fixed write to this register when the DMAE bit in the DMiCON
281. igure 16 1 shows the CRC Circuit Block Diagram Figure 16 2 shows Registers CRCD and CRCIN Figure 16 3 shows an Example of Using the CRC Operation Data bus high order Data bus low order Eight low order bits Eight high order bits CRCD register CRC code generating circuit X16 X12 4 X54 1 CRCIN register CQ Figure 16 1 CRC Circuit Block Diagram CRC Data Register b15 b8 b7 Symbol Address After Reset CRCD O3BDh to O3BCh Indeterminate Function Setting Range When data is written to the CRCIN register after setting the 4jinitial value in the register the CRC code can be 0000h to FFFFh read out from the CRCD register CRC Input Register b0 Symbol Address After Reset CRCIN OSBEh Indeterminate Function Setting Range Data input 00h to FFh Figure 16 2 Registers CRCD and CRCIN RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 240 of 331 Jul 21 2011 M16C 6B Group 16 CRC Operation Setup procedure and CRC operation when generating CRC code 80C4h CRC operation performed by the M16C CRC code remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial X X12 X5 1 1 0001 0000 0010 0001b Setting procedure 1 Reverse the bit positions of the value 80C4h by program in 1 byte units 80h 01h C4h 23h b15 2 Write 0000h initial
282. igure 7 1 Interrupt flag request accepted Address match Watchdog timer Oscillation stop and re oscillation detection Low voltage detection Figure 9 10 Interrupts Priority Select Circuit R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 75 of 331 M16C 6B Group 9 Interrupt 9 6 INT Interrupt INTi interrupt i 0 to 1 is triggered by the edges of external inputs The edge polarity is selected using the IFSRi bit 1 0 to 1 in the IFSR register Figure 9 11 shows the IFSR Register and Figure 9 12 shows the IFSR2A Register Interrupt Source Select Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset IFSR 0207h 00h Bit Symbol Bit Name Function INTO interrupt polarity switch 0 One edge bit 1 Both edges INT1 interrupt polarity switch 0 One edge bit 1 Both edges Eeseseeesen iecore dp 2 2 d22c2 222 2222 No register bits If necessary set to 0 Read as undefined value NOTE 1 When setting this bit to 1 both edges make sure the POL bit in registers INTOIC to INT1IC are set to O falling edge Figure 9 11 IFSR Register Interrupt Source Select Register 2 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset IFSR2A 0206h 00h i c ii i idi Reserved bits Set to 0 Interrupt request source select 0 Timer B3 ele 1 UARTO bus collision detection a Interrupt request source select 0 Timer B4
283. illation stop detection reset are available to reset the microcomputer 5 1 Hardware Reset The microcomputer resets pins the CPU and SFR by setting the RESET pin If the supply voltage meets the recommended operating conditions the microcomputer resets all pins the CPU and SFR when an L signal is applied to the RESET pin When the signal applied to the RESET pin changes low L to high H the microcomputer executes the program in an address indicated by the reset vector The 125 kHz on chip oscillator clock divided by 8 is automatically selected as a CPU clock after reset Refer to 4 Special Function Registers SFRs for SFR states after reset The internal RAM is not reset When an L signal is applied to the RESET pin while writing data to the internal RAM the internal RAM is in an indeterminate state Figure 5 1 shows an Example Reset Circuit Table 5 1 lists Pin Status When RESET Pin Level is L Figure 5 2 shows a Reset Sequence 5 1 1 Reset on a Stable Supply Voltage 1 Apply L to the RESET pin 2 Wait for 1 fOCO S x 20 3 Apply an signal to the RESET pin 5 1 2 Power on Reset 1 Apply L to the RESET pin 2 Raise the supply voltage to the recommended operating level 3 Insert td P R ms as wait time for the internal voltage to stabilize 4 Wait for I fOCO S x 20 5 Apply H to the RESET pin Recommended operation voltage 0 2 VCC
284. ime Standard Min Max tsu TAIN TAOUT TAiOUT input setup time tsu TAOUT TAIN TAiIN input setup time Table 19 16 Serial Interface Parameter tc CK CLKi input cycle time Standard Min Max tw CKH CLKi input H pulse width tw CKL CLKi input L pulse width td C Q TXDi output delay time th C Q TXDi hold time tsu D C RXDi input setup time th C D RXDi input hold time Table 19 17 External Interrupt INTi Input Parameter INTi input H pulse width Standard Min 380 Max INTI input L pulse width 380 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 295 of 331 M16C 6B Group 19 Electrical Characteristics VCC 3 3 V XIN input TAIIN input TAiOUT input TAiOUT input Up down input During event counter mode input When count on falling th TIN UP fsu UP TIN A edge is selected input When count on rising edge is selected Two phase pulse input in event counter mode TAIIN input tsu TAIN TAOUT tsu TAIN TAOUT Isu TAOUT TAIN TAiOUT input tsu TAOUT TAIN Figure 19 4 Timing Diagram 1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 296 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics VCC 3 3 V tsu D C k ta c Q su D C dics
285. in the UOCO register to 1 RTSO selected RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 150 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 1 8 bit Data Transmit Timing with a Parity and 1 Stop Bit The transfer clock stops once because an signal is applied to the CTS pin when the stop bit is verified The transfer clock resumes running as soon as an L signal is applied to the CTS pin Transfer clock TE bit in UiC1 register TI bit in UiC1 register Data is transferred from the UiTB register to the UARTi transmit register CTSi Parityl Stop bit TXDi TXEPT bit in UiCO register IR bit in SITIC register Set to 0 by an interrupt request acknowledgement or by program i Oto2 The above timing diagram applies to the case where the register bits are set as follows Tc 16 n 1 fj or 16 n 1 fEXT The PRYE bit in the UiMR register 1 parity enabled The STPS bit in the UiMR register 0 1 stop bit fj frequency of UiBRG count source f1SIO f2SIO f8SIO f32SIO The CRD bit in the UiCO register 0 CTS RTS enabled and the CRS bit 0 CTS selected frequency of UIBRG count source external clock The UIIRS bit in the UiC1 register 1 an interrupt request occurs when transmit completed n value set to UIBRG 2 9 bit Data Transmit Timing with No Parity and 2 Stop Bits Tc Transfer clock Q4 1 TE bit in SY UiC1 register 0
286. in code Code in ID code OMPA Dil Function serial the OFS1 stored address programmer address ALeRASE User ROM area all erase forced erase function Other than 1 ROM code ALeRASE 1 protect disabled 0 ROM code ID code check no ID match protect enabled Other than ALeRASE ID code check no ID match ALeRASE Other than ID code check ALeRASE 1 NOTE For the combination of the stored addresses is Protect refer to 18 2 4 Standard Serial I O Mode Disable Function 18 2 4 Standard Serial I O Mode Disable Function This function is available in standard serial I O mode When the ID codes in the ID code stored addresses are set to Protect in ASCII code refer to Table 18 7 Reserved Character Sequence Reserved Word the MCU does not communicate with a serial programmer Therefore the flash memory cannot be read written or erased by a serial programmer User boot mode can be selected when the ID codes set to Protect When the ID codes are set to Protect and the ROMCPI bit in the address OFSI is set to 0 ROM code protect enabled ROM code protection cannot be disabled by a serial programmer Therefore the flash memory cannot be read written or erased by a serial or parallel programmer RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 256 of 331 Jul 21 2011 18 Flash Memory M16C 6B Group 18 Flash Memory Option Function Select Address b7 b6 b5 b4 b3 b2
287. in an address determined by the reset vector The 125 kHz on chip oscillator clock divided by 8 is automatically selected as a CPU clock after reset In the watchdog timer reset the microcomputer does not reset a part of the SFRs Refer to 4 Special Function Registers SFRs for details The internal RAM is not reset When the watchdog timer underflows while writing data to the internal RAM the internal RAM is in an indeterminate state Refer to 10 Watchdog Timer for details 5 4 Oscillation Stop Detection Reset The microcomputer resets and stops pins the CPU and SFRs when the CM27 bit in the CM2 register is 0 reset when oscillation stop detected if it detects main clock oscillation circuit stop Refer to 7 6 Oscillation Stop and Re Oscillation Detect Function for details In the oscillation stop detection reset the microcomputer does not reset a part of the SFRs Refer to 4 Special Function Registers SFRs for details Processor mode remains unchanged since bits PMO1 to PMOO in the register are not reset RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 31 of 331 Jul 21 2011 M16C 6B Group 5 Reset 5 5 Internal Space Figure 5 3 shows CPU Register Status After Reset Refer to 4 Special Function Registers SFRs for SFR states after reset 0000h Data register RO 0000h Data register R1 0000h Data register R2 0000h Data register R3 0000h Address register A0 0000h Address registe
288. in the UCON register 2 The TXD2 pin is N channel open drain output No NCH bit in the U2CO register is assigned When write set to 0 3 Set the bits not listed above to 0 when writing to the registers 12 mode 4 When using UART1 in I2C mode and enabling the CTS RTS separate function of UARTO set the CRD bit in the register to 0 CTS RTS enabled and the CRS bit to 0 CTS input R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 158 of 331 M16C 6B Group 13 Serial Interface Table 13 12 Registers Used and Settings in I2C Mode 2 Register 0 2 4 and NODC Function Set to 0 Set to 0 CKPH Refer to Table 13 13 I2C Mode Functions Refer to Table 13 13 I2C Mode Functions DL2 to DLO Set the amount of SDAi digital delay Set the amount of SDAi digital delay STAREQ Set this bit to 1 to generate start condition Set to 0 RSTAREQ Set this bit to 1 to generate restart condition Set to 0 STPREQ Set this bit to 1 to generate stop condition Set to 0 STSPSEL Set this bit to 1 to output each condition Set to 0 ACKD Select ACK or NACK Select ACK or NACK ACKC Set this bit to 1 to output ACK data Set this bit to 1 to output ACK data SCLHI Set this bit to 1 to have SCLi output stopped when stop condition is detected Set to 0 SWC9 Set to 0 Set this bit to 1 to set the SCLi to L hold at the f
289. ion This bit is read as the result corresponding to the receive RAM bank specified with the RCVBANKSEL bit in the BBTXRXMODES register Transmit Receive Status Register 1 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address BBTXRXST1 010Fh 2 a indidit 0 Normal no unlock 1 UNLOCKST Unlock receive status bit 1 Abnormal unlock occurred No register bits If necessary set to 0 Read as 0 b7 b1 1 This bit corresponds to the receive RAM bank Figure 15 25 Transmit Receive Status Register 1 Configuration After Reset 00h R01UH0197EJ0120 Rev 1 20 434 NESAS Jul 21 2011 Page 220 of 331 M16C 6B Group 15 Baseband Functionality 15 2 17 RF Control Register The RFPWRON bit is used to control the powering ON of the RF block After setting 1 in the RFPWRON bit IDLE status is selected after the wait time set in the BBIDLEWAIT register has elapsed The wait time set in the BBIDLEWAIT register is automatically counted with XIN as the count source and an IDLE interrupt request is generated after the startup time to IDLE status has been waited From OFF status make sure to transit to CCA reception or transmission status via this IDLE status While in IDLE status set 1 operation start in bits RCVTRG TRNTRG and CCATRG in the BBTXRXCON register and CSMAST bit in the BEBCSMACONO register After setting 1 in the XINPWRON bit the startup of the clock regulator is completed after the wait time set in
290. ion Overview of Oscillation Stop and Re Oscillation Detect Function Table 7 7 Specification Overview of Oscillation Stop and Re Oscillation Detect Function Item Specification Oscillation stop detectable clock and frequency bandwidth f XIN gt 2 MHz Enabling condition for oscillation stop re oscillation detect function Set 20 bit to 1 enabled Operation at oscillation stop re oscillation detection Reset occurs when CM27 bit 0 e Oscillation stop re oscillation detection interrupt generated when CM27 bit 1 7 6 1 Operation When CM27 bit 0 Oscillation Stop Detection Reset When main clock stop is detected when the CM20 bit is 1 oscillation stop re oscillation detection function enabled the microcomputer is initialized coming to a halt Oscillation stop reset Refer to 4 Special Function Registers SFRs and 5 Reset This status is reset with hardware reset Also even when re oscillation is detected the microcomputer can be initialized and stopped it is however necessary to avoid such usage During main clock stop do not set the 20 bit to 1 and the CM27 bit to 0 7 6 2 Operation When CM 27 bit 1 Oscillation Stop and Re oscillation Detect Interrupt When the main clock corresponds to the CPU clock source and the CM20 bit is 1 oscillation stop and re oscillation detect function enabled the system is placed in the following state if the main clock comes to a halt
291. ion in standard serial I O mode The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match If the ID codes do not match commands sent from the serial programmer are not accepted However if the four bytes of the reset vector are ID codes not compared allowing all commands to be accepted The ID codes are 7 byte data stored consecutively starting with the first byte into addresses OFFFDFh OFFFE3h OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh The flash memory must have a program with the ID codes set in these addresses The reserved character sequence of the ASCII codes ALeRASE is used for forced erase function The reserved character sequence of the ASCII codes Protect is used for standard serial I O mode disabled function Table 18 7 lists the Reserved Character Sequence Reserved Word When the ID codes stored in the ID code addresses in the user ROM area are set to the ASCII codes ALeRASE as the combination table listed in Table 18 7 forced erase function becomes active When the forced erase function or standard serial I O mode disabled function is not used use another combination of the ASCII codes Table 18 7 Reserved Character Sequence Reserved Word Reserved word combination of ID Code ID Code Address ASCII ALeRASE Protect 50h upper case P 72h lower case r 6Fh lower case 0 74h lower case t 65h lower case e 63h low
292. ion to become 1 Other than those above FMRO01 CPU rewrite mode select bit b1 Commands can be accepted by setting the FMRO1 bit to 1 CPU rewrite mode enabled To set the FMRO1 bit to 1 write 0 and then 1 in succession Make sure no interrupts or DMA transfers will occur before writing 1 after writing 0 Change the FMRO1 bit when the PM24 bit in the PM2 register is 0 NMI interrupt disabled or low is input to the NMI pin While in EWO mode write to this bit from a program in the RAM Enter read array mode and then set this bit to 0 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 260 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory FMRO 2 Lock bit disable select bit b2 The lock bit is disabled by setting the FMRO2 bit to 1 lock bit disabled Refer to 18 3 5 Data Protect Function The 2 bit does not change the lock bit data but disables the lock bit function If an erase command is executed when the 2 bit is set to 1 the lock bit data status changes from 0 locked to 1 unlocked after command execution is completed To set the FMRO2 bit to 1 write 0 and then 1 in succession when the bit is 1 Make sure no interrupts or DMA transfers will occur before writing 1 after writing 0 Do not change the FMR02 bit while programming or erasing FMSTP Flash memory stop bit b3 The FMSTP bit resets flash memory control circuits and minimizes current consumption in the flash memory A
293. ircuit Specifications Subclock Oscillation Circuit CPU clock source Clock source for timer A and B 125 kHz On Chip Oscillator CPU clock source Peripheral function clock source CPU and peripheral function clock sources when the main clock stops oscillating Clock frequency 16 MHz fixed 32 768 kHz About 125 kHz Usable oscillator Crystal oscillator Crystal oscillator Pins to connect oscillator XIN XOUT XCIN XCOUT Oscillation stop restart function Presence Presence Presence Oscillator status after reset Oscillating Stopped Oscillating Other NOTE Externally derived clock can be input 1 The main clock is fixed to 16 MHz since it is also used as the reference clock for the transceiver Select the crystal oscillator so that the allowed frequency tolerance should be 40 ppm or less R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 36 of 331 M16C 6B Group 7 Clock Generation Circuit CM01 to CMOO 00b Subclock ports oscillation circuit PMO1 to PMOO 00b CMO1 to CMOO O11 DN XCIN XCOUT 1 to PMOO 00b CMO1 to CMOO 10b CLKOUT o 1 to PMOO 00b C32 CMO1 to CMOO 11b 1 32 A P Subclock T 125 kHz 125 kHz on chip on chip oscillator oscillator clock Oscillation 1060 5 Stop re oscillation detection circuit
294. it is reloaded the value FFFFh is read Also if the counter is read before it starts counting after a value is set in the TAi register while not counting the set value is read RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 315 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 7 1 2 Timer A Event Counter Mode The timer is stopped after reset Set the mode count source counter value and others using the TAiMR register the TAi register the UDF register bits TAZIE TAOTGL and TAOTGH in the ONSF register and the TRGSR register and TAPOS register before setting the TAiS bit in the TABSR register to 1 count starts i 0 to 4 Always make sure the TAiMR register the UDF register bits TAZIE TAOTGL and TAOTGH in the ONSF register the TRGSR register and TAPOFS register are modified while the TAiS bit is 0 count stops regardless of whether after reset or not While counting is in progress the counter value can be read out at any time by reading the TAi register However while reloading FFFFh can be read in underflow and 0000h in overflow When the counter is read before it starts counting after a value is set in the TAi register while not counting the set value is read RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 316 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 7 1 3 Timer A One Shot Timer Mode The timer is stopped after reset Set the mode count source counter value and others using the TAiMR register t
295. ite data high order word 16 bits BA Highest order block address even address x Given even address in the program ROM 1 program ROM 2 and data flash xx Eight high order bits of command code ignored 18 3 4 1 Read Array Command The read array command reads the flash memory By writing the command code xxFFh in the first bus cycle read array mode is entered Content of a specified address can be read in 16 bit units by entering an address to be read after the next bus cycle The microcomputer remains in read array mode until another command is written Therefore contents from multiple addresses can be read consecutively 18 3 4 2 Read Status Register Command The read status register command reads the status register By writing the command code xx70h in the first bus cycle the status register can be read in the second bus cycle refer to 18 3 6 Status Register Read an even address in the program ROM program ROM 2 and data flash Do not execute this command in EW1 mode R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 267 of 331 M16C 6B Group 18 Flash Memory 18 3 4 3 Clear Status Register Command The clear status register command clears the status register By writing xx50h in the first bus cycle bits FMRO7 and FMRO6 in the FMRO register are set to 00b and bits SR5 and SR4 in the status register are set to 00b 18 3 4 4 Program Command The program command wr
296. ited Instructions Do not use the following instructions in EWO mode UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 18 6 3 4 Interrupts EWO Mode and EW1 Mode Do not use an address match interrupt during command execution because the address match interrupt vector is located in ROM Do not use a non maskable interrupt during block 0 erase because the fixed vector is located in block 0 18 6 3 5 Rewrite EWO mode If the power supply voltage drops while rewriting the block where the rewrite control program is stored the rewrite control program is not correctly rewritten This may prevent the flash memory from being rewritten If this error occurs use standard serial I O mode or parallel I O mode for rewriting 18 6 3 6 Rewrite EW1 mode Do not rewrite any blocks in which the rewrite control program is stored RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 284 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 6 3 7 Transfer In EW1 mode do not generate a DMA transfer while the FMROO bit in the FMRO register is set to 0 auto programming or auto erasing 18 6 3 8 Wait Mode To enter wait mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction 18 6 3 9 Stop Mode To enter stop mode set the FMROI bit to 0 CPU rewrite mode disabled and then disable DMA transfer before setting the CM10 bit in the re
297. ites 2 word 4 bytes data to the flash memory By writing xx41h in the first bus cycle and data to the write address in the second and third bus cycles an auto program operation data program and verify will start Set the end of the write address to Oh 4h 8h or Ch The FMROO bit in the FMRO register indicates whether an auto program operation has been completed The FMRODO bit is set to 0 busy during auto program and to 1 ready while in an auto program operation After the completion of an auto program operation the FMRO6 bit in the FMRO register indicates whether or not the auto program operation has been completed as expected Refer to 18 3 7 Full Status Check An address that is already written cannot be altered or rewritten Figure 18 8 shows a Flow Chart of the Program Command Programming The lock bit protects each block from being programmed inadvertently Refer to 18 3 5 Data Protect Function In EW1 mode do not execute this command on the block to which the rewrite control program is allocated In EWO mode the microcomputer enters read status register mode as soon as an auto program operation starts The status register can be read The SR7 bit in the status register is set to 0 at the same time an auto program operation starts It is set to 1 when the auto program operation is completed The microcomputer remains in read status register mode until the read array command is written After completion of an auto program o
298. its or 16 bits Transfer address direction Forward or fixed The source and destination addresses cannot both be in the forward direction Transfer mode Single transfer Transfer is completed when the DMAi transfer counter underflows Repeat transfer When the DMAi transfer counter underflows it is reloaded with the value of the transfer counter reload register and a DMA transfer is continued with it DMA interrupt request When the DMAi transfer counter underflowed generation timing DMA transfer start Data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMAiCON register 1 enabled DMA transfer Single transfer When the DMAE bit is set to 0 disabled stop After the DMAi transfer counter underflows Repeat transfer When the DMAE bit is set to 0 disabled Reload timing for forward When a data transfer is started after setting the DMAE bit to 1 enabled the forward address pointer and DMAi address pointer is reloaded with the value of the SARi or DARi pointer whichever is transfer counter specified to be in the forward direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register DMA transfer cycles Minimum 3 cycles between SFR and internal RAM i20to3 NOTES 1 DMA transfer is not effective to any interrupt DMA transfer is affected neither by the I flag nor by the interrupt control
299. l Mode Register 2 i 0 to 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address UOSMR2 U1SMR2 U2SMR2 0246h 0256h 0266h After Reset X0000000b LE MN Refer to Table 13 13 I2C Mode 2 IICM2 2C mode select bit 2 Functions 0 Disabled Clock synchronization bit 1 Enabled 0 Disabled 1 Enabled TEE 0 Disabled STAC initialization bit 1 Enabled 0 Transfer clock SWC2 SCL wait output bit 2 1 L output 0 Enabled 1 Disabled high impedance SDA output stop bit 0 Disabled SCL output bit 1 Enabled SDHI SDA output disable bit No register bit If necessary set to 0 Read as undefined value Figure 13 12 UOSMR2 to U2SMR2 Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 137 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Special Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset UOSMR3 U1SMR3 U2SMR3 0245h 0255h 0265h 000X0X0Xb Bit Symbol Bit Name Function RW No register bit If necessary set to 0 Read as undefined value 0 Without clock delay Clock phase set bit 1 With clock delay No register bit If necessary set to 0 Read as undefined value 0 CLKi is CMOS output Clock output select bit 4 GLKi is N channel open drain output No register bit If necessary set to 0 Read as undefined value Without delay 1 to 2 cycle s of UiBRG count source 2 to cycles o
300. l circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is
301. l count source Event Counter Mode The timer counts underflows of other times 0105 j i t however j 2 0 5 TBj R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 120 of 331 M16C 6B Group 12 Timers Timer Bi Mode Register i 0 to 5 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset LI Xel I TBOMR to TB2MR 033Bh to 033Dh 00XX0000b TB3MR to TBSMR 031Bh to 031Dh 00XX0000b NEN b1 bO 0 0 Timer mode Operation mode select bit 0 4 Event counter imode 1 x Do not set b3 b2 Reserved bits Set to 0 No register bit If necessary set to 0 Read as undefined value OX Go I ULT Function varies with each operation mode Count source select bit Function varies with each operation mode 1 Valid when the TCS3 bit or TCS7 bit in registers TACSO to TACS2 is set to 0 TCKO TCK1 enabled Timer Bi Register i 0 to 5 b15 b8 b7 bO Z 50 Symbol Address After Reset TBO 0331h to 0330h Indeterminate TB1 0333h to 0332h Indeterminate TB2 0335h to 0334h Indeterminate TB3 0311h to 0310h Indeterminate TB4 0313h to 0312h Indeterminate TB5 0315h to 0314h Indeterminate mm idu Timer mode Divide the count source by n 1 where 0000h to FFFFh n set value Event co hter mode Divide the count source by n 1 where 0000h to FFFFh n set value NOTES 1 Access to the register in 16 bit units 2 The timer counts overflows or und
302. lation stop or a re oscillation detection interrupt is not generated Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re oscillation detection interrupt routine This bit is valid when the CMO7 bit in the CMO register is set to 0 When the PM21 bit in the PM2 register is set to 1 disable clock modification this bit remains unchanged even if writing to the CM20 bit Set the CM20 bit to 0 disabled before entering stop mode Exit stop mode before setting the CM20 bit back to 1 enabled Set the CM20 bit in the CM2 register to O disabled before setting the CMO5 bit in the CMO register to 1 main clock stops Bits CM20 CM21 and CM27 remain unchanged at the oscillation stop detection reset When the CM21 bit is set to 0 main clock and the CMO5 bit is set to 1 main clock stops the CMO6 bit fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capacity high Figure 7 4 CM2 Register R01UHO197EJ0120 Rev 1 20 ztENESAS Page 40 of 331 Jul 21 2011 M16C 6B Group Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbo ojoo ojojo 0012h 7 Clock Generation Circuit After Reset 00000011b Function Timers A and B clock select bit clock source for Timers A OUE TIMAS PCLKO and B 1 f1TIMAB SI O clock select bit clock source for UARTO to UART2 0 1251 1 1151 Reserved bits S
303. le eaput Rr HIERRO EU REUTERS re REPRE QA 237 15 3 4 CSMA CA Procedure Example etre ttn UU UH UR Up m te ots 237 15 3 5 Baseband Startup Procedure Example sessi enne nennen trennen 238 15 3 6 Baseband Shutdown Procedure Example sese 238 15 3 7 Examples of Automatic Transmit and Receive Operations eseeeeeeeeeee 239 16 CRC Operat OM ou tete leue D tu te OI VE 240 17 Programmable W O Ports ssssssseeeeenneen nen eene nnne 242 17 1 Port Pi Direction Register PDi Register i 5 to 8 10 sese 242 17 2 Port Pi Register Pi Register i 5 to 8 10 en nre enne 242 17 3 Pull up Control Register 1 to Pull up Control Register 2 Registers PURI to PUR2 242 17 4 LED Port Switch Register LEDCON Register eere 242 18 Flash M mory ie beth biet e tena s ai iaasa A aaie asian 251 18 1 Memory Mappe ERE CRUS ded sad cae ERR ieee span E REED Se IEEE HI ERE VERRE CERE 252 18 11 du I 253 18 12 User Boot F nction eve ea eee eben e 253 18 2 Functions to Prevent Flash Memory from Rewriting 255 18 2 1 ROM Code Protect Function 5 e rete tte e ir tee re EE e nti pest 255 18 22 WD Code Check Function stet tite tt e tete 255 18 2 3 Forced Erase Function 2 p E
304. le bit 1 Output enabled 7 1 The UiLCH bit enabled when bits SMD2 to SMDO in the UiMR register are set to 001b clock synchronous serial mode 100b UART mode 7 bit transfer data or 101b UART mode 8 bit transfer data Set this bit to 0 when bits SMD2 to SMDO are set to 010b 12C mode or 110b UART mode 9 bit transfer data Figure 13 8 U0C1 U1C1 Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 133 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface UART2 Transmit Receive Control Register 1 b7 b6 b5 b4 b3 b2 61 bO Symbol Address After Reset U2C1 026Dh 00000010b i ids Tranemit anable bit 0 Transmission disabled 1 Transmission enabled 0 Data present U2TB register Transmit buffer empty flag 1 No data present in U2TB register B Receive enable bit 0 Reception disabled 1 Reception enabled 0 No data present in U2RB register Receive complete flag 1 Data present in U2RB register UART2 transmit interrupt 0 U2TB register empty TI 1 source select bit 1 Transmit completed TXEPT 1 UART2 continuous receive 0 Continuous receive mode disabled mode enable bit 1 Continuous receive mode enabled 0 No reverse 1 U2LCH Data logic select bit 1 Reverse 0 Output disabled U2ERE Error signal output enable bit 1 Output enabled 1 The U2LCH bit is enabled when bits SMD2 to SMDO the U2MR register are set 001b clock synchronous serial I
305. lect function i Oto2 NOTES Arbitration lost Timing at which the ABT bit in the register is updated can be selected SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable Clock phase setting With or without clock delay selectable 1 When an external clock is selected the conditions must be met while the external clock is in H state 2 If an overrun error occurs the received data of the register will be indeterminate The IR bit in the SiRIC register does not change R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 156 of 331 M16C 6B Group 13 Serial Interface Start and stop condition generation block STSPSEL 1 Delay 1 0 SDA STSP DMAO to DMAS request circuit SCL STSP STSPSEL 0 2 1 Transmission UARTI transmit ACKC 1 register o NACK interrupt request 1 and IICM2 0 DMAO DMA2 request gt Noise 1 filter IICM2 1 Reception a UARTI receive register ACK interrupt request ICM 1 and DMA1 DMAS request Start condition icis detection Stop condition detection Falling edge detection CLK Start stop condition detection STSPSEL External control interrupt request Noise 1 clock ESI gt 9th bit falling edge Sex SWC This diagram applies to the case where bits SMD2 to SMDO in the UiMR register 010b and the bit in the UISMR register 1 bit i
306. lect one pin from ANO to AN7 Reading of result of A D converter Read one of the registers ADO to AD7 that corresponds to the selected pin R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 183 of 331 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 0 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset ADCONO 03D6h 00000XXXb Select Select AN1 Select AN2 Select AN3 Select AN4 RW Select AN5 Select AN6 RW RW RW Analog input pin select bit 00008 00 0079 o 0 oO 00 Select AN7 A D operation mode select 64 b3 bit 0 0 1 Repeat mode RW Reserved bit Set to 0 m 0 A D conversion stop INE conversion start iag 1 A D conversion start m Frequency select bit 0 Refer to NOTE 2 of the ADCON2 Register NOTE 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 5 p4 b3 b2 bi bo Symbol Address After Reset ADCON1 03D7h 0000X000b A D sweep pin select bit Invalid in repeat mode RW n Gperationmode select Set to 0 when repeat mode is selected No register bit If necessary set to 0 Read as undefined value e Frequency select bit 1 Refer to NOTE 2 of the ADCON2 Register RW R o A D standby bit 2 Set to 1 A D operation enabled NOTES 1 If the ADCON1 register is rewritten during A D conversion the co
307. led 1 Received data present 0 No pending RCVPEND Receive pending bit 1 Pending m RCVBANKST Receive bank pointer bit 0 Bank 0 1 Bank 1 1 This bit corresponds to the receive RAM bank RCVBANK1 Receive bank 1 status bit Figure 15 17 Transmit Receive Status Register 0 Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 214 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 9 Transmit Frame Length Register The frame length value for transmission is written into this register The total of the payload data length and CRC length 2 bytes is set as the frame length value While the transmit frame length is equal to or less than 04h do not set 1 in the TRNTRG bit in the BBTXRXCON register or the CSMAST bit in the BBCSMACONO register transmission start or automatic CSMA CA start Only the ACK automatic response function enables the transmission of an ACK frame regardless of the transmit frame length Transmit Frame Length Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address BBTXFLEN 0108h i di eee TXFLEN Transmit frame length Indicates the frame length for transmission b7 No register bit If necessary set to 0 Read as 0 Figure 15 18 Transmit Frame Length Register Configuration After Reset 00h RO1UH0197EJ0120 Rev 1 20 tENESAS Jul 21 2011 Page 215 of 331 M16C 6B Group 15 Baseband Functionality 15 2 10 Transmit Receive Mode Register 2 For tran
308. led all frames transmitted transmission unlock detection 1 Stop after unlock detection 0 Disabled all frames received 1 Stop after unlock detection transit to reception standby Operation stop enable bit after UNLOCKSTRR reception unlock detection Bank 0 reception complete 0 Bank 0 reception complete interrupt eer IDLE interrupt select bit 1 IDLE interrupt Batis reception complete 0 Bank 1 reception complete interrupt BANK1INTSEL clock regulator interrupt select 7 bit 1 Clock regulator interrupt Reserved bits Set to 0 Figure 15 27 Transmit Receive Mode Register 4 Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 222 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 19 CSMA Control Register 1 The NB bit is used to set the value of macMaxCSMA Backoff shown in Figure 15 5 The initial value is 04h The BEMIN bit is used to set the value of macMinBE shown in Figure 15 5 The initial value is 03h The CW bit is used to set the value of CW shown in Figure 15 5 The initial value is 02h CSMA Control Register 1 b7 b6 b5 b4 b3 b2 b1 bO Symbol Address as BBCSMACON1 0112h LENIN _ mw NB bit Sets the value of macMaxCSMABackoff BEMIN bit Sets the value of macMinBE EB CW bit Sets the value of CW a Figure 15 28 CSMA Control Register 1 Configuration 15 2 20 CSMA Control Register 2 The BEMAX bit is used to set the value of macMaxBE shown in Figu
309. lue when the power input to the antenna is 0 dBm the value read from the RSSI CCA result register can be adjusted to 00h when the input power is the same level by setting EBh EEh 3h in the RSSI offset register beforehand RSSI Offset Register b7 bO Symbol Address After Reset eenssors 013D EEN Bit Symbol Bit Name Function RSSIOFS RSSI offset bit Sets an offset value of RSSI E Figure 15 40 RSSI Offset Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 232 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 32 Verification Mode Set Register This register can be used to set the verification mode necessary to obtain conformance certifications for technological standards By setting the CONTTX bit to and then the TRNTRG bit in the BBTXRXCON register to 1 transmission start continuous transmit mode is selected In this mode frame transmission is repeated for the number of the BBTXFLEN setting value 2 bytes The content of the frame to be transmitted is the value written into transmit RAM Frame length value for transmission must be equal to or greater than O5h The NOMOD bit can be used to switch a modulation or non modulation signal When transmitting a non modulation signal set 00h to address 00164h and 3Fh to address 00165h By setting the CONTRX bit to 1 and then the RCVTRG bit in the BBTXRXCON register 1 reception start continuous receive mode is selected In this m
310. me by program Do not access the flash memory during this wait time Before entering wait mode or stop mode be sure to set the FMR01 bit to 0 Y Set the FMRO 1 bit to 0 CPU rewrite mode disabled Y7 Set the FMSTP bit to 0 flash memory operation v Wait until the flash memory stabilizes tPS 9 v Jump to a desired address in the flash memory Figure 18 7 Processing Before and After Low Power Consumption Mode or On Chip Oscillator Low Power Consumption Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 266 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 4 Software Commands Software commands are described below Read and write the command code and data in 16 bit units from and to even addresses in the program ROM 1 program ROM 2 and data flash When the command code is written the 8 high order bits D15 to D8 are ignored Table 18 10 Software Commands First Bus Cycle Data D15to DO Command Read Array Second Bus Cycle Third Bus Cycle Mode Address Mode Address Data D15to DO Mode Address Data D15to DO Read Status Register Clear Status Register Program Block Erase Lock Bit Program Read Lock Bit Status Block Blank Check SRD Data in the status register D7 to DO WA Write address Set the end of the address to Oh 4h 8h or Ch WDO Write data low order word 16 bits WD1 Wr
311. ment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain
312. mer B4 Interrupt Control Register UART1 BUS Collision Detection Interrupt TB4IC UTBONIC XXXXX000b Control Register Timer B3 Interrupt Control Register UARTO BUS Collision Detection Interrupt TB3IC UOBCNIC XXXXX000b Control Register Timer Compare 0 Interrupt Control Register BBTIMOIC XXXXX000b Timer Compare 1 Interrupt Control Register BBTIM1IC XXXXX000b UART2 BUS Collision Detection Interrupt Control Register BCNIC XXXXX000b DMAO Interrupt Control Register DMOIC XXXXX000b Interrupt Control Register DM1IC XXXXX000b Key Input Interrupt Control Register KUPIC XXXXX000b A D Conversion Interrupt Control Register 2 ADIC XXXXX000b UART2 Transmit Interrupt Control Register S2TIC XXXXX000b UART2 Receive Interrupt Control Register S2RIC XXXXX000b UARTO Transmit Interrupt Control Register SOTIC XXXXX000b UARTO Receive Interrupt Control Register SORIC XXXXX000b UART1 Transmit Interrupt Control Register S1TIC XXXXX000b UART1 Receive Interrupt Control Register XXXXX000b Timer AO Interrupt Control Register TAO XXXXX000b Timer A1 Interrupt Control Register TA1 XXXXX000b Timer A2 Interrupt Control Register TA2 XXXXX000b Timer Interrupt Control Register XXXXX000b Timer A4 Interrupt Control Register TA4 XXXXX000b Timer BO Interrupt Control Register TBO XXXXX000b Timer B1 Interrupt Control Register TB1 XXXXX000b Timer B2 Interrupt Control Register TB2 XXXXX000b INTO Interrupt Control Register INTOIC XX00X000b INT1 Interrupt Control Register
313. mode bits FMR22 and FMR23 are both 1 20 10 3 11 Program and Erase Cycles and Execution Time Execution time of the program block erase and lock bit program commands becomes longer as the number of programming and erasing increases 20 10 3 12Suspending the Auto Erase and Auto Program Operations When the program block erase and lock bit program commands are suspended the blocks for those commands must be erased Execute the program and lock bit program commands again after erasing Those commands are suspended by the following reset or interrupts Reset NMI watchdog timer oscillation stop restart detect 20 10 4 User Boot Mode 20 10 4 1 Location of User Boot Mode Program Allocate a program which is invoked and executed in user boot mode only in program ROM 2 do not execute the program which is allocated in data flash or program ROM 1 in user boot mode 20 10 4 2 Entering User Boot Mode After Standard Serial I O Mode To use user boot mode after standard serial I O mode turn off the power when exiting standard serial I O mode and then turn on the power again cold start The MCU enters user boot mode under the right conditions R01UHO197EJ0120 Rev 1 20 ztENESAS Page 327 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 11 Noise Connect a bypass capacitor across pins VCC and VSS using the shortest and thicker possible wiring Figure 20 4 shows the Bypass Capacitor Connection M16C 6B Group Conn
314. must be the same highest order address of a block specified in the second bus cycle Figure 18 10 shows a Flow Chart of the Lock Bit Program Command Programming Execute read lock bit status command to read lock bit state lock bit data The bit in the FMRO register indicates whether a lock bit program operation is completed Refer to 18 3 5 Data Protect Function for details on lock bit functions and how to set it to 1 unlocked Write the command code xx77h to the highest order block address Write xxDOh to the highest order block address Full status check Lock bit program operation completed 1 Write command codes and data to even addresses NOTE Figure 18 10 Flow Chart of the Lock Bit Program Command RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 270 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 4 7 Read Lock Bit Status Command The read lock bit status command reads the lock bit state of a specified block By writing xx71h in the first bus cycle and xxDOh in the second bus cycle to the highest order even address of a block the FMR16 bit in the FMRI register stores information on the lock bit status of a specified block Read the FMR16 bit after the FMROO bit in the FMRO register is set to 1 ready Figure 18 11 shows a Flow Chart of the Read Lock Bit Status Command Programming Write xxDOh to the highest order block address YES Block locked Block not locked NOTE 1 Write comm
315. n S2TIC register Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where data is transmitted in the direct format The STPS bit in the U2MR register 0 1 stop bit TC 16 1 fior 16 n 1 fEXT The PRY bit in the U2MR register 1 even parity fi frequency of U2BRG count source 1510 f2SIO f8SIO 32510 The UFORM bit in the U2CO register 0 LSB first fEXT frequency of U2BRG count source external clock The U2LCH bit in the U2C1 register 0 no reverse q y The U2IRS bit in the U2C1 register 1 transmit completed n value set to U2BRG 2 Receive Timing Te Transfer clock l RE bit in 1 U2C1 register 1 Parity Stop Transmit waveform bit bit from transmitting end TXD2 TXD2 provides L aa due to a parity error RXD2 pin level 9 bs 01X D2 03K D4 D5X DEX 7X P 6 RI bit in U2C1 register oe l Read the U2RB register IR bit in 2 S2RICregister cm p Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where data is TC 16 n 1 fi or 16 n 1 fEXT m fi frequency of U2BRG count source f1SIO 12910 f8SIO 32510 The PRY bit in the U2MR register 1 even parity fEXT frequency of U2BRG count source external clock The UFORM bit in the U2CO register 0 LSB first n value
316. n Circuit System Clock Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset CM1 0007h 00100000b Bit Symbol Bit Name Function 0 Clock on 1 All clocks off stop mode b3 b b1 Reserved bits Set to 0 CM14 125 kHz on chip oscillator 0 125 kHz on chip oscillator on stop bit 7 1 125 kHz on chip oscillator off XIN ZOUT drive capacity Low b7 b6 Main clock divisi lect 0 0 No division mode ain clock division seleci 0 1 Divide by 2 mode bit 1 9 VES CM17 1 0 Divide by 4 mode 1 1 Divide by 16 mode Rewrite this register after setting the PRCO bit in the PRCR register to 1 write enabled When entering stop mode or the CMO5 bit is set to 1 main clock stops in low speed mode the CM15 bit is set to 1 drive capacity high This bit is valid when the CMO6 bit is set to 0 bits CM16 and CM17 enabled If the CM10 bit is set to 1 stop mode XOUT is held and the internal feedback resistor is disconnected Pins XCIN and XCOUT are in high impedance state When the CM20 bit in the CM2 register is set to 1 oscillation stop detection function enabled do not set the CM10 bit to 1 When the PM21 bit in the PM2 register is set to 1 disable clock modification this bit remains unchanged even if writing to CM10 bit When the CSPRO bit in the CSPR register is set to 1 count source protection mode this bit remains unchanged even if writing to the CM10 bit The CM14 bit can be set t
317. n the register IICM2 SWC ALS SWC2 SDHI bits in the UISMR2 register STSPSEL ACKC bits in the UiSMR4 register i Oto2 The above applies to the case where the IICM bit 1 the pin can be read even if the port direction bit corresponding to the SCLi pin 1 output mode Figure 13 27 12 Mode Block Diagram RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 157 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Table 13 11 Register 0 to 7 Registers Used and Settings in I2C Mode 1 Function Set transmission data Set transmission data 0 to 7 Reception data can be read Reception data can be read 8 ACK or NACK is set in this bit ACK or NACK is set in this bit ABT Arbitration lost detection flag Invalid OER Overrun error flag Overrun error flag 0 to 7 Set a bit rate Invalid SMD2 to SMDO Set to 010b Set to 010b CKDIR Set to 0 Set to 1 IOPOL Set to 0 Set to 0 CLK1 CLKO Select the count source for the UiBRG register Invalid CRS Invalid because CRD 1 Invalid because CRD 1 TXEPT Transmit register empty flag Transmit register empty flag CRD 4 Set to 1 Set to 1 NCH Set to 1 2 Set to 1 2 CKPOL Set to 0 Set to 0 Set to 1 Set to 1 TE Set this bit to 1 to enable transmission Set this bit to 1 to enable transmission TI
318. n until the operation is completed R01UH0197EJ0120 Rev 1 20 ztENESAS Page 259 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 3 Flash Memory Control Register Registers FMRO FMR1 FMR2 and FMR6 18 3 3 1 Flash Memory Control Register 0 FMRO Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset FMRO 0220h 00000001b Other than user boot mode 00100000b User boot mode im FMROO RY BY status flag 0 Busy being written or erased 1 Ready CPU rewrite mode select 0 CPU rewrite mode disabled bit 1 CPU rewrite mode enabled 0 Lock bit enabled Lock bit disable select bit 1 Lock bit disabled 0 Flash memory operation enabled Flash memory stop bit 1 Flash memory operation stopped low power mode flash memory initialized Reserved bits Set to 0 Reserved bits Set to 0 in other than user boot mode b5 Set to 1 in user boot mode FMR06 Program status flag normally 1 Terminated in error FMR07 Erase Status Flag Terminated normally 1 Terminated in error FMROO RY BY status flag b0 This bit indicates the flash memory operating state Condition to become 0 During the following commands execution Program block erase lock bit program read lock bit status and block blank check Flash memory stopped FMSTP is 1 e During restart operation when FMSTP is set to 0 after it is set to 1 Condit
319. ncluded Each time a DMA request occurs the DMAC transfers one 8 or 16 bit data from the source address to the destination address The DMAC uses the same data bus as used by the CPU Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method it can transfer one word 16 bits or one byte 8 bits of data within a very short time after a DMA request is generated Figure 11 1 shows the DMAC Block Diagram Table 11 1 lists the DMAC Specifications Figures 11 2 to 11 6 show the DMAC related registers Address bus DMAO source pointer SARO 20 addresses 0199h 0198h DMAt transfer counter TCR1 16 transfer counter reload register TCR2 16 Lo rel U addresses 01A9h 01A8h DMA2 transfer counter TCR2 16 DMAS transfer counter reload register TCR3 16 Lo U addresses 01B9h 01B8h DMAGS transfer counter TCR3 16 Lo Data bus low order bits Data bus high order bits 1 Pointer is incremented by a DMA request Figure 11 1 DMAC Block Diagram RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 87 of 331 Jul 21 2011 M16C 6B Group 11 DMAC A DMA request is generated by a write to the DSR bit in the DMiSL register i 0 to 3 as well as by an interrupt request which is generated by any function specified by bits DMS and DSEL4 to DSELO in the DMiSL register However unlike in the case of interrupt requests DMA requests are not affected by the I flag and
320. nd STPREQ from 0 to 1 20 8 4 Special Mode 4 SIM Mode A transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2CI register to 1 transmission completed and 1 error signal output respectively Therefore when using SIM mode make sure to clear the IR bit to 0 interrupt not requested after setting these bits 20 8 5 Common Items for Multiple Modes 20 8 5 1 CLKi Output When using the output format of the CLKi pin as N channel open drain output follow the procedures below to change the pin function When changing to CLKi from a port 1 Select the mode of the serial interface by setting bits SMD2 to SMDO in the UiMR register to other than 000b 2 Set the NODC bit in the UiSMR3 register to 1 When changing to a port from CLKi 1 Set the NODC bit to 0 2 Disable the serial interface by setting bits SMD2 to SMDO to 000b R01UHO197EJ0120 Rev 1 20 ztENESAS Page 323 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 9 A D Converter 64 Pin Version Only Set registers ADCONO except bit 6 ADCON1 and ADCON when A D conversion is stopped before a trigger occurs After A D conversion is stopped set the ADSTBY bit from 1 to 0 When the ADSTBY bit in the ADCONI register is changed from 0 A D operation stopped to 1 A D operation enabled wait for 1 AD cycle or longer to start A D conversion To prevent noise induced device malfunction or latchup as well as to minimize conversion e
321. ndefined value Frequency select bit 1 Refer to NOTE 2 of the ADCON2 Register a an ao an me im ii ies ims jus i an ee 4 an n a jan js en js js s A D standby bit Set to 1 A D operation enabled mw he ie gt NOTES 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the ADSTBY bit is changed from 0 A D operation stopped to 1 A D operation enabled wait for 1 9AD cycle or more before starting A D conversion Figure 14 4 Registers ADCONO and ADCON t in One Shot Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 182 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 1 2 Repeat Mode In repeat mode analog voltage applied to a selected pin is repeatedly converted to a digital code Table 14 3 lists the Repeat Mode Specifications Figure 14 5 shows the Registers ADCONO and ADCON in Repeat Mode Table 14 3 Repeat Mode Specifications Item Specification Bits CH2 to CHO in the ADCONO register select a pin Analog voltage applied to this pin is repeatedly converted to a digital code Function A D conversion start condition The ADST bit in the ADCONO register is set to 1 A D conversion start A D conversion stop condition Set the ADST bit to 0 A D conversion stop Interrupt request generation timing No interrupt requests generated Analog input pin Se
322. ne shot start flag TA1OS A1 one shot start flag TA4OS 4 one shot start flag imer A2 one shot start flag imer A3 one shot start flag bi 1 1 1 1 l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 TAOTGL Timer AO event trigger select bit TAOTGH Function The timer starts counting by setting this bit to 1 while bits TMOD1 and TMODO in the TAiMR register i 0 to 4 10b one shot timer mode and the MR2 bit in the TAIMR register 0 TAIOS bit enabled Read as 0 b7 b6 0 0 Input on TAOIN pin is selected 0 1 TB2 is selected 1 0 TA4 is selected 2 1 1 TA1 is selected 2 1 Make sure the PD7_1 bit in the PD7 register is set to 0 input mode 2 Overflow or underflow Only underflow for TB2 Trigger Select Register b7 b6 b5 b4 b3 b2 bi bO Symbol TRGSR Address After Reset 00h Timer A1 event trigger select bit TA1TGL TA1TGH TA2TGL Timer A2 event trigger select bit TA2TGH TAS3TGL Timer A3 event trigger select bit TASTGH Input on TAIN is selected TB2 is selected TAO is selected TA2 is selected Input on TA2IN is selected C 9 TB2 is selected 2 is selected 2 TAS is selected 2 Input on TASIN is selected 9 TB2 is selected TA2 is selected TA4 is selected RW TA4TGL Timer A4 event trigger TA4T
323. neration Circuit FMSTP Flash memory stop bit b3 The FMSTP bit resets flash memory control circuits and minimizes current consumption in the flash memory Access to the internal flash memory is disabled when the FMSTP bit is set to 1 flash memory operation stopped Set the FMSTP bit by a program located in the RAM Set the FMSTP bit to 1 under the following condition e A flash memory access error occurs while erasing or programming EWO mode FMROO bit does not switch back to 1 ready Use the following steps to rewrite the FMSTP bit To stop the flash memory 1 Setthe FMSTP bit to 1 2 Wait the wait time to stabilize flash memory circuit tps To restart the flash memory 1 Set the FMSTP bit to 0 2 Wait the wait time to stabilize flash memory circuit tps The FMSTP bit is valid when the FMROI bit is 1 CPU rewrite mode If the FMROI bit is 0 although the FMSTP bit can be set to 1 by writing 1 the flash memory is neither placed in low power mode nor initialized When the FMR23 bit is set to 1 low current consumption read mode enabled do not set the FMSTP bit in the FMRO register to 1 flash memory operation stopped Also when the FMSTP bit is set to 1 do not set the FMR23 bit to 1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 54 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 4 2 Flash Memory Control Register 2 FMR2 Flash Memory Control Register 2 b7 b6 b5 b4 b3 b2
324. ng the TAiS register to 0 count stops during PWM pulse output the following action occurs When the POFSi bit in the TAPOFS register is 0 e Stop counting When the TAiOUT pin is output output level is set to and the IR bit is set to 1 When the TAiOUT pin is output both output level and the IR bit remains unchanged When the POFSi bit in the TAPOFS register is 1 e Stop counting e When the TAiOUT pin is output L output level is set to H and the IR bit is set to 1 When the TAiOUT pin is output both output level and the IR bit remains unchanged If a low level signal is applied to the SD pin when the IVPCRI bit in the TB2SC register 1 three phase output forcible cutoff by input on the SD pin enabled pins TAIOUT TA2OUT and TA4OUT go to high impedance state RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 318 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 7 2 Timer B 20 7 2 4 Timer B Timer Mode The timer is stopped after reset Set the mode count source counter value and others using registers TBiMR TBi and TBCSO to TBCS3 before setting the TBiS bit in the TABSR or the TBSR register to 1 count starts 1 0 to 5 Always make sure the TBiMR register and registers TBCSO to TBCS3 are modified while the TBiS bit is 0 count stops regardless of whether after reset or not A value of a counter while counting can be read in the TBi register at any time FFF
325. nged to RF OFF status the RF initial setting is also cleared Perform the RF initial setting again while in IDLE status RF Initial Set Register b15 b8 b7 b0 b7 Symbol Address After Reset BBRFINI 017Dh 017Ch Indeterminate RFINI RF initial set Sets data Figure 15 44 RF Initial Set Register Configuration 1 1 1 1 1 1 1 1 1 4 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 235 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 3 Control Sequence 15 3 1 Transmission Procedure Example 1 Set 1 baseband functions enabled in the BBEN bit in the BBCON register 2 Set Olh 1 ms in the BBIDLEWAIT register Set 1 IDLE interrupt in the BANKOINTSEL bit in the BBTXRXMODEF4 register Set 1 RF power ON in the RFPWRON bit in the BBRFCON register and 1 XIN power ON in the XINPWRON bit Use registers BBPLLDIVL and BBPLLDIVH for to channel setting Use the BBTXOUTPWR register for output power setting Set the AUTORCVO bit in the BBTXRXMODEO register Write to transmit RAM addresses D100h to D17Eh Set the transmit frame length in the BBTXFLEN register After the IDLE interrupt is generated after the wait time set in the BBIDLEWAIT register has elapsed from step 2 Set 1 clock regulator in the XINREGSEL bit in the BBRFCON register Set the setting value in the BBRFINI register Set 1 transmission start in the TRNTRG bit in the BBTXRXCON register m ommno RU cuc o
326. nnel open drain ports the pin status becomes high impedance 2 The PD10 register in the 48 pin version is a reserved area No access is allowed 3 Only PD5 5 and PD5 7 are available in the PD5 register The bits other than these are reserved Set to 0 4 P7 4to P7 7 in the P7 register in the 48 pin version are reserved bits Set to 0 5 P8 4 in the PD8 register not is available It is a reserved bit Set to 0 6 P8 and P8 1 in the 48 pin version are reserved bits Set to 0 Figure 17 6 Registers P5 to P8 P10 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 247 of 331 Jul 21 2011 M16C 6B Group 17 Programmable I O Ports Pull Up Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset i fe o o PUR1 0361h 00000000b Bit Symbol Bit Name Function Reserved bits Set to 0 P5_5 to P5_7 pull up P6_0 to P6_3 pull up NS Not pulled hig PU15 P6 4 to P6 7 pull u PUIS 1 Pulled high 2 PU16 P7_2 to P7 3 pull up PU17 P7 4to P7 7 pull up 9 1 Pins P7 0 and P7 1 do not have pull ups 2 To enable the pull up registers the corresponding bit in the register should be set to 1 pulled high and the respective bits in the direction register should be set to 0 input mode 3 Reserved bit in the 48 pin version Set to 0 Pull Up Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset XM 1000 Pure 0362h ooh Bit Symbol Bit Name Function P8_0 to P8 pull up
327. not be completed normally because of instantaneous power failure or other reasons erase the block again R01UH0197EJ0120 Rev 1 20 ztENESAS Page 272 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 5 Data Protect Function Each block in the flash memory has a nonvolatile lock bit The lock bit is enabled by setting the FMRO2 bit to 0 lock bit enabled The lock bit allows each block to be individually protected locked against program and erase This prevents data from being inadvertently written to or erased from the flash memory A block changes its status according to the lock bit status When the lock bit status is set to 0 the block is locked block is protected against program and erase When the lock bit status is set to 1 the block is not locked block can be programmed or erased The lock bit status is set to 0 locked by executing the lock bit program command and to 1 unlocked by erasing the block No commands can set the lock bit status to 1 The lock bit status can be read by the read lock bit status command When the FMRO2 bit is set to 1 the lock bit function is disabled and all blocks are unlocked However individual lock bit status remains unchanged The lock bit function is enabled by setting the FMRO2 bit to 0 Lock bit status is retained If the block erase command is executed while the FMRO2 bit is set to 1 the target block or all blocks are erased regardless of lock bit status The lock bit s
328. not enter stop mode Operation when the timer underflows Watchdog timer reset refer to 5 3 Watchdog Timer Reset Registers bits When the CSPRO bit in the CSPR register is set to 1 count source protection mode enabled 2 the followings are set automatically Set OFFFh to the watchdog timer Set the CM14 bit in the CM1 register to 0 125 kHz on chip oscillator on Set the PM12 bit in the PM1 register to 1 The watchdog timer reset is generated when watchdog timer underflows The following conditions apply in count source protection mode Writing to the CM10 bit in the CM1 register is disabled It remains unchanged even if itis set to 1 The MCU does not enter stop mode Writing to the CM14 bit in the CM1 register is disabled It remains unchanged even if itis set to 1 The 125 kHz on chip oscillator does not stop NOTES 1 The WDTON bit cannot be changed by a program Write 0 to bit of address FFFFFh with a flash programmer to set the WDTON bit 2 EvenifO is written to the CSPROINI bit in the OFS1 address the CSPRO is set to 1 The CSPROINI bit cannot be changed by a program Write 0 to bit 7 of address FFFFFh with a flash programmer to set the CSPROINI bit R01UH0197EJ0120 Rev 1 20 ztENESAS Page 86 of 331 Jul 21 2011 M16C 6B Group 11 DMAC 11 DMAC The DMAC Direct Memory Access Controller allows data to be transferred without the CPU intervention Four DMAC channels are i
329. nously with the next clock pulse applied However UARTI output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock The receive shift register is initialized and the serial interface starts receiving data synchronously with the next clock pulse applied The SWC bit is set to 1 SCL wait output enabled Consequently the SCLi pin is pulled low at the falling edge of the 9th clock pulse Note that when UARTI transmission reception is started using this function the TI bit does not change state Select the external clock as the transfer clock to start UARTi transmission reception with this setting RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 165 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 4 Special Mode 2 In special mode 2 serial communication between one or multiple masters and multiple slaves is available Transfer clock polarity and phase are selectable Table 13 15 lists the Special Mode 2 Specifications Table 13 16 lists the Registers Used and Settings in Special Mode 2 Figure 13 31 shows Special Mode 2 Communication Control Example UART2 Table 13 15 Special Mode 2 Specifications Item Specification Transfer data format Transfer data length 8 bits Transfer clock Master mode The CKDIR bit in the UIMR register 0 internal clock fj 2 n 1 fj 1510 f2SIO f8SIO f32SIO n setting
330. ns are operating Power control is exercised by controlling the CPU clock frequency The higher the CPU clock frequency the greater the processing capability The lower the CPU clock frequency the smaller the power consumption in the chip If the unnecessary oscillator circuits are turned off the power consumption is further reduced Before the clock sources for the CPU clock can be switched over the new clock source to which switched must be oscillating stably If the new clock source is the main clock or subclock allow a sufficient wait time in a program until it becomes oscillating stably When the CPU clock source is changed from the 125 kHz on chip oscillator to the main clock change the operating mode to the medium speed mode divided by 8 mode after the clock was divided by 8 the CMO6 bit in the CMO register was set to 1 in the 125 kHz on chip oscillator mode 7 4 1 1 High speed Mode The main clock divided by 1 provides the CPU clock If the subclock is on fC32 can be used as the count source for timers A and B 7 4 1 2 Medium Speed Mode The main clock divided by 2 4 8 or 16 provides the CPU clock If the subclock is on fC32 can be used as the count source for timers A and B If fOCO S is oscillating fOCO S can be used as the count source for timers A and B 7 4 1 3 Low Speed Mode The subclock provides the CPU clock The main clock is used as the clock source for the peripheral function clock when the CM21 bit in the CM2 r
331. nterrupt priority If an instruction is executed control branches invariably to the interrupt routine Watchdog timer Oscillation stop and re oscillation detection Peripheral function Single step Address match Figure 9 9 Hardware Interrupt Priority 9 5 10 Interrupt Priority Level Select Circuit The interrupt priority level select circuit selects the highest priority interrupt in a sampled interrupt request s at the same sampling point Figure 9 10 shows the Interrupts Priority Select Circuit R01UH0197EJ0120 Rev 1 20 ztENESAS Page 74 of 331 Jul 21 2011 M16C 6B Group Level 0 initial value Reception overrun 0 PLL lock detection Address filter Bank 0 reception complete IDLE DMA3 Reception overrun 1 x lt Transmission overrun DMA2 ee if priority levels are E Timer A3 lt EKEKEKEKEKEXK Timer 1 Ho Timer B4 UART1 bus collision Timer compare 2 ol Timer B1 Timer A4 Timer A2 Timer B3 UARTO bus collision Timer B5 UART1 receive ACK1 9 Interrupt Priority level of each interrupt UARTO receive ACKO UART2 receive ACK2 A D conversion 64 pin version only DMA1 UART2 bus collision Timer compare 0 Timer AO Interrupt request level o __ _ selection output to clock generating circuit F
332. nversion result will be indeterminate 2 When the ADSTBY bit is reset from 0 A D operation stopped to 1 A D operation enabled wait for 1 9AD cycle or more before starting A D conversion Ww RW RW RW Ww Figure 14 5 Registers ADCONO and ADCON t in Repeat Mode R01UH0197EJ0120 Rev 1 20 ztENESAS Page 184 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 1 3 Single Sweep Mode In single sweep mode analog voltage that is applied to selected pins is converted one by one to a digital code Table 14 4 lists the Single Sweep Mode Specifications Figure 14 6 shows Registers ADCONO and ADCONI in Single Sweep Mode Table 14 4 Single Sweep Mode Specifications Item Specification Function Bits SCAN1 and SCANO in the ADCON1 register select pins Analog voltage applied to the pins is converted one by one to a digital code A D conversion start The ADST bit in the ADCONO register is set to 1 A D conversion start condition A D conversion stop Completion of A D conversion The ADST bit is cleared to 0 A D conversion condition stop Set the ADST bit to 0 Interrupt request Completion of A D conversion generation timing Analog input pin Select from ANO and AN1 2 pins ANO to AN3 4 pins ANO to AN5 6 pins and ANO to AN7 8 pin Reading of result of A D Read one of the registers ADO to AD7 that corresponds to the selected pin converter RO1UH0197EJ0120 Rev
333. o 11 The timer counts an internal count source The timer counts pulses from an external device only TAO and TA1 in the 48 pin version or overflows and underflows of other timers The timer outputs a pulse only once before it reaches the minimum count 0000h only TAO and in the 48 pin version The timer outputs pulses in a given width successively only TAO and TAI in the 48 pin version REIS ao o Bus 5 TMOD1 to MR2 Fi TMOD1 to TMODO 00 MR2 0 TMOD1 to 10 Timer gate function TMOD1 to 00 2 1 Event counter TMOD1 to 01 9 Reload Register Counter Increment decrement Always decrement except in event counter mode Decrement TMOD1 to TMODO To external trigger circuit 1 RE TAiOUT 9 O NOTES 1 Overflow or underflow Only underflow for TB2 2 Only TAO and TA1 in the 48 pin version 3 For TA2 to TA4 in the 48 pin version external pin input cannot be used as a count source 4 For TA2 to TA4 in the 48 pin version external pin input or output cannot be used as a count source TCK1 to TCKO TMOD1 to MR2 to MR1 bits in the TAiMR register i 1 to 4 to TAiTGL bits in the ONSF register when i 0 bits the TRGSR register when i 1 to 4 TAiS TAiUD TCSO to TCS7 POFSi bits in the TABSR register bits in the UDF register Figure 12 4 Timer A
334. o NOTE 1 Steps 2 to 7 can be interchanged A transmission complete interrupt is generated when one of the following events occurs after transmission starts Transmission is completed ACK reception is completed after the ACK reception function is enabled and transmission with an ACK request is performed The ACK is not received for a certain period after the ACK reception function is enabled and transmission with an ACK request is performed The CCA result is that the channel is busy when transmission is requested with automatic CSMA CA enabled 15 3 2 Reception Procedure Example 1 Set 1 baseband functions enabled in the BBEN bit in the BBCON register 2 Set Olh 1 ms in the BBIDLEWAIT register Set 1 IDLE interrupt in the BANKOINTSEL bit in the BBTXRXMODEF4 register Set 1 RF power ON in the RFPWRON bit in the BBRFCON register and 1 XIN power ON in the XINPWRON bit Use registers BBPLLDIVL and BBPLLDIVH for to channel setting Set bits AUTOACKEN AUTORCV O and BEACON in the BBTXRXMODEO register Set the PAN identifier in the BBPANID register Set the BSHORTAD register or registers BBEXTENDADO to BBEXTENDAD3 After the IDLE interrupt is generated after the wait time set in the BBIDLEWAIT register has elapsed from step 2 Set 1 clock regulator in XINREGSEL bit in the BBRFCON register Set the setting value in the BBRFINI register Set 1 reception start in the RCVTRG bit in the BBTXRXCON regi
335. o 0 program program program ist 2nd 3rd 5th 6th 7th 8th bit bit bit bit bit bit bit STSPSEL bit Set STAREQ 1 start Set STPREQ 1 Stop condition detection Start condition detection start interrupt i 0to2 interrupt Figure 13 30 STSPSEL Bit Functions 13 1 3 3 Arbitration Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of SCLi Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is updated If the ABC bit 0 update per bit the ABT bit is set to 1 at the same time unmatching is detected during check and is cleared to 0 when not detected In cases when the ABC bit is set to 1 if unmatching is ever detected the ABT bit is set to 1 unmatching detected at the falling edge of the clock pulse of 9th bit If the ABT bit needs to be updated per byte clear the ABT bit to 0 undetected after detecting acknowledge in the first byte before transferring the next byte Setting the ALS bit in the UISMR2 register to 1 SDA output stop enabled factors arbitration lost to occur in which case the SDAi pin is placed in the high impedance state at the same time the ABT bit is set to 1 unmatching detected R01UHO197EJ0120 Rev 1 20 ztENESAS Page 163 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 3 4 Transfer Clock The transfer clock is used to transmit and recei
336. o 1 125 kHz on chip oscillator off when the CM21 bit is set to 0 main clock When the 21 bit is set to 1 125 kHz on chip oscillator clock the CM14 bit is set to 0 125 kHz on chip oscillator on and remains unchanged even if writing 1 to this bit When the CSPRO bit in the CSPR register is set to 1 count source protection mode the CM14 bit is automatically set to 0 125 kHz on chip oscillator on and remains unchanged even if writing a 1 to this bit 125 kHz on chip oscillator does not stop CM10 All clock stop control bit 5 CM16 Figure 7 3 CM1 Register R01UH0197EJ0120 Rev 1 20 ztENESAS Page 39 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset CM2 000Ch 0X00001 0b 19 EIS Oscillation stop and re oscillation Oscillation stop and detection function disabled CM20 re oscillation detection enable bane m bit 7 8 9 10 Oscillation stop and re oscillation detection function enabled CM 1 System clock select Main clock bit 2 2 3 6 10 11 125 kHz on chip oscillator clock Oscillation stop and Main clock stops and re oscillation not En detected CM22 jre oscillation detection Mai 4 Main clock stops and re oscillation flag detected Main clock oscillates 6 CM23 XIN monitor flag 1 Main clock stops b5 b4 Reserved bits Set to 0 b6 No register bi
337. ock and reception status is enabled 138 us later Setting the TRNTRG bit to 1 starts the warming up of the RF block and transmission starts 144 us later Setting the CCATRG bit to 1 starts the warming up of the RF block and CCA operation starts 138 ps later Make sure to set these bits in IDLE status Do not set two or more bits to 1 simultaneously These bits are automatically cleared to 0 when transmission reception or CCA is completed To cancel transmission reception or CCA in progress use the RFSTOP bit in the BBTXRXCON register Transmit Receive Control Register b7 b6 b5 b4 b2 bi bO Symbol Address After Reset BBTXRXCON 010Ch 00h 0 No action RCVTRG Receive trigger bit 1 Reception start 0 No action 1 Transmission start 0 No action 1 CCA start Figure 15 22 Transmit Receive Control Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 218 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 14 CSMA Control Register 0 Setting the CSMAST bit to 1 starts CSMA CA operation Make sure to set this bit in IDLE status Also this bit is automatically cleared to 0 when CSMA CA operation is completed Setting O in this bit does not allow any write operation Setting the CSMATRNST bit to 1 allows transmit processing to be automatically performed if the result is TRUE when CSMA CA operation is completed To cancel CSMA CA operation in progress use the RFSTOP bit in the BBT
338. ock output function select bit 0 0 port P5 7 valid only in single chip 0 1 Output fC mode 1 0 Output f8 1 1 Output f32 0 Peripheral function clock f1 does not WAIT mode peripheral stop in wait mode function clock stop bit 19 1 Peripheral function clock f1 stops in wait mode 8 XCIN XCOUT drive capacity 0 Low select bit 2 1 High 0 I O ports P8 6 P8 7 1 XCIN XCOUT oscillation function F 0 On 3 4 10 12 13 CMO5 Main clock stop bit 1 Off Main clock division select 0 CM16 and CM17 enabled bit 0 7 13 14 1 Division by 8 mode Port XC select bit 2 CM06 0 Main clock or 125 kHz on chip oscillator clock 1 Subclock System clock select bit 6 10 11 12 Rewrite this register after setting the PRCO bit in the PRCR register to 1 write enabled The CMO3 bit is set to 1 high while the CM04 bit is set to 0 I O port or when entering stop mode This bit is provided to stop the main clock when the low power consumption mode or 125 kHz on chip oscillator low power consumption mode is selected This bit cannot be used for detection as to whether the main clock stops or not To stop the main clock set bits as follows 1 Set the CMO7 bit to 1 subclock selected with the subclock stably oscillates or set the CM21 bit in the CM2 register to 1 125 kHz on chip oscillator selected 2 Set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection fun
339. ode Timer B 16 bit timer x 6 Timer mode Serial interface UARTO to UART2 Clock synchronous asynchronous x 3 channels A D converter 64 pin version 10 bit resolution x 8 channels including sample and hold function conversion time 2 69 us CRC calculation circuit CRC CCITT X16 X12 X5 1 compliant Baseband 127 byte transmit RAM 127 byte receive RAM x 2 Automatic ACK response function 26 bit timer Compare function in 3 channels Flash memory Programming and erasure power supply voltage 2 7 V to 3 6 V Programming and erasure endurance 100 times all area or 1 000 times program ROM1 program ROM2 10 000 times data flash Program security ROM code protect ID code check Debug functions On chip debug on board flash rewrite function address match x 4 Encryption AES AES Encryption Decryption Key length 128bit R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 2 of 331 M16C 6B Group 1 Overview Table 1 2 Specifications 2 Function Specification Operation frequency supply voltage 16 MHz no division 2 7 V to 3 6 V 16 MHz divided by 2 4 8 16 2 2 V to 3 6 V Power consumption Tx MCU f BCLK 4 MHz 35 7 mA Rx MCU f BCLK 4 MHz 46 7 mA RF idle MCU f BCLK 4 MHz 6 7 mA RF off MCU f BCLK 4 MHz 4 7 mA Tx MCU f BCLK 8 MHz 37 5 mA Rx MCU f BCLK 8 MHz 48 5 mA RF idle MCU f BCLK
340. ode In wait mode the CPU clock is turned off so are the CPU and the watchdog timer because they are operated by the CPU clock However if the CSPRO bit in the CSPR register is 1 count source protection enabled the watchdog timer remains active Because the main clock subclock and 125 kHz on chip oscillator clock all are on the peripheral functions using these clocks keep operating 7 4 21 Peripheral Function Clock Stop Function If the CMO2 bit in the register is 1 peripheral function clock f1 turned off during wait mode f1 clock is turned off while in wait mode with the power consumption reduced that much However fC32 and fOCO S clock source of Timers and B remain on for the CMO2 bit 7 4 22 Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction 7 4 2 3 Pin Status during Wait Mode Table 7 3 lists Pin Status during Wait Mode Table 7 3 Pin Status during Wait Mode Single Chip Mode Retains status before wait mode When fC selected Does not stop When 8 f32 selected Does not stop when the CMO 2 bit is 0 When the CMO 2 bit is 1 the status immediately prior to entering wait mode is maintained R01UHO197EJ0120 Rev 1 20 24 NC SAS Page 48 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 4 2 4 Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset NMI interrupt or peripheral function interru
341. ode IDLE status is not selected even if frame reception is completed and reception status remains the same In case using continuous receive mode set O1h to the address of 0D2A6h Do not set bits CONTTX and CONTRX to 1 simultaneously Verification Mode Set Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset BBEVAREG 0168h 00h CONTTX Continuous transmit mode D Normal operation RW bit 1 Continuous transmit operation 0 Modulation signal 1 Non modulation signal 0 Normal operation 1 Continuous receive operation Figure 15 41 Verification Mode Set Register Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 233 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 33 IDLE Wait Set Register This register is used to set the wait time to transit to IDLE status after setting RFPWRON bit in the BBRFCON register to 1 RF power ON or XINPWRON bit in the BBRFCON register to 1 XIN power ON When the setting time has elapsed an IDLE interrupt request or clock regulator interrupt is generated The initial value is 19h 25 ms the setting value is 1h 1 ms IDLE Wait Set Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset BBIDLEWAIT 0176h 19h b7 b5 No register bits If necessary set to 0 Read as undefined value IDLEWAIT IDLE wait set Sets the wait time to transit to IDLE status Figure 15 42 IDLE Wait Set Register Configuration 15 2 34 ANTSW Outpu
342. ode the Divided by 4 RF idle current output pins are RF Tx open and other RF Rx pins are VSS f BCLK 8 MHz RF off Divided by 2 RF idle RF Tx RF Rx f BCLK 16 MHz RF off No division RF idle RF Tx RF Rx 125 kHz On chip oscillation No division RF off Flash memory f BCLK 8 MHz program VCC 3 3 V Flash memory 8 MHz erase VCC 3 3 V Flash memory f BCLK 32 kHz Low power consumption mode RF off 125 kHz On chip oscillation wait mode RF off f BCLK 32 kHz Wait mode 2 Oscillation capability High RF off f BCLK 32 kHz Wait mode 2 Oscillation capability Low RF off Stop mode Topr 25 C NOTES 1 Referenced to VCC 2 7 to 3 6 V VSS 0 V at Topr 20 to 85 C 40 to 85 C f BCLK 16 MHz unless otherwise specified 2 With one timer operated using fC32 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 293 of 331 Jul 21 2011 M16C 6B Group 19 Electrical Characteristics VCC 3 3 V Timing Requirements VCC 3 3 V VSS 0 V at 20 to 85 C 40 to 85 C unless otherwise specified Table 19 10 Timer A Input Counter Input in Event Counter Mode te TA Parameter input cycle time Standard Min Max tw TAH input H pulse width tw TAL Table 19 11 tc TA input L puls
343. ode Register 4 U2SMR4 00h UART2 Special Mode Register 3 U2SMR3 000X0X0Xb UART2 Special Mode Register 2 U2SMR2 X0000000b UART2 Special Mode Register U2SMR X0000000b UART2 Transmit Receive Mode Register U2MR 00h UART2 Bit Rate Register U2BRG XXh UART2 Transmit Buffer Register U2TB XXh XXh UART2 Transmit Receive Control Register 0 U2C0 00001000b UART2 Transmit Receive Control Register 1 U2C1 00000010b UART2 Receive Buffer Register U2RB XXh 026Fh XXh 0270h to 02FFh NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 24 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 10 SFR Information 10 1 Address Register Timer B3 B4 B5 Count Start Flag After Reset 000XXXXXb Timer B3 Register Timer B4 Register Timer B5 Register Timer B3 Mode Register 00XX0000b Timer B4 Mode Register 00XX0000b Timer B5 Mode Register 00XX0000b Count Start Flag 00h One Shot Start Flag 00h Trigger Select Register 00h Up Down Flag 00h Timer AO Register XXh XXh Timer A1 Register XXh XXh Timer A2 Register XXh XXh Timer A3 Register XXh XXh Timer A4 Register XXh XXh Timer BO Register XXh XXh Timer B1 Register XXh XXh Timer B2 Register XXh XXh
344. of a timer count source and then set the ADST bit in the ADCONO register to 1 A D conversion start Do not set bits ADST and ADSTBY to 1 at the same time Also do not set the ADSTBY bit to 0 A D operation stopped standby during A D conversion RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 191 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 4 Output Impedance of Sensor under A D Conversion Microcomputer Sensor equivalent circuit RO Sampling time C 10 0 pF ge A Figure 14 9 Analog Input Pin and External Sensor Equivalent Circuit RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 192 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 Baseband Functionality 15 1 Baseband Functional Description The following baseband functions are implemented in hardware 1 26 bit timer 2 Transmit RAM 3 Receive RAM 4 Transmit frame generator 5 Filter function 6 Interrupts 7 CRC circuit 8 Automatic ACK response function 9 Automatic ACK reception function 10 Automatic reception switching function 11 ANTSW output switching function 12 Automatic CSMA CA function 13 State transitions 14 Baseband associated registers 15 Control sequence 16 Examples of automatic transmit and receive operations RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 193 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 1 1 Baseband Block Diagram
345. or to Main Clock Simultaneously with oscillation stop and re oscillation detection interrupt occurrence the CM22 bit becomes 1 When the CM22 bit is set to 1 oscillation stop and re oscillation detection interrupt are disabled By setting the CM22 bit to 0 in a program oscillation stop and re oscillation detection interrupt are enabled If the main clock stops during low speed mode where the CM20 bit is 1 an oscillation stop and re oscillation detection interrupt request is generated At the same time the 125 kHz on chip oscillator starts oscillating In this case although the CPU clock is derived from the subclock as it was before the interrupt occurred the peripheral function clocks now are derived from the 125 kHz on chip oscillator clock To enter wait mode while using the oscillation stop and re oscillation detection function set the CMO2 bit to 0 peripheral function clocks not turned off during wait mode Since the oscillation stop and re oscillation detection function is provided in preparation for main clock stop due to external factors set the CM20 bit to 0 oscillation stop and re oscillation detection function disabled where the main clock is stopped or oscillated in a program that is where the stop mode is selected or the CM05 bit is altered This function cannot be used if the main clock frequency is 2 MHz or less In that case set the CM20 bit to 0 Switch the main clock Determine several times whether the CM2
346. ordinator PANCORD PAN coordinator bit 4 PAN coordinator b3 b2 0 O Level filter disabled 0 1 Do not set 1 0 Do not set 1 1 Level filter enabled RCVBANKSEL Receive bank select bit 0 Bank 0 1 Bank 1 Receive RAM overwrite 0 Overwrite disabled REVOVERWREN enable bit 1 Overwrite enabled ry b7 b b6 Reserved bits Set to 0 Figure 15 20 Transmit Receive Mode Register 3 Configuration LVLFILENO Receive level filter enable bit LVLFILEN1 0 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 217 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 12 Receive Level Threshold Set Register This register is used to set the threshold value for the reception level filter function Set the value to two s complement in dBm units example 9Eh is indicated as 98 dBm The value set in the receive level threshold set register is compared with the value to be stored in the RSSI CCA result register the value added with the offset value set in the RSSI offset register Receive Level Threshold Set Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset BBLVLVTH 010Bh 00h Bit Symbol Bit Name Function Sets the threshold value for the reception LVLVTH Receive level threshold level filter function Figure 15 21 Reception Level Threshold Set Register Configuration 15 2 13 Transmit Receive Control Register Setting the RCVTRG bit to 1 starts the warming up of the RF bl
347. ory Rewrite Modes Overview Standard Serial I O Mode Program ROM 1 program ROM 2 and data flash are rewritten using a dedicated serial programmer Standard serial I O mode 1 clock synchronous serial I O Standard serial I O mode 2 clock asynchronous serial I O Parallel I O Mode Program ROM 1 program ROM 2 and data flash are rewritten using a dedicated parallel programmer Areas which can be rewritten Program ROM 1 program ROM 2 and data flash Program ROM 1 program ROM 2 and data flash Program ROM 1 program ROM 2 and data flash Operating mode Single chip mode Boot mode Parallel mode ROM programmer None Serial programmer Parallel programmer R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 251 of 331 M16C 6B Group 18 Flash Memory 18 1 Memory Map The flash memory contains program ROM 1 program ROM 2 and data flash Figure 18 1 shows a Flash Memory Block Diagram Program ROM 1 is divided into several blocks each of which can be protected locked from program or erase Program ROM 1 and program ROM 2 can be rewritten in CPU rewrite standard serial I O and parallel I O modes Program ROM 2 can be used when the PRG2CO bit in the PRG2C register is set to 0 program ROM 2 enabled The user boot code area is in program ROM 2 Data flash can be used when the PM10 bit in the PM1 register is set to 1 OE000h to OFFFFh data flash Data flash is div
348. oup 13 Serial Interface 13 1 2 Clock Asynchronous Serial I O UART Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format Table 13 5 lists the UART Mode Specifications Table 13 5 UART Mode Specifications Transfer data format Character bit transfer data selectable from 7 8 or 9 bits Start bit 1 bit Parity bit selectable from odd even or none Stop bit selectable from 1 bit or 2 bits Transfer clock The CKDIR bit in the UIMR register 0 internal clock fj 16 n 1 fj 1510 12510 f8SIO f32SIO setting value of UIBRG register 00h to FFh CKDIR bit 1 external clock fEXT 16 n 1 fEXT input from CLKi setting value of UiBRG register 00h to FFh Transmission Selectable from CTS function RTS function or CTS RTS function disabled reception control Transmission start Before transmission starts satisfy the following requirements condition The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register 0 data present in the UiTB register If CTS function is selected input on the CTSi pin L Reception start condition Before reception starts satisfy the following requirements The RE bit in the UiC1 register 1 reception enabled Start bit detection Interrupt request For transmission one of the following conditions can be selected generation timing The
349. oup 9 Interrupt Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 bi bo Symbol Address After Reset AIER 020Eh XXXXXX00b ia m asia Address match C 0 0 Interrupt disabled RW enable bit 1 Interrupt enabled Address match interrupt 1 0 Interrupt disabled RW enable bit 1 Interrupt enabled No register bits If necessary set to 0 Read as undefined value Address Match Interrupt Enable Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset AIER2 020Fh XXXXXX00b 2 mM ee Address match interrupt 2 0 Interrupt disabled enable bit 1 Interrupt enabled Address match interrupt 3 0 Interrupt disabled AED enable bit 1 Interrupt enabled AIER20 No register bits If necessary set to 0 Read as undefined value b7 b2 Address Match Interrupt Register i i 2 O to 3 023 b19 b16 b15 b8 b7 b3 b0 b7 b0 b7 b0 Symbol Address After Reset RMADO 0212h to 0210h X00000h RMAD1 0216h to 0214h X00000h RMAD2 021Ah to 0218h X00000h RMAD3 021Eh to 021Ch X00000h Faction Setting Range ES Address register for address match interrupt 00000h to FFFEFh EI b19 to b0 No register bits If necessary set to 0 Read as undefined value Figure 9 16 Registers AIER AIER2 and RMADO to RMAD3 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 81 of 331 Jul 21 2011 M16C 6B Group 10 Watchdog Timer 10 Watchdog Timer The watchdog timer detects whether the program is out of control
350. ource Select Register DMA1 Source Select Register NOTES X Undefined 1 The blank areas are reserved and cannot be accessed by users 2 When the CSPROINT bit in the OFS1 address is set to 0 value after reset is 10000000b R01UH0197EJ0120 Rev 1 20 24 NC S AS Page 27 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 13 SFR Information 13 1 Address Register After Reset CRC Data Register XXh XXh CRC Input Register XXh A D Register 0 2 XXXXXXXXb 000000XXb A D Register 1 2 XXXXXXXXb 000000XXb A D Register 2 2 XXXXXXXXb 000000XXb A D Register 3 2 XXXXXXXXb 000000XXb A D Register 4 2 XXXXXXXXb 000000XXb A D Register 5 2 XXXXXXXXb 000000XXb A D Register 6 2 XXXXXXXXb 000000XXb A D Register 7 2 XXXXXXXXb 000000XXb A D Control Register 2 2 ADCON2 0000X00Xb A D Control Register 0 2 ADCONO 00000XXXb A D Control Register 1 2 ADCON1 0000X000b NOTES X Undefined 1 The blank areas are reserved and cannot be accessed by users 2 64 pin version only R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 28 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 14 Address SFR Information 14 1 Register After Reset 03DAh 03DBh
351. output Each bit in the PDi register corresponds to one port 17 2 Port Pi Register Pi Register i 5 to 8 10 Figure 17 6 shows the Pi Registers Data input output to and from external devices are accomplished by reading and writing to the Pi register Each bit of the Pi register consists of a port latch to hold the output data and a circuit to read the pin status For ports set for input mode the input level of the pin can be read by reading the corresponding Pi register and data can be written to the port latch by writing to the Pi register For ports set for output mode the port latch can be read by reading the corresponding Pi register and data can be written to the port latch by writing to the Pi register The data written to the port latch is output from the pin Each bit in the Pi register correspond to each port 17 3 Pull up Control Register 1 to Pull up Control Register 2 Registers PUR1 to PUR2 Figure 17 7 shows the Registers and PUR2 Bits in registers PUR1 to PUR2 can be used to select whether or not to pull the corresponding port high in 4 pin units The port chosen to be pulled high has a pull up resistor connected to it when the direction bit is set for input mode 17 4 LED Port Switch Register LEDCON Register Figure 17 8 shows the LEDCON Register Bits in the LEDCON register can be used to switch the drive capacity of P5 5 and P5 7 R01UH0197EJ0120 Rev 1 20 ztENESAS Page 242 of 331 Jul 21 2011 M
352. peration the status register indicates whether or not the auto program operation has been completed as expected Write the command code xx41h to the write address Write data to the write address y Full status check Program operation is completed 1 Write the command codes and data to even addresses NOTE Figure 18 8 Flow Chart of the Program Command RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 268 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 4 5 Block Erase Command By writing xx20h in the first bus cycle and xxDOh in the second bus cycle to the highest order even address of a block an auto erase operation erase and verify will start in the specified block The bit in the FMRO register indicates whether an auto erase operation has been completed The FMROO bit is set to 0 busy during auto erase and to ready when the auto erase operation is completed After the completion of an auto erase operation the FMRO7 bit in the FMRO register indicates whether or not the auto erase operation has been completed as expected Refer to 18 3 7 Full Status Check Figure 18 9 shows a Flow Chart of the Block Erase Command Programming The lock bit protects each block from being erased inadvertently Refer to 18 3 5 Data Protect Function In EW1 mode do not execute this command on the block where the rewrite control program is allocated In EWO mode the microcomputer enters read status regist
353. pt If the microcomputer is to exit wait mode by a hardware reset NMI interrupt or set the peripheral function interrupt bits ILVL2 to ILVLO to 000b interrupts disabled before executing the WAIT instruction The peripheral function interrupts are affected by the CMO2 bit If the CMO2 bit is 0 peripheral function clocks not turned off during wait mode peripheral function interrupts can be used to exit wait mode If the CMO02 bit is 1 peripheral function clocks turned off during wait mode the peripheral functions using the peripheral function clocks stop operating so that only the peripheral functions activated by external signals can be used to exit wait mode Table 7 4 Resets and Interrupts to Exit Wait Mode and Use Conditions Reset Interrupt CM02 1 NMI interrupt Usable Usable Serial interface interrupt Usable when operating with Usable when operating with internal or external clock external clock Key input interrupt Usable Usable A D conversion interrupt Usable in one shot mode or single Do not use 64 pin version only sweep mode Timer A interrupt Usable in all modes Usable in event counter mode or Timer B interrupt when the count source is fC32 or fOCO S INT interrupt Usable Usable Timer compare 0 1 2 interrupt Usable Do not use Transmission complete interrupt Usable Do not use Bank 0 1 reception complete Usable Do not use interrupt Address filter interrupt Usable Do not use CCA interrupt Usable Do not use
354. quested To use an interrupt change the interrupt generate factor and then be sure to clear the IR bit for that interrupt to O interrupt not requested Changing the interrupt generate factor referred to here means any act of changing the source polarity or timing of the interrupt assigned to each software interrupt number Therefore if a mode change of any peripheral function involves changing the source polarity or timing of an interrupt be sure to clear the IR bit for that interrupt to 0 interrupt not requested after making such changes Refer to the description of each peripheral function for details about the interrupts from peripheral functions Figure 20 2 shows the Procedure for Changing the Interrupt Generate Factor Change the interrupt source Disable interrupts 3 Change the interrupt generate factor including a mode change of peripheral function Use the MOV instruction to clear the IR bit to 0 interrupt not requested Enable interrupts 9 Change is completed IR bit A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES 1 The above settings must be executed individually Do not execute two or more settings simultaneously using one instruction 2 Use the flag for the INTi interrupt i 0 1 For the interrupts from peripheral functions other than the INTi interrupt turn off the peripheral function that is the sou
355. r A1 0000h Frame base register FB b19 bo 00000h Interrupt table register INTB Content of addresses FFFFEh to FFFFCh Program counter PC b15 bo 0000h User stack pointer USP 0000h Interrupt stack pointer ISP 0000h Static base register SB Flag register FLG Figure 5 3 CPU Register Status After Reset RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 32 of 331 Jul 21 2011 M16C 6B Group 6 Processor Mode 6 Processor Mode 6 1 Types of Processor Mode Three processor modes are available to choose from single chip mode Table 6 1 lists the Features of Processor Modes Table 6 1 Features of Processor Modes Pins Which Are Assigned VO Poris Single chip mode SFR internal RAM internal ROM ca Or Dan phiere Winaar 6 2 Setting Processor Modes Processor mode is set by using the CNVSS pin Table 6 2 lists the Processor Mode After Hardware Reset Table 6 2 Processor Mode After Hardware Reset CNVSS Pin Input Level VSS Single chip mode Figures 6 1 to 6 3 show the processor mode associated registers Figure 6 4 show the Memory Map in Single Chip Mode Processor Mode Register 0 Z b6 b5 b4 b3 b2 bi bO Symbol Address After Reset PMO 0004h 00000000b Function b1 bO 0 0 Single chip mode Other than above Do not set Setting this bit to 1 resets the Software microcomputer Read as 0 Dp n
356. r less by the CMO6 bit in register and bits CM17 and CM16 in register Also set the PM17 bit in the PMI register to 1 wait state FMR60 EW1 mode select bit bO To set the FMR60 bit to 1 write 1 when both FMROI bit in the FMRO register and FMR11 bit in the FMRI register are 1 Change the FMR60 bit when the PM24 bit in the PM register is 0 NMI interrupt disabled or high is input to the NMI pin Also change this bit when the FMROO bit in the FMRO register is 1 ready FMR61 b1 Set the FMR61 bit to 1 when using CPU rewrite mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 264 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory Figure 18 5 shows Setting and Resetting of EWO Mode Figure 18 6 shows Setting and Resetting of EW1 Mode Procedure to Enter EWO Mode Set the FMRO01 bit to 0 and then 1 CPU rewrite Single chip mode mode enabled 2 Set the FMR11 bit to 1 FMR6 register write enabled and then set the FMR6 register to 02h EWO mode and then set the FMR11 bit to 0 FMR6 register write disabled Set registers CM1 PM1 Execute the software commands J Jump to the rewrite control program transferred to Execute the read array command 9 the RAM In the following steps use the rewrite control program in the RAM Set the FMRO 1 bit to 0 CPU rewrite mode disabled NOTES Jump to a desired address in the flash memory 1 In CPU rewrit
357. r output 1 5 V pin for the XIN circuit Connect only a bypass capacitor between pins VREGOUTS and VSS Do not use as the power supply for other circuits RF I O RFIOP RFION RF I O pins Test ports TESTIOP TESTION Ports for testing Leave open or apply 0 V External antenna switch control output ANTSWCONT Signal output pin to control the external antenna switch If antenna switch control is not required leave open R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 11 of 331 M16C 6B Group 2 Central Processing Unit CPU 2 Central Processing Unit CPU Figure 2 1 shows the CPU registers Seven registers RO R1 R2 R3 AO Al and FB out of thirteen registers configure a register bank There are two sets of register banks b8b7 b0 FOH high order bits of FO FOL bits of PO RIH tigh order bits of Ri RIL loworder bits of Ri R2 R3 AO A1 Data registers 2 Address registers 1 2 Frame base registers 1 b19 b15 INTBH INTBL Interrupt table register INTBH is 4 high order bits of INTB register and INTBL is 16 low order bits of INTB register b19 Program counter User stack pointer Interrupt stack pointer Static base register Flag register Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow fl
358. r transmission one of the following conditions can be selected The UiIRS bit 3 0 transmit buffer empty when transferring data from the UiTB register to the UARTi transmit register at start of transmission The UiIRS bit 1 transfer completed when the serial interface finished sending data from the UARTi transmit register For reception When transferring data from the UARTi receive register to the UiRB register at completion of reception Error detection Overrun error 2 This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select function i Oto2 NOTES CLK polarity selection Transfer data input output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock LSB first MSB first selection Whether to start sending receiving data beginning with bit O or beginning with bit 7 can be selected Continuous receive mode selection Reception is enabled immediately by reading the UiRB register Switching serial data logic This function reverses the logic value of the transmit receive data Transfer clock output from multiple pins selection UART1 The output pin can be selected a program from two UART1 transfer clock pins that have been set Separate CTS RTS pins UARTO CTSO and RTSO are input output from separate pins 1 When an external clock is selec
359. ransmit or receive operation the operation stops before the next data For the RTS function the CTSi RTSi pin outputs L when the microcomputer is ready to receive The output level becomes H on the first falling edge of the CLKi pin The CRD bit in the UiCO register 1 disable CTS RTS function CTSi RTSi pin is programmable I O function The CRD bit 0 CRS bit 0 CTS function selected CTSi RTSi pin is CTS function The CRD bit 0 CRS bit 1 RTS function selected CTSi RTSi pin is RTS function 13 1 1 8 CTS RTS Separate Function UARTO This function separates CTSO RTSO outputs RTSO from the P6 0 pin and inputs CTSO from the P6 4 pin To use this function set the register bits as shown below The CRD bit in the UOCO register 0 enable CTS RTS of UARTO The CRS bit in the register 1 output RTS of UARTO The CRD bit in the U1CO register 0 enable CTS RTS of UART1 The CRS bit in the U1CO register 0 input CTS of UARTI The RCSP bit in the UCON register 1 inputs CTSO from the P6 4 pin The CLKMDI bit in register 0 CLKSI not used Note that when using the CTS RTS separate function CTS RTS of UARTI function cannot be used Microcomputer TXDO P6 3 RXDO P6 2 CLKO P6 1 RTSO 0 CTS0 P6 4 Figure 13 20 CTS RTS Separate Function R01UH0197EJ0120 Rev 1 20 ztENESAS Page 147 of 331 Jul 21 2011 M16C 6B Gr
360. rasitic diode Make sure the input voltage on each port will never exceed VCC 2 symbolizes a parasitic diode 3 64 pin version only Figure 17 2 I O Ports 2 R01UH0197EJ0120 Rev 1 20 24 NC SAS Page 244 of 331 Jul 21 2011 M16C 6B Group NMI enabled Direction register lt Data bus 9 Port latch Pull up selection lt NMI interrupt input P Direction p register 17 Programmable I O Ports NMI enabled Data bus Port latch p Pull up selection ie Direction e register symbolizes a parasitic diode Make sure the input voltage on each port will never exceed VCC Figure 17 3 Ports 3 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 245 of 331 M16C 6B Group 17 Programmable I O Ports CNVSS signal input M 4 O NOTE 1 RESET signal input G4 4O NOTE 1 M symbolizes a parasitic diode Make sure the input voltage on each port will never exceed VCC Figure 17 4 I O Pins Port Pi Direction Register i 5 to 8 10 b7 b6 b5 b4 b3 b2 b1 bd Symbol Address After Reset PD5 2 PD6 PD7 9 O3EAh OSEBh OSEEh O3EFh 00h PD8 5 03F2h 00h PD10 O3F6h 00h PDi 0 Port Pi O0 direction bit 0 Input mode Port Pi 1
361. rce of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor In this case if the maskable interrupts can all be disabled without causing a problem use the flag Otherwise use the corresponding bits ILVL2 to ILVLO for the interrupt whose interrupt generate factor is to be changed Refer to 20 5 6 Rewrite the Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution Figure 20 2 Procedure for Changing the Interrupt Generate Factor 20 5 5 INT Interrupt Either an L level of at least tw INL width or an level of at least tw INH width is necessary for the signal input to pins INTO through INTI regardless of the CPU operation clock If the POL bit in registers INTOIC to INTIIC or bits IFSR1 to IFSRO in the IFSR register are changed the IR bit may inadvertently set to 1 interrupt requested Be sure to clear the IR bit to 0 interrupt not requested after changing any of those register bits R01UHO197EJ0120 Rev 1 20 ztENESAS Page 311 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 5 6 Rewriting the Interrupt Control Register a The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur Otherwise disable the interrupt before rewriting the interrupt control register b To rewrite the interrupt control register for
362. re 15 5 The initial value is 05h CSMA Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBCSMACON2 0113h 05h Bit Symbol Bit Name Function T 1 1 L L 1 1 L 4 Sets the value of macMaxBE Set to 0 i 1 1 i L L 1 L L 1 1 1 1 L L L 1 L 1 1 uU Figure 15 29 CSMA Control Register 2 Configuration RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 223 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 24 PAN Identifier Register This register is for setting PAN identifiers It consists of 16 bits and is used to detect a match with the PAN identifier of a receive frame PAN Identifier Register b15 b8 b7 b0 b7 Symbol Address After Reset BBPANID 0115h 0114h 0000h Function PAN identifier Figure 15 30 PAN Identifier Register Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 224 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 22 Short Address Register This register is for setting short addresses It consists of 16 bits and is used to detect a match with the short address of a receive frame Short Address Register b15 b8 b7 b7 b0 Symbol Address BBSHORTAD 0117h 0116h After Reset 0000h Function Short address Figure 15 31 Short Address Register Configuration 15 2 23 Extended Address Register This register is for setting
363. re the command execution 1 Flash memory status detection NOTES Read bits FMROO FMRO6 FMRO7 in the FMRO register by program Execute the read status register command to read bits SR7 SR5 and SR4 in the status register Read bits FMROO FMRO6 FMRO7 in the FMRO register by program 1 Do not generate an interrupt except NMI interrupt or start a DMA transfer 2 When in CPU rewrite mode PM10 bit in the PM1 register is set to 1 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 24 NC SAS Page 258 of 331 M16C 6B Group 18 Flash Memory 18 3 4 Mode The microcomputer enters CPU rewrite mode by setting the FMROI bit in the FMRO register to 1 CPU rewrite mode enabled and is ready to accept commands EWO mode is selected by setting the FMR60 bit in the FMR6 register to 0 Figure 18 5 shows Setting and Resetting of Mode The software commands control programming and erasing The FMRO register or the status register indicates whether a program or erase operation is completed as expected or not 18 3 2 EW1 Mode EW1 mode is selected by setting the FMR60 bit to 1 after setting the FMROI bit to 1 Figure 18 6 shows Setting and Resetting of EW1 Mode The FMRO register indicates whether or not a program or erase operation has been completed as expected The status register cannot be read in mode When a program erase operation is initiated the CPU halts all program executio
364. reby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renes
365. register is 0 DMA disabled If the DAD bit is 1 forward direction this register can be written to at any time If the DAD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written to it can be read DMAi Transfer Counter i 0 to 3 b8 b0 b7 bO Symbol Address After Reset TCRO 0189h to 0188h Indeterminate TCR1 0199h to 0198h Indeterminate TCR2 01A9h to 01A8h Indeterminate TCR3 01B9h to 01B8h Indeterminate Function Setting Range Set the transfer count minus 1 The written value is stored in the DMAi transfer counter reload register and when the DMAE bit in the DMiCON register is set to 1 DMA enabled or the DMAi transfer counter underflows when the DMASL bit in the DMiCON register is 1 repeat transfer the value of the transfer counter reload register is transferred to the DMAi transfer counter When read the DMAi transfer counter is read 0000h to FFFFh Figure 11 6 Registers DARO to DAR3 and TCRO to TCR3 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 92 of 331 Jul 21 2011 M16C 6B Group 11 DMAC 11 1 Transfer Cycles Transfer cycle is composed of a bus cycle to read data from source address source read and a bus cycle to write data to destination address destination write The number of read and write bus cycles depends on source and destination addresses The bus cycle itself is extended by a software wait 11
366. rnal RAM or internal ROM Figure 6 2 PM1 Register Program 2 Area Control Register ODDIDA Symbol Address After Reset 1 1 LI 1 1 LI PRG2C 0010h XXXXXXXO0b Function 0 Enable program ROM 2 1 Disable program ROM 2 pr Set to 0 L L L L L L L L L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a NOTE 1 Write to this register after setting the PRC6 bit in the PRCR register to 1 write enabled Figure 6 3 PRG2C Register R01UHO197EJ0120 Rev 1 20 ztENESAS Page 34 of 331 Jul 21 2011 M16C 6B Group 6 Processor Mode 6 3 Internal Memory The internal RAM can be used in all processor modes The internal ROM is used in single chip mode Three internal ROMs are available data flash program ROM 2 and program ROM 1 Data flash includes block A addresses OE000h to OEFFFh and block B addresses OF000h to OFFFFh When data flash is enabled by the setting of the PM10 bit in the PM1 register both block A and block B can be used Table 6 3 lists Data Flash Addresses OE000h to OFFFFh Table 6 3 Data Flash Addresses 0E000h to OFFFFh PUTO BR PMI Single chip mode Data flash Set the PRG2CO bit in the PRG2C register to select program ROM 2 Table 6 4 lists Program ROM 2 Addresses 10000h to 13FFFh Do not use the last 16 bytes addresses 13FFOh to 13FFFh when using program ROM 2 in single chip mode or memory expansion mode These bytes ar
367. roducts or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of interna
368. rrors insert capacitors between pins VCC VREF analog input ANi i 0 to 7 and VSS Similarly insert a capacitor between pins VCC and VSS Figure 20 3 shows an Example Connection of Individual Pin Make sure the port direction bits corresponding to the pins that are used as analog inputs are set to 0 input mode When using key input interrupts do not use any of the four pins AN4 to AN7 as analog inputs A key input interrupt request is generated when the A D input voltage goes low When changing an A D operating mode set bits CH2 to CHO in the ADCONO register and bits SCAN1 to SCANO in the ADCONI register again to select analog input pins Microcomputer C1 C2 H gt ak ANi ANi i 0 to 7 NOTES 1 C1 2 0 47 uF C2 gt 0 47 uF gt 100 pF 4 gt 0 1 uF C5 gt 0 1 uF reference 2 Use thick and shortest possible wiring to connect capacitors Figure 20 3 Example Connection of Individual Pin R01UHO197EJ0120 Rev 1 20 ztENESAS Page 324 of 331 Jul 21 2011 M16C 6B Group 20 Precautions When A D conversion is forcibly terminated by setting the ADST bit in the ADOCONO register to 0 A D conversion stops by program during A D conversion the A D conversion result is undefined The ADi register not performing A D conversion may also be undefined If the ADST bit is set to 0 by program during A D conversion do not use values obtained from any ADi registers The applied intermediate potential may
369. rsion stop Set the ADST bit to 0 Interrupt request generation timing Completion of A D conversion Analog input pin Select one pin from ANO to AN7 Reading of result of A D converter Read one of the registers ADO to AD7 that corresponds to the selected pin R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 181 of 331 M16C 6B Group 14 A D Converter 64 Pin Version Only A D Control Register 0 b7 be b5 b4 b3 b2 bi bO Symbol Address After Reset Tofo 2 ADCONO 03D6h 00000XXXb Bit Symbol Bit Name Function o N CHO Select ANO Select AN1 Select AN2 Select AN3 Select AN4 Select AN5 Select AN6 RW Select AN7 CH1 Analog input pin select bit 0000 00 007 202090292298 A D operation mode select b4 b3 RW bit 0 0 0 One shot mode BW Reserved bit Set to 0 RW 0 A D conversion stop 1 A D conversion start di A D conversion start flag Frequency select bit 0 Refer to NOTE 2 of the ADCON2 Register RW 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset olol iol L ADCON1 03D7h 0000X000b i SCANO A D sweep pin select bit Invalid in one shot mode iy operation mode select Set to 0 when one shot mode is selected RW No register bit If necessary set to 0 Read as u
370. rt flag 0 Stop counting 1 Start counting Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer BO count start flag Timer B1 count start flag Timer B2 count start flag 12 Timers Up Down Flag b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0324h 00h TAQUD Timer AO up down flag 0 Decrement 1 Increment TA1UD A1 up down flag Enabled during event counter mode when not TA2UD Timer A2 up down flag 5 two phase pulse signal Timer A3 up down flag Timer A4 up down flag Timer A2 two phase 0 Two phase pulse signal processing pulse signal processing disabled select bit 9 1 Two phase pulse signal processing enabled 1 2 Timer A3 two phase pulse signal processing select bit 9 Timer A4 two phase pulse signal processing select bit 9 1 Set the port direction bits for pins TA2IN to TA4IN and pins TA2OUT to TA4OUT to 0 input mode 2 When not using the two phase pulse signal processing function set the bit corresponding to Timer A2 to Timer A4 to 0 3 64 pin version only Figure 12 8 Registers TABSR and UDF RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 105 of 331 Jul 21 2011 R01UH0197EJ0120 Rev 1 20 Jul 21 2011 M16C 6B Group One Shot Start Flag 7 b6 b5 b4 b3 b2 bi bd Symbo ONSF Address 0322h 12 Timers After Reset 00h Bit Symbol Bit Name TAOOS AO o
371. rupt enable 0 Disabled Enabled Reserved bits Set to 0 Figure 9 15 KICON1 Register RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 79 of 331 Jul 21 2011 M16C 6B Group 9 9 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register i 0 to 3 Set the start address of any instruction in the RMADi register Use bits AIERO and in the ATER register and bits AIER20 and AIER21 in the AIER2 register to enable or disable the interrupt Note that the address match interrupt is unaffected by the I flag and IPL When address match interrupt requests are acknowledged the value of the PC that is saved to the stack area refer to 9 5 7 Saving Registers varies depending on the instruction at the address indicated by the RMADi register The value of the PC that is saved to the stack area is not the correct return address Therefore follow one of the methods described below to return from the address match interrupt Rewrite the content of the stack and then use the REIT instruction to return Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return Table 9 8 lists the Value of the PC That Is Saved to the Stack Area When an Address Match Interrupt Request is Accepted Note that when using the
372. rupt request are acknowledged SFRs are allocated from address 00000h to 003FFh and from O0D000h to OD7FFh Peripheral function control registers are located here All blank spaces within SFRs are reserved and cannot be accessed by users The special page vectors are addressed from FFEO0h to FFFD7h They are used for the JMPS instruction and JSRS instruction Refer to the M16C 60 M16C 20 and M16C Tiny Series Software Manual for details 00000h 00400h XXXXXh 0D000h 0D800h 0E000h Internal ROM data flash Special page 10000h Internal ROM vector table program ROM 2 14000h Reserved area BRK instruction Internal RAM Internal ROM Address match Address XXXXXh Address YYYYYh Single Eo 20 Kbyt 053FFh 192 Kbytes D0000h YYYYYh peed ytes DBC un EC ANS NE rm E FFFFFh Figure 3 1 Memory Map R01UHO0197EJ0120 Rev 1 20 ztENESAS Page 15 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs 4 Special Function Registers SFRs An SFR Special Function Register is a control register for a peripheral function Tables 4 1 to 4 14 list SFR information Table 4 1 Address SFR Information 1 1 Register After Reset 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PMO 00000000b 2 0005h Processor Mode Register 1 PM1 00001000b 0006h System Clock Control Register 0 CMO 01001000b 0007h System
373. ry from Rewriting RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 283 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 6 Notes on Flash Memory 18 6 1 Functions to Prevent Flash Memory from Being Rewritten Addresses OFFFDFh OFFFE3h OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh store ID codes When the wrong data is written to these addresses the flash memory cannot be read or written to in standard serial I O mode OFFFFFh is OFS1 address When the wrong data is written to this address the flash memory cannot be read or written to in parallel I O mode These addresses correspond to the vector address H in fixed vector 18 6 2 Reading Data Flash When 2 2 V VCC lt 2 7 V one wait must be inserted to execute the program on the data flash and read the data Set the PM17 in the PM1 register or FMR17 bit in the FMRI register to insert one wait 18 6 3 CPU Rewrite Mode 18 6 3 1 Operating Speed Set a CPU clock frequency of 8 MHz or less by the CMO6 bit in the register and bits CM17 and CM16 in the register before entering CPU rewrite mode EWO or EW1 mode Also set the PM17 bit in the PM1 register to 1 wait state 18 6 3 2 CPU Rewrite Mode Select Change FMRO1 bit in the FMRO register FMR11 bit in the FMR1 register and FMR60 bit in the FMR6 register while in the following state PM24 bit in the PM2 register is 0 NMI interrupt disabled High is input to the NMI pin 18 6 3 3 Prohib
374. s TA1IC Timer A2 Interrupt Control Regis TA2IC Timer A3 Interrupt Control Regis Timer 4 Interrupt Control Regis TA4IC Timer BO Interrupt Control Regis TBOIC Timer B1 Interrupt Control Regis TB1IC Timer B2 Interrupt Control Regis TB2IC INTO Interrupt Control Register INTOIC INT1 Interrupt Control Register INT1IC Processor Mode Register 2 Timer Compare 2 Interrupt Control Register BBTIM2IC DMA2 Interrupt Control Register DM2IC DMAS Interrupt Control Register DM3IC Transmit Complete Interrupt Control Register BBTXIC Bank 0 Receive Complete IDLE Interrupt Control Register BBRXOIC BBIDLEIC Bank 1 Receive Complete Clock Regulator Interrupt Control Register BBRX1IC BBCREGIC Address Filter Interrupt Control Register BBADFIC CCA Complete Interrupt Control Register BBCCAIC PLL Lock Detection Interrupt Control Register BBPLLIC Transmit Overrun Interrupt Control Register BBTXORIC Receive Overrun 0 Interrupt Control Register BBRXOROIC Receive Overrun 1 Interrupt Control Register BBRXOR1IC LED Port Switch Register LEDCON Key Input Control Register 0 KICONO
375. s 6 to 0 in the register and the 8th bit DO is stored in bit 8 in the UiRB register Even when the 2 bit 1 providing the CKPH bit 1 the same data as when the 2 bit 0 can be read To read the data read the UiRB register after the rising edge of 9th bit of the corresponding clock pulse RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 164 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface 13 1 3 7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to 0 start and stop conditions not generated and the ACKC bit in the UiSMR4 register is set to 1 ACK data output the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin If the IICM2 bit 0 the NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse The ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse If ACKi is selected to generate a DMA1 or DMA3 request source a DMA transfer can be activated by detection of an acknowledge 13 1 3 8 Initialization of Transmission Reception If a start condition is detected while the STAC bit 2 1 UARTI initialization enabled the serial interface operates as described below The transmit shift register is initialized and the content of the UiTB register is transferred to the transmit shift register In this way the serial interface starts sending data synchro
376. s and phases 0102 NOTES 1 When an external clock is selected the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in high state if the CKPOL bit 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in L state 2 If an overrun error occurs the received data of the UiRB register will be indeterminate The IR bit in the SIRIC register does not change P7 2 CLK2 CLK2 P7 1 RXD2 RXD2 P7 0 TXD2 Microcomputer master Microcomputer slave Figure 13 31 Special Mode 2 Communication Control Example UART2 R01UHO197EJ0120 Rev 1 20 24 N SAS Page 166 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Table 13 16 Registers Used and Settings in Special Mode 2 Register 0 to 7 Function Set transmission data 0 to 7 Reception data can be read OER Overrun error flag 0 to 7 Set a bit rate SMD2 to SMDO Set to 001b CKDIR Set to 0 in master mode or 1 in slave mode IOPOL Set to 0 CLKO CLK1 Select the count source for the UiBRG register CRS Invalid because CRD 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select TXDi pin output format 2 C
377. s to wait mode or to stop mode A current flows in active output ports A pass current flows to input ports in high impedance state When entering wait mode or stop mode set non used ports to input and stabilize the potential A D converter 64 pin version only When A D conversion is not performed set the ADSTBY bit in the ADCONI register to 0 A D operation stop When A D conversion is performed start the A D conversion at least 1 cycle or longer after setting the ADSTBY bit to 1 A D operation enabled Stopping peripheral functions Use the 2 bit in the register to stop the unnecessary peripheral functions during wait mode Switching the oscillation driving capacity Set the driving capacity to L when oscillation is stable R01UH0197EJ0120 Rev 1 20 ztENESAS Page 309 of 331 Jul 21 2011 M16C 6B Group 20 Precautions 20 5 Interrupt 20 5 1 Reading address 00000h Do not read the address 00000h in a program When a maskable interrupt request is accepted the CPU reads interrupt information interrupt number and interrupt request priority level from the address 00000h during the interrupt sequence At this time the IR bit for the accepted interrupt is cleared to 0 If the address 00000h is read in a program the IR bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0 This factors a problem that the interrupt is canceled or an unexpected interrupt request
378. set to U2BRG The U2LCH bit in the U2C1 register 0 no reverse The U2IRS bit in the U2C1 register 1 transmit completed NOTES 1 Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit 2 Because pins TXD2 and RXD2 are connected a composite waveform consisting of transmit waveform from the TXD2 pin and parity error signal from the receiving end is generated 3 Because pins TXD2 and RXD2 are connected a composite waveform consisting of transmit waveform from the transmitting end and parity error signal from the TXD2 pin is generated Figure 13 36 Transmit and Receive Timing in SIM Mode R01UH0197EJ0120 Rev 1 20 ztENESAS Page 174 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface Figure 13 37 shows an Example of SIM Interface Connection Connect TXD2 and RXD2 and then place a pull up resistance Microcomputer SIM card Figure 13 37 Example of SIM Interface Connection 13 1 6 1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 error signal output The parity error signal is output when a parity error is detected while receiving data A low level signal is output from the TXD2 pin in the timing shown in Figure 13 38 If the U2RB register is read while outputting a parity error signal the PER bit is cleared to 0 no parity error and at the same time the TXD2 output is returned
379. sion When this bit is 0 frame transmission continues even if an unlock occurs When this bit is 1 transmit operation stops if an unlock occurs Make sure to set the PLLINTSEL bit to 0 unlock detected when using this function As IDLE status is selected after operation stops set to transmission or reception again The UNLOCKSTPR bit can be used to set the operation if an unlock occurs during reception When this bit is 0 frame reception is not terminated even if an unlock occurs and the reception continues until its end When this bit is 1 reception is terminated if an unlock occurs and the status transits to reception standby Whether an unlock has occurred or not during reception can be confirmed by using the UNLOCKST bit in the BBTXRXSTI register which is set when reception is completed Make sure to set the PLLINTSEL bit to 0 unlock detected when using this function The BANKOINTSEL bit can be used to select a bank 0 reception compete interrupt or an IDLE interrupt The BANKIINTSEL bit can be used to select a bank 1 reception complete interrupt or a clock regulator interrupt Transmit Receive Mode Register 4 Symbol Address BBTXRXMODE4 0111h gt cea ee ME 08088 2 0 When CCA sequence is completed CCAINTSEL CCA interrupt select bit 1 When CSMA CA sequence is completed 0 Unlock detected 1 Lock detected PLLINTSEL PLL lock detection select bit UNLOCKSTPT Operation stop enable bit after 0 Disab
380. sion start flag 1 A D conversioh start Frequency select bit 0 Refer to NOTE 2 of the ADCON Register NOTE 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi bO 0 Symbol Address After Reset ADCON1 03D7h 0000X000b When repeat sweep mode 1 is selected b1 bO 0 0 ANO 1 pin 0 1 ANO to AN1 2 pins 1 0 ANO to AN2 3 pins 1 1 ANO to AN3 4 pins 1 Repeat sweep mode 1 No register bit If necessary set to 0 Read as undefined value Set to 1 A D operation enabled RW NOTES 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the ADSTBY bit is changed from 0 A D operation stopped to 1 A D operation enabled wait for 1 AD cycle or more before starting A D conversion A D sweep pin select bit 1 Figure 14 8 Registers ADCONO and ADCONI in Repeat Sweep Mode 1 RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 190 of 331 Jul 21 2011 M16C 6B Group 14 A D Converter 64 Pin Version Only 14 2 Conversion Rate The conversion rate is defined as follows Start dummy time depends on which AD is selected Table 14 7 lists Start Dummy Time When the ADST bit in the ADCONO register is set to 1 A D conversion start A D conversion starts after start dummy time elapses 0 A D conversion stop is read if the ADST bit is read
381. smission the NOCRC bit can be used to select whether to add the CRC result automatically or only to transmit data in transmit RAM The FLMPEND bit can be used to specify the value to be set in the pending bit in an ACK frame The information of this bit is automatically included in the automatic ACK response frame The FLMPEMDST bit indicates whether an ACK frame is responded with pending or without pending for automatic ACK response This bit is updated at the same time as a bank 0 1 reception complete interrupt request is generated when ACK response is completed The FLMPEMDST bit reflects the result of automatic ACK response performed for each bank which received a frame with an ACK request When reading this bit it returns the frame pending information when an ACK is responded with the receive RAM data in the bank which is selected with the RCVBANKSEL bit in the BBTXRXMODES register Transmit Receive Mode Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBTXRXMODE2 0109h 00h NOCRC CRC disable bit pi aeque RW 1 Disabled FLMPEND Frame pending bit 0 No frame pending RW 1 Frame pending 0 ACK frame response with no frame FLMPENDST Frame pending status bit 1 pending 1 ACK frame response with frame pending b7 b3 No register bits If necessary set to 0 Read as 0 e 1 This bit corresponds to the receive RAM bank Figure 15 19 Transmit Receive Mode Register 2 Configuration RO1UH0197EJ0120 Rev
382. stable 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products How to Use This Manual 1 Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU It is intended for users designing application systems incorporating the MCU A basic knowledge of electric circuits logical circuits and MCUs is necessary in order to use this manual The manual comprises an overview of the product descriptions of the CPU system control functions peripheral functions and electrical characteristics and usage notes Particular attention should be paid to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details The following documents apply to the M16C 6B Group Make sure to refer to the latest versions of
383. status flag b7 This bit indicates the auto erase operation state Condition to become 0 Execute the clear status command Condition to become 1 Refer to 18 3 7 Full Status Check The following commands cannot be accepted when the FMRO7 bit is 1 Program block erase lock bit program read lock bit status and block blank check R01UHO197EJ0120 Rev 1 20 24 NC SAS Page 261 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory 18 3 3 2 Flash Memory Control Register 1 FMR1 Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset FMR1 0221h 00X0XX0Xb Bit Symbol Bit Name Function b0 Reserved bit Read as undefined value ese st No register bit If necessary set to 0 Read as undefined value b5 0 Lock FMR16 Lock bit status flag 1 Unlock 0 1 wait Data flash wait bit 1 Follow the setting of the PM17 bit in the PM1 register Write to FMR6 register 0 Disabled RW enable bit 1 Enabled Reserved bits Read as undefined value RO Reserved bit Set to 0 RW FMR11 Write to FMR6 register enable bit b1 Change the FMR11 bit when the PM24 bit in the PM register is 0 NMI interrupt disabled or low is input to the NMI pin FMR16 Lock bit status flag b6 This bit indicates the execution result of the read lock bit status command FMR17 Data flash wait bit b7 This bit is used
384. ster Allow a delay for the reception complete interrupt Set the RCVBANKSEL bit in the BBTXRXMODES register for bank selection 0 Read the BBRXFLEN register 1 2 m nmm om om cc Confirm the CRC result by using the CRC bit in the BBTXRXSTO register Read receive RAM data addresses D180h to DIFEh NOTES 1 Steps 2 to 6 can be interchanged 2 When the automatic ACK response function is enabled a transmission complete interrupt is generated when ACK response is completed If no transmission complete interrupt is required set the priority level of the interrupt to O disabled RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 236 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 3 3 1 2 AU cc 5 6 CCA Procedure Example Set 1 baseband functions enabled in the BBEN bit in the BBCON register Set O1h 1 ms in the BBIDLEWAIT register Set 1 IDLE interrupt in the BANKOINTSEL bit in the BBTXRXMODEF4 register Set 1 RF power ON in the RFPWRON bit in the BBRFCON register and 1 XIN power ON in the XINPWRON bit Use registers BBPLLDIVL and BBPLLDIVH for channel setting After the IDLE interrupt is generated after the wait time set in the BBIDLEWAIT register has elapsed from step 2 Set 1 clock regulator in the XINREGSEL bit in the BBRFCON register Set the setting value in the BBRFINI register Set 1 CCA start in the CCATRG bit in the BBTXRXCON register Allow a
385. ster contents and continues counting Divide ratio 1 1 n set value of the TBi register 0000h to FFFFh Count start condition Set the TBiS bit 1 to 1 start counting Count stop condition Set the TBiS bit to 0 stop counting Interrupt request generation timing Timer underflow Read from timer Count value can be read by reading the TBi register Write to timer i 0to5 NOTE When not counting Value written to the TBi register is written to both reload register and counter When counting Value written to the TBi register is written to only reload register transferred to counter when reloaded next 1 Bits TBOS to TB2S are assigned to bits 5 to 7 in the TABSR register and bits TB3S to TB5S are assigned to bits 5 to 7 in the TBSR register Timer Bi Mode Register i 0 to 5 b7 b6 b5 b4 b3 b2 b1 bO LL DOAN Symbol Address After Reset TBOMR to TB2MR 033Bh to 033Dh 00XX0000b TB3MR to TB5MR 031Bh to 031Dh 00XX0000b nd Operation mode select bit 0 1 Event counter mode No register bits If necessary set to 0 Read as undefined value Invalid in event counter mode Set 0 or 1 TCKO Write 0 in event counter mode Read as undefined value in event counter mode 1 TBj underflow TER OTE jai 1 however j 2ifi 0 j 5ifi 3 1 Set to 1 in event counter mode Figure 12 24 TBiMR Register in Event Counter Mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Pa
386. supplying the necessary clock for the microcomputer R01UHO197EJ0120 Rev 1 20 ztENESAS Page 43 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 2 CPU Clock and Peripheral Function Clock Two types of clock exists CPU clock to operate the CPU Peripheral function clocks to operate the peripheral functions 7 2 1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer The main clock subclock or 125 kHz on chip oscillator clock can be selected as the clock source for the CPU clock When the main clock or 125 kHz on chip oscillator clock is selected as the clock source for the CPU clock the selected clock source can be divided by 1 undivided 2 4 8 or 16 to produce the CPU clock Use the CM06 bit in the CMO register and bits CM17 and CM16 in the CM1 register to select a divide by n value After reset the 125 KHz on chip oscillator clock divided by 8 provides the CPU clock Note that when entering stop mode or when the CMO5 bit in the CMO register is set to 1 stop in low speed mode the CMO6 bit in the register is set to 1 divide by 8 mode RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 44 of 331 Jul 21 2011 M16C 6B Group 7 Clock Generation Circuit 7 2 2 Peripheral Function Clock f1 fC32 These are operating clocks for the peripheral functions fl 15 produced from the main clock or the 125 kHz on chip oscillator clock and is used for timers and B UARTO to UART2 and
387. t Pulse Width Measurement Modes 64 Pin 48 Pin 64 Pin 48 Pin 64 Pin 48 64 Pin 48 Pin 64 Pin 48 Pin Available Trigger from the internal timer overflows underflows is available Trigger from the external pin or the output function to the external pin is not available x Not available bo PPI5Ib b5boIo ojo R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 98 of 331 M16C 6B Group 12 Timers 1c32 fOCO S fe4TIMAB 2 f8TIMAB fi TIMAB or f2TIMAB TCK1 to TCKO TMOD1 to TMODO 00 Timer mode 10 One shot timer mode 11 PWM mode Q 10 i Timer A0 interrupt O 00 c 01 Event counter mode 11 TAOTGH to TAOTGL lo lo 5 OO ZEE 5 5 TAOIN Noise gt TCK1 to TCKO TMOD1 to TMODO 00 Timer mode 10 One shot timer mode Q 11 PWM mode S Timer A1 interrupt t ee poo 00 01 Event counter mode 11 TA1TGH to 5 SIS W TCK1 to Q TMOD1 to TMODO 00 Timer mode 0 10 One shot timer mode 9 11 PWM mode PS Timer A2 interrupt oo 01 Event counter mode 2 TA2TGH to TA2TGL 2 OO
388. t If necessary set to 0 Read as undefined value Operation select bit 0 Oscillation stop detection reset CM27 when an oscillation stops and 1 Oscillation stop re oscillation detection RW re oscillation is detected 10 interrupt Rewrite this register after setting the PRCO bit in the PRCR register to 1 write enabled When the 20 bit is set to 1 oscillation stop and re oscillation detection function enabled the CM27 bit is set to 1 oscillation stop and re oscillation detection interrupt and the CPU clock source is the main clock the 21 bit is set to 1 125 kHz on chip oscillator clock if the main clock stop is detected If the CM20 bit is set to 1 and the CM23 bit is set to 1 main clock stops do not set the CM21 bit to 0 This bit is set to 1 when the main clock stop is detected and the main clock re oscillation is detected When this flag changes state from 0 to 1 an oscillation stop or a re oscillation detection interrupt is generated Use this bit in an interrupt routine to determine the factors of interrupts between the oscillation stop re oscillation detection interrupt and the watchdog timer interrupt This bit is set to 0 by writing 0 in a program This bit remains unchanged even if a 1 is written Nor is it set to 0 when an oscillation stop or a re oscillation detection interrupt request is acknowledged When the CM22 bit is set to 1 and an oscillation stop or a re oscillation is detected an oscil
389. t disabled if the lock bit in the block where the error occurred is set to 0 locked 3 Execute the block erase command again 4 Execute 1 2 and 3 at least 3 times until an erase error is not generated NOTE 1 If similar error still occurs the block cannot be used If the lock bit is set to 1 unlocked in 2 above the block cannot be used FMRO06 0 When a program operation is executed 1 Execute the clear status register command and set the FMRO6 bit to 0 completed as expected 2 Execute the read lock bit status command and set the FMRO2 bit to 1 if the lock bit in the block where the error occurred is set to 0 3 Execute the program command again NOTE 2 If similar error occurs the block cannot be used If the lock bit is set to 1 in 2 above the block cannot be used When a lock bit program operation is executed 1 Execute the clear status register command and set the FMRO6 bit to 0 2 Set the FMRO2 bit in the FMRO register to 1 3 Execute the block erase command to erase the block where the error occurred 4 Execute the lock bit program command again Full status check NOTE completed 3 If similar error occurs the block cannot be used NOTE 4 When either the FMRO6 or FMRO7 bit is set to 1 terminated by error the program block erase lock bit program block blank check and read lock bit status commands cannot be accepted Execute the clear status register command before
390. t for using key input interrupts Figure 9 13 shows the Block Diagram of Key Input Interrupt While input on any pin which has had bits KIENO to KIEN7 in registers KICONO and KICONI set to 1 enabled is pulled low inputs on all other pins of the port are not detected as interrupts Table 9 7 Key Input Interrupt Setting Key Input Control Key input control register 0 Address 00082h Disabled Enabled Key input control register 0 00082h Disabled Enabled Key input control register 0 00082h Disabled Enabled Key input control register 0 00082h Disabled Enabled Key input control register 1 00083h Disabled Enabled Key input control register 1 00083h Disabled Enabled Key input control register 1 00083h Disabled Enabled NOTES 1 64 version only Key input control register 1 2 Inthe 48 pin version the KINO to KING interrupts are disabled 00083h Disabled Enabled R01UH0197EJ0120 Rev 1 20 RENESAS Jul 21 2011 Page 77 of 331 M16C 6B Group 9 Interrupt PU16 bit in PUR1 register m KUPIC register PD7_3 bit in PD7 register PD7_3 bit in PD7 register KIEN7 bit in KICON1 register transistor 4 Direction register Pull up KIENS bit in KICON1 register transistor T Interrupt control Key npu K6 O circuit realest Direction register KIENS bit in KICON1 register Direction register
391. t Timing Set Register This register is for setting the timing for the ANTSWCONT pin output After setting the TRNTRG bit in the BBTXRXCON register to 1 transmission start the time to drive the ANTSWCONT pin output to high can be set The setting value is available from 01h to 8Dh and the initial value is 72h the setting value is 1h about 1 us Do not set values other than 01h about 1 us to 8Dh about 141 us ANTSW Output Timing Set Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset BBANTSWTIMG 017Ah 72h T T 1 1 1 1 1 1 1 1 1 1 4 E ee eee eee ee Bt Syma Bt Syma Binme Name o Ami Sets the timing for the ANTSWCONT pin Quiputitiming set output The setting value is 01h to 8Dh ES T 1 1 1 L Figure 15 43 ANTSW Output Timing Set Register Configuration R01UH0197EJ0120 Rev 1 20 ztENESAS Page 234 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 35 RF Initial Set Register This is a 16 bit register is for the initial setting in the RF block The setting is performed while in IDLE status To set this register set the higher and lower bytes at the same time or set data in the lower byte first and then the higher byte To set this register again after having set data once allow 40 cycles or more of f BCLK However access to other registers is enabled If IDLE status is cha
392. t are performed over a period from the instant an interrupt request is accepted to the instant the interrupt routine is executed is described here If an interrupt request occurs during execution of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle If an interrupt occurs during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence The CPU behavior during the interrupt sequence is described below Figure 9 5 shows Time Required for Executing Interrupt Sequence 1 The CPU obtains interrupt information interrupt number and interrupt request level by reading address 00000h Then the IR bit applicable to the interrupt information is set to 0 interrupt not requested 2 The register prior to an interrupt sequence is saved to a temporary register within the CPU 3 Flags L D and U in the FLG register become as follows The I flag is set to O interrupt disabled The D flag is set to O single step interrupt disabled The U flag is set to 0 ISP selected Note that the U flag does not change states if an INT instruction for software interrupt Nos 32 to 63 is executed 4 The temporary register 1 within the CPU is saved to the stack 5 The PC is saved to the stack
393. t this bit to 1 when bits SMD2 to SMDO are set to 010b 12C mode and to 0 when bits SMD2 to SMDO are set to 100b UART mode 7 bit transfer data or 110b UART mode 9 bit transfer data CTST RTST can be used when the CLKMD1 bit in the register 0 only CLK1 output and the RCSP bit in the UCON register 0 CTSO RTSO not separated Selected by the PCLK1 bit in the PCLKR register When changing bits CLK1 and CLKO set the UiBRG register UiBRG count source select function select Transmit register empty flag CTS RTS disable bit Data output select bit Figure 13 7 Registers UOCO to U2CO RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 132 of 331 Jul 21 2011 M16C 6B Group 13 Serial Interface UARTIi Transmit Receive Control Register 1 i 0 1 b7 b6 b5 b4 b3 b2 61 bO Symbol Address After Reset U0C1 U1C1 024Dh 025Dh 00XX0010b Bit Symbol Bit Name Function TE Transmit enable bit Transmission Head 1 Transmission enabled 0 Data present in UiTB register Transmit buter empty fag 1 No data present in UiTB register 0 Reception disabled 1 Reception enabled Recaive combletadia 0 Data present in UiRB register p 9 1 No data present UiRB register No register bits If necessary set to 0 Read as undefined value Receive enable bit 654 b4 UiLCH logic select bit 0 No reverse 1 Reverse 0 Output disabled UiERE Error signal output enab
394. tatus of each block is set to 1 after an erase operation is completed Refer to 18 3 4 Software Commands for details on each command 18 3 6 Status Register The status register indicates the flash memory operation state and whether or not an erase or program operation is completed as expected Bits FMRO0 FMRO6 FMRO7 in the FMRO register indicate status register states Table 18 11 lists the Status Register In EWO mode the status register can be read when the followings occur Any even address in the program ROM 1 program ROM 2 or data flash is read after writing the read status register command Any even address in the program ROM 1 program ROM 2 or data flash is read from when the program block erase lock bit program or block blank check command is executed until when the read array command is executed 18 3 6 1 Sequence Status Bits SR7 and FMROO The sequence status indicates the flash memory operation state It is set to 0 while the program block erase lock bit program block blank check or read lock bit status command is being executed otherwise it is set to 1 18 3 6 2 Erase Status Bits SR5 and FMRO07 Refer to 18 3 7 Full Status Check 18 3 6 3 Program Status Bits SR4 and FMRO06 Refer to 18 3 7 Full Status Check RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 273 of 331 Jul 21 2011 M16C 6B Group 18 Flash Memory Table 18 11 Status Register Bits in Status Register Bitin FMRO
395. ted the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit in the UiCO register 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state 2 If an overrun error occurs the receive data of the UiRB register will be indeterminate The IR bit in the SIRIC register does not change to 1 interrupt requested 3 Bits UOIRS and U1IRS correspond to bits 0 and 1 in the UCON register respectively U2IRS bit is in U2C1 register respectively R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 140 of 331 M16C 6B Group 13 Serial Interface Table 13 2 Registers Used and Settings in Clock Synchronous Serial I O Mode Function Register UiTB 3 0 to 7 Set transmission data UiRB 39 0107 Reception data can be read OER Overrun error flag UiBRG 0 to 7 Set a bit rate UiMR 3 SMD2to SMDO Set to 001b CKDIR Select the internal clock or external clock IOPOL Set to 0 UiCO CLK1 to CLKO Select the count source for the UiBRG register CRS Select either CTS or RTS to use functions TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS
396. ter BBTIMECON 0135h Backoff Period Register BBBOFFPROD 0136h 0137h 0138h 0139h 013Ah PLL Division Register 0 BBPLLDIVL 013Bh PLL Division Register 1 BBPLLDIVH 013Ch Transmit Output Power Register BBTXOUTPWR 013Dh RSSI Offset Register BBRSSIOFS 013Eh 013Fh NOTE 1 The blank areas are reserved and cannot be accessed by users X Undefined RO1UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 19 of 331 M16C 6B Group 4 Special Function Registers SFRs Table 4 5 SFR Information 5 1 Address Register After Reset Verification Mode Set Register BBEVAREG IDLE Wait Set Register BBIDLEWAIT ANTSW Output Timing Set Register BBANTSWTIMG RF Initial Set Register BBRFINI NOTE X Undefined 1 The blank areas are reserved and cannot be accessed by users R01UH0197EJ0120 Rev 1 20 ztENESAS Page 20 of 331 Jul 21 2011 M16C 6B Group 4 Special Function Registers SFRs Table 4 6 Address 0180h 0181h 0182h SFR Information 6 1 DMAO Source Pointer Register After Reset 0183h 0184h 0185h 0186h DMAO Destination Pointer 0187h 0188h 0189h DMAO Transfer Counter 018Ah 0
397. ter 184 to 187 pw ee pe 00B8h to OOBBh OO0BCh to OOBFh 00COh to 00C3h 00C4h to 00C7h 00C8h to 00CBh 00CCh to OOCFh CCA complete 188 to 191 PLL lock detection 192 to 195 Transmission overrun 196 to 199 Reception overrun 0 200 to 203 Reception overrun 1 204 to 207 NOTES 1 Address relative to address in INTB 2 Switchable by using the BANKOINTSEL bit in the BBTXRXMODE4 register address 0111h 3 Switchable by using the BANK1INTSEL bit in the BBTXRXMODE4 register address 0111h t n RO1UH0197EJ0120 Rev 1 20 24 NC SAS Page 67 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 5 Interrupt Control The following describes how to enable disable the maskable interrupts and how to set the priority in which order they are accepted What is explained here does not apply to nonmaskable interrupts Use the I flag in the FLG register IPL and bits ILVL2 to ILVLO in each interrupt control register to enable disable the maskable interrupts Whether an interrupt is requested or not is indicated by the IR bit in each interrupt control register Figures 9 3 and 9 4 show the Interrupt Control Registers Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 61 b0 Figure 9 3 Symbol TB5IC TB4IC U1BCNIC 9 TB3IC UOBCNIC 9 BBTIMOIC BBTIM1IC BBTIM2IC BCNIC DMOIC to DM3IC KUPIC ADIC SOTIC to S2TIC SORIC to S2RIC TAOIC to TA4IC TBOIC to TB2IC
398. terface f1SIO or f2SIO f8SIO 32510 polarity ie mo O sc UART reception SMD2 to SMDO circuit 010 100 101 110 Receive em Transmit cloci i Clock source selection Clock sync type control circuit receive CLK1 to cipis 001 unit 0 Internal U2BRG register UART transmission Transmit 010 100 101 110 clock Clock sync type 001 Clock synchronous type when internal clock is selected Clock synchronous type Clock synchronous type when external clock is selected CKDIR when internal clock is selected CLK polarity reversing circuit CTS RTS disabled CTS RTS selected n values set to the U2BRG register PCLK1 bit in the PCLKR register SMD2 to SMDO CKDIR bits in the U2MR register CLK1 to CLKO CKPOL CRD CRS bits in the U2CO register NOTE 1 UART2 is an N channel open drain output CMOS output cannot be set Figure 13 3 UART2 Block Diagram RO1UH0197EJ0120 Rev 1 20 zeENESAS Page 128 of 331 Jul 21 2011 M16C 6B Group IOPOL No reverse 0 RXD data 2 reverse circuit 72 Reverse PC PRYE Clock sync STPS PAR 1SP disabled 0 0 Q Dir 1 1 1 28P PAR enabled UART 2i S SMD2 to SMDO D eT 9 bits PC UART PRYE SMD2 to SMDO bits PAR enabled PAR disabled clock sync type SP stop bit PAR parity bit i Oto2 SMD2 to SMDO STPS PRYE IOPOL CKDIR bits in the UIMR register CLK1 to CLKO CKPOL CRD CRS bits in t
399. the BBIDLEWAIT register has elapsed The wait time set in the BBIDLEWAIT register is automatically counted with XIN as the count source and a clock regulator interrupt request is generated after the regulator startup time has been waited Set bits RFPWRON and XINPWRON to 1 simultaneously The XINREGSEL bit can be used to switch the XIN power supply to a stable power supply To set this bit to 1 make sure the clock regulator has been started up RF Control Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address BBRFCON 0110h LONE PEE NR 0 OFF 1 RF power ON IDLE RFPWRON RF power ON bit 0 OFF AXINPWRON XIN power ON bit 1 XIN power ON 0 MCU regulator XINREGSEL XIN regulator switch bit 1 Clock regulator Reserved bits Set to 0 b7 b b6 No register bits If necessary set to 0 Read as 0 E Figure 15 26 RF Control Register Configuration R01UH0197EJ0120 Rev 1 20 24 NC SAS Page 221 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 18 Transmit Receive Mode Register 4 The CCAINTSEL bit can be used to select when a CCA sequence is completed or a CSMA CA sequence is completed as the generation source of a CCA interrupt The PLLINTSEL bit can be used to select when an unlock is detected or a lock is detected as the generation source of a PLL lock detection interrupt The UNLOCKSTPT bit can be used to set the operation when an unlock occurs during transmis
400. the interrupt control register so that even when interrupt requests are disabled and no interrupt request can be accepted DMA requests are always accepted Furthermore because the DMAC does not affect interrupts the IR bit in the interrupt control register does not change state due to a DMA transfer A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register 1 DMA enabled However if the cycle in which a DMA request is generated is faster than the DMA transfer cycle the number of transfer requests generated and the number of times data is transferred may not match Refer to 11 4 DMA Request for details Table 11 1 DMAC Specifications 3 No of channels 4 cycle steal method Transfer memory space From given address in the 1 Mbyte space to a fixed address From a fixed address to given address in the 1 Mbyte space From a fixed address to a fixed address Maximum No of bytes 128 Kbytes with 16 bit transfers or 64 Kbytes with 8 bit transfers transferred DMA request factors 1 2 Falling edge of INTO to INT1 Both edges of INTO to INT1 Timer AO to timer A4 interrupt requests Timer BO to timer B5 interrupt requests UARTO to 2 transmission interrupt requests UARTO to 2 reception ACK interrupt requests A D conversion interrupt requests 64 pin version only Software triggers Channel priority DMAO gt DMA1 gt DMA2 gt DMAO takes precedence Transfer unit 8 b
401. these documents The newest versions of the documents listed may be obtained from the Renesas Electronics Web site Document Type Description Document Title Document No User s manual Hardware specifications pin assignments memory M16C 6B Group This User s Hardware maps peripheral function specifications electrical User s Manual manual characteristics timing charts and operation description Hardware Note Refer to the application notes for details on using peripheral functions Application note Information on using peripheral functions and Available from Renesas Electronics application examples Web site Sample programs Information on writing programs in assembly language and C Renesas technical Product specifications updates on documents etc update 2 Notation of Numbers and Symbols The notation conventions for register names bit names numbers and symbols used in this manual are described below 1 Register Names Bit Names and Pin Names Registers bits and pins are referred to in the text by symbols The symbol is accompanied by the word register bit or pin to distinguish the three categories Examples the PMO3 bit in the PMO register P3 5 pin VCC pin Notation of Numbers The indication b is appended to numeric values given in binary format However nothing is appended to the values of single bits The indication h is appended to numeric values given in hexade
402. tions Figure 14 1 shows the A D Converter Block Diagram Figures 14 2 and 14 3 show the A D converter related registers Table 14 1 A D Converter Specifications Item Performance A D conversion method Successive approximation Analog input voltage 1 0 V to AVCC Operating clock 1 fAD divide by 2 of fAD divide by 3 of fAD divide by 4 of fAD divide by 6 of fAD Resolution 10 bit Integral nonlinearity error VREF AVCC VCC 2 3 8 V 3 VREF AVCC VCC 2 2 V 6 Operating modes Analog input pins One shot mode repeat mode single sweep mode repeat sweep mode 0 repeat sweep mode 1 8 pins ANO to AN7 A D conversion start condition Software trigger The ADST bit in the ADCONO register is set to 1 A D conversion start Conversion speed per pin NOTE 43 AD cycles minimum 1 Set AD frequency as follows When VCC 3 2 to 3 6 V 2 MHz lt AD lt 16 MHz When VCC 3 0 to 3 2 V 2 MHz lt 9AD lt 8 MHz When VCC 2 2 to 3 0 V 2 MHz x 9AD lt 4 MHz R01UH0197EJ0120 Rev 1 20 Jul 21 2011 ztENESAS Page 177 of 331 M16C 6B Group 14 A D Converter 64 Pin Version Only A D conversion rate selection iv nversion register Successive conversion registe ADCON register ADO register 16 bits AD1 register 16 bits AD2 register 16 bits AD3 register 16 bits Decoder AD4 register 16 bits for register AD5 register 16 bits AD6 register
403. tput Power Transmit Output Power Register b7 b6 b5 b4 b3 b2 b1 bO Symbol Address After Reset BBTXOUTPWR 013Ch 00h t L L 42 TXOUTPWR Transmit output power Refer to Table 15 4 b7 b5 No register bits If necessary set to 0 Read as 0 S Figure 15 39 Transmit Output Power Register Configuration Table 15 4 Correspondence Between Register Setting Values and Output Power Reference Data TXOUTPWR Output Power dBm TXOUTPWR Output Power dBm 00h Min 10h 01h 11h 02h 12h 03h 13h 14h 15h 16h Max NOTE 1 Set TXOUTPWR to 00h to 16h Do not use 17ht to 1 Fh RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 231 of 331 Jul 21 2011 M16C 6B Group 15 Baseband Functionality 15 2 31 RSSI Offset Register This register can be used to set an offset value as the RSSI value during CCA ED or reception The value can be used to adjust the power value read from the RSSI CCA result register to the power value input to the antenna Set the value to two s complement in dBm units The value set in the receive level threshold set register or CCA level threshold set register is compared with the value to be stored in the RSSI CCA result register the value added with the offset value set in the RSSI offset register Example If the value read from the RSSI CCA result register is FDh 3 dBm while the value set in the RSSI offset register is EEh initial va
404. ts logic reversed when read from the UiRB register Figure 13 24 shows Serial Data Logic Switching 1 When the UiLCH bit in the UiC1 Register 0 No Reverse Transfer LILILILILILILI LILI LILI LT LI Clock st bo pr oz Kos X pa Yos X pe 057 No Reverse 2 When the UiLCH Bit in the UiC1 Register 1 Reverse Transfer d l Clock TXDi ST 50 Di D2 D3 D4 D5 DO 074 SP Reverse ST start bit P parity bit SP stop bit i Oto2 The above applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge of the transfer clock the UFORM bit in the UiCO register 0 LSB first the STPS bit in the UiMR register 0 1 stop bit and the PRYE bit in the UIMR register 1 parity enabled Figure 13 24 Serial Data Logic Switching 13 1 2 5 TXD RXD I O Polarity Reverse Function This function reverses the polarities of the TXDi pin output and RXDi pin input The logic levels of all input output data including bits for start stop and parity are reversed Figure 13 25 shows the TXD and RXD I O Polarity Reverse 1 When the IOPOL Bit in the UiMR Register 0 No Reverse Transfer ui Clock TXDi 8 DO D1 D2 D3 D4 D5 ADe j D7 j P f SP No Reverse RXDi M ST A D0 Di D2 D5 f Do
405. ve Control Register 0 RT1 Transmit Receive Control Register 1 RT1 Receive Buffer Register Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2 RT2 Special Mode Register 4 U2SMR4 RT2 Special Mode Register 3 U2SMR3 RT2 Special Mode Register 2 U2SMR2 RT2 Special Mode Register U2SMR RT2 Transmit Receive Mode Register U2MR RT2 Bit Rate Register U2BRG RT2 Transmit Buffer Register U2TB RT2 Transmit Receive Control Register 0 U2CO RT2 Transmit Receive Control Register 1 U2C1 RT2 Receive Buffer Register U2RB Flash Memory Control Register 6 ART TO Special Mode Register 4 UOSMR4 ART TO Special Mode Register 3 UOSMR3 ART TO Special Mode Register 2 UOSMR2 ART Special Mode Register UOSMR ART TO Transmit Receive Mode Register UOMR ART Bit Rate Register UOBRG ART TO Transmit Buffer Register UOTB ART TO Transmit Receive Control Register 0 uoco ART TO Transmit Receive Control Register 1 UOC1 ART TO Receive Buffer Register UORB Blank columns are all reserved space No access is allowed Register Timer B3 B4 B5 Count Start Flag 0345h Register 0346h
406. ve data as is shown in Figure 13 28 Transfer to UiRB Register and Interrupt Timing The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock internal SCLi and an external clock supplied to the SCLi pin In cases when the CSC bit is set to 1 clock synchronization enabled if a falling edge on the SCLi pin is detected while the internal SCLi is high the internal SCLi goes low at which time the value of the UiBRG register is reloaded with and starts counting in the low level interval If the internal SCLi changes state from low to high while the SCLi pin is low counting stops and when the SCLi pin goes high counting restarts In this way transfer clock is equivalent to AND of the internal SCLi and the clock signal applied to the SCLi pin The transfer clock works between a half cycle before the falling edge of the internal SCLi Ist bit and the rising edge of the 9th bit To use this function select an internal clock for the transfer clock The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to be or freed from low level output at the falling edge of the 9th clock pulse If the SCLHI bit in the UiSMR4 register is set to 1 enabled SCLi output is turned off placed in the high impedance state when a stop condition is detected Setting the SWC2 bit in the UiSMR2 register 1 0 output makes it possible to forcibly output a low level signal from the SCLi pin even while sen
407. when a request from the peripheral functions in the microcomputer is acknowledged The peripheral function interrupt is a maskable interrupt Refer to Tables 9 2 and 9 3 Relocatable Vector Table for sources of the corresponding peripheral function interrupt Refer to the descriptions of each function for details about how the peripheral function interrupt occurs RO1UH0197EJ0120 Rev 1 20 ztENESAS Page 64 of 331 Jul 21 2011 M16C 6B Group 9 Interrupt 9 4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes Set the start address of each interrupt routine in the respective interrupt vectors When an interrupt request is accepted the CPU branches to the address set in the corresponding interrupt vector Figure 9 2 shows the Interrupt Vector MSB LSB Vector address L Low order address Middle order address 0000 peed Vector address H 0000 0000 Figure 9 2 Interrupt Vector 9 4 1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh Table 9 1 lists the Fixed Vector Table In the flash memory of microcomputer the vector addresses H of fixed vectors are used by the ID code check function For details refer to 18 2 Functions to Prevent Flash Memory from Rewriting Table 9 1 Fixed Vector Table Vector Table Addresses Address L to Address H Undefined instruction FFFDCh to FFFDFh M16C 60 M16C 20 and M16C Tiny UND instruction series software

M16C/6B Group User`s Manual: Hardware

Contents

Download Pdf Manuals

Related Search

Related Contents