jwchoi _kari
Contents
1. Fig 1 The SCU DM internal architecture 3 1 Architecture of LAYSIM leon3 LAYSIM leon3 has been developed by using the GNU compiler and the GTK library for GUI so it can be executed at Windows and Linux platform without any modification LAYSIM leon3 can be divided into seven parts broadly First the file loader module is responsible for loading a LEON3 program into memory and it analyzes and stores the symbol information and debugging information according to file format a out elf or binary format The source disassembler module displays the mixed format of source codes and disassembled code to GUI source viewer The IU Integer Unit execution module is the core of LAYSIM leon3 which executes SPARC v8 instructions The FPU execution module takes the responsibility of FPU operation All GRLIB operations are controlled and executed by GRLIB execution module Trap or interrupts are treated by the trap interrupt handling module Finally the GUI control module takes care of the watch breakpoint operation real time register update user control of GUI environment Event Handler disasm GUI GRLIB Interfaces Se Sens cials as event update control read GUI cycle time control r GUI execution control N GUI memory show ye S GRLIB Reg FPU Reg IU Registers f show maintain MCFG1 fer MCFG2 MCFG3 q wim tbr y UARTD12. GUI processing but it supports significantly better environment for s w developers Currently the instruction level verification test has been completed and the operation level test is undergoing It will be the main core of flight software simulator and operation simulator of SWT KARI References 1 Alastari Pidgeon Paul Robison Sean McCellan QERx A High Performance Emulator for Software Validation and Simulations Proceeding of DASIA 2009 Istanbul Turkey 2009 2 Aeroflex Gaisler GRLIB IP Core Users Manual Version 1 1 0 B4104 http www gaisler com 2010 3 Aeroflex Gaisler LEON3FT RTAX Data Sheet and User s Manual Version 1 1 0 9 http www gaisler com 2010 4 SPARC International Inc The SPARC Architecture Manual Version 8 http www sparc org 1992
3. Platform erc32 KARI Source Level Debugging and Cycle True KOMPSAT 3 5 Ground Operation Simulator in KARI 3 Architecture and Design of LAYSIM leon3 The LEON3 FT from Aeroflex Gaisler is a fault tolerant version of the standard LEON3 SPARC V8 processor it is designed for operation in the harsh space environment and includes functionality to detect and correct errors in all on chip memories It is a synthesizable VHDL model that can be implemented on FPGA board or AISC and it is just one of GRLIB which is a library of reusable IP cores for SoC development from Aeroflex Gaisler 2 The LEON3FT RTAX processor is a SoC design based on LEON3 FT implemented in the RTAX2000S radiation tolerant FPGA with various application specific IP cores 3 The SCU DM developed by KARI is based on LEON3FT RTAX and various ASIC FPGA cores Fig 1 shows the internal architecture of the SCU DM IEEE 754 LEON3FT _ Debug Serial JTAG FPU SPARC V8 Support Unit Debug Link GRFPU lite SpaceWire GRFIFO 8KB 4KB icache dcache AMBA AHB interface MUL amp DIV AMBA AHB AHB Controller LEON3 FT RTAX Memory AHB APB AMBA APB Controller Bridge UART Timers IRQMP GRGPIO 8 32bit memory bus SCU DM Processor Board EEPROM RAM Ethernet VME IPN 1553B RTC IMSL 1MB 2MB Ctrl Ctrl Ctrl Ctrl Ctrl Ctrl
4. 0001170 9de3bf90 0x40000000 volatile unsigned i save Ss int INTMKR vo 40001174 03200000 sethi CONE 40001178 82106240 or g1 0x240 4000ad48 00000000 lay_var2 vib ino emo IBT yat aly stp 4000ad44 00000000 lay_var3 oxo0000000 volatile unsigned int atile unsi 40001180 03200000 sethi hi Ox 0x00000064 40001184 62106208 or 0x4000A940 ANOURIERSCZ27HELO st sal fp 9 Num Type Address size Name OxFFFFFFFS lay_vari 100 bss 4000aaic 00000080 inirq T 4000118 0310002b sethi Shi 0x4000ac zr 0x40009000 40001190 9a106140 Or g1 0x140 4000aa9c 00000004 no_inirq_check bss Ox40004914 40001194 862102064 10 0x64 g1 bss 4000aaa0 00000200 _oirqtbl bss Ox4000941C 40001198 c2234000 st sgl 05 4000aca0 00000080 _irgtbl lay_var2 150 Ox00000000 gt 4000119c 0310002b sethi ss 4000ad20 00000004 __lbst_pthread_mutexattr_ 400011a0 98106148 or a0001iaa 82102096 x96 4000ad24 00000004 __Ibst_pthread_mutexattr_ 400011a8 2234000 st gi o 4000ad28 00000004 __lbst_pthread_mutexattr_ lay_var3 200 400011ac 03100025 sethi ss 4000ad2c 00000004 __Ibst_pthread_mutex_unl Oxo0000000 400011b0 90106144 or sgl Ox ss 4000ad30 00000004 __Ibst_pthread_mutex_locl 400011b4 821020c8 0x00000000 40004168 2234000 5 ss 4000ad34 00000004 _ Ibst_pthread_mutex_tryl 0x00000000 Ss 4000ad38 00000004 __lbst_pthread_mutex_des 0x00000000 Gaqusvee os 100004 Sethi ss 4000ad3c 00000004 _lbst_pthread_mutex_init 0x00000000 400011c0 90106
5. 218 or iss 4000ad40 00000004 lay_vari sy Ox40200000 ss 4000ad44 00000004 lay_var3 0x00000000 ss 4000ad48 00000004 lay_var2 Ox00000000 psr F34010R6 n 0 z 1 v 0 c 0 ef 1 pil 0 s l ps l et l ss 4000ad4c 00000004 0x00000000 j ss 4000ad50 00000004 heap_ptr oxoo000000 BS an ea 4000ad60 00000008 xtime 0x00000000 Oxo0000000 Ox00000000 Ox00000000 Fig 4 S W Development Environment on LAYSIM leon3 Figure 5 shows the case of VxWorks Tornado on Windows Tornado IDE is connected with LAYSIM leon3 through virtual network which enables FSW members to develop monitor and debug the FSW with Tornado IDE LAYSIM leon3 is also connected with the 1553B Monitor Simulator which sends receives 1553B command data to from LAYSIM leon3 Software Development Environment Tornado 2 0 VxWorks 5 4 ele Z z mf2 rix E alalelels 14 0x0000040E LAYSIM leon3 SCU DM model O1fddat 0097400 05 Ox3de virtual 1553B Fig 5 S W Development Environment with VxWorks 5 4 Tornado 2 0 on LAYSIM leon3 5 Conclusion In this paper we introduced the development of LEON3 FT emulator LAYSIM leon3 which is a GUI based and cycle true emulator and can support the full system simulator for the SCU DM And we described the software development and test on LAYSIM leon3 LAYSIM leon3 shows the slightly lower performance compared with TSIM leon3 due to overhead of
6. Development of LEON3 FT Processor Emulator for Flight Software Development and Test Jong Wook Choi Hyun Kyu Shin Jae Seung Lee and Yee Jin Cheon Satellite Flight Software Department SWT Korea Aerospace Research Institue 115 Gwahanno Yuseong Daejeon Korea jwchoi hkshin jslee yjcheon kari re kr Abstract During the development of flight software the processor emulator and satellite simulator are essential tools for software development and verification SWT KARI has developed the software based spacecraft simulator based on TSIM LEON3 processor emulator from Aeroflex Gaisler But when developing flight software using TSIM LEON3 there is much limitation for emulation of real LEON3 FT processor and it is difficult to change or modify the emulator core to integrate FSW development platform and satellite simulator To resolve these problems this paper presents the development of new GUlI based and cycle true LEON3 FT processor emulator as LAYSIM leon3 and describes the software development and debugging method on VxWorks RTEMS RTOS Keywords LEON3 LAYSIM leon3 emulator ISS Cycle True GUI based 1 Introduction The microprocessor in on board computer OBC is responsible for performing the flight software FSW which controls the satellite and accomplishes missions to be loaded and executed and it is specially designed to be operated in the space environment Currently developing satellites by KARI Korea Aerospa
7. ERC32 and LEON2 3 shown in Table 1 have been developed in ESA related companies the last two emulators for ERC32 was developed by Satellite Flight Software Department SWT in KARI LAYSIM leon3 has been developed based on LAYSIM erc32 and applied the specific features of LEON3 FT processor Both LAYSIM erc32 and LAYSIM leon3 use the interpretation method whereas QEMU laysim erc32 uses the dynamic translation method based on QEMU core Table 1 Processor Emulator Support Status for ERC32 amp LEON2 3 Emulator Type Processor Supplier Remark TSIM Interpretation ERC32 Aeroflex Cycle True Commercial LEON2 3 GR Used for most ESA projects KOMPSAT 3 5 Satellite Simulator in KARI Leon SVE Interpretation LEON2 Spacebel Full representative of LEON2 FT SimERC32 _ Interpretation ERC32 Astrium Astrium Internal SIMERC32 emulator in SIMIX SimLEON LEON2 3 CNES Used for Gaia Real Time Simulator Sim Dynamic LEON3 Astrium Spacecraft Controller On a Chip with LEON3 FT SCOC3 Translation Sim MDPA Interpretation LEON2 Astrium Multi DSP Micro Processor Architecture with LEON2FT ESOC Interpretation ERC32 ESOC Used for most ESOC ESA ground system Simulator VEGA QERx Dynamic ERC32 SciSys F Based on QEMU 0 9 1 Translation LEON2 FQTECH Used for Galileo Constellation Operation Simulator QEMU Dynamic ERC32 SWT Based on QEMU 0 11 1 laysim Translation KARI S W development in VxWorks RTEMS RTOS erc32 LAYSIM Interpretation ERC32 SWT Windows amp Linux
8. ce Research Institute use the ERC32 processor and the LEON3 FT processor will be embedded for the OBC of next generation satellites and those processors were developed by ESA European Space Agency ESTEC European Space Research and Technology Centre The processor emulator is an essential tool for developing FSW and the core of building the satellite simulator but there is a very limited selection for choosing LEON3 processor emulator Only TSIM LEON3 from Aeroflex Gaisler is available for commercial purpose so it is inevitable to purchase TSIM LEON3 continuously for development of FSW and constructing the satellite simulator But TSIM LEON3 does not support full features of the LEON3 FT model and it is difficult to change or modify the emulator core to integrate FSW development platform and satellite simulator In order to resolve these problems successfully a new LEON3 FT processor emulator LAYSIM leon3 has been developed LAYSIM leon3 is a cycle true instruction set simulator ISS for the LEON3 FT processor and it includes the embedded source level debugger Also LAYSIM leon3 can support the full system simulator for the SCU DM Spacecraft Computer Unit Development Model based on the LEON3 FT GRLIB and various ASIC FPGA cores This paper presents the architecture and design of LAYSIM leon3 and the result of FSW development and test under LAYSIM leon3 In Section 2 we introduce the emulation method and status of emulators for LEON3 T
9. fled UARTS1 so j gt j 2 UARTC1 Lee BEA UARTSCI ILR IPR IFR ICR IMR Memory ROM RAM ASI 0x01 ASI 0x02 ASI OxOC GPIOIE 31 ASI 0x10 ASI 0x11 control 4 show show IU Execution Model x GUI register show A load d FPU Execution Model GUI file loader gt uonewoyy SUISSNqaq 2497 Spo NOS a qeL JOqUUIAS GRLIB Execution Model Fig 2 LAYSIM leon3 Emulator Architecture 3 2 File Loader Module LEON3 programs which can be loaded to LAYSIM leon3 are a out file format from VxWorks 5 4 output and elf file format from VxWorks 6 5 RCC RTEMS LEON ERC32 Cross Compiler and BCC Bare C Cross Compiler System for LEON Also binary file format can be loaded to LAYSIM leon3 with address option During loading a LEON3 program the appropriate loader is executed after the analysis of file format it extracts symbol and debugging information and copies text data segments to memory If a RAM based LEON3 program is selected then stack frame pointers of the IU are automatically are set for its execution in RAM 3 3 Source Disassembler Module If the matching C source code of a LEON3 program which is l
10. handling module The GRGPIO and GRFIFO are supported in LAYSIM leon3 for external interface and DMA operation The APBUART is implemented as GUI console or can be redirected to external interface 3 GPTimers are also implemented as the real hardware operation mechanism The scaler and count of timers are decremented as the cycle time of IU FPU instruction execution and if timer is expired then corresponding interrupt is invoked it will be treated by the IU execution module with the trap interrupt handling module The SpW module can send receive data via virtual SpW channel to from external SpW test equipment which is also software based simulator All registers of GRLIB devices are mapped to AMBA APB AHB address and controlled by event function and register operations 3 7 Trap Interrupt Handling Module The LEON3 FT has 3 operation modes reset run error mode It supports three types of traps synchronous floating point and asynchronous traps Synchronous traps are caused by hardware responding to a particular instruction or by the Ticc instruction and they occur during the instruction that caused them Floating point traps caused by FP instruction occur before that instruction is completed Asynchronous trap interrupt occurs when an external event interrupts the processor such as timers UART and various controllers The software handlers for window overflow underflow trap among synchronous traps are provided by RTOS or compiler so they ca
11. hardware interlock adds one or more delay cycles Currently H W interlock mechanism is implemented in LAY SIM leon3 with the actual LEON3 FT The FPU mode is operated as the execution exception pending exception mode During execution mode if exceptions such as divide by zero overflow underflow are occurred then it transits to the pending exception mode but the IU cannot immediately aware of the error condition of FPU The IU finally figures out the FPU exception mode on executing another FP instruction then FPU mode is changed to the exception mode the FPU exception trap will be invoked by the IU deferred trap If software handles the FPU exception properly then FP queue becomes empty and FPU mode is changed to execution mode which operates FP instruction otherwise the LEON3 FT enters error mode which halts anymore operation 3 6 GRLIB Execution Module The GRLIB execution module in LAYSIM leon3 implemented various IP cores such as the memory controller APBUART GPTimer IRQMP GRGPIO GRFIFO SpaceWire SpW etc They consist of registers memory and controller where software can be accessed as real hardware In case of memory controller it sets the size of RAM ROM and waitstates If software accesses an unimplemented area the trap will arise and waitstates will consume the additional cycles of memory read write operation The IRQMP controls the 15 internal external interrupts for CPU and it will be treated by the trap interrupt
12. he detailed simulation of the LAYSIM leon3 is discussed in Section 3 Section 4 gives the software development environment under LAYSIM leon3 with VxWorks RTEMS RTOS Finally we draw the conclusion in Section 5 2 Emulation Method and Emulator Status The method of emulating the processor can be categorized into two major ways interpretation and dynamic translation The interpretation is the widely used method for cross platform program execution It fetches an instruction from target executable codes decodes it to host platform such as x86 machine and then executes it So it has a large overhead for every converting instruction and it is very hard to meet the real time performance when target system is running on high system clock But this method is relatively easy to implement and cycle true emulation of the target platform The dynamic translation such as QEMU takes a different approach Blocks of target instructions are complied to host instructions Just In Time JIT as they encountered and stored in memory When the same block is encountered again the precompiled block is retrieved from memory and executed This enables around 5 and 10 times remarkable performance than interpreted emulator However this method cannot emulate as cycle true and lead issues with target processor clock and I O timing 1 So it is difficult to verify of flight software modules which have time constrained attributes The seven processor emulators supporting
13. ing to supervisor user mode read f Instruction Fetch update Instruction Cache Update Service Interrupt Y ge pending nterrupt eo o s Fig 3 LAYSIM leon3 IU Execution Module Flow Instruction Decode read FP l LEON3 write Instruction inst Service FPU register memory Execute amp Write Execution Module DCACHE heck result 0 Y execution trap occur Service GRLIB Execution Module ai is rial Cycle Time Update GUI Environment Service Trap Check Breakpoint 3 5 FPU Execution Module Because the FPU GRFPU lite of LEON3 FT follows IEEE 754 standard LAYSIM leon3 uses the resources of x86 machine to perform FPU instruction and the results are reflected into the FPU registers If FPU exception is occurred during FPU operation the FPU exception of host x86 machine is first processed accurately and then the exception information is applied to FSR FPU of LAYSIM leon3 While the GREFPU lite can perform a single FP instruction at a time if FP instructions are performed in succession first FP instruction is stored in FP queue until the end of execution and qne FSR is set to 1 not empty The IU execution also will be blocked till the empty of FP queue which means the end of execution of FP instruction The calculation of cycle time of FPU instruction is more complicated than the IU case And if the register which is the result of previous execution of instruction is used as a source operand in current instruction
14. n be handled correctly by software But other traps whose handlers are not installed properly by software will lead the LEON3 FT to error mode Interrupts can be processed by the IU on no pending synchronous trap All trap operations are handled by the trap interrupt handling module as the real LEON3 FT trap operation 4 Software Development Test on LAYSIM leon3 The Flight Software based on VxWorks 5 4 6 5 or RTEMS can be loaded and executed on LAYSIM leon3 without any modification as the real hardware environment For s w development on the SCU DM LAYSIM leon3 supports the full system simulator for the SCU DM which has the Ethernet LAN91C VME IPN 1553B RTC IMSL controllers All devices are integrated to memory mapped I O area in LAYSIM leon3 and controlled by event function and register operations with the same operation mechanism of GRLIB devices Figure 4 shows the software development environment using BCC and the embedded debugger of LAYSIM leon3 can debug as C source code level and trace variables memory GUI based LEON3 FT Processor Emulator laysim leon3 v0 02 by layright SCU DM model File Edit View Debug Tools Window Help IU ae iat ms 4 Sa B lire Ss Cycles 00000000000000002438 IU Reg Feu Reg crus x oid int14 handler int irq oid intil_handler int irq oid intiO0_handler int irq 0x4000119C 0x40001140 OxF34010E6 int main void unsigned int lay vari lay_var2 lay_var3 0x00000002 4
15. not access the memory as indicated by PC nPC then the instruction access error trap will be occurred After it checks current pending interrupts and conditions trap PSR is enabled and interrupt level is bigger than pil PSR it updates the trap base register TBR and services a highest pending interrupt On instruction decode stage it analyzes SPARC v8 instruction to be executed and it calls the corresponding emulation function The execute memory step performs the called function to be executed and it reads required register memory it stores the result into register memory back If the decoded instruction is a floating point instruction then it will be treated by the FPU execution module During the execution of each instruction this module checks the privilege align trap condition of instruction If exception case is occurred then it sets the trap environment and services trap operation where it processes the trap operation according to LEON3 trap handling rule If the occurred trap cannot be recovered then the LEON3 mode is transited to error mode and it stops execution On non critical exception case it calculates the cycle time of instruction and it updates system clock and timer registers through the GRLIB execution module which also services the timed event for various GRLIB operation and user FPGA ASICs Lastly the IU execution module updates GUI environments for timers UARTs etc Y LEON3 Error Mode Set ASI accord
16. oaded through the file loader module is available then the source disassembler module displays the mixed format to GUI source viewer otherwise it displays assembler code only As for disassemble the rule of Suggested Assembly Language Syntax 4 from SPARC is adopted for the convenience of software engineers The LEON3 FT SPARC v8 core supports 5 type s instructions such as load store arithmetic logical shift control transfer read write control register and FP CP instructions To trace the code execution LAYSIM leon3 has the function of code coverage In GUI source viewer the executed code line is highlighted with blue color untouched code is colored in black and current executing code line is marked with red color After execution it can report the code coverage of the LEON3 program with source code 3 4 IU Execution Module The IU execution module which executes SPARC v8 instructions operates as a single thread and it can be controlled by run stop step etc from GUI control toolbar or console It performs 7 stage instruction pipeline of the LEON3 FT FE Instruction Fetch DE Decode RA Register Access EX Execute ME Memory RA Register Access XC Exception WR Write All operations of the IU execution module are shown in Figure 3 During the fetch stage it gets two instructions according to PC nPC from memory or icache and it updates icache according to icache update rule If it can
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