SECTION 4 BURST BUFFER
Contents
1. MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 9 4 6 1 Region Base Address Registers MI RBA 0 3 Region Base Address Register SPR 784 787 a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RA RESET Unaffected by Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 en RA Reserved RESET Unaffected by Reset Table 4 5 MI RBA 0 3 Bit Settings 0 19 RA Region address This field defines the base address most significant 20 bits for the region 20 31 Reserved 4 6 2 Region Attribute Registers MI RA 0 3 Description MI RA 0 3 Region Attribute Registers SPR 816 819 si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RS RESET Unaffected by Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 re RS PP RESERVED G RESERVED RESET Unaffected by Reset MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 10 Table 4 6 MI RA 0 3 Bit Settings Region size The region size is a power of two determined as follows 0000 0000 0000 0000 0000 4 Kbytes 0000 0000 0000 0000 0001 8 Kbytes 0000 0000 0000 0000 0011 16 Kbytes 0000 0000 0000 0000 0111 32 Kbytes 0000 0000 0000 0000 1111 64 Kbytes 0000 0000 0000 0001 1111 128 Kbytes 0000 0000 0000 0011 1111 256 Kbytes 0000 0000 0000 0111 1111 512 Kbytes 0000 0000 0000 1111 1111 1 Mbyte 0000 0000 0001 1111 1111 2 Mbytes 0000 0002. branch fo branch fo branch to Main code can start here Figure 4 2 Exception Table Entries Mapping MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 8 4 6 Burst Buffer Programming Model The BBC and IMPU module configuration registers are MPC555 special purpose reg a isters SPRs They are programmed with the MPC555 mtspr mfspr instructions All the registers can be accessed in supervisor mode only The processor generates an exception internally if an attempt is made to access the registers from user mode The following 32 bit registers contain the starting address and the size of the region There is one register for each region Table 4 2 Region Base Address Registers RBA 0 1 MI_RBAO 784 0x2180 MI RBA1 785 0x2380 MI RBA2 786 0x2580 MI RBA3 787 0x2780 The following registers hold the attributes of the corresponding regions and of the default region Each of the four MI RAx registers contains access permission attributes The MI GRA global region attribute register contains two additional bits to enable each of the MI_RBAx registers Table 4 3 Region Attributes Registers MI_RAO 816 0x2190 MI_RA1 817 0x2390 MI_RA2 818 0x2590 MI RA3 818 0x2790 MI GRA 528 0x2100 The BBC holds only one register the BBC module configuration register BBCMCR Table 4 4 BBC Module Configuration Register BBCMCR 560 0x2110
3. IMPU notifies the RCPU core for an interrupt is by feeding error informa tion into four bits 1 3 4 and 10 in the SRR1 regsiter in the core Only one bit is set at a time The exception vector address that the core issues for this event is OxnnnO 1300 The encoding of the status bits is as follows e SRR1 0 e SRR3 Gaurded storage e SRR4 Protected storage e SRR10 0 4 5 Exception Table Relocation The BBC hasthe ability to relocate the exception table Exception table relocation is a feature to save memory space in the exception table This is done by mapping excep tions to be separated by 8 bytes instead of 256 bytes see Table 4 1 The relocation feature only maps the exception table into the internal memory space of the MPC555 which reguries MSR IP 1 This feature is important in multi MPC555 systems where more than one MCU can have internal exception tables with the same exception addresses issued by the RCPU The relocation feature also saves the wasted space between exception table entries when each exception entry contains only a branch instruction to the exception routine which is located elsewhere If exception relocation is enabled ETRE bit is set in the BBCMCR all exception rou tines except the reset exception routine can be controlled to either remain in the lower addresses of the memory base address exception offset or to be relocated to memory base address 32 Kbytes The reset exception routi
4. address of the access to its region programming The BBC determines whether the access can be immediately transferred to the U bus If not it requests the U bus for the next clock Each new BBC U bus access is accompanying by the burst request attribute If burst able access is enabled the BBC performs a burst access otherwise it performs a single access If the IMPU detects an access violation it does the following e Cancels the request that was forwarded to the BBC e Informs the RCPU core that the requested address generated an exception If the required address contains show cycle or program trace attributes the BBC deliv ers the access to the U bus even if the request is cancelled due to the exception it caused MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 3 The BBC forwards show cycle program trace and debug port access attributes accompanying the CPU access along with the U bus access 4 4 2 Slave Operation The burst buffer module is operating as a U bus slave module when the instruction memory protection unit IMPU registers are accessed by the user in order to be pro grammed This programming is done using the mtspr mfspr instructions 4 4 3 Reset Operation On reset the BBC goes to an idle state and all pending U bus accesses are ignored The IMPU goes to a disabled state in which all memory space is accessible to both user and supervisor 4 4 4 Debug Mode Operation When the
5. fetch address issued by the processor is the one that is transferred to the U bus 4 1 Burst Buffer Block Diagram Figure 4 1 is a block diagram of the burst buffer MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 1 Protection Abort to U bus RCPU InstructionAddress Bus In Page Access Figure 4 1 Burst Buffer Block Diagram 4 2 Burst Buffer Features The BBC offers the following features e Supports pipelined access to internal memory and burstable access to the exter nal memory e Supports the de coupled interface with the RCPU instruction unit e Serves as parked master on the U bus resulting in zero clocks delay for RCPU fetch access to cross to the U bus e Full utilization of the U bus pipeline for fetch accesses e Tightly interfaced with L2U Interface module taking advantage of full U bus band width and back to back accesses e Supports program trace and show cycle attributes e Supports special attribute for debug port fetch accesses e Is programmed using the MPC555 mtspr mfspr instructions to from implemen tation specific special purpose registers Designed for minimum power consumption The IMPU has the following features e Four regions in which the base address and size can be programmed e Region sizes of 4 Kbytes up to 4 Gbytes in powers of two can be programmed A region must start on the specified region size boundary e Overlap between region
6. of IMPU 0 ENRO 0 Region 0 is off 1 Region 0 is on Enable region 1 of IMPU 1 ENR1 0 Region 1 is off 1 Region 1 is on Enable region 2 of IMPU 2 ENR2 0 Region 2 is off 1 Region 2 is on Enable region 3 of IMPU 3 ENR3 0 Region 3 is off 1 Region 3 is on 4 19 Reserved Protection bits 00 No supervisor access no user access 20 21 PP 01 Supervisor fetch access no user access 10 Supervisor fetch access user fetch access 11 Supervisor fetch access user fetch access 22 24 Reserved Guarded attribute for region 25 G 0 Fetch is allowed from guarded region 1 Fetch is prohibited from guarded region An attempted fetch will generate an exception 26 31 Reserved 4 6 4 BBC Module Configuration Register BBCMCR BBCMCR BBC Module Configuration Register SPR 560 ia 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pp Reserved BE ETRE OERC Reserved RESET 0 0 0 ID 19F 0 0 0 0 0 0 0 0 0 0 0 0 Reset value is taken from the indicated bit of the reset configuration word MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 12 Table 4 8 BBCMCR Bit Settings 16 17 Reserved Burst enable 18 BE 0 BBC does not reguest burst accesses 1 BBC reguests burst accesses Exception table relocation en
7. 0 0011 1111 1111 4 Mbytes 0000 0000 0111 1111 1111 8 Mbytes 0000 0000 1111 1111 1111 16 Mbytes 0000 0001 1111 1111 1111 32 Mbytes 0000 0011 1111 1111 1111 64 Mbytes 0000 0111 1111 1111 1111 128 Mbytes 0000 1111 1111 1111 1111 256 Mbytes 0001 1111 1111 1111 1111 512 Mbytes 0011 1111 1111 1111 1111 1 Gbyte 0111 1111 1111 1111 1111 2 Gbytes 1111 1111 1111 1111 1111 4 Gbytes Protection bits 00 No supervisor access no user access 20 21 PP 01 Supervisor fetch access no user access 10 Supervisor fetch access user fetch access 11 Supervisor fetch access user fetch access 22 24 Reserved Guarded attribute for region 25 G 0 Fetch is allowed from guarded region 1 Fetch is prohibited from guarded region An attempted fetch will generate an exception 26 31 Reserved 4 6 3 Global Region Attribute Register Description MI_GRA MI_GRA Global Region Attribute Register SPR 528 a 2 3 4 5 6 7 8 9 10 11012 13 14 15 ENRO ENR1 ENR2 ENR3 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 34 RESERVED PP RESERVED G RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 11 Table 4 7 MI GRA Bit Settings Enable region 0
8. CPU is in debug mode fetch accesses are attached with a special attribute If this attribute is asserted the BBC must initiate not burstable accesses to the debug port 4 4 5 Standby Mode Operation In this low power modes the CPU stops issuing further accesses The BBC clocks are turned off and the BBC enters a power save state When the low power mode is exited clocks are activated and a new access from the CPU will activate the BBC 4 4 6 Burst Operation The BBC can run burst accesses on the U bus Such burst cycles if forwarded to external memory are then exported to the EBI as burst cycles if bursts are enabled by the USIU The BE bit defined in 4 6 4 BBC Module Configuration Register BBCMCR deter mines whether the BBC operates burst cycles or not Burst requests are enabled only when the BE bit is set NOTE The negated state of the BE bit is useful mainly when the RCPU core runs in serialized mode 4 4 7 Error Detection If the IMPU detects access violation the following actions must be taken 1 Cancel the request that was forwarded to the burst buffer controller 2 Inform the RCPU core that the requested address generated an exception If the required address contains show cycle or program trace attributes than the BBC delivers the access onto the U bus even if the request is cancelled due to the excep tion it caused MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 4 The way the
9. SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruc tion memory protection unit IMPU The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U bus It utilizes the full U bus pipeline and a special page access attribute in order to take full advantage of the U bus bandwidth It can handle both burstable and non burstable external memories as well as non burstable internal memories flash EEPROM SRAM The IMPU allows the memory to be divided into four regions with different attributes as well as a default global region for memory space that is not included in either of the two regions Each of the two regions can be of size 4 Kbytes to 4 Gbytes Overlap between regions is allowed The IMPU includes registers that contain the following information region base address region size and the region s access permissions For each access from the processor to the memory the IMPU finds which region matches the address If more than one region matches the region with the lowest index is chosen If no region is matched the global region is chosen The IMPU compares the attributes of the access from the processor to the attributes of the appropriate region If the access is allowed the proper signals are sent to the BBC If the access is not permitted an interrupt is sent to the processor The IMPU does not support address translation The effective
10. able 19 ETRE 0 Exception table relocation is off the BBC does not map exception addresses 1 Exception table relocation is on the BBC maps exception addresses to a branch instruction table Refer to 4 5 Exception Table Relocation Other exceptions relocation control 20 OERC 0 All exceptions except reset are mapped to the internal memory base address 1 All exceptions except reset are mapped to the internal memory base address 32 Kbytes 21 31 Reserved MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 13 MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 14
11. age Error 0x0_1300 0x0098 0x8098 Implementation Dependant Data Breakpoint 0x0_1C00 0x00E0 0x80E0 MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 6 Table 4 1 Exception Addresses Mapping by BBC implementation Dependant 0x0 1D00 Ox00E8 Ox80E8 Instruction Breakpoint Implementation Dependant Maskable 0x0_1E00 0x00F0 0x80F0 External Breakpoint Non Maskable External Breakpoint 0x0_1F00 0x00F8 0x80F8 NOTES 1 Assuming 12 MSBs OxFFFO which is set by MSR IP 1 2 OERC bit See 4 6 4 BBC Module Configuration Register BBCMCR 3 The reset exception is NOT affected by OERC MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 7 Exception Pointer by RCPU Internal Memory Structure MI branch fo branch fo branch to 100 branch fo branch fo branch to 200 branch fo branch to branch fo 300 branch to branch to branch 10 400 branch to Branch 10 Exception Table branch fo branch to 500 branch fo branch fo branch to 600 branch fo branch fo branch to 700 branch To branch 10 branch fo branch fo branch 10 1F00 branch to
12. ne location is fixed in memory base address the reset exception offset and can not be relocated See 4 6 4 BBC Module Configuration Register BBCMCR for programming details 4 5 1 Exception Table Relocation Operation When an exception is requested the CPU initiates a fetch cycle that branches to the exception routine associated with the exception that caused the fetch The exception addresses are fixed within the RCPU architecture and are 0x100 bytes apart from each other starting at address 0x0000_0100 or 0xFFFO 0100 depending on the value of the MSRJ IP bit If the relocation feature is disabled the BBC transfers the exception fetch address to the internal bus of the MPC555 with no interference In order to activate exception table relocation the following steps are required 1 Set the MSRIIP bit To set this bit out of reset set the appropriate bit in the re set configuration word 2 Set the ETRE bit in BBCMCR register See 4 6 4 BBC Module Configuration Register BBCMCR for programming details MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 5 exception routine into the address located at the lowest portion ofthe internal memory Atthat location the user mustinsert a series table of consecutive branch instructions that point to the appropriate exception routines Thus the CPU branches twice to reach the appropriate exception routine If the relocation feature is enabled the BBC translate
13. s is allowed e Each of the four regions supports the following attributes Access protection user supervisor fetch or no access Guarded attribute causes an interrupt in case of fetch try MPC555 BURST BUFFER MOTOROLA USER S MANUAL Revised 15 September 1999 4 2 On off option e Global region entry declares the default access protection and guarded attributes f for all memory areas not covered by the four regions e Interrupt generated upon access violation or fetch from guarded region e MPC555 MSRIIR bit controls MPU protection Programming is done using MPC555 mtspr mfspr instructions to from imple mentation specific special purpose registers e Designed for minimum power consumption 4 3 Little Endian Support The BBC supports little endian operation only when bursts are disabled see 4 6 4 BBC Module Configuration Register BBCMCR for more details The BBC does not support little endian in the following cases 1 For internal code data memories 4 4 Modes Of Operation The burst buffer module can operate in the following modes e Normal e Slave e Reset e Debug e Standby e Burst The modes of operation are described in the following paragraphs 4 4 1 Normal Operation During normal operation the burst buffer module transfers fetch accesses from the CPU to the U bus When a new access is issued by the CPU it is transferred in parallel to both the IMPU and the BBC The IMPU compares the
14. s the starting address of the E NOTE The 8 Kbytes allocated for the exception table can be almost fully uti lized This is possible if the MPC555 s address space is not mapped to the exception address space that is if addresses OxFFFO_0000 to OxFFFO_1FFF are not part of the MPC555 address apace In this case these 8 Kbytes can be fully utilized by the compiler except for the lower 64 words 256 bytes which are reserved for the exception pointers NOTE That if the CPU issues any address that falls between two successive exception entries e g OXFFFO_0104 then an exception is gener ated to the CPU if exception relocation is enabled See 4 6 4 BBC Module Configuration Register BBCMCR Table 4 1 Exception Addresses Mapping by BBC Reserved 0x0_0000 0x0000 0x8000 System Reset 0x0_0100 0x0008 0x00082 Machine Check 0x0_0200 0x0010 0x8010 Data Storage 0x0_0300 0x0018 0x8018 Instruction Storage 0x0_0400 0x0020 0x8020 External Interrupt 0x0_0500 0x0028 0x8028 Alignment 0x0_0600 0x0030 0x8030 Program 0x0_0700 0x0038 0x8038 Floating Point unavailable 0x0_0800 0x0040 0x8040 Decrementer 0x0 0900 0x0048 0x8048 Reserved 0x0 0A00 0x0050 0x8050 Reserved 0x0 0B00 0x0058 0x8058 System Call 0x0 0C00 0x0060 0x8060 Trace 0x0 0D00 0x0068 0x8068 Floating Point Assist 0x0_0E00 0x0070 0x8070 gies a 0x0 1000 0x0080 0x8080 Implementation Dependant Stor
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