DUTYS v1.0 USER`S MANUAL VLSI DESIGN AND TESTING
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1. information society technologies DUTYS v1 0 USER S MANUAL VLSI DESIGN AND TESTING CENTER DEPT OF ELECTRICAL AND COMPUTER ENG DEMOCRITUS UNIVERSITY OF THRACE Created by Kostas Siozios George Koutroumpezis Konstantinos Tatas and Dimitrios Soudris Status Version Shareware 1 0 Date 07 11 2006 Developed during AMDREL project IST 2001 34379 DUTYS Democritus University of Thrace Architecture file generator synthesizer creates the architecture file of the FPGA that is required by T VPack and VPR The architecture file contains a description of various parameters of the FPGA architecture including size array of CLBs number of pins and their positions number of BLEs per CLB plus interconnection layout details such as relative channel widths switch box type etc It has a GUI that helps the designer select the FPGA architecture features and then automatically creates the architecture file in the required format 1 1 Function of DUTYS DUTYS creates the FPGA architecture file in the required format Each line in an architecture file consists of a keyword followed by one or more parameters In the description below strings between curly braces denote all the possible choices for an option All of the following keywords must be specified in the architecture file Description of I O pads io_rat lt int gt Sets the number of pads inputs or outputs that fit into the space occupied by one CLB This is the2. pieces of wiring will use this type of switch e opin_switch The index of the switch type used by CLB and pad output pins to drive this type of segment e Frac_cb Describes the internal population of the segment for connection boxes connections to logic blocks This number gives the fraction from 0 to 1 of logic blocks passed by this segment to which it will have a connection box A switch exists from a segment to a logic block pin only if 1 the segment wants a connection box to that logic block and 2 the logic block connection box pattern for that pin wants a connection to that segment e Frac_sb Describes the internal population of the segment for switch boxes connections to other routing tracks This number gives the fraction from O to 1 of the length 1 switch blocks which could exist along the segment that do in fact exist So a segment of length 9 that had a Frac_sb value of 0 5 would have 5 switch boxes along its length Exactly which tracks a segment connects to at each switch box is determined by the switch_box_type parameter e Rmetal Resistance per unit length in terms of logic blocks of this wiring track in Ohms For example a segment of length 5 with Rmetal 10 Ohms logic block would have an end to end resistance of 50 Ohms e Cmetal Capacitance per unit length in terms of logic blocks of this wiring track in Farads For example a segment of length 5 with Cmetal 2e 14 F logic block would have a total m
3. and a flip flop If the net file as created with T VPack the pin ordering we need to match the net file is inputs for use by BLEs outputs clock it Uniform channel architecture cluster based Logic block COntaliang 2 BLEs io_rat 2 2 Pads per row or column chan_width_io 1 Same as core channels chan_width_x uniform 1 All same width ebhan wLata y untrtorm 1 Logic block with 2 BLEs 5 Inputs for use by BLEs first then two outputs then the clock pL Class 0 DOLL On ini Class O Tert inpin class 0 Lrgint Login class 0 TOP ipin Class 0 DOLEOM outpin class 1 top bottom Output 1 outon Class 1 ere rignt FOVWEPUE Z inpin class 2 global top Clock gt accessible only by global nets in this case t Class 0 is LUT inputs class 1 is th OVtputy Glass 2 15 the CLOCK in this case subblocks per clib 2 Two BLES 11 each logic block subblock_lut_size 4 The LUT in a BLE has 4 inputs Notice that all the inputs are of the same class indicating they are all logically equivalent and all the outputs are of the same class indicating they are also logically equivalent This is true of all cluster based logic blocks as the local routing within the block provides full connectivity However for most logic blocks all the inputs and all the outputs are not logically equivalent For example consider the logic block in Fig 2 which consists of a 3 input and gate and a 2 input or gate In this case
4. is for an FPGA with all channels of the same width and a CLB compatible with that produced by T VPack with the no_clustering option This CLB contains a 4 input LUT and a flip flop the input pins are listed first followed by the CLB output pin followed by the clock pin Notice that the four inputs all have the same pin class indicating that they are logically equivalent and the router may connect nets to any one of them Notice also that pins can be physically accessible from several sides Uniform channel architecture 4 input LUT and a FF one BLE per Le io Fat 2 2 Pads per row or column chan_width_io 1 Same as core channels chan_width_x uniform 1 All same width Chan wrath y UNiEOEm L S anputs BUT LUT Inputs Tirst then OuUEput then clock inpin class 0 bottom top Physical pins at both top and bottom of Clb non Lasse 0 Lert Egan Tiwari Classe O DOCCOM COP Lapur class U Lerm Ldne outpin class 1 top Bottom inpin class 2 top Clock pin Class O is LUT inputs class 1 is the output class 2 is the GLOCK in this case subblocks_per_clb 1 One BLE in each logic block subblock_lut_size 4 The LUT in a BLE has 4 inputs As a second example of an architecture file consider a logic block consisting of a cluster based logic lock where each logic block has 5 inputs for use by its BLEs 2 outputs and one clock input Each logic lock contains two separate BLEs and each BLE consists of a 4 input LUT
5. must be subblocks_per_clb of these 1_subblock lines The first line specifies the delays of subblock zero which is the first subblock listed in each CLB in the circuit netlist file The second T_subblock line specifies the delay of subblock one the second subblock in each CLB in the circuit netlist file and so on If the subblocks within a CLB have different delays then you must list them in the same order in the architecture and netlist files The above delays are illustrated in Fig 6 Logic Block Routing Channel he Logic Block Connection CLB Inputs Outputs T_sblk_opin_to_clb_opin T_clb_ipin_to_sblk_ipin Fig 6 Local routing delays within a logic block CLB e T comb The delay from any subblock input to the subblock output when this subblock is used in combinational mode A subblock is used in combinational mode when the netlist leaves its clock pin OPEN e T_seq_in The delay from any subblock input pin to the FF storage element when this subblock is used in sequential mode A subblock is used in sequential mode when the netlist hooks its clock pin to some signal If this subblock was a simple flip flop for example then T_seq_in is the setup time If this subblock corresponds to say a LUT feeding into a flip flop then T_seq_in should be set to the LUT delay plus the setup time e T_seg_out The delay from the subblock storage element FF to the subblock output pin when this block is used in
6. the set in1 in2 in3 is logically equivalent and could all be made class 0 Similarly the set in4 in5 is logically equivalent and could be made class 1 Outi and out2 are obviously not logically equivalent so each must be different class say class 2 and class 3 inpin class 0 top inl inpin class 0 left in2 inpin class 0 right in3 inpin class 1 bottom in4 inpin class 1 right in5 outpin class 2 left outl outpin class 3 Op FOuUtZ2 lf we want to perform timing analysis on the logic block of Fig 7 we must describe the timing relationship between the inputs and outputs Clearly outi depends only on ini in2 and in3 while out2 depends only on in4 and ind Therefore we could model this logic block as consisting of two BLEs with each BLE having 3 inputs subblocks_per_clb 2 subblock_lut_size 3 One line of a net file of a circuit made out of such logic blocks might therefore be MO Loa T pintists Dni az nS INA Ino Our Gutz subblock and gate 0 1 2 5 open outl d pends on inl 12 and 1135 and is not registered subblock or_gate 3 4 open 6 open out2 depends on in4 and ind and is not registered 1 3 Detailed Routing Architecture Description The following information is only required to be in the architecture description file if combined global detailed routing is to be performed Note that currently combined global detailed routing is possible only when all channels have been specified
7. tracks in a channel to which each pin connects fractional Fc_input lt float gt Sets the number of tracks to which each logic block input pin connects in each channel bordering the pin The F value used is always the minimum of the specified F and the channel width W so you can set F to be huge if you want F to always be W Fc_ output lt float gt Sets the number of tracks to which each logic block output pin connects in each channel bordering the pin Fc_pad lt float gt Sets the number of tracks to which each I O pad connects in the channel bordering the pad segment frequency lt float gt length lt int longline gt wire switch lt int gt opin_switch lt int gt Frac_cb lt float gt Frac_sb lt float gt Rmetal lt float gt Cmetal lt float gt Describes a type of segment You can specify as many types of segments as you like just use one segment line for each The meaning of each value is e frequency The fraction from O to 1 of routing tracks composed of this type of segment The sum of the frequency values for all the segment lines must be 1 i e 100 of the tracks have been described e length Either the number of logic blocks spanned by each segment or the keyword longline Longline means segments of this type span the entire FPGA array e wire_switch The index of the switch type used by other wiring segments to drive this type of segment That is switches going to this segment from other
8. ce of minimum width nmos transistor This data is used only by the area model built into VPR R_minW_pmos lt float gt The resistance of minimum width pmos transistor This data is used only by the area model built into VPR The lines below give an example of a detailed routing description from a arch file RAMAL fA KA SZA KA RATE SA CY LY WS CY LA UNY CY EN WS RALES NA ALL KA eo KD _ x lt Ly LES 2S 2 TISTI 2S K 6 K AL AA SAA AL SOS So ARA SA 2S Cy ES LS ES 2 XL VYTY 2S K lt Switch Box lt Connection Box Fig 4 Example of a segmented routing channel with four tracks per channel switch_block_type planar Uses the fewest switches on a segmented architecture Fc_type fractional Fc values below are in terms of fraction of W Fc_ output 1 clb output pins connect to all W tracks in adjacent channels if each of those tracks wants a connection box there Fc_input 0 5 clb input pins connect to half 0 5 W of adjacent tracks if each of those tracks wants a connection box there Fc_pad 0 7 1 0 pads connect to 70 0 7 W of adjacent tracks if each of those tracks wants a connection box there 50 of segments are length 2 50 are length 4 Length two segments are driven by type 1 switches when the connection is coming from another wire and are driven by type 0 switches when the connection comes from a clb output pin The length four segments are always driven by type O swi
9. etal capacitance of 10e 13F For example let s say an architecture file describes two types of segments segment frequency 0 5 length 2 wire_switch O opin_switch O Frac_cb 1 1 Frac_sb 0 666 Rmetal 5 Cmetal 5e 15 segment frequency 0 5 length 4 wire_switch O opin_switch O Frac_cb 0 51 Frac_sb 1 Rmetal 3 Cmetal 2e 15 If the FPGA you wish to route has a channel width of 4 one channel will look as shown in Fig 4 Notice that 2 tracks 50 of the tracks are segments of length 2 and 2 tracks are segments of length four Also notice that the number of switch boxes and connection boxes along each segment has been set in accordance with the Frac_sb and Frac_cb values for each segment type switch lt int gt buffered yes no R lt float gt Cin lt float gt Cout lt float gt Tdel lt float gt Describes a a type of switch This statement defines what a certain type of switch is segment statements refer to a switch types by their number the number right after the switch keyword The various values are e buffered yes if this switch is a tri state buffer no if this switch is a pass transistor e R resistance of the switch e Cin Input capacitance of the switch e Cout Output capacitance of the switch e Tdel Intrinsic delay through the switch If this switch was driven by a zero resistance source and drove a zero capacitance load its delay would be 7 R C R_minW_nmos lt float gt The resistan
10. n e delta A function used to specify a channel width distribution in which all the channels have the same width except one The syntax is chan_width_x delta peak xpeak dc e peak The extra width of the single wide channel e xpeak A parameter between O and 1 and specifies the location within the FPGA of the extra wide channel it is the fractional distance across the FPGA at which this extra wide channel lies 1 2 e dc specifies the width of all the other channels For example the statement chan_width_x delta 3 0 5 1 specifies that the horizontal channel in the middle of the FPGA is four times as wide as the other channels chan_width_y gaussian uniform pulse delta peak lt width gt lt xpeak gt lt dc gt Sets the distribution of tracks for the y directed channels Xpeak is pulse midpoint Relative 2 AIR AI S eR ge ot fe ale oe Width peak Uniform 0 5 Fig 1 Specification of relative channel widths Logic Block Description inpin class lt int gt global top bottom left right top bottom left right Declares an input pin determines the class to which this pin belongs and sets the side s of CLBs on which the physical output pin connection s is are All pins with the same class number are logically equivalent such as all the inputs of a LUT Class numbers must start at zero and be consecutive The global keyword is optional if specified it comes after the class number Global input pi
11. ns can connect only to signals marked as global in the netlist typically clocks Global input pins are not connected into the normal routing it is assumed they connect to a special dedicate resource used for special nets like clocks outpin class lt int gt top bottom left right top bottom left right All parameters have the same meanings as their counterparts in the inpin statement NOTE The order in which your inpin and outpin statements appear must be the same as the order in which your netlist net file lists the connections to the CLBs For example if the first pin on each CLB in the netlist file is the clock pin your first pin statement in the architecture file must be an inpin statement defining the clock pin Pads are always assumed to have only one pin either an input or an output and this pin is accessible from the one channel bordering that pad Hence no inpin or outpin statements are given for pads subblocks per_clb lt int gt Specifies the maximum number of subblocks or BLEs in each logic block This information is used only for timing analysis subblock lut_size lt int gt The number of LUT inputs to each of the subblock BLEs i e K Again this information is only needed for timing analysis Even if your logic block is not constructed from BLEs it is possible to describe the timing relations between inputs and outputs in terms of BLEs as one of the examples below illustrates The listing below
12. number of pads in each row or column of the FPGA Description of Relative Channel Widths in the FPGA The next three keywords are used to describe the relative widths of the various channels in the FPGA Fig 1 If global routing is to be performed channels in different directions and in different parts of the FPGA can be set to different relative widths f detailed routing is to be performed however all the channels in the FPGA must have the same width chan_width_io lt float gt Width of the channels between the pads and core relative to the widest core channel chan_width_x gaussian uniform pulse delta lt peak gt lt width gt lt xpeak gt lt dc gt The italicized quantities are needed only for pulse gaussian and delta which does not need width Most values are from O to 1 Sets the distribution of tracks for the x directed channels the channels that run horizontally e uniform if specified you simply specify one argument peak This value by convention between O and 1 sets the width of the x directed core channels relative to the y directed channels and the channels between the pads and core Fig 1 should make the specification of uniform dashed line and pulse solid line channel widths more clear e gaussian This keyword takes the same four parameters as the pulse keyword and they are all interpreted in exactly the same manner except that in the gaussian case width is the standard deviation of the functio
13. sequential mode A subblock is used in sequential mode when the netlist hooks its clock pin to some signal If this subblock had a flip flop hooked to its output pin for example then T_seq_out would be the clock to Q delay of the flip flop 2 Running DUTYS As with all tools in the AMDREL tool flow DUTYS can be executed both from the command line and using the GUI 2 1 Running DUTYS from the command line DUTYS can be run from the command line by typing dutys at the command line The tool then proceeds by asking the user to supply the name of the desired architecture file After the name of the new architecture file is typed the tool proceeds by asking the user to input the parameters mentioned in the previous section one by one 2 2 DUTYS GUI The DUTYS GUI part from the MEANDER design framework can be seen in the Fig 7 The GUI has a number of fields that need to be filled and each one corresponds to the questions asked in the command line execution Next to each field a short description of the corresponding architecture file parameter is included The GUI is available from the URL http vlsi ee duth gr amarel E AMDREL Fine Grain Design Tools 7 3 1 Wels Browser 0 0 G 2 Y e Oa amp ag 3 Bark Enri Hop alng O Sew Fariates Hida Hisbory Mal Print Eril Diri rica Hamr Licda aa CApocuments and Serios lksopiDeitopL 11 htm Ele adti QUES An T py aeussien z an B BO BB spockyco dathgr P
14. tches segment frequency 0 5 length 2 wire_switch 1 opin_switch O Frac_cb 1 Frac_sb 0 666 Rmetal 5 Cmetal 5e 15 segment frequency 0 5 length 4 Frac_cb 0 5 Frac_sb 1 Rmetal 31 Cmetal 2e 15 In this case type 1 switches are pass transistors while type 0 switches are tri state buffers switch 1 buffered no R 100 Cin 2e 15 Cout 2e 15 Tdel 0 Pass transistor switch O buffered yes R 50 Cin 5e 15 Cout 4e 15 Tdel 1e 11 Tri state buffer 1 4 R_minW_nmos 100 Used by area model Min width transistor resistances R_minW_pmos 200 Timing Analysis Parameters The following parameters are required if timing analysis is to be performed on the placed and routed circuit or the timing driven router is to be used C_ipin_cblock lt float gt Input capacitance of the buffer isolating a routing track from the connection boxes multiplexers that select the signal to be connected to a logic block input pin Fig 5 One of these buffers is inserted in the FPGA for each track at each location at which it connects to a connection box For example a routing segment that spans three logic blocks and connects to logic blocks at two of these three possible locations would have two isolation buffers attached to it If a routing track connects to the logic blocks both above and below it at some point only one isolation buffer is inserted at that point If your connection from routing track to connection block does not include a b
15. to have the same width switch_block_type subset wilton universal All the switch blocks have F 3 That is whenever horizontal and vertical channels intersect each wire segment can connect to three other wire segments The exact topology of which wire segment connects to which can be one of three choices e subset The switch box used in the AMDREL fine grain architecture a wire segment in track O can only connect to other wire segments in track 0 and so on Fig 8a e wilton The switch box illustrated in Fig 8b e universal The switch box illustrated in Fig 8c To see the topology of a switch box simply hit the Toggle RR button when a completed routing is on screen in VPR In general the wilton switch box is the best of these three topologies and leads to the most routable FPGAs in in2 out ing in4 out2 ind Fig 2 Example logic block where many pins are not logically equivalent de 4 Xt DK y ANY N ul L MTV oy Ay f N eee y X IMA VNV al il UU Y y A pi A i An ae a e ae P lt fox ARERR AX AXX PRIS RT ACR KK LW RRKT TRE T mm RAROS TOS DR L KNABINA ANS Scr a e Fig 3 Switch box types Fc_type absolute fractional Indicates whether the three F values see below should be interpreted as the number of tracks to which each pin connects absolute or the fraction of
16. uTTY E inde of domi v EJ AMDREL Fine Grain Fig 7 DUTYS GUI
17. uffer set this parameter to the capacitive loading a track would see at each point where it connects to a logic block or blocks T_ipin_cblock lt float gt Delay to go from a routing track through the isolation buffer if your architecture contains these and a connection block typically a multiplexer to a logic block input pin T_ipad lt float gt Delay through an input pad T_opad lt float gt Delay through an output pad T_clb_ipin_to_sblk_ipin lt float gt Delay from an input pin of a CLB logic block to an input pin of a subblock within that CLB For architectures without local routing i e CLB input pins connect directly to some logic element like a LUT or multiplexer this delay is essentially zero T_sblk_opin_to_sblk_ipin lt float gt Delay from the output of a subblock to the input of another subblock within the same CLB For architectures without local routing e g the output of one subblock is hardwired to the input of another this delay is essentially zero T_sblk_opin_to_clb_opin lt float gt Delay from the output of a subblock to a CLB logic block output pin For architectures without local routing e g the output of a LUT is hardwired to each logic block output this delay is essentially zero T_subblock T_comb lt float gt T_seq_in lt float gt T_seq_out lt float gt Describes the delays within a subblock There must be one T_subblock line for each subblock a logic block can contain i e there
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