User`s Manual - MSC Technologies
Contents
1. Address Function Value PIN 0x07C8 CAN1 RX 0x10 ATA DATA7 0x07CC CAN2 0x01 RTS2 0x07D0 CCM_32K 0x00 CAPTURE 0x07D4 PMIC_RDY 0x00 GPIO1_0 0 07 0 CSPI2 0 10 0x07E8 CSPI2 MISO 0x00 SRXD5 0x07EC CSPI2 MOSI 0x10 ATA DIOW 0x07F0 CSPI2 550 0x01 51 0x07F4 CSPI2 SS1 0x01 ATA_DIOR 0x0800 EMI DTAC 0x01 TXO 0 082 1_0 0 01 STXD5 0x0830 GPIO1 10 0x00 TX5 0x0834 GPIO1 11 0x00 TX4 RX1 0x0838 1 0x10 CONTRAST 0x083C GPIO1 20 0x01 CSI D8 0x0840 GPIO1 21 0x01 CSI D9 0x0844 GPIO1 22 0x01 CSI D810 0x0848 GPIO1 2 0x00 SCK5 0x084C GPIO1 3 0x01 03 REV 0x0850 GPIO1_4 0x10 D3 CLS 0x0854 GPIO1 5 0x10 D3 SPL 0x0858 GPIO1 6 0x01 HCKR 0x085C GPIO1 7 0x01 HCKT 0x0860 GPIO1_8 0x01 FST 0x0864 GPIO1_9 0x00 HCKT 0x0868 GPIO2 0 0x01 LDO 0x086C GPIO2 10 0x10 ATA DMACK 0x0870 GPIO2 11 0x10 ATA RESET 0x0874 GPIO2 12 0x01 ATA_IORDY 0x0878 GPIO2 13 0x01 ATA_DATAO 0x087C GPIO2 14 0x01 0x0880 GPIO2 15 0x01 ATA_DATA2 0x0884 GPIO2 16 0x01 LD16 0x0888 GPIO2 17 0x00 LD17 0x088C GPIO2 18 0x01 ATA_DATA5 0x0890 GPIO2_19 0x01 ATA DATA6 0x0890 GPIO2 1 0x00 LD1 0x0898 GPIO2 20 0x01 ATA_DATA7 0x08A0 GPIO2 21 0x01 ATA_DATA8 0x08A1 GPIO2 22 0x01 ATA DATA9 0x08A2 GPIO2 23 0x01 ATA_DATA10 0x08AC GPIO2 25 0 01 DATA12 0 08 0 GPIO2 26 0x01 ATA_DA2. Pin Signal Pin Signal Pin Signal Pin Signal 1 Multi Mode Pin 2 1 Multi Mode Pin 2 3 Multi Mode Pin 4 3 Multi Mode Pin 4 5 Multi Mode Pin 6 5 Multi Mode Pin 6 7 Multi Mode Pin 8 Multi Mode Pin 7 Multi Mode Pin 8 Multi Mode Pin 9 Multi Mode Pin 10 Multi Mode Pin 9 Multi Mode Pin 10 Multi Mode Pin 11 Multi Mode Pin 12 11 Multi Mode Pin 12 13 Multi Mode Pin 14 Multi Mode Pin 13 Multi Mode Pin 14 Multi Mode Pin 15 Multi Mode Pin 16 15 Multi Mode Pin 16 17 Multi Mode Pin 18 50100 WP 17 Multi Mode Pin 18 SDIO0 WP 19 Multi Mode Pin 20 50100 CLK 19 Multi Mode Pin 20 SDIO0 CLK 21 Multi Mode Pin 22 50100 CD 21 Multi Mode Pin 22 SDIO0 CD 23 Multi Mode Pin 24 50100 23 Multi Mode Pin 24 50100 25 Multi Mode Pin 26 50100 DATO 25 Multi Mode Pin 26 50100 DATO 27 Multi Mode Pin 28 SDIOO_DAT1 IRQ 27 Multi Mode Pin 28 SDIOO_DAT1 IRQ 29 Multi Mode Pin 30 SDIOO DAT2 RW 29 Multi Mode Pin 30 SDIOO DAT2 RW 31 Multi Mode Pin 32 SDIOO 31 Multi Mode Pin 32 SDIOO DAT3 33 LCD2 EN 34 MODULE 100 MB 33 LCD2 EN 34 MODULE 100 EXT 35 MODULE DETECT 36 MODULE 101 MB 35 MODULE DETECT 36 MODULE 101 EXT 37 COMO TXD 38 37 COMO TXD 38 n c 39 COMO RXD 40 39 COMO RXD 40 41 COMO _RTS 42 41 COMO RTS 42
3. Pin Signal Pin Signal Pin Signal Pin Signal 1 2 CF SCKSEL 1 2 CF SCKSEL 3 4 1 3 4 5 6 CF 2 5 6 2 7 PWEN a CF_IORD 7 PWEN a CF_IORD 9 CF1_PWEN 10 CFJOWR 9 CF1_PWEN CFJOWR 11 CF_INPACK 12 11 INPACK 12 13 RESET 14 13 RESET 14 PWE Z 15 CF1 RESET 16 WAIT 15 CF1 RESET 16 WAIT 17 SPI 550 18 101516 17 SPI SSO 18 101516 19 SPI 551 20 CF PREG 19 SPI SS1 20 CF PREG 21 n c 22 RDY 21 22 23 SPI SCK 24 CF1 23 SPI 5 24 CF1 RDY 25 SPI MOSI 26 CF0 25 SPI MOSI 26 27 SPI MISO 28 CF1 27 SPI MISO 28 CF1 29 GND 30 GND 29 GND 30 GND 31 GND 32 GND 31 GND 32 GND 33 GND 34 GND 33 GND 34 GND 35 GND 36 GND 35 GND 36 GND 37 GND 38 GND 37 GND 38 GND 39 GND 40 GND 39 GND 40 GND 41 GND 42 GND 41 GND 42 GND 43 GND 44 GND 43 GND 44 GND 45 GND 46 GND 45 GND 46 GND 47 GND 48 GND 47 GND 48 GND 49 GND 50 GND 49 GND 50 GND 51 GND 52 GND 51 GND 52 GND Pin Signal Pin Signal Pin Signal Pin Signal 1 DOO 2 D01 1 D00 2
4. 1011 ALTO IPU DISPB DAT 11 LD12 ALTO IPU DISPB DAT 12 LD13 ALTO IPU DISPB DAT 13 LD14 ALTO IPU DISPB DAT 14 LD15 ALTO IPU DISPB DAT 15 LD16 ALT5 GPIO2 GPIO 16 LD17 ALT5 GPIO2 GPIO 17 LD18 ALTO IPU DISPB DAT 18 LD19 ALTO IPU DISPB DAT 19 LD20 ALTO IPU DISPB DAT 20 LD21 ALTO IPU DISPB DAT 21 LD22 ALTO IPU DISPB DAT 22 LD23 ALTO IPU DISPB DAT 23 D3 HSYNC ALTO IPU DISPB D3 HSYNC 03 FPSHIFT ALTO IPU DISPB D3 CLK D3 DRDY ALTO IPU DISPB D3 DRDY CONTRAST ALT5 GPIO1 GPIO 1 D3 VSYNC ALTO IPU DISPB D3 VSYNC D3 REV ALT5 GPIO1 GPIO 3 D3 CLS ALT5 GPIO1 GPIO 4 D3 SPL ALT5 GPIO1 GPIO 5 01 ALTO ESDHC1 CMD SD1_CLK ALTO ESDHC1 CLK SD1_DATAO ALTO ESDHC1 DATO SD1_DATA1 ALTO ESDHC1 DAT1 SD1 DATA2 ALTO ESDHC1 DAT2 SD1_DATA3 ALTO ESDHC1 DAT3 SD2_CMD ALT1 1203 SCL SD2_CLK ALT1 2 3 SDA SD2_DATAO ALT5 GPIO2 GPIO 2 SD2 DATA ALT5 GPIO2 GPIO 3 SD2 DATA2 ALT5 GPIO2 GPIO 4 SD2 DATAS ALT5 GPIO2 GPIO 5 ATA CSO ALT5 GPIO2 GPIO 6 ATA CS1 ALT4 2 980 DIOR ALT4 2 91 DIOW ALT4 CSPI2 MOSI ATA DMACK ALT5 GPIO2 GPIO 10 ATA RESET ALT5 GPIO2 GPIO 11 ATA IORDY ALT5 GPIO2 GPIO 12 ATA DATAO ALT5 GPIO2 GPIO 13 ATA DATA ALT5 GPIO2 GPIO 14 ATA DATA2 ALT5 GPIO2 GPIO 15 ATA DATA3 ALT5 GPIO2 GPIO 16 ATA DATA4 ALT5 GPIO2 GPIO 17 ATA DATAS ALT5 GPIO2 GPIO 18 ATA DATAG ALT1 CAN1 TXCAN
5. Pad Name Mode Instance Port Pad settings Function IMX35 IMX35 IMX35 IMX35 DDR Memory SDO ALTO EMI DRAM 0 SDO SD1 ALTO EMI DRAM 1 SD1 SD2 ALTO EMI DRAM 2 502 503 ALTO EMI SD3 504 ALTO EMI 4 804 805 ALTO EMI DRAM S SD5 SD6 ALTO EMI DRAM 6 SD6 807 ALTO EMI DRAM T 807 808 ALTO EMI 8 808 809 ALTO EMI 9 809 5010 ALTO EMI 10 5010 5011 ALTO EMI DRAMI 1 1 SD11 SD12 ALTO EMI DRAN 12 SD12 SD13 ALTO EMI DRAM 13 SD13 SD14 ALTO EMI DRAN 14 SD14 SD15 ALTO EMI DRAN 15 SD15 SD16 ALTO EMI DRAN 16 SD16 SD17 ALTO EMI DRAM 17 SD17 SD18 ALTO EMI DRAM 18 5018 5019 ALTO EMI DRAM 19 SD19 SD20 ALTO EMI DRAM 20 SD20 8021 ALTO EMI DRAM 21 5021 5022 ALTO EMI DRAM 22 SD22 SD23 ALTO EMI DRAM 23 SD23 SD24 ALTO EMI 24 8024 5024 ALTO EMI DRAM 25 SD24 SD26 ALTO EMI DRAM 26 SD26 SD27 ALTO EMI DRAM 27 SD27 SD28 ALTO EMI DRAM 28 SD28 28 EXM32 EXM IMX35 CPU Module User s Manual SD29 ALTO EMI 29 8029 5030 ALTO EMI DRAM 30 SD30 8031 ALTO EMI DRAN 31 E SD31 SDBA1 ALTO EMI EMI SDBA1 SDBA1 SABAO ALTO EMI EMI SDBAO SABAO DQMO ALTO EMI DRAM DQMO DQMO DQM1 ALTO EMI DRAM DOM DQM1 DQM2 ALTO EMI DRAM DQM2 DQM2 DQM3
6. ALT1 CAN1 RXCAN DATA8 ALT1 UART3 RTS 40 EXM32 EXM IMX35 CPU Module User s Manual ATA DATA9 ALT1 UART3 CTS ATA DATA10 ALT1 UART3 RXD MUX ATA DATAt1 ALT1 UART3 TXD MUX ATA DATA12 ALT5 GPIO2 GPIO 25 ATA DATA13 ALT5 GPIO2 GPIO 26 ATA DATA14 ALT5 GPIO2 GPIO 27 ATA_DATA15 ALT5 GPIO2 GPIO 28 ATA INTRQ ALT5 GPIO2 GPIO 29 ATA BUFF EN ALT5 GPIO2 GPIO 30 ATA DMARQ ALT5 GPIO2 GPIO 81 ATA DAO ALT5 GPIO3 GPIO 0 ATA DA1 ALT5 GPIO3 GPIO 1 ATA DA2 ALT5 GPIO3 GPIO 2 TTM PAD ALTO THERMAL TTM PAD N C MLB CLK ALTO MLB MLB CLK MLB DAT ALTO MLB MLB DAT MLB SIG ALTO MLB MLB SIG FEC TX CLK ALTO FEC TX CLK FEC RX CLK ALTO FEC RX CLK FEC RX DV ALTO FEC RX DV FEC COL ALTO FEC COL FEC RDATAO ALTO FEC RDATA 0 FEC TDATAO ALTO FEC TDATA O FEC TX EN ALTO FEC TX EN FEC MDC ALTO FEC MDC FEC MDIO ALTO FEC MDIO FEC TX ERR ALTO FEC TX ERR ERR ALTO FEC RX ERR FEC CRS ALTO FEC CRS RDATA1 ALTO FEC RDATA 1 FEC TDATA1 ALTO FEC TDATA 1 FEC RDATA2 ALTO FEC RDATAI2 FEC_TDATA2 ALTO FEC TDATA 2 FEC ALTO FEC ALTO FEC TDATA 3 EXT ARMCLK ALTO CCM EXT ARMCLK TEST MODE ALTO FEC TEST MODE Table 42 IMX35 I O multiplexing pin out 41 EXM32 EXM IMX35 CPU Module User s Manual 4 1 2 Daisy Chain Bit
7. Pad Name Mode Instance Port Function CAPTURE ALTA CCM CLK32K COMPARE ALT7 SDMA EXTDMA 2 WDOG_RST ALTO WDOG WDOG B GPIO1 0 ALT1 CCM PMIC RDY GPIO1 1 ALT7 SDMA 1 GPIO2 0 ALTO GPIO2 GPIO 0 GPIOS3 0 ALTO GPIOS GPIO 0 CLKO ALTO CCM CLKO VSTBY ALTO CCM VSTBY CS1 ALTO EMI EIM CS1 CS2 No Muxing EMI EIM CS2 CS3 No Muxing EMI EIM_CS3 CS4 ALTO EMI 54 55 ALTO EMI EIM CS5 NF CEO ALTO EMI NANDF CEO NFWE B ALTO EMI NANDF WE B NFRE B ALTO EMI NANDF RE B NFALE ALTO EMI NANDF ALE NFCLE ALTO EMI NANDF CLE NFWP B ALTO EMI NANDF WP B NFRB ALTO EMI NANDF RB CSI D8 ALTO IPU CSI D 8 CSI D9 ALTO IPU CSI D 9 CSI D10 ALTO IPU CSI D 10 CSI D11 ALTO IPU CSI D 1 1 CSI D12 ALTO IPU CSI D 12 CSI D13 ALTO IPU CSI D 13 CSI D14 ALTO IPU CSI D 14 CSI D15 ALTO IPU CSI D 15 CSI MCLK ALT5 GPIO1 GPIO 28 CSI VSYNC ALTO IPU CSI VSYNC CSI HSYNC ALTO IPU CSI HSYNC CSI PIXCLK ALTO IPU CSI PIXCLK l2C1 ALTO 1261 SCL 1261 DAT ALTO 1261 SDA 1262 ALT2 USB TOP USB2 PWR 1262 DAT ALT2 USB TOP USBH2 OC STXD4 ALTO AUDMUX AUDA TXD SRXD4 ALTO AUDMUX AUD4 RXD SCK4 ALTO AUDMUX AUD4_TXC STXFS4 ALTO AUDMUX AUD4_TXFS 38 EXM32 EXM IMX35 CPU Module User s Manual STXD5 ALT5 GPIO1 GPIO O SRXD5 ALT2 CSPI2 MISO SCK5 ALT5 GPIO1 GPIO 2 STXF
8. GPIO3 IN NO GPIO_DDR_ASMBL Y_OPT ATA_DA0 GPIO3 IN NO IMX CPLD1 GPIOO ATA DA1 GPIO3 OUT NO IMX SUSPEND ATA DA2 GPIO3 OUT NO IMX_USER_LEDO CSPM SCLK GPIO3 OUT NO X1D DACKO CSPI1 SPI GPIO3 GPIO OUT NO X1D_DACK1 DY ATA_DAO GPIO3 GPIO OUT NO IMX_USER_LED1 RXD2 TXD2 GPIO3 IN NO CPLD1 GPIO1 Table 28 IMX35 GPIO Bank I O multiplexing 27 EXM32 EXM IMX35 CPU Module User s Manual 2 1 20 DDR2 SDRAM During initialisation the software can detect the amount of DRAM populated on the module by reading GPIO3 0 H 256MByte L 128MByte It is not possible to detect memory by reading writing invalid memory After reading GPIO3 0 the pin multiplexing must be changed as follows 1 Set GPIOS 0 as input 2 Read GPIOS 0 3 Route GPIOS 0 to pin ATA 4 Set respective daisy chain bit The EXM32 IMX35 CPU Module can be populated with up to 256 Mbyte 133MHz DDR2 SDRAM memory organized in 2 banks of 2 x16 devices 512MBit each For the 128 MByte configuration only bank 0 is populated For detailed description of the memory space mapping and for detailed setup and initialization of the 35 SDRAM Controller please refer to chapter 3 3 7 3 3 8 Off chip Memory
9. 26 27 28 27 28 29 30 TX 29 30 31 GND 32 CANO STB 31 GND 32 n c 33 34 CAN1 EN 33 n c 34 35 36 35 36 37 GND 38 37 38 39 GND 40 CANO TX 39 GND 40 41 USB D 42 STB 41 USBO EXT D 42 43 USB OTG D 44 USB OTG ID 43 USBO EXT D 44 n c 45 GND 46 USB OTG VBUS 45 GND 46 n c 47 USB MB _ D 48 USB OTG PWEN 47 USB1 EXT D 48 n c 49 USB MB D 50 USB MB PWEN 49 USB1 EXT D 50 51 GND 52 USB OC 51 GND 52 n c X2 B MB CPU Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 GND 1 GND 2 GND 3 4 3 4 5 GND 6 5 GND 6 GND 7 8 7 8 9 GND 10 GND 9 GND 10 GND 11 12 11 12 13 14 13 14 15 16 15 16 17 18 17 18 19 n c 20 n c 19 n c 20 n c 21 22 BSCAN EN 21 22 BSCAN EN 23 GND 24 GND 23 GND 24 GND 25 26 25 26 27 GND 28 GND 27 GND 28 GND 29 30 29 30 31 32 31 32 33 34 33 34 35 GND 36 GND 35 GND 36 GND 37 38 37 38 39 40 39 40 41 42 41 42 43 44 43 44 45 46 45 46 47 48 47 48 49 50 49 50 51 52 51 52 EXM32 EXM IMX35 CPU Module User s Manual X2 C X2
10. 43 COMO CTS 44 43 5 44 45 TXD 46 45 COM1 TXD 46 47 COM1 RXD 48 47 1 RXD 48 n c 49 1 RTS Z 50 49 COM1 RTS 50 51 COM1 CTS 52 51 COM1 CTS Z 52 10 EXM32 EXM IMX35 CPU Module User s Manual 2 Hardware Description 21 Functional Blocks 2 1 1 CPU Freescale 532 MHz IMX35 Processor with 133 MHz AHB Clock and 66 5 MHz external Local Bus Clock CLKOUT 2 1 2 Clocks The processor clocks are generated from two crystals a 24MHz crystal for the core frequency and a 24 576 MHz crystal for the audio subsystem 2 1 3 PC ID EEPROM The IDEEPROM is used to store module specific parameters For a parameter overview and a memory map of the IDEEPROM please refer to appendix A The Catalyst Supervisor CAT1026 device is used on the board to provides 2048 byte of serial electrical erasable and programmable read only memory Data transfer between CPU and the IDEEPROM is handled via 2 Bus I C Bus is routed to I C Channel 1 of the IMX35 2 interface The address offset 1010000 is used to access the device IDEEPROM device address 1010000x 0 Table 1 ID EEPROM Address 2 1 4 Real Time Clock On the EXM32 IMX35 CPU Module a discrete 2 device is used so a Lithium coin cell is sufficient to buffer the device over 5 years The Seiko Epson RTC8564NB real time clock module offer
11. X2D LCD2 D0 I amp X2D LCD2 HSYNC I X2D LCD2 VSYNC I X2D SHFCLK 4 Figure 7 IMX35 Camera Sensor interface EXM 32 Module Connector The IMX35 CPU can boot from NOR Flash NAND Flash SD Card or NOR Flash populated on motherboards The various boot modes are selected by the EXM32 signals Module 100 1 Boot medium Baseboard Module ID Chip select NOR FLASH 00 CSO NAND FLASH 00 CSN SD CARD 10 or 01 NOR FLASH TEST 11 CSA mode Table 25 IMX35 Boots Modes For detailed EXM32 pin multiplexing please refer the EXM32 specification 25 EXM32 EXM IMX35 CPU Module User s Manual 2 1 19 GPIO The IMX35 microprocessor provides 3 Banks of GPIO with interrupt capability all system interrupts are located on GPIO Bank 1 Pad Name Mode Instance Port Pad GPIO Interrupt Function IMX35 IMX35 IMX35 settings capability EXM 32 IMX35 STXD5 ALT5 GPIO1 GPIO1 0 22K UP IN Yes X1B IRQ MBO CONTRAST ALT5 GPIO1 GPIO1 1 22K UN IN Yes X1B IRQ 1 SCK5 ALT5 GPIO1 GPIO1 2 22K UP IN Yes X1B_IRQ_MB2 D3_REV ALT5 GPIO1 GPIO1 3 OUT NO IMX CNFG RDY STXFS5 ALT5 GPIO1 GPIO1 3 22K UP IN Yes SDIO 03 CLS ALT5 GPIO1 GPIO1 4 22K UP IN Yes X1B_IRQ_EXTO D3_SPL ALT5 GPIO1 GPIO1 5 22K UP IN Yes X1B_IRQ_EXT1
12. 20 5 19 20 5 21 22 5 21 22 VCC3V3STB 23 24 VCC3V3STB 23 24 VCC3V3STB 25 26 VCC5VO 25 VBAT 26 VCC5VO 27 VBAT RET 28 VCC5VO 27 28 5 0 29 PWROFF SUSPEND 30 5 0 29 PWROFF SUSPEND 30 VCC5VO 31 SLEEP 32 5 0 31 SLEEP 32 33 WAKEUP 34 VCC5VO 33 WAKEUP 34 VCC5VO 35 PWRFLT 36 VCC5VO 35 PWRFLT 36 VCC5VO 37 MASTER RST 38 ETH ACTLED 37 MASTER RST 38 n c 39 PERIPH RST 40 ETH_LNKLED 39 PERIPH_RST 40 41 AUDIO RST 42 AC97 SDIN1 41 AUDIO RST 42 AC97 SDIN1 43 AC97 SYNC 44 AC97 SDINO 43 AC97 SYNC 44 97 SDINO 1250 LRCLK 1250 SCLK 1250 LRCLK 1250 SCLK 45 1261 LRCLK 46 1251 5 45 1251 LRCLK 46 1251 5 97 SDOUT AC97_SDOUT SNP 8 250 8010 AT ANE 48 1250 8010 AC97 BCLK 97 BCLK 49 125 MCLK 50 1251 SDIO 49 125 50 1251 SDIO 51 GND 52 51 GND 52 X1 D MB CPU X1 Pin Signal Pin Signal Pin Signal Pin Signal 1 2 A01 1 2 A01 3 A02 4 A03 3 A02 4 A03 5 A04 6 A05 5 A04 6 A05 7 A06 8 A07 7 A06 8 A07 9 A08 10 A09 9 A08 10 A09 11 A10 12 A11 11 A10 12 A11
13. 1 100K UP X2A CANO RX ATA 1 ALT5 GPIO2 GPIO2 14 X2A CAN1 EN ATA DATA2 ALT5 GPIO2 GPIO2 15 X2A CANO EN IORDY ALT5 GPIO2 GPIO2 12 100K UP 2 ERRZ DATA12 ALT5 GPIO2 GPIO2 25 100K UP X2A CANO DATAO ALT5 GPIO2 GPIO2 13 2 STB Z ATA DATAO ALT5 GPIO2 GPIO2 26 2 5 Table 9 IMX35 CAN I O multiplexing pin out 16 EXM32 EXM IMX35 CPU Module User s Manual 2 1 12 Audio Codec Interface AC 97 PS LJ RJ The EXM IMX35 CPU Module features a combined AC 97 l S slave audio codec interface The signals are routed through the CPLD in order to adapt the audio signal to the module pin out as required for the respective interface mode The audio multiplexer in the CPLD is controlled by GPIO IMX 125 97 MODE Pad Name Mode Instance Port Pad settings Function IMX35 IMX35 IMX35 IMX35 EXM 32 STXD4 ALTO AUDMUX AUD4_TXD CPLD0 SRXD4 ALTO AUDMUX AUD4_RXD CPLDO SCK4 ALTO AUDMUX AUD4_TXC CPLD0 STXFS4 ALTO AUDMUX AUD4 TXFS CPLDO 502 DATAO ALT5 GPIO2 GPIO2 2 125 97 MODE ATA INTRQ ALT5 GPIO2 GPIO2 29 100K DN X1C AUDIO RST Table 10 IMX35 125 9 interface to CPLD I O multiplexing pin out Pad Name Mode Instance Port Direction Function IMX35 IMX35 IMX35 5
14. 2 5 7777 OUT NO X2C LCD BLON 50 ALT5 GPIO2 2 6 7777 OUT NO X2C LCD VCON ATA DMACK ALT5 GPIO2 GPIO2 10 77 OUT NO X2C LCD VDON ATA ALT5 GPIO2 GPIO2 11 77 OUT NO X2C LCD DON ATA IORDY ALT5 GPIO2 GPIO2 12 77 IN NO 2 ERR ATA DATAO ALT5 GPIO2 GPIO2 13 77 OUT NO 2 5 DATA1 ALT5 GPIO2 GPlO2 14 777 OUT NO 2 EN DATA2 ALT5 GPIO2 GPIO2 15 77777 OUT NO 2 CANO EN ATA DATAS ALT5 GPIO2 GPlO2 18 7777 OUT NO IMX RESET OUT ATA DATA12 ALT5 GPIO2 GPIO2 25 7777 IN NO X2A CANO ERR ATA DATA13 ALT5 GPIO2 GPlIO2 26 7777 OUT NO 2 CANO 5 DATA14 ALT5 GPIO2 GPIO2 27 OUT NO X2D SDIO WP ATA DATA15 ALT5 GPIO2 GPlO2 28 7777 OUT NO X2D LCD2 EN ATA INTRQ ALT5 GPIO2 GPIO2 29 OUT NO 128 97 MODE ATA BUFF E ALT5 GPIO2 GPIO2 30 OUT NO X2D GP OUTO N ATA ALT5 GPIO2 GPIO2 31 77777 OUT NO X2D GP LDO ALT5 GPIO2 2 0 777 OUT NO X2D GP OUT 2 LD1 ALT5 GPIO2 GPIO 777 OUT NO X2D_GP_OUT3 LD8 ALT5 GPIO2 2 8 OUT NO X2D_GP_OUT4 LD9 ALT5 GPIO2 2 9 77777 OUT NO X2D GP OUT5 LD16 ALT5 GPIO2 GPIO2 16 OUT NO X2D GP OUT6 LD17 ALT5 GPIO2 GPIO2 17 77 OUT NO X2D GP OUT7 Table 27 IMX35 GPIO Bank 2 I O multiplexing Pad Name Mode Instance Port Pad IGPIO Interrupt Function IMX35 IMX35 IMX35 settings capability IMX35
15. Pin Signal Pin Signal Pin Signal Pin Signal 1 LCD D00 BO 2 2 0 SDA 1 LCD D00 BO 2 2 0 SDA 3 LCD 001 B1 4 2 SCL 3 LCD 001 B1 4 2 SCL 5 LCD 002 B2 6 12C1_ SDA 5 LCD 002 B2 6 12C1_ SDA 7 LCD D03 B3 8 2 SCL 7 LCD D03 B3 8 2 SCL 9 LCD 004 B4 10 ETH CENTER 9 LCD 004 B4 10 n c 11 LCD 005 B5 12 11 LCD 005 B5 12 n c 13 LCD 006 GO 14 13 LCD 006 GO 14 n c 15 LCD 007 G1 16 GND 15 LCD 007 G1 16 GND 17 LCD 008 G2 18 ETH TXDO 17 LCD 008 G2 18 n c 19 LCD 009 G3 20 ETH TXDO 19 LCD 009 G3 20 21 LCD 010 04 22 GND 21 LCD D10 G4 22 GND 23 LCD D11 G5 24 ETH 23 LCD D11 G5 24 n c 25 LCD D12 RO 26 ETH RXDO 25 LCD 012 RO 26 nc 27 LCD D13 R1 28 GND 27 LCD D13 R1 28 GND 29 LCD D14 R2 30 29 LCD D14 R2 30 n c 31 LCD D15 R3 32 31 LCD D15 R3 32 n c 33 LCD D16 R4 34 GND 33 LCD D16 R4 34 GND 35 LCD D17 R5 36 35 LCD D17 R5 36 37 LCD VDON 38 GND 37 LCD VDON 38 GND 39 LCD M DE 40 39 LCD M DE 40 n c 41 LCD VCON 42 GND 41 LCD VCON 42 GND 43 LCD HSYNC 44 43 LCD HSYNC 44 n c 45 LCD VSYNC 46 GND 45 LCD VSYNC 46 GND 47 LCD DON 48 47 LCD DON 48 n c 49 LCD SHFCLK 50 49 LCD SHFCLK 50 51 LCD BLON 52 GND 51 LCD BLON 52 GND X2 D MB CPU X2
16. HCKR ALT5 GPIO1 GPIO1 6 100K DN IN Yes IMX WAKEUP SCKT ALT5 GPIO1 GPIO1 7 IN Yes IMX IEE INTO FST ALT5 GPIO1 1 8 IN Yes IMX IEE INT1 HCKT ALT5 GPIO1 GPIO1 IN Yes IMX IEE INT2 TX5 RXO ALT5 GPIO1 GPIO1 10 IN Yes IMX IEE INT3 TX4 RX1 ALT5 GPIO1 GPIO1 11 IN Yes 4 TX3 RX2 ALT5 GPIO1 GPIO1 12 IN Yes IMX_IEE_INT5 TX2_RX3 ALT5 GPIO1 GPIO1 13 22K UP IN Yes IMX CF 01 TXi ALT5 GPIO1 GPIO1 14 22K UP IN Yes IMX CF 02 8 MOSI ALT5 GPIO1 GPIO1 16 22K UP IN Yes IRO 8 MISO ALT5 GPIO1 GPIO1 17 22K UP IN Yes IMX_ETH_MDINT 5 1_550 ALT5 GPIO1 GPIO1 18 OUT NO IMX_FUSE_WRITE CSPI1_SS1 ALT5 GPIO1 GPIO1 19 OUT NO IMX CPLDO GPIOO CSI MCLK ALT5 GPIO1 GPIO1 28 IN TBD IMX CPLDO GPIO1 Table 26 IMX35 GPIO Bank 1 I O multiplexing 26 EXM32 EXM IMX35 CPU Module User s Manual Pad Name Mode Instance Port Pad IGPIO Interrupt Function IMX35 35 IMX35 settings capability IMX35 DD2 DATAO ALT5 GPIO2 2 2 777 OUT NO IMX AUDIO RST SD2 DATA1 ALT5 GPIO2 2 3 777 OUT NO X1D SD2 DATA ALT5 GPIO2 2 4 777 OUT NO X1D SD2 DATA3 ALT5 GPIO2
17. For detailed MLB capability please refer to the IMX35 Reference Manual chapter 36 Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 MLB CLK ALTO MLB RXD MUX 22K UP X2A MLB MCLK MLB DAT ALTO MLB TXD MUX X2A MLB MDAT MLB SIG ALTO MLB RTS X2A MLB MSIG Table 14 IMX35 MLB multiplexing pin out 2 1 15 USB The IMX35 microprocessor has got two independent USB interfaces one of which is a High Speed USB OTG Port while the other interface is just a Full Speed USB Host There are three assembly options in the 35 CPU module USB Hub is populated full speed USB host 1x High Speed On The Go Four High speed USB ports HOST only USB Hub is not populated 1x Full speed USB host 1x High speed On The Go in this case USB is only available on motherboards 18 EXM32 EXM IMX35 CPU Module User s Manual USB HOST EXM32 CONN USB OTG i MX35 Figure 5 IMX35 USB interface Pad N
18. X2C LCD R6 LD23 ALTO IPU X2C LCD R7 HSYNC ALTO DISPB 03 HSYNC X2C LCD HSYNC FPSHIFT ALTO IPU IDISPB 03 X2C LCD SHFCLK DRDY ALTO IPU DISPB DRDY X2C LCD M DE D3 VSYNC ALTO IPU DISPB D3 VSYNC X2C LCD R5 Table 23 IMX35 24 Bit LCD interface multiplexing pin out 23 EXM32 EXM IMX35 CPU Module User s Manual Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 LDO ALTO GPIO2 GPIO2 0 X2C GP OUT2 LD1 ALTO GPIO2 GPIO 2 1 X2C GP OUT3 LD2 ALTO IPU I X2C_LCD_B0 LD3 ALTO IPU D n X2C LCD B1 LD4 ALTO IPU IPU_D n X2C LCD B2 LD5 ALTO IPU D n X2C LCD LD6 ALTO IPU X2C LCD B4 LD7 ALTO IPU D n X2C LCD B5 LD8 ALTO GPIO2 2 8 X2C GP OUT4 LD9 ALTO GPIO2 GPIO2 9 X2C GP OUT5 LD10 ALTO IPU s X2C LCD GO LD11 ALTO IPU X2C LCD G1 LD12 ALTO IPU X2C LCD 92 LD13 ALTO IPU I X2C_LCD_G3 LD14 ALTO IPU X2C LCD G4 LD15 ALTO IPU I X2C LCD G5 LD16 ALTO GPIO2 GPIO2 16 X2C_GP_OUT6 LD17 ALTO GPIO2 GPIO2 17 X2C GP OUT7 LD18 ALTO IPU s X2C LCD RO LD19 ALTO IPU X2C LCD R1 LD20 ALTO IPU X2C LCD R2 LD21 ALTO IPU X2C LCD
19. 13 A12 14 A13 13 A12 14 A13 15 A14 16 A15 15 A14 16 A15 17 A16 18 A17 17 A16 18 A17 19 A18 20 A19 19 A18 20 A19 21 A20 22 A21 21 A20 22 A21 23 A22 24 A23 23 A22 24 A23 25 A24 26 A25 25 A24 26 A25 27 DREQ0 28 DREQ1 27 DREQ0 28 29 30 29 30 31 32 31 32 33 n c 34 33 n c 34 35 36 35 PCIE PERST Z 36 37 n c 38 37 38 39 GND 40 GND 39 GND 40 GND 41 GND 42 41 GND 42 43 GND 44 43 GND 44 45 GND 46 GND 45 GND 46 GND 47 GND 48 47 GND 48 49 GND 50 49 GND 50 51 GND 52 GND 51 52 GND EXM32 EXM IMX35 CPU Module User s Manual X2 MB CPU 2 Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 1 GND 2 3 4 3 n c 4 MLB MCLK 5 5 n c MLB MSO MLB MSO a GND MLB MSIG GND MLB MSIG 9 10 9 n c 10 MLB MDO n c MLB MDO 12 MLB MDAT n 12 MLB MDAT 13 GND 14 JTAG TDO 13 GND 14 JTAG TDO 16 JTAG TDI 15 n c 16 JTAG TDI 18 JTAG TCK 17 n c 18 JTAG TCK 19 GND 20 JTAG TMS 19 GND 20 JTAG TMS 21 22 JTAG_TRST 21 n c 22 JTAG_TRST 23 24 CANO EN 23 n c 24 n c 25 GND 26 25
20. 28 27 26 25 24 23 22 21 20 19 18 17 16 R tW N tXP TR tRp tMRD DEFAULT 14 dde fe fe fe dede Je fe fe fe INIT 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 15 14 113 112 11 10 9 8 7 6 5 4 3 2 1 0 i E tRAS tRRD tCAS tRCD tRC DEFAULT d fe fe dede fe fe e INIT 1 1 1 1 1 1 0 0 0 0 1 1 0 1 0 0 Table 40 IMX35 Bank 2 SDRAM Timing Register 3 3 8 Area 1 DDR Memory Bank 1 DDR Memory CS1 0x90000000 OX9FFFFFFF The following memory bus timings are needed for reliable system operation ESDCFG1 Address 0xB800100C BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ET tXP tW tRp tMRD TR DEFAULT e Je qe Ver des me lo lo io io lo lo lo lo 1 1 1 Hi 1 BIT 15 14 13 12 11 10 9 8 7 6 5 4 2 1 Jo y W RAS tCAS tRCD tRC DEFAULT e l fee que ae lee 1 1 1 1 1 1 0 o lo Jo 1 1 lo 1 0 Jo Table 41 IMX35 Bank 1 SDRAM Timing Register 37 EXM32 EXM IMX35 CPU Module User s Manual 4 Pinl O Multiplexing 4 1 1 The base address for I O multiplexing and daisy chain is 0 IMX35 Pin Out
21. 32 STXD4 ALTO AUDMUX AUD4_TXD Output X1C 125 SDOUT SRXD4 ALTO AUDMUX AUD4 RXD Input X1C 125 SDIN SCK4 ALTO AUDMUX AUD4_TXC Input X1C l28 SCLK STXFS4 ALTO AUDMUX AUD4_TXFS Input X1C_l2S LRCLK Table 11 IMX35 125 interface I O multiplexing pin out Pad Name Mode Instance Port Direction Function IMX35 IMX35 5 5 32 STXD4 ALTO AUDMUX AUD4 TXD Output X1C_AC_SDOUT SRXD4 ALTO AUDMUX AUD4 RXD Input X1C AC SDIN SCK4 ALTO AUDMUX AUD4_TXC Input X1C_AC_BCLK STXFS4 ALTO AUDMUX AUD4_TXFS Output X1C_AC_SYNC Table 12 IMX35 AC97 interface I O multiplexing pin out 17 EXM32 EXM IMX35 CPU Module User s Manual 2 1 13 UART Interfaces COMO COM1 UART1 and UARTS of the IMX35 are used to implement EXM32 COMO amp COM1 Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 RXD1 ALTO UART1 RXD_MUX 22K UP X2D COMO RXD TXD1 ALTO UART 1 TXD MUX X2D COMO TXD RTS1 ALTO UART1 RTS 22K UP X2D COMO CTS CTS1 ALTO CTS X2D COMO RTS DATA10 ALT1 UART3 RXD 22K UP X2D COM1 RXD DATA11 ALT1 UART3 TXD MUX X2D COM TXD DATA8 ALT1 UART3 RTS 22K UP X2D_COM1_CTS DATA9 ALT1 UART3 CTS X2D RTS Table 13 IMX35 UART I O multiplexing pin out 2 1 14 Media Local Bus MLB The 3 wire MLB interface of the IMX35 microprocessors is routed to the respective EXM32 connector pins
22. D01 3 D02 4 D03 3 D02 4 D03 5 D04 6 D05 5 D04 6 D05 7 D06 8 D07 7 D06 8 D07 9 D08 10 D09 9 D08 10 D09 11 D10 12 D11 11 D10 12 D11 13 D12 14 D13 13 D12 14 D13 15 D14 16 D15 15 D14 16 D15 17 18 17 18 19 20 19 20 21 22 21 22 23 24 23 24 25 26 25 26 27 28 27 28 29 30 29 30 31 32 31 32 33 BEO 34 1 33 BE0 34 1 35 36 35 36 37 IRQ 38 37 IRQ 38 n c 39 IRQ EXTO 40 CSA 39 IRQ_EXTO 40 41 IRQ_MB2 42 41 IRQ_MB2 42 43 IRQ_MB1 44 43 IRQ_MB1 44 45 IRQ_MB0 46 OE 45 IRQ 46 47 GND 48 WE 47 48 49 BUSCLK 50 R W 49 BUSCLK 50 R W 51 GND 52 RDY 51 GND 52 RDY EXM32 EXM IMX35 CPU Module User s Manual X1 MB CPU X1 Pin Signal Pin Signal Pin Signal Pin Signal 1 VCC3V3 2 VCC3V3 1 VCC3V3 2 VCC3V3 3 VCC3V3 4 VCC3V3 3 4 VCC3V3 5 VCC3V3 6 VCC3V3 5 VCC3V3 6 VCC3V3 7 VCC3V3 8 VCC3V3 7 VCC3V3 8 VCC3V3 9 VCC3V3 10 9 VCC3V3 10 11 12 VCC3V3 11 12 VCC3V3 13 14 VCC3V3STB 13 VCC3V3 14 VCC3V3STB 15 VCC3V3 16 VCC3V3STB 15 16 VCC3V3STB 17 VCC3V3 18 VCC3V3STB 17 18 VCC3V3STB 19
23. LD22 ALTO IPU X2C LCD R4 LD23 ALTO IPU X2C LCD R5 HSYNC ALTO IPU DISPB_D3_HSYNC X2C LCD HSYNC 03 FPSHIFT ALTO IPU IDISPB 03 X2C LCD SHFCLK DRDY ALTO IPU DISPB D3 DRDY X2C LCD M DE D3 VSYNC ALTO IPU DISPB D3 VSYNC X2C LCD R5 Table 24 IMX35 18 Bit LCD interface multiplexing pin out The IPU interface must generally be configured for 24 bit mode In 18 bit mode the two least significant bits of each colour component must be configured as GPIO GP OUT 24 EXM32 EXM IMX35 CPU Module User s Manual 2 1 18 IPU CSI CAMERA SENSOR INTERFACE A subset of the camera interface of the IMX35 CPU is available on the EXM32 camera interface for 8 Bit BT 656 video sources The CSI is routed through a CPLD since the signals also serve as strap option pins during Reset For detailed boot options of the microprocessor please refer the IMX35 Reference Manual CSI D15 CSI 014 CSI D13 CSI 012 CSI D CSI D10 CSI CSI 008 CSI HSYNC CSI VSYNC CSI SHFCLK i MX35 CSI D7 CSI D6 CSI 05 CSI CSI o CPLD 1 CSI DI CSI CSI HSYNC lt lt lt lt lt lt lt lt lt lt CSI VSYNC CSI SHFCLK lt X2D LCD2 D7 X2D LCD2 D6 l X2D LCD2 D5 4 20 LCD2 K X2D LCD2 X2D LCD2 D2 IK X2D LCD2 amp
24. gals Copyright NotiCe ce ponen ata te eei ie eate A u u sna a eee apes Ee teen EMG IR I8S u u NEL E ur ceni sepe ECC dm Pee aai o ieee Certification umet uh tute be da ais ier e ete o PT eedem S Product Supports l vn reo eta Urge t o eer eut 1 ie n Ped lote edt E pu wakasapa aaa kaa dus 1 1 Functional BICK ie EN ed et e Do ck e PA T Hd dore 12 EXMS2 i MX35 available Signals 2 Hardware erties P REED RC Re e PEDEM ederet edd 11 2 1 Funcional BloCkS interire ier eerie a ets 11 2 1 1 Aer D Es tec istis 11 211 2 UGIOCKS ic sto r eie tg s ttt nei te as tv e cee 11 249 EC IDEEPROM uu etre aa amam ttt fee to n ere NR or eet UT Du enters 11 2 1 4 Time Glock dee deerant e eoa gan Ce cese na adero etn 11 2 1 5 esrb itor bte kuna 12 2 1 0 112 n E 12 2 1 IMMQG SD SDIQO rer Y ertet M o Ee O
25. 0x00001000 Table 31 IMX35 Memory interface power supply register WARNING Setting this registers to 0 00000800 Power Supply 3 3V may damage the memory 30 EXM32 EXM IMX35 CPU Module User s Manual 3 Programming Guide 3 1 For a description of the Peripheral Memory Space please refer to the IMX35 Hardware Manual Peripheral Memory Map 3 2 Off chip Memory Map AREA OPF CHIP ADDRESSES SIZE BUS WIDTH INTERFACE A25 A0 0 0xA0000000 to OxA7FFFFFF 128 16 50 1 0xA8000000 to OxAFFFFFFF 128 16 CS1 Flash 2 0xB0000000 to OxBiFFFFFF 32 16 CS2 SRAM 3 0xB2000000 to OxB3FFFFFF 32 MB 16 bit 16 bit CS3 Spare 4 0xB4000000 to OxB5FFFFFF 32 MB 16 bit 16 bit CS4 Spare 5 0xB6000000 to OxB7FFFFFF 32 16 bit CS5 spare Table 32 IMX35 external memory space cso CS1 CSA gt _ Compact Flash CTRL SIGNALS 55 gt LBA EBT y CPLD1 OE gt RW gt CLOCKOUT gt TXO DTAC DTAC CBSC_CTRL ere 5 i FLASH S Ax 1 i MX35 i E ADD BUS KOAZ B DAT BUS D0 D15 Figure 8 IMX35 external Local Bus architecture The TXO pin of the IMX35 must be configured as Data Acknowledge DTACK input Data Acknowledge is used for CS1 CS4 and CS5 The CLKO pin must be configured
26. ALTO EMI DRAM DQM3 DQM3 RAS ALTO EMI DRAM_RAS RAS CAS ALTO EMI DRAM_CAS CAS SDWE ALTO EMI DRAM SDWE SDWE SDCKEO ALTO EMI DRAM SDCKEO SDCKEO SDCKE1 ALTO EMI DRAM_SDCKE1 SDCKE 1 SDCLK ALTO EMI DRAM SCLK SDCLK SDQSO ALTO EMI DRAM SDQGS 0 lt SDQS0 SDQS1 ALTO EMI DRAM SDGS 1 SDQS1 SDQS2 ALTO EMI DRAM_SDQS 2 SDQS2 SDQS3 ALTO EMI 5005131 50653 ALTO EMI EMI DA H 0 1 ALTO EMI EMI DA H 1 A1 A2 ALTO EMI EMI DA H 2 A2 A3 ALTO EMI EMI DA H 3 A3 A4 ALTO EMI EMI DA H 4 D 4 5 ALTO EMI EMI DA H 5 A5 A6 ALTO EMI EMI DA H 6 A6 A7 ALTO EMI EMI 7 8 ALTO EMI EMI DA H 8 A8 A9 ALTO EMI EMI DA H 9 A9 MA10 ALTO EMI EMI DA H 10 MA10 MA11 ALTO EMI EMI DA H 11 MA11 MA12 ALTO EMI EMI DA H 12 E MA12 SDCLK ALTO EMI DRAM_SDCLK SDCLK Table 29 IMX35 Memory interface Address Space Memory Select Bank 0 0x80000000 0x8FFFFFFF CS0 CS2 Bank 1 0x90000000 0x9FFFFFFF CS1 CS3 Table 30 IMX35 Memory Space 29 EXM32 EXM IMX35 CPU Module User s Manual The following register settings defaults are needed to select the appropriate power rail for the SDRAM memory Address Source Power Value Supply in V Ox43FAC794 CAS RAS SDCKEO SDCKE1 1 8 0x00001000 0 43 798 SDQSO 50051 50052 50053 1 8 0x00001000 0x43FAC79C SDBAO SDBA 1 1 8 0x00001000 0x43FAC7A0 500 5031 1 8 0 00001000 0x43FAC7A4 A0 A25 DQM0 DQM3 MA10 1 8
27. B NFWP B ALTO EMI NANDF WP WP Table 7 NAND FLASH IMX35 I O multiplexing pin out 14 EXM32 EXM IMX35 CPU Module User s Manual 2 1 10 Ethernet There are two options available for the PHY used with the integrated Fast Ethernet Controller FEC MAC of the IMX35 microprocessor Either a standard PHY SMSC LAN8710i or an IEEE1588 compatible Real time PHY National DP83640 can be populated Figure 3 EFC Interface i MX35 GPIOS 0 Interrupt R EFC Interface ETHERN PHY MDIN T zr gt lt 32 Module Connector IMX35 Ethernet interface PHY SMSC LAN 8710i EFC Interface EFC Interface oo oo gt amp i MX35 z im MER pope Su INTERRUPT3 gt 20108 EU INTERRUPT 2 P 20104 INTERRUPT1 INTERRUPTO gt 2202 GPIO1 7 mreRRUPr MDINT MDINT Figure 4 TX IMX35 Real Time Ethernet interface RX TX EXM 32 Module Connector Figure 4 and figure 5 show simplified wiring schemes of the MAC PHY interface MDINT is standard interrupt and interrupt 0 5 are Real time IEEE 1588 interrupts GPIOs 15 EXM32 EXM IMX35 CPU Module User s Manual Pad Name Mode Instance Port Pad setting
28. DA L 14 X1D A15 A15 ALTO EMI DA 115 X1D A16 A16 ALTO EMI EMI DA L 16 X1D A17 A17 ALTO EMI DA 1 17 X1D A18 A18 ALTO EMI EMI DA L 18 X1D A19 A19 ALTO EMI DA 1 19 X1D A20 A20 ALTO EMI EMI DA L 20 X1D A21 A21 ALTO EMI DA 1121 X1D A22 A22 ALTO EMI EMI DA L 22 X1D A23 A23 ALTO EMI DA 11231 X1D A24 A24 ALTO EMI DA 1124 X1D A25 A25 ALTO EMI DA L 25 CLKO ALTO CCM CLKO X1B BUSCLK 32 EXM32 EXM IMX35 CPU Module User s Manual EBO ALTO EMI EBO X1B BEO EB1 ALTO 1 1 _ 1 ALTO X1B CS0 ALTO 50 i NOR_FLASH_CS0 CS1 ALTO EMI CS1 X1B CSA CS2 ALTO EMI EMI CS2 DDR CSO CS3 ALTO CS3 E DDR CS1 CS4 ALTO EMI EMI CS4 5 CS5 ALTO EMI EMI CS5 LBA ALTO EMI LBA 5 RW ALTO EMI RW X1B_R W TXO ALT3 EMI X1B_RDY X1A_CF_WAIT COMPARE ALT7 SDMA 2 X1D_DREQO GPIO1_1 ALT7 SDMA EXTDMA_1 X1D_DREQ1 Table 33 IMX35 Local Bus I O multiplexing 3 3 Local Bus External Timing Definition Figure 9 External Bus Timing definitions Definition Description Time in ns Read or Write Cycle 150 Chip select Assertion Time 106 Tc
29. DO Figure 6 IMX35 Compact Flash interface Only address bits A0 A9 are used for the Compact Flash interface in DTACK mode Card Detect and READY or IRQ signals connected to GPIOs Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 CS4 ALTO EMI 54 TXO ALT3 EMI 22K UP TX1 ALT5 GPIO1 GPIO1 14 22K UP X1A_CF1_CD TX2_RX3 ALT5 GPIO1 GPIO1 13 22K UP X1A_CFO_CD ATA DAO ALT5 GPIO3 GPIO3 0 22K UP RDY IRQ TXD2 ALT5 GPIO3 1 1 22K UP CF1 RDY IRQ Table 19 IMX35 Compact Flash I O multiplexing pin out 21 EXM32 EXM IMX35 CPU Module User s Manual Slot Operation Mode Chip select Base Address Slot 1 PC Card Memory Mode 54 0 4000800 Slot 1 PC Card I O Mode CS4 0xB4000800 Slot 2 PC Card Memory Mode 54 0 4002800 Slot 2 PC Card I O Mode CS4 0xB4002800 Table 20 Compact Flash operation modes Address bus A11 is used to decode Memory Mode or I O Mode cycles Slot PC Card Memory Mode Chip select Base Address Slot 1 Common Memory Mode CS4 0 4000000 Slot 1 Attribute Mode 54 0xB4001000 Slot 2 Common Memory CS4 0xB4002000 Slot 2 Attribute Mode CS4 0xB4003000 Table 21 Compact Flash PC Card Memory Mode sub operations For reliable operation of the CF Interface the memory c
30. EXM32 EXM IMX35 CPU Module User s Manual Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings USB HUB 35 USBPHY1 ALTO USBPHY UTMI USBPHY1 DP USBUP USBPHY1 DM ALTO USBPHY UTMI USBPHY1 DM USBUP_D USBOTG ALTO USBPHY USBOTG 22K UP X2A USB 2 2 DAT ALTO2 USB TOP USBH2 OC 22K UP X2A USB Table 17 IMX35 High Speed USB interface with HUB USBOTG 2 2 DAT must always be configured as input USBOTG PWhR Pull Down 1262 Pull Up as output 20 EXM32 EXM IMX35 CPU Module User s Manual 2 1 16 Compact Flash The CF interface implemented on the EXM32 IMX35 module supports only PC Card Memory Mode and PC Card I O Mode while True IDE Mode is not supported The various operational modes are implemented by address decoding For detailed information please refer to the Compact Flash Specification Compact Flash CTRL SIGNALS EXM 32 Module Connector Slot Chip select Base address Slot 1 CS4 0xB4000000 Slot 2 CS4 0xB4000000 Table 18 Compact Flash address space CARD DETECT SLOT 1 1 lt CARD DETECT SLOT 0 READY IRQ SLOT 1 __ C P LD1 lt READY IRQ SLOT 0 54 p gt TXO DTACK DTACK i i MX35 ADD BUS A9 A0 DAT BUS D15
31. O2 GPIO2 27 22K UP X2D_SDIO_CD STXFS4 ALT5 GPIO2 GPIO2 31 22K UP X2D SDIO WP Table 5 SD MMC Card IMX35 I O multiplexing pin out 13 EXM32 EXM IMX35 CPU Module User s Manual 2 1 8 Linear NOR Flash Up to 128MByte NOR Flash can be populated on the module in one device connected to 50 Therefore the NOR Flash can be used as boot device Hardware write protection for Linear Flash Memory is not supported Pad Name Mode Instance Port Pad settings Function IMX35 IMX35 IMX35 IMX35 NOR FLASH 00 015 ALTO EMI EMI DQ 0 DQ 15 0 25 ALTO EMI EMI A n 0 25 50 ALTO EMI EMI CSO CE RW ALTO EMI EMI RW WE OE ALTO EMI EMI OE TXO ALT3 EMI DTACK_B CPLD RDY Table 6 Linear Flash IMX35 I O multiplexing pin out For a detailed description of the memory space mapping please refer to chapter 3 off chip Memory 2 1 9 NAND Flash The EXM32 IMX35 CPU module can be populated with an 8 Bit NAND Flash For detailed information please refer the IMX35 Processor Reference Manuel Pad Name Mode Instance Port Pad settings Function 5 IMX35 IMX35 IMX35 NAND FLASH 00 08 ALTO EMI IO0 IO 15 CEO ALTO EMI NANDF CE NFALE ALTO EMI NANDF ALE ALE NFCLE ALTO EMI NANDF CLE CLE NFRE B ALTO EMI NANDF RE RE NFWE B ALTO EMI NANDF WE WE NFRB ALTO EMI NANDF RB R
32. S5 ALT5 GPIO1 GPIO 3 SCKR ALTO ESAI SCKR N C FSR ALTO ESAI FSR N C HCKR ALT5 GPIO1 GPIO 6 SCKT ALT5 GPIO1 GPIO 7 FST ALT5 GPIO1 GPIO 8 HCKT ALT5 GPIO1 GPIO 9 TX5 RXO ALT5 GPIO1 GPIO 10 TX4_RX1 ALT5 GPIO1 GPIO 11 TX3 RX2 ALT5 GPIO1 GPIO 12 TX2 RX3 ALT5 GPIO1 GPIO 13 TX1 ALT5 GPIO1 GPIO 14 TXO ALT5 GPIO1 GPIO 15 MOSI ALT5 GPIO1 GPIO 17 CSPI1_MISO ALT5 GPIO1 GPIO 17 CSPM 550 ALT5 GPIO1 GPIO 18 CSPM 881 ALT5 GPIO1 GPIO 17 CSPM SCLK ALT5 GPIO3 GPIO 4 CSPM SPI RDY ALT5 GPIO3 GPIO 5 RXD1 ALTO UART1 RXD_MUX TXD1 ALTO UART1 TXD_MUX RTS1 ALTO UART1 RTS CTS1 ALTO UART1 CTS RXD2 ALT5 GPIO3 GPIO 10 TXD2 ALT5 GPIO3 GPIO 11 RTS2 ALT2 CTS2 ALT2 USBPHY1_VBUS ALTO USBPHY UTMI USBPHY1 VBUS USBPHY1 DP ALTO USBPHY UTMI USBPHY1 USBPHY1 DM ALTO USBPHY UTMI USBPHY1 DM USBPHY1 UID ALTO USBPHY UTMI USBPHY1 UID USBPHY2 DM ALTO USBXCVR USBPHY2 DM USBPHY2 DP ALTO USBXCVR USBPHY2 DP USBOTG PWR ALTO USB TOP USBOTG PWR USBOTG OC ALTO USB TOP USBOTG OC LDO ALT5 GPIO2 GPIO 0 LD1 ALT5 GPIO2 GPIO 1 LD2 ALTO IPU DISPB DAT 2 LD3 ALTO IPU DISPB DAT 3 LD4 ALTO IPU DISPB DAT 4 LD5 ALTO IPU DISPB DAT 5 LD6 ALTO IPU DISPB DAT 6 LD7 ALTO IPU DISPB DAT 7 LD8 ALT5 GPIO2 GPIO 8 LD9 ALT5 GPIO2 GPIO 9 LD10 ALTO IPU DISPB DAT 10 39 EXM32 EXM IMX35 CPU Module User s Manual
33. TA13 0x08B4 GPIO2 27 0x01 ATA_DATA14 42 EXM32 EXM IMX35 CPU Module User s Manual 0x08B8 GPIO2 28 0x01 ATA DATA15 0x08BC GPIO2 29 0x01 ATA INTRQ 0 08 0 2 2 0 01 8502 ATAO 0 08 4 GPIO2 30 0x01 ATA BUFF EN 0x08C8 GPIO2 31 0x01 ATA DMARQ 0x08CC GPIO2 3 0x01 SD2 DATA1 0x08DO GPIO2 4 0x01 SD2 DATA4 0x08D4 GPIO2 5 0x01 SD2 DATA3 0x08D8 GPIO2 6 0x00 ATA 50 0x08E0 2 8 0 00 LD8 0 08 4 2 9 0 00 LD9 0x08E8 0 0 00 0 0x08EC GPIO3 10 0 00 RXD2 0x08F0 GPIO3_11 0x00 TXD2 0x0904 GPIO3_4 0x00 CSPI1_SCLK 0x0908 GPIO3_5 0x00 CSPI1 SPI RDY 0x091C Il2C3 SCL 0x10 SD2 CMD 0x0920 2 3 SDA 0x10 SD2 CLK 0x099C UART3 RTS 0x01 ATA DATA8 0x09A0 UART3_RXD 0x10 ATA_DATA10 0x09F4 USBH2 OC 0x00 2 DATA Table 43 Daisy Chain Register 43 EXM32 EXM IMX35 CPU Module User s Manual End of Document 44
34. User s Manual MSC EXM32 IMX35 CPU Module Rev 1 1 boards msc ge com www msc ge com boards EXM32 EXM IMX35 CPU Module User s Manual Document change history Date Version Document change description 2009 08 28 0 1 initial release Hardware Rev 2 0 2010 06 2 11 0 Hardware Rev 3 0 amp Hardware Rev 4 0 2010 12 17 1 1 Various Updates amp Corrections EXM32 EXM IMX35 CPU Module User s Manual Preface Copyright Notice Copyright 2008 MSC Vertriebs GmbH All rights reserved Copying of this document and giving it to others and the use or communication of the contents thereof are forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Important Information This documentation is intended for qualified audience only The product described herein is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure a
35. ame Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 USBPHY1 VBUS ALTO USBPHY UTMI USBPHY1 VBUS X2A USB OTG VBUS USBPHY1 DP ALTO USBPHY UTMI USBPHY1 DP X2A USB OTG D USBPHY1 DM ALTO USBPHY UTMI USBPHY1 DM X2A USB OTG D USBPHY1 UID ALTO USBPHY UTMI USBPHY1 UID X2A USB OTG ID USBOTG PWR ALTO USBPHY UTMI USBOTG PWR 100K DN X2A USB OTG PWEN l2C2 ALT2 USB TOP USBH2 PWR 100K DN X2A USB MB PWEN USBPHY2 DM ALTO USBPHY UTMI USBXCVR X2A USB MB D USBPHY2 DP ALTO USBPHY UTMI USBXCVR X2A USB MB USBOTG OC ALTO USBPHY UTMI USBOTG OC 22K UP X2A USB OC l2C2 DAT ALT2 USB TOP USBH2 OC 22K UP X2A USB Table 15 IMX35 Full Speed USB High Speed no HUB OTG I O multiplexing pin out Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 USBPHY1 VBUS ALTO USBPHY UTMI USBPHY1 VBUS X2A USB OTG VBUS USBPHY1 DP ALTO USBPHY UTMI USBPHY1 DP X2A USB OTG D USBPHY1 DM ALTO USBPHY UTMI USBPHY1 DM X2A USB OTG D USBPHY1 UID ALTO USBPHY UTMI USBPHY1 UID X2A USB OTG ID USBOTG PWR ALTO USBPHY UTMI USBOTG PWR 100K DN X2A USB OTG PWEN USBPHY2 DM ALTO USBPHY UTMI USBXCVR X2A USB MB D USBPHY2 DP ALTO USBPHY UTMI USBXCVR X2A USB MB USBOTG OC ALTO USBPHY UTMI USBOTG OC 22K UP X2A USB OC l2C2 DAT ALTO2 USB TOP USBH2 OC 22K UP X2A USB OC Table 16 IMX35 Full Speed USB High Speed OTG with HUB I O multiplexing pin out 19
36. ds EXM32 EXM IMX35 CPU Module User s Manual 11 Functional Blocks The 32 IMX35 ARM 11 CPU Module includes the following functional blocks CPU IMX35 ARM11 CPU 532 MHz main clock AHB Bus with maximum 133MHz clock with Vector Floating Point Unit 32 KB Boot ROM 128 SRAM and 2 KB Secure Ram Peripherals Camera Interface 8 Bit PCMCIA CF Interface Ethernet 10 100Mbit s Mac with external IEEE1588 PHY or standard PHY Cortina LXT971A Single Port Flex Can 2x Controller 12 2x SPI MLB 3 wire Media Local Bus 97 25 Sound Interface RTC SD MMC Secure Digital Memory Card Multimedia Card LCD USB High Speed USB OTG and Full Speed USB Host Memory onboard Up to 256 Mbyte DDR2 Memory 32bit Data bus width 133MHz Up to 128 Mbyte linear Flash NOR Flash with 16 Bit bus width Optional NAND Flash Memory up to 1GByte 8 bit Bus Local Bus 16 Bit CPU bus for SRAM or VLIO type peripherals with Data acknowledge logic available on module connector Buffer is 3 3V tolerant Connectors Two 2 Connectors carry all interfaces the system CPU bus and the power supply A Debug connector allows the connection of a JTAG based debug tool EXM32 EXM IMX35 CPU Module User s Manual 1 2 EXM32 i MX35 available Signals X1 A MB CPU X1
37. e oer eerie 13 2 1 8 Einear NOB Flash eir Mene eerte eter e Repone etter es 14 2 19 terere e ebore bue 14 244103 eec eeu ER ere e te petu aa ong etes 15 2 T1 T1 CO ANIBUS tete tire rer Ld rrr 16 2 1 12 Audio Codec Interface 97 28 17 2 1 43 Interfaces COMO 18 2 4 14 Media Local Bus MLB iE Rr De etra 18 ZEIT 18 21 16 Compa tE AS Mies nori rv 21 2 1 17 Graphics Controllers Ee ei 23 2 1 18 IPU CSI CAMERA SENSOR INTERFACE tenere 25 PANO tato 26 2 1 20 DDR2 SDRAM repe LE MILI D 28 Be GUIG C56 31 3 1 Peripheral Memory entren 31 3 2 Off chip Memory eite na ee 31 3 3 Local Bus External Timing 33 3 3 1 Area 0 Nor Flash aee ee eee eee eee eec ete dete e ee eec a 35 OPEP C mm 35 3 33 ANCA 2 ese euer 35 33 14 AP082896 2 eee edi ee tede techn E ere E ee e ee 35 CRIME Em 36 MC MEE Cmm 36 3 3 7 Area 0 DDR Mem
38. nd used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her own expense Trademarks All used product names logos or trademarks are property of their respective owners Certification MSC Vertriebs GmbH is certified according to DIN EN ISO 9001 2000 standards Life Cycle Management MSC products are developed and manufactured according to high quality standards Our life cycle management assures long term availability through permanent product maintenance Technically necessary changes and improvements are introduced if applicable A product change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Vertriebs GmbH please consult the respective pages on our web site at www msc ge com support boards for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Technical Support Email support boards msc ge com Phone 49 8165 906 200 EXM32 EXM IMX35 CPU Module User s Manual Content Document change history cies u annaba 8 Ue Mate
39. ontroller must be configured as follows Description CSA TBD OEA TBD LBA TBD DCT TBD EDC TBD Table 22 CS5 not available 22 IMX35 CS4 and CS5 Compact Flash Timings EXM32 EXM IMX35 CPU Module User s Manual 2 1 17 Graphics Controller The LCD controller signals are routed directly to the EXM connector Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 LDO ALTO IPU X2D LCD BO LD1 ALTO IPU D n X2D LCD B1 LD2 ALTO IPU X2C LCD B2 LD3 ALTO IPU D n X2C LCD B3 LD4 ALTO IPU IPU_D n X2C LCD B4 LD5 ALTO IPU D n X2C LCD B5 LD6 ALTO IPU X2C LCD B6 LD7 ALTO IPU D n X2C LCD B7 LD8 ALTO IPU X2D LCD GO LD9 ALTO IPU D n X2D LCD G1 LD10 ALTO IPU IPU_D n X2C LCD Ge LD11 ALTO IPU X2C LCD G3 LD12 ALTO IPU X2C LCD G4 LD13 ALTO IPU X2C LCD G5 LD14 ALTO IPU X2C LCD G6 LD15 ALTO IPU X2C LCD G7 LD16 ALTO IPU X2D LCD RO LD17 ALTO IPU X2D LCD R1 LD18 ALTO IPU IPU_D n 2 X2C LCD R2 LD19 ALTO IPU X2C LCD LD20 ALTO IPU X2C LCD R4 LD21 ALTO IPU D n X2C LCD R5 LD22 ALTO IPU
40. ory 0 37 3 3 8 Area 1 DDR Memory 1 37 4 Pin M ltiplexihg inicie eee er erede reete e ee pete etu arm dere enr 38 4 1 1 5 QUE EDS UE EH 38 41 2 Daisy Chain Bit iti ee rotta et deters bet RETE 42 EXM32 EXM IMX35 CPU Module User s Manual 1 Blockdiagram 0 24 3 3V I 0 25 1 8 2 0 A0 A24 b 2432 9 COMPACTFLASH LBSC C ONTROL lt m 1255 97 FlexCAN1 4 m 125 4 97 FlexCANO gt gt SDIO MMC UARTI gt UART AHB L US USB Host USB OTG Full Speed High Speed Camera CSI PHY PHY CSI BOOT PINS Figure 1 EXM 32 IMX35 CPU Module The highly integrated IMX35 microprocessors possesses various interfaces except of CompactFlash The Compact Flash interface is implemented in a CPLD which adapts the CPU timing to the Compact Flash specification The DDR Memory Controller and the Local Bus share the lower address lines 0 12 except of A10 The access decoding for the Local Bus is also implemented in the CPLD The entire Local Bus is buffered in order to decouple the module from the baseboard and to facilitate baseboard designs so further buffering level converting etc is not needed Motherboar
41. s Function IMX35 5 5 5 FEC TX ALTO FEC TX CLK PHY TX CLK FEC RX CLK ALTO FEC RX CLK PHY RX CLK DV ALTO FEC RX DV PHY RX DV FEC COL ALTO FEC COL PHY_COL FEC RDATAO ALTO FEC RDATA 0 PHY 0 FEC TDATAO ALTO FEC TDATA 0 PHY TD 0 FEC TX EN ALTO FEC TX EN PHY TX EN FEC MDC ALTO FEC MDC PHY MDC FEC MDIO ALTO FEC MDIO PHY MDIO FEC TX ERR ALTO FEC TX ERR PHY TX ERR FEC RX ERR ALTO FEC RX ERR PHY ERR FEC CRS ALTO FEC CRS PHY 5 FEC_RDATA1 ALTO FEC RDATA 1 PHY RD 1 FEC TDATA1 ALTO FEC TDATA 1 PHY TD 1 FEC_RDATA2 ALTO FEC RDATA 2 PHY RD 2 FEC_TDATA2 ALTO FEC TDATA 2 PHY TD 2 FEC ALTO FEC FEC ALTO FEC TDATA S PHY TD S Table 8 Ethernet IMX35 I O multiplexing pin out 2 1 11 CAN Bus The EXM IMX35 CPU Module has got two independent CAN interfaces 0 Transceiver Enable CAN lt 1 0 gt _STB Transceiver Standby and CAN lt 1 0 gt _ERR Bus Error Flag are controlled via GPIO Tx and Rx are dedicated pins of the IMX35 microprocessor Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 IMX35 RTS2 ALT2 CAN2 RXCAN 100K UP 2 1 CTS2 ALT2 CAN2 TXCAN X2A CAN1 TX ATA 6 ALT1 2 DATA7 ALT1
42. s many functions such as calendar clock alarm timer and frequency output 1 Hz 32 Hz 1024 Hz and 32 768 kHz Bus Channel 1 on IMX35 is used to access the RTC at address offset 1010001 RTC device address 1010001x 0xA2 Table 2 RTC Address For a detailed description of the real time clock device please refer to the Seiko Epson RTC8564NB Application Manual 11 EXM32 EXM IMX35 CPU Module User s Manual spa 2C0 SDA SO 2co SCL gt CSPI1 MOSI GPIO1 16 lt IRQ lt BAT M RTC vec S lt a o 5 3 i MX35 8 N gt Figure 1 5 and Real Time Clock 2 1 5 SPI Interface The EXM32 IMX35 CPU Module features one SPI interface The interface supports up to two devices via slave select logic SPI 2 interface of the IMX35 microprocessor is used to provide the interface Pad Name Mode Instance Port Pad settings Function IMX35 IMX35 IMX35 5 32 SRXD5 ALT2 CSPI2 MISO 22K UP X1A SPI MISO ATA DIOW ALT4 CSPI2 MOSI X1A SPI MOSI ATA DATA3 ALT4 CSPI2 SCLK X1A SPI SCK ATA DIOR ALT4 CSPI2 SS1 22K UP X1A SPI 551 ATA CS1 ALT4 CSPI2 550 22 X1A SPI 550 Table 3 SPI IMX35 I O multiplexing pin out 2 1 6 PCinterface The EXM32 IMX35 CPU Module supports I C Busses 2 1 and 1263 interfaces of the IMX35 are used for EXM32 2 0 1 The IMX35 2 interface s
43. sh Chip select Deassertion Time 44 Tcsdv Chip select Valid Tasu Address Setup Time 22 Tah Address Hold Time 8 Tdoh Data Hold Time 34 33 EXM32 EXM IMX35 CPU Module User s Manual Table 34 Bus Timing Definitions HCLK tae BCLK WW NW 2 f Lm Ci ADDR 2 2 ll x LBA LBN 7 LBA Pete fy D MH ZZ AKI Ret A P p ud OE DTACK Pai Figure 10 IMX35 Internal Bus Timing Figure 10 shows the bus timing of the IMX35 CPU on the module The bus timing parameters must be configured for each CS signal BCLK is alyways half of AHB Clock HCLK Time in ns CSA CSN 24 24 OEA OEN 46 22 LBA DCT 46 EDC 15 Data Setup 34 Table 35 IMX35 WEIM Timing Configuration Register Bits 34 EXM32 EXM IMX35 CPU Module User s Manual 3 3 1 Area 0 Nor Flash Area 0 50 addresses up to 128MByte NOR Flash The 50 address space is mapped to 0xA0000000 to OxA7FFFFFF Description CSA OEA LBA DCT EDC Table 36 Chip Select 0 Timings WEIM control registers for Area 0 defaul
44. t values please refer Datasheet 3 3 2 Area 1 Area 1 CS1 is reserved for EXM32 Motherboards Local Bus select X1B_CSA mapped to 0xA800 0000 OxAFFF FFFF Description CSA 6 OEA C LBA 0 DCT 0 EDC 2 Table 37 Chip Select 1 Timings WEIM control registers for Area 1 0xB8002010 gt Ox3F02 0xB8002014 gt 6561 0xB8002018 gt 1000 3 3 3 Area 2 CS2 50 for DDR Memory 3 3 4 Area3 CS3 CS1 for DDR Memory 35 EXM32 EXM IMX35 CPU Module User s Manual 3 3 5 Area 4 CS4 Compact Flash Slot 0 0xB4000000 to OxB5FFFFFF Description CSA 5 OEA F LBA 2 DCT 3 EDC 0 Table 38 Chip Select 4 Compact Flash Timings WEIM control registers for Area 4 0xB8002040 gt Ox3F00 0xB8002044 gt OxFA005551 0xB8002048 gt 0x22FA0A30 3 3 6 Area 5 This Area is no longer available CS5 Compact Flash Slot 0XB6000000 to 0xB7FFFFFF Description CSA OEA LBA DCT EDC Table 39 Chip Select 5 Compact Flash Timings 36 EXM32 EXM IMX35 CPU Module User s Manual 3 3 7 Area 0 DDR Memory Bank 0 DDR Memory 50 0x80000000 Ox8FFFFFFF The following memory bus timings are needed for reliable system operation ESDCFGO Address 0xB8001004 BIT 31 30 29
45. to output the Local Bus clock signal 2 AHB Clock 2 31 EXM32 EXM IMX35 CPU Module User s Manual Pad Name Mode Instance Port Pad Function IMX35 IMX35 IMX35 settings EXM 32 5 ALTO EMI D 0 X1B DO D1 ALTO EMI EMI D 1 X1B D1 D2 ALTO EMI D 2 X1B D2 D3 ALTO EMI D3 4 ALTO EMI D 4 X1B D4 D5 ALTO EMI EMI D 5 X1B D5 D6 ALTO EMI D 6 X1B D6 D7 ALTO EMI EMI D 7 X1B D7 D8 ALTO EMI D 8 X1B D8 D9 ALTO EMI EMI D 9 X1B D9 D10 ALTO EMI D 10 X1B D10 D11 ALTO EMI EMI D 1 1 X1B D11 D12 ALTO EMI D 12 X1B D12 D13 ALTO EMI EMI D 13 X1B D13 D14 ALTO EMI D 14 X1B D14 D15 ALTO EMI EMI D 15 X1B D15 ALTO EMI DA X1D A1 A1 ALTO EMI EMI DA X1D A2 A2 ALTO EMI DA 1 2 X1D A3 ALTO EMI EMI DA X1D A4 4 ALTO EMI DA 114 X1D A5 A5 ALTO EMI EMI DA L 5 X1D A6 A6 ALTO EMI EMI DA X1D A7 A7 ALTO EMI EMI DA X1D A8 A8 ALTO EMI EMI DA X1D A9 A9 ALTO EMI DA X1D A10 A10 ALTO EMI EMI DA L 10 X1D A11 A11 ALTO EMI EMI DA 1 11 X1D A12 A12 ALTO EMI EMI DA L 12 X1D A13 A13 ALTO EMI DA 11131 X1D A14 A14 ALTO EMI EMI
46. upports transfer rates of 100 Kbits s and 400 Kbits s Pad Name Instance Pad settings Function IMX35 IMX35 IMX35 EXM 32 CLK ALTO X2C 12 0 SCL 201 DAT ALTO 2 2C0 SDA SD2 CLK 2 201 SDA SD2 CMD 2C1 SCL Table 4 2 IMX35 I O multiplexing pin out 12 EXM32 EXM IMX35 CPU Module User s Manual 2 1 7 MMC SD SDIO Multi Media Card MMC Secure Digital Memory Card SD Secure Digital Input Output Card SDIO The EXM32 IMX35 CPU Module supports an SD SDIO MMC I O Card interface using the IMX35 eSDHC controller The interface supports both write protection and card detection using IMX35 GPIOs SD DATAS3 SD DATA2 SD DATA1 SD DATAO Y v v v SD CMD SD CLK d i MX35 GPIO1 4 SD CARD DETECT v E XM 32 Module Connector GPIO2 14 lt SD WRITE PROTECTION Figure 2 IMX35 SD interface A falling edge interrupt indicates a card insertion GPIO2 14 senses the Card Write Protection switch Pad Name Mode Instance Port Pad settings Function IMX35 IMX35 IMX35 IMX35 EXM 32 SD1 CMD ALTO ESDHC1 CMD X2D SDIO CMD SD1 CLK ALTO ESDHC1 CLK X2D SDIO CLK SD1 DATAO ALTO ESDHC1 DATO X2D SDIO DATO 8501 1 ALTO ESDHC1 DAT1 X2D SDIO SD1 DATA2 ALTO ESDHC1 DAT2 X2D SDIO DAT2 SD1 ALTO ESDHC1 X2D SDIO DAT3 DATA14 ALT5 GPI
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