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1. Notes 1 All settings from the factory are external 2 This example shows two internal and two external clock jumper settings 3 You must also set the distribution panel jumpers to match these settings FigureA 1 16 port 232 Clock Jumper Settings DC 900 0408E 85 ICP6000 X ICP 9000 X ardware Description and Theory of Operation 2 Z85C30 285230 Serial Communications Controller EIM D has eight Z85C 30 ICP6000 ICP9000 or 285230 ICP6000X ICP9000X serial communications controllers SCCs Each SCC implements two communications ports A 2 1 SCC Register Access Access to the SCC data and command registers is made using the addresses shown in Table5 10n page 51 H ardware protection is provided so that the SCC writerecovery limits are automatically met A 2 2 SCC Timebase The SCCs are driven from a 7 3728 MHz ICP6000 ICP9000 or 14 7456 MHz ICP6000X I CP9000X peripheral clock signal PCLK A 2 3 SCC DMA Each communications port is assigned two DMA channels one for transmitting and the other for receiving Section 5 8 on page 58 describes the setup and operation of the DMA controller A 3 Modem Control EIMD supports five modem control signals three inputs Data Set Ready Clear To Send and Data Carrier Detect and two outputs Data Terminal Ready and Request To Send These modem controls are connected to either the SCC or to a dedicated hard ware re
2. 5 9 1 VM Ebus Slave Address Decoder 5 9 2 VMEbus Mailboxes and SoftwareReset 5 9 3 Mailbox Slave Address Decoder 5 9 4 ConfiguringtheMailboxInterrupts 595 uus BAe eee EER OE ERR 5 10 Lu n gov eee EGRE ES 5 11 VMEbus Master 5 12 Operating Controls and Indicators 5 121 Fault Indicator ouod uou adore 5 122 VO DMA Ge a aida 5 12 3 VME Access Indicator hide 5 13 Serial EEPROM Operation DC 900 0408E Contents 5 14 Board Select SHIRES d od oed Ro E RR POR HS Rok EXC 12 6 Diagnostics 73 Bl Tess sena oak bake ROO we BSH OD wo 13 611 ROM Checksum 73 612 73 6 1 3 68901 Multi function Peripheral 74 614 VMEbus Slave Interface VSI 74 Lu she kw EGER X 74 616 DMA Controle uu eek ee wd Bow RR Owe oko OR 3d 75 7 BootLoad Procedure 77 7 1 Download M essage Format v ossa rd RO XO eee es 77 72 78 A 16 port EIA 232 Electrical Interface Module 83 AJ Modem lt 83 11 5 83 Bi
3. T Port5 E R R R R N 12 4 N Por2 N 12 7 N Port 6 A O O A L 9 bota 2 0 L Port7 O O O O Ne 4 7 lt gt A J 2 Lo y I 7 i dX 4 J 4 4 4 7 Lf y 7 80 pin yo nnector Daughterboard J VMEbus 7 Connectors d 2 P4 Vi 2 Ny Ld 7 Console Port Jj DRWG 2225 Notes 1 All settings from the factory are external 2 This example shows two internal and two external clock jumper settings FigureC 1 8 port V 35 Clock Jumper Settings DC 900 0408E 105 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation C 2 2 SCC Timebase The SCCs are driven from a 7 3728 MHz ICP6000 ICP9000 or 14 7456 MHz ICP6000X I CP9000X peripheral clock signal PCLK C 2 3 SCC DMA Each communications port is assigned two channels one for transmitting and the other for receiving Section 5 8 on page 58 describes the setup and operation of the DMA controller C 3 Driver Supply Voltages EIGH is equipped with TO 92 three terminal regulators to reduce the available 124 to 5V as required by the V 35 differential drivers and receivers 4 Single ended Interface EIGH is equipped with 14C88 single ended line drivers that feature internal slew rate control as required by theV 35 specification EIGH is also equipped with 14C89 si
4. ICP6000 X ICP9000 X Width 234 mm 9 2 in 368mm 14 5 in Depth 160 mm 6 3 in 403 mm 15 9 in Front Panel 20 3 mm 0 8 in 20 3 mm 0 8 in 4 1 2 Power Requirements 5V dc 5 5 0 amps typical 6 0 amps maximum 12V dc 5 0 15 amps maximum 12V dc 5 0 15 amps maximum DC 900 0408E 45 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation The host power supply must meet these requirements Be sure to consider the needs of all devices that are serviced by the power supply Consider both total current for each voltage source and total power 4 1 3 Environment Several environmental factors should be considered to ensure reliable operation of the ICP and its host system The room air conditioning system should provide cool filtered humidified air Tem perature should be held as stable as possible to prevent thermal related failures Low humidity contributes to static electricity which can cause catastrophic failures The allowable temperature and humidity ranges are as follows Temperature 0 to 55 C operating 55 to 85 C non operating Humidity 1096 to 9096 non condensing Recommended operating conditions are 20 degrees Centigrade 70 degrees Fahrenheit and 45 percent relative humidity 4 2 DeviceSpecifications Table 4 1 lists the specifications for the devices on the base board 46 DC 900 0408E 4 Hardware Specifications Table 4 1 Specifications for ICP Devi
5. bus but the Software Reset Register is not See Table 5 1 for mailbox addresses on the local processor bus Because setup of the VSI requires multiple operations it is not enabled onto the VM Ebus until all setup operations are complete 5 9 3 Mailbox SlaveAddress D ecoder The following example sets up the mailboxes at a VM Ebus address of OxFE000000 in Extended Supervisor or User space A similar procedure is performed by PROM resident boot loader according to the EEPROM configuration parameters see Section 2 6 1 on page 28 This is shown for your information only user application code does not normally program the mailbox slave address decoder 1 Load bits 31 24 OxFE of thedesired addressinto theV 51 SlaveAddress Compare Register A31 A24 2 Similarly load bits 23 16 0x00 into the VSI Slave Address Compare Register A23 A16 and bits 15 9 0x00 into the VSI Slave Address Compare Register A15 A09 3 The Extended Supervisor User Address space requires that Address M odifier Bits 2 0 be decoded don t care and that Address M odifier bits 5 3 be compared to 001 To accomplish this the VSI Slave Address Modifier Compare Register is loaded with 0x08 and the VSI Slave Address Modifier Don t Care Register is loaded with 0x07 5 9 4 Configuring the Mailbox Interrupts In this example the mailbox interrupts are set so that LIRQ2 autovector 1 is activated when mailbox 0 is written by the VM Ebus LIRQO autovector 3
6. BIA Deas Ready ROO ROBUR des BL B Data Carrier Detect d B 7 4 amp B5 Request To Send B 8 Connector Pin Assignments 8 portV 35CCITT Electrical Interface Module CA MOUS og eee C Ll Receive Clock Inputs ee oon C L2 Transmit Clock Inputsand Outputs 2 Z85C30 Z85230 Serial Communications Controller C 2 1 SCC Register 5 bold SCC INE ROUES T Tr C 3 Driver Supply Voltages Singleended Interface C 5 Differential CO Moden CO acid EROR Ca dedo op e deoa C 6 1 DataSet Ready and Calling Indicator C62 Le ES C 6 3 Received Line Signal Detector C 6 4 DataTerminal Ready Local Test 6 5 5 Request To Send oua o o ns C 7 Connector Pin Assignments usu oro DC 900 0408E Contents D 8 port 422 Electrical Interface Module DL Modam Clocks ieor ach D 1 1 D 1 2 Transmit Clock Inputs Outputs D 2 Z85C30 or Z85230 Serial Communications Controller Dl SCC Register Acc
7. RR see Receiver ready RS see Request to send RTS see Request to send RxC inputs 93 S Scanner range select 61 SCC see Serial communication controller Serial communication controller 86 94 104 114 DMA 86 96 106 116 interrupts 57 register access 86 94 104 116 timebase 86 96 106 116 DC 900 0408E Serial EEPROM operation 68 Single ended interface 106 Slave address compare 29 Slave address decoder configuration 28 Slave address decoder VMEbus 62 Slave address modifier compare 31 Slave address modifier compare don t care 31 Slave interface VMEbus 60 Software reset 64 Software reset VMEbus 62 Software programmable configuration options 28 Specifications device 46 environmental 45 hardware 45 mechanical 45 Support product 15 Switches board select 72 Sysfail 70 T Technical support 15 Terminal ready 117 Tests diagnostic 73 Timers 56 TR see Terminal ready Transmit clock inputs and outputs 83 103 113 Transmit receive polarity 96 TxC inputs and outputs 93 U U 19 pinout configuration 25 U39 pinout configuration 23 U7 pinout configuration 24 U8 pinout configuration 27 Unpacking 22 V V 35 Bell 306 8 port electrical interface 103 VME access indicator 68 VM Ebus configuring master interface and interrupter 32 125 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation interrupter Interrupter VM Ebus 64 mailboxes 62 master interface 65 slave address decode
8. dB N e Protective Ground Transmitted Data TxD Received Data TxD Request to Send RTS Clear to Send CTS Data Set Ready DSR Signal Ground Common Return GND Received LineSignal Detector DCD DRWG 2564 FigureA 5 EIA 232 Interface DC 900 0408 89 ICP6000 X ICP9000 X ardware Description and Theory of Operation TableA 2 Pin Assignments for 16 port EIA 232 Cable Connectors 80 pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal 1 8 1 00 GND 41 9 04 GND 2 8 2 00 TXD A 42 J9 2 04 TXD A 3 8 3 00 RTS A 43 J9 3 04 RTS A 4 8 4 00 RXD A 44 J9 4 04 RXD A 5 J8 5 00 CTS A 45 J9 5 04 CTS A 6 J8 6 00 DCD A 46 J9 6 04 DCD A 7 Je 7 00 DTR A 47 J9 7 04 DTR A 8 Je 8 00 RXC A 48 J9 8 04 RXC A 9 Je 9 00 DSR A 49 J9 9 04 DSR A 10 J8 10 00 TXC A 50 J9 10 04 TXC 11 8 11 01 GND A 51 J9 11 05 GND A 12 8 12 01 TXD A 52 J9 12 05 TXD A 13 J8 13 01 RTS A 53 J9 13 05 RTS A 14 8 14 01 RXD A 54 J9 14 05 RXD A 15 8 15 01 5 55 J9 15 05 CTS A 16 J8 16 01 DCD A 56 J9 16 05 DCD A 17 8 17 01 DTR 57 J9 17 05 DTR A 18 8 18 01 RXC A 58 J9 18 05 RXC A 19 8 19 01 DSR A 59 J9 19 05 DSR A 20 J8 20 01 TXC A 60 J9 20 05 TXC A 21 8 21 02 GND A 61 J9 21 06 GND A 22 8 22 02 TXD A 62 J9 22 06 TXD A 23 J8 23 02 RTS A 63 J9 23 06 RTS A 24 8 24 02 RXD A 64 J9 24 06 RXD A 25 J8 25 02 CTS A 65 J9 25 06 CTS A 26 J8 26 02 DCD A 66 J9 26 06 DCD A
9. 110 DC 900 0408E C 8 port V 35 CCITT Electrical Interface M odule TableC 2 Pin Assignments for 8 port V 35 Cable Connectors Cont d 80 pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal B 1 J amp T 04 GND B 41 9 1 06 GND B 2 8 2 04 GND B 42 J9 2 06 GND B 3 8 3 04 GND B 43 9 3 06 GND B 4 8 4 04 CTS B 44 J9 4 06 CTS B 5 J8 5 04 RLSD B 45 9 5 06 RLSD B 6 8 6 04 DSR B 46 9 6 06 DSR B 7 J87 04 CI B 47 J9 7 06 CI B 8 8 8 04 RTS B 48 9 8 06 RTS B 9 8 9 04 LT B 49 J9 9 06 LT B 10 J8 10 04 DTR B 50 J9 10 06 DTR B 11 18 11 04 SD A B 51 J9 11 06 SD A B 12 18 12 04 SD B B 52 J9 12 06 SD B B 13 J8 13 04 RD A B 53 J9 13 06 RD A B 14 8 14 04 RD B B 54 J9 14 06 RD B B 15 J8 15 04 SCR A B 55 J9 15 06 SCR A B 16 J8 16 04 SCR B B 56 9 16 06 SCR B B 17 18 17 04 SCTE A B 57 J9 17 06 SCTE A B 18 J8 18 04 SCTE B B 58 J9 18 06 SCTE B B 19 8 19 04 SCT A B 59 9 19 06 SCT A B 20 J8 20 04 SCT B B 60 J9 20 06 SCT B B 21 18 21 05 GND B 61 J9 21 07 GND B 22 J822 05 GND B 62 9 22 07 GND B 23 J8 23 05 GND B 63 J9 23 07 GND B 24 8 24 05 CTS B 64 9 24 07 CTS B 25 J8 25 05 RLSD B 65 J9 25 07 RLSD B 26 J8 26 05 DSR B 66 J9 26 07 DSR B 27 8 27 05 CI B 67 9 27 07 CI B 28 J8 28 05 RTS B 68 J9 28 07 RTS B 29 J8 29 05 LT B 69 J9 29 07 LT B 30 8 30 05 DTR B 70 9 30 07 DT B 31 8 31 05 SD A B 71 9 31 07 SD A B 32 8 32 05 SD B B 72 9 32 07 SD B B 33 8 33 05 RD A B 73 9
10. 3000001F VSI Mode Selection Register 40000000 40xFFEFF 40xFFF00 40xFFF3F 4OxF FF40 40xF FF 7F 40xF FF80 40xFFFBF 4OxF FFCO 40xF FFFF 60000000 60000001 60000002 60000003 60000004 60000005 60000006 60000007 60000008 60000009 6000000A 6000000B 6000000C Dynamic RAM read write longword wide Ports 0 15 Receive DM A M emory Address Register M AR read write longword wide Ports 0 15 Transmit DM A MAR read write longword wide Ports 0 15 Receive DM A Terminal Count Register TCR read write longword wide Ports 0 15 Transmit DM A TCR read write longword wide EIM SCC Port 0 Data read write byte wide EIM SCC Port 0 Control EIM SCC Port 1 Data EIM SCC Port 1 Control EIM SCC Port 2 Data EIM SCC Port 2 Control EIM SCC Port 3 Data EIM SCC Port 3 Control EIM SCC Port 4 Data EIM SCC Port 4 Control EIM SCC Port 5 Data EIM SCC Port 5 Control EIM SCC Port 6 Data DC 900 0408 53 ICP6000 X ICP9000 X Hardware Description and Theory of Operation Table5 1 General M emory M ap Cont d Memory Range hex Device 6000000D EIM SCC Port 6 Control 6000000E EIM SCC Port 7 Data 6000000F EIM SCC Port 7 Control 60000010 EIM SCC Port 8 Data 60000011 EIM SCC Port 8 Control 60000012 EIM SCC Port 9 Data 60000013 EIM SCC Port 9 Control 60000014 EIM SCC Port 10 Data 60000015 EIM SCC Port 10 Control 60000016 EIM SCC Port 11 Data 60000017 EIM SCC Port 11 Control 6000001
11. M s Validate load address move block from host mE ACK 88 Download request For last block store host buffer address load address and byte count in PXR Wears BIOGR Validate load address move block from host ACK ME Download request Store execution address in PXR Init procedure gt Validate address 8 ACK Subroutine call to execution address Run time system is initialized and boot loader does not run again until reset 0300 Figure 7 1 Typical Download Sequence DC 900 0408E 81 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 82 DC 900 0408E Appendix 16 port EI A 232 Electrical Interface Module This Electrical Interface M odule is referred to as EIM D It is a 16 port daughterboard for the base board and supports 16 port 232 operation Modem Clocks EIMD supports the full functionality of the serial communications controller SCC with respect to external and internal clock sources A 1 1 Receive Clock Inputs The Receive Clock and RxCB pins are always inputs to the SCC RxC inputs 0 15 are connected to the even numbered ports and odd numbered ports inputs of the SCCs A 1 2 Transmit Clock Inputs O utputs The Transmit Clock TxCA and TxCB pins can be programmed as either inputsto or outputs from the SCC To support this bidirectional interface EIM D is equi
12. The board select switches are located on the base board near the end of the electrical interface module the daughterboard six switches SW 1 through SW 6 Refer to Section 2 5 on page 23 for information on setting the board select switches The switch positions can be read from the Status Register as shown in Figure 5 11 Address 10000003 7 6 5 4 3 2 1 0 SW6 SW5 EEPDO DMARDY SW4 SW3 SW2 SW1 Mnemonic Name Description SW6 SW1 Board Select Switches 0 Switch on toward front pane 1 Switch off toward VM E backplane SW6 SW5 00 Go to PTBUG 0 1 Use extended space slave addressing 1 0 Use short space slave addressing 1 1 Ignore SW 3 1 and use address values currently in EE SW4 SW1 Binary encoded board number Figure 5 11 Status Register Usefor Board Select Switches 72 DC 900 0408E Chapter Diagnostics PROM contains a comprehensive hardware self test that is normally executed when the ICP is powered on or reset During execution of the self test the FAULT LED shown in Figure 5 8 on page 70 is illuminated On successful completion of the test and subsequent loading of the VSI address compare registers etc the LED is extinguished An error detected by the self test terminates thetest and the FAULT LED remains illuminated 6 1 Tests Performed The hardware self test is composed of the subtests described in the following sections 6 1 1 ROM Checksum The ROM c
13. Transmit Receive Polarity As required by MIL STD 188C EIME is equipped with jumper options to select the polarity of the transmit and receive data signals These jumpers are set as shown in Table B 2 EIMF is configured for El A 232 operation The jumper positions are permanently sol dered into inverting mode B 4 Driver Supply Voltages B 5 96 Asrequired by M IL STD 188C EIM E is equipped with Zener diodes to reducethe volt age supplied to the driver devices from the 12V and 12V supplied by the VM Ebus to MIL STD 188C levels EIM F has Zener diodes and utilizes the full 12V and 12V levels Interface Driver Waveshaping As required by MIL STD 188C EIM E is equipped for the installation of waveshaping capacitors used in conjunction with the 1488 line drivers The capacitor locations for each output signal are shown in Table B 3 No capacitors are installed in the standard factory version of EIME or EIMF DC 900 0408E B 8 port MIL STD 188C and 8 port EIA 232 Electrical Interface M odule Table 2 Jumper Settings for 8 port MIL STD 188C Function Inverted Not Inverted RXD00 K32 1 2 K322 3 TXD00 K242 3 K24 1 2 RXDOI K311 2 K312 3 TXDO1 K23 2 3 K23 1 2 RXD02 K30 1 2 K302 3 TXD02 K222 3 K22 1 2 RXD03 K29 1 2 K29 2 3 TXD03 K212 3 K21 1 2 RXD04 K28 1 2 K282 3 TXD04 K202 3 K20 1 2 RXD05 K27 1 2 K27 2 3 TXD05 K192 3 K19 1 2 RXD 06 K26 1 2 K262 3 TXD06 K182 3 K18 1 2 RXD07 K25 1 2 K252 3 TXD0
14. ee2e 0000002E 00000030 0000 PTBUG ee7c 0000007C 00B7 8000 00000080 C6A5 PTBUG gt Usethis command to program each of the configurable values shown in Table 3 2 into the EEPROM When programming the configurable parameters at addresses 1 and Ox2E through 0x36 substitute the configurable parameters you selected in Chapter 2 for those shown in the table Note During power up reset diagnostics one of the tests calculates a checksum of the ICP s PROM and compares it to a checksum stored at EEPROM address 0x7C generating an error if the values do not match As shown in Table 3 2 EEPROM address 7 must initially be programmed to the value 0x8000 This instructs the diagnostic one time only to calculate the PROM checksum and store it at this location overwriting the value 0x8000 rather than do the comparison Therefore if you review the contents of EEPROM after you have executed the diagnostics one or more times address 0x7C will no longer equal 0x8000 This is normal 40 DC 900 0408E 3 VM Ebus Installation Table 3 2 EEPROM Default Values Address Value Hex Description Hex 0 Validity word CAFE 2 Validity word FOOD 4 18 Reserved 1A Validity word BOBB 1C Boot flags Startup code EEPROM address high word 0 20 Startup code EEPROM address low word C000 22 Address to move startup code to in RAM high word 400E 24 Address to move startup code to
15. 0299 Figure 5 7 ICP Front Panel Showing Location of LEDs DC 900 0408E 69 ICP6000 X ICP9000 X ardware Description and Theory of Operation Address 10000001 7 6 5 4 3 2 1 0 VMERMS VMEBR1 VMEBRO RCINT EEPDI EEPSK EEPCS FAULT Mnemonic Name Description FAULT FAULT LED and SYSFAIL 0 FAULT LED and SYSFAIL asserted Control 1 FAULT LED and SYSFAIL negated The post reset state of this bit is 0 LED on and SY SFAIL asserted Figure5 8 Control Register 0 Usefor FAULT LED Address 10000001 7 6 5 4 3 2 1 0 VMERMS VMEBR1 VMEBRO RCINT EEPDI EEPSK EEPCS FAULT Mnemonic Name Description EEPDI EEPROM Line This bit selects the Data In line to the serial EEPROM EEPSK EEPROM Serial Clock Line This bit selects the clock to the serial EEPROM EEPCS EEPROM Chip Select 0 EEPROM not selected 1 EEPROM selected The post reset state of this bit is 0 Figure 5 9 Control Register 0 Use for EEPROM Operation 70 DC 900 0408E 5 Hardware Overview Address 10000003 7 6 5 4 3 2 1 0 SW6 SW5 EEPDO DMARDY SW4 SW3 SW2 SW1 Mnemonic Name Description EEPDO EEPROM Data Out Line This bit selects the Data Out line from the serial EEPROM Figure 5 10 Status Register Use for EEPROM Operation DC 900 0408 71 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation 5 14 Board Select Switches
16. 116 DC 900 0408E D 8 port EIA 422 Electrical Interface odule D 3 3 Terminal Ready The Terminal Ready TR outputs 0 7 are connected to a discrete hardware register and are written using a single address decode as shown in Figure D 2 Address 60000022 write only 7 6 5 4 3 2 1 0 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TRO FigureD 2 Terminal Ready Address Decode D 3 4 Request To Send The Request To Send RS outputs 0 7 are connected to the RTSA even numbered ports and RTSB odd numbered ports outputs of the SCCs and are written using the appropriate SCC accesses D 4 Connector Pin Assignments ThelCP isconnected to thedistribution panel by two cables Each cable has a high den sity 80 pin connector on the ICP end and two 40 pin connectors on the distribution panel end FigureA 4 on page 88 shows the orientation of the pins on the ICP connec tor The connector nearer the console port debug port is designated B and the con nector farther away is designated A See Figure 5 7 on page 69 for the location of the connectors Table D 2 shows the signal mapping for the cables that connect the ICP to either the EIA 449 the EIA 530 distribution panel Figure D 3 shows the EIA 449 connector with the supported signals their proper signal names and the mnemonics used in Table D 2 Figure D 4 shows the same for the EI A 530 connector DC 900 0408E 117 ICP6000 X ICP9000 X ardware Description and Theory o
17. 18 19 DataTerminal Ready DTR 20 21 22 23 DTE Transmitter Signal Element Timing TxC 24 25 Jumpers on the distribution panel and the ICP determine which of these pins is connected to the SCC FW N rn ua N Protective Ground Transmitted Data TxD Received Data TxD Request to Send RTS Clear to Send CTS Data Set Ready DSR Signal Ground Common Return GND Received LineSignal Detector DCD DRWG 2564 FigureB 4 232 MIL STD 188C Interface DC 900 0408E 101 ICP6000 X ICP9000 X Hardware Description and Theory of Operation TableB 5 Pin Assignments for 8 port MIL STD 188C amp EIA 232 Cable Connectors 80 pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal A 1 8 1 00 GND A 41 9 1 04 GND A 2 8 2 00 TXD A 42 9 2 04 TXD A 3 8 3 00 RTS A 43 J9 3 04 RTS A 4 8 4 00 RXD A 44 J9 4 04 RXD A 5 8 5 00 CTS A 45 J9 5 04 CTS A 6 J8 6 00 DCD 46 9 6 04 7 J8 7 00 DTR A 47 J9 7 04 DTR A 8 8 8 00 RXC 48 9 8 04 RXC A 9 J8 9 00 DSR A 49 9 9 04 DSR A 10 J8 10 00 TXC A 50 J9 10 04 TXC A 11 8 11 01 GND A 51 J9 11 05 GND A 12 J8 12 01 TXD A 52 J9 12 05 TXD A 13 J8 13 01 RTS A 53 J9 13 05 RTS A 14 J8 14 01 RXD A 54 J9 14 05 RXD A 15 J8 15 01 CTS A 55 J9 15 05 CTS A 16 J8 16 01 DCD A 56 J9 16 05 DCD A 17 J8 17 01 DTR A 57 J9 17 05 DTR A 18 J8 18 01 RXC A 58 J9 18 05 RXC A 19 J8 19 01 DS
18. 2 Data Set Ready Address D ecodes B 7 4 Data Terminal Ready The Data Terminal Ready DTR outputs 0 7 are connected to a discrete hardware reg ister and are written using a single address decode as shown in Figure 3 Address 60000020 write only 7 6 5 4 3 2 1 0 DTR7 DTR6 DTR5 DTR4 DTR3 DTR2 DTR1 DTRO Figure B 3 Data Terminal Ready Address Decode B 7 5 Request To Send The Request To Send RTS outputs 0 7 are connected to the RTSA even numbered ports and RTSB odd numbered ports outputs of the SCCs and are written using the appropriate SCC accesses 100 DC 900 0408E B 8 port MIL STD 188C and 8 port EIA 232 Electrical Interface M odule B 8 Connector Pin Assignments ThelCP is connected to thedistribution panel by a cable that has a high density 80 pin connector on the ICP end and two 40 pin connectors on the distribution panel end FigureA 4 on page 88 shows the orientation of the pins on the ICP connector See Figure 5 7 on page 69 for the location of the connectors The ICP in this case has only thetop 80 pin connector Table B 5 shows the signal mapping for the cable that connects the ICP to the distribu tion panel Figure B 4 shows the 232 or MIL STD 188C connector with the sup ported signals their proper signal names and the three letter mnemonics used in Table B 5 14 DCE Transmitter Signal Element Timing 15 16 Receiver Signal Element Timing RxC 17
19. 2 02 GND A 3 J8 3 00 GND A 43 J9 3 02 GND A 4 J8 4 00 CTS A 44 J9 4 02 CTS A 5 J8 5 00 RLSD A 45 J9 5 02 RLSD A 6 J8 6 00 DSR A 46 J9 6 02 DSR A 7 8 7 00 CI A 47 J9 7 02 CI A 8 J8 8 00 RTS A 48 J9 8 02 RTS A 9 8 9 00 LT A 49 9 9 02 LT A 10 J8 10 00 DTR A 50 J9 10 02 DTR A 11 J8 11 00 SD A A 51 J9 11 02 SD A A 12 J8 12 00 SD B A 52 J9 12 02 SD B A 13 J8 13 00 RD A A 53 J9 13 02 RD A A 14 J8 14 00 RD B A 54 J9 14 02 RD B A 15 J8 15 00 SCR A A 55 J9 15 02 SCR A A 16 J8 16 00 SCR B A 56 J9 16 02 SCR B A 17 J8 17 00 SCTE A A 57 J9 17 02 SCTE A A 18 8 18 00 SCTE B A 58 J9 18 02 SCTE B A 19 J8 19 00 SCT A A 59 J9 19 02 SCT A A 20 J8 20 00 SCT B A 60 J9 20 02 SCT B A 21 8 21 01 GND A 61 9 21 03 GND A 22 J8 22 01 GND A 62 J9 22 03 GND 23 8 23 01 GND 63 9 23 03 GND A 24 8 24 01 CTS A 64 J9 24 03 CTS A 25 J8 25 01 RLSD A 65 J9 25 03 RLSD 26 8 26 01 DSR 66 9 26 03 DSR A 27 J8 27 01 CI A 67 J9 27 03 CI 28 8 28 01 RTS 68 9 28 03 RTS 29 8 29 01 LT 69 9 29 03 LT A 30 J8 30 01 DTR A 70 J9 30 03 DTR A 31 8 31 01 5 71 J9 31 03 SD A A 32 8 32 01 SD B A 72 J9 32 03 SD B A 33 J8 33 01 RD A A 73 J9 33 03 RD A A 34 J8 34 01 RD B A 74 J9 34 03 RD B A 35 J8 35 01 SCR A 75 J9 35 03 SCR A A 36 J8 36 01 SCR B 76 J9 36 03 SCR B A 37 J8 37 01 SCTE A 77 J9 37 03 SCTE A A 38 J8 38 01 SCTE B A 78 J9 38 03 SCTE B A 39 J8 39 01 SCT A 79 J9 39 03 SCT A A 40 J8 40 01 SCT B A 80 J9 40 03 SCT B
20. 27 8 27 02 DTR A 67 J9 27 06 DTR A 28 J8 28 02 RXC A 68 J9 28 06 RXC A 29 J8 29 02 DSR A 69 J9 29 06 DSR A 30 8 30 02 TXC A 70 J9 30 06 TXC A 31 8 31 03 GND 71 9 31 07 GND A 32 8 32 03 TXD A 72 J9 32 07 TXD A 33 8 33 03 RTS A 73 J9 33 07 RTS A 34 8 34 03 RXD A 74 J9 34 07 RXD 35 8 35 03 5 75 9 35 07 5 36 J8 36 03 DCD 76 9 36 07 DCD A 37 8 37 03 DTR 77 9 37 07 DTR A 38 8 38 03 RXC A 78 J9 38 07 RXC A 39 8 39 03 DSR A 79 J9 39 07 DSR A 40 J8 40 03 TXC A 80 J9 40 07 TXC 90 DC 900 0408E A 16 port EIA 232 Electrical Interface M odule TableA 2 Pin Assignments for 16 port EIA 232 Cable Connectors Cont d 80 pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal 1 8 1 08 GND 41 9 1 12 GND B 2 8 2 08 TXD B 42 J9 2 12 TXD B 3 8 3 08 RTS B 43 J9 3 12 RTS B 4 8 4 08 RXD B 44 J9 4 12 RXD B 5 8 5 08 5 45 J9 5 12 CTS B 6 8 6 08 B 46 J9 6 12 DCD B 7 8 7 08 DTR B 47 J9 7 12 DTR B 8 Je 8 08 RXC B 48 J9 8 12 RXC B 9 Je 9 08 DSR B 49 J9 9 12 DSR B 10 J8 10 08 TXC B 50 J9 10 12 TXC B 11 8 11 09 GND B 51 9 11 13 GND B 12 8 12 09 TXD B 52 J9 12 13 TXD B 13 8 13 09 RTS B 53 J9 13 13 RTS B 14 8 14 09 RXD B 54 J9 14 13 RXD B 15 8 15 09 5 55 J9 15 13 CTS B 16 J8 16 09 DCD B 56 J9 16 13 DCD B 17 8 17 09 DTR B 57 J9 17 13 DTR B 18 J8 18 09 RXC B 58 J9 18 13 RXC B 19 J8 19 09 DSR B
21. 33 07 RD A B 34 J8 34 05 RD B B 74 J9 34 07 RD B B 35 J8 35 05 SCR A B 75 J9 35 07 SCR A B 36 J8 36 05 SCR B B 76 J9 36 07 SCR B B 37 8 37 05 SCTE A B 77 J9 37 07 SCTE A B 38 8 38 05 SCTE B B 78 9 38 07 SCTE B B 39 8 39 05 SCT A B 79 9 39 07 SCT A B 40 J8 40 05 SCT B B 80 J9 40 07 SCT B DC 900 0408 111 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 112 DC 900 0408E Appendix 8 port EIA 422 Electrical Interface Module This Electrical Interface M oduleis referred to as EIM J Itis an 8 port daughterboard for the ICP base board and supports both EIA 449 and EIA 530 operation EIMJ is equipped with 26LS31 drivers and 26LS32 receivers which are designed to meet therequirements of EI A 422 Provision is madeon the EIM J PCB for termination on all receive differential lines Thetermination components are not installed on the standard factory version of the assembly D 1 Modem Clocks EIMJ supports the full functionality of the serial communications controller SCC with respect to external and internal clock sources D 1 1 Receive Clock Inputs The Receive Clock and pins are always inputs to theSCC inputs 0 7 are connected to the RXCA even numbered ports and RxCB odd numbered ports inputs of the SCCs D 1 2 Transmit Clock Inputs Outputs The Transmit Clock TxCA and TxCB pins can be programmed as either inputs to or outputs from the SCC To support
22. 59 J9 19 13 DSR B 20 J8 20 09 TXC B 60 J9 20 13 TXC B 21 8 21 10 GND B 61 J9 21 14 GND B 22 8 22 10 TXD B 62 J9 22 14 TXD B 23 J8 23 10 RTS B 63 J9 23 14 RTS B 24 J8 24 10 RXD B 64 J9 24 14 RXD B 25 J8 25 10 CTS B 65 J9 25 14 CTS B 26 J8 26 10 DCD B 66 J9 26 14 DCD B 27 8 27 10 DTR B 67 J9 27 14 DTR B 28 J8 28 10 RXC B 68 J9 28 14 RXC B 29 J8 29 10 DSR B 69 J9 29 14 DSR B 30 8 30 10 TXC B 70 J9 30 14 TXC B 31 8 31 11 GND 71 9 31 15 GND B 32 8 32 11 TXD B 72 9 32 15 TXD B 33 8 33 11 RTS B 73 J9 33 15 RTS B 34 8 34 11 RXD B 74 J9 34 15 RXD B 35 8 35 11 CTS B 75 J9 35 15 CTS B 36 J8 36 11 DCD B 76 J9 36 15 DCD B 37 Je 37 11 DTR B 77 9 37 15 DTR B 38 J8 38 11 RXC B 78 J9 38 15 RXC B 39 J8 39 11 DSR B 79 J9 39 15 DSR B 40 J8 40 11 TXC B 80 J9 40 15 TXC DC 900 0408E 91 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 92 DC 900 0408E Appendix 8 port MIL STD 188C and 8 port El A 232 Electrical Interface Module The Electrical Interface M odules referred to as EIM E or EIMF are 8 port daughter boards for the ICP base board and support MIL STD 188C or EIA 232 operation respectively Because their jumper locations and pinouts are identical and their func tionality is very similar they are both discussed in this Appendix B 1 Modem Clocks EIM E and EIM F support the full functionality of the serial communications controller SCC with respect to external and internal clock sou
23. 900 0408E 55 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 5 5 Timers The 68901 Multi Function Peripheral M FP provides four timers The timers perform thefollowing functions Operating system clock VM Ebustimeout timing Console port data rate generation Thetimers are driven by a 3 6864 M Hz clock 5 6 ConsolePort ThelCP sconsole port is provided by thesingle channel U SART on the Multi Function Peripheral It is equipped with EIA 232 interface and supports transmit and receive signals over the common asynchronous speed range The console port connector is a 14 pin dual row header located on the ICP s front panel This connector is designed to allow construction of a simple adapter to the stan dard 25 pin D EIA 232 connector using insulation displacement connectors and 14 conductor ribbon cable Table 5 3 showsthe pin assignments 5 7 Communications D evices 56 The Electrical Interface M is a daughterboard that contains to eight Z85C 30 SCCs operating at 7 3728 M H z ICP6000 1 C P9000 or 285230 SCCs operating at 14 7456 M Hz ICP6000X I CP9000X and optionally bit registers for modem and other control applications All drivers and receivers are located on the Oneor two 80 conductor ribbon cables connect the EIM to thedistribution panel Thedistribution panel is completely passive and serves only to mount connectors Specific EIM descrip tions can be f
24. If the board select switches are set to select an ICP number EEPROM values are updated for consistency The configurable parameters in Table 3 2 are boot flags slave address compare high and low words of address modeselection slave address modifier compare slave address modifier compare don t care DC 900 0408E 2 Unpacking and Configuration The options for the configurable parameters are described in the following sections After you have selected a value for each of these parameters follow the installation steps in Chapter 3 to program the EEPROM 2 6 1 1 Boot Flags The boot flags word determines the operations performed by the PROM resident firm ware when the ICP is powered on or reset The PROM code includes a set of diagnostic self tests that may be enabled or disabled see Chapter 6 If enabled errors encoun tered during the tests may be displayed on a terminal attached to the console port The PROM code also includes a boot loader that allows code and data to be down loaded from the host system see Chapter 7 On completion of the diagnostics or immediately after reset if diagnostics are disabled control is normally transferred to the boot loader If this function is disabled control is transferred to PTBUG instead and the PT BUG boot command must be used to execute the boot loader The five low order bits of the boot flag word are used to configure these options as shown in Figure 2 1
25. The Transmit Clock TxCA and TxCB pins can be programmed as either inputsto or outputs from the SCC To support this bidirectional interface EIGH is equipped with both a driver and a receiver for this line The 7 drivers and receivers are selected using the jumper settings shown in Table C 1 Refer also to Figure C 1 DC 900 0408E 103 ICP6000 X ICP9000 X Hardware Description and Theory of Operation Caution You must also use the protocol software to configure the desired clocking TableC 1 Clock Jumper Settings for 8 port V 35 Transmit Clock Source Port Internal DTE External DCE 0 K11 2 1 3 4 1 21 2 2 3 4 2 K31 2 3 4 3 K41 2 3 4 4 K51 2 K5 3 4 5 K61 2 K63 4 6 K71 2 K7 3 4 7 K81 2 K83 4 a Only one jumper per port C 2 Z85C30 285230 Serial Communications Controller EIGH has four Z85C30 ICP6000 ICP9000 285230 ICP6000X I CP9000X serial communications controllers SCCs Each SCC implements two communications ports C 2 1 SCC Register Access Access to the SCC data and command registers is made using the addresses shown in Table5 10n page 51 H ardware protection is provided so that the SCC writerecovery limits are automatically met 104 DC 900 0408E C 8 port V 35 CCITT Electrical Interface M odule O O 12 34 Porto 12 p Pot4 N B X N X T 12 34 T T 32
26. Theremaining bits are unused 2 6 1 2 Slave Address Compare Addresses 0x2E and 0x30 the EEPROM specify the baseV M E address where the mail boxes reside The default of OXFE000000 assumes A 32 addressing This address can be changed as required for a given environment and must be changed if more than one exists in the chassis Each ICP must have a different base address The base address of the mailboxes must be on a 512 byte boundary DC 900 0408E 29 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 15 5 4 3 2 1 0 not used M1 MO DISPLAY DIAGS BOOT Mnemonic Name Description BOOT Boot Load Execution This bit selects the conditions under which the boot loader will execute 0 boot on power up or reset 1 boot on PTBUG boot command only DIAGS Diagnostic Execution Thisbit selects whether or notthe diagnostic self tests will execute on power up and reset 0 2 no diagnostics 1 diagnostics enabled DISPLAY Diagnostic Error Display This bit enables or disables the display of diagnostic errors if any on the consoleter minal 0 2 no output to console 1 display errors on console M 1 M 0 DRAM M emory Size These bits enable the message size 00 21megabyte 01 4 megabytes 10 8 megabytes Figure 2 1 EEPROM Boot Flag Word 2 6 1 3 ModeSelection Thevalue stored in EEPROM address 0x32 selects whether the will A32 A24 or A16 slave Legal valuesfor this word are
27. Usefor EEPROM Operation 70 Status Register Usefor EEPROM Operation 71 Status Register Use for Board Select Switches 72 Typical Download Sequence 81 16 port 232 Clock Jumper Settings 85 Data Set Ready Address Decodes 87 Data Terminal Ready Address Decodes 88 Front View of 80 pin Connector 88 __ prx 89 8 port MIL STD 188C or EIA 232 Clock Jumper Settings 95 Data Set Ready Address Decodes 100 Data Terminal Ready Address Decode 100 EIA 2320r MIL STD 188C 101 8 port V 35 Clock Jumper Settings 105 DC 900 0408E 9 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation Figure C 2 Figure C 3 Figure C 4 Figure D 1 Figure D 2 Figure D 3 Figure D 4 10 Data Set Ready and Calling Indicator Address Decodes 107 Data Terminal Ready and Local Test Address Decodes 108 IHE ed dd 109 8 port EIA 422ClockJumperSettings 115 Terminal Ready Address Decode 117 449 Interface 118 ELO IDE DOR aw ded 119 DC 900 0408E Table 1 1
28. as follows A32 slave 0x04 A24 slave 0x14 A16 slave 0x34 30 DC 900 0408E 2 Unpacking and Configuration 2 6 1 4 Slave Address Modifier Compare The value stored in EEPROM address 0x34 specifies the address modifier pattern for slave address compares Table 2 5 lists the legal values for this byte Table 2 5 Values for the Slave Address M odifier Compare Hex Code Function 3F 3E 3D 3B 3A 39 30 2D 29 20 OF OE 00 0B OA 09 00 A24 Standard Supervisory Block Transfer A24 Standard Supervisory Program Access A24 Standard Supervisory Data Access A24 Standard Non Privileged Block Transfer A24 Standard Non Privileged Program Access A24 Standard Non Privileged Data Access A24 Don t care about lower four bits A16 Short Supervisory Access A16 Short Non Privileged Access A16 Don t care about lower four bits A32 Standard Supervisory Block Transfer A32 Standard Supervisory Program Access A32 Standard Supervisory D ata Access A32 Standard Non Privileged Block Transfer A32 Standard Non Privileged Program Access A32 Standard Non Privileged Data Access A32 Don t care about lower four bits 2 6 1 5 Slave Address Modifier Compare Don t Care Any or all of the address modifier bits can be ignored in the comparison The value stored in location 0x36 in theEEPROM specifies a comparison mask where aonein the bit pattern signifies don t care DC 900 0408E 31 ICP6000 X ICP9000 X Hardware Descri
29. boards are in the host s backplane refer to your system documentation for the correct orientation Caution The ICP will be severely damaged if inserted into the backplane incorrectly Step 6 To access PTBUG connect a terminal to the ICP s console port connector See Figure 3 1 on page 37 for the location of the console port The terminal should be set to 9600 baud 8 bits no parity one stop bit For the ICP6000 X 60 form factor a console cable is shipped with the board For CP9000 X 90 form factor the con sole cable connects the console port on the ICP board to the corresponding port on the 9U carrier You will need to providea null modem crossover cable to connect terminal to the console port Step 7 Turn on the power to your host system Type Control C at the terminal to cause the PTBUG gt prompt to appear on theterminal screen Program or verify the EEPROM using the PTBUG EE command The following example verifies that address Ox2E is set to and sets address 7 to 0x8000 Press carriage return to accept the current value press period to return to the prompt Because the EEPROM isorganized as 64 16 bit words this command operates in 16 bit word operands For more information see the PT BUG Debug and Utility Program Ref erence M anual DC 900 0408E 39 ICP6000 X ICP 9000 X ardware Description and Theory of Operation Syntax PTBUG gt ee address Example PTBUG
30. check DC 900 0408 75 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 76 DC 900 0408E Chapter Boot Load Procedure ThelCP PROM contains a boot loading program that downloads code and data from the host system to thel CP SRAM This chapter describes the interface between the boot loader and the host system 7 1 Download Message Format The boot loader which resides in PROM on the ICP communicates with the host by defining the ICP s 16 byte wide mailboxes as a protocol exchange region PXR The PXR occupiesthe first twelve mailboxes and is defined in Table 7 1 Table 7 1 Protocol Exchange Region Mailbox Number s Field Name Description 0 h cmd Host command register 1 i cmd ICP command register 2 3 h_bytes Byte count 4 7 h_iaddr Load or execution address 8 11 h_haddr Host buffer address The ICP writes function codes to the i cmd field and the host writes function codes to theh cmd field The host must clear the i cmd field after reading a value from it indicat ing to the ICP that it may write another value to the field Likewise the ICP clears the h cmd field after it reads a value written by the host The host must not write another value to theh cmd field until it has been cleared by the ICP DC 900 0408E 77 ICP6000 X ICP9000 X ardware Description and Theory of Operation The following function codes are written to the h_cmd field by the host processor Funct
31. eee ee tees Eg dient e 26 12 Slave Address Compare 2 6 1 3 ModeSdection sa gp EORR 2 6 1 4 Slave Address M odifier Compare 2 6 15 Slave Address Modifier 2 6 2 Configuring theVM Ebus M aster Interface and Interrupter DC 900 0408E 13 17 17 18 21 21 22 22 22 23 23 24 25 26 28 28 29 29 30 M 3l ICP6000 X ICP 9000 X Hardware Description and Theory of Operation 3 VMEbusiInstallation 4 HardwareSpecifications 41 Mechanical and Environmental Specifications 411 Physica Characteristics 412 Power Requirements 13 EVANS dado 42 5 Hardware Overview 51 Internal Architecture oa aaa ee 5 a d acr oe Se ae 53 MOMMY cuu ca EXC RR PROC ES ERS COM o So 50 LODSIOPUIT LG 202 57 CommunicatiionsDevices 5 51 BODEN _ PE eRe RRS A oe eae 5 8 5 8 1 MAR TCRMemoryLocations 5 8 2 DMA Terminal Count Interrupts 5 8 3 1 0 DMA Command Register 59 VMEbus
32. this bidirectional interface EIMJ is equipped with both a driver and a receiver for this line DC 900 0408 113 ICP6000 X ICP9000 X Hardware Description and Theory of Operation The 7 drivers and receivers are selected using the jumper settings shown in Table D 1 Refer also to FigureD 1 Caution You must also use the protocol software to configure the desired clocking Table D 1 Clock Jumper Settings for 8 port 422 Transmit Clock Source Port Internal DTE External DCE 0 K11 2 1 3 4 1 21 2 2 3 4 2 K31 2 3 4 3 K41 2 K43 4 4 K51 2 K5 3 4 5 K61 2 K63 4 6 K71 2 K7 3 4 7 K81 2 K83 4 a Only one jumper per port D 2 285 30 285230 Serial Communications Controller EIMJ has four Z85C30 ICP6000 ICP9000 or 285230 ICP6000X ICP9000X serial communications controllers SCCs Each SCC implements two communications ports 114 DC 900 0408E D 8 port 422 Electrical Interface M odule 1 2 N T 12 E R N 12 A 1 2 LEDs 80 pin Connectors Console Port DC 900 0408E 3 4 Port 3 1 2 3 4 Port 7 6 X N X 34 T Port2 T 12 3 4 Port6 R R R 34 N Portl N 12 60 34 N Port5 Q P 34 Porto L Q2 9 5x4 Pora N 7 Daughterboard VMEbus Connectors E DRWG 2223 Notes 1 All settings from the fa
33. ware installation Step 11 After you boot the new kernel or operating system verify the hardware and software installation by running the verification test Refer to the ICP6000 ICP9000 Software Installation Guidefor UNIX Products Note Some operating systems support loadable drivers rather than requiring the build of a new image DC 900 0408E 3 VM Ebus Installation Knob LEDs 6U Format Q 9 L oopback Cable Port 0 to Port 1 to Lower Ports Distribution Box Recessed 80 pin Connector for Upper Ports Console Port Connector E 6U Style Panel 2218 Note Connections for the 9U panel are similar Figure3 2 ICP6000 X Labeling and Loopback Connections DC 900 0408 43 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 44 DC 900 0408E Chapter Hardware Specifications The IC P6000 X I CP9000 X consists of a base board that is a VM Ebus controller an Electrical Interface M odule EIM daughterboard and one or more passive distribu tion panels The base board contains the 680x0 memory Ebus interfaces and DM controller The EIM contains the communications and line interface devices The dis tribution panel provides the required transition from the ICP to the connector inter face 4 1 Mechanical and Environmental Specifications The following sections define the requirements for the ICP 4 1 1 Physical Characteristics
34. 1 3 K2 1 to K2 2 128K x8 28 pin PROM ROM K2 1 to K2 2 256K x8 32 pin PROM ROM K1 1 to K1 2 K2 1 to K2 2 DC 900 0408E 23 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 2 5 2 7 ICP6000X ICP9000X Pinout Configurations Thejumpers at locations K 1 and K2 allow for variations in the pinout of PROM ROM socket U 7 see Table 2 2 When installing 28 pin devices be sure that pin 14 of the deviceenters pin 16 of the socket bottom justified Table 2 2 7 ICP6000X I CP9000X Configuration Jumpers Installed DeviceType All Other 1 K2 10 K 11 Removed 32Kx8 28 pin PROM ROM K1 2 to K1 3 K2 2 to K2 3 K10 2 to K10 3 K11 2 to K11 3 64K x8 28 pin PROM ROM K1 2 to K1 3 K2 1to K2 2 K10 2 to K10 3 K11 2 to K11 3 128K x8 32 pin PROM ROM K1 2 to K1 3 K2 1to K2 2 K10 2 to K10 3 K11 2 to K11 3 256K x8 32 pin PROM ROM K1 1to K1 2 K2 1to K2 2 K10 2 to K10 3 K11 2 to K11 3 512K x8 32 pin PROM ROM 1 1 K1 2 K2 1to K2 2 K10 1 to K10 2 K11 2 to K11 3 1024K x8 32 pin PROM ROM K1 1to 1 2 K2 1to K2 2 K10 1 to K10 2 K11 1 to K11 2 24 DC 900 0408E 2 Unpacking and Configuration 2 5 3 U19 ICP6000 ICP9000 Pinout Configurations The jumpers at locations K5 K6 and K7 allow for variation in the pinout of the PROM ROM EEPROM SRAM socket U 19 see Table 2 3 When installing 28 pin device be sure that pin 14 of the device enters pin 16 of the socket
35. 3 K7 2 to K7 3 K8 2 to K8 3 K9 2 to K9 3 K5 1to K5 2 K6 2 to K6 3 K7 2 to K7 3 K8 2 to K8 3 K9 2 to K9 3 K5 1to K5 2 K6 2 to K6 3 K7 1to K7 2 K8 2 to K8 3 K9 2 to K9 3 K5 1to K5 2 K6 2 to K6 3 K7 1to K7 2 K8 1to K8 2 K9 2 to K9 3 K5 1to K5 2 K6 2 to K6 3 K7 1to K7 2 K8 1to K8 2 K9 1to K9 2 DC 900 0408E 27 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 2 6 Software Programmable Configuration O ptions M any of the configuration options normally associated with jumpers or switches are software firmware controllable on the CP 2 6 1 Configuring the Slave Address D ecoder 28 During hardware installation parameters for configuring the VM Ebus slave address decoder may be programmed into the ICP s EEPROM using PTBUG the debug ging tool An additional configurable parameter selects diagnostic and boot load options Some fixed values must be programmed into the EEPROM as well Once the EEPROM is programmed the PROM resident boot loader reads the values from EEPROM and or the board select switches and uses them to program the slave address decoder each time the ICP is powered on or reset Table 3 2 shows the EEPROM map and recommended values The values shown would bea typical configuration for a Sun 3 or Sun 4 Entries shown with an asterisk are configurable options All other entries are not configurable and must be pro grammed into the EEPROM with the values shown Note
36. 3 SW 2 SW1 Mnemonic Name Description DMARDY 1 0 DMA Controller Ready Do not write to DMA Command Register 1 to writeto DM A Command Register Figure5 4 Status Register Usefor DMA Thehost may issue hardware reset of thelCP by accessing a specific location decoded by the VSI The location must be accessed using a specific data pattern to reduce the chances of inadvertent reset 0xAA to offset Ox3D 5 9 1 VMEbus Slave Address D ecoder TheVM Ebus slave address decoder provides address decoding to allow the mailboxes to be addressed from the VM Ebus The PROM based startup code loads the VSI Slave Address Decoder Registers from values it reads from the EEPROM or the board select switches Refer to Table 5 1 VSI register addresses 5 9 2 VMEbus Mailboxes and Software Reset 62 Using its registers the VSI device decodes a 512 byte region of the VM Ebus address space The 16 byte wide mailboxes and the software reset decoder are in this region VM Ebus access to the mailboxes can be made to interrupt the local processor bus The type of access and the interrupt pin to be used can be programmed The mailboxes are accessible on the VM Ebus at odd addresses B 0 beginning at offset 1 from the base of the 512 byte region The Software Reset Register is accessed the VM Ebus at offset Ox3D from the base with OxAA The mailboxes are also accessible by the local processor DC 900 0408E 5 Hardware Overview
37. 6 describes the hardware self test diagnostics DC 900 0408 13 ICP6000 X ICP9000 X Hardware Description and Theory of Operation Chapter 7 describes the boot load procedure Appendix A describes the daughterboard that provides the 16 port EI A 232 electrical interface Appendix B describes the daughterboard that provides the 8 port MIL STD 188C and EIA 232 electrical interfaces Appendix C describes the daughterboard that provides the 8 port V 35 CCITT electri cal interface Appendix D describes the daughterboard that provides the 8 port EIA 422 electrical interface References 14 While reading this manual you might also need to refer to the manuals listed below CP9000 Software Installation Guide for UNIX Products Simpact Inc DC 900 0550 M C68020 32 Bit M icroprocessor U ser s M anual M otorola Inc M C68030 32 Bit M icroprocessor U ser s M anual M otorola Inc M C68901 M ulti function Peripheral Specification M otorola Inc PTBUG Debug and Utility Program Reference Manual Simpact Inc DC 900 0424 VM Ebus Specification M anual Revision C 1 VM Ebus International Trade Associ ation VITA VSI VM Ebus Slave Interface ASI C M anual Performance Technologies Inc 28530 Serial Communications Controller Technical M anual Zilog Inc 785230 Serial Communications Controller Technical M anual Zilog Inc DC 900 0408E Preface Document Conventions Thefollowing convent
38. 7 9 37 03 TR B A 38 J8 38 01 TR A 78 9 38 03 A 39 J8 39 01 TT B A 79 J9 39 03 TT B A 40 J8 40 01 TT A A 80 J9 40 03 TT A 120 DC 900 0408E D 8 port EIA 422 Electrical Interface M odule TableD 2 Pin Assignments for 8 port 422 Cable Connectors Cont d 80 pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal B 1 8 1 04 SG B 41 9 1 06 SG B 2 8 2 04 SG B 42 J9 2 06 SG B 3 J8 3 04 RD B B 43 J9 3 06 RD B B 4 J8 4 04 RD A B 44 J9 4 06 RD A B 5 J8 5 04 RT B B 45 J9 5 06 RT B B 6 J8 6 04 RT A B 46 J9 6 06 RT A B 7 8 7 04 CS B B 47 J9 7 06 CS B B 8 J8 8 04 CS A B 48 J9 8 06 CS A B 9 8 9 04 RR B B 49 J9 9 06 RR B B 10 J8 10 04 RR A B 50 J9 10 06 RR A B 11 8 11 04 ST B B 51 J9 11 06 ST B B 12 J8 12 04 ST A B 52 J9 12 06 ST A B 13 J8 13 04 SD B B 53 J9 13 06 SD B B 14 J8 14 04 SD A B 54 J9 14 06 SD A B 15 J8 15 04 RS B B 55 J9 15 06 RS B B 16 J8 16 04 RS A B 56 J9 16 06 RS A B 17 J8 17 04 TR B B 57 J9 17 06 TR B B 18 J8 18 04 TR A B 58 J9 18 06 TR A B 19 J8 19 04 TT B B 59 J9 19 06 TT B B 20 J8 20 04 TT A B 60 J9 20 06 TT A B 21 J8 21 05 SG B 61 J9 21 07 SG B 22 J8 22 05 SG B 62 J9 22 07 SG B 23 J8 23 05 RD B B 63 J9 23 07 RD B B 24 J8 24 05 RD A B 64 J9 24 07 RD A B 25 J8 25 05 RT B B 65 J9 25 07 RT B B 26 J8 26 05 RT A B 66 J9 26 07 RT A B 27 J8 27 05 CS B B 67 J9 27 07 CS B B 28 J8 28 05 CS A B 68 J9 28 07 CS A B 29 J8 29 05 RR B B 69 J9 29 07 RR B B 30
39. 7 K172 3 K17 1 2 30nejumper per signal B 6 Interface Receiver Response Control Asrequired by MIL STD 188C EIME is equipped for the installation of response con trol capacitors used in conjunction with 1489 line receivers The capacitor locations for each input signal are shown in Table B 4 No capacitors installed in thefactory stan dard version of EIM E or EIM F B 7 Modem Control EIM E and EIMF support five modem control signals three inputs Data Set Ready Clear To Send and Data Carrier Detect and two outputs Data Terminal Ready and DC 900 0408E 97 ICP6000 X ICP9000 X Hardware Description and Theory of Operation TableB 3 Capacitor Locations for Waveshaping Signal Capacitor Signal Capacitor Name Location Name Location DTROO C29 DTRO4 C39 TXD00 C9 TXD04 C19 500 11 504 21 TXCO00 C4 TXC04 C12 DTRO1 C31 DTRO5 C41 TXD01 C3 TXD05 C10 RTSO1 C43 505 C33 1 45 TXC05 C35 DTRO2 C22 C32 TXD02 C13 TXD06 C23 87502 C15 RT S06 C25 TXC02 C6 TXC06 C16 C20 DTRO7 C30 TXD03 C5 TXD07 C14 RTS03 C36 507 C26 TXC03 C34 TXC07 C24 Request To Send These modem controls are connected to either the SCC or to a ded icated hardware register B 7 1 Data Set Ready The Data Set Ready DSR inputs 0 7 are connected to a discrete hardware register and are read using two address decodes as shown in Figure B 2 B 7 2 Clear To Send TheClear To Send CTS input
40. 8 EIM SCC Port 12 Data 60000019 EIM SCC Port 12 Control 6000001A EIM SCC Port 13 Data 6000001B EIM SCC Port 13 Control 6000001C EIM SCC Port 14 Data 6000001D EIM SCC Port 14 Control 6000001E EIM SCC Port 15 Data 6000001F EIM SCC Port 15 Control 60000020 6000003F 80000000 FFFFFFFF EIM Bit Registers VM Ebus Access 0 for ICP6000 I CP9000 or for ICP6000X I CP9000X 54 DC 900 0408E 5 Hardware Overview Table5 2 General Interrupt M ap Level Source Vector hex 7 NMI Toolkit Panel 6 DMA Channel Terminal Count SCC viaMFP Software Timer VSI Interrupt 0 LIRQO VSI Interrupt 0 LIRQ1 VSI Interrupt 0 LIRQ2 e N W 7C EO EF receive FO FF transmit x0 xF programmable 1C Auto Vector 4 1B Auto Vector 3 1A Auto Vector 2 19 Auto Vector 1 5 3 Main Memory Main memory is one or four megabytes of dynamic RAM 5 4 PROM The board is equipped with two 32 pin JEDEC sockets configured as byte ports One socket is used with read only devices The second socket can be configured for read only or read write devices As supplied by Simpact the read only socket U 39 or U 7 contains a 64Kx8 PROM The diagnostics boot loader and PTBUG debugging tool reside in this PROM The other socket is empty and available for a user added device See Section 2 5 on page 23 for the jumper configurations to enable these sockets for the typeof memory to be used DC
41. 97 Capacitor Locations for Waveshaping 98 Capacitor Locations for Response 99 Pin Assignments for 8 port MIL STD 188C amp EIA 232 Cable Connectors 102 Clock Jumper Settings for 8 portV 35 104 Pin Assignments for 8 port V 35 Cable Connectors 110 Clock Jumper Settings for 8 port 422 114 DC 900 0408E 11 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation TableD 2 Pin Assignments for 8 port EIA 422 Cable Connectors 120 12 DC 900 0408E Preface Purpose of Document This manual describes Simpact s ICP6000 X I CP9000 X front end communications processor its architecture and how it works in the VM Ebus based system The infor mation in this manual supplements the basic information that appears in the installa tion guides delivered with the Intended Audience This manual should be read by maintenance technicians computer system integrators and software developers who need detailed information about the operating theory and features of the hardware Organization of Document Chapter 1 is a functional overview of thelCP Chapter 2 describes how to unpack and configure the ICP Chapter 3 describes how to install the CP Chapter 4 defines the mechanical and environmental specifications Chapter 5 contains a detailed theory of operation with hardware descriptions Chapter
42. C 900 0408E 7 Boot Load Procedure address space decoded by the VSI see Section 5 9 on page 60 After resetting the ICP the host driver must wait for the mailboxes to appear on the VM Ebus This must be done in such a way that the host system does not crash with a bus error For example SunOS provides a subroutine called peekc which takes an address as input and returns an error codeif the address is invalid Simpact s SunOS host driver calls peekc periodi cally with the address of the first mailbox until no error is returned Next the host must issue a download ready command to provide the with a set of parameters to initializetheVM Ebus master interface and interrupter These parameters must be stored in the PXR before issuing the command The fields of the PXR havea special definition used for this command only as shown in Table 7 2 Refer to Section 2 6 2 on page 32 for a description of appropriate values for these fields After setting the parameters the host writes the download ready command codeto theh cmd field and waits for an acknowledgment from an in the i cmd field Table 7 2 Protocol Exchange Region for Download Ready Command Mailbox Number Field Name Description 0 h cmd Host command register 1 i cmd ICP command register 2 h vec Vector 3 h lev Level 4 h_mode Mode 5 h_amod Address modifier When the host has read the ack function code from the i cmd field the boot loader writes a d
43. ICP6000 X I CP9000 X Hardware Description and Theory of Operation DC 900 0408E Simpact Inc SIMPACT 9210 Sky Park Court San Diego CA 92123 January 1998 Simpact Inc 9210 Sky Park Court San Diego CA 92123 619 565 1865 CP6000 X I CP9000 X Hardware Description and Theory of Operation 1989 1998 Simpact Inc All rights reserved Printed in the United States of America This document can change without notice Simpact Inc accepts no liability for any errors this document might contain Sun 3 Sun 4 and SunOS aretrademarks of Sun M icrosystems Incorporated Contents Preface 1 Overview of theICP ll MEILE uua ACE e ode co 1 2 HPADOUDONIDUES gt Lack 2 Unpacking and Configuration 21 SUG Pie UGS EE 127 dew eee 23 MEN pedon e de oC a OR ob ak d ERE 25 i bod eG hed eee Wb ded eS Ra ees 2 5 1 U39 ICP6000 ICP9000 Pinout Configurations 2 5 2 U7 ICP6000X ICP9000X Pinout Configurations 2 5 3 U19 I1CP6000 IC P9000 Pinout Configurations 2 5 4 U8 ICP6000X ICP9000X Pinout Configurations 2 6 Software Programmable Configuration Options 2 6 1 Configuring the Slave Address Decoder SELL POCHE wie
44. J8 30 05 RR A B 70 J9 30 07 RR A B 31 8 31 05 ST B B 71 J9 31 07 ST B B 32 8 32 05 ST A B 72 9 32 07 ST A B 33 J8 33 05 SD B B 73 9 33 07 SD B B 34 8 34 05 SD A B 74 J9 34 07 SD A B 35 J8 35 05 RS B B 75 J9 35 07 RS B B 36 8 36 05 RS A B 76 9 36 07 RS A B 37 J8 37 05 TR B B 77 J9 37 07 TR B B 38 J8 38 05 TR A B 78 J9 38 07 TR A B 39 J8 39 05 TT B B 79 J9 39 07 TT B B 40 J8 40 05 TT A B 80 J9 40 07 TT A DC 900 0408 121 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 122 DC 900 0408E Index Numerics 68901 multi function peripheral 74 A Antistatic precautions 21 Applications 18 communications protocols 18 data acquisition 19 device control 19 multiplelines 19 Board select switches 72 Boot flag word EEPROM 30 Bootflags 29 Boot load execution 30 Boot load procedure 77 C Calling indicator 107 Channel stop start 61 Channel transmit receive 61 Checksum ROM 73 CI see Calling indicator Clearto send 98 107 116 Communications devices 56 register access 57 SCC interrupts 57 Communications protocols 18 Configuration mailbox interrupts 63 slave address decoder 28 VMEbus master interface and interrupter 32 DC 900 0408E Configuration options software programmable 28 U19 jumper 25 U39 jumper 23 U7jumper 24 U8jumper 27 Connector pin assignments EIA 232 16 port 88 EIA 232 8 port 101 EIA 449 8 port 117 MIL STD 188C 8 port 101 V 35 Bell 306 8 port 108 C
45. Mailbox Register 7 30000008 VSI Mailbox Register 8 30000009 VSI Mailbox Register 9 3000000A VSI Mailbox Register 10 3000000B VSI Mailbox Register 11 3000000C VSI Mailbox Register 12 3000000D VSI Mailbox Register 13 3000000E VSI Mailbox Register 14 3000000F VSI Mailbox Register 15 30000010 VSI Mailbox 7 0 Interrupt M ask Register write only 30000010 VSI Mailbox 7 0 Interrupt Pending Register read only 30000011 VSI Mailbox 15 8 Interrupt M ask Register write only 30000011 VSI Mailbox 15 8 Interrupt Pending Register read only 30000012 VSI Mailbox 03 00 Interrupt Pin Select 30000013 VSI Mailbox 07 04 Interrupt Pin Select 30000014 VSI Mailbox 11 08 Interrupt Pin Select 30000015 VSI Mailbox 15 11 Interrupt Pin Select 30000016 VSI Slave Address M odifier Compare Register 30000017 VSI Slave Address M odifier Don t Care Register DC 900 0408E 5 Hardware Overview Table5 1 General Memory M ap Cont d Memory Range hex Device 30000018 VSI Slave Address A31 A24 Compare Register 30000019 VSI Slave Address A23 A 16 Compare Register 3000001A VSI Slave Address A15 A09 Compare Register 3000001B VSI VM Ebus Interrupter Request Level Register write only 3000001B VSI VM Ebus Interrupter Level Pending Register read only 3000001C VSI VM Ebus Interrupt Vector Number Register 3000001D VSI SlaveAuxiliary Address Compare Don t Care 3000001E VSI Global Interrupt Status Register read only 3000001E VSI Master Enable Register write only
46. R A 59 J9 19 05 DSR A 20 J8 20 01 TXC A 60 J9 20 05 TXC A 21 8 21 02 GND A 61 9 21 06 GND A 22 J8 22 02 TXD A 62 J9 22 06 TXD A 23 8 23 02 RTS A 63 9 23 06 RTS A 24 J8 24 02 RXD A 64 J9 24 06 RXD A 25 J8 25 02 CTS A 65 J9 25 06 CTS A 26 8 26 02 DCD A 66 9 26 06 DCD A 27 J8 27 02 DTR A 67 J9 27 06 DTR A 28 J8 28 02 RXC A 68 J9 28 06 RXC A 29 8 29 02 DSR 69 9 29 06 DSR A 30 J8 30 02 TXC A 70 J9 30 06 TXC A 31 8 31 03 GND A 71 9 31 07 GND A 32 8 32 03 72 9 32 07 A 33 J8 33 03 RTS A 73 J9 33 07 RTS A 34 J8 34 03 RXD A 74 J9 34 07 RXD A 35 8 35 03 CTS 75 9 35 07 CTS A 36 J8 36 03 DCD 76 19 36 07 37 J8 37 03 DTR 77 J9 37 07 DTR A 38 J8 38 03 RXC A 78 J9 38 07 RXC A 39 J8 39 03 DSR A 79 J9 39 07 DSR A 40 J8 40 03 TXC A 80 J9 40 07 TXC 102 DC 900 0408E Appendix 8 port V 35 CCITT Electrical Interface Module This Electrical Interface M odule is referred to as EIGH It is an 8 port daughterboard for the ICP base board and supports V 35 operation C 1 Modem Clocks EIGH supports the full functionality of the serial communications controller SCC with respect to external and internal clock sources 1 1 Receive Clock Inputs TheReceive Clock and pinsarealwaysinputsto theSCC RxC inputs 0 7 are connected to the even numbered ports and odd numbered ports inputs of the SCCs C L2 Transmit Clock Inputs and Outputs
47. R Programming Function SCC Interrupt Request Ports 14 15 SCC Interrupt Request Ports 12 13 SCC Interrupt Request Ports 10 11 SCC Interrupt Request Ports 8 9 SCC Interrupt Request Ports 6 7 SCC Interrupt Request Ports 4 5 SCC Interrupt Request Ports 2 3 SCC Interrupt Request Ports 0 1 Uu 5 8 Peripheral DeviceDMA Controller 58 The SCC devices are served by a 32 channel DMA controller This controller is config ured so that for each communications port one channel is allocated to transmit and a separate channel is allocated to receive For each channel the controller stores a Memory Address Register M AR value and a Transfer Count TC valuein a dedicated 64 longword field at thetop of onboard main memory Refer to the General M emory M ap in Table 5 1 During operation a high speed state machine receives the DM A request and fetches the MAR and Terminal Count Register TCR valuesfrom memory TheM AR and TCR are incremented or decremented and replaced in memory The byte read or write cycle at the address specified by the M AR isthen conducted and the data transferred to or from the SCC TheDMA controller can interrupt thelocal processor on terminal count for both trans mit and receive operations An interrupt is generated when channel reachester minal count Each DMA channel has a separate interrupt vector DM A terminal count interrupts may be disable
48. Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 3 1 Table 3 2 Table 4 1 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 7 1 Table 7 2 Table A 1 Table A 2 Table B 1 Table B 2 Table 3 Table 4 Table B 5 Table C 1 Table 2 Table D 1 List of Tables IEP Haee REOR REESE 18 U39 ICP6000 ICP9000 Configuration 23 U7 ICP6000X ICP9000X Configuration 24 U 19 ICP6000 ICP9000 Configuration 25 U8 ICP6000X ICP9000X Configuration 27 Values for the Slave Address odifier Compare al VM EDUS SUIS 2u dd y dedo ER eg SESS eee RE 38 EEPROM Default MU orn PORE 41 Specifications for ICP 47 51 Genera Interrupt Map iss sek RR ER 55 Console Port Pin Assignments 57 MFP DDR Programming uua A 58 Protocol Exchange uuo dao or kay 77 Protocol Exchange Region for Download Ready Command 79 Clock Jumper Settings for 16 232 84 Pin Assignments for 16 port EIA 232 Cable Connectors 90 Clock Jumper Settings for 8 port MIL STD 188C or EIA 232 94 Jumper Settings for 8 port MIL STD 188C
49. Tr nemibClock Input ee ee RR 83 2 285 30 285230 Serial Communications Controller 86 Al SCC Register ACCESS sea cea ERERERRAS 86 AGI SEC VARI aac ee Bad Piia RO EORR 86 A23 SCC DMA qs ru dq dox pue 86 Bs s uou 86 BN a aos 86 CM IDA EUR XE OR E COE Rn 87 A 33 Data Detect 87 A 34 DataTermina Ready 87 A39 ECT 87 Connector Pin Assignments 88 B 8 portMIL STD 188C and 8 port EIA 232 Electrical Interface Module 93 Do 0155 Perm 93 B LI 5 93 B L2 Transmit Clock Inputs and 93 DC 900 0408 5 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 2 Z85C30 or 285230 Serial Communications Controller Bl CC Register ACCESS be pub dul de BJ SCC DDR ced kar ERA EE ERE Bid ui d acd dp REOR oko dr B 3 Driver Supply Voltages ra B 5 Interface Driver Wavehaping Interface Receiver Response Control cun us
50. arefeatures 18 Hardware overview 49 124 Hardware specifications 45 History of revisions 15 Indicator fault 68 68 VME access 68 Inspection 22 Installation VMEbus 35 Interface driver waveshaping 96 Interface receiver response control 97 Interface differential 106 Interface single ended 106 Interface VMEbus master 65 1 0 DMA command register 60 I O DMA indicator 68 J Jumpers U19 25 U39 23 U7 24 08 27 L Lines multiple 19 Local test 108 Loopback connections 43 LT see Local test M Mailbox interrupts 63 M ailbox slave address decoder 63 Mailboxes VMEbus 62 Main memory 55 MAR TCR memory locations 59 Memory main 55 Memory PROM 55 Microprocessor 49 MIL STD 188C electrical interface 93 Modeselection 30 Modem clocks 83 93 103 113 Modem control 86 97 106 116 DC 900 0408E Index Multi function peripheral 74 Multiplelines 19 0 Operating controls 68 Overview hardware 49 P Peripheral device DM A controller 58 Physical characteristics 45 Polarity transmit receive 96 Port select bits 61 Power requirements 45 Product support 15 PROM 55 Protocol exchangeregion 77 PurposeofthelCP 17 R rangeseect 61 Receive clock inputs 83 103 113 Receiveinterrupt 60 Receiver ready 116 Reference documents 14 Register access 57 Request mode select 66 Request to send 87 100 108 117 Response control interface receiver 97 Revision history 15 ROM checksum 73
51. ate SCC accesses C 6 3 Received Line Signal Detector The Received Line Signal Detector RLSD inputs 0 7 are connected to the RLSDA even numbered ports and RLSDB odd numbered ports inputs of the SCCsand are read using the appropriate SCC accesses DC 900 0408E 107 ICP6000 X ICP9000 X Hardware Description and Theory of Operation C 6 4 Data Terminal Ready and Local Test TheData Terminal Ready DTR outputs 0 7 and Local Test LT outputs 0 7 are con nected to a discrete hardware register and are written using two address decodes as shown in Figure C 3 Address 60000021 write only 7 6 5 4 3 2 1 0 LT7 LT6 LT5 LT4 LT3 LT2 LT1 LTO Address 60000022 write only 7 6 5 4 3 2 1 0 DTR7 DTR6 DTR5 DTR4 DTR3 DTR2 DTR1 DTRO FigureC 3 Data Terminal Ready and Local Test Address D ecodes C 6 5 Request To Send The Request To Send RTS outputs 0 7 are connected to the RTSA even numbered ports and RTSB odd numbered ports outputs of the SCCs and are written using the appropriate SCC accesses C 7 Connector Pin Assignments ThelCP is connected to thedistribution panel by two cables Each cable has a high den sity 80 pin connector on the ICP end and two 40 pin connectors on the distribution panel end FigureA 4 on page 88 shows the orientation of the pins on thelCP connec tor The connector nearer the console port debug port is designated B and the con nector farth
52. bottom justified EEPROM s used in this application must have write protection built in Table2 3 U 19 CP9000 Configuration Jumpers Installed DeviceType All Other K5 K6 K7 Removed 8K x8 28 EEPROM SRAM K6 1 to K6 2 K7 1to K7 2 32K x8 28 pin EEPROM SRAM K5 2 to K5 3 K6 1 to K6 2 K7 2 to K7 3 64K x8 28 pin PROM ROM 5 1 to K5 2 K6 2 to K6 3 K7 2 to K7 3 128K x8 32 pin PROM ROM K5 1to K5 2 K6 2 to K6 3 256K x8 32 pin PROM ROM K5 1to K5 2 K6 2 to K6 3 K7 1to K7 2 DC 900 0408E 25 26 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 2 5 4 U8 ICP6000X ICP9000X Pinout Configurations The jumpers at locations K5 K6 and K7 allow for variation in the pinout of the PROM ROM EEPROM SRAM socket U8 see Table 2 4 When installing a 28 pin device be surethat pin 14 of the device enters pin 16 of the socket bottom justified EEPROM s used in this application must have write protection built in DC 900 0408E 2 Unpacking and Configuration Table2 4 U8 ICP6000X ICP9000X Configuration DeviceType Jumpers Installed All Other K5 K6 K7 K8 K9 Removed 8Kx8 28 pin EEPROM SRAM 32Kx8 28 pin EEPROM SRAM 64K x8 28 pin PROM ROM 128Kx8 32 pin PROM ROM 256K x8 32 pin PROM ROM 512Kx8 32 pin PROM ROM 1024K x8 32 pin PROM ROM K6 1 to K6 2 K7 2 to K7 3 K5 2 to K5 3 K6 1 to K6 2 K7 2 to K7 3 K5 1to K5 2 K6 2 to K6
53. bus master interface This isolation ensures that the real time requirements of the SCCs DMA controller are not jeopardized by long processor accesses to the VM Ebus A VM Ebus M aster requests the VM Ebus with one of five priority levels and using one of two modes Bits for controlling the requester priority level and mode are found in Control Register 0 as shown in Figure 5 5 A VM Ebus Master also issues Address M odifier codes with each address The M as ter Interface obtains these codes from bitsin Control Register 1 as shown in Figure 5 6 A VMEbus Master must adapt to limitations and options in the system of which it isa part Control bitsto limit transfers to 16 bits and to perform internal data alignment are provided in Control Register 1 This allows operation with systems that do not support D 32 and or non aligned transfers DC 900 0408E 65 ICP6000 X ICP9000 X ardware Description and Theory of Operation Address 10000001 7 6 5 4 3 2 1 0 VMERMS VMEBR1 VMEBRO RCINT EEPDI EEPSK EEPCS FAULT Mnemonic Name Description VMERMS VMEbusRequetMode 0 ReleaseOn Request Select 1 Release When Done VMEBRI 0 VMEbus Bus Request These bits select the corresponding bus request Level level 0 3 after the next VM Ebus cycle arbitra tion completes Figure5 5 Control Register 0 Use for VM Ebus Bit 31 of the local address bus is used to decode VM Ebus accesses and is not available for direc
54. ces Device Specification Processor 68020 at 16 M Hz or 68030 at 30M Hz Main RAM 1 or 4 Megabytes D ynamic PROM EEPROM SRAM Two 32 pin JEDEC Byte Ports 1 32Kx8PROM 64Kx8 PROM or 128Kx8 PROM or 256Kx8 PROM or 512Kx8 PROM or 1024Kx8 PROM Socket2 8Kx8EEPROM or 8Kx8 SRAM or 32Kx8 EEPROM or 32Kx8 SRAM or 64Kx8 PROM or 128Kx8 PROM or 256Kx8 PROM or 512Kx8 PROM or 1024K x8 PROM VM Ebus M aster A32 A24 D 32 D 16 Block M ode Unaligned Transfers VM Ebus Slave A32 A24 A16 D8 0 DC 900 0408E 47 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 48 DC 900 0408E 5 1 Chapter Hardware Overview This chapter describes the CP6000 X I CP9000 X architecture memory map buses and design Figure 5 1 shows a block diagram of the board Table 5 1 showsthe alloca tion of memory space and Table 5 2 shows the interrupt levels sources and vectors All circuitry pinout and distribution panel information that applies to specific electri cal interfaces such as 232 EIA 422 and so on is found in Appendix A through Appendix D Internal Architecture The ICP VM controller allows accesses to the VM Ebus that are of indeterminate length and take place without compromising the ability of the 1 0 DMA controller to transfer data M any VM Ebus setup parameters usually associated with jumpers or switches are soft ware programmableon Ebus slave addr
55. coded and all bits are user selectable Refer to Section 5 11 on page 65 for the selection of these eight bits which are stored into Con trol Register 1 by the boot loader For A32 D 32 operation this variables recommended value is OX8D 32 DC 900 0408E 2 Unpacking and Configuration After selecting the appropriate values for these variables refer to the driver installation instructions for your host system in the appropriate ICP software installation guide These instructions will tell you how to define and initialize the variables The host driver uses these valuesto configure the V M Ebus master interface and interrupter each timethe host system is powered up DC 900 0408 33 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 34 DC 900 0408E Chapter VMEbus Installation This chapter describes how to install an ICP During installation you will perform the following steps Set the board select switches and jumpers e Plugin the console cable and ICP Check and set the EEPROM Attach the cables to the upper and lower ports Verify the hardware and software installation You should perform the software installation described in the CP6000 I CP9000 Soft ware Installation Guide for UNIX Products before proceeding with the following hard wareinstallation steps This avoids extra power up and power down cycles Step 1 Turn off the power to the host system Caution The ICP shou
56. ctory are external 2 This example shows two internal and two external clock jumper settings FigureD 1 8 port 422 Clock Jumper Settings 115 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation D 2 1 SCC Register Access Access to the SCC data and command registers is made using the addresses shown in Table5 10n page 51 H ardware protection is provided so that the SCC writerecovery limits are automatically met D 2 2 SCC Timebase The SCCs are driven from a 7 3728 MHz ICP6000 ICP9000 or 14 7456 MHz ICP6000X I C P9000X peripheral clock signal PCLK D 2 3 SCC DMA Each communications port is assigned two DMA channels one for transmitting and onefor receiving Section 5 8 on page 58 describes the setup and operation of theDMA controller D 3 Modem Control EIMJ supports four differential modem control signals two inputs Clear To Send and Receiver Ready and two outputs Terminal Ready and Request To Send These modem controls are connected to either the SCC or to dedicated hardware registers D 3 1 Clear To Send The Clear To Send CS inputs 0 7 are connected to the CTSA even numbered ports and CTSB odd numbered ports inputsof the SCCsand areread usingthe appropriate SCC accesses D 3 2 Receiver Ready The Receiver Ready RR inputs 0 7 are connected to the DCDA even numbered ports and DCDB odd numbered ports inputs of the SCCs and are read using the appropriate SCC accesses
57. d for receive channels only DC 900 0408E 5 Hardware Overview Thel O DMA controller is programmed using the O DMA Command Register and the M ARsand TCRs After programming the channel s SCC appropriately the channel buffer address is loaded into the channel s M AR memory location and thetransfer byte count into the channel s TCR memory location The channel is then started using a command to the 1 0 DMA Command Register 5 8 1 MAR TCR Memory Locations Each 1 0 DMA channel is assigned a dedicated longword near the top of the main memory as its M AR and a second longword as its TCR see Table 5 1 Each longword has 20 22 valid bits allowing an 1 0 DMA address range of 1 or 4 megabytes The MAR counts up and the TCR counts down asthe DM A operation progresses 5 8 2 DMA Terminal Count Interrupts Typical operation of SCCsin DMA modeisto have transmit completions signaled by DMA Terminal Count Interrupts and receive completions signaled by SCC Receive Complete Interrupts In this case the TCR value of receive channels is set to a value larger than the largest anticipated receive packet and the TCR acts as a safety net should arogue packet exceed anticipated size Transmit Channel Terminal Count Interrupts are generated by thel O DMA Controller at level 6 The vector number is determined by combining the number of the channel interrupting with a fixed base vector Vector numbers are in theform Fx hex where x is the po
58. e 68030 CPU running at 30M Hz Up to 16 synchronous asynchronous Serial protocols may beimplemented communications ports 32 channel DMA controller Full duplex DMA support provided for all 16 serial com munications channels aggregate bandwidth of 4 0 megabits second VM Ebus master interface Local processor has direct access to the V M Ebus VM Ebus slaveinterface ASIC 16 byte dual ported mailboxes with programmable slave address programmable interrupt of onboard CPU upon VM Ebus access of mailboxes VM Ebus interrupter with programmable level and vector and reset function initi ated by VM Ebus software EEPROM Storage of startup parameters EIA 232 console port Debugging of onboard code using port as console Two 32 pin JEDEC PROM sockets Space for power on diagnostics debugger boot loader and other code 1 2 ICP Applications ThelCP isageneral purposecomputer that do many different tasks At system star tup the gainsits run time personality from downloaded application software The application software may be customer specific or part of a Simpact connectivity prod uct The following are some typical applications for the ICP as a front end processor Communications ICP resident software can implement complex communica Protocols tions protocols freeing the host for end user tasks The pro grammable ICP can easily be reconfigured for many serial protocols and the software ca
59. ed with any further configuration and installation 2 Check for loose or missing hardware such as unseated ICs 2 4 Configuration 22 Configuration of the ICP takes place on two levels Jumper Configuration Thejumpers are generally set at the factory either to a fac Options tory default or to customer requirements T hese options do not usually requirefield alteration but should alteration be DC 900 0408E 2 Unpacking and Configuration necessary full configuration information is provided in Section 2 5 Software Programmable Many of the configuration options normally associated Configuration Options with jumpers or switches such as bus request level and mode and interrupt request level are software firmware controllable on the ICP This procedure is described in Section 2 6 2 5 Jumper Options Jumper options are typically installed at the factory to a default specification They may be changed using the information in the following sections 2 5 1 U39 IC P6000 1C P9000 Pinout Configurations The jumpers at locations K1 and K2 allow for variationsin the pinout of PROM ROM socket U 39 see Table 2 1 When installing 28 pin devices be sure that pin 14 of the device enters pin 16 of the socket bottom justified Table 2 1 U 39 IC P6000 1C P9000 Configuration Jumpers Installed DeviceType All Other K1 K2 Removed 32K x8 28 pin PROM ROM K1 2 to K1 3 K2 2 to K2 3 64K x8 28 pin PROM ROM K1 2 to K
60. er away is designated A See Figure 5 7 on page 69 for the location of the connectors 108 DC 900 0408E C 8 port V 35 CCITT Electrical Interface M odule Adapter cables are used to map the 25 pin D connector pinout on a distribution panel to theV 35 connector shown in Figure 4 Table C 2 shows the signal mapping for the cables that connects the ICP to the distri bution panel Figure C 4 shows the V 35 connector with the supported signals their proper signal names and the mnemonics used in Table 2 PIN PIN Signal Ground GND B Clear to Send CTS D C Request to Send RTS Received Line Signal Detect RLSD E DataSet Ready DSR Calling Indicator H Data Terminal Ready DTR K Local Test LT Receive Data RD A Receive Data RD B Serial Clock Receive SCR A Serial Clock Receive SCR B Send Data SD A Send Data SD B Serial Clock Transmit External SCTE A Serial Clock Transmit External SCTE B Serial Clock Transmit SCT A Serial Clock Transmit SCT B 095 DRWG 2566 Signal suffixes A and B refer to differential signal pairs Figure C 4 V 35 Interface DC 900 0408 109 ICP6000 X ICP9000 X ardware Description and Theory of Operation TableC 2 Pin Assignmentsfor 8 port V 35 Cable Connectors 80 pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal A 1 8 1 00 GND A 41 9 1 02 GND A 2 8 2 00 GND A 42 J9
61. erview of the The ICP intelligent communications processor is an ancillary computer dedicated to the processing of communications related data ThelCP 15 asingle board computer that has central processing unit CPU random access memory RAM programmable read only memory PROM and input output 1 0 circuitry The software consists of an onboard operating system diagnostic tests host interface drivers and application routines 1 1 Purpose of The main purpose of the ICP isto improve the overall computing efficiency of the host computer To do this low level communications tasks that are traditionally performed by the host central processor are migrated to the ICP An ICP increases overall system bandwidth by distributing the 1 0 processing away from the host CPU In the traditional minicomputer architecture the host services all 1 0 requests This load on the CPU has grown steadily as computer peripherals have become increasingly more powerful M odern operating systems allow intelligent front end processors to perform these relatively simple tasks The result is an overall increase in system throughput Table 1 1 summarizes the features of the CP DC 900 0408E 17 ICP6000 X ICP9000 X ardware Description and Theory of Operation Table 1 1 Hardware Features Feature Description 68020 CPU running at 16 MHz or High performance processor with linear addressing spac
62. ess nc kv ee RR tee dees 27 NCC TIME eua ded nob RoE RR OA Dog XL DM rs ud Dal Cher TO NR o 0 3 2 Receiver Ready D33 Tamina BOND D 34 Request Send D 4 Connector Pin Assignments Index DC 900 0408E ICP6000 X ICP9000 X Hardware Description and Theory of Operation 8 DC 900 0408E Figure 2 1 Figure 3 1 Figure 3 2 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 7 1 FigureA 1 FigureA 2 FigureA 3 Figure 4 Figure 5 Figure B 1 Figure B 2 Figure B 3 Figure B 4 FigureC 1 List of Figures EEPROM Boot Pad VOIE ado CC 30 ICP6000 X ICP9000 X Switch Settings 37 ICP6000 X Labeling and Loopback Connections 43 ICP6000 X ICP9000 X Block Diagram 50 Control Register 0 Usefor DMA 60 I O CommandRegister 61 Status Register Usefor DMA 62 Control Register 0 Use for VM EbuS 66 Cono REE Decor ue a eis e SEWER 67 ICP Front Panel ShowingLocationofLEDs 69 Control Register 0 Use for FAULT 70 Control Register 0
63. ess master request level and master request mode are programmable by the local processor An EEPROM is provided for non volatile storage of these parameters The board select switches accessible to the firmware are provided for those applications that demand a manual input see Section 5 14 5 2 Microprocessor ThelCP6000 l CP9000 uses a otorola 68020 microprocessor running at 16 M Hz The I CP6000X I CP9000X uses a M otorola 68030 microprocessor running at 30 M Hz DC 900 0408 49 ICP6000 X ICP9000 X Hardware Description and Theory of Operation ncomsc lt 50 a Base M odule Interrupts L Buffer 32 EPROM or EEPROM 32 channel Electrical Interface Module 1 Interface 0298 Figure5 1 ICP6000 X I CP9000 X Block Diagram DC 900 0408E 5 Hardware Overview Table5 1 General M emory M ap Memory Range hex Device 00000000 0001FFFF or 00000000 0003FFFF 00020000 OFFFFFFF or 00040000 OFFFFFFF 10000000 10000001 10000002 10000003 20000000 20000001 20000002 20000003 20000004 20000005 20000006 20000007 20000008 20000009 2000000A 2000000B 2000000C 2000000D 2000000E 2000000F 20000010 20000011 20000012 20000013 Read only M emory Socket U 39 or U 7 jumper selectable K3 Read Write M emory Socket U 19 or U8 jumper selectable K 3 1 0 DMA Command Register write only byte wide General Control Register 0 write only b
64. f Operation 1 Shield Signal Ground SG 20 5 21 Send Data SD B 22 4 Send Data SD A Send Timing 5 23 o 5 SendTiming ST A ReceiveData RD B 24 6 Receive Data RD A Request to Send RS B 25 7 Request to Send RS A ReceiveTiming RT B 26 8 ReceiveTiming RT A Clear to Send CS B 27 9 Clear to Send CS A 28 10 29 11 Terminal Ready TR B 30 12 Terminal Ready TR A Receiver Ready RR B 31 BS 13 Receiver Ready RR A 14 33 15 34 16 Terminal Timing TT B 35 17 Terminal Timing TT A 18 Signal Ground SG 37 19 Signal Ground SG DRWG 2565 FigureD 3 EIA 449 Interface 118 DC 900 0408E D 8 port 422 Electrical Interface M odule 1 Shield Send Data 50 14 s 2 Send Data SD A Send Timing ST A 15 3 Receive Data RD A Receive Data RD B 16 MM 4 Request to Send RS A ReceiveTiming RT A 17 5 Clear to Send CS A 18 Request to Send RS B 19 7 Signal Ground SG Terminal Ready TR A 20 8 Receiver Ready 9 Receive Timing RT B 10 Receiver Ready RR B Terminal Ready TR B 23 a 2 11 Terminal Timing TT B Terminal Timing TT A 24 un 12 SendTiming ST B 13 Clear to Send CS B DRWG 2610 FigureD 4 EIA 530 Interface DC 900 0408 119 ICP6000 X ICP9000 X Hardware Description and Theory of Operation TableD 2 Pin Assignments for 8 port 422 Cable Connectors 80
65. gister A 3 1 Data Set Ready The Data Set Ready DSR inputs 0 15 are connected to a discrete hardware register and read using two address decodes as shown in FigureA 2 86 DC 900 0408E A 16 port EIA 232 Electrical Interface M odule Address 60000020 read only 7 6 5 4 3 2 1 0 DSR14 DSR12 DSR10 DSR8 DSR6 DSR4 DSR2 DSRO Address 60000021 read only 7 6 5 4 3 2 1 0 DSR15 DSR13 DSR11 DSR9 DSR7 DSR5 DSR3 DSR1 FigureA 2 Data Set Ready Address Decodes A 3 2 Clear To Send The Clear To Send CTS inputs 0 15 are connected to the CTSA even numbered ports and CTSB odd numbered ports inputs of the SCCs and are read using the appropriate SCC accesses A 3 3 Data Carrier Detect The Data Carrier Detect DCD inputs 0 15 are connected to the DCDA even num bered ports and DCDB odd numbered ports inputs of the SCCs and are read using the appropriate SCC accesses A 3 4 Data Terminal Ready The Data Terminal Ready DTR outputs 0 15 are connected to a discrete hardware register and are written using two address decodes as shown in FigureA 3 A 3 5 Request To Send The Request Send RTS outputs 0 15 are connected to the RTSA even numbered ports and RTSB odd numbered ports outputs of the SCCs and are written usingthe appropriate SCC accesses DC 900 0408E 87 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation Address 60000021 wri
66. hecksum subtest sums the bytes of the onboard PROM This value is then compared to the precalculated checksum located in ROM checksum word at address 0x7C of the EEPROM see Table 3 2 on page 41 6 1 2 Dynamic RAM DRAM The DRAM subtest performs a series of pattern comparisons on the CP s one or four megabytes of DRAM The patterns are Alternating bits Checkerboard with lookahead DC 900 0408 73 ICP6000 X ICP9000 X Hardware Description and Theory of Operation Unique address check All ones with zeros lookahead All zeros with lookahead using read modify write RM W cycles 6 1 3 68901 Multi function Peripheral MFP Subtests performed by the are Write read compare of the M FP local registers Countdown by timersA and B Interrupt generation by timersA and B nterrupt generation by the software timer 6 1 4 VMEbus Slave Interface VSI Subtests performed on the VSI are Mailbox registers write read compare Mailbox unique address check Mailbox registers RM W cycle check 6 1 5 EEPROM The EEPROM is tested by performing ten read cycles of locations zero and two of the EEPROM In order for the test to pass the values read must be OxCAFE and OxFOOD respectively 74 DC 900 0408E 6 Diagnostics 6 1 6 DMA Controller TheDMA controller is verified by the following subtests DMA controller command check DMA controller interrupt check Transfer count registers
67. hes LEDs Daughterboard Switches may bein either location on 80 pin the board Connectors VM Ebus Connectors Console Port 2217 Figure 3 1 CP6000 X ICP9000 X Switch Settings DC 900 0408 37 ICP6000 X ICP9000 X ardware Description and Theory of Operation 38 Table3 1 VM Ebus Settings Base Address IC p Select Board Select Number Number 5 6 SW5 SW4 SW3 SW2 SW1 VMEbusSlaveAddress ICPx 0 0 X X X X Goto PTBUG ICPO 1 0 0 0 0 1 2000000 ICP1 1 0 0 0 1 0 4000000 2 1 0 0 0 1 1 F6000000 1 0 0 1 0 0 F8000000 ICP4 1 0 0 1 0 1 FA000000 ICP5 1 0 0 1 1 0 FC000000 ICP6 1 0 0 1 1 1 FE000000 ICP7 1 0 0 0 0 0 F0000000 ICP8 0 1 0 0 0 0 FE000000 ICP9 0 1 0 0 0 1 FE000200 ICP10 0 1 0 0 1 0 FE000400 ICP11 0 1 0 0 1 1 000600 ICP12 0 1 0 1 0 0 FE000800 ICP13 0 1 0 1 0 1 FE000A00 ICP14 0 1 0 1 1 0 FE000C00 ICP15 0 1 0 1 1 1 FEO00E00 ICP16 0 1 1 0 0 0 FE001000 ICP17 0 1 1 0 0 1 FE001200 18 0 1 1 0 1 0 FE001400 19 0 1 1 0 1 1 FE001600 20 0 1 1 1 0 0 FE001800 21 0 1 1 1 0 1 FE001A00 22 0 1 1 1 1 0 FE001C00 23 0 1 1 1 1 1 1 1 X X X X Useaddress etc as defined in EE memory and disre gard board select Note Ois off 1 DC 900 0408E 3 VM Ebus Installation Step 5 Insert the ICP so that the component side is facing the same direction as the other boards in the backplane If no other
68. in RAM low word 0 26 Number of bytes of startup code to move high word 0 28 Number of bytes of startup code to move low word 600 2A Startup code execution address high word 400E 2C Startup code execution address low word 020A 2E Slave address compare high word 0000 or 9 30 Slave address compare low word F600 0200 32 M ode selection 34 4 34 Slave address modifier compare 20 36 Slave address modifier don t care F 38 Master enable 60 7 Reserved PTBUG is used to verify these values P Entries shown with a b are configurable options See Figure 2 1 on page 30 for further information about the boot flags d This value is determined by the board select switches shown in Figure 3 1 on page 37 DC 900 0408E 41 ICP6000 X ICP9000 X ardware Description and Theory of Operation 42 Step 8 When EEPROM programming is complete enter BO CR to re enter the download routine Step 9 Attach the cables to the upper and lower ports Install the loopback cable from Port 0 to Port 1 in preparation for verification testing Refer to Figure 3 2 Step 10 If you previously performed the software installation to configure the new kernel or boot operating system for Simpact s hardware power on the system to boot the new kernel or operating system Otherwise boot the existing kernel and refer to the 9 Software Installation Guide for UNIX Products to perform the soft
69. ing the addresses shown in Table5 10n page 51 H ardware protection is provided so that the SCC writerecovery limits are automatically met 94 DC 900 0408E B 8 port MIL STD 188C and 8 port EIA 232 Electrical Interface M odule Internal External O Port 7 K9 6 e Port 7 O Port6 K10 e Port6 5 5 Port4 K12 e Port4 Port 3 K13 o Port 3 Port2 14 Port2 Port1 K15 9 1 PortO K16 e PortO f Ll 2 Zz EY X 7 ES d TM Se q 4 E 80 pin Conn tors D aughterboard Console Port Notes 1 settings from the factory are external VM Ebus Connectors DRWG 2222 2 This example shows oneinternal and seven external clock jumper settings 3 You must alsoset the distribution panel jumpers to match these settings FigureB 1 8 port MIL STD 188C or EIA 232 Clock Jumper Settings DC 900 0408 95 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation B 2 2 SCC Timebase The SCCs are driven from a 7 3728 MHz ICP6000 ICP9000 or 14 7456 MHz ICP6000X I CP9000X peripheral clock signal PCLK B 2 3 SCC DMA B 3 Each communications port is assigned two channels one for transmitting and the other for receiving Section 5 8 on page 58 describes the setup and operation of the DMA controller
70. ion Value hex Download ready 10 Write block 04 Init procedure 08 The following function codes are written to the i cmd field by the ICP Function Value hex Download request 80 Acknowledge ACK 04 Negative acknowledge NAK 10 Theremaining fields of the PXR are always written by the host and read by the For a particular function these fields should be filled in before writing the function code to theh_cmd field Theh bytes field isa 16 bit valuewith the high order byte in mailbox 2 and the low order byte in mailbox 3 Theh iaddr and h haddr fields are each 32 bits with the high order byte in the lowest numbered mailbox 4 or 8 and the low order byte in the highest numbered mailbox 7 or 11 7 2 Download Procedure 78 On power on or reset the self test diagnostics execute and on completion pass control to the boot loader The boot loader which is not interrupt driven initializes and clears the mailboxes then begins polling the h cmd field of the PXR waiting for a download ready function code to be stored in the field by the host When download ready 15 received the boot loader acknowledges the host by storing an ack function codein the i cmd field Before beginning the download the host should reset the CP to ensure that the system isin a known state and that the boot loader is running To reset the write the value OxAA to the software reset register at offset 0x3D in the 512 byte region of VM Ebus D
71. ions apply throughout this document When a model number is not mentioned ICP or ICP6000 X ICP9000 X refers to all models including the ICP6000X ICP9000X The ICP6000 and I CP9000 consist of the same board housed in different form factors A signal name that appears with an overline for example ECS indicates that the signal is asserted low Hexadecimal values are shown preceded by the characters Ox or with the nota tion hex Bitsarenumbered from rightto left beginning with zero Bit zero isthelow order bit Revision History The revision history of the ICP6000 X ICP9000 X ardware Description and Theory of Operation Simpact document D C 900 0408E is recorded below DocumentRevision Release Date Description DC 900 0408E January 1998 Converted to FrameM aker 5 U pdated for the high speed ICP 6000X Customer Support If you are having trouble with any Simpact product call us at 1 800 275 3889 M onday through Friday between 8 a m and 5 p m Pacific time You can also fax your questions to us at 619 560 2838 or 619 560 2837 any time Please include a cover sheet addressed to Customer Service We are always interested in suggestions for improving our products You can use the report form in the back of this manual to send us your recommendations DC 900 0408E 15 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 16 DC 900 0408E Chapter Ov
72. is activated when mailbox 7 is written and 1 autovector 2 is activated when mailbox 8 is written 1 Load a value of 0x02 into Mailbox Interrupt Pin Select 3 0 offset 0x12 This routes mailbox 0 to LIRQ2 autovector 1 DC 900 0408E 63 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 2 Similarly load a value of 0x00 into Mailbox Interrupt Pin Select 7 4 offset 0x13 and a value of 0x01 into M ailbox Interrupt Pin Select 11 8 offset 14 3 Enable mailbox 0 7 and 8 interrupts by loading a value of 0x81 into Mailbox Interrupt M ask 7 0 offset 0x10 and a value of 0x01 into M ailbox Interrupt M ask 15 8 offset 0x11 5 9 5 Software Reset The software controlled reset location is connected directly to the local reset pin and cannot be disabled except by disabling the VSI VM Ebus address decode A reset is gen erated when a value of is written to the Software Reset Register by the VM Ebus 5 10 VMEbus Interrupter TheVM Ebus Interrupter is integrated into the VSI Two VSI registers are used to con trol the interrupter The V M Ebus Interrupt Request Level Register specifies the desired interrupt level and also contains interrupter done status bits The VM Ebus Interrupt Request Vector Number Register specifies the desired interrupt vector and initiates the interrupt The VM Ebus interrupter is normally programmed by system level down loaded code provided by Simpact The progra
73. ith these techniques take the following precautions Always work at a static safe workstation wearing thestatic guard wrist strap pro vided with each installation kit Directions for using the wrist strap are on the back of the package Leavetheboard insideits antistatic plastic bag until you are ready to inspect con figure or install the board When inspecting or configuring the board keep the solder side in direct contact with the antistatic bag DC 900 0408 21 ICP6000 X ICP9000 X ardware Description and Theory of Operation Return the board to the bag immediately after inspection configuration or removal from the host backplane 2 2 UnpackingthelCP Inspect the shipping carton for any damage that may have occurred during shipment If such damage is noted an agent of the shipping carrier should be present at any fur ther unpacking and contents inspection Remove the packing list and check it against the items shipped to ensure that you have received the correct board cables and so on Carefully removethe board from its antistatic bag and observe normal electrostatic dis charge precautions described in Section 2 1 as you inspect the board for shipping damage 2 3 Initial Inspection Usethefollowing procedure when inspecting your board 1 Check overall appearance for breaks or cracks that may have occurred during shipping If such damage is noted report it to Simpact Inc and do not proce
74. ld never be inserted into or removed from the VM Ebus cardcage while power is applied Insertion or removal with power applied could seriously damage the system or the ICP components DC 900 0408 35 ICP6000 X ICP9000 X ardware Description and Theory of Operation Step 2 Refer to the documentation provided with your host system for instructions on install ing boards in the VM Ebus cardcage 115 documentation should explain how to access and set the daisy chain backplane jumpers and Bus Grant Other preparations Such as setting jumpers on the system s CPU board may also be required Note If the host system s daisy chain backplane jumpers are not set cor rectly the system or the will not operate Step 3 Set the board select switches to the desired position as defined by the required ICP address Figure 3 1 shows where the switches are on the CP Table 3 1 shows the valid settings for the switches and the V M Ebus address configured for each Note An easy way to remember the orientation of the board select switches is For debug set all switches ON toward the console port for host mode set all switches OFF toward the V M Ebus Step 4 The jumpers from the factory are set for internal clocking Refer to the appropriate appendix for your electrical interface for figures showing the jumper locations on the 36 DC 900 0408E 3 VM Ebus Installation Switc
75. mming sequence is summarized below Details are available in the VM Ebus Slave Interface VSI manual 1 Poll the VMEbus Interrupt Request Level Register until status indicates not busy 2 Load the desired request level into the VM Ebus Interrupt Request Level Register 3 Load the desired vector number into the VM Ebus Interrupt Vector Number Reg ister Thisload initiatesthe interrupt process 4 Theinterrupter goes busy asindicated by the Interrupt Request Level Register and remains busy until the VM Ebus interrupt acknowledge cycle is completed 64 DC 900 0408E 5 Hardware Overview Optionally one of the LIRQ pins can be configured as an interrupter done interrupt 5 11 VMEbus Master Interface The ICP allows the local processor to have direct access to the VM Ebus through the VM Ebus M aster Interface VM Ebus access appears as a portion of the local processor memory map and can be freely read from or written to using full A32 D 32 capability During V M Ebus accesses AM 0 5 and A31 are supplied from a local register All byte position translations and unaligned transfers are automatically performed The VM Ebus request level and request mode Release W hen Done and Release On Request are software programmable Because V M Ebus accesses may be of indeterminate length due to bus contention from unknown sources the ICP provides a level of logical isolation between the local mem ory array and the VM E
76. n be modified when protocol requirements change 18 DC 900 0408E 1 Overview Multiple Lines Data Acquisition Device Control DC 900 0408 Multiple communication ports enable ICP to perform net work management functions such as message routing error logging line usage monitoring and various checkout and test ing functions CP resident software can poll remote stations for status mes sages or maintain a database of alarm point states Additional remotestations can be handled easily and economically by add ing ICPs ThelCP is effective in formatting or modifying large amounts of output data in ways that are inefficient or inappropriate at the host level 19 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 20 DC 900 0408E Chapter Unpacking and Configuration This chapter describes how to unpack and configure an ICP 2 1 Antistatic Precautions ThelCP circuit board contains integrated circuits that are sensitive to electrostatic dis charge ESD that is static electricity Improper handling can damage the ICP and result in symptoms ranging from unreliable operation to total failure Caution DN a Never handle the when it is outside its protective bag without wearing a static guard wrist strap or taking an equivalent ground ing precaution Standard ESD handling precautions are sufficient to protect the ICP If you are not familiar w
77. ngle ended linereceiversthat meet theV 35 specifications without the use of external capac itors C 5 Differential Interface EIGH is equipped with XR T 3588 V 35 drivers and XR T 3589 V 35 receivers that are designed to meet the requirements of the V 35 specification The differential lines are terminated externally to the drivers and receivers C 6 Modem Control EIGH supports seven single ended modem control signals four inputs Data Set Ready CallingIndicator Clear To Send and Data Carrier Detect and three outputs Data Ter 106 DC 900 0408E C 8 port V 35 CCITT Electrical Interface M odule minal Ready Local Test and Request To Send These modem controls are connected to either the SCC or to dedicated hardware registers C 6 1 Data Set Ready and Calling Indicator The Data Set Ready DSR inputs 0 7 and Calling Indicator CI inputs 0 7 are con nected to a discrete hardware register and are read using two address decodes as shown in Figure C 2 Address 60000020 read only 7 6 5 4 3 2 1 0 6 4 CI2 CIO DSR6 DSR4 DSR2 DSRO Address 60000021 read only 7 6 5 4 3 2 1 0 7 5 Cll DSR7 DSR5 DSR3 DSR1 FigureC 2 Data Set Ready and Calling Indicator Address D ecodes C 6 2 Clear To Send TheClear To Send CTS inputs 0 7 are connected to the CTSA even numbered ports and CT SB odd numbered ports inputs of the SC Cs and areread using theappropri
78. onsole port 56 Controller ready 62 CS see Clear to send CTS see Clear to send Customer support 15 D Data acquisition 19 Data carrier detect 87 99 107 Data set ready 86 98 107 Data terminal ready 87 100 108 DCD see Data carrier detect Decoder mailbox slave address 63 Devicecontrol 19 Device specifications 46 Diagnostic error display 30 Diagnostic execution 30 Diagnostic tests 73 DMA controller 75 DynamicRAM 73 EEPROM 74 multi function peripheral 74 123 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation ROM checksum 73 VM slave interface 74 Differential interface 106 DMA controller 75 DMA controller ready 62 DMA controller peripheral device 58 DMA receiveinterrupt 60 DMA terminal count interrupts 59 Document conventions 15 Documents reference 14 Download message format 77 Download procedure 78 DRAM 73 DRAM memory size 30 Driver supply voltages 96 106 DSR see Data set ready DTR see Data terminal ready DynamicRAM 73 E EEPROM 74 EEPROM boot flag word 30 EEPROM chip select 70 EEPROM datain line 70 EEPROM dataoutline 71 EEPROM serial clock line 70 EIA 232 16 port electrical interface 83 EIA 232 8 port electrical interface 93 EIA 449 8 port electrical interface 113 Electrical interface 16 port EIA 232 83 8 port EIA 232 93 8 port EIA 449 113 8 port MIL STD 188C 93 8 port V 35 Bell 306 103 Environment 46 F Fault 70 Fault indicator 68 H Hardw
79. or when VM Ebus accesses are made A flexible system of controls allows this monitor interrupt function to be adapted to spe cific firmware requirements TheVSI also provides the VM Ebus interrupter function This interrupter is fully pro grammable Both request level and vector number can be selected by software DC 900 0408E 5 Hardware Overview Address 10000000 7 6 5 4 3 2 1 0 5851 5850 CSS T R PORT Mnemonic Name Description SRS Scanner Range Select These bits select one of four request scanner ranges for the peripheral DMA controller M aximum peripheral DMA performance is achieved when the scanner range covers only the active channels 0 0 Scan ports 0 15 01 Scan ports 0 7 10 Scan ports 0 3 11 Scan ports 0 1 CSS Channel Start Stop This bit commandsthe channel addressed by T R and PORT 3 0 0 Start Channd DMA 1 Stop Channel T R Transmit or Receive Channel This bit selects either the transmit or receive channel for the port selected by PORT 3 0 0 Receive Channel Selected 1 Transmit Channel Selected PORT Port Select Bits This nibble may contain a value between 0 DC 900 0408 and OxF and along with the T R bit selects the DMA channel to be started or stopped Figure5 3 1 0 DM A Command Register 61 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation Address 10000003 7 6 5 4 3 2 1 0 SW6 SW5 EEPDO DMARDY SW4 SW
80. ound in the appendices of this manual DC 900 0408E 5 Hardware Overview Table 5 3 Console Port Pin Assignments EIA 232 Front Panel P4 25DsubPin Connector Pin Description 1 1 Ground 2 3 Transmit Data driven by ICP 3 5 Receive Data received by ICP 4 7 Jumpered to P4 9 5 9 Jumpered to 4 7 6 11 Jumpered to 4 14 7 13 Ground 8 10 Reserved for NM switch 12 Reserved for Reset switch 8 19 Not connected 20 14 Jumpered to P4 11 21 25 Not connected 5 7 1 Register Access Direct access to the SCC registers can be made by using the addresses listed in the gen eral memory map see Table 5 1 5 7 2 SCC Interrupts The parallel 1 0 port of the MFP is used to receive interrupt requests from the SCCs residing on the EIM daughterboard The M FP s Data Direction Register DDR should be programmed so that all bits are inputs see Table 5 4 The Active Edge Register AER should be programmed so that all bits are triggered by the falling edge When SCC asserts its interrupt line the MFP causes an interrupt request to the 680x0 on level 5 Theinterrupt vector is based on the SCC requesting the interrupt and the con tents of the M FP Vector Register VR TheVector Register should not be programmed for base of or OxF0 as these vector ranges are reserved for thel O DMA control ler DC 900 0408E 57 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation Table5 4 MFP DD
81. ownload request function code to the i cmd field On receipt of the download request the host stores the address of a block of code data in theh haddr field of the PXR stores the onboard transfer address for the block in the h iaddr field and stores the byte count in theh count field The host then stores a write block function code cmd field DC 900 0408 79 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 80 On receipt of a write block command the boot loader validates the load address spec ified by the host in thePXR and if itisa valid RAM address transfers the block of data from the specified host address to the load address and stores an ACK function code in the i_cmd field to acknowledge completion of the operation The boot loader stores a function codein the i cmd field if the load address is invalid When the host has read the ACK or the boot loader stores another download request function code in the i field On receipt of the download request the host prepares the next block of code data and issues another write block command This process continues until the final block has been transferred to the ICP When it receives the next download request from the boot loader the host usesthe init procedure function code to begin execution of the downloaded code For this function the host must write the onboard execution addressto theh iaddr field of the PXR and store an ini
82. pin 40 pin 80 pin 40 pin Connector Connector Port Signal Connector Connector Port Signal A 1 8 1 00 SG 41 9 1 02 SG 2 8 2 00 SG A 42 J9 2 02 SG A 3 J8 3 00 RD B A 43 J9 3 02 RD B A 4 8 4 00 RD A 44 J9 4 02 RD A A 5 J8 5 00 RT B A 45 J9 5 02 RT B A 6 J8 6 00 RT A A 46 J9 6 02 RT A A 7 J8 7 00 CS B A 47 J9 7 02 CS B A 8 J8 8 00 CS A A 48 J9 8 02 CS A A 9 8 9 00 RR B A 49 J9 9 02 RR B A 10 J8 10 00 RR A A 50 J9 10 02 RR A A 11 18 11 00 ST B A 51 J9 11 02 ST B A 12 J8 12 00 ST A A 52 J9 12 02 ST A A 13 8 13 00 SD B A 53 9 13 02 SD B A 14 J8 14 00 SD A 54 9 14 02 SD A A 15 J8 15 00 RS B A 55 J9 15 02 RS B A 16 J8 16 00 RS A A 56 J9 16 02 RS A A 17 J8 17 00 TR B A 57 J9 17 02 TR B A 18 J8 18 00 TR A A 58 J9 18 02 TR A A 19 J8 19 00 TT B A 59 J9 19 02 TT B A 20 J8 20 00 TT A A 60 J9 20 02 TT A A 21 J8 21 01 SG A 61 J9 21 03 SG A 22 J8 22 01 SG A 62 J9 22 03 SG A 23 J8 23 01 RD B A 63 J9 23 03 RD B A 24 J8 24 01 RD A A 64 J9 24 03 RD A A 25 J8 25 01 RT B A 65 J9 25 03 RT B A 26 J8 26 01 RT A A 66 J9 26 03 RT A A 27 J8 27 01 CS B 67 9 27 03 CS B A 28 J8 28 01 CS A A 68 J9 28 03 CS A A 29 J8 29 01 RR B A 69 J9 29 03 RR B A 30 J8 30 01 RR A 70 9 30 03 RR A A 31 8 31 01 ST B A 71 9 31 03 ST B A 32 8 32 01 ST A A 72 J9 32 03 ST A A 33 J8 33 01 SD B A 73 9 33 03 SD B A 34 J8 34 01 SD A A 74 J9 34 03 SD A A 35 J8 35 01 RS B 75 9 35 03 RS B A 36 J8 36 01 RS A 76 J9 36 03 RS A A 37 J8 37 01 TR B 7
83. pped with both a driver and a receiver for this line The TxC0 15 drivers and receivers are selected using the jumper settings shown in Table A 1 Refer also to FigureA 1 DC 900 0408E 83 ICP6000 X ICP9000 X Hardware Description and Theory of Operation Caution p You must also set the jumper on the distribution panel and usethe protocol software to configure the desired clocking Table A 1 Clock Jumper Settings for 16 port 232 Transmit Clock Source Port Internal DTE External DCE 0 K9 1 2 K11 2 1 K10 1 2 K2 1 2 2 1 2 K31 2 3 K12 1 2 K41 2 4 K13 1 2 K5 1 2 5 K14 1 2 K6 1 2 6 K15 1 2 K7 1 2 7 K16 1 2 K8 1 2 8 K25 1 2 K17 1 2 9 K26 1 2 K18 1 2 10 K27 1 2 K191 2 11 28 1 2 20 1 2 12 29 1 2 21 1 2 13 K30 1 2 22 1 2 14 K311 2 K231 2 15 K321 2 K24 1 2 a Only one jumper per port 84 DC 900 0408E A 16 port EIA 232 Electrical Interface M odule inr 5555555565 4 gt External 0000000 m sti OR 1 Internal ogsdamunsaus 80 pin Connectors Daughterboard VMEbus Connectors 55555555 a L L External S8ASHANS Console 1 900002000 ing Port
84. ption and Theory of Operation 2 6 2 Configuring the VM Ebus Master Interface and Interrupter ICP allows the local processor to have direct access to the VM through the VM Ebus master interface In addition the VM Ebus interrupter enables the ICP to gen erateV M Ebus interrupts at a given level and vector Configuration of theV M mas ter interface and interrupter is accomplished each time the ICP is reset when the host driver passes the relevant parameters to the ICP s boot loader as the first step of the download procedure described in Chapter 7 Thefollowing 8 bit external variable arrays must be defined by the user during driver installation One element in each array must be initialized for each I CP configured into the host system icp vector This variable is the vector number to be supplied to the VM Ebus as part of theinterrupt process icp level This variable is the interrupt request level at which the inter rupt will be generated by the ICP icp request A portion of this variable specifies the VM Ebus request mode and the VM Ebus bus request level This value is bit encoded and must take the form xxx10001 where xxx are the user programmable bits for VM ERMS VM 1 and VM EBRO Refer to Section 5 11 on page 65 The recommended value for this variableis OxF 1 icp options This variable specifies the data size and address parameters for VM Ebus master mode data transfers This valueis bit en
85. ption and Theory of Operation 5 12 Operating Controls and Indicators This section describes the LEDs on the board Figure 5 7 shows their locations on the ICP 5 12 1 Fault Indicator The ICP FAULT indicator is a red LED controlled by a bit in Control Register 0 as shown in Figure 5 8 5 12 2 1 0 DMA Indicator The green 1 0 DM A indicator is illuminated whenever the local DMA controller has control of theinternal bus TheLED illumination intensity is a relative indication of the DMA activity 5 12 3 VME Access Indicator The green VM indicator is illuminated whenever the ICP is accessing the VM E bus 5 13 Serial EEPROM Operation Theserial EEPROM stores setup parameters and is reserved for use by the PROM based code Accessing the serial EEPROM is a software intensive operation because the con trol lines Chip Select Clock Data In and Data Out must manipulated on a bit by bit basisto clock data into or out of the EEPROM Consult the EEPROM manufactur ers documentation regarding the required timing and control The output lines Chip Select Clock and Data In are controlled from bits in Control Register 0 see Figure 5 9 Theinput line Data Out is accessed from the Status Reg ister see Figure 5 10 68 DC 900 0408E 5 Hardware Overview Red LED Green LEDs Lower ports 80 pin connectors U pper ports Solder side Component side Console port connector
86. r 62 slave interface 60 74 software reset 62 VM address bit 31 67 VM Ebus address modifier codes 67 VM Ebus data alignment 67 VMEbus datasize 67 VMEbus installation 35 VMEbus request level 66 VMEbus request modeselect 66 Voltages driver supply 106 voltages driver supply 96 VSI see VM slave interface Waveshaping interface driver 96 126 DC 900 0408E SIMPACT IC P6000 X 1 9000 Hardware Description and Theory of Operation DC 900 0408E Customer Report Form We are constantly improving our products If you have suggestions or problems you would liketo report regarding the hardware software or documentation please complete this form and mail it to Simpact at 9210 Sky Park Court San Diego CA 92123 or fax it to 619 560 2838 If you are reporting errors in the documentation please enter the section and page number Your Name Company Address PhoneNumber Product Problem or Suggestion Simpact Inc Customer Service 9210 Sky Park Court San Diego CA 92123
87. rces 1 1 Receive Clock Inputs TheReceive Clock and pins are always inputs to theSCC RxC inputs 0 7 are connected to the even numbered ports and odd numbered ports inputs of the SCCs B L2 Transmit Clock Inputs and Outputs The Transmit Clock TxCA and TxCB pins can be programmed as either inputsto or outputs from the SCC To support this bidirectional interface EIM E and EIMF are equipped with both a driver and a receiver for this line The 7 drivers and receivers are selected using the jumper settings shown in Table B 1 Refer also to Figure B 1 DC 900 0408E 93 ICP6000 X ICP9000 X Hardware Description and Theory of Operation Caution mM You must also set the jumper on the distribution panel and usethe protocol software to configure the desired clocking Table B 1 Clock Jumper Settings for 8 port MIL STD 188C or 232 Transmit Clock Source Port Internal DTE External DCE 0 K8 1 2 K16 1 2 1 K71 2 K15 1 2 2 K61 2 K14 1 2 3 K51 2 K131 2 4 K41 2 K121 2 5 K31 2 K111 2 6 K21 2 K101 2 7 1 1 2 K9 1 2 a Only one jumper per port B 2 Z85C30 285230 Serial Communications Controller EIME and EIMF have four Z85C30 ICP6000 ICP9000 or Z85230 ICP6000X ICP9000X serial communications controllers SCCs Each SCC implements two communications ports B 2 1 SCC Register Access Access to the SCC data and command registers is made us
88. rt number For example the transmit vector number for port 5 is 5 Receive Channel Terminal Count Interrupts can be globally enabled or disabled using bit 4 in Control Register 0 as shown in Figure 5 2 These interrupts are also at level 6 with vectors of theform Ex hex For example the receive vector number for port 11 is DC 900 0408E 59 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation Address 10000001 7 6 5 4 3 2 1 0 VMERMS VMEBR1 VMEBRO RCINT EEPDI EEPSK EEPCS FAULT Mnemonic Name Description RCINT DMA Receive Interrupt 0 Interruption on receive terminal count 1 No interruption on receive terminal count The post reset state of this bit is 0 Figure5 2 Control Register 0 Usefor DMA 5 8 3 1 0 DMA Command Register Thel O DMA Command Register defined in Figure 5 3 is used to start or stop any one of the 32 DMA channels A bit in the Status Register shown in Figure 5 4 is used to control write access to this register Writes to this register must be made only when bit 4 of the Status Register is 1 DM ARDY 5 9 VMEbus Slave Interface 60 TheVM Ebus slave interface is implemented using the VM Ebus Slave Interface VSI ASIC TheVSI s 16 byte wide mailboxes are accessible from both the VM Ebus and the local processor bus The mailbox control logic monitors accesses from the V M Ebus and has the capability of interrupting the local process
89. s 0 7 areconnected to the CT SA even numbered ports and CTSB odd numbered ports inputs of the SCCs and are read using the appropriate SCC accesses 98 DC 900 0408E B 8 port MIL STD 188C and 8 port EIA 232 Electrical Interface M odule Table 4 Capacitor Locations for Response Control Signal Capacitor Signal Capacitor Name Location Name Location 059800 C104 05804 100 RXD00 C79 RXD04 C49 CTS00 C81 CTS04 C51 RXCOO C76 RXC04 C42 DCD00 C75 DCD04 C40 TXCO00 C53 TXC04 C69 DSRO1 C105 DSRO5 C102 RXDO1 C83 RXD05 C59 CTS01 C85 CTS05 C61 1 C82 RXCO5 C52 1 C80 DCD05 C50 TXCO1 C55 TXC05 C64 DSRO2 C103 05806 97 RXD02 C89 RXD06 C67 5902 C91 CTS06 C69 RXCO2 C86 RXC06 C62 DCD02 C84 DCD06 C60 TXC02 C46 TXC06 C16 DSR03 C101 059807 C95 RXD03 C94 RXD07 C73 CTS03 C96 CTS07 C74 RXC03 C92 RXCO7 C70 DCD03 C90 DCD07 C68 TXCO03 C44 TXC07 C54 B 7 3 Data Carrier Detect The Data Carrier Detect DCD inputs 0 7 are connected to the DCDA even num bered ports and DCDB odd numbered ports inputs of the SCCs and are read using the appropriate SCC accesses DC 900 0408 99 ICP6000 X ICP 9000 X Hardware Description and Theory of Operation Address 60000020 read only 7 6 5 4 3 2 1 0 Unused Unused Unused Unused ose DSR4 DSR2 DSRO Address 60000021 read only 7 6 5 4 3 2 1 0 Unused Unused Unused Unused DSR7 DSR5 DSR3 0581 Figure B
90. t procedure function code in the h cmd field The h haddr and h count fields are not used On receipt of an init procedure command the boot loader validates the execution address that the host has stored in the PXR and if it is a valid RAM address stores an ACK function codein the cmd field If theaddressisinvalid a is returned and pro cessing of the command is terminated After writing the Ack the boot loader waits for the host to read the i cmd field and then makes a subroutine call to the specified address In general this subroutine call initializes the run time system and never returnsto the boot loader H owever the init procedure command can be used to exe cute a subroutine that does in fact return on completion In this case the boot loader will then send another download request to the host and download operations may continue Note that the host will receive an completing the operation whether or not the subroutine call returns to the boot loader Figure 7 1 illustrates a typical download sequence DC 900 0408E 7 Boot Load Procedure LAN CPU ICP Init M9 ICP is reset self test runs and passes control to boot loader Wait for mailboxes to appear on bus Perform initialization and wait for download ready Download ready 9 m ACK 4 Download request For block 1 store host buffer address load address and byte count in PXR Write block
91. t use the VM Ebus In order to provide access to the full 32 bit address range of the VM Ebus the VM M aster Interface uses bit 31 supplied from Control Regis ter 1 The VMEbus Master may access non existent or non responsive VM Ebus addresses particularly during software development To prevent a hang condition the ICP is equipped with aVM Ebus cycle timer that is programmed by the PROM resident code 66 DC 900 0408E 5 Hardware Overview Address 10000002 7 6 5 4 3 2 1 0 VMEDA VMEDS 5 4 1 2 1 Mnemonic Name Description VMEDA VMEbusDataAlignment Thisbit controlsthe data alignment mode of the ICP When the bit is 1 the internal VMEbus master logic aligns non aligned data When the bit is 0 non aligned transfers are performed on theVM Ebus 0 Non aligned transfers performed 1 Alignment performed internally VMEDS VMEbus Data Size This bit controls the maximum data size used by the ICP for VM Ebus transfers 0 D 32 master transfers allowed 1 D 16 master transfers only AM5 0 VMEbus Address Modifier These bits provide VMEbus address modifier Codes bits 5 0 respectively during VM Ebus read and write cycles AM 3 is not programmable as it is derived directly from AM 5 and AM 4 A31 VMEbusAddressBit31 This bit provides A31 during VMEbus master read and write cycles Figure5 6 Control Register 1 DC 900 0408E 67 ICP6000 X ICP 9000 X Hardware Descri
92. te only 7 6 5 4 3 2 1 0 DTR15 DTR14 DTR13 DTR12 DTR11 DTR10 DTR9 DTR8 Address 60000022 write only 7 6 5 4 3 2 1 0 DTR7 DTR6 DTR5 DTR4 DTR3 DTR2 DTR1 DTRO FigureA 3 Data Terminal Ready Address D ecodes A 4 Connector Pin Assignments ThelCP isconnected to thedistribution panel by two cables Each cable has a high den sity 80 pin connector on the ICP end and two 40 pin connectors on the distribution panel end Figure 4 shows the orientation of the pinson connector Thecon nector nearer the console port debug port is designated B and the connector farther away is designated A See Figure 5 7 on 69 for the location of the connectors DRWG 0297 FigureA 4 Front View of 80 pin Connector on the 88 DC 900 0408E A 16 port EIA 232 Electrical Interface M odule Table 2 shows the signal mapping for the cables that connect the ICP to the distribu tion panel FigureA 5 shows the EIA 232 connector with the supported signals their proper signal names and the three letter mnemonics used in Table 2 14 DCE Transmitter Signal Element Timing TxC 15 16 Receiver Signal Element Timing 17 18 19 DataTerminal Ready DTR 20 21 22 23 DTE Transmitter Signal Element Timing TxC 24 25 Jumpers on the distribution panel and the ICP determine which of these pins is connected to the SCC A WU N PP
93. yte wide General Control Register 1 write only byte wide General Status Register read only byte wide MFP General Purposel O Data Register GPDR MFP Active Edge Register AER MFP Data Direction Register DDR MFP Interrupt Enable Register A IERA MFP Interrupt Enable Register B IERB MFP Interrupt Pending Register A IPRA MFP Interrupt Pending Register B IPRB MFP Interrupt In Service Register A ISRA MFP Interrupt In Service Register B ISRB MFP Interrupt M ask Register IM RA Interrupt M ask Register B IM RB MFP Vector Register VR MFP Timer A Control Register TACR MFP Timer B Control Register TBCR MFP TimersC amp D Control Register TCDCR MFP Timer A Data Register TADR MFP Timer B Data Register TBDR MFP Timer C Data Register TCDR MFP Timer D Data Register TDDR MFP Sync Character Register SCR DC 900 0408 51 ICP6000 X ICP9000 X Hardware Description and Theory of Operation 52 Table5 1 General M emory M ap Cont d Memory Range hex Device 20000014 M FP USART Control Register UCR 20000015 Receiver Status Register RSR 20000016 MFP Transmitter Status Register TSR 20000017 MFP USART Data Register UDR 30000000 VSI Mailbox Register 0 30000001 VSI Mailbox Register 1 30000002 VSI Mailbox Register 2 30000003 VSI Mailbox Register 3 30000004 VSI Mailbox Register 4 30000005 VSI Mailbox Register 5 30000006 VSI Mailbox Register 6 30000007 VSI

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