Application Note
Contents
1. External vector Index IX 7 0 in interrupt vector interrupt number register ICR Default t channel decimal decimal DMA Offset in Pd 0 17 17 Ox3B8 1 18 18 0x3B4 2 19 19 Ox3BO 3 20 20 Ox3AC 4 21 21 8 5 22 22 4 6 23 23 7 24 24 es 0x39C OxFFFCOO 8 25 25 0x398 offset 9 26 26 0x394 10 27 27 0 390 11 28 28 0x38C 12 29 29 0x388 13 30 30 0x384 14 31 31 0x380 15 32 32 0x37C Table 3 27 Interrupt vector table A default interrupt vector table for MB96340 series is located in file vectors c provided in the template project An example for the external interrupt 3 is shown below define MIN ICR 12 define MAX ICR 96 define DEFAULT MASK 7 void InitIrqLevels void interrupt level definition volatile ant Eor unge MINIER IMANE RSS ICR lt lt 8 DEFAULT ILM MASK TER Ext TNT3 interrupt void ExtlInt3 IROHandler void interrupt service routine pragma intvect ExtInt3 IROHandler 20 interrupt vector definition MCU AN 300046 E V 10 34 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 MB88121 Chapter 3 Configuration FUJITSU 3 8 Debugging support The MB88121 offering also debug support at some pins debug pins2. Function type Configuration register Start of dynamic segment OUT 8 CYCSO Cycle 0 start OUT 14 CYCS Cycle start OUT 23 MT Macrotick start OUT Debug support register 38 MBSU TX1 DBGS 39 MBSU RX1 Message buffer status update port OUT 44 MBSU TX2 45 MBSU RX2 Table 3 28 Debug pins on MB88121 After power on reset these pins are set to output driving Low level The upper 16 bit Bit 31 16 of CUS2 Register is called Debug support register DBGS having the offset address 0x08 0x10 0008 Via these pins the output of the dedicated debug signal is controlled The output of the signals is enabled by setting 1 to the corresponding bit position in 3 9 Stop Watch pin The MB88121 supports the Stop Watch function The function is similar to Input Capture Unit the time base is FlexRay global time In case a external Signal connected to Stop Watch pin is changing its Level the Macrotick value of FlexRay channel A and B is stored in register and can be read out by host MCU This pin is an input pin If the function is not used a pull up or pull down resistor must be connected to this pin Fujitsu Microelectronics Europe GmbH 35 MCU AN 300046 E V10 FUJIT SU Interfacing MB96340 TO MB88121 Chapter 4 Reference 4 Reference e MB96340 series Datasheet e MB96300 super series Hardware Manual e Application note hardware set up for 16FX series mcu an 300223 e 16fx hw setup
3. 30 3 7 2 MOCU external Interrupt asics usas dae Ere eta esa 31 3 7 2 1 External interrupt configuration 31 3 7 2 2 port register DDR and 32 3 7 2 3 Interrupt vector table 33 440 Debugging Support c 35 3 9 Stop Watch ses aa Quia e DA Ue Fab nin UR 35 4 REFERENCE E 36 5 APPENDIX es 37 5 1 Table asragan ea 37 MCU AN 300046 E V10 4 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 FUJITSU Contents SS COR 38 Fujitsu Microelectronics Europe GmbH 5 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 1 Introduction 1 Introduction FUJITSU Microelectronics Europe GmbH offers a stand alone FlexRay Communication Controller MB88121 series which supports parallel and serial connectivity to Host MCU The MB88121 series supports a parallel Bus interface modes 16 bit multiplexed mode especially for Fujitsu 16FX MCU The 16FX MCU MB96340 series is supporting a 16 bit multiplexed bus interface The following discusses Hardware and Software requirement based MB96F348RS series Note Not all MB96300 devices support an multiplexed external
4. FE EFFE User ROM INROMO1 Main Flash EE df 007f GE 000 de 002f Satellite Flash de 00007 External bus area 2 10 0000 0x100000 Ox10FFFF 0 000 Boot ROM 02 0000 Internal RAM not used ROM RAM Mirror Internal RAM INRAMO1 General purpose register 00 RAM access Figure 3 2 Memory map of internal RAM external bus mode MCU AN 300046 E V10 14 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 3 Configuration FUJITSU 3 3 88121 CC operation mode The mode pins MD 2 0 and MDE 2 0 select between different bus types The multiplexed mode is fixed encoded MD2 MD1 MDO Mode MDE2 MDE1 MDEO Mode extension 0 0 0 460 Multiplexed bus 1 7 7 7 16bit parallel 0 16FX 1 Non multiplexed 460 bus FR360 O oO Table 3 3 Mode selection input of the communication controller Fujitsu Microelectronics Europe GmbH 15 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration 3 4 Configuration of the external bus interface MB96340 has 6 chip select areas The configuration registers are listed in the table Address 0 1 External bus area 5 0 configuration register 0 0006 0 0 0006 2 EACL1 EACH1 0 0006 4 2 2 0 0006 6 0
5. Other bits shall be set to 0 The stabilisation time of the PLL is 600us After this time the MB88121 The PLL clock usage be selected via the CCNT SEEL bit set to 1 The wait time can be assured using a reload timer of the MCU The MB88121 is operating with 80 MHz It is now possible to initialise the MB88121 with the FlexRay bus parameter settings THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES 7 VE C Fujitsu Microelectronics Europe GmbH n define CCNT uint32 t 0x100004 address of CCNT ERAY Register Sz OR CIR TMCSRS LRG 1 RS Um Count operi setup of reload timer 3 TMCSR3 CNTE 0 stop reload Timer TMRLR3 600 reload value 7 TMCSR3 0x0802 set MB88121 Clock CCNT 0x0000000D enable PLL PLLx8 SHOE start wait time while TMCSR3 UF PLL stabilization wait time CCNT 0x0000000F SW Co BPEL Clock ay Fujitsu Microelectronics Europe GmbH 29 MCU AN 300046 E V10 Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration 3 7 Interrupts The MB88121 FlexRay CC is supporting also interrupt events These events are available at pins and can be connected to MCU external
6. MCU AN 300046 E V 10 20 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 Chapter 3 Configuration co FUJITSU 3 4 5 External Area Configuration registers EACH EACL 5 0 Function of register EACH and EACL is listed below In this application note external area 2 is used The corresponding parameter is 52 CONFIG Register EACH2 Bit Name Function 15 14 ee 1 Only data read possible 1 Chip select signal is high active CS 0 Chip select output disabled 10 8 EASZ 2 0 External area size Register EACL2 7 BW 1 8bit data bus width Ng 1 Big endian 0 WRL write strobe is activated RE I O 0 Strobe timing scheme 0 is selected 0 Address cycle is not extended CU DT sommes 2 0 R 2 0 Automatic wait cycles Gray Settings used for MB88121 connectivity Table 3 10 Register EACH EACL Note 1 Bit ACE decides the length of the address cycle in multiplexed bus mode 2 Bit STS selects the timing of the signal ALE WR and RD for details please see the hardware manual of MB96300 series Fujitsu Microelectronics Europe GmbH 21 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration EASZ2 EASZ1 EASZO0 Valid bit of register EAS 0 0 0 64KB EAS A 7 0 0 0 1 128KB EAS A 7 1 0 1 0 256KB EAS A 7 2 0 1 1 512 EAS A 7 3 1 0
7. 11 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 MB88121 FUJ ITSU Chapter 3 Configuration ADOO AD15 A00 A23 ALE RDX WRLX WRHX KO X1 HRQ X1A HAKX RDY RSTX NMI MDO MD2 ECLK LBX UBX 50 55 External Bus 16FX Interrupt Main Flash Satellite Flash Memory Patch Clock amp Interface CPU Controller Memory Memory Unit ode Controlle 16FX Core Bus CLKB DMA Peripheral m dS E Bus Bridge Voltage Regulator amp a 5 vcc o X SDAO SDA1 a gt 2 d VSS 2 ch SCLO SCL1 E CAN jp TKA NEE T T Interface AVRH 10 bit ADC 9 2 ch 44 RXO RX1 AVRL 24 ch E ANO AN23 a ADTG TINO TIN3 16 bit Reload Timer 4 SINO SIN3 SIN72 SIN9 TONG TOT3 4 ch USART 5 SOT72 SOT9 7 ch SCKO SCK3 SCK7 SCK92 FRCKO Timer 0 INO IN3 ICU 0 1 2 3 Alarm 4 ALARMO OUTO OUT3 OCU 0 1 2 3 Comparator D ch 4 ALARM FRCK1 Timer 1 INA IN7 ICU 4 5 6 7 OUT4 OUT7 OCU 4 5 6 7 EG TTGO TTG15 16ch PPGO PPG15 Real Time D WOT External INTO INT15 Interrupt Clock 2 Clock Output CKOTO CKOT1 Function 2 ch CKOTXO CKOTX1 Figure 3 1 Block diagram of the MB96340 series MCU AN 300046 E V10 12 Fujitsu Microelectronics Europe GmbH
8. e Application note external bus interface for 16FX series mcu an 300208 e 16fx ext bus e Application note external interrupts for 16FX series mcu an 300203 e 16fx ext int e Application note Interrupts for 16FX series mcu an 300210 e 16fx e Application note l O port for 16FX series mcu an 300200 e 16fx io ports e MB88121B preliminary data sheet Ver1 3 e MB88121B User s Manual MCU AN 300046 E V10 96 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 FUJITSU Chapter 5 Appendix 5 Appendix 5 1 Tables 3 1 5 5 ruin CURE A RR on 11 Table 3 2 Configuration of internal ROM external bus 13 Table 3 3 Mode selection input of the communication controller 15 Table 3 4 External bus interface registers sseese nne nseessse tt rte tertre trrnnt re rnrsrtrrrn trs neesrerr nnne 16 Register EBM ii C 17 Table 3 6 Register EBCF 18 Table 3 7 Bit DIV 2 0 of register EBCF aran b eaaa Montes 18 Table 3 8 Register EBAE 2 0 19 Table 3 9 Register EBCS e nasag aia kaa Rag adden 20 Table 3 10 Register EFACH
9. co Interfacing MB96340 TO MB88121 FUJ ITSU Chapter 3 Configuration 3 4 2 External Bus Clock and Function register Register EBCF controls the external bus clock the external READY and HOLD function Bit function is listed below Bit Name Function 0 HOLD function disabled 15 HDE parameter HOLD REQ in start asm 1 HOLD function enabled 0 READY function disabled 14 RYE READY function enabled parameter EXT READY in start asm 0 External bus clock output disabled 13 CKE 4 External bus clock output enabled parameter EXT CLOCK ENABLE in start asm External bus clock is not inverted 9 the inactive level ECLK is 0 and the rising edge is the active edge 12 CKI External bus clock is inverted 1 the inactive level of ECLK is 1 and the falling edge is the active edge parameter EXT CLOCK INVERT in start asm 0 External bus clock is always output 11 CSM parameter EXT CLOCK SUSPEND in start asm 1 External bus clock is only output during transfer External bus clock ECLK divider DM parameter EXT CLOCK DIVISION in start asm Gray Settings used for MB88121 connectivity Table 3 6 Register EBCF External bus clock ECLK divider setting DIV2 DIV1 DIVO 0 0 0 CLKB CPU clock 0 0 1 CLKB 2 0 1 0 CLKB 4 0 1 1 CLKB 8 1 0 0 CLKB 16 1 0 1 CLKB 32 1 1 0 CLKB 64 1 1 1 CLKB 128 Gray Settings used for MB881
10. CC debug pins Function type Configuration register Start of dynamic segment OUT 8 CYCSO Cycle 0 start OUT 14 CYCS Cycle start OUT 23 MT Macrotick start OUT Debug support register 38 MBSU TX1 DBGS iid MBSU RAI Message buffer status update port OUT 44 MBSU TX2 45 MBSU RX2 CC stop watch trigger pin Function After stop watch is triggered rising or falling edge register STPW 1 9 STPW IN captures actual cycle counter macrotick value register STPW2 captures slot counter values for channel A and B CC pins in connection with physical layer transceiver I Name Function I lOtype Connection 11 TXDA Data transmission OUT 12 TXENA Channel transmission enable OUT Channel A transceiver 13 RXDA Data reception IN 24 RXDB Data reception IN 25 TXENB Channel transmission enable OUT Channel B transceiver 26 TXDB Data transmission OUT CC power pins 1 17 33 49 VSS Ground 16 32 48 Single power supply input between 3 3v and 5v 18 C Power supply stabilization capacitor 2100nF CC external clock pin 2 X1 Oscillation output 4MHz 5MHz 8MHz 10MHz 3 X0 Oscillation input crystal or ceramic oscillator Fujitsu Microelectronics Europe GmbH 9 MCU AN 300046 E V10 FUJITSU Interfacing MB96340 TO MB88121 Chapter 2 Connection example
11. PERFORM The following document contains information on Cypress products Although the document is marked with the name Spansion and Fujitsu the company that originally developed the specification Cypress will continue to offer these products to new and existing customers Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product Any changes that have been made are the result of normal document improvements and are noted in the document history page where supported Future revisions will occur when appropriate and changes will be noted in a document history page Continuity of Ordering Part Numbers Cypress continues to support existing part numbers To order these products please use only the Ordering Part Numbers listed in this document For More Information Please contact your local sales office for additional information about Cypress products and solutions About Cypress Cypress NASDAQ CY delivers high performance high quality solutions at the heart of today s most advanced embedded systems from automotive industrial and networking platforms to highly interactive consumer and mobile devices With a broad differentiated product portfolio that includes NOR flash memories F RAM and SRAM microcontrollers the industry s only PSoC programmable system on chip solutions analog and PMIC Power Management ICs CapSense capacitive touch sensing cont
12. 0006 8 EACL4 EACH4 0x0006EA EACL5 5 External bus area 5 2 select register 0 0006 52 EAS3 0 0006 54 55 0 0006 0 external bus clock and function external bus mode register register External bus address output enable register 0x0006F2 EBAEO 1 5 0 0006 4 2 external bus control signal register Gray Settings used for MB88121 connectivity Table 3 4 External bus interface registers The MB88121 CC requires a minimum address range of 2K 0 Ox7FF That means that CSO cannot be used due to insufficient address range In this example CS2 is used MCU AN 300046 E V 10 16 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 Chapter 3 Configuration FUJITSU 3 4 1 External Bus Mode register EBM Register EBM defines the bus mode of the external bus interface Bit function is listed below Bit Name Function 7 NMS Non multiplexed bus mode for all external areas 6 ERE External ROM mode 5 5 External area 5 is enabled 4 EAE4 External area 4 is enabled 3 EAE3 External area 3 is enabled 0 External area 2 is disabled 2 EAE2 1 EAE1 1 External area 1 is enabled 0 EAEO 1 External area 0 is enabled Gray Settings used for MB88121 connectivity Table 3 5 Register EBM Fujitsu Microelectronics Europe GmbH 17 MCU AN 300046 E V10
13. 3 5 2 MB88121 write timing D 15 11 AD 10 0 valid data 12 Write i i data i i Figure 3 4 Write operation Operation sequence 1 The address is latched by the falling edge of ALE pin 2 The WR pin signal WR becomes low level At the next falling edge of the BCLK signal the data on pins D 15 11 and AD 10 0 is written to a temporary register and the RDY pin becomes low level which causes the MCU to wait 3 The data in the temporary register is written to the addressed register The RDY pin becomes high level again Note Details about RDY wait cycle and byte ordering are located in the MB88121 data sheet MCU AN 300046 E V10 28 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 3 Configuration FUJITSU 3 6 Initialisation sequence of MB88121 After the proper setup of the bus interface MB88121 is visual in the MCU address range starting at 10 0000 The MB88121 requires internal operation frequency of 80 MHz This frequency is generated via the internal PLL of the MB88121 First access to MB88121 should setup the PLL The PLL is set in the CLOCK CONTROL REGISTER Address 0x04 gt 0x10 0004 The example is using a 10 MHz crystal The PLL must be setup to multiplication ratio x8 PMUL 1 0 to achieve the 80 MHz The PLL must be enabled via PON bit To supply the FlexRay CC with clock the STOP bit needs to be set to 0
14. 0 1MB EAS A 7 4 1 0 1 2MB EAS A 7 5 1 1 0 4MB EAS A 7 6 1 1 1 8MB EAS A 7 Table 3 11 EASZ 2 0 of register EACH R2 R1 Automatic wait cycles 0 0 0 No wait cycle 0 0 1 1 cycle 0 1 0 2 cycle 0 1 1 3 cycle 1 0 0 4 cycle 1 0 1 8 cycle 1 1 0 16 cycle 1 1 1 32 cycle Table 3 12 R 2 0 of register EACL 3 4 6 Registers EAS 5 2 MB96340 series support 6 external bus areas Among them area 0 and area 1 have fixed address range External area Address range CS0 0x0000F 0 0x0000FF CS1 0x000C00 RAM start 1 Table 3 13 address range of area 0 and area 1 Device RAM size RAM start MB96344 6KB 0x006A40 MB96 F 346 MB96 F 347 16KB 0x004240 MB96F348 24KB 0x002240 Table 3 14 RAM start address of different devices MCU AN 300046 E V 10 22 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 Chapter 3 Configuration co FUJITSU The address range of area 2 to area 5 is programmable through register EAS 5 2 and register EACH 5 2 External area CS2 CS3 CS4 CS5 Available address area 0x100000 0xFFFFFF EAS2 EACH2 EASZ Corresponding register 53 EASZ 54 EASZ 5 5 EASZ Table 3 15 Configuration registers for area range Register EAS defines the upper 8 bit address start bank of the ex
15. Fujitsu Microelectronics Europe MCU AN 300046 E V10 Application Note F MC 16FX FAMILY 16 BIT MICROCONTROLLER MB96340 MB88121 INTERFACING MB96340 TO MB88121 APPLICATION NOTE MCU AN 300046 E V10 1 Fujitsu Microelectronics Europe GmbH FUJIT SU Interfacing MB96340 TO MB88121 Revision History Revision History Date 2008 03 25 V1 0 MSt First draft This document contains 38 pages MCU AN 300046 E V10 2 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 FUJITSU Warranty and Disclaimer Warranty and Disclaimer To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for all products delivered free of charge eg software include or header files application examples target boards evaluation boards engineering samples of IC s etc its performance and any consequential damages on the use of the Product in accordance with i the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered ii the technical descriptions and iii all accompanying written materials In addition to the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and or reverse engineering and or dis
16. MB96F348RS MB88121B 88121 MCUP96 a MCUP94 m 89 4 MCUP88 2 5 3 TES 1 TEST FA GND Tin 2 MCUP86 4 84 56 MCUP82 58 MCUPSI E MCUPS80 60 IVecs V GND w 9 e MCUP78 Debug pins a MCUP46 w n 3 Dii MCUP48 35 MCUP49 36 Channel A Transceiver 1 VecsV 6 lok Channel B Transceiver 24 3 MCUP6 20 MCUPIS MCUP6S VeesV 10k unused pins are pulled up 5 MCUP90 MCU AN 300046 E V 10 10 Fujitsu Microelectronics Europe GmbH co FUJITSU 3 Configuration Interfacing MB96340 TO MB88121 Chapter 3 Configuration This chapter introduces the concrete configuration of MB96F348RS series 3 4 MB96340 series MB96340 series is based on Fujitsu s 16FX architecture Some features of this MCU family are listed below Flash ROM RAM MB96340 series 128KB 6KB MB96344R MB96344Y 288KB 16KB MB96F346R MB96346R MB96F346Y MB96346Y MB96F346A A16KB 16KB MB96F347R MB96347R MB96F347Y MB96347Y MB96F347A 544KB 24KB MB96F348R MB96F348Y MB96F348A Main Flash 544 MB96F348C MB96F348H MB96F348T Satellite 24KB Flash 32KB External interrupts 16 channels External bus interface Multiplexed mode Chip select signal 6 Table 3 1 MB96340 feature MCU AN 300046 E V 10
17. bus interface MCU AN 300046 E V10 6 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 2 Connection example MB96F348RS MB88121B FUJITSU 2 Connection example MB96F348RS MB88121B A connection example is summarized in the following table All pins of the communication controller CC are divided into 7 categories External bus interface CC pins in connection with MCU pins CC mode pins CC debug pins CC stop watch trigger pin CC pins in connection with physical layer transceiver CC power supply pins CC external clock pin The connection of the interrupt pins is application specific The table here shows only an example 2 The CC reset pin can be controlled by MCU reset pin or by an independent circuitry In this application note external bus area 2 is configured for MB88121B Other areas can also be used For the power supply it should be noticed that MB88121B is a single voltage supply chip All power supply pins should have the same supply voltage between 3 3V and 5 Fujitsu Microelectronics Europe GmbH 7 MCU AN 300046 E V10 co FUJITSU Interfacing MB96340 TO MB88121 Chapter 2 Connection example MB96F348RS MB88121B External bus interface CC pins in connec
18. interrupt pins 3 7 1 CC interrupt CC interrupt pins signal different interrupt request For details please refer to the document MB88121B preliminary data sheet and E Ray user manual CC pin Interrupt type INTO E Ray interrupt lineO intO INT1 E Ray interrupt line1 int1 INT2 E Ray timerO interrupt INT3 E Ray timer1 interrupt Low voltage detection interrupt Table 3 19 CC interrupt output by 16bit multiplexed mode After power on Reset these pins are set to output driving Low level Interrupt requests are indicated by High Level output at the pins To enable the output of the signals INT2 to INT 4 the INT Interrupt register at offset address OxOC Address 0x10 000C in our example configuration must be used The dedicated E Ray timer interrupts are indication a request just a few Macroticks It is recommended to use rising edge detection for the external interrupts The INTO and INT1 pins are connected to the Eray intO and Eray int1 interrupts The functions are configured with the E Ray interrupt registers In case of an interrupt request the pins output High level and remaining the level until the Interrupt Flag is clear in the corresponding register Following interrupt registers are available e Error Interrupt Register EIR indicates an error interrupt request e Status Interrupt Register SIR indicates a status interrupt request e Error Interrupt Line Select EIL
19. 2 ER1 ERO 15 14 13 12 11 10 9 8 0x00005B LB7 7 LB6 LB5 LA5 LB4 LA4 ELVRO 7 6 5 4 3 2 1 0 0x00005A LB3 LA3 LB2 LA2 LB1 LA1 LBO LAO External interrupt 8 15 g addre 7 6 5 4 3 2 1 0 ENIR1 0x00005C EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EIRR1 0x00005D ER15 ER14 ER13 ER12 ER11 ER10 ER9 8 15 14 13 12 11 10 9 8 0x00005F LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 ELVR1 7 6 5 4 3 2 1 0 0x00005E LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 Table 3 20 EIRR ENIR ELVR overview Fujitsu Microelectronics Europe GmbH 31 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration LBn LAn Description 0 0 Detect L level and generate an interrupt request 0 1 Detect H level and generate an interrupt request 1 0 Detect the rising edge and generate an interrupt request 1 1 Detect the falling edge and generate an interrupt request Table 3 21 ELVR register CC interrupt pins are high level active Therefore signal high level or rising edge should be chosen for external interrupt detection ERn Read register Write register No external interrupt 0 request present Clear external interrupt request flag 4 External interrupt No effect request present Table 3 22 EIRR register ENn Description 0 External interrupt request is disabled 1 External interrupt request is enabled Table 3 23 ENIR register 3 7 2 2
20. 21 connectivity Table 3 7 Bit DIV 2 0 of register EBCF MCU AN 300046 E V 10 18 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 MB88121 Chapter 3 Configuration FUJITSU Note 1 All operations of the external bus are based on ECLK even if the output of this clock is disabled 2 5 0 ECLK is always output also in HOLD state The 16FX MCU offers two methods to extend the read write access to an external device the auto wait function bits EACL R 2 0 and the READY function through RDY pin bit EBCF RYE They enable the access to low speed memory and peripheral circuits The auto wait function can insert 1 to 32 wait cycles to extend the data cycle By READY function the data cycle is extended as long as pin RDY 20 3 4 3 External Bus Address output Enable registers EBAE 2 0 Registers EBAE 2 0 control the output function of each address line 0 disable the address line 1 enable the address line Corresponding parameter in file start asm Address Bit Bit5 Bit4 BitO 0x0006F2 A6 A5 A3 0 ADDR PINS 7 0 EBAEO 1 1 1 1 1 1 1 1 0x0006F3 15 A14 A13 2 A11 10 A9 A8 ADDR PINS 15 8 EBAE1 1 1 1 1 1 1 1 1 0 0006 4 A23 A22 A21 A20 A19 A18 17 A16 EBAE2 0 O 0 0 0 0 0 0 ADDR PINS 23 16 Gray Settings used for MB88121 connectivity Table 3 8 Register EBAE 2 0 In the m
21. 8 11bit address line MCU AN 300046 E V 10 26 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 3 Configuration FUJ ITSU 3 5 Simplified timing diagram of MB88121B The be low shown timing diagram is required to achieve a correct access to MB88121 The settings discussed for the bus interface register will generate this timing Depending on PCB layout the number of wait states may differ This needs to be rechecked and optimised case by case 3 5 1 MB88121 read timing BCLK CS ALE RD WR D 15 11 AD 10 0 Invalid RDY Figure 3 Operati 1 2 3 Read operation on sequence The address is latched by the falling edge of ALE pin The RD pin signal RD becomes low level the output data on pins D 15 11 and AD 10 0 is invalid After that the RDY pin becomes low level at the next falling edge of the clock signal BCLK pin BCLK which causes the MCU to wait After several wait cycles the RDY pin becomes high level at the rising edge of the BCLK pin the valid data is output from the pins D 15 11 and AD 10 0 When the RD pin becomes high level again the read access is finished Pins D 15 11 and AD 10 0 become Hi Z Fujitsu Microelectronics Europe GmbH 27 MCU AN 300046 E V10 Interfacing MB96340 MB88121 FUJ ITSU Chapter 3 Configuration
22. Appendix 5 2 Figures Figure 3 1 Block diagram of the MB96340 series 12 Figure 3 2 Memory map of internal RAM external bus 14 PIQUPS RSS pM 27 Figure 3 4 Write operation m 28 END MCU AN 300046 E V10 38 Fujitsu Microelectronics Europe GmbH
23. CLOCK SPEED CPU 48 2 CLKP2 16 2 External Bus Interface BUSMODE INTROM EXTBUS 2 bus mode ADDRESSMODE MULTIPLEXE address mode CHIP SELECI 7 selectarea HOLD 2 HODBDSEunction READY Ready function CLOCK ENABLE external bus clock output EXT CLOCK INVERT clock inversion EXT CLOCK SUSPEND OFF EXTOGBOGKODBVIESTDONSUEXTSChOOGRSDEV2 select clock divider 5 237416 B 00000000 select used address lines ADDR PINS 15 8 Bah Pa TT ANO CAU ADDR PINS 7 0 BUND OW BYTE SIGNAL HIGH BYTE SIGNAL LOW WRITE STROBE ON write strobe signal WRLX WRX HIGH WRITE STROBE READ STROBE ON read strobe signal RDX ADDRESS STROBE ON address strobe signal ALE ASX ADDRESS STROBE LVL OFF address strobe active low CONFIG 0000100000111010 Select Area 2 configuration CS2 START 0x10 Start bank of chip select area2 MCU AN 300046 E V10 24 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 3 Configuration FUJITSU 6 6 Set external bus configuration OV EBCF HOLD REQ lt lt 7 EXT READY lt lt 6 EXT CLOCK ENABLE lt lt 5 EXT CLOCK INVERT 4 EXT C
24. EACL xke GR anana aana aana INDIA FINDER 21 Table 3 11 EASZ 2 0 of register EACH 22 Teble 3 12 R 2 0 af register p rera daa a uia andar ka Gd a ia 22 Table 3 13 address range of area 0 and area 1 22 Table 3 14 RAM start address of different 22 Table 3 15 Configuration registers for area range 23 Table 3 16 Configurations of area range in file start asm 23 Table 3 17 Configuration registers of port 26 Table 3 18 11bit address line 26 Table 3 19 CC interrupt output by 16bit multiplexed 30 Table 3 20 EIRR ENIR ELVR 31 T M 32 Zudiqita 32 Table Pm 32 Table 3 24 register DDR and 32 Table 2 25 Register qr 33 Table 3 26 Register ICR qmm 33 Table 3 27 Interrupt vector table ss 34 Table 3 28 Debug pins on 88121 35 Fujitsu Microelectronics Europe GmbH 37 MCU AN 300046 E V10 FUJIT SU Interfacing MB96340 TO MB88121 Chapter 5
25. IGURATION mc 11 3 1 MB96340 series hais 11 A2 MENU MdG sen aga Na an a AA aa a E Gan rie RC fni 13 3 3 88121 CC operation mode sssssssnsnnsnssnnrntnttttttrntrttttrttttttttrtrttrrttttrtrtrrertrnn 15 3 4 Configuration of the external bus interface 16 3 4 1 External Bus Mode register 17 3 4 2 External Bus Clock and Function register 18 3 4 3 External Bus Address output Enable registers EBAE 2 0 19 3 44 External Bus Control Signal register 20 3 4 5 External Area Configuration registers EACH EACL 5 0 21 3 4 6 Registers EAS 5 2 2 neni aa aaa nenne er hn pa onto ann ans anna asa aa sac san rasa 22 3 4 7 Settings in file SAR ANNE T 24 3 4 8 Used bus interface functions at pins on MB96F348RS 25 3 5 Simplified timing diagram of MB88121B 27 3 5 1 88121 read iot re ennt en bna 27 4 52 MBBS12T write timing aae dn 28 3 6 nitialisation sequence of MB88121 29 SM AEn do 30 3 7 1 eii ario
26. Interfacing MB96340 MB88121 Chapter 3 Configuration FUJITSU 3 2 MCU operation mode The MCU operates in the internal ROM external bus mode That means the internal Flash is accessible and in addition the external bus interface might be enabled during initialization phase of the MCU The configuration of mode pins and file start asm are listed below Operation Mode setting hode Description Internal The boot vector user program start address is read from MD1 1 vector internal memory address OxFFFFDC MDO 1 mene Table 3 2 Configuration of internal ROM external bus mode 4 1 Controller Series Devic set ERIE MB96340 set MB96348R 4 14 Boot Vector set BOOT VECTOR BOOT VECTOR TABLE if BOOT VECTOR BOOT VECTOR TABLE SECTION RESVECT CONST LOCATE H FFFFDC TION BOOT SELECT CONST E H DF0030 A L OxFFFFFFFFE kendit 6 1 Import external symbols main user cod ntranc start 2 Program start the boot vector should point here The memory map of this operation mode is illustrated in the next page Fujitsu Microelectronics Europe GmbH 13 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJ ITSU Chapter 3 Configuration
27. LOCK SUSPEND 3 EXT CLOCK DIVISION OV EBAEO ADDR PINS 7 0 EBAE1 ADDR_PINS 15 8 EBAE2 ADDR PINS 23 16 EBCS ADDRESS STROBE LVL lt lt 6 ADDRESS STROBE lt lt 5 READ STROBE HIGH WRITE STROBE lt lt 3 LOW WRITE STROBE lt lt 2 HIGH BYTE SIGNAL BYTE SIGNAL EACL2 4CS2 CONFIG OV 82 34652 START OV EBM ADDRESSMODE lt lt 7 BUSMODE 1 lt lt 6 CHIP SELECTS lt lt 5 CHIP SELECTA lt lt 4 CHIP SELECTS s CHIP SELECT2 x2 CHIP SEBLECT CC GHREESETEGTO MOV PIEROO 0xFF MCU port 0 MOV MCU port 1 SETB PIERO3 6 PREADY function ROMM CONFIG EQU MIRROR BANK 4 MIRROR SIZE ROMMIRROR MOV ROMM ROMM CONFIG 3 4 8 Used bus interface functions at pins on MB96F348RS All the used pins of the external bus interface are listed below Data output function of pins AD 15 00 is automatically enabled Pin ALE is used to distinguish value on the address data lines Pin RDY is used by slow external devices to insert wait cycles The initial value of register DDR data direction register and PIER port input enable register is O Description Register PIER Register DDR O
28. S Selects which error interrupt is output at which eray int 0 or 1 line e Status Interrupt Line Select SILS Selects which status interrupt is output at which eray int 0 or 1 line e Error Interrupt Enable Set Reset EIES EIER Enable disable error interrupts e Status Interrupt Enable Set Reset SIES SIER Enable disable status interrupts e Interrupt Line Enable ILE Enable interrupt lines MCU AN 300046 E V 10 30 Fujitsu Microelectronics Europe GmbH Interfacing MB96340 TO MB88121 3 7 2 MCU external interrupt Following show the setup and usage of the external interrupt rising edge for MB88121 connection Chapter 3 Configuration Following registers are relevant for external interrupt ELVR interrupt request level register EIRR interrupt request register ENIR interrupt request enable register DDR data direction register PIER port input enable register ICR interrupt control register 3 7 2 1 External interrupt configuration registers Register ELVR EIRR and ENIR specify the external interrupt function ELVR defines how to detect interrupt request signal EIRR shows if an external interrupt request is detected ENIR enables disables interrupt request co FUJITSU External interrupt 0 7 g addre 7 6 5 4 3 2 1 0 ENIRO 0x000058 EN6 EN5 EN4 EN3 EN2 EN1 ENO EIRRO 0x000059 7 6 5 ER4 ER3 ER
29. and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the US Export Administration Regulations or the applicable laws of any other country the prior authorization by the respective government entity will be required for export of those products Trademarks and Notice The contents of this document are subject to change without notice This document may contain information on a Spansion product under development by Spansion Spansion reserves the right to change or discontinue work on any product without notice The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy completeness operability fitness for particular purpose merchantability non infringement of third party rights or any other warranty express implied or statutory Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document Copyright O 2013 Spansion Inc All rights reserved Spansion the Spansion logo MirrorBit MirrorBit Eclipse ORNAND and combinations thereof are trademarks and registered trademarks of Spansion LLC in the United States and other countries Other names used are for informational purposes only and may be trademarks of their respective owners
30. assembling Note all these products are intended and must only be used in an evaluation laboratory environment 1 Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer Concerning the hardware components of the Product Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer 2 Should a Product turn out to be defect Fujitsu Microelectronics Europe GmbH s entire liability and the customer s exclusive remedy shall be at Fujitsu Microelectronics Europe GmbH s sole discretion either return of the purchase price and the license fee or replacement of the Product or parts thereof if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport However this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH 3 To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disc
31. laims all other warranties whether expressed or implied in particular but not limited to warranties of merchantability and fitness for a particular purpose for which the Product is not designated 4 To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH s and its suppliers liability is restricted to intention and gross negligence NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever including but without limitation consequential and or indirect damages for personal injury assets of substantial value loss of profits interruption of business operation loss of information or any other monetary or pecuniary loss arising from the use of the Product Should one of the above stipulations be or become invalid and or unenforceable the remaining stipulations shall stay in full effect Fujitsu Microelectronics Europe GmbH 3 MCU AN 300046 E V10 FUJIT SU Interfacing MB96340 TO MB88121 Contents Contents REVISION HISTORY Scoss 2 WARRANTY AND DISCLAIMER aranan een nra terae Sonn ni Sosa eua 3 CONTENTER eee 4 1 IINTRODUCTIQN m aan aa 6 2 CONNECTION EXAMPLE MB96F348RS 88121 7 3 CONF
32. port register DDR and PIER MB96F348RS have altogether 16 external interrupt channels User should choose five of them for MB88121B The external interrupt function is assigned to MCU 00 and port07 Each of them has a 8bit data direction register DDR and a 8bit port input enable register PIER The default value of register DDR and PIER after reset is zero respectively all ports are input mode and disabled To use the external interrupt function only register PIER should be set to one Register Bit7 Bit6 Bit5 Bit4 Bit2 BitO description IEx 0 disable digital input PIERxx IE7 IEG IES IE4 IE2 IE IEO IEx 1 enable digital input Dx 0 input mode DDRxx D7 D6 D5 D4 03 02 D1 00 Dx 1 output mode Table 3 24 register DDR and PIER MCU AN 300046 E V 10 32 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 3 Configuration FUJITSU An initialization example of the external interrupt 0 is shown below void Init extint 0 void 0 ing interrupe e port07 0 Data direction input enable digital input rising edge detection clear interrupt request flag enable interrupt Before enabling the external interrupt request ENn 1 it is recommended to clear the request flag of the ex
33. rollers and Wireless BLE Bluetooth Low Energy and USB connectivity solutions Cypress is committed to providing its customers worldwide with consistent innovation best in class support and exceptional system value TX SPANSION a Colophon The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for any use that includes fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for any use where chance of failure is intolerable i e submersible repeater and artificial satellite Please note that Spansion will not be liable to you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection
34. ternal bus area Together with bits EASZ 2 0 of register EACH the address range of each external bus area can be specified The configurations in file start asm are listed below Area 2 is modified for MB88121B Area 3 4 5 are not used EAS register EACH register 52 0 10 2 EASZ 2 0 0 0x100000 0x10FFFF parameter CS2 START parameter CS2 CONFIG 64KB 53 0 40 EACH3_EASZ 2 0 6 0x400000 0x7FFFFF parameter CS3 START parameter CS3 CONFIG 4MB 54 0 80 EACH4_EASZ 2 0 6 0x800000 0xBFFFFF parameter CS4 START parameter CS4 CONFIG 4MB EAS5 0xC0 5 54712 0 6 0xC00000 0xFFFFFF parameter CS5 START parameter CS5 CONFIG 4MB Table 3 16 Configurations of area range in file start asm Fujitsu Microelectronics Europe GmbH 23 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJ ITSU Chapter 3 Configuration 3 4 7 Settings in file start asm FUJITSU Microelectronics Europe GmbH offers Software examples for MB96340 series including a template project The start asm file is used to initialise the MCU All settings are done via defines according to the selected defines a code content is generetade during compilation Following find the required bus interface settings for start asm file using MB96340 and Mb88121 series Clock selection CRYSTAL FREQ 4MHZ CPU 48MHZ CLKP2 16MHZ 0x08
35. ternal interrupt ERn 0 to avoid interrupts caused by previous trigger ERn is set independently of the setting of ENn 3 7 2 3 Interrupt vector table Register ICR defines the interrupt level Bits IX 7 0 select the interrupt resource and bits IL 2 0 specify the corresponding interrupt level 7 priority levels are programmable Level 0 has the highest priority and level 7 disables the interrupt The address of each interrupt service routine is set in the interrupt vector The vector address is calculated by adding the offset listed in the following table to the table base register value TBR Register TBR defines the most significant 14 bits TB 23 10 of the 24bit start address of the interrupt vector table The least significant bits TB 9 0 are fixed to O The initial value after reset is OXFFFC which results in a table start address Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 TB23 22 21 20 TB19 TB18 17 16 TB15 14 TB13 TB12 11 TB10 10 Table 3 25 Register TBR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IX6 IX5 IX4 IX3 IX3 IX2 IX1 IKO N N N N IL2 IL1 ILO Table 3 26 Register ICR Fujitsu Microelectronics Europe GmbH 33 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration
36. ther registers RDY ready signal 1 6 1 DDROS3 D6 0 EBCF RYE address output EBAE 2 0 AD 15 0 data output data input PIEROO OKFF DDROO 0 P PIERO1 0xFF DDRO1 0 ALE address latch enable EBCS ASE signal CS2 chip select signal EACH_CSE RDX read signal EBCS_RDE WRX Write signal EBCS_WRLE Fujitsu Microelectronics Europe GmbH 25 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration Description Register PIER Register DDR Other registers ECLK external bus clock EBCF_CKE Table 3 17 Configuration registers of I O port function MB96348RS provides maximal 24bit address line and 16bit data line for the external bus interface Since the communication controller MB88121B has 11bit address line and 16bit data line the bus width is fixed 16bit data bus MCU pins AD 15 00 E Ray registers are 16bit addressed from 0 0000 to 7 Each register is 32bit long and begins at even address Since the data bus is restricted to 16bit the high order 16bit data and low order 16bit data are distinguished by address bit A 1 The first five bits and the last bit of a 16bit address are always zero The 11bit address bus MCU pins AD 10 00 is shown below Address A 23 16 are not used MCU port 0 and port 1 are reused for data and address bus 0 0 0 0 0 X X X X X X X X X X 0 Always zero Address A 10 2 A 1 A 0 Table 3 1
37. tion with MCU pins Function pin Nr 53 AD10 87 1 2 AD10 54 AD9 86 1 1 ADO9 55 AD8 85 P01 0 ADO8 56 AD7 84 00 7 ADO7 57 AD6 83 00 6 ADO6 Address data bus 58 AD5 82 5 ADO5 MCU amp CC 59 AD4 81 00 4 ADO4 60 AD3 80 00 3 ADO3 61 AD2 79 00 2 ADO2 62 AD1 78 POO 1 ADO1 63 ADO 77 00 0 ADOO Function 46 015 1 7 AD15 47 D14 95 P01 6 AD14 Data bus 50 D13 94 P01 5 AD13 MCUSCC 51 D12 89 P01 4 AD12 52 D11 88 1 3 AD11 Function MCU pin Nr Name 10 INTO 46 PO7_1 INT1 34 INT1 47 P07 2 INT2 Interrupt output 35 INT2 CC gt MCU 48 P07 3 INT3 36 INT3 49 P07 4 INTA 37 4 50 P07 5 INT5 CC pin Nr Function MCU pin Nr 6 RST Reset 15 BCLK Bus clock 12 19 CS Chip select 72 09 5 CS2 3 MCU gt CC 20 RD Read enable 6 P03_1 RDX 21 WR Write enable 7 P03_2 WRLXWRX 22 ALE Address latch 5 P03_0 ALE enable 27 RDY Ready signal 11 P03_6 RDY CC gt MCU 31 DMA_REQ DMA request 55 P07 6 INT6 CC mode pins Nr Function type Logic value 64 MD2 Mode selection IN 1 16bit parallel bus interface 4 MD1 0 MCU AN 300046 E V10 8 Fujitsu Microelectronics Europe GmbH co Interfacing MB96340 TO MB88121 Chapter 2 Connection example MB96F348RS MB88121B FUJITSU 5 MDO 0 28 MDE2 0 Extended mode Multiplexed mode MDE1 selection 5 for 16FX 30 MDEO 1
38. ultiplexed bus mode register EBAEO and control the address output of the pins AD15 AD00 As the 16 bit multiplexed mode is used ADOO AD15 needs to be enabled Fujitsu Microelectronics Europe GmbH 19 MCU AN 300046 E V10 co Interfacing MB96340 TO MB88121 FUJITSU Chapter 3 Configuration 3 4 4 External Bus Control Signal register EBCS Register EBCS enables disables the control signals of the external bus Corresponding parameter file start asm Bit Function 15 N N N 0 Address strobe is low active AS function 1 Address strobe is high active ALE function 14 ASL ADDRESS STROBE LVL 0 Address strobe output ALE AS disabled 13 ASE ADDRESS STROBE 1 Address strobe output ALE AS enabled 0 Read strobe output RD disabled 12 READ STROBE 1 Read strobe output RD enabled 0 Write strobe output WRH disabled 11 WRHE HIGH WRITE STROBE 1 Write strobe output WRH enabled 0 Write strobe output WRL IWR disabled 10 WRLE LOW WRITE STROBI 1 Write strobe output WRL WR enabled 0 Byte select output UB disabled 9 NENNEN HIGH BYTE SIGNAL 1 Byte select output UB enabled 0 Byte select output LB disabled 8 LBE LOW BYTE SIGNAL 1 Byte select output LB enabled Gray Settings used for MB88121 connectivity Table 3 9 Register EBCS
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