STM32-H103 user`s manual
Contents
1. STM H103 development board user s manual Rev B March 2014 Copyright c 2014 OLIMEX Ltd All rights reserved Page 1 of 18 INTRODUCTION STM32 H103 board is an entry level development board for the new ARM Cortex M3 family of devices produced by ST Microelectronics Inc With STM32 H103 you can explore the features of STM32 family on budged the board have everything necessary to build simple applications USB port where power is taken and power supply circuit reset and oscillator circuits JTAG port for programming and debugging two status LEDs and user button Although a very simple board it is sufficient to easily build USB application like PC mouse USB mass storage device USB Audio class device USB to Virtual RS232 port There are plenty of GPIOs on extension headers where you can connect your additional circuits BOARD FEATURES CPU STM32F103RBT6 ARM 32 bit CORTEX M3 JTAG connector with ARM 2x10 pin layout for programming debugging with ARM JTAG ARM USB OCD ARM USB TINY USB connector user button RESET button status LED power supply LED on board voltage regulator 3 3V with up to 800mA current single power supply takes power from USB port or extension connector pin 8 Mhz crystal oscillator 32768 Hz crystal and RTC backup battery connector extension headers for all uC ports PCB FR 4 1 5 mm 0 062 soldermask silkscreen component print Dimensions 61x 34mm 2 4 x2. Page 8 of 18 EXTERNAL CONNECTOR DESCRIPTION EXTENSION 1 ETE Signal Name ETE Signal Name PA12 USBDP CANTX PA9 UART1 TX 2 26 e PC11 USBpull PC12 LED Page 9 of 18 EXTENSION 2 Poe Semin TP Stone som d foe pomme e m s m e esum Page 10 of 18 JUMPER DESCRIPTION R T connects JTAG TRST signal to STM32F103RBT6 RESET Default state closed shorted VBAT connects 3 3V to STM32F103RBT6 Vbat pin 1 Default state closed shorten Vbat signal is also available to EXT1 23 so if you want to connect external backup battery to the STM32F103RBT6 this jumper should be opened unshorted and the external battery to be connected to EXT1 23 pin USBP E connects USB power supply to STM32F103RBT6 pin 24 PC4 ADC14 and allow to detect if the board is connected to USB host Default state closed shorten LED E connects STATUS LED to STM32F103RBT6 pin 53 PC12 Default state closed shorten BOOTO BOOTI1 boot sequence select B1_H BI L Bootl High Bootl Low BO H BO L Boot0 High Boot0 Low Default position Bootl is log 0 Boot0 is log 0 Boot mode selection pins Boot mode BOOT1 BOOTO User Flash memory User Flash memory is selected as boot space x 9 Oo SystemMemory SystemMemory is selected as boot space pa f oa Embedded SRAM Embedded SRAM is selected as boot space Page 11 of 18 INPUT OUTPUT lT AG TMS TCK TDI TDO TRST Input Input Input Output Input User butto
3. products Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material from except with the prior written permission of the copyright holder The product described in this document is subject to continuous development and improvements All particulars of the product and its use contained in this document are given by OLIMEX in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product OLIMEX Ltd shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Page 18 of 18
4. The TRST pin can be used to reset the test logic within the EmbeddediCE logic Page 12 of 18 RS232 STM32F103RBT6 have 3 USARTs which are available on the extension headers One of them can operate up to 4 5 Mbit s the other two up to 2 25 Mbit s They provide hardware management of the CTS and RTS signals IrDA SIR ENDEC support are ISO 7816 compliant and have LIN Master Slave capability All USART interfaces can be served by the DMA controller USARTI Tx pin 42 PA9 EXTI 4 USARTI Rx pin 43 PA10 EXT1 7 USART2 Tx pin 16 PA2 EXT2 7 USART2 Rx pin 17 PA3 EXT2 10 USART3 Tx pin 29 PB10 EXT2 14 USART3 Rx pin 30 PB11 EXT2 15 STM32F103RBT6 have 2 SPIs which able to communicate up to 18 Mbits s in slave and master modes in fullduplex and simplex communication modes The 3 bit prescaler gives 8 master mode frequencies and the frame is configurable from 8 bit to 16 bit The hardware CRC generation verification supports basic SD Card MMC modes Both SPIs can be served by the DMA controller SPII NSS pin 20 PA4 EXT2 11 SPII SCK pin 21 PAS EXTI 18 SPII MISO pin 22 PA6 EXTI 14 SPII MOSI pin 23 PA7 EXT1 22 SPI2 NSS pin PB12 SPI2 SCK pin PB13 SPI2 MISO pin PB14 SPI2 MOSI pin PB15 STM32F103RBT6 have two PC bus interfaces which can operate in multi master and slave modes They can support standard and fast modes They support dual slave addressing 7 bit only and both 7 10 bit addressing i
5. byte 1 Kbit ox4000 6000 USBICAN SRAM USB Registers 1 Kbit 0x4000 5C00 d 0x4000 5800 1 Kbit 0x4000 5400 0x4000 4C00 USART3 1 Kbit Bu 0x4000 4800 aen memory USART2 1 Kbit 0x4000 4400 T TI 0x0800 0000 2 Kbits 0x4000 3C00 0x4000 3800 0x4000 3400 1 Kbit 0x4000 2C00 0x4000 2800 0x4000 0C00 1 Kbit 0x4000 0800 TIM3 1 Kbit 0x4000 0400 0x4000 0000 TIM2 1 Kbit ai14394b 0x4000 6C00 reserved 0x4000 0000 Peripherals 0x2000 0000 0x0000 0000 Reserved Page 7 of 18 POWER SUPPLY CIRCUIT STM32 H103 can take power from two sources USB connector where SV power supply is applied by USB host Vin input in extension pin EXT2 26 where 5 9V may be applied The board power consumption is about 40 mA with all peripherials and MCU running at full speed there are different power saving modes which may put STM32F103RBT6 in power sleep mode and in these modes the consumption of the MCU is only few micro ampers RESET CIRCUIT STM32 H103 reset circuit is made with RC group R8 10K and C19 100nF Although on the schematic is made provision for external reset IC such is not necessary as STM32 have build in brown out detector Manual reset is possible by the RESET button CLOCK CIRCUIT Quartz crystal 8Mhz is connected to STM32F103RBT6 Internal PLL circuit can multiply this frequency up to 72Mhz 32 768 KHz quartz crystal is connected to STM32F103RBT 6 for it s internal Real Time Clock
6. 1 3 Distance between the extension connectors 25 4 mm 1 ELECTROSTATIC WARNING The STM32 H103 board is shipped in protective anti static packaging The board must not be subject to high electrostatic potentials General practice for working with static sensitive devices should be applied when working with this board BOARD USE REOUIREMENTS Cables 1 8 meter USB A B cable to connect to USB host Hardware ARM JTAG ARM USB OCD ARM USB TINY or other ARM JTAG compatible tool Software ARM C compiler and debugger software the possible options are free open source platform GNU C compiler OpenOCD and Eclipse support all low cost Olimex JTAG debuggers commercial solution EW ARM from IAR Systems AB require expensive J LINK debugger CrossWorks from Rowley supports all Olimex low cost JTAG debuggers Page 2 of 18 BOARD LAYOUT v regulator reset BUTTON buenas USB bea 1 owe F sen I E il time E i ved wt wet P m ows rvs T ni tant LOCOCO AAT RAT IAT CRT ONT ENT RIT RITRATTI bbkttEEDEEE E ETE o x kite sed oes e stat LED STA AA UII OLIMEK COMZD EU 02 2007 user BUTTON quartz crystal JTAG extension header 2 ILU E T Ma 26 R TIT en cg VAI 2 NE Own a ME 44 dg t JF si A fi dT i cad P X PES k ic Mo A y Li w cent V Peri da arte a ad a2 Oi 23 UBAT Eust i UUU OliMex COM extension header 1 Page 3 of 18 SCH
7. C 2 AF alternate function on I O port pin Page 6 of 18 Fimax 24 36 MHz APB1 pr XTAL OSC OSC_OUT 4 16 MHz Stand by interface BAT OSC32_IN OSC32_OUT TAMPER RTC lt a TIM2 lt gt 4 Channels c TIM3 lt gt 4 Channels gt TIM 4 lt gt 4 Channels USART2 CK SmartCard as AF RX TX CTS RTS UD USART3 CK SmartCard as AF Q SPI2 lt _ gt MOSI MISO SCK NSS as AF E gt 1201 K gt SCL SDA SMBAL as AF CS 1202 Cor SCL SDA as AF lt bxcan USBDP CANTX USBDM CANRX lt 5 UsB20FS lt DI SRAM 5128 gt RT ai14390b MEMORY MAP Memory mapping The memory map is shown in Figure 7 Figure 7 Memory map APB memory space OxFFFF FFFF reserved OxEO10 0000 0x6000 0000 0x4002 3000 0x4002 2400 0x4002 2000 0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000 reserved 1 Kbit 0x4002 3400 OxFFFF FFFF op mM iii Cortex M3 Internal 0xE000 0000 Peripherals 0x4001 3C00 USART1 1 Kbit 0x4001 3800 0x4001 3400 1 Kbit TIM1 1 Kbit 0x4001 2C00 ADC2 1 Kbit 0x4001 2800 ADC1 1 Kbit 0x4001 2400 0x4001 1C00 0x4001 1800 OxlFFF FFFF reserved OxlFFF F80F 0x4001 1400 Option Bytes 0x4001 1000 OxlFFF F800 daoni GODS 0x4001 0800 System memory 0x4001 0400 0x4001 0000 OxlFFF F000 0x4000 7400 0xC000 0000 0x4001 3000 0xA000 0000 0x8000 0000 0x6000 0000 1 Kbit 1 Kbit 1 Kbit 0x4000 6800 bxCAN 1 Kbit 0x4000 6400 shared 512
8. EMATIC Please note that the schematic suits two boards STM32 H103 and SMT32 H405 There is a slight variation mentioned over the microcontroller 3 34 3 3U 3 3U UDDA 2 ee STM32F 485RET6 lt LQF P64 is mounted C20 and C23 must be populated 3 3U en STM32F103RBT6LQFP64 is mounted C20 and C23 must be short circuit for example with 0 Ohm resistor Q Q L1 CO 3 U1 s symbol refers to STM32F1 3RBT6 LQFP64 B1 H B41 L ferrite bead For the STM32F4 5RET6 lt LQFP64 please see the corresponding datasheet default to B1 L 1 3 pa PB0 ADC8 TIM3_CH3 TIM1_CH2N EXT1 21 R28 NE U2 10k 10uF 190 PB1 ADC9 TIM3_CH4 TIM1_CH3N EXT1 26 33K NA UBAT PB2 BOO0T1 SEU SS 2 fi RST TE PB3 JTDO TIM2_CH2 TRACESWO SPI1_SCK UCC RESET PB4 JTRST TIM3_CH1 SPI1_MISO a e XU LA BUT t c19 PB6 12C1_SCL TIM4_CH1 USART1_TX EXT1 13 a ee me 4 n PB7 12C1_SDA TIM4_CH2 USART1_RX EXT1 15 RA ie Vi a PERO PB8 TIM4_CH3 12C1_SCL CANRX EXT1 16 ic a 160nF c C5 lee c gt FS PB9 TIM4_CH4 12C1_SDA CANTX EXT1 17 1QuF 48U PB10 12C2_SCL USART3_TX TIM2_CH3 EXT2 14 NE LT E C20 sn PB11 12C2_SDA USART3_RX TIM2_CH4 EXTZ L5 uno RIS M IE e USS uceo 1 PB12 SPI2 NSS I2C2 SMBRL USART3 CK TIMA BKIN EXT2 17 O 3 3U S E USS ucap_2 PB13 SPI2_SCK USART3_CTS TIM1_CH1N EXT2 16 33K RST USS PB14 SPI2_MISO USART3_RTS TIM1_CH2N EXT2 18 3 3U USS PB15 SPI2_MOSI TIM1_CH3N EXT2 19 R6 R25 N ig EXT1 25 RSI 7 NRST PCO ADC10 EXT1 19 VW STAT i fi i R T BOOTE a PC1 ADC11 E
9. XT1 20 x led0603 gree Z i 4 9 sm BOOT PC2 ADC12 EXT2 2 a 10K 10K TRST BUT 14 PC3 ADC13 EXT2 9 ECT pec rA EXT2 4 15 PA WKUP USART2_CTS ADC TIM2_CH1_ETR PC4 ADC14 EXT2 12 R4 e a a a oS EXT2 8 E PA1 USART2_RTS ADC1 TIM2_CH2 PC5 ADC15 EXT2 13 2k ae EXT2 7 F PA2 USART2_TX ADC2 TIM2_CH3 PC6 TIM3_CH1 EXT2 20 11 PZA 18k EXT2 10 36 PA3 USART2_RX ADC3 TIM2_CH4 PC7 TIM3 CH2 EXT2 24 EXT2 41 aT PA4 SPI1_NSS USART2_CK ADC4 PC8 TIM3_CH3 EXT2 22 a EXT1 18 zz PA5 SPI1_SCK ADC5 PC9 TIM3_CH4 EXT2 24 17 RD 18k EXT1 14 33 PAG6 SPI1_MISO ADC6 TIM3_CH1 TIM1_BKIN PC1 USART3_TX EXT1 8 hg ps 43 EXT1 22 2 PA7 SPI1_MOSI ADC7 TIM3_CH2 TIM1_CH1N PC11 USART3_RX EXT1 9 EXT1 2 32 PAS USART1_CK TIM1_CH1 MCO PC12 USART3_CK EXT1 10 EXT1 4 PAS USART1_TX TIM1_CH2 PC13 ANTI_TAMP EXT1 24 JTAG EXT1 7 B t PA1 USART1_RX TIM1_CH3 PC14 0SC32_IN EXT1 1 PA11 USART1_CTS CANRX USBDM TIM1_CH4 PC15 0SC32 OUT USB_P 5U USB FXT2 23 3 30 EXT1 3 USBDP do PA12 USART1_RTS CANTX USBDP TIM1_ETR ci le e Po N a PA14 JTCK SWCLK PD1 0SC_OUT SEO PA15 JTDI TIM2_CH1_ETR SPI1_NSS PD2 TIM3_ETR EXT1 11 SA RE STM32F405RET6CXLQFP 64 STM32F103RBT6 LQF P64 TRST TDI TMS TCK TDO RST 3 D2 VIN irm EXT2 26 UDDA fec EXT2 1 Pz 1N5819S C21 C22 DA mE 3 3U 100nF 100nF Pa 1N5819S UR O EXT2 25 EXT2 3 LM1117 iih IN QUT Rec 33 EXT1 5 3 3U EXT2 5 USBDM R10 EXT T I EXT2 6 m a 05 ESP E dea 240 1 gy PHR S e t OHH de 4 USBDP C1 C2 C24 C3 C4 ia _____ STM32 H193_H405 board rev
10. er to check the schematics and the board design files to compare the differences Document revision history board rev A 1 Replaced boot jumpers from 2 pin package to 3 pin package 2 Connected VUSB to PC4 ADC14 through ladder 3 Change BH to reiki board rev B 1 R3 now changed from 10K to 47K 2 Added D2 so the board cab be powered from JTAG pin 19 3 C8 gets changed from 100nF to 4 7uF 6 3V according to the datasheet board rev C 1 Added C20 and C23 capacitors on processor pins 31 and 47 which change whether you have STM32 H103 or STM32 H405 board If there STM32F103RBT6 LQFP64 c20 and c23 would be 0 Ohm resistors If there STM32F103RBT6 LQFP64 c20 and c23 would 2 2uF 6 3V be resistors 2 C11 ot 10uF 6 3V is now 10uF 10V 3 C8 ot 4 7uF 6 3V is now 10uF 10V 4 C3 ot 47uF 6 3 becomes 22uF 6 3V parallel to it we add C24 22uF 6 3V 5 All resistors capacitors and the LED diodes are now in 0603 package 6 The VBAT USBP E LED E are now closed by default 7 R16 bow becomes OR Board Mounted Page 17 of 18 Disclaimer 2014 Olimex Ltd All rights reserved Olimex logo and combinations thereof are registered trademarks of Olimex Ltd Other terms and product names may be trademarks of others The information in this document is provided in connection with Olimex products No license express or implied or otherwise to any intellectual property right is granted by this document or in connection with the sale of Olimex
11. ision C se Te C17 C16 188nF gt R9 g l R Cas 3 390 17 6 S 2k Olimex LTD PLOUDIU BULGARIA 2014 Loone 47pFXNe 47pF NAD a i 8 GR Board Mounted a https wuuwu olimex com Page 4 of 18 PROCESSOR FEATURES STM H103 board use ARM 32 bit Cortex M3 CPU STM32F103RBT6 from ST Microelectronics with these features CPU clock up to 72Mhz FLASH 128KB RAM 20KB DMA x7 channels RTC WDT Timers x3 1 SPI x2 I120x2 USART x3 USBxl CANxI multiplexed with USB so both can t be used in same time GPIO up to 51 multiplexed with peripherials 2 ADC 12 bit Operating voltage 2 0 3 6V temperature 40C 85C Page 5 of 18 Figure 1 STM32F103xx performance line block diagram TRACECLK TRACEDIO 3 TPU Trace as AS M ML Traceltrig C pus 7 Controlle r JNTRS gt SWIJTAG JTDI JTCK SWCLK Cortex M3 CPU JTMS SWDIO JTDO se Fmax 72 MHz 7 channels SUPPLY SUPERVISION POR PDR 80AF WES PA 15 0 lt gt emo K Penso K cPos KED gt PC 15 0 lt gt emo KE Ponso K eroon KK gt PE 15 0 lt lt 0 EIE 4 Channels 3 compl Channels oe Brk input MOSI MISO SCK NSS as AF my SPI1 RX TX CTS RTS Smart Card as AF 5 gt USART1 GDA 12bit ADC IF 12bit ADC2 12bit ADC2 IF n rrmmc e io POWER Vpp 2 to 3 6V VOLT REG V 3V TO 1 8V SS Flash 128 KB ALSO 64 bit 1 Ta 40 C to 105 C junction temperature up to 125
12. n master mode A hardware CRC generation verification is embedded They can be served by DMA and they support SM Bus 2 0 PM Bus I2C1 SDA pin 59 PB7 EXT1 15 I2C1 SCL pin 58 PB6 EXT1 13 I2C1 SMBA pin 57 PB5 EXT1 12 I2C2 SDA pin 30 PB11 EXT2 15 I2C2 SCL pin 29 PB10 EXT2 14 I2C2 SMBA pin 33 PBI2 EXT2 17 Page 13 of 18 CAN ADC The STM32F103RBT6 CAN is compliant with specifications 2 0A and B active with a bit rate up to 1 Mbit s It can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers It has three transmit mailboxes two receive FIFOs with 3 stages and 14 scalable filter banks The CAN and USB share same pins PAI1 EXT1 1 and PA12 EXT1 3 so you can t use both CAN and USB on same time The STM32F103RBT6 embeds a USB device peripheral compatible with the USB Full speed 12 Mbs The USB interface implements a full speed 12 Mbit s function interface It has software configurable endpoint setting and suspend resume support The dedicated 48 MHz clock source is generated from the internal main PLL The CAN and USB share same pins PA11 EXT1 1 and PA12 EXT1 3 so you can t use both CAN and USB on same time STM32F103RBT6 have two 12 bit Analog to Digital Converters which share up to 16 external channels performing conversions in singleshot or scan modes In scan mode automatic conversion is performed on a selected group of analog inputs Addi
13. n with name BUT connected to STM32F103RBT6 pin 14 PAO WKUP Status green LED with name STAT connected to STM32F103RBT6 pin 53 PC12 note that LED E SMT jumper should be shorted to may LED work properly it s shorted by default if you decide to use PC12 port for other purpose you have to remove the solder short on this jumper which will disconnect the LED from PC12 port Power supply red LED with name PWR indicates that 3 3V power supply is applied The JTAG connector allows the software debugger to talk via a JTAG Joint Test Action Group port directly to the core Instructions may be inserted and executed by the core thus allowing STM32F103RBT6 memory to be programmed with code and executed step by step by the host software For more details refer to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture and STM32F103RBT6 datasheets and users manual JTAG CONNECTOR PIN DESCRIPTIONS E Signal Name KCN Signal Name Test Mode Select The TMS pin selects the next state in the TAP state machine Test Clock This allows shifting of the data in on the TMS and TDI pins It is a positive edgetriggered clock with the TMS and TCK signals that define the internal state of the device Test Data In This is the serial data input for the shift register Test Data Output This is the serial data output from the shift register Data is shifted out of the device on the negative edge of the TCK signal Test Reset
14. tional logic functions embedded in the ADC interface allow Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all selected channels An interrupt is generated when the converted voltage is outside the programmed thresholds The events generated by the standard timers TIMx and the Advanced Control timer TIM1 can be internally connected to the ADC start trigger injection trigger and DMA trigger respectively to allow the application to synchronize A D conversion and timers Page 14 of 18 MECHANICAL DIMENSIONS OOOOOOOOO DQOOO JOLIMEX COM DEU lt C gt 2087 Page 15 of 18 AVAILABLE DEMO SOFTWARE DEMOI Blinking LED for EW ARM 5 11 Blinks the on board LED DEMO2 USB mouse for EW ARM 5 11 Creates USB mouse and when board is connected to PC it starts moving the mouse cursor in circle DEMO3 Blinking LED for GCC OpenOCD Eclipse Blinks the on board LED Page 16 of 18 ORDER CODE STM32 H103 assembled and tested no kit no soldering required How to order You can order to us directly or by any of our distributors Please visit our web site www olimex com for more info Potes See All boards manufactured by Olimex LTD are ROHS compliant Document revision history REV A created February 2008 REV B updated March 2014 Rememb
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