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User Manual - Hytec Electronics Ltd

1. D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DO1 D00 DC15 DC14 DC13 DC12 DC11 DC10 DC9 DC8 DC7 DC6 DCS DC4 DC3 DC2 DC1 DCO Write a 1 to disable a channel i e DC 1 Channel 1 is disabled 5 4 14 Change of Function Register I O address 59 Read Write register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DO1 D00 Do Do Not Note Fl FO CH L3 L2 Ll LO set set LO L3 This shows the configuration of the logic types 00 Standard logic setup with LVDS 01 Standard logic setup with LTTL Note Other logic types may be possible consult Hytec CH Change function This loads the Preset Scaler application into FPGA FO F1 This shows which function is loaded in FPGA 00 Histogram function 01 Preset scaler function Page 16 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 5 Select TTL level Register I O address 60 Only in version V105 and above Read write register This allows the TTL logic level of the unit to be set D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DO1 DOO PS3 PS2 PS1 PSO PS0 This sets Trigger to accept active high LVTTL when 0 or active Low LVTTL when 1 Trigger
2. The Trig EBA input can be up to 20MHz but with the restriction that the combination of the rate and the number of divides as set by the register is no shorter than the minimum allowed dwell time of the device see relevant section on Dwell times If zero or one is entered will count for one gate interval D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DOI DOO T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 TO Page 14 D Hytec Electronics Ltd 5 4 5 Number of Cycles Triggers Register I O address 50 Read write register Specifies the number of cycles in Histogram mode or the number triggers in straight scaler mode In straight scaler mode can have up to 32K of 32bit data for each channel If zero is entered unit will not start in either mode MCS8522 UTM 3 0 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DOI DOO C15 C14 C13 C12 Cll C10 CH C8 C7 C6 C5 C4 C3 C2 Cl CO T14 T13 T12 T11 TIO T9 TS T7 T6 TS T4 T3 T2 Tl TO 5 4 6 Number of Gates per cycle memory depth Register I O address 51 Read write register Specifies the number of time bins gates per cycle in Histogram mode Each channel can have a maximum of 16k 1 64bit bins In Scaler mode this register is not used If zero is entered in
3. D06 DOS D04 D03 D02 DOI DOO V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 Vi VO Page 15 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 4 10 Interrupt Disable Register UO address 55 Read write register Writing a 1 to bit zero causes the Interrupt Enable bit IE in the CSR to be cleared D15 D14 D13 D12 D11 D10 D09 DOs DO7 DO6 DOS Do4 DO3 D02 DOI DOO 5 4 11 Memory pointer LSW Register I O address 56 Read register LSW of memory pointer when in scaler mode In Histrgram mode the memory pointer holds the start address for the next 16x64bit data address In Straight and Prescler mode the memory pointer holds the start address for the next 16x32bit data address D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DOI DOO A15 A14 A13 Al2 All A10 A9 AN A7 A6 A5 A4 A3 A2 Al AO 5 4 12 Memory pointer MSW Register I O address 57 Read register MSW of memory pointer when in scaler mode D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO a x 3 a 2 a a 7 A19 A18 A17 Al6 5 4 13 Mask Channel Input I O address 58 Write register Disable channels
4. D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 S31 530 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 Both these registers are cleared when a reset is issued 5 4 2 Coincidence Registers UO Address 32 47 Read write register Coincidence Registers 0 to 15 are held in the I O space of the IP scaler card The coincidence registers may be read at addresses 20 2F D15 D14 D13 D12 D11 D10 DOI D08 D07 D06 DOS D04 D03 D02 DOI DOO C15 C14 C13 C12 Cll ClO C9 ICH C7 C6 C5 C4 C3 C2 IC CO Each scaler has an AND coincidence pattern for the 16 inputs which operates when EC is a alee Page 13 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 4 3 Control amp Status Register CSR I O Address 48 Read write register Control and Status bits D15 D14 D13 D12 D11 DIO DOI DOS D07 D06 DOS D04 D03 D02 DO1 DOO ETM TSI TSO EBA EXET MDO TM FF EC ST ER ET IE R IRQ IRQ Interrupt Request generated when the programmed number of cycles triggers is reached Read only R Reset writing a 1 to this bit resets all the counters and memory to zero This bit also indicates when clear memory routine has started 1 and f
5. 21 GND AM2 AM3 GND N C IACKOUT P1B22 NC Pic22 ale PiD22 33y Ir GND B22 NIC B23 GND P1 C23 P1 D23 N C P1 Z23 B24 IRQ7 P1 C24 P1 D24 3 3V P1 Z24 B25 A32 5V P1 Pin Assignment P P P P P B26 B27 B28 B29 B30 IRQ5 IRQ4 IRQ3 IRQ2 IRQI B32 5V Page 30 D Hytec Electronics Ltd MCS8522 UTM 3 0 C AGND GND N C E GND P2 Z08 P2 Z09 P2 Z P2 D P2 Z P2 Z P2 Z P2 Z P2 Z P2 Z P2 Z P2 A18 A Chan 13 P2 B18 P2 C18 AChan13 P2 D18 BChan11 P2 Z G P2 Z P2 A20 AChan 15 P2 B20 P2 C20 AChan15 P2 D20 BChan13 P2 22 C C A Chan 16 4 N C A Chan 16 B Chan 14 N C ND N C B Chan 14 A X Trigger N C A XTrigger B Chan 15 N N C N C B Chan 16 4 C 4 C C C C C N P2 22 P2 22 P2 22 N d IC Ur P2 Z2 P2 Z3 Out 3 3V Out 3 3V P2 Z31 Out 3 3V P2 A32 P2 B32 P2 C32 Out 5V PC 5V P2 Z32 P2 pin assignment C C P2 22 ND Denotes pins with thickened tracks which can be used for power inputs Page 31
6. NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL SAFE PERFORMANCE SUCH AS IN LIFE SUPPORT OR SAFETY DEVICES OR SYSTEMS CLASS II MEDICAL DEVICES NUCLEAR FACILITIES APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE INDIVIDUALLY AND COLLECTIVELY CRITICAL APPLICATIONS FURTHERMORE SOME COMPONENTS USED IN THIS HYTEC ELECTRONICS LTD PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT UNLESS THERE IS A FAIL SAFE OR REDUNDANCY FEATURE AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR THE CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF HYTEC ELECTRONICS LTD PRODUCT IN CRITICAL APPLICATIONS Page 2 D Hytec Electronics Ltd MCS8522 UTM 3 0 CONTENTS 1 INTRODUCTION oooncccocconoononnonoonnonoonoononnonconconoononncnnoncononanonoonconcononconconcononccanonnononcroncononronornonncnnnos 5 2 MODES OF OPERATION ccsscsssssscssesssesscsssessssscsssssscssesssessessesssessessesssssscssssssessosssesssssossoss 6 2 1 Saale eege 6 22 STRAIGHT SCALER MODE aa eek e beta de de lil 6 2 3 PRESET SCALERMMODE soda ddr iran oso CERN Eed KEEN EEN 6 3 PRODUCT SPECIFICATIONS sscssscsscscscosssoesessasesesscssesesessesssseseseosssoesessasesesscosssessesesvasesssseoseoeseuss 7 4 LOGIC SIGNAL LEVELS e seseesossesessesossesosses
7. Output driven from Trigger IN PS1 This sets External Reset to accept active high LVTTL when 0 or active Low LVTTL when 1 PS2 Sets Scaler Inputs to drive active high LVTTL when 0 or active Low LVTTL when 1 This is only applicable when unit is configured for TTL scaler in puts and has no effect when in LVDS mode PS3 This sets Trigger Enable to accept active high LVTTL when 0 or active Low LVTTL when 1 5 5 1 Counter Source I O address 62 Read write register D15 D14 D13 D12 D11 DIO D09 DOS D07 D06 DOS D04 D03 DO2 DO DOO CS 15 CS 14 CS 13 CS 12 CS 11 CS 10 CS9 CS8 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CSO Write 1 to select internal counter clock or 0 to selects external input in to the counter for each channel The internal counter clock is set by bits 13 and 14 of the CSR CSR 14 CSR 13 Internal Counter Clock 0 0 25MHz 0 1 50MHz 1 0 100MHz 1 1 200MHz 5 6 Internal and External Reset When an internal or external Reset is issued the follow registers and logic are reset Scan Enable lines cleared Nos Cycles and or Triggers Received register is cleared Memory Cleared both external RAM and FPGA RAM Page 17 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 7 External Time Bin Advance EBA The next time bin can be advance to via the External Bin Advance EBA inp
8. bit time bins for each channel This memory is accessed when the ETM bit in the CSR is set to 0 Organisation of Time Bin Data in External RAM Memory 1M x 16 bits memory External RAM Memory allocation 16 Bit IP Card Address CSR 15 0 16K x64bit time bins for channel 16 Base 960K 16K x64bit time bins for channel 15 Base 896K 16K x64bit time bins for channel 14 Base 832K 16K x64bit time bins for channel 13 Base 768K 16K x64bit time bins for channel 12 Base 704K 16K x64bit time bins for channel 11 Base 640K 16K x64bit time bins for channel 10 Base 576K 16K x64bit time bins for channel 9 Base 512K 16K x64bit time bins for channel 8 Base 448K 16K x64bit time bins for channel 7 Base 384K 16Kx64bit time bins for channel 6 Base 320K 16Kx64bit time bins for channel 5 Base 256K 16Kx64bit time bins for channel 4 Base 192K 16Kx64bit time bins for channel 3 Base 128K 16Kx64bit time bins for channel 2 Base 64K 16Kx64bit time bins for Channel 1 Time Bin 16K MSW 16 bit Time Bin 16K Third 16 bit word Time Bin 16K Second 16 bit word Time Bin 16K LSW 16 bit Base OK Time Bin 1 MSW 16 bit Time Bin 1 Third 16 bit word Time Bin 1 Second 16 bit word Time Bin 1 LSW 16 bit Page 10 D Hytec Electronics Ltd MCS8522 UTM 3 0 Totaliser Memory Organisation of the sixteen 64 bit totaliser registers in FPGA RAM Memory 64 bit words for the t
9. differential signaling standards LVDS requires that one data bit is carried through two signal lines and it has an inherent noise immunity over single ended I O standards The voltage swing between two signal lines is approximately 350 mV The use of a reference voltage VREF or a board termination voltage VTT is not required LVDS requires the use of two pins per input or output LVDS has onboard 100ohm resistor termination implemented in FPGA on the unit Ry 1000hm 0 O LVDS Termination Scheme 8 3 J1 Pull up or Pull down For TTL Logic Signals The jumper J1 allows the user to pull up to 3 3V or 5V or pull down to ground SR J1 8522 INPUT O Scaler FPGA Ext Trig IN INPUTS Ext Trig Enable AND Ext Reset oa eae SET TO OUTPUT LTTL Ext Trig OUT Page 26 D Hytec Electronics Ltd APPENDIX A VO Connector 50 way on 8522 Scaler Board Signal a 5 MCS8522 UTM 3 0 Signal 4 BW dh Nn ac UY IO1 Pl 102 N 103 P2 104 N 105 N oN 27 NIN O 0 1026 N13 16 106 N 31 1031 P SION 107 P LA N 1032 N16 00 BER WW 108 N 109 P5 33 1033 P17 ExtRST 1034 N17 ES ole n w pP oy 15 1015 P 40 1040 IN20 1018 N9 43 GND 1019 P10 44 1042 22 1022 NI 47 GND 1023 P12 48 1044 nN 1010 N 35 1035 P18 TRIGOUT N VWOloo o0 _ Signal Naming Key IO5_P3 can be single en
10. the trigger input When the gate interval is finished the counter values are loaded in memory The number of logged values is set in the Nos Cycles Triggers register When the programmed number of triggers as set in the Number of Triggers register has occurred and the sequence completed the Finished Flag FF in the CSR is set and an interrupt is generated if enabled The current memory address is given by the Memory pointer registers LSW and MSW The memory pointer holds the start address for the next 16x32bit data address 5 2 1 Memory Layout Straight Scaler Mode 512K x 32 bits memory External RAM Nos Triggers Memory allocation 32bits IP Card Address CSR 15 0 32k Chan 16 Base 32k Chan 15 Base 32k Chan 3 Base 32k Chan 2 Base 32k Chan 1 Base 2 Chan 16 Base 60 2 Chan 15 Base 58 2 Chan 2 Base 34 2 Chan 1 Base 32 1 Chan 16 Base 30 1 Chan 15 Base 28 1 Chan 3 Base 4 1 Chan 2 Base 2 1 Chan 1 Base 0 5 3 Automated Memory Clear Both internal FPGA RAM and external RAM are automatically cleared by issuing a Reset R in the CSR bit 1 Or if the Enable External Reset bit ER bit 4 is set and the External reset pin is taken high The CSR bit 1 indicates when clear memory routine has started 1 and finished 0 for both hardware and software resets clears It takes approx 80ms for the whole of the external ram memory to be cleared
11. 1 CS 10 CS9 CS8 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CSO Write 1 to select internal counter clock or 0 to selects external input in to the counter for each channel The internal counter clock is set by bits 13 and 14 of the CSR CSR 14 CSR13 Internal Counter Clock 0 0 25MHz 0 1 50MHz 1 0 100MHz 1 1 200MHz 6 3 Internal and External Reset Preset Scaler Mode When an internal or external Reset is issued the follow registers and logic are reset Scan Enable lines cleared and scanning stopped All counters and shadow registers are cleared to zero The Overflow register is cleared Finish flag FF in CSR cleared Page 23 D Hytec Electronics Ltd MCS8522 UTM 3 0 7 ID PROM The 8522 IP module includes a configuration ID PROM The ID information held in the PROM is as detailed below The byte addresses of the ID PROM are as below Base 80 Base 82 Base 84 Base 86 Base 88 Base 8A Base 8C Base 8E Base 90 Base 92 Base 94 Base 96 Base 98 Base 9A ASCII VI 5649h ASCII TA 544 1h ASCII 4 3420h Hytec ID high byte 0080h Hytec ID low word 0300h Model number 8522h Revision 1101h This shows PCB Issue 1 and Xilinx V101 means FPGA at issue 1 for PCB issue 1 Reserved 0000h Driver ID 0000h Driver ID 0000h Flags 0002h No of bytes used 001Ah Funtion Logic Type Histogram 00xxh Preset Scaler 01xxh Serial
12. 1 Total 95 1 Trig NC 52 NC 53 NC 42 NC 39 NC 20 NC 80 NC 95 381 Cyc 1 Total 52 Total 53 Total 42 Total 39 Total 20 Total 80 Total 95 Set by Time Bin Time Bin Time Bin Time Bin Time Bin Time Bin Time Bin Nos 1 2 3 4 5 6 7 Cycles External Memory Locations Nos Bins per trigger up to 16K 64bit words per channel Reg Set by Nos Gates per Cycle Reg Each bin has a 32bit counter and a 64bit totaliser The bin totaliser is stored in external RAM The maximum number of bins per channel is 16K Page 9 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 1 2 Histogram Coincidence Mode This is the same as histogram mode but where inputs which match the patterns set in the channel coincidence registers will increment the counters Coincidence mode is enabled by setting the EC bit in the CSR then inputs are AND gated with the Coincidence registers and if true increment the scaler for that channel The minimum time of overlap required is 2ns min to ensure coincidence triggering Note If the pattern in the coincidence register is zero then when the scaler inputs all go to zero it does not give a count If a channel input is disabled then it will always read as zero in the pattern in the coincidence mode and the coincidence counter for that channel will always read zero 5 1 3 Memory Layout for Histogram Mode Time Bin Memory The External 1M x 16 bit RAM memory contains the sixteen groups of time bins organised as up to 16K 64
13. 6 APPENDIX A AA ST TE AET TN 27 APPENDIX B EE 28 APREND X Coni idad 29 NM VOIR TK EI SE E 30 Page 4 D Hytec Electronics Ltd MCS8522 UTM 3 0 1 INTRODUCTION The Hytec IP MSC 8522 is a single width Industry Pack that provides 16 scalers channels with the following characteristics 16 independent counting channels 32 bit counter depth Shadow register to allow on the fly reading of scalers Full 32 bits binary count capacity and 64 bit histogram capability 2Mbytes SRAM Gate Bin advance by internal timer or programmable number of external pulses 200MHz Count rates LVDS LVPECL and NIM 100MHz for TTL TTL LVDS and LVPECL inputs Input type must be specified when ordered Input type can be reconfigured in the field via the JTAG port if requirements change NIM input via dedicated terminal block Each scaler has a 16 bit input coincidence pattern register Interrupt on completion of programmed number of cycles triggers counts External hardware trigger software enable or software trigger Trigger output to allow Trigger In Out daisy chain connection for synchronisation Software and external hardware reset of scalers and memory Scaler external inputs via transition board Trigger ignored if cycle has not completed Channel masking Counter Overflow register Number of Cycle Triggers Received register The ability to read the module identity manufacturer model revisions input type and serial number fro
14. DC7 DC6 DCS DC4 DC3 DC2 DCI DCO 6 2 8 Change of Function Register I O address 59 Read Write register D15 D14 D13 D12 D11 D10 D09 DOS D07 DO6 DOS D04 D03 D02 DO DOO Do Do Not Note CH Fl FO set set FO F1 This shows which function is loaded in FPGA 00 Histogram function 01 Preset scaler function Change function This loads the Histogram application into FPGA CH Page 22 D Hytec Electronics Ltd MCS8522 UTM 3 0 6 2 9 Select TTL level I O address 60 Read write register This allows the TTL logic level of the unit to be set D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DO1 DOO PS2 PSI PSO PSO This sets Trigger to accept active high LVTTL when 0 or active Low LVTTL when 1 Trigger Output driven from Trigger IN PS1 This sets External Reset to accept active high LVTTL when 0 or active Low LVTTL when 1 PS2 Sets Scaler Inputs to drive active high LVTTL when 0 or active Low LVTTL when 1 This is only applicable when unit is configured for TTL scaler in puts and has no effect when in LVDS mode 6 2 10 Counter Source I O address 62 Read write register D15 D14 D13 D12 D11 DIO D09 DOS D07 D06 DOS D04 D03 DO2 DO DOO CS 15 CS 14 CS 13 CS 12 CS 1
15. HYTEC ELECTRONICS Ltd 5 CRADOCK ROAD READING BERKS RG2 0JT UK Telephone 44 0 118 9757770 Fax 44 0 118 9757566 E mail sales hytec electronics co uk Copyright 2011 Hytec Electronics Ltd Data and specifications are subject to change without notice MCS8522 MULTI CHANNEL SCALER INDUSTRY PACK USERS MANUAL PCB Issue 1 0 Firmware Versions Histogram Mode LVDS TTL V103 Histogram Mode LVDS TTL V104 Histogram Mode LVDS TTL V105 Preset Scaler Mode LVDS TTL V103 Document Nos MCS8522 UTM G x 3 0 Date 18 12 2014 Author MRN D Hytec Electronics Ltd MCS8522 UTM 3 0 Revision History The following table shows the revision history for this document Date Version Revision 30 05 12 1 0 Initial release FF flag put in CSR Unit does not start when nos cycles triggers is set to zero Unit does not start in Hist mode when Nos Gates per cycle is set to 25 07 12 1 1 zero Enter value required as opposed to not one less Mem address reg in straight scaler mode shows next memory location to be written to 27 07 12 2 0 Dual boot for histogram mode or Preset scaler mode 04 09 12 2 1 1 O configuration section expanded and added to contents page 18 12 14 3 0 In Histogram Mode add External Enable function and amend TTL logic level register to include External Enable bit level CRITICAL APPLICATIONS DISCLAIMER THIS PRODUCT FROM HYTEC ELECTRONICS LTD USES COMPONENTS THAT ARE
16. Histogram mode unit will not start D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO G13 G12 G11 G10 G9 G8 G7 G6 GS G4 G3 G2 Gl G0 5 4 7 Overflow Register I O address 52 Read write register The overflow from each scaler is latched When a bit is set it indicates scaler overflow Writing a 1 to a bit will clear the Overflow bit for that channel Writing a zero changes nothing Reset also clears this register D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO O15 O14 O13 O12 Oll O10 09 O8 07 06 OS 04 03 02 Ol 00 5 4 8 Nos Cycles and or Triggers Received Register IP address 53 Read Only register Number of cycles and or triggers received This register is cleared when the number of cycles register addr 50 is cleared It is also cleared when an internal Reset bit1 CSR is set or an external reset is issued D15 D14 DI3 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO TR15 TR14 TR13 TR12 TR11 TRIO TR9 TR8 TR7 TR6 TRS TR4 TR3 TR2 TRI TRO 5 4 9 Interrupt Vector Register I O address 54 Read write register Defines the interrupt vector D15 D14 D13 D12 D11 D10 D09 DOS D07
17. NAL AND EXTERNAL RESET ANEN 17 5 7 EXTERNAL TIME BIN AIDNANCE EBA oran o non nn carr cnn rra n rra renos 18 5 8 EXTERNAL TRIGGER ENABLE ONLY IN VERSION V104 AND ABONVEI 18 SH MINIMUM DWELE TIME oeaan a a a a A 19 6 PRESET SCALER Soteer eaeoe ie o o eis eeaeee onae o aar ooa eoe teoei sets ians 20 6 1 SETTING VALUE TO LOAD IN TO PRESET SCALER seeseseerereerreeerrrererresrrseereessrnsrereersrnseerereeree 20 6 2 APPLICATION REGISTERS PRESET SCALER iiaii a 20 6 2 1 Preset Counting and Shadow Registers I O Address 321 2I 6 2 2 Control amp Status Register CSR I O Address 28 21 6 2 3 Preset Hit Register 1 0 address 372 21 6 2 4 Count Termination Mask Register IP address 371 22 6 2 5 Interrupt Vector Register I O address 34 22 6 2 6 Interrupt Disable Register I O address 231 22 6 2 7 ARM Channel Input I O address 38 22 6 2 8 Change of Function Register I O address 3901 22 6 2 9 Select TTL level I O address ol 23 Page 3 D Hytec Electronics Ltd MCS8522 UTM 3 0 6 2 10 Counter Source 1 0 address Gil 23 6 3 INTERNAL AND EXTERNAL RESET PRESET SCALER Mopp 23 Tee IPRO Mica di 24 8 I O STANDARDS INPUT CONFIGURATION cccsssccsscsssssscccsssccccessssccccesssscccesssccecesses 25 8 1 LVPECL LOW VOLTAGE POSITIVE EMITTER COUPLED Loo 25 8 2 LVDS LOW VOLTAGE DIFFERENTIAL SIGNAL sessssssssssssersersssssssssretresssssssssrerrrressrereeee 26 8 3 J1 PULL UP OR PULL DOWN FOR TTL LOGIC SIONALS 2
18. Number xxxxdec Logic Type xx00h Standard logic setup with LVDS Logic Type xx01h Standard logic setup with LTTL Note Other logic setups may to be defined later Logic Type x0xxh Histogram Logic Type 01xxh Scaler Note Other setups may to be defined later Page 24 D Hytec Electronics Ltd MCS8522 UTM 3 0 8 I O Standards Input Configuration V Internal DE P Differential Logic 7 N gt UO Pair Pins INN Vinn Vine GND level Vine Vinn Vicm Input common mode voltage Vip Differential input voltage Vinp Vinn Differential Input Voltages Recommended Operating Conditions for User I Os Using Differential Signal Standards IOSTANDARD VID Vicm Attribute Min mV Nom mV Max mV Min V Nom V Max V LVDS 33 100 350 600 0 3 1 25 239 LVPECL 100 800 1000 0 3 1 2 1 5 8 1 LVPECL Low Voltage Positive Emitter Coupled Logic Differential I O standard with a voltage swing between two signal lines of approximately 850 mV The use of a reference voltage VREF or a board termination voltage VTT is not required Important Note The LVPECL standard requires external 2200hm resistor termination which is not implemented on the 8522 module The1000hm resistor termination is implemented on the unit Page 25 D Hytec Electronics Ltd MCS8522 UTM 3 0 8 2 LVDS Low Voltage Differential Signal LVDS is a differential I O standard As with all
19. Page 12 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 4 Application Registers Histogram and Straight Scaler Application Register Table Byte Word Addressing Addressing 16 Bit Application Registers Hex Dec Hex Dec 0 3E 0 62 28 1F 0 31 32 bit Shadow Counting registers chans 1 to 16 40 5E 64 94 20 2F 32 47 Coincidence Registers chans 1 to 16 60 96 30 48 CSR 62 98 31 49 Gate Interval Reg 64 100 32 50 Number of cycles 66 102 33 51 Nos Gates per cycle memory depth 68 104 34 52 Overflow register 6A 106 35 53 Nos cycles and or triggers received 6C 108 36 54 Interrupt Vector register 6E 110 37 55 Interrupt Enable disable 70 102 38 56 Memory pointer LSB 72 104 39 57 Memory pointer MSB 74 106 3A 58 Mask Channel Input 76 108 3B 59 Change of Function Register 78 110 3C 60 Select TTL level when card configured for TTL 7A 112 3D 61 NOT USED 7C 114 3E 62 Counter Source 5 4 1 Counting Registers I O Address 0 31 Counter Shadow Registers 0 to 15 are held in the I O space of the IP scaler card The counter registers may be read at addresses 00 1E even for the least significant words D15 D14 D13 D12 D11 D10 DOI DOS D07 D06 DOS D04 D03 D02 DOI DOO S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 So and 01 1F odd for the most significant words
20. SR 5 1 1 Basic Histogram Mode The counters and memory can be reset to zero using the Reset bit see CSR section Then the memory depth and number of cycles need to be set as required The gate interval can be internally generated by writing to the Gate Interval register Or can advance to the next time bin via the External Bin Advance EBA input The external bin advance occurs on every N th external pulse as set by the value set in the Gate Interval register When a trigger occurs the counters are automatically cleared to zero The counters then count input pulses for an interval generated by the Gate Interval register At the end of the interval all scaler contents are added to the first memory location for that channel and the gate interval restarted The scalers count for the next interval and at the end of that interval the contents are added to the next memory location This is repeated until the preset number of gates as set in the Number of Gates register has been reached A new trigger will start the next cycle wherein the scaler contents are repeatedly added to memory at the end of each gate interval The memory pointer holds the start address for the next 16x64bit data address When the programmed number of cycles as set in the Number of Cycles register have been triggered and the sequence completed the Finished Flag FF in the CSR is set and an interrupt is generated if enabled There are sixteen 64 bit totalisers which record the t
21. ad at addresses 00 1E even for the least significant words MCS8522 UTM 3 0 D15 D14 D13 D12 Dil D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 So and 01 1F odd for the most significant words D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 Important Note When reading the counters with the Scalers enable both the low and high word of the counter are latched in to the shadow register when the Least significant word is read and not when the most significant word read This will ensure the correct 32 bit count word is read 6 2 2 Control amp Status Register CSR I O Address 48 Read write register Control and Status bits D15 D14 D13 D12 D11 DIO D09 D08 D07 D06 DOS D04 D03 D02 DOI D00 IRQ Interrupt Request Ready generated at the end of the programmed number of cycles or when preset value reached in preset Scaler mode Read only R Reset writing a 1 to this bit resets all the counters and memory to zero This bit also indicates when clear memory routine has start
22. ded logic I O chan 5 or positive of LVDS chan 3 I O 106_N3 can be single ended logic I O chan 6 or negitive of LVDS chan 3 I O Some channels have dedicated signal names i e 1035 P18 TRIGOUT Note If unit is accidentally connected to Hytec transition card with DC to DC connected then the pins shown will have 12V supplied These lines are grounded in the 8522 so the fuse on the Hytec transition card will blow and no damage will be caused to the 8522 IP card Page 27 3 Hytec Electronics Ltd APPENDIX B HYTEC TRANSITION CARD CONNECTIONS FOR LVDS 3 3V INPUTS VO Connector 50 way on transition Card 8304 Where this feeds ONE IP sites Pin Trans Pin 8522 Signal Trans Pin 8522 MCS8522 UTM 3 0 4 104 N2 10 1010 N5 P 2 2 2 2 103 P2 12 1012 N6 1022 N11 1024 N12 in 6 7 8 9 30 31 32 33 34 17 1011 P6 1017 P9 1023 P12 1026 N13 1028 N 1030 N15 1032 N 37 38 23 25 1 1025 P13 14 1029 P15 16 lot Used lot Used dot U Not Used Not Used Not Used 44 37 Not Used Not Used 45 39 TRIG EBA IN sed 3 GND GND Not Used Page 28 GND GND 3 Hytec Electronics Ltd MCS8522 UTM 3 0 APPENDIX C HYTEC TRANSITION CARD CONNECTIONS FOR TTL INPUTS VO Connector 50 way on transition Card 8304 Where this feeds ONE IP sites Pin Pin Pin Pin i Jot Used 27 3 103 Pi Jot Used d sed 4 N 12 N
23. ed 1 and finished 0 for both hardware and software memory clears IE Interrupt enable enables IRQ to generate interrupt when set to a 1 ET Enable Hardware TRIGGER IN from Transition board to initiate each acquisition cycle ER Enable Reset Enables external hardware reset to clear scalers and memory ST Software TRIGGER enables the counters CT This clears the trigger and stops the counters FF Finish flag set when a counter s as shown in Preset Hit reg reach its there preset value This flag is cleared when the Preset Hit registers is cleared read only TSx Selects a 00 25MHz 01 50MHz 10 100MHz or 11 200MHz test input to counters 6 2 3 Preset Hit Register I O address 52 Read write register The Preset Hit from each scaler is latched When a bit or bits are set it indicates scaler has reached its preset value Writing a 1 to a bit will clear the Preset Hit bit for that channel Writing a zero changes nothing This register is also cleared by a Reset TS1 TSO FF CT ST ER ET IE R IRQ D15 D14 D13 D12 Dil D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 015 014 013 012 Oll O10 09 OS 07 06 OS 04 03 02 Ol 00 Page 21 D Hytec Electronics Ltd 6 2 4 Count Termination Mask Register IP address 53 Read Write register This registe
24. h the EBA set then the GIT reg holds the number of counts before advancing to the next bin Important entering 0 will give a count of 1 and 1 2 etc this is same as before Example If signal in to Ext Trig is 1MHz lus period and GIT set to 100 then each bin lasts for 100us Beware minimum Gate interval time is approx 10us no IP memory reads as this causes dwell time to increase The number of gates register still sets the max number of gates before stopping data acquisition and generating an interrupt This should be set to Ox3FFF this allows the unit to acquire up to its maximum memory depth Or it can be set to less to stop excessive time wastage if external ET is not de asserted within a certain time as an interrupt will be generate In this mode the software trigger will be ignored and the number of cycles register Page 18 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 9 MINIMUM DWELL TIME The minimum dwell time on the MSC8522 is defined as the time needed to take the data from the 16 counters and form a histogram which is saved in the external RAM memory The current design has a Dwell time of approx 10us This means that if the EBA is 20MHz will need to put in the following calculated value to the EBA registers GIT 10us x 20MHz 200counts min This may be longer if the memory is being read at the same time see following scenario IP Clock 32MHz memory reads every 1200ns Dwell increased to approx IP Clock 32MHz mem
25. inished 0 for both hardware and software memory clears IE Interrupt enable enables IRQ to generate interrupt when set to a 1 ET Enable Hardware TRIGGER IN from Transition board to initiate each acquisition cycle ER Enable Reset Enables external hardware reset to clear scalers and memory ST Software TRIGGER initiates a single acquisition cycle EC Enable coincidence The coincidence patterns are AND gated to increment the appropriate scalers Coincidence register 20 increments scaler 1 if the AND is true FF Finish flag set when the number of cycles triggers reached read only TM Sets the interval timer multiples from 1ms to 100us in Gate Interval Register MD This bit set the mode of the unit MD 0 MODE TYPE 0 Histogram 1 Straight Scaler EXET Enable External Trigger Enable EBA Enable External time Bin Advance EBA TSx Selects a D0 25MHz 01 50MHz 10 100MHz or 11 200MHz test input to counters ETM Enable Totaliser memory 5 4 4 Gate Interval Bin Advance Register I O address 49 Read write register When EBA in the CSR set to 0 specifies the count for the gate interval timer in multiples of 1msec 1 to 65535ms when TM 0 in CSR or in multiples of 100us 100us 6553 5ms when TM 1 in CSR When EBA in CSR set to 1 then the gate interval register sets then number of external pulses from the Trig EBA input to set the gate interval Bin advance
26. input When the gate interval is finished the counter values are loaded in memory The number of logged values is set in the Nos Cycles Triggers register up to 32k per channel of 32bit data When the programmed number of triggers as set in the Number of Triggers register has occurred and the sequence completed the Finished Flag FF in the CSR is set and an interrupt is generated if enabled e Gate Bin advance by internal timer or programmable number external pulses 1 to 65525 e Internal Gate time intervals may be programmed from 100usec to 65secs e Number of cycles register determines number of add to memory cycles upto 32K per channel 32bit counter data 2 3 Preset Scaler Mode In this mode the counters are loaded with a preset count value An arbitrary channel or a combination of channels can then be selected as the condition for the termination of the counting process for all counters The selection of the channel s is done via the Count Termination Mask Register The first selected channel that reaches its preset value will terminate the counting process and sets the FF flag in the CSR The individual counters can be driven from external inputs or from an internal pulse generator selected by the Counter Source register The internal pulse generator can be set to the following frequencies 25MHz 50MHz 100MHz or 200MHz Page 6 D Hytec Electronics Ltd MCS8522 UTM 3 0 3 Product Specifications Size Operating temp N
27. m an onboard ID ROM In the field firmware upgrade capability Page 5 D Hytec Electronics Ltd MCS8522 UTM 3 0 2 Modes of Operation 2 1 Histogramming Mode In this mode a histogram is formed for each channel This is achieved by acquiring and logging the data for each channel over a number of programmable time intervals gates bins for a programmable number of cycles e Gate Bin advance by internal timer or programmable number external pulses 1 to 65525 e Internal Gate intervals may be programmed from 100usec to 65secs e Output pulse on each Gate Bin advance Programmable memory depth number of time intervals or Gate Bins per triggered cycle of gate intervals up to 16k per channel of 64bit data 64 bit totalisers records each channels total counts for each Gate Bin 64 bit totalisers records each channels total count for all Gates Bins in each cycle Dwell time approx 10us Coincidence mode allows counting for coincidence on multiple inputs 2 2 Straight Scaler Mode Straight scaler mode allows fixed or variable length counting time intervals The interval length can be defined by an internal timer or by an external signal which can also be prescaled In this mode a time period or gate interval is set and when the unit is trigged the sixteen 32 bit counters will The gate interval can also be controlled externally by setting the EBA bit in the CSR Here the timing pulses are user defined and received via the trigger
28. means that the counters may not read zero when frequencies are above 60MHz 6 1 Setting Value To Load in to Preset Scaler The counters use the counter overflow to signal when the preset value is reached Therefore the desired number of counts needs to be first inverted and incremented by 1 E g require a count of 0x100 then OxXFFFFFE0O0 is loaded in to the counters 6 2 Application Registers Preset Scaler Application Register Table Byte Word Addressing Addressing 16 Bit Application Registers Hex Dec Hex Dec 0 3E 0 62 28 1F 0 31 Write 32 bit preset scaler value chans 1 to 16 Read 32 bit scaler value chans 1 to 16 40 5E 64 94 20 2F 32 47 Not used 60 96 30 48 CSR 62 98 31 49 Not used 64 100 32 50 Not used 66 102 33 51 Not used 68 104 34 52 Preset Hit Register 6A 106 35 53 Count Termination Mask register 6C 108 36 54 Interrupt Vector register 6E 110 37 55 Interrupt Enable disable 70 102 38 56 Not used 72 104 39 57 Not used 74 106 3A 58 ARM channel enable 76 108 3B 59 Change of Function Register 78 110 3C 60 Select TTL level when card configured for TTL 7A 112 3D 61 Not used 7C 114 3E 62 Counter Source 0 External 1 Internal Page 20 D Hytec Electronics Ltd 6 2 1 Preset Counting and Shadow Registers I O Address 0 31 Counter Registers 0 to 15 are held in the I O space of the IP scaler card The counter registers may be preloaded and re
29. ory reads every 800ns Dwell increased to approx IP Clock 32MHz memory reads every 500ns Dwell increased to approx IP Clock 8MHz memory reads every 1300ns Dwell increased to approx Page 19 D Hytec Electronics Ltd MCS8522 UTM 3 0 6 Preset Scaler The 8522 can be operated as Preset Scaler In this mode the counters are loaded with a preset count value An arbitrary channel or a combination of channels can then be selected as the condition for the termination of the counting process for all counters The selection of the channel s is done via the Count Termination Mask Register The first selected channel that reaches its preset value will terminate the counting process and sets the FF flag in the CSR The preset values are defined by pre loading the counters If no counters are selected by the Count Termination on Preset Mask Register then the counters will all count to there preset value and stop All counters which have reached there preset count value will set the relevant bit in the Preset Hit register and stop The individual counters can be driven from external inputs or from an internal pulse generator selected by the counter source register The internal pulse generator can be set to the following frequencies using bits D14 and D13 of the CSR 25MHz 50MHz 100MHz or 200MHz It should be noted that the stopping of the counters will not be immediate on preset condition being detected but could take uptol5ns This
30. ossosossosossosossosossosossosossosossosossosossosossossssossosesessoseso 8 5 HISTOGRAM AND STRAIGHT SCALER OPERATING MODES eseesesesososososssossosessossesese 9 5 1 HISTOGRAM MODE MD0 0 mNCSRI 9 SL LEE H 5 1 2 Histogram Coincidence Mode 10 5 1 3 Memory Layout for Histogram Mode 10 5 2 STRAIGHT SCALER MODE MDO 1 mNCHR 12 5 2 1 Memory Layout Straight Scaler Mode 12 5 3 AUTOMATED MEMORY CLEAR dto 12 5 4 APPLICATION REGISTERS HISTOGRAM AND STRAIGHT SCALER ccooccocconnonncnncnnnonnconcnnncnncnnninos 13 5 4 1 Counting Registers I O Address 3211 13 5 4 2 Coincidence Registers I O Address 23 47 13 5 4 3 Control amp Status Register CSR I O Address A8 14 5 4 4 Gate Interval Bin Advance Register I O address 29 14 5 4 5 Number of Cycles Triggers Register I O address 201 15 5 4 6 Number of Gates per cycle memory depth Register I O address 311 15 5 4 7 Overflow Register I O address 37 15 5 4 8 Nos Cycles and or Triggers Received Register IP address 3311 15 5 4 9 Interrupt Vector Register I O address 33 15 5 4 10 Interrupt Disable Register I O address 323 16 5 4 11 Memory pointer LSW Register I O address 3091 16 5 4 12 Memory pointer MSW Register 1 0 address 371 16 5 4 13 Mask Channel Input I O address 28 16 5 4 14 Change of Function Register I O address 301 16 5 5 SELECT TTL LEVEL REGISTER I O ADDRESS 60 ONLY IN VERSION V105 AND ABOVE 17 5 5 1 Counter Source 1 0 address Gil 17 5 6 INTER
31. ot Used 31 Il 1011 D 0 Not Used d sed Not Used 38 23 1025 P13 Not Used Not Used Not Used 41 lot Used lot Used Not Used 37 Ext Trig Enable IN Not Used GND Not Used Not Used Not Used GND From version 104 onwards Page 29 MCS8522 UTM 3 0 D Hytec Electronics Ltd APPENDIX D VME64X PIN ASSIGNMENT ON HYTEC 8002 4 IP CARRIER BOARD FOR MCS8522 ROW A SIG SIG SIG SIG P0 A01 D Chan 1 D Chan 2 D Chan 2 D Chan 34 P0 A02 D Chan 4 D Chan 4 D Chan 5 D Chan 5 P0 A03 D Chan 6 D Chan 7 D Chan 7 D Chan 84 P0 A04 D Chan 9 D Chan 9 D Chan 10 D Chan 10 P0 A05 P0 A06 P0 A07 P0 A08 P0 A09 PO A10 PO A11 PO A12 PO A13 PO A14 PO A15 P0 A16 P0 A17 PO A18 PO A19 PO pin assignment P1ROWA SIGNAL P1ROWB SIGNAL P1ROWC SIGNAL P1ROWD SIGNAL P1ROWZ SIGNAL Doo PI BOl N C P1 col Dog P1 D01 N C P1 Z01 D01 P1 B02 N C P1 co2 mm P1 D02 N C P1 Z02 D02 D07 P1 B03 N C P1 C03 P1 D03 N C P1 Z03 P1 B04 BGOIN P1 C04 P1 D04 N C P1 Z04 P P P B05 B06 B07 BGOOUT P1 C05 P1 D05 NIC P1 Z05 BGIIN P1 C06 P1 D06 N C P1 Z06 BGIOUT P1 C07 P1 D07 N C P1 Z07 N C P BG3IN BG30UT LWORD N C AM5 GND A23 N C A22 IACKIN A07 ou lazi iaz ul gt E o A Dal har woo A NIB WLM lo nol Raed ta iol ood Ke N Fa o olojuljololo oju uolw 2 AMI A22
32. otal count for each channel A Trigger can be Hardware generated if ET set in the CSR This diagram shows the memory lay out for one channel where the scaler registers are set as below Gate Interval 16 Nos Cycles Triggers 10 Number of Gates 7 This is memory layout for a single channel Number of Gate Open Time set by Gate Interval Reg Cycle Trig Cyc Trigs 4st46ms 2 16ms 3 16ms Ap 16ms 5 16ms gi 16ms 7 16ms T lee Hard Soft 64 bits gate open gate open gate open gate open gate open gate open gate open FPGA 10 Trig NC NC NC NC NC NC NC Cyc 10 Total Total Total Total Total Total Total 9 Trig NC NC NC NC NC NC NC Cyc 9 Total Total Total Total Total Total Total 8 Trig NC NC NC NC NC NC NC Cyc 8 Total Total Total Total Total Total Total 7 Trig NC NC NC NC NC NC NC Cyc 7 Total Total Total Total Total Total Total 6 Trig NC NC NC NC NC NC NC Cyc 6 Total Total Total Total Total Total Total 5 Trig NC NC NC NC NC NC NC Cyc 5 Total Total Total Total Total Total Total 4 Trig NC NC NC NC NC NC NC Cyc 4 Total Total Total Total Total Total Total 3 Trig NC NC NC NC NC NC NC Cyc 3 Total Total Total Total Total Total Total 2 Trig NC 23 NC 2 NC 4 NC 7 NC 5 NC 1 NC 0 424 Cyc 2 Total 75 Total 55 Total 46 Total 46 Total 25 Total 8
33. otaliser values are read as four 16 bit words from the IP ram memory This memory is accessed when the ETM bit in the CSR is set to 1 16 x 64 bits FPGA RAM memory Memory allocation IP Card Address CSR 15 1 Channel 16 Totaliser 64bits Base 60 Channel 15 Totaliser 64bits Base 56 Channel 14 Totaliser 64bits Base 52 Channel 13 Totaliser 64bits Base 48 Channel 12 Totaliser 64bits Base 44 Channel 11 Totaliser 64bits Base 40 Channel 10 Totaliser 64bits Base 36 Channel 9 Totaliser 64bits Base 32 Channel 8 Totaliser 64bits Base 28 Channel 7 Totaliser 64bits Base 24 Channel 6 Totaliser 64bits Base 20 Channel 5 Totaliser 64bits Base 16 Channel 4 Totaliser 64bits Base 12 Channel 3 Totaliser 64bits Base 8 Channel 2 Totaliser 64bits Base 4 Channel 1 Totaliser 64bits Most significant 16 bits of 64 bit word Third 16 bit word Base 0 Second 16 bit word Least significant 16 bits of 64 bit word Page 11 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 2 Straight Scaler Mode MDO 1 in CSR In this mode the time the gate is open is set using the gate Interval register The period of the gate interval is controlled by the gate interval register setting the number of internally generated 100us or Ims pulses The gate interval can also be controlled externally by setting the EBA bit in the CSR Here the timing pulses are user defined and received via
34. r IN and External Reset can be set via the TTL level register to accept active low LVTTL External pull up required or active high LVTTL External pull down required Trigger Output driven from Trigger IN Standard Configuration of Logic Level Signals for LTTL Inputs Logic Type 0001h Scaler Input levels LTTL Trigger Reset levels LTTL Trigger Output levels LTTL The Scaler Inputs Trigger IN and External Reset can be set via the TTL level register to accept active low LVTTL Jumper J1 set in pull up position or External pull up required Or active high LVTTL Jumper J1 set in pull down position or External pull down required Trigger Output driven from Trigger IN User Set TTL Logic Level The user can set TTL logic levels as required by removing J1 and providing external pull up down resisters The TTL level register must be set accordingly The logic lines for the scaler inputs external triggers external trigger enable and reset logic signals can be e LTTL compatible with positive negative edge clocking e LVDS 3 3V e A mixture of both as required Note The required configuration standard needed or if different logic signal levels from standard configuration are required must be specified when ordering The unit can be reconfigured in the field via the JTAG port if requirements change Page 8 D Hytec Electronics Ltd MCS8522 UTM 3 0 5 Histogram and Straight Scaler Operating Modes 5 1 Histogram Mode MDO 0 in C
35. r selects which channel s will terminate the counting process when the preset value is reached the first selected counter to reach its preset value will terminate the counting process for all channels and generate an interrupt Enable Interrupt on channel when it reaches its preset value MCS8522 UTM 3 0 D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TRS5 TR4 TR3 TR2 TRI TRO 6 2 5 Interrupt Vector Register I O address 54 Read write register Defines the interrupt vector D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 VI VO 6 2 6 Interrupt Disable Register I O address 55 Read write register Writing a 1 to bit zero causes the Interrupt Enable bit IE in the CSR to be cleared D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DOI DOO 6 2 7 ARM Channel Input I O address 58 Write register Write a 1 to ARM a channel D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DO1 DOO DC15 DC14 DC13 DC12 DC11 DC10 DC9 DC8
36. umber of channels Max count Data format Count rate TTL Count rate LVDS Coincidence Scaler Input levels Trigger Reset levels Trigger Delay Trigger Output levels Clock accuracy Power Single width Industry Pack 1 8ins x 3 9 ins 0 to 45 deg C ambient 16 32 bits with IRQ at end of programmed number of cycles Binary 0 to 100Mpps 0 to 200Mpps 2ns min overlap for detection TTL compatible with positive or negative edge clocking or LVDS 3 3V External Trigger Input TTL compatible settable active low or active high options the maximum Trigger delay due to internal logic is 25ns Trigger Output for synchronisation of modules TTL compatible settable active low or active high options 50ppm 0 005 5V 250mA typical Page 7 D Hytec Electronics Ltd MCS8522 UTM 3 0 4 Logic Signal levels The configuration of the logic types are indicated in the 8522 ID ROM at Base 98 Logic Type 0000h Standard logic setup with LVDS Logic Type 0001h Standard logic setup with LTTL Note Other logic types may be possible consult Hytec Standard Configuration of Logic Level Signals for LVDS Inputs Logic Type 0000h Scaler Input levels LVDS 3 3V Trigger Reset levels LTTL Trigger Output levels LTTL The jumper J1 Pull up pull down voltage select should not have a jumper fitted Pull up and Pull down resistors need to be implemented externally as required for the Trigger Reset and Tigger Out Trigge
37. ut TRIG EBA IN The external bin advance occurs on every N th external pulse as set by the value in the Gate Interval register When the EBA bit in CSR is set to 1 then the gate interval register sets then number of external pulses from the Trig EBA input to set the gate interval Bin advance The Trig EBA input can be up to 20MHz but with the restriction that the combination of the rate and the number of divides as set by the register is no shorter than the minimum allowed dwell time of the device see relevant section on Dwell times The EBA signal comes in on the same pin as the External Trigger so if external trigger bit is set in the CSR then the unit will trigger on the first EBA signal This first pulse will be counted as part of the EBA count interval The unit can alternatively be triggered via software 5 8 External Trigger enable Only in version V104 and above Here an external line drives the external trigger enable need to set ExET bit 11 in CSR If ET bit 3 is set it has no effect and if the nExtET line is de asserted then an in put on the external trigger will not be seen To enable the unit using external trigger take the nExtET line pin 37 8522 pin 44 transition card Low When this line is taken High the unit is disabled and an interrupt is generated on INTRO if enabled When a trigger has occurred in this mode need to clear the ExET bit 11 in CSR to reset it before another trigger can be seen In this mode wit

User Manual - Hytec Electronics Ltd

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