Home

Radstone PIO-2 Manual

Contents

1. E 1 4 DO sls M E 1 4 Counter arrsa SU FREE C REP EP UTEM EXPE PELA E PPM 1 6 Input Change GL State svn evt pere rip erp SEHE 1 6 But m p c _ _ 1 6 PIO 2 Numbering ses ev Aeon eap MY PR RE 1 7 Chapter 2 Specifications einen eterni an tuu RR SR RRRRAR 2 1 General cedi diva ater odia unen n rice n etd Pr e i i td eere 2 1 Spsel I alios no cn n Geen tee 2 1 Saky n pr AR DRE Le to i D ER OR end p n de bt 2 2 Mechanical Speci Gica REO en pepe eii br a eer PER RRA 2 3 A di ERE EC REP dr Deb 2 3 Desi IS eorpore edita iceman eos arene ee 2 3 Bbnvironmental See aola conte era Ts vi HE ERE e bI MO RU 2 5 EA nda abscess E ME M E MU 2 6 Cliapter Configuration aeree iter itta uri ox 3 1 Betting the 2 Base Address ios suse Ir peter Ro Ri EFE pi Nur vei i a dbi ibi 3 2 Debounce Clock SES CH OM CIE i cau
2. A 1 input SBeclUcatlofis od p buc x HERI EH A 2 ME adsis acta ME CE 2 GNIS ac PE PE ENEE TTEA E EEE EEEN TEE A 3 Output Specifications ie i qub bed t desu REEE ANE P eU VR E RENNE EE A 5 e A 5 mt A 6 Appendix B Example Code B 1 Appendix Typical Load Connection C 1 C KEU d le UH be ERE RARE EIN BIA CARP eae RR DEO at C 1 cingi C 1 c C 2 Page ii Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Introduction Chapter 1 Introduction Scope of this Manual This manual describes Radstone s PIO 2 Parallel I O Interface board The PIO 2 in common with other Radstone boards is available in five environmental build standards Conventions Used in This Manual This manual adopts the following conventions As with the 680x0 bits are numbered from 0 to n where 0 is the LSB and n is the MSB Signal names follow the ANSI VITA 1 1994 Specification Signal names ending in deonte active
3. E20 21 ina U93 U 2 LJ LJ r3 8 A o N o wo U1 c c 97 021 L3 Co LJ LJ Co LJ LJ LJ 034 045 056 065 074 ojojo Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Page 3 1 Rev D Radstone PIO 2 Manual Configuration Setting the PIO 2 Base Address To set the PIO 2 base address using on board links link E11 must be fitted If link E11 is fitted links to E10 and E12 to E19 set the VME address bits A23 to 8 as follows Fitting a link makes the corresponding address bit a 0 leaving the link out makes the corresponding address bit a 1 The granularity sets the board base address to 256 byte boundary e OL Je d Qu
4. Hours 330 340 157 661 68 211 87 359 28 219 35 437 Level 4 45555 Fail Rate FPMH 1 4894 3 56328 7 45288 6 447372 MTBF Hours 671 411 280 640 134 176 155 102 45 39 15198 25 541 14 81342 67 506 55 55 70 70 164 1383 6 092 48 13314 20 776 55 30 11 886 16 0057 24 77843 32 80141 2 717338 84 133 62 478 40 358 30 486 386 007 6 909372 8 86858 12 08786 15 91902 1 38257 144 731 112 758 82 728 62 818 723 291 45 28 90645 34 594 11 75686 85 057 55 46 43864 Page 2 6 Rev D 21 534 22 55308 44 340 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Configuration Chapter 3 Configuration This chapter provides the information required to configure the PIO 2 The board is delivered with push on jumper links but for rugged or Military applications you are recommended to connect the posts using wire wraps Note To maintain the environmental integrity of cards that have been conformally coated during manufacture user made wire wrap links should be given a conformal coating Figure 3 1 Link Locations e e c2 024 T uae 095 014 135 066 047 025 02 026 036 048 088 097 075 E3 tee Ure U90 027 U37 149 ES ETO a E11 077 091 199 U5 029 U39 U50 EL EJ u78 092
5. 3 4 qu 3 5 3 6 Chapter 4 Registers iiec niece 4 1 dM EE di 4 1 eod ut 4 3 pie d rod 2 6 4 4 Mask Rec Siers VIO Tennad rerna 4 5 BIT V ME Interrupt Control Register ion oso mero pnr rtr 4 6 VME Interrupt Vector Register edel n apr vet Ree 4 7 Programmable Interyal Timer IP PERS 4 8 Counter luba ce Rm 4 8 Control Word Regislets UE EO 4 9 PIT Programming Overview adda nep ir o e i eH 4 10 PIT Read back Operatigns ino nasi meri A NS E 4 10 Counter Latch Command A 4 11 Read back Command esanian Pep PER mained EP DUM 4 12 luu M 4 14 0 Interrupt on Terminal Count o Dor P Pr rper e err EE 4 14 Mods 1 Hardware Retriggerable One Shot conati bl rer dui 4 14 Mods
6. ca E ea ca Page 3 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Configuration If E11 is not fitted the address decoding is done by U94 which compares addresses against a code set via pins 17 the LSB to 20 the MSB of the J4 connector as shown in the table below This is only intended to be used on level 5 boards where Mean Time To Repair MTTR requirements rule out configuration via numerous links Table 3 1 Code Set via J4 J4 Pin Code Address gt gt epe gt _ e o o S If none of the addresses listed above meet your requirement please consult Radstone Technology for alternatives Lie O 091 099 BRB o U92 iiim J4 Cm 093 gu i mm mm m 058 p59 0 Qux PO Pa
7. Due to the way in which the VMEbus organises its addresses even addresses end up on the most significant data bits D8 to D15 and odd addresses on the least significant data bits DO to D7 PIO 2 always routes data bit 0 to channel 8 or channel 24 data bit 1 to channel 9 or channel 25 and so on up to data bit 15 to channel 7 or channel 23 This leads to a difference between byte and word accesses to PIO 2 in that the byte order for word accesses is the reverse of what you might expect Examples 1 To operate the relay on channel 3 using a byte access write 0x08 to BASEADD 0x0 2 To operate the relay on channel 14 using a byte access write 0x40 to BASEADD 0 1 Note all the registers on PIO 2 are implemented in a Logic Cell Array LCA there is an initialization period following power on where the board does not respond to a VMEbus access This period lasts for approximately 100ms after the removal of SYSRESET on the VMEbus Page 4 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Data Registers 0 to 3 Offsets 0 to 3 Register 7 0 Offset 2 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 2 3 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 3 There are four 8 bit read write registers that give access to the 32 I O channels by reading from or writing to bits in the corresponding register as follows Bit Write Bit Read
8. These are a group of five 8 bit read only registers The first four registers store the interrupt status of the 32 channels while the fifth stores the interrupt status of the six timer counters If a change is detected in an I O cell and the cell is configured to generate an interrupt on that change then the interrupt is recorded in the appropriate interrupt status register At any time any or all of the channels can detect a change but only one interrupt may be generated on the VMEbus Once an interrupt has been serviced the status register is read which resets it ready for the next change Since all the changes are recorded in the register this method ensures that no interrupts are missed If a change is detected after an interrupt service routine has started then it is stored until after the status register has been reset at which time the bit is set in the status register and a new VMEbus interrupt may be generated Interrupt generation on a change of state of a cell is controlled by the Interrupt Mask Registers described overleaf Page 4 4 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Interrupt Mask Registers 0 to 7 Offsets 0x10 to 0x17 Register 7 0 Offset 0 0x10 1 CH7 CH7 CH6 CH6 5 5 CH4 CH4 0x11 5 0x15 There are eight 8 bit write only registers that control the generation of interrupts from the input channels
9. mask code shows the test that failed and the fail_code shows the fail point within the test module The remainder of the fail data is fail point specific The following table shows the mask code values for the test modules Mask_Code Test Module Internal loopback test External loopback test PIT counter test Interrupt test ID register test Page 5 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Reset Routine BIT Configuration and Fail Data This routine is common to all tests so the following fail codes apply to all Mask_Code values Fail_Code Meaning Write to channels 0 to 7 Write to channels 8 to 15 Write to channels 16 to 23 Write to channels 24 to 31 Initialize interrupt masks Initialize PIT 0 counters 0 1 and 2 Initialize PIT 1 counters 3 4 and 5 Clear interrupt status for channels 0 to 7 Clear interrupt status for channels 8 to 15 Clear interrupt status for channels 24 to 31 Clear interrupt status for counters 0 to 5 Check channels 0 to 7 initialized Check channels 8 to 15 initialized Check channels 16 to 23 initialized Check channels 24 to 31 initialized Page 5 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data Internal Loopback Test Mask_Code 0001 The intern
10. 1 00 Load Curent 0 00 gt 2 R 55 15 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature C Figure A 8 Typical Current Trip Levels 5 4 g 3 E t 5 5 55 C 8 No 55 C 25 25 1 105 105 C 0 0 01 01 1 10 100 1000 Time seconds Page A 7 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Example C Code Subroutines Appendix B Example C Code Subroutines These example code sub routines make use of a structure called pio2emdblk which declares the various registers that make up the PIO 2 memory map This structure assumes that accesses to the PIO 2 are made as bytes which is the preferred method typedef unsigned long Ulong typedef unsigned char Uchar typedef unsigned short Ushort struct pio2cmdblk Uchar 0 7 Uchar ch8 15 Uchar chl6 23 Uchar ch24 31 unsigned 32 Uchar intstatO0 7 Uchar intstat8 15 Uchar intstatl6 23 Uchar intstat24 31 Uchar cntintstat unsigned 24 Uchar intmask0 3 intmask4 7
11. 4 rtisan tisan Technology Group is your source for quality new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED aed Contact us 888 88 SOURCE sales artisantg com www artisantg com Radstone PIO 2 Manual RADSTONE Publication 681 2 TECHNOLOGY Rev D March 2002 Why settle for less Radstone Technology PLC 2002 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Copyright Notice Radstone Technology PLC 2002 All rights reserved This publication is issued to provide outline information only which unless agreed by the Company in writing may not be used applied or reproduced for any purpose or
12. Load P2 Row C The zener rated at 33V is included to protect the relay from high back EMF generated by inductive loads Note The zener diode is only fitted on level 5 boards Figure 1 4 Circuit for Monitored Output Cell Vcc Channel Out Plastic PVDZ172 Hermetic CD20CD Zener 1N4970 33V Vcc Resistor 16kQ for 28V for 12V 2 2kQ for 5V Channel In Opto isolator Plastic HCPL2731 Diode 1N4148 P2 Row A 5V 12V0r28V Load P2 Row C Hermetic 6N140A This type of cell is formed by fitting the components for both Input and Output cells The input section of the monitored output circuit works in the opposite way to the input only circuit In the quiescent state a small current 1 6 mA large enough to operate the opto coupler but not enough to operate most loads is drawn by the opto coupler Consideration should be given to this when operating sensitive loads such as some solid state relays The operation of the opto relay short circuits the output terminals the load is energised and the opto coupler is turned off This means that the data read in from the opto coupler is opposite to that returned by the input only circuit Note Page 1 5 Rev D The zener diode is only fitted on level 5 boards Artisan Technology Group Quality Instrument
13. low signals all others are active high The prefix Ox indicates a hexadecimal value following the C programming language convention Related Documents ANSI VITA 1 1994 VMEbus Specification IEEE Std 1101 2 1992 Standard for Mechanical Core Specifications for Conduction Cooled Eurocards Radstone BIT V3 User Manual publication number HH681BITE3 Radstone Glossary publication number 5116 BIT on Radstone PPCx User Guide publication number 5107 Features e Fully ANSI VITA 1 1994 VMEbus Specification compatible e 32 digital I O bits for monitoring and control applications e A variety of population options Opto isolation e Input filtering and high voltage spike protection e Six programmable 16 bit counter timers e Change of state monitoring for all inputs All T O through the P2 connector VMEbus slave e BIT facilities Page 1 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Introduction Build Styles The PIO 2 is available in Radstone s five electrically compatible build levels These have two basic mechanical configurations e convection cooled build levels 1 to 3 in accordance with ANSI VITA 1 1994 specification designed to be used in standard industrial VME chassis e Conduction cooled build levels 4 and 5 in accordance with IEEE Std 1101 2 1992 for use in Radstone or third party ATR style en
14. 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Device Specifications Appendix A 1 0 Device Specifications This appendix provides input output electrical specifications for the solid state relays and opto isolators used on 2 Build Level Solid State Opto coupler Relay Used Used PVDZ172 HCPL 2731 PVDZ172 HCPL 2731 CD20CD 6N140A CD20CD 6N140A CD20CDY 6N140A 883B DESC 8302401EC Note HCPL2731 and 6N140A are manufactured by Hewlett Packard The CD20CD range is manufactured by Teledyne Solid State Page A 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Device Specifications Input Specifications 2731 40 C to 85 C Ambient Temperature Parameter Minimum Maximum 32 see Note 1 V DC 14 for 28V version 5 7 for 12V version 3 6 for 5V version 15 for 28V version see note 2 6 8 for 12V version 1 2 for 5V version V us Notes Surge above 32V can be tolerated in line with the protective zener diode ratings 2 This assumes 10 load power supply see Figure A 2 Normally would only represent cabling resistance Figure A 1 Zener Rating 100k 50k 20k 10k 5k 2k 1 500 200 100 100ns 1us 1018 100us 1115 10ms 2 Rev D Artisan Technology Group Quality
15. Affects associated output channel Gives status of associated input channel 0 1 0 1 Deactivates relay Activates relay for Indicates that Indicates that for associated associated channel associated input associated input channel channel is inactive channel is active i e no current is i e current is flowing through flowing through the input opto coupler input opto coupler associated with that associated with that channel channel If a channel or group of channels is input only then writing to the corresponding bits has no effect Similarly if a channel or group of channels is output only then reading the corresponding bits gives an invalid result Note Inthe case of a combined I O cell or where loopback testing mode has been invoked the state of the input bit is the inverse of the output bit i e writing a 1 results in a 0 being read and vice versa This is because an activated relay provides a very low impedance path between the P2 connector pins which prevents any current from flowing through the input opto coupler Page 4 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Interrupt Status Registers Offsets 8 to 0xC Register 7 0 Offset Status 0 8 Status 1 9 Status 2 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 0 Status 3 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 0 Counters CNTRS CNTR4 CNTR3 CNTR2 CNTRI CNTRO OxC
16. 17 is an input and used to sense when port 2 is connected to port 3 Remote supply P2 2 motor 0 SSR Motorsed or waveguide switch with position indication switches Channel 175 Y A Opto Channel 1 SSR Remote GND assumes a grounded remote supply Notes 1 Separate return wires have been used for the relays and opto couplers If the relay current is no greater than a few 10s of mA the return wires could be commoned 2 The configuration shown is for a low side switch A high side switch could be implemented just as easily 3 Ifthe motor solenoid requires more than 1A drive current it is possible to connect outputs in parallel to provide the extra capability Typically if two relays are paralleled both would be turned on simultaneously to provide the peak initial current for the motor solenoid then one would be turned off several milliseconds later leaving the other to provide the hold current Page C 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 rtisan tisan Technology Group is your source for quality new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full
17. 2 Manual Device Specifications Output Specifications PVDZ172 40 C to 85 C Ambient Temperature Parameter Minimum Typical Maximum Units A DC see note 1 uA VDC V DC see note 2 ms see Fig A 4 ms see Fig A 4 Notes 1 There is no in built current limiting feature in the PVDZ172 2 This is limited by the protective zener diode The relay itself withstand 60 V DC Figure A 4 Output Turn on Turn off Figure A 5 Thermal Derating Curve 1 2 1 1 1 0 0 8 i 90 i 10 06 1 1 1 0 4 tor 0 2 ton 4 20 40 60 80 100 Ambient Temperature C Max Amps Page A 5 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Device Specifications CD20CD 55 C to 105 C Ambient Temperature Parameter Minimum Typical Maximum Units A DC see note uA VDC V DC see note ms E Fig A 6 ms see Fig A 6 Note This is limited by the protective zener diode The relay can withstand 60 V DC continuous Figure A 6 Output Turn on Turn off Timing Vcontrol Voutput Page A 6 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Device Specifications Figure A 7 Thermal Derating Curve 250 7 2 200 2 2 a 2 22 Amperes
18. 2 before setting it LED off Enable Loopback 0 Normal operation 1 Loopback mode Setting this bit disables the outputs and inputs and enables an internal loopback path between them outputs are off relays open and the inputs are ignored This feature is intended for use during BIT testing of the card by the host CPU Note In loopback mode all output channels including those that are not populated on a particular build version are looped back to their corresponding inputs A 32 channel input only card can therefore still use this feature In loopback mode the inputs are inverted A 1 written to a channel is read back as 0 and a 0 written to a channel is read back as 1 after waiting for the input debounce circuitry to pass the change through Page 4 6 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers VME Interrupt Vector Register Offset 0x19 7 4 3 0 Interrupt Vector Interrupt Source This is a 4 bit read write register that contains the most significant four bits of the interrupt vector that is returned during the VMEbus interrupt acknowledge cycles This is user programmable to a value that is compatible with the host processor requirements After a reset bits 4 to 7 are clear bits 0 to 3 are don t care During IACK cycles or reads of this register the least significant four bit
19. Rowb P2 Row b D D03 GND SYSCLK GND DS1 050 WRITE GND DTACK GND AS GND IACKIN IACKOUT AM A A A Al 12V 5V Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ACFAIL BGOIN BGIOUT j BG2IN BG20UT j BG3IN BG3OUT j BRO BRI BR2 BR3 AMO AMI AM2 AM3 GND SERCLK SERDAT IRQ7 IRQ4 IRQ3 T5V Page 3 6 Rev D GND 00 BBSY D08 5V D01 BCLR D09 GND 02 D10 Reserved D11 GND SYSFAIL BERR SYSRESET LWORD AM5 A23 22 A21 A20 19 18 17 16 15 14 13 12 G D D D 4 07 06 IRQ6 A05 5 04 ND D24 DS 26 py D28 All 03 10 D29 A02 IRQ2 A09 D30 A01 IRQI A08 D31 GND 5VSTDBY 12V 5V 5V Radstone PIO 2 Manual Configuration Table 3 4 PIO 2 Interface P2 Connector This table details the PIO 2 function allocated to each pin RowA RowC Page 3 7 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Chapter 4 Registers Register Map 2 is driven via the set of registers shown below These are mapped onto the VMEbus at the board base address BASEADD as set up by either on board links or the P4 connector The register map is shadowed 4 times in the first 256 byt
20. Two bits are allocated per channel where the LSB is bit 0 and the MSB is bit 1 Using the two bits allocated per channel each channel can be independently programmed as to whether it generates an interrupt on an input change and if so whether this occurs on a positive or negative edge or both as follows Bit0 Action 0 0 0 1 0 1 1 1 Where high current flow through the input opto coupler low no current flow through the input opto coupler Page 4 5 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers BIT VME Interrupt Control Register Offset 0x18 7 6 5 3 2 1 0 This 8 bit write only register controls the level at which a VME interrupt can be generated in response to an input channel or timer change Bits After a reset bits 4 to 7 are clear and bits 0 to 3 are don t care Mnemonic ILO to IL2 BIT LED Function Used to select which VME interrupt level is used when the PIO 2 generates interrupts as follows 0 Disable VME interrupt generation 1 1 2 IRQ2 3 IRQ3 4 IRQ4 5 IRQ5 6 IRQ6 7 IRQ7 Do not write to these bits Turns the front panel LED on and off as follows 0 LED 1 LED off This bit has no effect on other areas of the PIO 2 circuitry It is cleared LED on during power up or system reset A host CPU should BIT test the PIO
21. at the thermal interface Storage 50 to 100 Shock 10 C minute over range Decompression 0 to 70 000 off from 1000 to 2000 Hz Sine 5g from 5 to 2000 Hz Page 2 5 Rev D 5 salt 48 hours vibration small space envelope and restricted cooling supplies Conformally coated as standard Optional ESS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Specifications Reliability Using MIL HBK 217F notice 1 as a data base and the parts count method the following estimates have been made of the MTBF for the PIO 2 Configured as Input Board Environment Temp C Level 2 21111 Fail Rate MTBF Fail Rate MTBF FPMH Hours FPMH Hours 30 3 807148 262 664 1 700408 588 094 Level 4 41111 Environment 40 45 40 45 55 55 70 70 55 30 6 79689 11 41862 8 27089 12 72184 12 58174 13 46782 23 91722 26 63558 16 35648 3 772207 147 126 87 576 120 906 78 605 79 480 74 251 4 98312 8 88552 7 36302 13 80574 12 0295 20 61802 200 677 112 543 135 814 72 434 83 129 48 501 42 522 24 06652 41 551 37 544 61 138 265 092 44 13698 21 26868 1 541514 201097 47 017 648 713 45 12 28732 81 385 11 55612 86 534 55 Configured as Output Board Temp 30 40 45 40 19 414 51 509 Level 2 25555 Fail Rate 3 027184 6 34272 14 6604 11 44704
22. intmask8 11 Uchar intmask12_ 15 Uchar intmaskl6 19 Uchar intmask20 23 Uchar intmask24 27 Uchar intmask28 31 Uchar ctrlreg Uchar intvec unsigned 32 unsigned 16 Uchar counter0 unsigned 8 Uchar counterl unsigned 8 Uchar counter2 unsigned 8 Uchar cntctrlO 2 unsigned 8 Uchar counter3 unsigned 8 Uchar counter4 unsigned 8 Uchar counter5 unsigned 8 Uchar cntctrl3 5 unsigned 8 Uchar IDreg unsigned 32 unsigned 32 unsigned 32 unsigned 24 cmdblk Page B 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Example C Code Subroutines The following example is a reset routine a common requirement when writing code for I O cards This routine clears all the outputs disables and clears out all interrupts and programs the six counter timers into an inactive mode Clear out all output registers interrupts clear control register i e void reset pio2 disable all input channel disable VM E interrupts turn on front panel LED and disable loopback mode board s VME interrupt vector for completeness cm 0 cm cm cm cm dblk gt ctrlreg dblk chO 7 dblk ch8 15 0 dblk ch16 23 0 dblk gt ch24 31 0 0 and clear dblk in dblk in dblk gt in dblk in dblk in dblk in dblk in dblk in dblk c
23. reading of the ISRs are stored in temporary registers and then loaded into the ISRs after they have been read to generate further interrupts This ensures that no input state transition goes unnoticed Input filtering prevents spurious detections caused by noise or contact bounce The detection of a change of state in a particular group of 8 bits causes a local interrupt request and the generation of a VMEbus interrupt The lower 4 bits of the Status ID byte identify the group in which the change was detected The VMEbus host processor may then read the ISRs to determine which bit or bits have changed Built In Test The PIO 2 is tested on power up over the VMEbus by a host CPU card Radstone provides this test package as part of Built In Test BIT to allow a complete configured BIT system to be constructed The BIT firmware is located on the VMEbus master processor card and is used to test the system configuration with the PIO 2 card s installed Page 1 6 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Introduction PIO 2 Numbering System The PIO 2 is numbered as follows Channels 8 to 15 Channels 0 to 7 Channels 16 to 23 Level 1 to 5 N Channels 24 to 31 PIO2 6BA XXXXX 5V 12V 28V Other Not fitted Input Output Input Output For example PIO2 6BA 33560 Level 3 board Channels 0 to 7 28V inputs Channels 8 to 11 outputs Ch
24. service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED aed Contact us 888 88 SOURCE sales artisantg com www artisantg com
25. word usually means 16 bits The term Control Word is part of the manufacturer s terminology for the PIT 7 6 5 4 3 2 1 0 Bits Mnemonic Function and SCO Select which of the three Counters is to be programmed as follows Counter Counter 0 or 3 Counter or 4 Counter 2 or 5 Read back command RWI and Select the initial count format which can be one or two byte as follows Format Counter Latch command Read write least significant byte only Read write most significant byte only Read write least significant byte then most significant byte M2 and Selects the Mode in which the Counter is to operate as follows Controls whether the initial count is in binary or BCD form as follows 0 Binary Counter 16 bits BCD Counter 4 decades Page 4 9 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers PIT Programming Overview Each PIT contains several internal 8 bit registers that allow it to be programmed to operate in various ways Each Counter is programmed by writing a Control Word and then an initial count The Counter counts down from this initial count to zero The action taken when the Counter reaches zero depends on the Mode and the interrupt generation capabilities set up Software for setting up a Counter in the PIT with an initial count value must obey the following restrictions e Fo
26. 2 E23 E25 and E27 as they have no effect on the operation of the PIO 2 but provide the host software with a means of identifying the PIO 2 s configuration how many inputs and outputs are fitted voltage ranges etc For example if there were three PIO 2s in a rack two with 32 output only channels and one with 32 input only channels then by setting up different ID values on the output and input boards the host software could differentiate between the output and input boards by reading this register on each board The host could then run the appropriate code for each board The mapping of values to configuration is user dependent and can be read by the host in the ID register at VME address BASEADD 0x30 where a 0 bit means that the corresponding link is fitted and a 1 means that the corresponding link is not fitted Bits 7 and 6 can be used to read back the state of links E2 and E1 respectively Links E2 and E1 select the clock that is used to debounce input signals from the opto couplers as shown in the following table E2 El Debounce Clock Rate Response Timet worst case 4 76 Hz 76 Hz 1220 Hz 19 53 kHz The measured total time from the opto coupler current flow to an interrupt generated on the VMEbus if enabled Page 4 18 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data Chapter 5 BIT Co
27. 32 0 8 Page 2 4 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Specifications Environmental Specification Convection cooled Boards Build Low Pressure Style Feet Comments Shock Humidity Salt Fog Vibration Temperature C Commercial grade cooled by forced air for use in benign environments and software development applications Optional conformal coating Up to 95 RH 20g peak sawtooth 1178 duration Random 0 002g2 Hz from 10 to 2000 Hz Sine 2g from 10 to 500 Hz Operating 0 to 55 with airflow of 300 feet minute Storage 40 to 85 Shock 10 C minute over range Operating 15 000 Storage 50 000 As Standard but conformally coated and temperature characterised 20g peak sawtooth 1178 duration Up to 95 RH with varying temperature 10 cycles 240 hours Random 0 002g2 Hz from 10 to 2000 Hz Sine 2g from 10 to 500 Hz Operating 15 000 Storage 50 000 Operating 20 to 65 with airflow of 300 feet minute Storage 40 to 85 Shock 10 C minute over range Operating 40 to 75 with airflow of 600 feet minute Storage 50 to Shock Decompression 10 C minute over range 0 to 50 000 Up to 95 RH with varying temperature 10 cycles 240 hours 5 salt 48 hours Wide temperature rugged cooled by forced air Conformally coated for additi
28. 88 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data External Loopback Test Mask_Code 0002 This test is only run in factory test mode tertiary BIT as it requires an additional Known To Be Good KTBG PIO 2 an external loopback cable and external power input to drive the loopback If factory test mode is not selected this routine exits with a pass status The external loopback test includes an access test of the card under test a reset of both PIO 2 cards a check of the configuration data and an external loopback checking the speed of loopback Access is tested by reading from and writing to the BIT VME Interrupt Register Configuration Data Word 5 is checked identifying channels and modes to be tested Reset of the PIO 2 under test is done using the standard reset routine A similar routine resets the KTBG PIO 2 The inputs of the card under test are tested by writing 18 test patterns to the KTBG PIO 2 and checking the data received on the card under test Outputs are tested after inputs using the reverse transfer both tests checking the transfer is within the appropriate time window The Fail_ Data words contain the following information Fail_Data Word Contents Data received from input channel Data transmitted via output channel Data expected from input channel block under test 0 channels 0 to 7 1 channels 8 to 15 2 channels 16 to 23 3 channels 24 to 31 Page 5 5
29. Cremer ac PUR LUE 4 14 Mods 3 square Wave MOS as 4 15 Mode Software Mod aee actis aen te PI UH 4 15 Mode 5 Hardware Triggered Strobe Retriggerable esses 4 15 Operation Common to Modes A HP PIE A MUS 4 16 PIT Programining UR 4 17 EIU 4 18 Pagei Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Contents Chapter 5 BIT Configuration and Fail Data eese nennen nnn nnns 5 1 Com curation Deta onam odi ERR P b Ht Re na on ad teri noe en bed er ed rece Pr eio 5 1 Eal Di p I 5 2 Pecot bie 5 3 Enernal LoogbacEs oe 5 4 Esra l TT 5 5 desir dio rH 5 7 S EI 5 9 croi Hee 5 10 Appendix Device
30. Hz clock signal from the LCA This allows time intervals to be programmed in multiples of 1 64ms Page 4 16 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers PIT Programming Examples Example 1 To initialize Counter 2 of PIT 1 in mode 0 with an initial count of OXABCD the host software would perform the following steps 1 Write a byte of value to address BASEADD 0x26 to set the Control Word for Counter 2 for writing a 16 bit binary count and setting Counter 2 in Mode 0 2 Write a byte of value OxCD to address BASEADD 0x 24 to set the least significant byte of the initial count for Counter 2 3 Write a byte of value to address BASEADD 0x 24 to set the most significant byte of the initial count for Counter 2 Example 2 To initialize Counter 0 of PIT 2 in mode 0 with an initial count of OxABCD the host software would perform the following steps 1 Write a byte of value 0x30 to address BASEADD 0x2E to set the Control Word for Counter 0 for writing a 16 bit binary count and setting Counter 0 in Mode 0 2 Write a byte of value OxCD to address BASEADD 0x28 to set the least significant byte of the initial count for Counter 0 3 Write a byte of value OxAB to address BASEADD 0x28 to set the most significant byte of the initial count for Counter 0 Example 3 To initialize Counter 1 of PIT 2 in mode 4 with an initial c
31. Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Device Specifications 6N140A 55 C to 125 C Ambient Temperature Parameter Minimum Maximum Units 32 for 28V version VDC 32 for 12V version 24 for 5V version see Note 1 14 for 28V version 5 7 for 12V version 3 6 for 5V version 15 for 28V version see note 2 6 8 for 12V version 1 2 for 5V version V us Notes 1 Surge above 32V can be tolerated in line with the protective zener diode ratings 2 This assumes 10 load power supply Vi see Figure A 2 Normally would only represent cabling resistance Figure A 2 Test Circuit 16k for 28V 12V R Rr nfor 5V Page A 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Device Specifications Figure A 3 Input Circuit Characteristics HCPL 2731 amp 6N140A version 12 version 28V version 20 Protective Zener 1N4969 4 16 t 12 Maximum continuous 6N1040A 8 4 1 6 Nominal le Minimum for 0 75 logic 1 36 57 10 14 20 30 Volts V Page A 4 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO
32. Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data The Fail Codes are listed below Fail_Code Meaning KTBG PIO 2 access fail should be at address 0x100 above card under test KTBG PIO 2 setup failed Access to BIT VME Interrupt Control Register failed Check Configuration Data Word 5 valid Error during write of test data to KTBG card Data on channels 0 to 7 received too fast Data on channels 8 to 15 received too fast Data on channels 16 to 23 received too fast Data on channels 24 to 31 received too fast Data on channels 0 to 7 not received Data on channels 8 to 15 not received Data on channels 16 to 23 not received Data on channels 24 to 31 not received Error during write of test data to test card Data on channels 0 to 7 transmitted too fast Data on channels 8 to 15 transmitted too fast Data on channels 16 to 23 transmitted too fast Data on channels 24 to 31 transmitted too fast Data on channels 0 to 7 not transmitted Data on channels 8 to 15 not transmitted Data on channels 16 to 23 not transmitted Data on channels 24 to 31 not transmitted X is the test pattern number in hex Y is the test pattern number less 16 Page 5 6 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data PIT Counte
33. al loopback test includes an access test a PIO 2 card reset and an internal loopback checking the speed of loopback The access test checks access to the BIT VME Interrupt Register PIO 2 reset uses the standard reset routine The internal loopback test is run on all 32 channels of the PIO 2 card under test this is because internal loopback is a function of the on board LCA The test algorithm is write to all I O ports check no exceptions are generated and that ports do not change too quickly after a suitable delay re read all ports checking that they are now all changed to the correct values The test is then repeated writing 0 to all I O ports and checking they respond in the expected time The Fail_ Data words contain the following information Fail_Data Word Contents Data received from input channel Data expected from input channel T O block under test 0 channels 0 to 7 1 channels 8 to 15 2 channels 16 to 23 3 channels 24 to 31 The Fail_Codes are listed in the following table Fail Code Meaning Access to BIT VME Interrupt Control Register failed Exception generated during write to I O ports Ports 0 to 7 changed too quickly Ports 8 to 15 changed too quickly Ports 16 to 23 changed too quickly Ports 0 to 7 failed to change in time Ports 16 to 23 failed to change in time X 2 for writes of 1 X 3 for writes of 0 Page 5 4 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 8
34. ally if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one immediately after the other read or write or programming operations of other Counters may be inserted between them The format of the Counter Latch command is shown below SCI SCO 0 0 Don t care 0 Where SC1 and SCO specify the counter to be latched as follows SCO Counter 0 0 0 1 Page 4 11 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Read back Command The Read back command allows the user to check the count value programmed Mode and current state of the Out pin and Null Count flag of the selected counter s The command is written into the Control Word register and has the format shown below 7 6 5 4 3 2 1 0 1 COUNT STATUS CNT2 CNTI CNTO Bit Mnemonic Function COUNT Clear to latch count of selected Counter s STATUS Clear to latch status of selected Counter s Set to latch Counter 2 or 5 Set to latch Counter or 4 Set to latch Counter 0 or 3 Must be clear The Read back command may be used to latch more than one Counter by clearing the COUNT bit bit 5 and selecting the desired Counters more than one of the CNT bits can be set This single command is functionally equivalent to several Counter Latch commands The value of each Counter is held separately in its Counter regist
35. annels 12 to 23 5V input outputs Channels 24 to 32 not fitted Page 1 7 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Specifications Chapter 2 Specifications This section details the specifications common to all versions of the PIO 2 General Specifications VMEbus Compliance ANSI VITA 1 1994 Specification A24 016 D08 EO Supports Read Modify Write RMW and Supports Address Modifier Codes 0x39 0x3A 0x3D Ox3E Release on Register Access RORA interrupter Front Panel Single width VME containing a single LED Electrical Specifications Two 96 way DIN41612 compatible connectors that mate with rack mounted backplane connectors form the electrical connection to the board Current Consumption Current At 5V 0 6A 0 9A Power Dissipation VME 5V Remote Supply per Remote Supply per Active Input Active Output at 1A load current 50 mW 28V 20 mW 12V 8 mW 5V 50 mW 28V 20 mW 12V 8 mW 25V Voltage Supply Requirements 5V 0 25V DC total excursion including all transients Vripple 5 50 mV RMS maximum contained within the total excursion Page 2 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Specifications Safety Requirements WARNING Do not exceed the maximum rated input voltages or apply reversed bias to the a
36. ared by read of interrupt mask Interrupt not generated on VME bus X 2 for Interrupt levels 7 and 6 Y 0 or 8 for PIT counter 0 X 3 for Interrupt levels 5 and4 Y 1 or 9 for PIT counter 1 X 4 for Interrupt levels 3 and2 Y 2 or A for PIT counter 2 X 5 for Interrupt level 1 Y 3 or B for PIT counter 3 Y 4 or for PIT counter 4 Y 5 or D for PIT counter 5 Page 5 9 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data Where X C Fail_Code Meaning Transition interrupt check for I O channels 0 to 7 Transition interrupt check for I O channels 8 to 15 Transition interrupt check for I O channels 16 to 23 Transition interrupt check for I O channels 24 to 31 Interrupt queuing error X 6 for Interrupt level 7 7 for Interrupt level 6 8 for Interrupt level 5 X 9 for Interrupt level 4 X A for Interrupt level 3 for Interrupt level 2 for Interrupt level 1 ID Register Test Mask_Code 0010 The ID register test is in 2 parts first checking access to the BIT VME Interrupt Register and secondly reading and checking the ID Register The Fail Codes are listed in the following table Fail Code Meaning Access to BIT VME Interrupt Control Register failed Read of ID Register failed Page 5 10 Rev D Artisan Technology Group Quality Instrumentation Guaranteed
37. ation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Introduction Counter Timers The PIO 2 has six 16 bit programmable timers These timers are independent of the I O bits and may be used in any system application that requires enhanced counter timer capability All timers are fed from a common on board crystal clock running at 5 MHz divided to give a timer range up to second The counter timers may be programmed by the host VMEbus CPU to generate regular clock ticks or to time out after a pre programmed time period Each counter timer when it expires makes a local interrupt request which the PIO 2 then presents as a VMEbus interrupt The VMEbus interrupt level and the top 4 bits of the Status ID byte are preset by the host VMEbus CPU during the initialization of the PIO 2 The on board interrupt generator prioritizes local interrupt requests and adds the lower 4 bits of the Status ID byte to identify the source of the interrupt request uniquely Input Change of State Input bits can be programmed either to ignore changes of state or to generate an interrupt request as a result of the following conditions e A high to low transition e A low to high transition On either transition Whenever an interrupt is generated the Interrupt Status Registers ISRs are frozen until they are read over the VMEbus during the interrupt service routine Any input changes that are detected between the freezing and the
38. bit bcd 0 ctrlbyte bit RWmode 3 switch mode case 0 ctrlbyte bit mode 0 break case 1 ctrlbyte bit mode 1 break case 2 ctrlbyte bit mode 2 break case 3 ctrlbyte bit mode 3 break case 4 ctrlbyte bit mode 4 break case 5 ctrlbyte bit mode 5 break Page B 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual switch cntr case 0 ctrlbyte b break case 1 ctrlbyte bi break case 2 ctrlbyte break case 3 ctrlbyte break case 4 ctrlbyte bi break case 5 ctrlbyte bi break cntlo Uchar cnthi Uchar if cntr lt 2 else cmdbl switch cntr case 0 cmdblk co cmdblk co break case 1 cmdblk co cmdblk co break case 2 cmdblk co cmdblk co break case 3 cmdblk co cmdblk co break case 4 cmdblk co cmdblk co break case 5 cmdblk co cmdblk co break bi bi it counter 0 it counter 1 it counter 2 it counter 3 it counter 4 it counter 5 count count 8 cmdblk cntctrl0 2 k ontctrl3 5 unterO cntlo unterO cnthi unterl cntlo unterl cnthi unter2 cntlo unter2 cnthi unter3 cntlo unter3 cnthi unter4 cntlo unter4 cnthi unter5 cntlo unter5 cnthi Page B 4 Rev D Example C Code Subroutines ctrlbyte
39. bles counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on next CLK pulse This allows the counting sequence to be synchronized by software Again OUT does not go high until n 1 CLK pulses after the new count of n is written Mode 1 Hardware Retriggerable One Shot Not available on PIO 2 as the GATE inputs to the PIT are tied high Mode 2 Rate Generator This Mode functions like divide by counter OUT is initially high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter reloads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of n the sequence repeats every n CLK cycles After writing a Control Word and initial count the Counter is loaded on the next CLK pulse OUT goes low n CLK pulses after the initial count is written This also allows the Counter to be synchronized by software Writing a new count while counting does not affect the current counting sequence Page 4 14 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Mode 3 Square Wave Mode Interrupt generating capabilities are identical to Mode 2 use Mode 2 Mode 4 Software Triggered Mode OUT is initially high When the initial count expires OUT goes low fo
40. closures In addition to these COTS configurations PIO 2 may be supplied to meet the mechanical and thermal requirements of specific platforms with the addition of mission specific to type mechanics Radstone uses advanced thermal and mechanical design in the PCB metal work and assembly process to build in the required levels of ruggedness Build level 2 and higher circuit card assemblies include conformal coating as standard five styles fully support the power and versatility of the VMEbus so no matter how large or diversified your project absolute compatibility 15 assured at all stages of development A brief description of each build style follows Level 1 Intended for use in benign environments level 1 also provides the ideal cost effective method of complete system development The level 1 assembly comprises a double Eurocard size printed wiring board with high quality commercial plastic encapsulated components As software compatibility throughout the build styles is absolute a system intended for final implementation in a severe tactical environment can be developed and debugged at low cost switching over to target style only in the final stages of system integration Level 2 As Level 1 but tested in manufacture to provide an extended operating range Level 3 Level 3 boards are intended for applications that have extended temperature shock and vibration requirements but can be served by conventional forced air
41. complete ctrlbyte complete Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Typical Load Connection Schemes Appendix C Typical Load Connection Schemes Example Circuits The following example circuits are included to show typical load connection schemes Example 1 This example describes connection to a simple remote indicator panel containing a few switches and indicator bulbs and their connection to the remote DC supply 28V 12V 5V Remote supply PIO 2 Indicator Switch Row 17 SSR Row gq GND Remote supply Row Re te Indicat emote Indicator panel s Row d Note To maintain the full 250V isolation the remote supply GND must be connected in the vicinity of the remote indicator panel and not at the PIO 2 VME rack Page C 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Typical Load Connection Schemes Example 2 This example describes a typical setup for driving a motorised valve where any one of two ports can be connected to a third port a common setup in hydraulics pneumatics and waveguide switches for example Channel 0 is an output and used to connect port to port 3 Channel 1 is an output and used to connect port 2 to port 3 Channel 16 is an input and used to sense when port 1 is connected to port 3 Channel
42. configuration of a PIO 2 to the host how many inputs and outputs are fitted voltage range etc The mapping of values to configuration is user dependent The value set up by the links can be read by the host in the ID register at VME address BASEADD 0x30 where a 0 bit means that the corresponding link is fitted and a 1 means that the corresponding link is not fitted 7 6 5 4 3 2 1 0 2 and read back User defined link area Bits 7 and 6 can be used to read back the state of links E2 and E1 respectively See the previous description of links E2 and 1 Note Do not use links E24 and E26 Page 3 5 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Configuration Connector Pinouts In Table 3 3 the signals enclosed in braces are not active on PIO 2 However they are passed on to the next VME slot Table 3 3 VME Interface P1 Connector and P2 Connector Row B Pin Number Rowa
43. cooled racking systems These rugged boards comprise a double Eurocard size printed wiring board fitted with wide temperature range industrial grade components Level 4 Designed primarily for use in sealed ATR chassis and other conduction cooled environments the level 4 board features wide temperature range industrial grade devices an integral thermal management layer It also incorporates a central stiffening bar for additional strength Cooling is achieved through conduction of heat from the thermal management layer to the cold wall of the rack to which the boards are secured by screw driven wedgelocks Level 4 boards are temperature characterised during manufacture Level 5 As Level 4 but tested in manufacture to provide an extended operating range See Chapter 2 for more details of the environmental specifications of each build style Page 1 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Introduction Functional Overview The PIO 2 provides an efficient means of monitoring and controlling remotely located machinery and equipment from a VMEbus computer system Solid state relays permit the PIO 2 to switch low power DC voltages to provide fully isolated control of external relays or amplifiers of electro mechanical systems This offers the system designer the flexibility to interface with the real world in such application areas as Naval machi
44. dstone PIO 2 Manual Example C Code Subroutines The counter timers are designed to provide simple time interval generation terminating with an interrupt to the host processor over the VMEbus The following example contains a sample counter timer routine that is intended to generate such intervals This routine requires three parameters entr the counter to be used in the range 0 to 5 mode the counter mode to use mode 0 is recommended count a 16 bit count value representing the number of 1 64ms time periods 1 For this routine to generate a VME interrupt properly the VME Interrupt Vector and BIT VME Interrupt Control Registers must be set up before it 1s run When setting or clearing bits in the data registers remember that when written to these bits control the solid state relays if any and when read reflect the status of the opto couplers if any This means that for an output only configuration where only a few bits within a data register are to be set cleared this must first be carried out on RAM copy of the data register before the actual register is written to if the other bits of the data register are not to be affected void counter Uchar cntr Uchar mode Ushort count Uchar cntlo cnthi typedef union Uchar complete struct unsigned counter 2 unsigned RWmode 2 unsigned mode 3 unsigned bcd 1 bit TIMERCTRL TIMERCTRL ctrlbyte cmdblk struct pio2cmdblk BASEADD ctrlbyte
45. er until it is read the Counter registers are separate from the Counters themselves so the Counter registers can hold the latched counts while the Counters continue to decrement If multiple count Read back commands are issued to the same Counter without reading the count all but the first are ignored i e the count that is read is the count at the time the first Read back command was issued Page 4 12 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers The Read back command may also be used to latch status information on the selected Counter s by clearing the STATUS bit bit 4 The status of a Counter can then be accessed by a read from its Counter register this status information cannot be read without being latched first The format of the Counter status is shown below 7 6 5 4 3 2 1 0 Bits Mnemonic Function OUTPUT The current state of the OUT pin as follows 1 OUT pin is 1 0 OUT pin is 0 The PIT has an OUT pin for each Counter This allows software to monitor the Counter s output NULL COUNT 1 Null count has been reached 0 Count available for reading Indicates whether the last initial count written to the Counter register was loaded into the Counter itself The exact time this happens depends on the Mode in which the Counter was programmed to operate but until the count is loaded into the Counter it cannot be read from t
46. es of address space Offset From BASEADD Function Access Data channels 0 to 7 Read Write Data channels 8 to 15 Read Write Data channels 16 to 23 Read Write Data channels 24 to 31 Read Write Not used Interrupt status channels 0 to 7 Read Only Interrupt status channels 8 to 15 Read Only Interrupt status channels 16 to 23 Read Only Interrupt status channels 24 to 31 Read Only Interrupt status counters 0 to 5 Read Only Not used Interrupt mask set channels 0 to 3 Write Only Interrupt mask set channels 4 to 7 Write Only Interrupt mask set channels 8 to 11 Write Only Interrupt mask set channels 12 to 15 Write Only Interrupt mask set channels 16 to 19 Write Only Interrupt mask set channels 20 to 22 Write Only Interrupt mask set channels 24 to27 Write Only Interrupt mask set channels 28 to 31 Write Only BIT VME Interrupt Control Write Only VME Interrupt Vector Read Write Not used Counter 0 Read Write Counter 1 Read Write Counter 2 Read Write Control Word Register 0 Write Only Counter 3 Read Write Counter 4 Read Write Counter 5 Read Write Control Word Register 1 Write Only ID Register Read Only Not used Page 4 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers These registers may be accessed individually as bytes or in pairs as words Any attempt to access an unused location is bus errored by the PIO 2
47. form part of any order or contract or be regarded as a representation relating to products or services concerned The Company reserves the right to alter without notice the specification design price or conditions of supply of any product or service Trademarks Radstone and the Radstone logo are trademarks of Radstone Technology PLC All other company and product names are acknowledged as being the trademarks or registered trademarks of their respective companies Document History The document revision state refers only to the manual not the board Revision Date 10 92 1 95 4 97 1 98 3 02 Changes from the previous revision are sidelined Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Contents Contents Chapter 1 2 ce p a te ee 1 1 URS Wrasse ore ele a es 1 1 Used m Chis 1 1 BReliten Docume mE eeu E 1 1 Umm 1 1 ee uui mre lr mmi 1 2 rae 1 3 2 NTISDUS EOE os aceite alas 1 3 secs rats
48. ge 3 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Configuration Debounce Clock Selection Links E2 and select the clock that is used to debounce input signals from the opto couplers as shown in the following table Table 3 2 Debounce Clock Selection E2 El Debounce Clock Rate Response Timet worst case Out Out 4 76 Hz Out 76 Hz In In Out 1220 Hz In In 19 53 kHz The measured total time from the opto coupler current flow to an interrupt generated on the VMEbus if enabled O 9 Page 3 4 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Configuration ID Register The user can set up a value on links E20 E21 E22 E23 E25 and E27 Any combination of these links can be fitted as they have no effect on the function of the board but can be used to identify the particular
49. he Counter If the count is latched or read before this time the count value will not reflect the new initial count just written M2 to MO BCD Counter s programmed Mode BCD bits as programmed in the last Control Word written for that Counter If multiple status Read back commands are issued to the same Counter s without reading the status all but the first are ignored i e the status that is read is the status of the Counter at the time the first status read back command was issued Both the count and the status of the selected Counter s may be latched simultaneously by clearing both the COUNT and STATUS bits bits 5 and 4 in the Read back command This is functionally equivalent to issuing two separate Read back commands at once If both the count and the status of a Counter are latched in this way the first read of its Counter register returns the latched status The next one or two reads of the Counter register depending on whether the counter is programmed for one or two byte counts returns the latched count If multiple count and or status Read back commands are Issued to the same Counter s without any intervening reads all but the first are ignored Page 4 13 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Modes The Control Word used to program the PIT includes bits that control the Mode in which the Counter operates T
50. he available Modes are described in this section Definitions The following terms are used in describing the operation of the PIT CLK The clock input pin of a Counter which causes it to count GATE The GATE input pin of a Counter which enables counting OUT The OUT output pin which is controlled by a counter CLK pulse A rising edge then a falling edge of a Counter s CLK input Trigger A rising edge of a Counter s GATE input Counter Loading The transfer of a count from the Counter Register to the Counter Note Each of the three Counters has a CLK a GATE pin and an OUT pin of its own on the PIT The GATE pins however are not used on the PIO 2 and are permanently pulled up into the active state Mode 0 Interrupt on Terminal Count After the Control Word is written OUT is initially low and remains low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written to the Counter After the Control Word and initial count are written to a Counter the initial count is loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of n OUT does not go high until n 1 CLK pulses after the initial count is written If a new count is written to the Counter it is loaded on the next CLK pulse and counting continues from the new count If a two byte count is written the following happens 1 Writing the first byte disa
51. ing status only Mode 0 status check latching status and count Mode 0 count check latching status and count Mode 0 status check after loading count Mode 0 count check after loading count Mode 0 status check MSB WRD mode Mode 0 status check during MSB WRD countdown Mode 0 count check during MSB WRD countdown Mode 0 status check after second write to counter Mode 0 count check after second count write Mode 0 status check during wrap around test Mode 0 count check during wrap around test Mode 2 3 status check during count Mode 2 3 check count reload during countdown not allowed in this mode Mode 2 3 check count during wrap around test Mode 4 count running check Mode 4 check count during wrap around test Mode 5 status check Page 5 8 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data Interrupt Test Mask_Code 0008 After carrying out the access test and resetting the card under test the Interrupt test checks all PIO 2 interrupt sources from VME interrupt level 7 down to 1 and tests interrupt queuing Access is tested by reading from and writing to the BIT VME Interrupt Register reset of the PIO 2 is done using the standard reset routine Interrupts are disabled and cleared vector base is setup 0 0 0 and a check for premature interrupts is made before testing PIO 2 generated interrupts I
52. m cm cm cm cm cm cm cm cm cm cm cm cm cm cm cm Initialize coun where they will 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt 1 gt cm cm cm cm cm cm cm cm cm cm cm cm cm cm cm cm cm cm CC cr x ct Hd HO Hd SO Ss Bodom o uud sS Clear out any i counter activit 0 as as as as as as as as DO ters by programming them into mode of operation not generate interrupts mode 5 in this case trlo 2 trlo 2 trlO ter2 ter2 Lrl3 ter3 ter3 Erl3 ter4 ter4 ter5 ter5 x7A x7A C I xBA I nterrupts remaining from input channel and or y before initialisation There may be up to 2 interrupts pending for each while cmdblk intstatO 7 while cmdblk gt intstat8 15 while cmdblk intstat16 23 while cmdblk gt intstat24 31 while cmdblk cntintstat Page B 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Ra
53. nery control vehicle systems control power plants avionics and many others Figure 1 1 2 Functional Block Diagram Status and VMEbus Control Slave Register Interface BIT LED Interrupt Interrupt Generator gt Group 1 Group 2 K 3 Group 3 um Group 4 Generator ip VMEbus Interface The PIO 2 is addressed as a VMEbus slave occupying a block of locations in A24 address space Either 8 or 16 bit data transfers may be used between the VMEbus host processor and the PIO 2 to transfer status control and data The PIO 2 is a VME interrupter with interrupts generated on any change of state of an input bit or by the expiration of any one of the timer counters The basic Status ID interrupt word is set into the PIO 2 by the VMEbus host processor and the source of interrupt 1s encoded to permit simple identification Page 1 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Introduction Connections All I O connections to the PIO 2 are made through the system backplane to the user I O pins of the P2 connector Each I O bit is assigned 2 pins with no common connections Input bits are always optically isolated and must be driven from an external DC current source Cells The PIO 2 has 32 identical I O cells arranged in 4 group
54. nfiguration and Fail Data Configuration Data The PIO 2 test requires 6 longwords of configuration data 4 of which are the fixed usage test masks and slave processor timeout Configuration Meaning Data Word PIO 2 test ignore mask Bits are set to ignore tests as follows Bit Test 0 Internal loopback tests PIT counter tests PIO 2 interrupt tests 4 PIO 2 ID register test PIO 2 test serious failure mask The bit allocation is as above PIO 2 test fatal failure mask The bit allocation is as above PIO 2 slave processor time out count PIO 2 under test base address PIO 2 I O blocks fitted Bit Channels Tested if Bit Set Output on channels 0 to 7 Output on channels 8 to 15 Output on channels 16 to 23 12 Input on channels 24 to 31 Output on channels 24 to 31 The run time for a fully populated PIO 2 card under test is approximately 2 seconds for Initial BIT 12 seconds for Comprehensive BIT 2 to 3 minutes for Factory Test BIT Page 5 1 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data Fail Data The PIO 2 test is divided into the following test modules 1 2 3 4 5 Internal loopback test External loopback test PIT counter test Interrupt test ID register test Each test is identified by its respective mask code The following sections describe each test module with its fail data The
55. nter Latch Command should be written to the PIT before reading the Counter register alternatively the Read Back command can be used see page 4 12 Page 4 10 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Counter Latch Command The Counter Latch command is written to the Control Word register of the PIT This causes the selected Counter s value to be latched into the Counter register and held until the register has been read the Counter register is separate from the Counter itself so the Counter register can hold the latched count while the Counter continues to decrement This allows the contents of the Counters to be read without affecting counting in progress Multiple Counter Latch commands may be used to latch more than one Counter Each latched Counter value is held in its own Counter register until it is read Counter Latch commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch command is ignored The count read is the count at the time the first Counter Latch command was issued The count must be read according to the format least significant byte only most significant byte only or least significant byte then most significant byte which was set in the Control Word when the Counter was programmed Specific
56. nterrupts generated by each of the 6 PIT counters are tested at level 7 down to 1 I O port interrupts are tested in factory test mode only This is because with a debounce clock of 4 76 Hz the test time increases by approximately 1 minute from that taken by the fastest setting 19 53 kHz Interrupts tested in all 3 modes high to low and low to high transition high to low only and low to high only For the second and third options a check is made that interrupts are not generated when not expected Interrupt queuing is exercised by interrupts generated on both transitions checking that the correct interrupts are active or inactive as expected during the formation and clearing of the queue The Fail_ Data words contain the following information Fail_Data Word Contents Interrupt mask LSByte A bit is set for each active interrupt level Last test pattern written to I O port Address of I O port block last written to Timeout count If 0 test failed due to a timeout Address of Interrupt Status Register last accessed Last value written to the BIT VME Interrupt Control register The Fail_Codes are listed in the following tables Where 2 to 5 Fail_Code Meaning Access to BIT VME Interrupt Control Register failed Premature interrupts found in the test system PIT timeout error PIT countdown failed therefore no interrupt generated Wrong interrupt vector generated Wrong interrupt status mask generated Interrupt not cle
57. onal protection 20g peak sawtooth 11105 duration Bench handling Random 0 04g2 Hz with a flat response to 1000 Hz 6db Octave roll off from 1000 to 2000 Hz Sine 5g from 5 to 2000 Hz Operating 15 000 Storage 50 000 Conduction cooled Boards Build Style Comments Shock Humidity Salt Fog Low Pressure Vibration Feet Temperature C Mechanically compliant with IEEE 1101 2 1992 Designed for severe environment applications with high levels of shock and vibration small space envelope and restricted cooling supplies Conformally coated as standard Optional ESS Mechanically compliant with IEEE 1101 2 1992 Designed for severe environment applications with high levels of shock and Up to 95 RH with varying temperature 10 cycles 240 hours 5 salt 48 hours 40g peak sawtooth 11116 duration Bench handling Random 0 1 g2 Hz with a flat response to 1000 Hz 6db Octave roll off from 1000 to 2000 Hz Sine 5g from 5 to 2000 Hz Operating 70 000 Storage 70 000 Operating 40 to 75 at the thermal interface Storage 50 to Shock Decompression 10 C minute over range 0 to 70 000 Up to 95 RH with varying temperature 10 cycles 240 hours 40g peak sawtooth 11116 duration Bench handling Random 0 1g2 Hz with a flat response to 1000 Hz 6db Octave roll Operating 70 000 Storage 70 000 Rapid Operating 40 to 85
58. ount of OxFFFF the host software would perform the following steps 1 Write a byte of value 0x78 to address BASEADD 0x2E to set the Control Word for Counter 1 for writing a 16 bit binary count and setting Counter 1 in Mode 4 2 Write a byte of value OxFF to address BASEADD 0x2A to set the least significant byte of the initial count for Counter 1 3 Write a byte of value OxFF to address BASEADD 0x2A to set the most significant byte of the initial count for Counter 1 Example 4 To initialize Counter 0 of PIT 1 in mode 2 with an initial count of OXFFFF the host software would perform the following steps 1 Write a byte of value 0x34 to address BASEADD 0x26 to set the Control Word for Counter 0 for writing a 16 bit binary count and setting Counter 0 in Mode 3 2 Write a byte of value OxFF to address BASEADD 0x20 to set the least significant byte of the initial count for Counter 0 3 Write a byte of value OxFF to address BASEADD 0x20 to set the most significant byte of the initial count for Counter 0 Page 4 17 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers ID Register Offset 0x30 7 6 5 4 3 2 1 0 This is an 8 bit read only register that returns the value preset on links E20 E21 E22 E23 E25 and E27 It also returns the debounce clock selection on links E2 and The user may fit any combination of links E20 E21 E2
59. put is level sensitive and the logic level is sampled on the rising edge of CLK In modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a trigger sets an edge sensitive flip flop in the Counter This flip flop is reset immediately after it is sampled In this way a trigger is detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Notes In Modes 2 and 3 the GATE input is both edge and level sensitive The GATE inputs of all 6 counters are permanently tied high on PIO 2 so Modes 1 and 5 are not available Counter New counts are loaded and Counters are decremented on the falling edge of CLK The largest possible initial count is 0 see the Note below The counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either OxFFFF for binary counting or 9999 for BCD counting Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there The minimum and maximum count values for each Mode are shown below Mode Minimum Count Maximum Count Note 0 is equivalent to 2 for binary counting and 10 for BCD counting OUT The OUT outputs for each of the 6 counters is connected to the LCA which generates an interrupt on a low to high transition of these pins CLK The CLK inputs for all six counters are connected together and supplied with a 610 35
60. r Test Mask_Code 0004 The PIT Counter Test checks all modes 0 to 5 Tests are divided into initial comprehensive and factory depending on the run time An access test of the card under test and reset of the card are also included Access is tested by reading from and writing to the BIT VME Interrupt Register reset of the PIO 2 is done using the standard reset routine Each counter is tested in turn all following the same tests starting with mode 0 and working through to mode 5 modes are checked by a counter running a status check Wrap round tests are carried out in modes 0 2 3 and 4 during factory test BIT Mode 3 test checks the OUT signal Modes 2 and 3 are checked to ensure counter reload while the counter is running is not allowed Conversely in the mode 4 test counter reload while the counter is running is allowed The Fail_ Data words contain the following information Fail_Data Word Contents Counter under test 0 to 5 Counter value at fail point 4 Mode 2 test 6 Mode 3 test 10 LSByte counter under test 20 MSByte counter under test 30 WRD counter under test Page 5 7 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual BIT Configuration and Fail Data The Fail_Codes are listed in the following table Fail_Code Meaning Access to BIT VME Interrupt Control Register failed Mode 0 status check latch
61. r each Counter the Control Word must be written before the initial count is written e The Control Word must be written to the Control Word register for the Counter being initialised and the initial count must be written to the Counter register for the Counter being initialised e Initial counts of length 16 bits are set by writing the least significant 8 bits to the Counter register then writing the most significant 8 bits to the same Counter register e The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least significant byte and then most significant byte Since the Control Word register and the three Counters have separate addresses and each Control Word specifies the Counter to which it applies with the SCO SC1 bits no special instruction sequence is required Any programming sequence that follows the above restrictions is acceptable A new initial count may be written to a Counter at any time without affecting the Counter s programmed Mode in any way Counting is affected as described in the Mode definitions The new count must follow the programmed count format PIT Read back Operations It is often desirable to read the value of a Counter without disturbing the count in progress The Counter registers can be read directly but the Counter may be in the process of changing when it is read giving an undefined result To avoid this problem a Cou
62. r one CLK pulse then goes high again The counting sequence is triggered by writing the initial count After writing a Control Word and initial count the Counter is loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of n OUT does not strobe low until n 1 CLK pulses after the initial count is written If a new count is written during counting it is loaded on the next CLK pulse and counting continues from the new count If a two byte count is written the following happens 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to retriggered by software OUT strobes low 1 CLK pulses after the new count of is written Mode 5 Hardware Triggered Strobe Retriggerable This Mode is not available on PIO 2 as GATE inputs to the PITs are tied high Page 4 15 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Operation Common to All Modes This section contains general information on the operation of the PIT Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE in
63. s of 8 cells The configuration of these groups depends on the board variant Input and output components are fitted to or omitted from the cells in the groups to give the required configuration of inputs and outputs The three basic build configurations are e Input only Output only Monitored output Figure 1 2 Circuit of Input Only Cell Resistor 16kQ for 28V 12 2 2kQ for 5V P2 Row A Vcc Switch T 5V 12V or 28V Zener 1N4970 Channel In aav bomo c A Diode Opto isolator 1N4148 Plastic HCPL2731 Hermetic 6N140A P2 Row C The diode protects the opto coupler from reverse voltages caused by contact bounce in the load when the protective zener has not been fitted Note The zener diode is only fitted on level 5 boards The resistor value depends on the configured load voltage 5V 12V or 28V and is chosen to give a current of approximately 1 6 mA through the opto coupler The input terminals are polarised so that the opto coupler and transorb function correctly Page 1 4 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Figure 1 3 Circuit of Output Only Cell Vec Channel Out Opto relay Introduction Plastic PVDZ172 Hermetic CD20CD Zener 1N4970 33V P2 Row A 5V 12Vor28V
64. s of the vector contain a priority encoded indication of the source of the interrupt as follows 0 Spurious interrupt 1 Channels 7 to 0 2 Channels 15 to 8 3 Channels 23 to 16 4 Channels 31 to 24 5 Counter 0 6 Counter 1 7 Counter 2 8 Counter 3 9 Counter 4 10 Counter 5 Page 4 7 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Programmable Interval Timer Registers Offsets 0x20 to 0x2E The PIO 2 has two Programmable Interval Timers PITs These are either Intel or Harris 82C54 devices Each PIT has three independent Counters Counter Registers Each of the three Counters is a 16 bit down counter and has a separate 8 bit read write register for loading it and reading it back to access all 16 bits of the Counter requires two consecutive accesses to the Counter register The addresses of these Counter registers are as follows PIT Counter Offset Page 4 8 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Registers Control Word Registers These are 8 bit write only registers at offset 0x26 for PIT 1 and 0x2E for PIT 2 The Counters are programmed by writing a Control Word which specifies which Counter is being programmed into the Control Word register Note The Control Word has 8 bits whereas the term
65. ssembly If such conditions occur toxic fumes may be produced due to the destruction of components Page 2 2 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Specifications Mechanical Specifications Weight The approximate weights of the different styles of PIO 2 are as follows Level4and5 450g Levels to 3 3755 Dimensions Figures 2 1 and 2 2 show basic VME board dimensions in millimetres with inches in parentheses for guidance only All build standards of the PIO 2 board are ANSI VITA 1 1994 VMEbus Specification compatible This allows all styles of assembly to be fitted into any commercial VMEbus development chassis Level 4 and 5 boards comply with IEEE Std 1101 2 1992 Figure 2 1 VME Dimensions for Build Levels 1 to 3 261 85 10 309 y lt gt 160 6 29 xi 20 32 0 8 2 54 0 1 Page 2 3 Rev D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Radstone PIO 2 Manual Specifications Figure 2 2 VME Dimensions for Build Levels 4 and 5 2 233 36 9 187 2 4 20

Download Pdf Manuals

Related Search

Related Contents

Fujitsu LIFEBOOK E7440    baixar o manual de utilização.  伊予市固定資産台帳整備及び公共施設等 総合管理計画策定業務委託  IC-3115W Quick Installation Guide  Samsung 931C Felhasználói kézikönyv  Alcohol 120% / 52% Manual USER Manual  An 2000, ère nouvelle = produits nouveaux  Whirlpool er6ahkxsq00 User's Manual  caution  

Copyright © All rights reserved. Failed to retrieve file