Istituto Nazionale di Fisica Nucleare Sez di Ferrara
Contents
1. Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN Servizio Elettronico Istituto Nazionale di Fisica Nucleare Sez di Ferrara AUTO irta aa ie ira iii Roberto Malaguti ORA Angelo Cotta Ramusino Roberto Malaguti Via Saragat 1 44100 Ferrara http www fe infn it servizi elettronica printed in Ferrara 10 April 2008 Version 1 1 Pag 1 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN La Servizio Elettronico Index KU CCUG AUN I T E EE E A 4 LE BICK VA SU eeina e E EE EEEE E EOE 5 I2 beha i0fsoMmMari eea E E EE 5 1 3 Simulazuons dIaSfaliSisazizianala rara 6 DCO LR RR OR A 7 Aka FEP Done S Sae a ent 7 2 1 b Communication LED figure 5 i 7 ZE Rady LED INGUIN CD ll 7 2 1 d SIPAaLEED 0009 7 2 1 e NIM Inputs figure 5 and 6 7 2 1 f NIM Outputs figure 5 and 0 8 ZEO VEO DOUTE G na a E E oecine pu eme ss nessa sao aain rai 8 2 1 b Global OR output INOUE aaa secet eset cetaacunteeeratdacsasseavauszaeeiadasson cen svssatausin EENEN 8 2 1 i ECL Outputs EVES pic sciesptch ces ones taicscowk pacepsnsaic torn ieri 8 2 1 j ECL spare Outputs figure 6 8 2 1 k UART JTAG port figure lla 8 2 1 1 In System Programming of Serial Configuration Device figure 7 8 2 1 m CPLD JTAG port MULES icc ssreccachonesdincsceusciantssiaacscressncesisacesenereseaoteiauiavxap2. Sezione di Ferrara INFN U Servizio Elettronico 5 3 TDC time jitter evaluation 1200 1000 800 600 400 200 Se EIJESHIEEIZIRKRIIERGEZ EG Figure 16 TDC Jitter measure To valuate the TDC precision on figure 16 is show the measurement obtained connecting both TDC input at the same signal and plotting the time difference histogram Pag 19 PI Istituto Nazionale di Fisica Nucleare Sezione di Ferrara NF N Servizio Elettronico 6 Schematic Diagrams inside the CPLD 6 1 The Global OR output The Global OR output is the result of the 16 trigger outputs a zero in the Mask_OR register hides the correspondent channel into the Global OR output result Figure 17 Global OR schematic 6 2 The Prescaler Counter 1 of 16 The DATA 15 0 set the counter module One cycle trigger pulse before the pm_counterO reaches the end of the counting the output cout became active When the cout signal is active the trig_in signal can pass to the Trig_out output The cout signal also active the sload input this input re loads the pm_counterO with the counter module Presc_Reg 15 0 at the rising edge of the clock signal Figure 18 Prescaler programmable Counter simplified schematic 6 3 The Rate Meter Counter 1 of 16 The trigger inputs are sampled with a 80MHz clock and feed a 24bit wide counter Every 1 second the Load_latch signal
3. SW DIP 8 SM Board Address 2 OFF 1 Board Address 2 OFF 2 Board Address 2 OFF 4 4 Board Address 2 OFF 8 5 ON Disable UART communications 6 8 Notused Tonon SW H ILL Figura 11 switch 1 is on the left Switch 1 to 4 sets the board address from 0 to 15 Each board placed in the same crate must have a different board address When Switch 5 is OFF at power on the PAX_PS accept commands coming from the UART port When Switch 5 is ON at power on the PAX_PS accept commands coming from the SPI port Pag 10 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN La Servizio Elettronico 4 0 Operating instructions How to configure the PAX_PS with the UART port Terminal Configuration 115200bps 8 N 1 SWI S OFF Adaptor cable from J6 connector to RS232 connector DB9 pin 2 connect to J6 pin 8 DB9 pin 3 connect to J6 pin 7 DB9 pin 5 connect to J6 pin 10 or 2 or both DB9 pin D SUB Female solder side 10 pin IDC connector J6 4 5 1 3 7 OO G G G ooocoo No iu no ooos hi 3 ie e IT rransmitData Data Data Terminal oe SystemGround Ground x e eal fs Trees O es forse ooo a TE Fine ndo ST 4 1 Presentation message coming from PAX_PS at reset At power on the Flash memory data are checked and loaded into the working registers a Main Menu page is displayed ValidDataInFlash 1 Using data in Non Volatile Memory to configure th
4. in differential ECL levels by the MCI0ELT24 The transistors BRF450 also provide the NIM conversion 7 3 The NIOS processor z te Lei i E E E F 2 x a dn Ad dl 2 i ali si DE nn LI rac D die ge sommi A fe og Pak Di aia FO anu SIAT terr E ed ED dik e a Fila Fak SEE a Ci TED Ci E SeA Rit ig Fila La Fak mAN a Kat Foe Dr 1 Si FER ai ca E H io E Di ca EI a us sir 5 a 4 LI zi a ed ae or ta 1 d nio ET 5 td Cra eee oti EE LS ey E Le da Uli mira aos ici FACE x ae Emer Fok Lol Tae io aia ae a ere LAI H a ai Said Or __L Asi sd Gr oi Gil FSG Apia Cron ae ta mn b Lr fia sil 1 TGA 1 T Si Aa om pei Foo SRAM pls Gra i ee FG Aly i presto l LAI n r Era s a La a Lia SPAM alli cd al ps ni men ria del a Cir ee LI n Gros Cui 7 yo RAGA pf oo 3 Pt sel ig ean i Fee 05a MICSCMORGOVOLED las rea arabe greta a p ai E AE L akja Lira ch a di a i Fra GU RIT lt C ned Pul Gs NE TH rg eer We aT z l Ra ali LAET FK Wi Figure 21 NIOS schematic diagram The NIOS processor is build into the Cyclone IT logic the program is executed from an extern memory and its clock come from a 20Mhz clock multiplied 5 2 by the FPGA PLL unit The NIOS function is to govern the communication store the function parameter input Mask and counters module and read the rate meters counters Pag 22 TY Istituto Nazionale di Fisica Nucleare Se
5. m r_ehkauto_generated safe_q 0000 0001 xX 0000 xX 0001 x Figure 4 Pag 6 PI Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN L Servizio Elettronico 2 Connectors Outputs CH 14 CH 15 Global OR out ECL outputs 1 fo e Figure 5 Front Panel Top Figure 6 Front Panel Bottom 2 1 a SPI Port figure 5 SPI Port allows communication with the PAX_CTRL board The connection cable is pin to pin Different boards plugged into the same crate are parallel connected to the same SPI bus This is NOT a Ethernet connection Improper connection can damage the board 2 1 b Communication LED figure 5 Communication LED blinks when the board recognise its own address 2 1 c Ready LED figure 5 Ready LED 1s on when all voltages are correct and the on board logic is ready 2 1 d Signal LED figure 5 Signal LED blinks when a trigger transit on an output OR function 2 1 e NIM Inputs figure 5 and 6 The NIM inputs connectors group is the right side column Channel 0 1s the first connector on the top Channel 15 is the penultimate Pag 7 LE Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN LA Servizio Elettronico 2 1 f NIM Outputs figure 5 and 6 The NIM outputs connectors group is the left side column Channel 0 is the first connector on the top Channel 15 is the penultimate 2 1 g Veto in f
6. ver 1 0 20 Feb 2008 INFN FE R Malaguti 1 Flash Parameters Valid Flag PAX SPI_BoardIDb Basic Diagnostic Functions Menu a lene a b 4 4 Choice c Select Choice 4 5 Choice a a Initialize board registers with a debug pattern 3 Set signal simulating beam activity Exit Target Registers IDs Followed by lt enter gt A Cotta Ramusino Listen to PAX SPI commands Stop UART communication and switch to SPI communication Parametric Setting Menu Set a parameter on board PAX_PS display the list of available parameters and prompt for modification PRESC_00 addr 0x01 PRESC_01 addr 0x02 PRESC_02 addr 0x03 PRESC_03 addr 0x04 PRESC_04 addr 0x05 PRESC _05 addr 0x0 6 PRESC_06 addr 0x07 PRESC_07 addr 0x08 PRESC_08 addr 0x09 PRESC_09 addr 0x0A PRESC_10 addr 0x0B PRESC_11 addr 0x0C PRESC_12 addr 0x0D PRESC_13 addr 0x0E PRESC_14 addr 0x0F PRESC_15 addr 0x10 IN_MASK addr 0x20 OUT_OR_MASK addr 0x21 CPLD_FakeBeamFlags addr 0x22 Enter ID of Target Parameter Enter Dat a hex hex for Target Parameter ConsoleSetOneParamOnBoard TargetAdr 0x01 0x1 0x00 SetValue 0x0 ReadBack Value 0x0 Pag 12 PT Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN La Servizio Elettronico Note IN_MASK and OUT_OR_MASK are 16 bit wide words a zero written into these registers disable the corresponding channel a unos enable the
7. 65535 or can be software disabled with a Input Mask register When the Global Veto input is active all the PAX_PS outputs are disabled For monitoring the output activity a Global OR output port with a mask register to select the channels and 16 Rate Meters Counters readable via UART or SPI port are available All the signals inputs meet the NIM standard level 0 OV 1 800mV on 50ohm The outputs are provided both in NIM and ECL levels The global OR output is provided only in NIM level Numbers of inputs 16 NIM Numbers of outputs 16 NIM 16 ECL Controls signals 1 NIM Veto input 1 NIM global OR output Communications port Ix UART 115200bps 8 N 1 2x JTAG ports J7 CPLD Jo FPGA 1x Active Serial Programming port J5 1x SPI communication J2 1x parallel private BUS on P2 VME connector not jet implemented Board Dimension VME 6U 233 35 x 160 mm Weight 450gr Power supply SV 5 2Amp from standard VME P2 backplane Forced ventilation is recommended Pag 4 1 1 Block Diagram NIM input 1 D gt Trigger INs NIM input 16 O gt NIM O gt Global Veto SPI BUS Nim to LVTTL Nim to LVTTL Nim to LVTTL Istituto Nazionale di Fisica Nucleare Sezione di Ferrara Servizio Elettronico MSVIN LOdNI MAX II CLPD Cyclone II FPGA connector lt 6 x RateMeter Counters RS 232 1 2 Behavior summar
8. CL outputs can be left unconnected Tra OmV pi 783 4529 mc 7980 MI 772 01 o 5 736 10 0nadiv F Smi a 2 0m p 211 4470 728 0ra M 4 0m m 341 1 10 0ns dr 2IL0GS IT 25 0pa pi fica 200m vo 20 065 IT 25 0pa pi Mica 164mV Eca 200mv n Eei 164mv dl 200m 10 0ns A3 200m 10 0n5 Figure 12 NIM output terminated Figure 13 NIM output unconnected Channel 2 light blue Test input signal NIM Channel 3 magenta Trigger Out NIM signal 0 0 Volt 1 774mV on 50ohm Channel 4 green Trigger Out ECL signal 0 0 79Volt 1 1 75Volt Channel4 comes from a differential to single ended probe with an attenuation factor 10 5 2 Timing All timings measurements are performed with a TDC Time to Digital Converter model C A E N V1290A with a time resolution of 25pS The measurement set up was so arranged A NIM pulse is sent to the PAX_PS inputs the same pulse but ECL level is send to TDC input 1 the PAX_PS NIM output is connect to the TDC Start trigger and the same ECL output channel from the PAX_PS board is send to the TDC input 2 The time difference between input 2 and input 1 represent the delay time introduced by the PAX_PS board plus the cables figure 14 5000 measurement input 2 input 1 for each channel are recorded for time jitter evaluation Figure 15 show the set up for valuate the TDC measure precision the same signal was send at input 1 and input 2 the measured time difference 1s
9. copies the pm_counter1 measure into lpm_ff1 The count_aCLR pulse fellows the Load_latch pulse and clear the counter The pm_FFI keeps rate meter measure available for reading Pag 20 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN a Servizio Elettronico SOHIHZ C knick l Cinzia ha Drag ipm f 5 3 E ET ipm csunier OVE Faan ni DFF Rate Meter messure n na Sur aa iL e Riki in bh j Fati i Ma fi LR a chock gna o i_ UL dock m PM Ota oy g DA Jt Tigger signa cout enaiis A is ina I E One clock pulse every Tsoonid int Lia leks 4 BE i Sarr A Counter Clear one cice avery 1 econ aes BI a i very l i Orern Flag coon sll gt An i in Figure 19 Rate meter logic 7 0 Board Schematic 7 1 The input circuit nbuss wilches DE 138 LL gt To SHTETI GAF C139 anne WEE Figure 20 input circuit The input circuit converts NIM level signals coming from the front panel LEMO connectors to Low Voltage TTL signals for the CPLD logic It s based on a ECL to TTL converter MC10ELT25 and a level adapter transistor BRF450 The signal is reduced at 3 3V maximum with the SN74CB3T1G125 Pag 21 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN LA Servizio Elettronico 7 2 The output circuit RCL outs HIM LHH LAT FIL LH L TTLNn Figure 20 LVTTL to NIM ECL Converter The LVTLL signals coming from the CPLD outputs is converted
10. corresponding channel But for simplicity the numbers are shown in hexadecimal format 4 6 Choice a b Parametric Setting Menu Read Rate Meters Counters Rate Meters shows the number of trigger for each channel given per second Counters are 24 1bit deep 24bit is the counter and 1 bit is the overflow flag For counts greater than 16 777 215 an overflow occurs RM_00 RM_O1 RM_02 RM_ OS RM_04 RM_05 RM_06 RM_07 RM_08 RM_09 RM_10 RM_11 RM_12 RM_13 RM_14 RM_15 Oo Oo o 5 o o o 9oo too ooo Oo O 4 7 Choice a c Parametric Setting Menu Read and Print all parameters stored on board This function shows all the registers address and current value Adr 0x01 PRESCOO 10 AdF 0x02 3 PRESCOI 20 Adr 0x03 PRESCOZ FA Adr 0x04 PRESCO3 8 Adr 0x05 PRESCO4 5 Adr 0x06 PRESCO5 5B1 Adr 0x07 PRESCO6 10 Adr 0x08 PRESCO7 10 Adr 0x09 PRESCOS 40 Adr 0x0a PRESCO9 80 Adr 0x0b PRESC10 100 Adr 0x0c PRESCLI 30 Adr 0x0d PRESCI2 6B Adr 0x0e PRESC13 AA Adr 0x0f PRESC14 1B Adr 0x10 PRESCI5 0 Adr 0x20 IN_MASK gt ILIE Adr 0x21 QUT OF MASK ffff Beam Activity Flag is OFF 4 8 Choice a d Parametric Setting Menu Store all parameters previously read from board to Non Volatile Memory This function stores all the current working registers into the Non Volatile Memory Confirm Store parmeters to Non Volatile Memory y n q Exit Select C
11. e board XferParamTOBoard passed Number of Mismatches 0 Board Configuration done n PAX PS Board on board configuration amp diagnostics ver 1 1 28 March 2008 INEN FE R Malaguti A Cotta Ramusino Flash Parameters Valid dei 1 PAX SPI _BoardID 2 Main Menu a Parameters Setting Menu b Diagnostic Menu C Listen to PAX_SPI commands q ERIC Select Choice a c Followed by lt enter gt Pag 11 Istituto Nazionale di Fisica Nucleare Sezione di Ferrara Servizio Elettronico 2 INFN L_ 4 2 Choice a Parametric Setting Menu A menu with 5 option regarding parameter reading and setting is proposed PAX PS Board on board configuration amp diagnostics ver 1 0 20 Feb 2008 INFN FE R Malaguti A Cotta Ramusino Flash Parameters Valid Flag 1 PAX SPI BoardID 3 Console commands to work on Board Parameters a Set a parameter on board b Read Rate Meters Counters C Read and Print all parameters stored on board d Store all parameters previously read from board to Non Volatile Memory e f q Read and Print all parameters present in Non Volatile Memory Configure board with parameters read from Non Volatile Memory Exit Select Choice a f Followed by lt enter gt 4 3 Choice b Diagnostic menu This diagnostic menu allows to initialize the board with a pre configured diagnostic setup and to modify the Beam activity Flag PAX PS Board on board configuration amp diagnostics
12. ensayaestunasmenrngereioacs 8 2 1 n JI VME connector figure d Ja s nr 9 2 1 0 Push button Reset figure 10 9 U Boot 10 4 0 Operating INSIFICHOlS car 11 4 1 Presentation message coming from PAX_PS at reset 1 4 2 Choice a Parametric Setting Menu 12 4 3 Choice b Diagnostic MENU 12 4 4 Choice c Listen to PAX SPI commandS iii rie rie rie rie rie rie rie nie rioni nie nienione 12 4 5 Choice a a Parametric Setting Menu Set a parameter on board 12 4 6 Choice a b Parametric Setting Menu Read Rate Meters Counters 13 4 7 Choice a c Parametric Setting Menu Read and Print all parameters stored on board 13 4 8 Choice a d Parametric Setting Menu Store all parameters previously read from board to Non Volatile VICO nananana 13 4 9 Choice a e Parametric Setting Menu Read and Print all parameters present in Non Volatile Memory 14 4 10 Choice a f Parametric Setting Menu Configure board with parameters read from Aon yvonne DeO ee ATO E 14 S Mers URGING INES aaie E EEE A EE T EEE E EE 15 5 1 NIM amp ELL Snare dirai E eran 15 SII aa 15 Table 2 Board 1 time measurement eerccrreerece iconica rene zio nice ren zio nic ee ee iice rece zio rice ricezione 17 Table 3 Board 2 t
13. hoice n y Followed by lt enter gt y ParamFromBoard table copied to Non Volatile Memory done Pag 13 2 INFN C 4 9 Choice a e This Function shows the Non Volatile Memory data Non Volatile Memory ValidDataInFlash 1 1 PRESCOO 0 2 PRESCOO 2 3 PRESCOO 4 4 PRESCOO 8 5 PRESCOO 10 6 PRESCOO gt 20 7 PRESCOO 40 8 PRESCOO 80 9 PRESCOO 100 10 PRESCOO 200 11 PRESCOO 400 12 PRESCOO 800 13 PRESCOO 1000 14 PRESCOO 2000 15 PRESCOO 4000 16 PRESCOO 8000 17 IN MASK Pirie 18 OUT OR MASK ffff Beam Activity Flag is 4 10 Choice a f Non Volatile Memory This function copies the data from the Non Volatile Memory into the working registers XferParamTOBoard passed Number of Mismatches ConsoleConfigureBoardFROMFlash was successful Istituto Nazionale di Fisica Nucleare Sezione di Ferrara Servizio Elettronico Parametric Setting Menu Read and Print all parameters present in Parametric Setting Menu Configure board with parameters read from Pag 14 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN La Servizio Elettronico 5 Measurements 5 1 NIM amp ECL signals For a better ECL output signal corresponding NIM output must be terminated on 50ohm Figure 12 NO Delay on rising edge Figure 13 NIM output unconnected and the ECL output with a slow rising edge When only the NIM output is required the E
14. igure 6 The Veto input is the last connector on the right An active signal on this input set all the NIM output at level 0 but the counters are still running 1 e when the Veto input is active the incoming triggers are counted but the triggers outputs are disabled 2 1 h Global OR output figure 6 The Global OR output is active whenever an output is active 2 1 1 ECL Outputs figure 6 The ECL outputs are the faithful copy of the corresponding NIM output Signals are in differential pair positive signals are on odd pins negative signals are on even pins The white arrow on the connector marks pin number 1 Channel 0 is on pins 1 and 2 channel 2 is on pins 3 and 4 and so on Pins 33 and 34 are connect to board Ground 2 1 j ECL spare Outputs figure 6 The ECL Spare connector is recessed respect the board front panel This connector and the ECL connector on the board edge are connected in parallel gt oe a Ti hi sha 2s iL i fe o3 S i di 7 seg be al E papatet 2 Uddenue ttt aru nut gta SL unre E ELLI LL LU e VI Lad DE OW DE Pe Lit Li 70590 a e F E E E s e E F E E E tE ILA h pi mi a bo hi hi a ma ca T co ca i Figure 7 J6 and J5 connectors Figure 8 J7 connector CPLD JTAG port 2 1 k UART JTAG port figure 7 Connector J6 is the JTAG port for the FPGA logic programming firmware download It s also the UART RS 232
15. ime measurement 0 ccscccssosssessccnsosssesscctccssesccctecsssesccccecssssrsestecsssescensooass 18 5 3 TDC time tter evaluation erasoren EE 19 6 Schematic Diagrams inside the CPLD eesssssscceccsscccccccssscccecccsscccccccsssecccccsssececccsscceee 20 CI The Giona OR GAN ecer E essence 20 Pag 2 PT Istituto Nazionale di Fisica Nucleare Sezione di Ferrara NF N Servizio Elettronico 6 2 The Prescaler Counter 1 Of 16 eee 20 6 3 The Rate Meter Counter 1 of 10 rire rie rie erre eee rei erereeiereeeieeeeee 20 0 board Schemalit air 21 de EDEPOL I U a rara 21 Ta The output Cr IO 22 Lr THE NIOS PrOCCSSOT aoro E E E E io 22 Pag 3 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN Servizio Elettronico i i errrrr 1 BEREEERECROOREREEEEEE as te ELELEIELS 4 iti A r aoe d P d r a a 4 a L i Un 1141 Iiii bR TO SERIO SLAF Aiai aan dik fiji ij tiir dit rT CILE oUF sith ni cd r4 Meg AF wE Mii mm fa Fi Oe ty Oy d 1 Oey d 1 te tt eo oe y g Pee ee ne pa pe a e dre ipo if Oo Ca lt gt Cd fe cy i DD OO Sigla ou uu uo C C Ar Er Er Cr eh eh cn PaP Figure 1 Board picture 1 0 Specification The PAX_PS board fig 1 1s a 16 independent channels programmable trigger pulse prescaler Each prescaler counter Count Reg can be set in a range from 0 to
16. lay column value are obtained from CPLD simulation Delay time values comprise the cables delay for this reason the actually channel transition time 1s less than the indicate value These value are reported only for channel to channel delay comparison Pag 17 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN Servizio Elettronico Simulated Measured Delay Delay Dev Stand Channel 0 14 846 0 0605 Channel 1 0 0507 0 0647 0 0574 14 14 58 0 0619 0 0567 00 999 154 16 Channel 6 1947 14 0 0574 34 Channel 7 Channel 8 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Channel 9 Channel 10 Channel 11 6 535 0 0616 Board 2 Standard Deviation 412 0 0553 0 0732 i 0 0629 Channel 13 Channel 14 Channel 15 Only Cable 0 0479 1928 0 0597 Channel 12 DE Board 2 Average Delay Delay time and Standard Deviation unit is nS 10 seconds Simulated Delay column value are obtains from CPLD simulation Delay time values comprise the cables delay for this reason the actually channel transition time is less than the indicate value These value are reported only for channel to channel delay comparison Pag 18 TY Istituto Nazionale di Fisica Nucleare
17. plotted on figure 16 Pag 15 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN Servizio Elettronico NIM in out Figura 14 Set up for Evaluating the PAX_PS propagation delay PULSE GEN NIM out m Figura 15 Set up for evaluating theTDC intrinsic precision So far we have made 2 PAX_PS boards table 2 and table 3 represents the measurements coming from board 1 and board 2 respectively Pag 16 TY Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN e Servizio Elettronico Table 2 Board 1 time measurement Board 1 Simulated Measured Dev Stand Channel 0 5 0 0573 0 0530 12 346 0 0600 Channel 1 Channel 2 Channel 3 z Channel 4 k Channel 5 Channel 6 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Channel 7 Channel 8 2 451 0 0629 Board 1 Standard Deviation Channel 9 0 0642 Channel 10 504 11 500 0 0658 Channel 11 15 2 0 0667 Channel 12 0 0618 Channel 13 1 230 0 0732 12 35 0 0612 0 0628 Channel 14 4 Channel 15 0 206 0 0483 12 790 0 0630 Only Cables Ha Average Board 1 Average delay Delay time and Standard Deviation unit is nS 10 seconds Simulated De
18. standard port Pinout and communication standard is described on paragraph 4 2 1 1 In System Programming of Serial Configuration Device figure 7 The Cyclone FPGA firmware is store into a Serial Configuration device type EPCS64 This memory can be directly programmed using the Active Serial Mode through J5 connector 2 1 m CPLD JTAG port figure 8 The Max IT CPLD firmware can be downloaded through the JTAG port J7 Pag 8 PA Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN Servizio Elettronico mi TN ABA AA RAE i i T ih alfa i Figure 9 JI VME Connector Figure 10 Reset push button 2 1 n J1 VME connector figure 9 The PAX_PS board meet the VME P2 connector standard regarding the power supply but bus communication standard is not implemented In any case this board doesn t interfere with VME communications 2 1 0 Push button Reset figure 10 The Reset button is placed behind the SPI connector and LEDs It can be pressed with a thin screwdriver Pag 9 TY INFN 2 3 0 Before installation Istituto Nazionale di Fisica Nucleare Sezione di Ferrara Servizio Elettronico The dip switch SW1 must be set before the board installation Sw H e ae PAX_SPI_IDO RS I 2 15 _ PAX SPLIDI RA ni di u PAX_SPI_ID2 R6 soli PAX_SPIID3 R8 o i ie SpareSWO0 R10 68 311 SpareSW1_ _R12 A 10 SpareSW2 R13 bl La SpareSW3 R14
19. y gt NIOS processor LVTTL to NIM Trigger OUT LVTTL to ECL P2 DATA aus 10 99UU0I JO gt O 10 99UU0I Zd O NIM Output 1 NIM Global OR 16x Trig ECL OUT AUX BUS 8bit a ae Mask a Count O 0 15 ini 0 15 OR E to a JL tL 1 0x0001 mi i e e Glossary LL NIM pulse No signal X Don t care Pag 5 LT Istituto Nazionale di Fisica Nucleare Sezione di Ferrara INFN La Servizio Elettronico 1 3 Simulations diagrams Fig 2 Mask Register in simulation called Enable stops the prescaler counting last row in diagram and disables the trigger output Pa us ian us ca Lis SB ED ue Presc_Feg Fasal l Velo Trig_out n generated sate_q DODA G00 XOD02 0001x0000 00d illo DOGS D002 COCK ODDOxOO04 100 Figure 2 Fig 3 When a new prescaler factor is set it has effect only when the previous count is completed 6 1 us 138 US 3 66 US 9 5 us Enable Presc_Reg 0004 k 0001 Reset New Prescaler Value Tagin LL TA LT TUT Veto Tnig_out PEt TT tt tt Lj i LL r_ehkauto _generated safe_g 0002 4 0007 xX 0000 X 0004 x 0003 X 0002 X 0001 x 0000 X 0001 X 0000 X 0007 xod Figure 3 Fig 4 Veto input disables PAX_PS trigger outputs the trigger count is non affected 95 us 10 14 US 10 78 US 1142 US 12 0 us Enable Presc_Reg Reset Trig_in Veto Ri Trig_out FT Veto m
20. zione di Ferrara INFN Servizio Elettronico Pag 23
Download Pdf Manuals
Related Search