NEC_uPD424260LE_RAM_..
Contents
1. tRWL amp gt NINNI 18 UPD42S4260 424260 a Upper Byte Late Write Cycle NINNI Remark L I O Don t care 19 4PD42S4260 424200 0 Lower Byte Late Write Cycle ae ED 600000 QOO Remark UIO Don t care 20 J J44 4PD4284260 424200 a Read Modify Write Cycle Address Samum 21 UPD42S4260 424260 Upper Byte Read Modify Write Cycle lt lt gt 105 lt Remark In this cycle the input data to Lower is ineffective The data out of that remains Hi Z 22 f 0 lt uPD42S4260 424260 a Lower Byte Read Modify Write Cycle Address IR te lt Remark In this cycle the input data to Upper is ineffective The data out of that remains Hi Z 23 4PD42S4260 424200 Fast Page Mode Read Cycle lt gt Address Remark I2. 2 After the first reflow process do not use water to remove residual flux water can be used in the second process Peak temperature of package 215 C or lower VP15 107 2 Reflow time 40 seconds or less 200 C or higher Number of reflow processes MAX 2 Exposure limit 7 daysNote 10 hours pre baking is required at 125 C afterwards Cautions 1 After the first reflow process cool the package down to room tempera ture then start the second reflow process 2 After the first reflow process do not use water to remove residual flux water can be used in the second process Partial heating Terminal temperature 300 C or lower method Time 3 seconds or less Per side of the package Note Exposure limit before soldering after dry pack package is opened Storage conditions 25 C and relative humidity at 65 or less Caution Do not apply more than one soldering method at any one time except for Partial heating method 38 _ NEC 254260 424260 uPD42S4260LE 424260LE 40 pin plastic SOJ 400 mil Infrared ray Peak temperature of package surface 235 C or lower IR35 207 2 reflow Reflow time 30 seconds or less 210 C or higher Number of reflow processes MAX 2 Exposure limit 7 daysNote 20 hours pre baking is required at 125 C afterwards Cautions 1 After the first reflow process cool the package down to room tempera ture then start the second reflow process
3. 2 After the first reflow process do not use water to remove residual flux water can be used in the second process Peak temperature of package 215 C or lower VP15 207 2 Reflow time 40 seconds or less 200 C or higher Number of reflow processes MAX 2 Exposure limit 7 daysNote 20 hours pre baking is required at 125 C afterwards Cautions 1 After the first reflow process cool the package down to room tempera ture then start the second reflow process 2 After the first reflow process do not use water to remove residual flux water can be used in the second process Partial heating Terminal temperature 300 C or lower method Time 3 seconds or less Per side of the package Note Exposure limit before soldering after dry pack package is opened Storage conditions 25 C and relative humidity at 65 or less Caution Do not apply more than one soldering method at any one time except for Partial heating method 39
4. tcwp gt lt lt gt lt QU Remark Inthe fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 30 M 4PD42S4260 424200 Fast Page Mode Byte Read Modify Write Cycle das _ Mi RA ViL iPRwc xw UCAS Vi LCAS ViL NEL tRAL tasr RAH tasc tasc ps 00009 Vi tacp tewo 00 eur 7 tec EJ tawo two U I O L I O U I O L I O Remarks 1 In the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 2 This cycle can be used to control either UCAS or LCAS only Or it can be used to control UCAS or LCAS simultaneously or at random 31 A P 4PD42S4260 424200 EC 4254260 424260 CAS Before RAS Self Refresh Cycle Only for the mPD42S4260 Remark Address WE OE Don t care L I O I O Hi Z Cautions on Use of CAS Before RAS Self Refresh CAS before RAS self refresh
5. centerline is located within 0 12 mm 0 005 inch of 0 2 0 008 its true position T P at maximum material condition B 26 297935 1 035 9014 10 16 0 400 D 11 18 0 2 0 440 0 008 0 006 E 1 08 0 15 0 043 0 009 F 0 7 0 028 G 3 5 0 2 0 138 0 008 0 009 H 2 4 0 2 0 094 0 008 I 0 8 MIN 0 031 MIN J 2 6 0 102 K 1 27 T P 0 050 T P 0 004 M 0 40 0 10 0 016 0 005 0 12 0 005 P 9 40 0 20 0 370 0 008 Q 0 15 0 006 ili R0 85 R0 033 0 10 0 004 U 0 202005 0 00875 005 P40LE 400A 2 37 ___ ______ o J PD4284260 424200 Recommended Soldering Conditions The following conditions see tables below and next page must be met when soldering 4254260 424260 For more details refer to our document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL IEI 1207 Please consult with our sales offices in case other soldering process is used or in case the soldering is done under different conditions Types of Surface Mount Device uPD4284260G5 424260G5 44 pin plastic TSOP II 400 mil Infrared ray Peak temperature of package surface 235 C or lower IR35 107 2 reflow Reflow time 30 seconds or less 210 C or higher Number of reflow processes MAX 2 Exposure limit 7 daysNote 10 hours pre baking is required at 125 C afterwards Cautions 1 After the first reflow process cool the package down to room tempera ture then start the second reflow process
6. lt V lt 0 2 V lo 2 0 mA Input leakage current V 0 to 5 5 V All other pins not under test 0 V Output leakage current Vo 0 to 5 5 V Output is disabled Hi Z High level output voltage lo 2 5 mA Low level output voltage Notes 1 lo 2 1 mA 1 1 1 4 lccs and Icce depend on cycle rates tnc and trc 2 Specified values are obtained with outputs unloaded 3 and 1 03 are measured assuming that address can be changed once less during RAS lt Vit MAX and CAS gt Vin 4 is measured assuming that all column address inputs are held at either high or low 5 is measured assuming that all column address inputs are switched only once during each fast page cycle UPD42S4260 424260 a 1 Input timing specification 2 Output timing specification ViH 2 4 V VoH MIN 2 2 4 V Vol 0 4 V max 0 8 V lt 4 die tr 5 ns tr 5 ns 3 Output load condition tRAc 60 ns tRAc 70 ns trac 80 ns MIN MIN 5 MIN Parameter Symbol Read Write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width RAS hold time CAS hold time RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address setup time Row address hold t
7. DATA SHEET NEC ee MOS INTEGRATED CIRCUIT uPD42S4260 424260 4M BIT DYNAMIC RAM 256 K WORD BY 16 BIT FAST PAGE MODE BYTE READ WRITE MODE Description The 4254260 424260 are 262 144 words by 16 bits dynamic CMOS RAMs The fast page mode and byte read write mode capability realize high speed access and low power consumption Besides the uPD4284260 can execute CAS before RAS self refresh These are packaged in 44 pin plastic TSOP II and 40 pin plastic SOJ Features 262 144 words by 16 bits organization Single 5 0 V 10 96 power supply Fast access and cycle time 1 04284260 60 424260 60 880 0 mW 110 ns 1 04284260 70 424260 70 880 0 mW 130 ns 1 04284260 80 424260 80 797 5 mW 150 ns The uPD42S4260 can execute CAS before RAS self refresh 1 04284260 512 cycles 128 ms CAS before RAS refresh 0 825 mW CAS before RAS refresh CMOS level input RAS only refresh Hidden refresh uPD424260 512 cycles 8 ms CAS before RAS refresh 5 5 mW RAS only refresh CMOS level input Hidden refresh Multiplexed address inputs Row address AO to A8 Column address AO to 8 The information in this document is subject to change without notice Document No M11089EJ5VODSU1 4PD4284260 4242000 Ordering Information Part number Access time MAX Package Refresh NEC UPD42S4260 424260 Pin Configurations Markin
8. Refresh Cycle tasr lt gt Yo XX WE OE Don t care LIO U I O Hi Z 33 b M UPD42S4260 424260 a Hidden Refresh Cycle Read m Data Out 34 UP UPD42S4260 424260 a Hidden Refresh Cycle Write Address Remark OE Don t care 35 UPD42S4260 424260 EC PD42S4260 424260 Package Drawings 44 PIN PLASTIC 400 mil detail of lead end H NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0 13 mm 0 005 inch of A 18 63 MAX 0 734 its true position T P at maximum material condition B 0 93 MAX 0 037 MAX C 0 8 T P 0 031 T P 0 08 D 0 3210 08 0 013 0 003 E 0 1 0 05 0 004 0 002 b 1 2 MAX 0 048 MAX G 0 97 0 038 H 11 76 0 2 0 463 0 008 1 10 16 0 1 0 400 0 004 0 8 0 2 OS i eE 0 025 K 0 14570 015 0 006 0 001 L 0 5 0 1 0 020 0 004 M 0 13 0 005 N 0 10 0 004 7 7 sT S44G5 80 7JF4 36 UPD42S4260 424260 E PD42S4260 424260 40 PLASTIC SOJ 400 mil CHEM MILLIMETERS Each lead
9. can be used independently when used in combination with distributed CAS before RAS long refresh However when used in combination with burst CAS before RAS long refresh or with long RAS only refresh both distributed and burst the following cautions must be observed 1 2 3 Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination please perform CAS before RAS refresh 512 times within an 8 ms interval just before and after setting CAS before RAS self refresh Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh When CAS before RAS self refresh and RAS only refresh are used in combination please perform RAS only refresh 512 times within an 8 ms interval just before and after setting CAS before RAS self refresh If trass min is not satisfied at the beginning of CAS before RAS self refresh cycles tras lt 100 us CAS before RAS refresh cycles will be executed one time If 10 us lt tras lt 100 us RAS precharge time for CAS before RAS self refresh tres is applied And refresh cycles 512 128 ms should be met For details please refer to How to use DRAM User s Manual 32 o UPD42S4260 424260 a CAS Before RAS Refresh Cycle UCAS LCAS Vi Remark Address WE OE Don t L I O U I O Hi Z RAS Only
10. ddress lead time referenced to RAS 35 40 Read command setup time Read command hold time referenced to RAS Le EM a 2 Read command hold time referenced to CAS esi cod 2 Output buffer turn off delay time from CAS ON 15 o 15 20 ns 3 Notes 1 For read cycles access time is defined as follows trap lt trap and lt tRcD MAX trap tRAD MAX and tRcb lt MAX MAX trap MAX trop gt trop MAX MAX trop tRAD MAX and are specified as reference points only they are not restrictive operating parameters They are used to determine which access time trac taa or tcac is to be used for finding out when output data will be available Therefore the input conditions trap gt trap and tRcp gt trep will not cause any operation problems 2 Either tRcH Or MIN should be met in read cycles 3 torF MAx and toez max define the time when the output achieves the condition of Hi Z and is not referenced to or VoL _ NEC 4PD4284260 424200 Write Cycle Notes 1 twp min is applied to late write cycles or read modify write cycles In early write cycles twcH min should be met 2 If twcs gt twcs min the cycle is an early write cycle and the data out will remain Hi Z thr
11. e CAS hold time CAS before RAS refresh RAS precharge CAS hold time RAS pulse width CAS before RAS self refresh cycle RAS precharge time CAS before RAS self refresh cycle CAS hold time CAS before RAS self refresh cycle WE hold time hidden refresh cycle Note 1 This specification is applied only to the 4254260 11 _ O NEC UPD42S4260 424260 0 Read Cycle Address iRcH 12 UPD42S4260 424260 a Upper Byte Read Cycle ANIA Remark Hi Z 13 UPD42S4260 424260 a Lower Byte Read Cycle Address Remark U Hi Z 14 d 4PD4284260 424200 Early Write Cycle 0000000000000 v etti Remark OE Don t care 15 P uPD42S4260 424260 a Upper Byte Early Write Cycle Remark OE LIO Don t care 16 b 4 PD42S4260 424200 Lower Byte Early Write Cycle Address Remark OE U I O Don t care 17 _ NEC o UPD42S4260 424260 Late Write Cycle
12. g Side 44 pin Plastic TSOP Il 40 pin Plastic SOJ 400 mil 400 mil to A8 Address Inputs 1 01 to 016 Data Inputs Outputs RAS Row Address Strobe UCAS Column Address Strobe upper LCAS Column Address Strobe lower WE Write Enable OE Output Enable Vcc Power Supply GND Ground NC No Connection _ NEC 04254260 424260 Block Diagram Lower Byte Upper Byte ___ ___ 9o uPD4254260 424260 The uPD42S4260 424260 have input pins RAS CASNete WE OE 0 to A8 and input output pins 1 01 to 1 016 name RAS Row address strobe Input Output Function RAS activates the sense amplifier by latching a row address to A8 and selecting a corresponding word line It refreshes memory cell array of one line selected by the row address AO to A8 It also selects the following function CAS before RAS refresh CAS Column address strobe CAS activates data input output circuit by latching column address AO to A8 and select ing a digit line connected with the sense amplifier A0 to A8 Address input 9 bit address bus Input total 18 bit of address signal upper 9 bit and lower 9 bit in sequence address multiplex method Therefore one word 16 bit is selected from 262 144 word by 16 bit memory cell array In actual operation latch row address by specifying row address and activating RAS T
13. hen switch the address bus to column address and activate CAS Each address is taken into the device when RAS and CAS are activated Therefore the address input setup time tasr tasc and hold time trav are specified for the activation of RAS and CAS WE Write enable Write control signal Write operation is executed by activating RAS CAS and WE OE Output enable Read control signal Read operation can be executed by activating RAS CAS and OE If WE is activated during read operation OE is to be ineffective in the device Therefore read operation cannot be executed to 1 016 Data input output Input Output 16 bit data bus to 1 016 are used to input output data Note CAS means UCAS and LCAS O N amp C PD42S4260 424200 Electrical Specifications CAS means UCAS and LCAS All voltages are referenced to GND After power up Vcc gt Vcc wait more than 100 RAS CAS inactive and then execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit Absolute Maximum Ratings Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended per
14. ime Column address setup time Column address hold time OE lead time referenced to RAS CAS to data setup time OE to data setup time OE to data delay time Masked byte write hold time referenced to RAS Transition time rise and fall Refresh time 42 4260 uPD424260 _ NEC PD4284260 424200 Notes 1 In CAS before RAS refresh cycles tras MAX is 100 us If 10 us lt tras lt 100 us RAS precharge time for CAS before RAS self refresh tres is applied 2 For read cycles access time is defined as follows trap lt trap MAX and lt trcp MAX trap tRAD MAX and tren lt MAX MAX trap MAX RCD gt tRCD tRcD tcac tRAD MAX and are specified as reference points only they are not restrictive operating parameters They are used to determine which access time trac taa or tcac is to be used for finding out when output data will be available Therefore the input conditions trap gt tRAD and tRcD gt trep max will not cause any operation problems 3 requirement is applied to RAS CAS cycles 4 This specification is applied only to the uPD42S4260 Read Cycle Access time from RAS Access time from CAS Access time from column address Access time from OE Column a
15. iods may affect device reliability Recommended Operating Conditions Capacitance Ta 25 C f 1 MHz Parameter Operating current UPD42S4260 4242600 Symbol Test condition RAS CAS cycling tRAc 60 ns MIN DAR MAX tnc tac min lo 0 MA trac 70 ns trac 80 ns Unit Notes Standby current uPD42S4260 uPD424260 RAS CAS gt VH mn lo 0 mA RAS CAS gt Voc 0 2 V lo 0 mA RAS CAS gt mn lo 0 mA RAS CAS gt Voc 0 2 V lo 0 mA RAS only refresh current RAS cycling CAS gt Vin tRAc 60 ns trc MIN lo 0 MA mes 70 me trac 80 ns Operating current Fast page mode RAS lt CAS cycling trac 60 ns tec tPc MIN lo 0 mA mes 70 ns trac 80 ns CAS before RAS refresh current RAS cycling trac 60 ns trc MIN lo 0 MA EOS trac 80 ns CAS before RAS long refresh current 512 cycles 128 ms only for the uPD42S4260 CAS before RAS refresh _ nc 250 0 us RAS CAS Voc 0 2 V lt OV Vi lt 0 2 V tRAs lt 200 ns Standby RAS CAS gt Vcc 0 2 V Address or Vit WE OE ViH lo 2 0 mA tras 1 us Self refresh current CAS before RAS self refresh only for the 1 04254260 RAS CAS trass 5 ms Vcc 0 2 V max 0 V
16. n the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 24 _ NEC UPD42S4260 424260 Fast Page Mode Byte Read Cycle tRHCP Address In the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 2 This cycle can be used to control either UCAS or LCAS only Or it can be used to control UCAS or LCAS simultaneously or at random Remarks 1 25 M 9 43 uPD42S4260 424260 Fast Page Mode Early Write Cycle tRHcP Address Remarks 1 OE Don t care 2 In the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 26 4PD42S4260 424200 Fast Page Mode Byte Early Write Cycle RHCP Address ain Remarks 1 OE Don t care 2 In the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 3 This cycle can be used to control either UCAS or LCAS only Or it can be used to c
17. ontrol UCAS or LCAS simultaneously or at random 27 UPD42S4260 424260 a Fast Page Mode Late Write Cycle I mm N tasc I tasc E Address MAE XX Row XX co XXX co ca MES 18 5 tres twp lt lt lt lt tcwL tow lt gt lt n 18 ot CD omar 2 lt Remark the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 28 NEC e 4JPD42S4260 424200 a Fast Page Mode Byte Late Write Cycle RHCP tos tos toeD OXIA AA Remarks 1 In the fast page mode read write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle 2 This cycle can be used to control either UCAS or LCAS only Or it can be used to control UCAS or LCAS simultaneously or at random 29 JJPD42S4260 424200 Fast Page Mode Read Modify Write Cycle tas lt gt sies em tRwD 5 icPWwD tcpwp__ tawo lawo E p tcwp F
18. ough the entire cycle 3 tps and min are referenced to the CAS falling edge in early write cycles In late write cycles and read modify write cycles they are referenced to the WE falling edge Read Modify Write Cycle Note 1 If twcs gt twcs the cycle is an early write cycle and the data out will remain Hi Z through the entire cycle If tRwp gt tRWD tcwD gt MIN tawD gt tawo and tcpwo gt tcPwb the cycle is a read modify write cycle and the data out will contain data read from the selected cell If neither of the above conditions is met the state of the data out is indeterminate 10 _ NEC PD4284260 424200 Fast Page Mode Fast page mode cycle time Access time from CAS precharge 35 40 45 RAS pulse width 125 000 125 000 125 000 CAS precharge time RAS hold time from CAS precharge tRHCP Read modify write cycle time CAS precharge to WE delay time Note 1 If twcs gt twcs the cycle is an early write cycle and the data out will remain Hi Z through the entire cycle If tawp gt tRWD MIN tcwD gt tcwD MIN tAWD gt tawo and tcPwp gt tcPWD MIN the cycle is a read modify write cycle and the data out will contain data read from the selected cell If neither of the above conditions is met the state of the data out is indeterminate Refresh Cycle CAS setup tim
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NEC_uPD424260LE_RAM_..