TS68483A Datasheet - PDF Format - Click Here
Contents
1. VI TIMING DIAGRAM VI 1 Microprocessor Interface TS68483 has an eight bit address bus and a sixteen bit data bus Little external logic is needed to adapt bus control signals from most of the common multiplexed or non multiplexed bus microprocessors UNMUX MODE One Block through Page Mode SPARED AREA m 68483 22 EPS Microprocessor Interface Timing A 0 7 D 0 15 AE DS CS R W Voc 5 0V 596 TA TL to TH CL 100pF on D 0 15 Reference levels Vu 0 8V and Vin 2V on all inputs Vor 0 4V and Von 2 4V on all outputs Indent Number Address Set up Time from CS Parameter Data Strobe Width high AS Set up Time from CS DS Inactive to High Impedance State read cycle 10 R W Set up Time from DS 9 DS Width low write cycle 80 B 11 Data in Set up Time from DS active write cycle 10 z 12 Data in Hold Time from DS Inactive write cycle 15 ns 3 21 30 SGS THOMSON d TICROELECTRONIGS TS68483A Figure 21 Read Cycle AS MPU DATA OUT D 0 15 Figure 22 Write Cycle RW DATA IN D 0 15 22 30 GS THOMSON SLA SES THOMSON 68483 23 EPS 68483 24 EPS TS68483A MUX MODE se 8 Microprocessor Interface Timing A 0 7 D 0 15 AE DS CS R W Voc 2 5 0V 596 TA TL to TH CC 10 pF on D 0 15 Reference Levels Vi 0 8V and Viu 2V on All Inputs Vor 0 4V and Vou 2 4V on All Outputs 18 Data in S2. 8 Figure 18 One Block Two Z ADM 8 15 Figure 19 ADM 0 7 TO T1 Page mode A MEMORY WORD V 3 2 MASKING PLANES Masking planes are very useful for general purpose area filling or clipping It may be practical to use one or two planes smaller than the color bit plane if they cyclically cover a frame buffer The masking planes must be in bank3 V 3 3 OBJECTS AND CHARACTERS Objects may be located in unused parts of the frame buffer Character generators can be implemented in any plane of any bank They can also be implemented in ROM In this case plane Z 1 or 3 offer relaxed 20 30 access time requirements V 4 Examples Figure 20 gives the schematic for a 512 x 384 non interlaced application A CLK signal in the 15 to 18 MHz range should produce a 50 to 60Hz refresh rate The on chip video shift registers may be used if no more than four bits per pixel are required One 64 K x 8 memory block may be implemented using either eight 64 K x 1 or two 64 K x 4 components One memory block holds two 512 x 384 color bit planes SGS THOMSON TA MICROELECTRONICS 68483 19 EPS 68483 20 EPS 68483 21 EPS TS68483A Figure 20 Memory Organization for 512 x 384 Application CYCLE CONTROLLER BANK ENABLE ADM 8 15 B 0 1 Y 0 2 ADM 0 7 64K x 8 bp FERE E late 74 64K x 8 64K x 8 384 64K x 8 MEMORY BLOCK
3. 1 7 A 1 7 ft UDS or LDS TS68008 TS68483 D 8 15 Figure 15 Interface with 8086 8008 MPU 8086 TS68483 AD 8 15 D 8 15 AD 0 7 14 30 SLL S O n GS THOMSON SLA SES THOMSON 68483 16 EPS 68483 17 EPS III 2 Hardware Recommendations see Figures 21 22 23 and 24 AO PIN 1 When using a 16 bit data bus the A0 input pin must be grounded No single byte access can be performed 2 In order to conform with the high byte low byte on chip packing the AO input pin must be inverted when using an 8 bit bus Intel type microprocessor 8088 for example A 1 7 D 0 7 D 8 15 pins 1 With any 8 bit data bus the D 0 7 and D 8 15 pins must be paired in order to demultiplex the low order data bytes and the high order data bytes 2 When using address data multiplexed bus the D 0 7 pins are paired with A 0 7 in order to demultiplex data from address Table 3 Command Execution Condition Execution Condition TS68483A AE DS R W CS See pin description Ill 3 SOFTWARE RECOMMENDATIONS 1 The CONFIGURATION register R10 must be first initialized The BW 15 flag is interpreted by the bus interface to recognize an 8 bit 16 bit data bus The MB and BW 15 flags are used to decide when to initiate a command execution 2 Each register byte has 4 addresses in the microprocessor memory map These 4 addresses differ only by A 6 7 This scheme allows a 68008 progra
4. JECT may then be printed in another location by use of a PRINT OBJECT command PEN This is the pattern which is repeatedly drawn along the coordinates definedby either a LINE or an ARC command The PEN may be a DOT single pel a CHARAC TER or an OBJECT THOMSON 1 1 590 SGS YA TICROELECTRONIGS TS68483A Figure 2 Cyclical Drawing Coordinates to Display Memory Mapping THE MEMORY WORD I COMMANDS Il 1 Introduction The command set is strongly organized in five subset or command types DRAWING COMMANDS LINEAR line arc AREA rectangle trapezium polygon polyarc PRINT CELL print character print object ACCESS COMMANDS CONTROL COMMANDS move cursor abort The commands are parametered this means that any command can be executed with options freely selected out of a given option set This option set is common for any command of a given type For example any drawing command may be parame tered for destination mask bit use The command code also defines the command type and its parameters A command is completely defined when a value has been set for each of its 6 30 LONG PELS sort PELS 4 BANKS OF 4 BIT PLANES EACH arguments These arguments are the geometric arguments given in the drawing coordinate system for every drawing command They are automatically mapped into the destina tion frame buffer the parametric values are the values required by the sel
5. This input selects the TS68483 registers for the current bus cycle A low level corresponds to an asserted chip select In multiplexed mode this input is strobed by AE Interrupt Request This active low open drain output acts to interrupt the microprocessor ADM VO Address Data Memory These multiplexed pins act as address and data bus for display 0 15 memory interface CYS O Memory Cycle Start The falling edge of this output indicates the beginning of a memory Ss BLEE O Memory Address Bank Number Memory Cycle Status cycle These outputs provide the least significant bits of the Y logical address These outputs provide the number of the memory bank to be accessed during the current memory cycle These outputs indicate the nature of the current memory cycle Read Write Refresh Display Video Shift Register Outputs These four pins correspond to the outputs of the internal video shift registers PC HS Phase Comparator This output can be programmed to provide either the phase comparator Horizontal Sync output or the horizontal sync signal HVSNS Composite or Vertical This output can be programmed to provide either the composite sync Sync signal or the vertical sync signal SYNC IN External Sync Input This input receives an external composite sync signal to synchronize TS68483 This input must be grounded if not used BLK O Blanking This output provides th
6. Yd and clipped at the dXd dYd dimensions When dXd dYd is much larger than DXs DYs the command may be parametered for repeatdrawing These commands may also be parametered for destination mask use Further more the PRINT OBJECT command may be parametered for source mask use These commands have a wide range of applica tions text drawing area tiling print or move ob jects scale and move viewports 12 30 68483 12 EPS Note an underlined cell is drawn when the MSB of R23 is set 1 5 4 ACCESS COMMANDS LOAD VIEWPORT Xs Ys DXs DYs SAVE VIEWPORT Xs Ys DXs DYs MODIFY VIEWPORT Xs Ys DXs DYs These commands provide sequential access to a viewport in a frame buffer from the microprocessor data base Data are transferred to from the display memory word sequentially The R14 to R17 registers are used as a two mem ory word FIFO memory word is 8 short pels i e 4 bytes The source pointer R20 R23 is used to address the viewport for all access commands When long pels are used the command must be executed once more when the bank number in R20 has been updated 11 5 5 COMMAND EXECUTION Each on chip 16 bit register has four addresses One address is used for plain read or write The other addresses are used to initiate command exe cution automatically on completion of the register access This scheme allows the command code and its arguments to be loaded or modified in any other
7. 1994 SGS THOMSON Microelectronics All Rights Reserved Purchase of PC Components of SGS THOMSON Microelectronics conveys a license under the Philips PC Patent Rights to use these components in a C system is granted provided that the system conforms to the C Standard Specifications as defined by Philips SGS THOMSON Microelectronics GROUP OF COMPANIES Australia Brazil China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U S A out yg G5 THOMSON MICROELECTRONICS PMPLCC68 EPS PLCC68 TBL
8. 3 Display Process The Video Timing Generator allocates memory cycles to the Display Processor in order to read the Display Viewport from memory The Display View port upper left corner address is programmable through DIB YOR and XOR The display viewport dimensions are related to the display interval of DWY lines by DWX cycles per field GS TH YA MICROELECTRONICS 68483 18 EPS IV 3 1 Y ADDRESSES When INE 0 the fields are not interlaced The Y Display Viewport address is initialized with YOR at the first displayable line then decremented by 1 at each scan line The Display Viewport is thus DWY pel high When INE 1 the fields are interlaced The Y Display Viewport address is initialized as shown in the table below It is then decremented by two at each scan line The viewport is thus 2 x DWY pel high ELLE Odd Field Yor Even Yor 1 Yor Odd Yor 1 Y display Viewport address initialization when INE 1 IV 3 2 X ADDRESSES AND MODX FLAGS The X Display Viewport address is initialized with XOR at the first displayable cycle of each display able line It is then incremented at each subsequent cycle according to MODX flags Video Shift Memory MODXO XINGR Register Cycle Type 0 1 Internal Read 1 1 External Dummy Read External D E Head ar ma internal mode the Display Viewport is 8 DWX pel wide The on chip video shift register are used In Dummy read the memory is read but the on chip vi
9. B 0 1 CYF 0 1 cvs a Y 0 2 E 2T ADM 0 15 WRITE CYCLE ADM 0 15 READ CYCLE ADM 0 15 DUMMY READ CYCLE DISPLAY ADM 0 7 FLOATING CYCLE ADM 8 15 ch kur SS D EVEN Z THOMSON MICROELECTRONICS O EVEN 2 D ODD Z D CEB queen D ODD n 25 30 68483 13 TBL 68483 27 EPS TS68483A VI 3 Video Interface PO P1 P2 P3 BLK HVS VS PC HS Vcc 5 0V 5 96 TA TL to TH CLK duty cycle 50 Reference levels Vu 0 8V and VH 2V Vor 0 4V and Von 2 4V CL 50pF Indent Number Parameter TCLK CLK Period CLK High Pulse Width Output Delay from CLK Rising Edge CLK Low Pulse Width Output Hold Time Figure 26 Timing Diagram Figure 27 Synchronization Signal Outputs i 7T Horizontal Sync MARGN V RGN BKX MF PX i DWA vs 25LINES 25LINES Non Interlaced Example HyS Uu l IL IL TUI skv FPy owv ePy 525 NHVS 1 EVEN FIELD BKY FPY DWY BPY LINES amp EVEN FIELD is LIL 0 Htettaoed NBLK 1 i Interlaced Sieg BPY Sei BKY 25LINES 25LINES Example BKY FPY DWY BPY UULILTU U U ees Lines 26 30 SGS THOMSON TA MICROELECTRONICS 68483 14 TBL 68483 28 EPS 68483 29 EPS VII TABLES VII 1 Register Map and Command Table Figure 28 COMMAND
10. TS68483A SX fi 1 SY Odd Bank Even Bank I L AD PPEDPPEDPPEDPPEDPPEDPPEDEPEDPPEDPPELEPEDEPEDEPELEPEDEPELEPEDEPEDEPEDEPEDPPEDEPELEPEPEVEPEDEPEDPPED Ge Odd Bank Even Bank putent Pe PH centre ERE PRU TELE PPT PTE PPT PEHA PL PTE AHA EA a TEXLIN R XOR i L L I PIG 0 E DIB1 DIBO MARGIN COLOR l I 1 I GE Ge GENEE ER ES Le YOR PPPPAVOPOLAVOLOPOPOV VO bereits cen pure rr ep PPP preter Ge pure ey FPX BKX f RA rer error MODX1 KE ODXO veter revertere e VIEWS KA pirra 2222 DWY t MB VSIE HSIE NBLK N a B T NHVS 1 L L L L L GE NPC SYNC FERSKE SEES AE SES ELERS EE Ge DEE OG ERSE 2 GE GENEE GE STATUS EE CEET Ge GENEE GE E e Bd DEST POINTER tre ve Pelr OPOLOVOPOVOVOVOPOVOLOVOLOVO POLO Leet TIE rer RE renn parerent Y eene N N arg a aa und ard ol olo Solo A g u o o EEN EEN Ee Leet EEN EE U N GA U N N efel SOURCE POINTER he js ky 655 Don t care Used or not according to the command 27 THOMSON gt MICROELECTRONICS 68483 30 EPS TS68483A VII 2 Command Table Sd3 1 8v89 0 431111080 yo penu siJossnd oul L7 1331 0 NMG dn umop pan st Josand eu NMA pesn
11. incremented according to MODX This Display viewport address is allowed to ad dress the memory for DWX cycles in only one line out of nine for refresh purposes When VRE 1 or DPD 1 any line is processed as anon displayable line with respect to the refresh process IV 5 Configuration and External Synchroniza tion The R10 register holds eight configuration flags Six of these flags are dedicated to the Video Timing Generator SSP this flag selects the synchronization output pin configuration NPC NHVS NBLK these three flags invert the PC HS HVS VS and BLK outputs respectively Ex When NBLK 1 blankingis active high The SYNC IN input pin provides an external com posite synchronization signal input from which a Vertical Sync In VSI signal is extracted The SYNC IN signal is sampled on chip at CLK fre quency Its rising sampled edge is comparedto the leading edge of HS A PC comparison signal is externally available see SSP and NPC flags VSIE this flag enables VSI to reset the internal line count HSIE this flag enablesthe rising edge of SYNC IN to actdirectly on the Video Timing Generator When the leading edge of HS does not match at 1 clock period a rising edge of SYNC IN one extended cycle is performed nine clock periods instead of eight Output Pins PC HS HVS VS Flag ez SGS THOMSON ue MICROELECTRONICS TS68483A Table 4 A ED Number of Display lines per Fie
12. which is 8 periods of the CLK input signal SGS THOMSON 9 Ais leuia These two parameters are internally programmed Horizontal sync pulse duration 7 cycles Vertical sync pulse duration 2 5 lines IV 2 2 BLANKING INTERVAL The blanking interval starts at the leading edge of the vertical sync pulse Vertical blanking interval actual duration is 2 5 lines more than the programmed value two cycles beforethe leading edge of the horizon tal sync pulse The actual horizontal blanking interval duration is 3 cycles more than the pro grammed value Note During the programmed blanking interval the video output pins P 0 3 are forced low IV 2 3 PORCH AND MARGIN COLOR During the porch interval the programmable mar gin coloris displayed on the P 0 3 outputs The display process may be disabled by setting DPD flag This will be interpreted as a porch exten sion Note By process the value of the block porch must be strictly above O 15 30 68483 06 TBL TS68483A IV 2 4 MEMORY TIME SHARING see Figure 16 Figure 16 Video Programming HORIZONTAL BLKX 2T sa 1T FPX FRONT Horizontal Minimum ar BKX PORCH Number of Cycles i BLANKING MARGIN The Video Timing Generator allocates memory cycles to either the display process RAM refresh or command execution In this respect the scan lines per field are split between the DWY display able lines When VRE 0 Video RAMs are no
13. An incremental line drawing command for exam ple may be executed again and again with succes sive incremental dimensions and whithout need to reload the command code itself As soon as a command execution is started the FREE bit is cleared in the STATUS register Thisbit is automatically set when the execution is com pleted The commands are generally executed only during retrace intervals However full time execution is possible when either the display is disabled or video RAM components are used 11 5 6 STATUS REGISTER see Figure 12 This register holds four read only status bits FREE this status bitis set when no execution is pending VS vertical synchronization state GEM this status bit is set when the FIFO memory wordis inacessible to the microprocessor during a viewport transfer NSEM this status bit is set when the FIFO memory word is accessible to the microprocessor during a viewport transfer Each of these status bits is maskable The masked status bits are NORed to the IRQ output pin SGS THOMSON YZ MICROELECTRONICS Figure 12 Status Register 15 14 13 12 11 10 9 8 STATUS REGISTER R12 MASK NSEM NSEM MASK SEM SEM MASK VS vs je MASK FREE READONLY Ill MCROPROCESSOR INTERFACE 11 1 Introduction The TS68483is directly compatible with any popu Figure 13 On chip Address and Byte Packing 68483 14 EPS TS68483A lar 8 or 16 bithost microprocessor e
14. Art scies FULLY PROGRAMMABLE TIMING GENER ATOR ALPHANUMERIC AND GRAPHIC DRAWING CAPABILITY EASY TO USE AND POWERFUL COMMAND SET VECTOR ARC CIRCLE WITH DOT OR PEN CONCEPT AND PROGRAMMABLE LINE STYLE FLEXIBLE AREA FILL COMMAND WITH TILING PATTERN VERY FAST BLOCK MOVE OPERATION CHARACTER DRAWING COMMAND ANY SIZE AND FONTS AVAILABLE LARGE FRAME BUFFER ADDRESSING SPACE 8 megabytes UP TO 16 PLANES OF 2048 x 2048 UP TO 256 COLOR CAPABILITIES MASK BIT PLANES FOR GENERAL CLIP PING PURPOSE FRAME BUFFER CAN BE BUILT WITH STANDARD 64 K OR 256 K DRAM OR DUAL PORT MEMORIES video RAM EXTERNAL SYNCHRONIZATION CAPABIL ITY ON CHIP VIDEO SHIFT REGISTERS FOR DOT RATE UP TO 18 MEGADOTS S 8 OR 16 BIT BUS INTERFACE COMPATIBLE WITH MARKET STANDARD MICROPROC ESSORS HMOS 2 TECHNOLOGY 68 PIN PLCC PACKAGE FOR DETAILED INFORMATION REFER TO TS68483 USER S MANUAL DESCRIPTION The TS68483 is an advanced color graphic proc essor that drastically reduces the CPU software overhead for all graphic tasks in medium and high range graphic applications such as business and personal computer industrial monitoring system and CAD systems September 1993 TS68483A HMOS2 ADVANCED GRAPHIC AND ALPHANUMERIC CONTROLLER PLCC68 Plastic Chip Carrier ORDER CODE TS68483A PIN CONNECTIONS 1 30 68483 01 EPS TS68483A PIN DESCRIPTION Name Type Function MICROPROCESS
15. G PA PXG PX X X X X X X X X X NAYS ds NAG 0 0 ololo na annoa 1 Jed 4001 LINI Noiusoduosuno IECH eeu rex ozy z1a 918 leg rg 614 slu eru eu eu t8 OH o l z v slo z ve m AMLLNOLLNOJX3 CONVININGOO NA SHALNIOd SININNDHV SHaALAWVHVd 3000 o be co N Figure 29 Typical Application HOST MICROPROCESSOR SYSTEM MEMORY TS68483 CRT CONTROLLER DISPLAY MEMORY INTERFACE DISPLAY MEMORY yg LLI o Lit tc c Ow z S GS THOMSON MICROELECTRONICS MONITOR TS68483A 29 30 68483 32 EPS TS68483A PACKAGE MECHANICAL DATA 68 PINS PLASTIC CHIP CARRIER 3 Millimeters Inches Dimensions Max 0 995 0 958 0 200 0 930 0 004 Information furnished is believed to be accurate and reliable However SGS THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No licence is granted by implication or otherwise under any patent or patent rights of SGS THOMSON Microelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS THOMSON Microelectronics
16. INEAR DRAWING command If a pen is used these signs are then irrelevant to the pen drawing The pen is mapped with positive increment values 11 30 MICROELECTRONICS 68483 12 EPS TS68483A I 5 Command Set Overwiew Figure 11 11 5 1 LINEAR DRAWING LINE Xd Yd DXd DYd ARC Xd Yd DXd DYd RAD STOP The curve may be drawn with any pen and with any linear texture register R3 For each set of com puted coordinates R3 is right rotated and the pen is printed when the shifted bit is set 11 5 2 AREA DRAWING RECT Xd Yd DXd DYd TRAPEZIUM Xd Yd DXd DYd X1 POLYGON Xd Yd DXd DYd POLYARC Xd Yd DXd DYd RAD STOP Either RECTor TRAPEZIUM allows to draw directly all the pels inside the boundary Any other closed boundaries may be filled by a 3 step process 1 The mask bits inside a boundary box must be reset by a RECT command 2 Asequenceof mixed POLYGON and POLYARC commands describing the closed boundary sets the mask bits of the pels inside this boundary 3 This area may then be painted by a RECTANGLE command defined for a bounding box with destination masking It may also be tiled by use of a PRINT CELL command Note themask bit of any pel lying on the boundary itself is not guaranteed to be set by step 2 11 5 3 PRINT CELL COMMANDS PRINT CELL Xd Yd DXd DYd Xs Ys DXs DYs The cell addressed by Xs Ys DXs DYs is scaled then printed at location Xd
17. MU 1 this active set is further reduced by the masking mechanism to only these destina tion pels with a bit mask set The active destination pels are then modified ac cording to two elementary transforms coded in RO COLOR TRANSFORM The color value C of each active pel is modified according to one color transform selected out of four 00 printed in CO C CO 01 printedin C1 C C1 10 printed in transparent Ce C 11 complemented Ce C This yields to a reversible marker mode MASK BIT TRANSFORM The destination mask bit of each active pel is modified according to one mask transform selected out of four 00 reset bit mask M 0 01 set bit mask M 1 10 no modification M M _ 11 complement bit mask M M This scheme allows the color bits and the mask bit of any pelbelonging to the active set to be modified independently The color transform is performed first 11 4 4 BICHROME MODE APRINT CHARACTER command is more complex because it involves two different active sets FOREGROUND and BACK GROUND The FOREGROUND is that set of destination pels printed from set elements in the character cell The BACKGROUND is made of all the remaining pels belonging to the destination window When DMU 1 the FOREGROUND and BACK GROUND are further reduced by the destination masking mechanism see Figure 8 A bichrome drawing mode is definedby 4 elemen tary and indepen
18. ON NOILVHAdO ON lv PAG PA PXG PX X X X x X nas 0 0 331 L ojt wao 3AOW TVNOOVIG Si Le PA pxa PX X xIx X nas NMG L 0 0 OL WH AAOW IHOIE L4A1 HOSHNO E 1 PAG PA PX X X X X DNI 0 L LAN 0 ofr wan FAONNMOQ dN WS 10L L SA SX X X X X X X X X DNI L 0 LAX 0 by LTE AWH LHOdJMAIA AION uc IONS lv L SA SX X X X X X X X X DNI 0 0 LAX 0 LILLE AVS LYOdMAIASAVS SS490v cl 1S L SA SX X X X X X X X X nus L NNG d3H 0 LIL IL AQ1 LHOdMAIAaVO1 A PA PXQ PX X X X X X X X X X X X nus L nwa daqd NWS F O I Ad 1 QHOM L9379O1NIHd 4 B AYOWSIN 19 lv PA PXa Px x X X X X X X X X X X NAYS ds NAG d3H L 0 O L SAd 3 PA PXQG PX X X X X X X X X X X Xx nas ds NWd 939 0 LO t vod HJLOVYVHOLNIHA 9 L t dA 3X X X X X X x x X X X nas dS nwa 939 0 EE O Wa OuvATOd 3 QHOM L 910N 99s FS V 3 GRE ly LOL PAG PA PXa PX X X XxX x X X X X nas ds nwa o L ofr lo TH NO ATOd 3 VIHV LOL PAG PA PXQ PX X X X X X X X X X nas dS nwa o L OPL IO vaL WAIAdvHL S M v lt LOL PAG PA PX X X X X X X X X nas ds nwa o L LIL IL 338 AIDNYLOJH H 199 LOL 1130 1S1 dA 3X X XXIX IX X X X X X X X x XZ x nas ds NWA N3d 0d 0 0 uvd OHV Nad 7 g 10a LOL ISL dA dx X X X X X X X X X X X NAYS ds NAG 0 0 Llol o Hva OHV LOG 3 1149 Jy 139 LS PAG PA PXa PX X X X X X X X X X X X X X NAYS dS NNA NAd 10d 0 0 0 nd ANITNAd h 10a lv 1g PA
19. OR INTERFACE Description D 0 15 VO Data Bus These sixteen bidirectional pins provide communication with either an 8 or 16 bit host microprocessor data bus A 0 7 l Address Bus These eigth pins select the internal register to be accessed The Address Enable address can be latched by AE for direct connection to address data multiplexed microprocessor busses When TS68483 is connected to a non multiplexed microprocessor bus this input must be wired to VCC For direct connection to a multiplexed microprocessor bus the falling edge of AE latches the address on A 0 7 pins and the CS input With an Intel type microprocessor AE is connected to the processor Address Latch Enable ALE signal Data Strobe Read Write Active Low In non multiplexed bus mode DS low enables the bidirectionnal data buffers and latches the A 0 7 lines on its high to low transition Data to be written are latched on the rising edge of this signal In multiplexed bus mode this signal low enables the output data buffers during a read cycle With intel microprocessors this pin is connected to the RD signal In non multiplexed bus mode this signal controls the direction of data flow through the bidirectional data buffers In multiplexed bus mode this signal low enables the input data buffers The entering data are latched on its rising edge With Intel microprocessors this pin is connected to the WH signal Chip Select
20. U parameter is cleared a source pel color may be mapped into destination pel color independently of the source bit mask value The source bit mask acts as a TRANSPAR ENCY OPACITY flag which is enabled by SMU A PRINT OBJECT command may be independently parameteredby both SMU and DMU This provides a very powerful tiling print object or move mecha nism 11 4 Drawing Attributes Figure 6 Color Register The general drawing attributes are the colors the drawing mode and the scaling factor Il 4 1 COLORS Registers R1 and R2 Two 8 bit color values CO and C1 may be speci fied in registers R1 and R2 The low order 4 bit nibble of a color value is drawn in an even bank The high order color nibble is drawn in an odd bank When long pels are used banks 0 and 1 are generally addressed as the frame buffer When 5G5 THOMSON d CROELESTRONICE 68483 08 EPS TS68483A short pels are used any bank may hold a frame buffer In this case the bank parity selects the color nibble used See destination pointer section for bank addressing 11 4 2 DRAWING MODE Register RO The drawing mode defines the transforms to be applied to the pels designated by the drawing commands There are three drawing modes 11 4 3 MONOCHROME MODE Any AREA drawing command RECTANGLE for instance defines through its geometric arguments an active set of destination pels that is to say a set of pels to be modified When D
21. age 0 4 V load 4 mA ADM 0 15 load 1 mA other Outputs Power Dissipation m mW Input Capacitance 5 pF Its Three State off state Input Current 10 uA GENERAL OPERATION 1 1 Introduction The TS68483 is an advanced color graphics con troller chip It is directly compatible with most popu lar 8 or 16 bit microprocessors Its display memory containingthe frame buffer and the character generators may be assembled from standard dynamic RAM components On chip video shift registers and fully programma ble Video Timing Generator allow the TS68483 to be used in a wide range of terminals or computer design Additionalinformation on applications can be found in the TS68483 User s Manual 1 2 Typical Application Building Blocks In atypical using TS68483 a host processordrives a display unit which drives in turn a color CRT monitor The display unit consists of four hardware building blocks an TS68483 advanced graphics controller adisplay memory dynamic RAM adisplay memory interface comprising a few TTL parts a CRT interface of CRT drivers For enhanced graphics the CRT interface may include a color look up table circuit For high pixel rate over 18 Mpixels s the CRT interface must include high speed video shift registers The display memory interface and organization are discussed in full details in the User s Manual 1 3 TS68483 Functions All the TS68483 fu
22. ck One block two Z two bit planes belonging to the SCLK when external video shift registers are same bank share a given block In this case this used block must be accessed twice during a memory RAS CAS OE R W signals to the memory cycle This can be solved by two successive page blocks mode accesses Table 5 Memory Cycle Types Output Pins Fanction Modx Flags Multiplexed ADM Cycle Type CYF1 CYFO 1 0 TA TO T1 1 0 Command Read Y X Z0 Z2 21 23 Read Read 0 1 0 0 Y X Display 0 1 Y X 20 22 21 23 Dummy Read 1 0 0 1 0 Y X Dummy Read 2 Refresh dummy read cycle is performed Table 6 Frame Buffer Organization Typical Block Size 16kx8 32kx 8 64kx8 256kx8 One Block one Bit Planes 512 x 256 512x 512 1024 x 512 2048 x 1024 One Block two Bit Planes 256x256 512x256 512x512 COMPONENTS 64KBITS 16K x 4 or 64K x 1 256K BITS 32K x 8 64K x 4 256K x 1 VIDEO RAM 64K x 1 64K x 4 Table 7 The Multiplexing Scheme HIGHER BYTES ADMS Multiplexed Pins 15 14 13 12 11 10 9 8 TA Address Period 10 X 3 0 0 TO Even Z Byte Period 7 Z 2 T1 Odd Z Byte Period 7 Z 3 LOWER BYTES ADMS Multiplexed Pins 7 6 5 4 TA Address Period 10 Y TO Even Z Byte Period 7 Z 0 T1 Odd Z Byte Period 7 Z 1 ez SGS THOMSON a MICROELECTRONICS 68483 08 TBL 68483 09 TBL 68483 10 TBL TS68483A Figure 17 One Block One Z ADM 8 15 8 ADM 0 7
23. dent transforms see Fig ure 7 a color transform and a mask transform for the FOREGROUND PELS 9 30 TS68483A a color transform and a mask transform for the BACKGROUND PELS 114 5 POLYCHROME MODE A print object command defines a source window through the source pointer When SMU 0 any pel of this window is active mapped and clipped to the destination window dimension When SMU 1 only pels which have a source mask bit set are active mapped and clipped to the destination window dimension In both cases when DMU 1 the active source pels are further reducedby the destination masking mechanism Both mask transforms must be programmed at NO MODIFICATION for correct operations see Fig ure 7 11 4 6 THE LINEAR DRAWING COMMAND CASE ALINE or ARC drawing command may be exe cuted in any drawing mode depending on the PEN When the pen is a DOT this pel is printed at each active coordinate according to monochrome mode When the penis a CELL this cell is printed at each active coordinate In the bichrome mode when the cell is a character and in the polychrome mode when the cell is an object For each active coordinates the active destination Figure 8 Print Character Command DESTINATION WINDOW MASK BIT 1 set is defined by the cell dimensions DXs DYs Note when the cell is an object SMU is not programmable and is implicitly set A calculated coordinate is active when the rotated LSB linea
24. deo shift registers are not loaded instead they retain their margin color External video shift regis ters are presumed to be loaded by either 8 pels or 16 pels per cycle according to the programmed increment value In Float cycle an external X address must be provided The Y address is still provided on ADM 0 7 and Y 0 2 while ADM 8 15 are in high impedance state Note See Memory Organization and Memory Timing for further details on the memory cycles IV 3 3 THE VIDEO RAM CASE VRE 1 In this case the last cycle of the horizontal blanking interval is systematically allocated to the display process for DWY scan lines per field This cycle bears the scan line address the bank number and the X address which is always XOR MODX must be programmed to use external shift register Dummy read TS68483A IV 3 4 PAN AND TILT The host can tilt or pan the Display Viewport through the frame buffer by modifying YOR or XOR arguments Panning is performed on 8 pel bounda ries IV 4 Dynamic Ram Refresh No memory cycles are explicity allocated to the RAM refresh when RFD 1 When VRE 0 and DPD 0 the Display Process is supposed to be able to over refresh dynamic components This can be done by careful logical to component address mapping During the remain ing non displayable lines the Display Viewport address continues to be incremented Y address on each line according to INE X address initialized by XOR then
25. e blanking interval information OTHER PINS Power Supply 5 V Supply S Ground Ground CLK Clock Clock Input 2 30 KSK SES EEN 68483 01 TBL TS68483A BLOCK DIAGRAM MICROPROCESSOR INTERFACE D 0 15 A 0 7 is CLK e BLK PC HS HVSNS VIDEO VIDEO TIMING SYNC IN INTERFACE GENERATOR DRAWING AND VIDEO ACCESS SHIFT PROCESSOR REGISTERS 2 2 NT CYS CYF 0 B 0 1 Y 02 ADM 0 15 16 DISPLAY MEMORY INTERFACE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Ta Operating Temperature Range Tstg Storage Temperature Range Max Power Dissipation With respect to Vss Stresses above those hereby listed may cause permanent damage to the device The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specifications is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Standard MOS circuits handling procedure should be used to avoid possible damage to the device ez SGS THOMSON s MICROELECTRONICS 68483 02 EPS 68483 02 TBL TS68483A ELECTRICAL CHARACTERISTICS Vcc 5 0V 5 Vss 0 Ta TL to TH unless otherwise specified Symbol Parameter Min Typ Max Unit Voc 475 5 v Vin Input High Voltage 2 Vcc V VoH Output High Voltage loaa 500 LA p24 V VoL Output Low Volt
26. ected parameters the attribute values are the other values required by adrawing command colors or scaling factors for example the display memory addresses The command code is specified in register RO Before initiating a command execution each argu ment must be specified in its dedicated register an Xd Yd drawing coordinate pair for example is always located in registers R14 R15 The monitoring of acommand execution is done by reading the status register R12 or using the IRQ signal SGS TH YZ MICROELECTRONICS 68483 04 EPS 68483 05 EPS Table 1 Command Set Structure Drawing Mode Line Arc Up to the Pen TS68483A Rectangle Monochrome Trapezium Polygon Polyarc Print Char Bichrome Cell Print Object Polychrome Load Viewport Save Viewport Modify Viewport Move Cursor Abort II 2 Pointers and Geometric Arguments see Figure 4 Pointers are used to specify main geometric argu ments and display memory addresses 11 2 1 DISPLAY MEMORY ADDRESS A bit in the display memory is addressedby a bank number B 0 t03 a plane number Z 0t03 an X address X 0 to 2047 a Y addres Y 0 to 2047 11 2 2 DESTINATION POINTER Registers R14 to R17 This pointer gives the coordinate Xd Yd and dimension DXd DYd of either a line or a window in the drawing coordinate system These drawing coordinates are easily mapped into a PEL DIS PLAY MEMORY address X Y coordi
27. er R13 II 3 Destination Mask and Source Mask A mask bit may be associated to any pel stored in the display memory 11 3 1 DESTINATION MASK USE DMU Any drawing command may be parametered for destination mask use In this case any destination pel cannot be modified when its mask bit is reset 68483 07 EPS 5 s S65 THOMSON gt MICROELECTRONICS 68483 06 EPS In other words When the destination mask use DMU parame ter is set a pel may be modified when its mask bit is set a pel cannot be modified when its mask bit is reset When the destination mask use DMU parame ter is cleared a pel may be modified independently of its mask bit value This provides a very flexible clipping mechanism not restricted to rectangular windows See desti nation pointer section for destination mask bit ad dressing 11 3 2 SOURCE MASK USE SMU A PRINT OBJECT command may be parametered for source mask use In this case the source mask bit associated with any source pel is read first When its mask bit is cleared a source pel is con sideredas transparent See source pointer section for source mask bit addressing In other words When the SMU parameter is set the color of a destination pel mapped by a given source pel may take this source color value only when this source bit mask is set The destination pel keeps its own color value when the source bit mask is cleared When the SM
28. er pair see Figure 5 4 The access commands use the destination pointer location as a data buffer The memory addresses and dimension of the access viewport are then specified in the source pointer independently of the data transfer 5 DXd DYd and DYs may specify a negative value In this case they must be coded by a sign 0 positive 1 negative and an 11 bit absolute value 7 30 MICROELECTRONICS 68483 04 TBL TS68483A Figure 4 Pointers 15 14 DTE Geier PAA PLETTET S Pel Bank number 13 bit positive value address Gebei zd ES Xd FR uec Plane number 13 bit positive value DESTINATION POINTER arreter ern D Sr DYd var rrr prt Ge De IIR Vereen Gees Dese Absolute value A A GRUDO marae DII er verri GARILIEAL err S kr DXd Ee er verri Geesen e EE WE Ge Ke Sign Absolute value vzp r Bs SS Ys reterr tel KOLY Byte Bank number 11 bit positive value address verpir Se R21 Zs See Xs Character cell plane PCA 8 bit positive value SOURCE or source mask plane PVS PVF POINTER DE EE DIEI COE A A dert S kk DYs vestre I E RIEPALL Absolute value I IR BERI TR ezerert rererere bezerori eege Ube Ie DXs ezerezte ITRLIELLAR GTELETETE err Underlined cell 11 bit positive value Reserved x Don t care only used with TRAPEZIUM command Note Sign value S 0 positive S 1 negative absolute value Figure 5 Short Dimension Regist
29. et up Time from R W Active fast write cycle 10 indent Number arameer win Mex Unit 1 AE Width High 90 ns 2 Address Set up Time to AE Inactive 55 3 4 CS Set up Time to AE Inactive 40 ns 5 DS and R W High 150 6 7 R W Width low write 110 ns 8 Data Access Time From DS read 9 10 DS Inactive to High Impedance State read 10 100 ns 11 Data in Hold Time from R W Inactive write 30 12 13 AE Inactive to R W Active 20 ns 14 DS Inactive to AE Active 10 15 R W Inactive to AE Active 10 16 R W Inactive to Next Address Valid 100 ns 17 DS Inactive to Next Address Active 100 2 Gy SGS THOMSON ISO d CROELESTRONICE 68483 12 TBL TS68483A Figure 23 Read Cycle E FAST WRITE Din 24 30 GS THOMSON y SES THOMSON 68483 25 EPS 68483 26 EPS VI 2 Memory Interface ADM 0 15 B 0 Voc 25 0V t 5 96 TA 1 CYF 0 1 Y 0 TL to Ty CLK Duty Cycle 50 96 Period T 2 CYS Reference Levels Vu 0 8V and Vin 2V Vor 0 4V and Von 2 4V Indent Number Parameter TS68483A TCLK Clock Period Memory Cycle Time T 8 X Toi Output Delay Time from CLK Output Data HI Z Time from CLK Output Hold Time from CLK Input Data Hold Time from CLK read cycle Figure 25 Memory I Input Data Set up Time from CLK read cycle Input Data HI Z Time from CLK Note All timing is referenced to the rising edge of CLK see timing diagram 3 nterface dik XDI
30. ither Motorola type 6809 68008 68000 or Intel type 8088 8086 The host microprocessor has direct access to any of the twenty four 16 bit on chip registers through the microprocessor interface pins D 0 15 16 bidirectional data pins A 0 7 8 address inputs AE DS R W CS 4 control inputs The twenty four registers are mapped in the host addressing space as 256 byte addresses see Figure 13 A 1 5 select one out of 24 registers AO selects the low order byte AO 1 or the high order byte AO 0 of the selected register A 6 7 provide the command execution condition The host microprocessor bus may be either 8 or 16 bits wide and may be address data multiplexed or not The two flags MB and BW in the CONFIGURATION register R10 allow the data bus size and multi plexed non mutiplexed organization to be speci fied see Table 2 ar A6 AS A4 3 A2 A1 AO High Low Byte Address 16 bit Register ADDRESS Execution Condition ps w ms se w vo o e v e s a aj 2 1 0 Byte Addressing Table 2 MPU Selection Type of MPU Bus Conf Reg TS68483 Pins BW MB D 8 15 Non Mux 16 bit 68000 ope O V M Den D 8 15 8 bit 68008 DS D 0 7 IS R E TER M AE AD 0 7 13 30 ZC G5 THOMSON MICROELECTRONICS 68483 15 EPS 68483 05 TBL TS68483A Figure 14 Interface with TS68000 68008 MPU TS68000 TS68483 D 8 15 D 8 15 D 0 7 D 0 7 A
31. l frequency When the pixel frequency is in the 15 to 18MHz range and 4 bits per pixel or least are required the on chip video registers and standarddynamic RAM components may be used When higher pixel rates SGS THOMSON TZ MICROELECTRONICS 68483 07 TBL TS68483A or up to 8 bits per pixel are reguired the designer RADand CAD Enable signals to the Mapper must provide external shift registers Video RAM components may also be considered V 3 1 FRAME BUFFER see Table 6 In eith th Kater A byte wide organization of each bit plane is re E eMe MUSLCESIN quired Obviously a bit plane must contain the A memory block This is the hardware memory Display Viewport size A straight organization im building block It includes the video shift registers plements only one bit plane per block if on chip VSR cannot be used It implies a RAM componentchoice It may be cost effective to implement several bit An Address Mapper which maps the logical ad planes per block Two basic schemes may be dress into hardware address block selection used Row Address RAD Column Address CAD One block one Z several bit planes belonging Amemory cycle controller This controller moni to different banks but addressed by the same Z tors the CYF and CYS output pins from TS68483 share agiven block There is little time constraint and block address from the Mapper It provides if any The CLK signal to the TS68483 and a shift clo
32. ld Interlace Enable when INE 1 s i Vertical Number of Lines in Vertical Blanking 2 5 Scan Number of Lines in Vertical Front Porch Number of Lines in Vertical Back Porch 2 5 Number of Double Cycles per Line Number of Cycles in Horizontal Front Porch Horizontal Number of Cycles in Horizontal Blanking 3 Scan Number of Cycles of the Display Window X Y and bank logical address in the display Display memory of the display viewport upper left corner Process Selection of the X Addressing Mode Margin Color RAM Refresh Disable when RFD 1 Memory 1 Display Process Disable when DPD 1 Time VRE 1 R8 Video RAM Enable When VRE 1 Sharing Note one cycle 8 periods ofCLK Clock V MEMORY ORGANIZATION V 1 Introduction The display memory is logically organized as four banks of 4 bit planes Thus a bit address in the display memory is given by the guadruplet B bank number from 0 to 3 Z plane number from 0 to 3 X bit address into the plane from 0 to 2047 Y bit address into the plane from 0 to 2047 In one memory cycle 8 CLK periods the controller can access a memory word This 32 bit memory word holds one byte from each plane in a given bank In order to address this memory word the controller supplies B 0 1 binary value of the bank number X 3 10 binary value of the word address Y 0 10 binary value of the word address Z and X 0 2 are not supplied They give o
33. mmer to read or write any data type byte word long word and automatically initiate or not a command execution at the end of this transfer The transfer lasts one two or four bus cycles A 68000 programmer is restricted to only word and long word data types see Table 3 Data Type Transfer 8 bit Data Bus 16 bit Data Bus NEC C mee Any Type Any Type 1 Word 1 Long Word Exec after a Bus Cycle 1 Byte Exec After 2 Bus Cycles 1 Word a ee Exec after 4 Bus Cycles 1 Long Word ILLEGAL Notes Word transfer must respect word boundary Long word transfer must respect long word boundary Not available with 8088 MPU type IV THEVIDEO TIMING GENERATOR RAM REFRESH AND DISPLAY PROCESS IV 1 Introduction The Video Timing Generator is completely synchro nous with the CLK input which provides a pixel shift frequency up to 18MHz The Video Timing Gen erator delivers the blanking signal BLK the horizontal HS and vertical VS synchronization signals on respective output pins schedulesthe memory time allocated to the dis play process dynamic RAM refresh and com mand execution is fully programmable can be synchronized with an external composite video sync signal connected to the SYNC IN input IV 2 Scan Parameters see Table 4 and Fig ure 26 IV 2 1 TIMING UNITS The time unit of any vertical parameter is the scan line The time unit of any horizontal parameter is the memory cycle
34. nates are clipped to 11 bits in order to get the Xd Yd destination pel addresses A bank number Bd must be explicitly provided to address a destination frame buffer When long pels are used Bd must be even When masked pels are used the destination mask plane number Zd implicitly in bank 3 must also be provided Il 2 3 SOURCE POINTER Registers R20 to R23 A source cell such as a character a pen or an object is addressed by the source pointer in the display memory A source pointer specifies a bank number Bs 0 to 3 ST G5 THOMSON Group Linear Area Drawing Access Management Control a Ysaddress Ys 0 to 2047 an Xs address this address is a byte address so that the 3 LSBs are not specified Xs 0 to 255 a cell dimension DXs DYs a bit plane address Zs When a character is addressed Zs gives the plane number into the bank Bs When an object is ad dressed Zs gives the source mask plane number in the bank B3 Il 2 4 NOTES 1 The TRAPEZIUM command makes a special use of R21 In this case R21 holds an X1 drawing coordinate which has the same format as Xd 2 The ARC and POLYARC commands require two extra geometric parameters RAD and STOP They are specified in the drawing coordinates system and storedin registers R18 R19 3 Any drawing command may be parametered to use short incremental dimensions DXY in register R13 instead of the standard DXd DYd in the R16 R17 regist
35. nctions are under the control of the host microprocessor via 24 directly accessible 16 bit registers These registers are referred to by their decimal index RO R23 see Figure 1 4 30 S74 SGS THO MICROELECTRONICS Figure 1 Register Map 15 8 RO COMMAND R1 Sy R2 R3 R4 R5 R6 R7 R8 R9 COMMAND DRAWING ATTRIBUTES TEXLIN MARGIN COLOR VIDEO TIMING GENERATOR SHORT RELATIVE REGISTER DESTINATION POINTER AUXILIARY GEOMETRIC ARGUMENTS SOURCE POINTER 1 3 1 VIDEO TIMING AND DISPLAY PROCES SOR R4 to R10 The video timing generator is fully programmable any popular horizontal scanning period from 20 us to 64 us may be freely combined with any number 68483 03 TBL 68483 03 EPS of lines per field up to 1024 The address of the display viewport this part of the display memory to be actually displayed on the screen is fully pro grammable The display processor provides the display dynamic RAM refresh see video timing generator section for details 1 3 2 DRAWING AND ACCESS COMMANDS RO to R3 R12 to R23 The 16 remaining registers are used to specify a comprehensive set of commands The highly or thogonal drawing command set allows the user to draw in the display memory such basic patterns as lines arcs polylines polyarcs rectangles and characters Efficient procedures are available for either area filling and tiling or line drawing and text
36. nly a bit address in a memory word V 2 Memory Cycles 24 pins are dedicated to the memory interface ADM 0 15 these 16 bidirectional pins are mul tiplexed three times during a memory cycle see Figure 25 TA address period Output of the X 3 11 and Y 3 11 address even data period The even Z bytes are either input or output T1 odd data period The odd Z bytes are either input or output TO 18 30 Y 0 2 three LSB Y address output pins non multiplexed B 0 1 two bank address output pins non multiplexed CYS Cycle start strobe output non multiplexed CYS is at CLK 8 frequency ACYS pulse is deliv ered only when a command display or refresh cycle is performed CYF 0 1 Two cycle status outputs non multi plexed Four cycle types are defined Command Read Command Write RAM Refresh Display Access Because several options may be selected for RAM refresh and display access by the MODX and VRE flags see Video Timing Section there are more than four memory cycle types see Figure 25 and Table 5 V 3 Display Memory Desing Overview The display memory implementation is application dependant The basic parameters are the number of pixels to be displayed Nx Ny the number of bits per pel the vertical scanning frequency which must be picked in the 40Hz to 80Hz range non interlaced or in the 60Hz to 80Hz range interlaced This yields a rough estimate of the pixe
37. r 2 bits B 0 to 3 Abit plane number 2 bits Z 0 to 3 AY address 11 bits Y 0 to 2047 An X address 11 bits X 0 to 2047 MEMORY WORD see Figure 3 A 32 bit memory word canbe either read or written during each memory cycle 8 CLK periods one byte at a time in each bit plane in the addressed bank The memory bandwidth is in the 6 to 8Mby tes s range VIEWPORT This is any rectangulararray of pels located in the display memory FRAME BUFFER This is the biggest viewport which can be held in the display memory The frame buffer maps a window at the origin of the drawing coordinates A short pel frame buffer may be located in any bank Along pel frame buffer mustbe located in the bank 0 bank 1 pair DISPLAY VIEWPORT This is the viewport which is displayed on screen MASK BIT PLANE When masked pels are used a mask bit plane must be associated to a frame buffer Mask bit planes may be located in any plane of bank 3 CELL A CELL is any pattern stored inthe display memory as a rectangular array of bit mapped elements The drawing of any CELL may be specified with a scaling factor CHARACTER This is a one bit per element CELL It may be stored in any bit plane then colored and drawn in a frame buffer by use of PRINT CHARACTER command OBJECT This is a one short pel per element CELL It may be drawn or loaded in a frame buffer A source mask bit may be associated to each element An OB
38. r texture bit in R3 is set Figure 7 Drawing Mode Register RO BACKGROUND FOREGROUND BACKGROUND FOREGROUND Monochrome Bichrome Polychrome CHARACTER CELL Y SET ELEMENT 1 ELEMENT 0 MAPPED CH ARA CTERWINDOW MAPPED ER Y Xd Yd CHARACT WINDOW X NO MODIFICATION FOREGROUND BACKGROUND 10 30 GS THOMSON EA MICROELECTRONICS 68483 09 EPS 68483 10 EPS Il 4 7 SCALING FACTOR AND CELL MAPPING see Figures 9 and 10 Figure 9 Scaling Factor Any cell may be printed with a scaling factor This scaling factor is an integer pair Sx Sy 1 to 16 This scaling factor is interpreted with the Figure 10 Cell Mapping versus DYd DYs SIGN Y DYs gt 0 X Xs Ys DXs gt 0 Y Xs Ys DXs gt 0 DYs 0 Xd Yd ST G5 THOMSON 68483 11 EPS TS68483A PRINT CHARACTER PRINT OBJECT and LIN EAR commands when the pen is a cell The AREA or ACCESS or LINEAR DOT commands are never scaled The LINEAR PEN command should be used with a scaling factor of 1 because the pen is clipped at DXs DYs The scaling factor is first applied to the source cell before mapping and drawing The drawing and mapping is processed with sign bit of DYd and DYs values see Figure 10 Notes DXs is always positive The DYS sign mirrors the cell DXd must be positive with a PRINT CELL com mand DXd and DYd may get any sign with a L
39. si ysew o01nosouL WS peiuud si joo euo juo 0 JIH ueuM MOPUIM uogeursep eui uBnojur pejeedei pue poddajs soo oul dadH Aepunog eui 0 amp BurBuojeg jad sad Ajaaoedsa 1g pue p ppe spueuiuioo 14 pue 114 104 BJON sa UOHODIIP A pejueujeJoep ojne JO pejueuJeJour ojne SI Jejurod eounos out 0 14X say uonoeurp x pejueujeJour ojne srjejurod eounos aui J4X L7 ONI spoued Aejdsip eui jo jno juo peuuogied sruonnoexe puewwog JSI uonoeJIp X pejueuieJour ojne JOU s JSJUIOd eojnos eu 07 ON peinbei s Bunuud seu ji 12 oje jod y uoB jod let x3 euo JSI OY 0 eoruepi Jou SI BUIMEJP puooes eu ueuw JUO 18se1 eq pjnous ejeureied siu pesn ere ued Duo ji LZ Bu oje jod 10 uoBAjode ou 538 L NWS HLI L9 ING JILL 4ejuiod anos y g pesseJppe ysew snos UJIM pejeroosse joe qo au si ued eui 1Od ejgei y ui doo jad uous eui oi ppe duu uonnoexe 104 4ejuod eoinos ay g passaippe joo Jejoejeuo eui si ued au 0 Od N3d spoued 490 9 YTD 8 ejofo JOLU U ed auis e ai ue oul 0 NId 9AI ISOd sdpwg SI SXG S sonpeA paubis ere SAT pue PAC PXA etH esnjeisibeueAnejejuous nus juejedsueJ ase O en eA 10 09 UJIM Sjad SpJOM Jeujo U 0 dS ueuw Jad Bug jad yous L dS pesn pue jes Apuduu seu MNOS S SEU 0 WUOJJJU IAJJIP 10 09 UJIM Jad Aue pUBLUWWOD JAd UMM AION een ysew uoneunsaq L NAG ze Lt L L L L L L t 188 1HO8V GS JOHLNOD un Lt 0 0 0 0 0 OPL d
40. t used The DWY x DWX cycles in the display interval are allocated to the display process when it is enabled DPD 0 When the display process is disabled these cycles are allocated as for non displayable lines When VRE 1 one cycle per display line is allo cated to the display process Other cycles are allocated as for non displayable lines The last period of the BLKX signal may be used to load the internal video RAM shift register the non displayable lines In one out of nine non displayable lines DWX cycles are allocatedto the refresh process when it is enabled RFD 0 n Float cycle an external X address must be provided The Y address is still provided on 16 30 DWX DISPLAY BACK PORCH FRONT4 PORCH FPY a DISPLAY DISPLAY DWY BACK k PORCH BPY 25 25 Lines BLANKING Vertical Minimum Number of Lines ADM 0 7 and Y 0 2 while ADM 8 15 arein high impedance state IV 2 5 COMMAND ACCESS RATIO This allocation scheme leaves about 50 of the memory bandwidth for command access when programming a standard TV scan This ratio drops to the 30 range when a better monitor is in use 32us out of 43us displayable per line 360 lines out of 390 fora 60Hz field rate The higher resolution means more memory accesses in order to edit a given percentage of the screen area In this case Video RAMs are very helpful to keep 90 of the memory bandwidth available forcommand access IV
41. uring Lines may be drawn with a PEN in order to ta get tg thick strokes Any drawing is specified in a x 2 drawing coordinate system a access the display memory the host microproc essor has an indirect sequential access to any window Access commands can be used to load the character generators as well as to load or save arbitrary windows stored in the frame buffer 1 4 Data Type Definitions PIXEL this is the smallest color spot displayable on the CRT PEL a Picture Element is the coding of a PIXEL in the display memory The TS68483 can handle 4 different PEL formats 4 colorbits short 4 color bits 1 mask bit short masked 8 colorbits long 8 color bits 1 mask bit long masked DRAWING COORDINATES see Figure 2 The drawin ng commands are specified and com puted in a 2 x 21 cyclical coordinate system The drawing coordinates are clipped and mapped into the 2 x 2 display memory addressing space Further clipping to the actual frame buffer size may be performed by the user designed memory inter face DISPLAY MEMORY This is the dedicated memory to the display unit This memory is addressed as four banks of 4 bit plane each BIT PLANE Each bit plane has a maximum capacity of 2 x 2 bits Abyte wide organization of each bit plane is required TS68483A MEMORY ADDRESS see Figure 3 In order to address one bit in the display memory the user must specify Abank numbe
Download Pdf Manuals
Related Search