LPC-MT-2138 User Manual
Contents
1. 2138 development board Users Manual Pb free Green boards produced by Olimex are ROHS compliant Rev Initial September 2005 Copyright c 2010 OLIMEX Ltd rights reserved Page INTRODUCTION LPC MT 2138 is small terminal board which uses LPC2138 microcontroller With its LCD relay five buttons variety of interfaces such as 5232 JTAG Dallas and extension connector for some of the microcontroller s pins this board is suitable for different embedded systems applications BOARD FEATURES Microcontroller LPC2138 16 32 bit ARM7TDMI S with 512K Bytes Program Flash 32K Bytes RTC 8x 10 bit ADC 2 44 uS 2 UARTS 2 SPI 2x 32bit TIMERS 8x CCR PWM WDT 5V tolerant I O up to 60MHz operation JTAG connector as per ARM s 2x10 pin layout ARM JTAG Wiggler compatible 14 7456 Mhz crystal on socket allow easy communication setup 4x PLL 58 9824 Mhz CPU clock RS232 interface circuit with SUB D 9 pin connector LCD16x2 display with BACKLIGHT five buttons Dallas iButton port Frequency input Relay with 10A 250VAC contacts Buzzer Status LED RESET circuit RESET button Bootloader enable jumper and pullup DEBUG jumper for JTAG enable disable RTCK pullup resistors Power plug in jack power supply 9VAC 12VDC three on board voltage regulators 1 8V 3 3V and 5V power supply filtering capacitor Four mounting holes PCB FR 4 1 5 mm 0 062 soldermask whi2. S 9 7 Sad 1 1541 4 vad E MOLE MOLT MOL OVIT LHON val szu 928 1H9n 9 E wore e o fe Q AG AS all C11 9 4 0 GLO 10uF 16V 1noeH NIIS NIZ L LNO L NILL CO CECEXYN 6 Page 8 BOARD LAYOUT B1 LED B4 LCD B2 B5 B3 22 REL_CON RS232_ICSP tm 2 DAC PWM CONTRAST COPYRIGHT CC 2005 N 7 4 a WIES i 3 sit RIG RE 7 BAT icd IURE 7 8 TIME i Tun 2 06 tis FIM AME DALLAS 3 e esi en DBG PWR EXT BUZZER JTAG POWER CIRCUIT LPC MT 2138 can is typically power supplied with 9VAC or 12VDC from power jack RESET CIRCUIT LPC MT 2138 reset circuit includes R6 10k pull up U3 MCP130T LPC2138 pin 57 RST and RST button CLOCK CIRCUIT Quartz crystal Q1 14 7456 MHz is connected to LPC2138 pin 61 X2 and pin 62 X1 Quartz crystal Q2 32 768 KHz is connected to LPC2138 pin 3 RTCX1 and pin 5 RTCX2 Page 9 DESCRIPTION VREF DAC PWM Connects LPC2138 pin 63 to 3 3V Default state is closed When this jumper is in position DAC connects LIGHT_LCD signal to LPC2138 pin 9 AOUT when this jumper is in positio
3. In System Programming In Application Programming ISP IAP via on chip bootloader software Single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms EmbeddedICE RT and Embedded Trace interfaces offer real time debugging with the on chip RealMonitor software and high speed tracing of instruction execution Two 8 channel 10 bit ADCs provide a total of up to 16 analog inputs with conversion times as low as 2 44 ms per channel Single 10 bit DAC provides variable analog output Two 32 bit timers external event counters with four capture and four compare channels each PWM unit six outputs and watchdog Low power Real time clock with independent power and dedicated 32 kHz clock input Multiple serial interfaces including two 16C550 two Fast 400 kbit s SPI and SSP with buffering and variable data length capabilities Vectored interrupt controller with configurable priorities and vector addresses Up to forty seven 5 V tolerant general purpose I O pins Up to nine edge or level sensitive external interrupt pins available 60MHz maximum CPU clock available from programmable on chip PLL with settling time of 100 ms Page 4 On chip integrated oscillator operates with external crystal in range of 1 MHz to 30 MHz and with external oscillator up to 50 MHz Power saving modes include Idle and Power down Individual enable disable of peripheral
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5. 000 RESERVED ADDRESS SPACE 2 0 0 8000 0000 BOOT BLOCK RE MAPPED FROM ON CHIP tipo MEMORY RESERVED ADDRESS SPACE 0x4000 8000 0x4000 7FFF TOTAL OF 32 kB ON CHIP STATIC RAM 1 0 GB 0x4000 0000 0x0008 0000 0x0007 FFFF RESERVED ADDRESS SPACE TOTAL OF 512 kB ON CHIP NON VOLATILE MEMORY 0 0 GB 0x0000 0000 Page 7 SCHEMATIC 8 1 M MAM d31U a H YL ids ig ca feg sg PIT X3WI10 5002 OD LHDINAdOO WY 9 ca Sa 1 2 1 rae GLY 9 LLY 138 gt 2 NOO AEE LO 154 X LZOd1 UOOL 9 4 0 18534 VSSA 2 isu we 45 69 4 CO LOELdOW MOL e ex v eqan a en do 9 ASE ru nes LX J3HA H x Z9 9 pes D EL 0 SSSA am Lk 4 va_ 01VW E odvo z 0AV 6Z od ESSA ED uooi uooL ZOlVW ZOdvo loQv ez od zss L4 uiam 8204 2 0d issn 9 2204 M eoqwizod 3 9 Zod Ob inowiroaviszod 2 m one eaan 8204 one eqqn s __ 001 VIN O OdVO Z Od e Q B O zng 21 ee 51 8
6. 6 to LPC2138 pin 40 P1 22 DB7 to LPC2138 pin 36 P1 23 Potentiometer with name Contrast for setting LCD contrast voltage Status Led with name LED connected to LPC2138 pin 17 31 Buzzer connected to LPC2138 pin 2 P0 22 Page 10 EXTERNAL CONNECTORS DESCRIPTION Relay with name REL connected to LPC2138 58 0 23 Signal Name Pin Signal Name 1 3 3 V 2 3 3 V 3 TRST 4 GND 5 TDI 6 GND 7 TMS 8 GND 9 TCK 10 GND 11 RTCK 12 GND 13 TDO 14 GND 15 RST 16 GND 17 Not Connected 18 GND 19 Not Connected 20 GND Pin Signal Name 2 3 4 1 GND 2 SCLO 3 SDAO 4 3 3V Page 11 1 3 5 7 9 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Signal Name Pin Signal Name 1 P0 4 2 P0 5 3 P0 6 4 P0 7 5 P0 8 6 P0 12 7 P0 13 8 P0 17 9 P0 18 10 P0 19 11 P0 26 12 P0 27 13 P0 28 14 P0 29 15 P1 24 16 P1 25 17 P1 16 18 AOUT 19 3 3V 20 GND FREQ Pin Signal Name 1 0 10 2 GND j DALLAS Pin Signal Name 1 DALLAS P0 11 2 GND tome Page 12 Pin Signal Name 1 VBAT 2 GND RS232 ICSP Signal Name DN 2 T1OUT o d PWR Signal Name REL CON This connector pr
7. functions as well as peripheral clock scaling down for additional power optimization Processor wake up from Power down mode via external interrupt or BOD Single power supply chip with POR and BOD circuits CPU operating voltage range of 3 0 V to 3 6 V 3 3 V 10 76 with 5 V tolerant I O pads Page 5 BLOCK DIAGRAM P0 31 0 P1 31 16 EINT 3 0 8 x CAP 8 x MAT ADO 7 0 AD1 7 0 AOUT P0 31 0 P1 31 16 PWMI 6 1 1 TMS TDI trace XTAL2 TRST fr 1 RESET TEST DEBUG LPC2138 INTERFACE 25 SYSTEM PLL EO FUNCTIONS ARM7TDMI S 32 221 VECTORED 2 BRIDGE INTERRUPT CONTROLLER LU Advanced High performance Bus ARM7 local bus 0 INTERNAL INTERNAL 5 FLASH CONTROLLER CONTROLLER AHB DECODER 32 kB SRAM 512 kB FLASH AHB TO APB APB BRIDGE DIVIDER APB ARM peripheral bus SCLO 1 EXTERNAL 2 SERIAL INTERRUPTS INTERFACES 0 AND 1 ae CAPTURE SCKO 1 COMPARE SPI AND SSP MOSIO 1 TIMER O TIMER 1 SERIAL INTERFACES MISOO 1 SSELO 1 A D CONVERTERS TXDO 1 0 AND 1 UARTO UART1 RXDO 1 DSR1 CTS1 RTS1 DTR1 DCD1 RTCX1 REAL TIME CLOCK RTCX2 GENERAL VBAT PURPOSE I O WATCHDOG TIMER SYSTEM CONTROL Pins shared with GPIO Page 6 MEMORY MAP 4 0 GB OxFFFF FFFF AHB PERIPHERALS 375 GB OxF000 0000 VPB PERIPHERALS 35 0xE000 0000 3 0 0 000 0
8. limex Ltd Other terms and product names may be trademarks of others The information in this document is provided in connection with Olimex products No license express or implied or otherwise to any intellectual property right is granted by this document or in connection with the sale of Olimex products Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material from except with the prior written permission of the copyright holder The product described in this document is subject to continuous development and improvements particulars of the product and its use contained in this document are given by OLIMEX in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product OLIMEX Ltd shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Page 17
9. n PWM connects LIGHT_LCD signal to LPC2138 pin 1 PWMB JRST BSL DBG Default state is PWM closed Enables LPC2138 reset via UART Default state is open This jumper is connected to LPC2138 pin 41 P0 14 When this jumper is open P0 14 is pulled up to 3 3V via R1 22k when is closed P0 14 is pulled down via R24 1k LOW level on pin P0 14 immediately after reset is considered as an external hardware request to start the ISP command handler If there is no request for the ISP command handler execution P0 14 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Default state is open Enables JTAG debug operations Default state is closed INPUT OUTPUT Reset button with name RST connected to LPC2138 pin 57 RST User button with name B1 connected to LPC2138 pin 45 P0 15 User button with name B2 connected to LPC2138 pin 46 P0 16 User button with name B3 connected to LPC2138 pin 55 P0 20 User button with name B4 connected to LPC2138 pin 15 P0 30 User button with name B5 connected to LPC2138 pin 34 0 9 LCD 16x2 display with BACKLIGHT connected as follows RS to LPC2138 pin 12 P1 17 R W to LPC2138 pin 4 P1 19 E to LPC2138 pin 8 1 18 DB4 to LPC2138 pin 48 P1 20 DB5 to LPC2138 pin 44 P1 21 DB
10. ovides the user with access to the contact plates of the relay Page 13 MECHANICAL DIMENSIONS 1 C N LON 10 X ardor 5 LPC213X HT 1 000 1 360 1 275 1 200 0 250 0 225 0 140 0 000 GG C GG N e X OLL N LO wow 0 OLDO lt lO GG OFT 0 9 GGG soa dd d 2665 2 402 1 500 1 380 1 265 1 360 1 240 5 1 195 1 065 0 800 555 0 535 OZ i 2 0 250 LSS 0 225 Hoooo ooo Hoooo ooo r s0000000000 s0000000000 2 0 140 0 008 0 000 0 000 0 100 0 275 0 550 1 450 1 850 2 750 3 050 4 750 All measures are in Inches Page 14 AV AILABLE DEMO SOFTWARE LCD drive code EW ARM RTC code EW ARM RS232 code EW ARM Button Relay LED buzzer demo code EW ARM LCD UART BUTTONs BUZZER demo code GNU by Markus Dornhofer OpenOCD Eclipse set of projects 1 00 include flash write make file for LPC 2138 15 ORDER CODE 2138 completely assembled and tested How to order You can order to us directly or by any of our distributors Check our web www olimex com dev for more info Revision history Rev Initial create September 2005 Page 16 Disclaimer 2010 Olimex Ltd rights reserved OlimexG logo and combinations thereof are registered trademarks of O
11. te silkscreen component print Dimensions 120x38 mm 4 75x1 5 Page 2 Page 3 ELECTROSTATIC WARNING The LPC MT 2138 board is shipped in protective anti static packaging The board must not be subject to high electrostatic potentials General practice for working with static sensitive devices should be applied when working with this board BOARD USE REQUIREMENTS Cables Depends on the used programming debugging tool It could be 1 8 meter USB cable to connect ARM JTAG EW ARM USB OCD ARM USB TINY and ARM USB TINY H to USB host on PC or LPT cable in case of other programming debugging tools You will need a serial cable if not for programming than for configuring the board Hardware Programmer Debugger some of Olimex programmers are applicable for example ARM JTAG ARM JTAG EW ARM USB OCD ARM USB TINY ARM USB TINY H or other compatible programming debugging tool PROCESSOR FEATURES LPC MT 2138 board use LPC2138 microcontroller based on a 16 32 bit ARM7TDMI S CPU with real time emulation and embedded trace support that combine the microcontroller with 512 kB of embedded high speed flash memory A 128 bit wide memory interface and a unique accelerator architecture enable 32 bit code execution at maximum clock rate with these features 232kBofon chip static RAM and 256 512 of on chip flash program memory 128 bit wide interface accelerator enables high speed 60 MHz operation
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