PQ–MDS–T1 084-00214-2 PMC T1/Slic
Contents
1. LM CARD Q PQ MDS T1 interconnect 1 LL LLL LEGERITY Line Module Le71HR0826 PS restricted P nm nal i e area ee 5 4 2 1 1 interconnect DS3 E3 LINE TRANSFORMERS DS3 T3 BNC 09 Q Add In Card with 8 RJ 45 Connectors Figure 7 Page 28 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 E 2 freescale semiconductor SLIC SLAC LM CARD LM CONNECTOR X PQ MDS T PQ MDS PIB Figure 8 Page 29 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor freescale semiconductor CONNEC2. 1 544MHz 2 048MHz gt TSYSCLK 16 884MHz Bit 0 1 BPCLK gt Bit 0 1 Figure 19 SYNCTSS OUTPUT 5 1 RSYNC2 20 RSYNC3 TSSYNCIO RSYNC5 RSYNC6 gt O Bito 3 RSYNC7 gt RSYNC8 Figure 20 Page 44 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com gt freescale semwconductor 1 544 2 1 544 2 2 048MHz 2 048MHz t gt O e 1046 RCLK eO RCLKS REFCLKIO us Bit 0 1 7 gt O TCLK2 PO TCLK6 RCLK2 RCLK6 gt O Bit 2 3 i gt O Bit23 e e gt O TCLK3 7 a TCLK7 RCLK3 RO 128145 EO 1 8145 gt O TCLK4 PO TCLK8 RCLKA RCLK8 RO 128167 gt O 8667 Figure 21 OUTPUT 3 STATE RSYNC1 lt _ 1 o e EO 1 O OUTPUT a 3 STATE RSYNC2 lt TSER2 OI RSER2 v 0 RSER2 Oo OUTPUT gt C 3 STATE RSYNC3 TDM
3. 54 JO _ 57 158 10 _ HSNZ GND aj VO x VO C Page 39 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor Section9 PQ MDS T1 PLD TDM channels routing PLD internal routing used to interface PQ MDS T1 on board 1 1 DS3 framers and LM card to PQ MDS PIB board Host TDM channels This routing represented in the Figure 14 Figure 18 Note e Signals marked in Black are general e Signals marked in Blue assigned for LM SLIC SLAC card interconnections e Signals marked in Red assigned to interface DS3 T3 framer TDM Ch A TDM Ch B DS3 NU DS3 NU A TXD0 e gt B Le 2 TDM TSER2 TSYNCS1 reg pM O 9 053 NU 053 NU A_RXDO gt RSER1 B RXDO 2 RSER2 Et 093 NU DS3 NU ATSYNC 7 TSYNC1 lt __B_TSYNC_g TSYNC2 S 72 o SSYNCIO C o SSYNCIO 053 DS3 NU O A TXCLK lt B IXCLK e Dei Del O lt m BPCLK O ns BPCLK
4. DS3 NU 053 NU E A RXCLK e 2 RCLK1 2 B_RXCLK e s RCLK2 Ox Ox 083 NU 083 NU A RSYNC 8 RSYNC1 RSYNC O RSYNC2 GCR bit 0 GCR bit3 6 GCR bit 0 GCR bit3 8 t NU Figure 14 Page 40 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com P 22 f i reescaie semiconductor DS3 NU DS3 NU C TXDO _ To TSYNCS1 reg TXDO lt TDM_TSER6 To 1 reg 9 9 DS3 NU 053 cm 52 RSER3 FR e RSER6 Ze DOUT ES LM DOUT PSN NU DS3 NU C_TSYNC TSYNC3 p F TSYNC tO e o e ou T x O SSYNCIO gt O SSYNCIO DS3 NU DS3 4 9 2 p F TXCLK g TCLK6 lt Delay Delay 718 BPCLK 24 s BPCLK iu DS3 NU 053 NU E C RXCLK RCLK3 F RXCLK o _ RCLK6 2e L x 053 NU 053 NU C RSYNC e 2 0 RSY
5. Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 treescale PQ MDS T1 084 00214 2 PMC T1 Slic Slac add in module User s Manual PQ MDS T1 084 00214 2UM ding Versi Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com E T z freescale semwconductor Table of contents Section General Information NOR 3 L2 PO MIDS T1 module features rra Sin asqa Aa UD 3 LY POMDS TI Hos INE ICE uuu u thas 4 1 4 1 functions esses nnne 4 1 4 1 Octal T1 E1 J1 Framer e 4 1 4 2 Dual DS3 T3 framer F 5 1 5 PQ MDS T1 module control functions 1 1 6 PQO MDS T1 module visual indicators 2 7 1 7 PQ MDS T1 module main circuit elements 7 Section2 PQ MDS T1 module Block Diagram 9 PQ MDS T1 Address map 9 2 1 General address SPACE ku 9
6. 35 TRDY ERXD2 36 33V 33V 220 37 39 PERR ERXD3 4 GND GND 33V 33V 42 SERRE ETXD 43 44 GND GND 45 4 146 ADI3 47 M66EN 48 0 DRXD 49 ADOS 5 33V 33V 51 __ 7 CRSYNC 52 888 1 0 53 33V 33V 54 JPMCRSRVD o o 55 PRC RSRVD C 56 GND GND 57 PMC RSRVD A RSYNC 58 PMC RSRVD E TXCLK _ 59 GND GND 60 PMCRSRYD 61 ACK64 GRXCLK 6 33V 33V ____ 63 GND GND 64 PMC RSRVD Page 37 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com gt z freescale semwconductor Continue Table 8 ree _ Function Function Function E 1 PCHRSRVD H TXCLK 2 oe O 5 6 7 ERXCLK 18 GND GND 9 vao 33V 10 PAR4 BRXCLK ADG3G 2 ADO BRSYNC 13 ab j 14j GND y 15 GND GND 16 ADO 5 17 ADS9 FRxDO 18 ADSS 5 19 AD7 2 GND 21 33
7. RCLKi REFCLKIO Framer TCLK Source Ports 5 8 RCLKi REFCLKIO 1 1 Framer TSYNC Source Ports 8 1 GND TSYNC out TSYNCi RSYNCI 200 es Framer TSER Source Ports 27 Tri state RSER Input Write Read 13 20C RSRVI Reserved for futureuse 14 20D RSRV2 J hResevedforfuureuse 00000 15 2002 RSRY3 J Resevedforfutureuse 16 20 RSRVA Reserved for future use 000000 Page 10 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor 3 3 PLD Control Register Description BRDID Register Description Board ID Value Register Address 2000 ee eee eee PLD Bit S __ 2 3 4 5 6 7 _ m mmm EJee Nme j Default 0 Initial value is 00h BRDREV Register Description Board Assembly Revision Register Address 2001 7 6 5 4 3 2 1 orp Ree 1 2 3 e s 6 7 Lis j Jj _ sb Name A Default 0 o Initial value is 00h e PLDREV Register Description Board PLD Firmware Revision Register Address 2002 Pi ee eee eee
8. RSER5 O lt LM DOUT 053 CH 1_RXD1 lt RXNIBO 1 E RXD4 3 Cy EXSER 1 DS3 _RXD2 gt RXNIB1_1 _ TA NU T RXNIB2 1 gt DS3 CHH RXNIB3 1 E RXD3 T lt T1 NU qu TXNIBFRAME1 42 1 Q Oa E TSYNC e TSYNC5 z TSSYNCIO 5 TXNIBCLKO 2 T E E TXCLK 2 TCLK5 Delay Ne 7nS BPCLK A E_RXCLK RCLK5 Q RXFRAME1 E RSYNC 2 0 RSYNC5 4 Ox e O RXOUTCLK1 C TXINCLK1 5 GCR_bit 0 DS3SET_bit3 bit 3 6 DS3SET bit 1 Figure 18 Page 43 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor Section10 PQ MDS T1 PLD control signals routing PLD mapped control signal routing used to configure PQ MDS T1 on board T1 Elor DS3 T3 framers and LM card to various operation modes Internal interconnections control provided by corresponding control registers see 3 3 PLD Control Register Description This routing represented in the Figure 19 Figure 22 CSR 1 544MHz 2 048MHz REFCLKIO STATE 3 STATE Bit C SYSCLK_TR 1 544MHz 2 048MHz RSYSCLK 16 384MHz BPCLK p
9. TIRST 0 Enables normal operation mode 1 Provide RESET signal to DS26528 device Page 12 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com freescale e CSR Register Name CSR Register Description DS26528 MCLK and REFCLKIO Source Register Address 2004 Reset value is 00h PLD Bit amp L se MSB Lame 38 18 Default 0 0 L9 gt PLD Bits 0 and 1 DS26528 MCLK Source MSRC 0 1 00 Drive MCLK with the 1 544MHz clock 10 Drive MCLK with 2 048MHz clock xl MCLK connected to GND Bits 6 and 7 0526528 REFCLKIO Source RCSRC 6 7 00 Drive REFCLKIO with the 1 544MHz clock 10 Drive REFCLKIO with the 2 048MHz clock x1 Tri state REFCLKIO REFCLKIO pin OUTPUT Page 13 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor e SYSCLK TR Register Name SYSCLK TR Register Description 0526528 TSYSCLK RSYSCLK Source Register Address 2005 Reset value 1s 00h T 6 __ ___ Default 0 0 PLD Bits 0 and 1 DS26528 Port 1 TSYSCLK Source 150 TS1 00 Drive TSYSCL
10. Table 5 Cosment 6 2008 TCSR2 Drive 5 8 with REFCLKIO 2009 TSYNCSI 0x40 TSYNCI 8 are Output TSER1 8 are Tri state Disconnected 200A DS3SET 0x05 Enables the DS3 framer Transmit Output Drivers DATA bus Nibble normal mode configured 200B GCR 0x05 DS3 E3 external interface type selected SLIC SLAC card constantly RESET and disconnect from Host TDM Page 23 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD 58 Austin TX 78735 www freescale com Tey 2 freescale semiconductor 4 4 DS3 serial mode possible scenario The corresponding data clock flow for 1 channel represented in the Figure 5 setting PLD for this mode represented in the Table 6 TXSERIN _ TXSER 083 CLK 44 736MHz RXSEROUT D_RXD0 RXSER TXSYNC EM 7 RXSYNC D RSYNC RXFRAME RXSERCLK D TCLK RXOUTCLK D_RCLK RXCLK RXNIBCLK DS3 T3 Host PMC FRAMER Connectors Ch 0 Figure 5 Table 6 Comment 6 2008 TCSR2 Drive TCLK5 8 with REFCLKIO 2009 TSYNCSI 0x40 TSYNCI 8 are Output TSERI 8 are Tri state Disconnected 200A DS3SET 0x07 Enables the DS3 framer Transmit Output Drivers DATA bus Serial normal mode configured 200B GCR 0x05 DS3 E3 external interface type selected SLIC SLAC card constantly RESET and disconnect from Host TDM Page 24 of 46 PQ MDS T1 084 00214 2
11. Austin TX 78735 www freescale com gt 2 freescale semwconductor SectionS PQ MDS T1 module floor plan The module realized as PMC form factor mezzanine card enclosed all mentioned above components besides SLIC SLAC LM card This add in card could be connected to the board through special LM connector PQ MDS T1 layout represented in the following Figure 7 and 8 Draft represented in the Figure 7 assumes that the external Add in Card enclosed 8 RJ 45 female connectors provide standard 1 1 interface while interconnect with PO MDS T1 module by extra mini edge card socket The advantage of the solution that the PQ MDS T1 module complies with PMC mezzanine card height standard without SLIC SLAC LM card assembled Figure 8 represented side view of the assembly In case when PQ MDS PIB board with PQ MDS T1 module and LM card assembled on it are inserted into the ATCA enclosure it s occupy two adjoining slots Figure 9 represented CS assembly while Figure 10 represented PS assembly of the module Figure 11 represented CS assembly of the Add in Card with 8 RJ 45 connectors which targeted to provide 8 1 1 standard connectors Page 27 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semiconductor PMC connectors O Extra PMC connector
12. PLD Bit 1 26 1 1 __ 2 3 4 5 6 7 _ X Name 7 Default 0 0 Initial value is 00h Page 11 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor PINSET Register Name PINSET Register Description DS26528 Configuration Pin Settings Register Address 2003 Reset value is 00h BB T 2 MSB Name Bici RE Dear 9 o o o o 1 0 o PLD Bit 0 DS26528 DIGIOEN PIN 0 Drive DS26528 DIGIO ENABLE pin Low Tri state all DS26528 digital I O pins if JTRST is low 1 Drive DS26528 DIGIO ENABLE pin High Normal operation Bit 1 DS26528 TXEN PIN 0 Drive DS26528 TX ENABLE pin Low Tri state TTIP and TRING 1 Drive DS26528 TX ENABLE pin High Normal operation drive TTIP and TRING with data Bit 5 DS26528 OUT_EN 0 Enables normal operation mode 1 TRI State B TXCLK RXCLK TDM signals to avoid these signal s contention in case of operating with MPC8360E MDS PB host board when its on board GETH interface is active Bit 6 0526528 JTRST 0 Enables normal operation mode 1 Provide TRST signal to DS26528 device Bit 7 0526528 RST
13. Setting PLD for this mode represented in the Table 4 2 048MHZ TXDA RXDA TSYNCA RSYNCA RCLKA TCLKA Host PMC Connectors 2 048MHz Figure 3 Table 4 Comment Framer DIGIO and TXEN pins are active Drive MCLK and REFCLKIO with 2 048MHz Drive TSYSCLK and RSYSCLK with 2 048MHz Not using transmit side elastic store TSSYNCIO pin Output 6 2008 TCSR2 Drive TCLKS 8 with 2 048MHz 2009 TSYNCSI 0x00 TSYNCI 8 are Output TSERI 8 are connected to Host TDM TXD A H correspondingly 200A DS3SET 0x00 Disables the 1553 framer Transmit Output Drivers 3 state DATA bus Nibble normal mode configured 200B GCR 0x00 TI El external interface type selected Drive SLIC SLAC card with 1 544M Hz and disconnect from Host TDM Page 22 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD 58 Austin TX 78735 www freescale com 4 freescale semiconductor 4 3 DS3 nibble mode possible scenario The corresponding data clock flow for 1 channel represented in the Figure 4 setting PLD for this mode represented in the Table 5 TXD 0 3 D TXD 0 3 0 3 053 44 736MHz RXD 0 3 D_RXD 0 3 0 3 D TSYNC TXNIBFRAME TXNIBFRAM RXSYNC D_RSYNC RXFRAME TXNIBCLK D TXNIBCLK RXCLK RXCLK RXNIBCLK DS3 T3 Host PMC FRAMER Connectors Ch 0 Figure 4
14. XRT79L72 from Exar Co PLD EPM3512AFC256 7N from Altera Page 7 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 4 2 freescale semiconductor Section2 PQ MDS T1 module Block Diagram PQ MDS TI1 Block Diagram represented in the Figure 1 34 368MHz 5 CH 0 Transmite OSCILLATOR 1 XRT79L72 CH 0 Receive DS3 T3 FRAMER 44 736MHz 40 5 CH 1 Transmite Seine 40 5 Receive SERIAL NIBBLE 7 DATA CHANNEL 0 SERIAL NIBBLE DATA CHANNEL 1 CONTROL TXD1 RXD1 TXD2 RXD2 TXDS RXD3 TXDA RXD4 TXD5 RXD5 TXD6 RXD6 TXD7 RXD7 TXD8 RXD8 TXDA RXDA TXDB RXDB TXDC RXDC TXDD RXDD TXDE RXDE TXDF RXDF TXDG RXDG TXDH RXDH CH 1 CLK SYNC RSYNCA RCLKA TSYNCA TCLKA RSYNCG RCLKG TSYNCG TCLKG RSYNCH RCLKH TSYNCH TCLKH MASTER CLOCK 1 544MHz OSCILLATOR 16 384MHz OSCILLATOR MDS PIB PMC CONNECTORS LOCAL BUS SELECTED TDM CHANNEL SPI interface LM CARD CONNECTOR
15. through Host Local Bus interface Power supply provided from PQ MDS PIB 1 4 PO MDS TI main functions support 1 4 1 Octal T1 E1 J1 Framer Octal T1 E1 J1 18 a single chip 8 port framer and line interface unit LIU combination for El and applications Each port is independently configurable supporting both long haul and short haul lines The main features are e Eight Complete 1 El or 71 Long Haul Short Haul Transceivers LIU plus Framer e Independent El or Selections for Each Transceiver e Internal Software Selectable Transmit and Receive Side Termination for 100Q Twisted Pair 1100 Twisted Pair 1200 E1 Twisted Pair and 750 Coaxial Applications e Crystal Less Jitter Attenuators can be selected for Transmit or Receive Path The Jitter Attenuator meets ETSI CTR 12 13 ITU G 736 G 742 G 823 and AT amp T PUB 62411 e External Master Clock can be Multiple of 2 048MHz or 1 544MHz for T1 J1 or 1 operation This Clock 15 Internally Adapted for 1 or 1 Usage in the Host Mode e Receive Signal Level Indication from 2 5dB to 36dB in 1 Mode and 2 5dB to 44dB in El Mode in Approximate 2 5dB Increments Transmit Open and Short Circuit Detection LIU LOS in Accordance with G 775 ETSI300233 and T1 231 Transmit Synchronizer Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor Port Alarm Detection and Insertion T1 Framing Formats of D4 SLC 96 a
16. 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com z freescale semiconductor DS26528 Common RSYSCLK TSER1 DS26528 Ch 1 RSER1 TSYNC1 RSYNC1 RCLK1 RM RFSYNC1 DS26528 Common TSSYNCIO PQ MDS T1 1 544MHz OSCILLATOR 1 544MHZ 2 048MHz 214 Ground I O s 1 544MHz CSR 2 048MHz REFCLKIO I iQ 0 1 544 2 posa SYSCLK_TR BPCLK 4 16 384 2 OSCILLATOR 16 384MHZ Ga 2 048MHz 16 384MHZ 1 544 2 TCSR 2 048MHz io 16 384 2 i _ _ 1127 _ 1 544MHz 2 048MHz TSYNCS1 RCLK1 REFCLKIO Delay 7nS MPC83xx CPU RSYNC1 Ground Paes Ce TDM Ch A RSYNCA NOT USED 2 048MHZ RCLKA FRAME SYNC 8KHZ USED TO SYNCHRONIZE SLIC SLAC MODEM 1 a ETENIM gt FS FSC RSYNC1 RSYNC2 RSYNC3 O RSYNC4 O RSYNC5 RSYNC6 x RSYNC7 RSYNC8 ERSTES GCR SYNCTSS ast Figure 13 P
17. 3 CH 0 TXD2 D TXNIB1_0 2 0 053 CH 0_TXD3 22 TXNIB3_0 D_TXD3 0 053 CH 0_RXD0 4 D_RXDO 2 RSER4 LM DOUT 083 CH 0 RXD1 lt D RXD4 Cg XNIBO 0 1 NU 0 4 RXSER 0 053 CH 0_RXD2 D RXD2 RXNIB1_0 T1 NU I RXNIB2 0 x 053 CH 0_RXD3 RXNIB3 0 P D RXD3 lt 0 1 42 0 I D TSYNC TSYNC4 74 TSSYNCIO x E TXNIBCLKO 0 2 T D TXCLK 2 TCLK4 Delay o Oa 7nS O BPCLK 3 D RXCLK e 9 RCLK4 e 2 RXFRAMEO D_RSYNC 2 0 RSYNC4 lt Ox RXOUTCLKO 2 On TXINCLKO GCR_bit 0 DS3SET_bit3 GCR bit3 6 DS3SET_bit 1 Figure 17 Page 42 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com f 1 ru reescaie semiconductor DS3 1 E TXDO 0 pe TDM_TSER5 To TSYNCS1 reg LM_DIN DS3 CH 1_TXD1 TXD1 gt TXNIBO 1 aes TXSER 1 083 CH 1 TXD2 gt gt TXD2 TXNIB1 1 Zen TXNIB2 1 TXD3 TXNIB3 1 E TXD3 rem 053 CH 1 RXDO E RXDO
18. 3 2 PLD Register 10 3 3 PLD Control Register Description M 8 11 Section4d PQ MDS T1 Configuration scenario s 21 4 1 mode possible scenario B 7 21 4 2 El mode possible 8 22 4 3 053 nibble mode possible 23 4 4 053 serial mode possible scenario 24 4 5 SLIC SLAC LM card possible 25 SectionS PQ MDS T1 module floor plan 27 Section6 PQ MDS T1 DS3 T3 Functionality 30 Section7 PQ MDS T1 T1 E1 J1 Functionality 34 SectionS PQ MDS T1 PMC connectors pin mapping 36 Section9 PQ MDS T1 PLD TDM channels routing 40 Section10 PQ MDS T1 PLD control signals routing 44 Page 2 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor Sectionl General Information 1 1 Introduction The PQ MDS T1 T1 E1 DS3 T3 SLIC SLAC Subscriber Line Interface Control
19. 384MHZ 8 192MHz OSCILLATOR gt 2 048MHz 16 384MHz 5 gt 4 096MHz Optional Figure 24 Page 46 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006
20. 9 AD9 DRXD2 50 SS Psi GND GND TxD 7 _53 Ap6 41 AD _55 AD4 GRXp 56 GND 57 33 f 58 ADB GTSIN 59 aboa 1 60 0006 _ 61 abo J ef 5 5V 63 GND GND 64 REQ64 SPFDOUT amp Page 36 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com gt z freescale semwconductor Continue Table 8 Function Function Function Function 1 DV 12V 2 Optional DFT usage 3 TMS Optional DFTusage 4 TDO Optional DFTusage obs Druan 6 GND 7 GND GND 8 5 y 9 PCLRSRVD 568 J 11 BUSMODE2 12 33V 33V C 13 RST GTxpo 14 BUSMODE3 15 33V 33V 16 BUSMOE4 17 PME 18 GND GND 9 19 AD0 5 10 AD 21 GND GND 22 AD6 9 23 BTXD0 24 33V 33V y 25 105 26 27 33V 33V 28 _ 29 8 DTXD2 30 GND GND 31 Abdio 32 33 GND GND J 34
21. CH 4 CH 3 n CH 2 CH 1 Figure 11 Page 32 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com z freescale semwconductor PQ MDS T1 DS3 T3 Functionality Block diagram of the interconnections between XRT79L72 and Host CPU MPC83xx family 1 channel represented 1 the Figure 12 EI 2 _ RXNIB 1 i T RXNIB 0 22 010 RXFRAME RXCLK RXNIBCLK RXOUTCLK O OE a Aa TXNIB2 TXNIBI an TXNIBO I I TXSER eq __ ANN wO TXNIBCLK I I oit E ee SURE M ye TXFRAME 1 2111 NIBBLE SERIAL MODE SELECT DS3SET bit 1 HOST CPU E CLKOUT NORMAL LOCAL TIMING MODE SELECT DS3SET bit 3 XRT79L72 4 Figure 12 Page 33 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com T 2 freescale Semiconductor Section7 PQ MDS T1 T1 E1 J1 Functionality Block diagram of the interconnections between DS26528 and Host CPU MPC83xx family 1 channel represented in the Figure 13 Page 34 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February
22. Figure 1 Page 8 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor Section3 PQ MDS T1 Address map 3 1 General address space Accordingly to Figure 1 the following components T1 E1Framer DS3 T3 Framer and PLD are mapped on the Host Local Bus to provide theirs SW control Control of the LM card provided through Host independent SPI interface The corresponding memory map represented in the Table 1 Table 1 Address range Data bus bit 1 1 A19 A31 n 0000 1FFF 0526528 T1 E1 J1 transceiver A12 A0 Board identification control and 16 31 1 STRE ________ O DS3 T3 4 8000 FFFF L ANNUO m XRT79L72 DS3 T3 transceiver A14 A0 5 LMeard MPI SPI serial Universal Voice Board Line Modue Page 9 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com gt freescale semwconductor 3 2 PLD Register Map On board control PLD register map represented in the Table 2 Table 2 6 2005 SYSCLK TR Write Read TI ElFramerTxand Rx SYSCLK Source Framer TCLK Source Ports 1 4 2007 TCSRI Write Read 1 544MHz 2 048MHz TCLKi
23. K with the 1 544MHz clock 10 Drive TSYSCLK with the 2 048MHz clock 01 Drive TSYSCLK with 16 384MHz clock 11 Drive TSYSCLK with DS26528 port BPCLK Bits 7 0526528 Port 4 RSYSCLK Source RSO RS1 00 Drive RSYSCLK with the 1 544MHz clock 10 Drive RSYSCLK with the 2 048MHz clock 01 Drive RSYSCLK with 16 384MHz clock 11 Drive RSYSCLK with DS26528 port BPCLK Page 14 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor e SYNCTSS Register Name SYNCTSS Register Description D826528 TSSYNCIO Source Register Address 2006 Reset value 1s 00h UNE UN PIDB 1 ___ j MB Name TERT s 9 9 9 9 o 1 9 fo PLD Bit 0 to 3 D826528 TSSYNCIO Source Select TSRC 0 3 0000 Not using transmit side elastic store tri state PLD pin connected to TSSYNCIO weak pull down TSSYNCIO pin OUTPUT 0001 Drive TSSYNCIO with RSYNC 1 08h 1001 Drive TSSYNCIO with RSYNC 2 09h 0101 Drive TSSYNCIO with RSYNC 3 0Ah 1101 Drive TSSYNCIO with RSYNC 4 0Bh 0011 Drive TSSYNCIO with RSYNC 5 0Ch 1011 Drive TSSYNCIO with RSYNC 6 0Dh 0111 Drive TSSYNCIO with RSYNC 7 OEh 1111 Drive TSSYNCIO with RSYNC 8 0Fh Note When driving TSSY
24. NC3 F_RSYNC RSYNC6 Ox GCR bit 0 GCR bit3 6 GCR bit 0 GCR bit3 6 Figure 15 DS3 NU DS3 NU G TXD0 p 5 7 To TSYNCS1 reg H TXD0 m TSERS8 To TSYNCS1 053 NU 053 NU GRO e ES RSER7 H_RXDO 2 0 RSER8 a Oe DOU 27 DS3 NU G TSYNC g TSYNC7 e TSYNC8 a cu 5 O SSYNCIO O SSYNCIO 053 NU 093 NU TXCLK 7 7 gt H_TXCLK TCLK8 Delay Delay Hs Ont BPCLK m BPCLK 093 NU 093 NU G_RXCLK e 2 RCLK7 H_RXCLK e 2 RCLK8 Ox 053 NU 053 NU G_RSYNC e P RSYNC7 lt RSYNC e 2 0 RSYNC8 Ox GCR bitQ GCR bit3 8 GCR_bit 0 GCR bit 3 6 ae Figure 16 Page 41 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 22 528 le reescaie semiconductor DS3 CH 0 TXDQ m D x C TDM_TSER4 TSYNCS1 reg p gt LM_DIN 053 CH 0_TXD1 D TXD4 26 0 T1 NU O _0 05
25. NCIO with RSYNCx the corresponding DS26528 port should be configured such that RSYNCXx is an output RIOCR 2 0 Page 15 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor e TCSRI Register Name n 1 to 4 Register Description 0526528 TCLK Source Ports 1 4 Register Address 2007 Reset value 1s 00h PLD Bit 2 ES TDS40 TDS41 Default 0 0 0 PLD Bits 0 1 DS26528 Port 1 TCLK Source TDS 10 11 00 Drive TCLK1 with the 1 544MHz clock 10 Drive TCLK1 with the 2 048MHz clock 01 Drive TCLK1 with RCLKI 11 Drive TCLK1 with REFCLKIO Bits 2 3 DS26528 Port 2 TCLK Source TDS 20 21 00 Drive TCLK2 with the 1 544MHz clock 10 Drive TCLK2 with the 2 048MHz clock 01 Drive TCLK2 with RCLK2 11 Drive TCLK2 with REFCLKIO Bits 4 5 DS26528 Port 3 TCLK Source TDS 30 31 00 Drive TCLK3 with the 1 544 clock 10 Drive TCLK3 with 2 048MHz clock 01 Drive TCLK3 with RCLK3 11 Drive TCLK3 with REFCLKIO Bits 6 7 DS26528 Port 4 TCLK Source TDS 40 41 00 Drive TCLK4 with the 1 544MHz clock 10 Drive TCLK4 with 2 048MHz clock 01 Drive TCLK4 with RCLK4 11 Drive TCLK4 with REFCLKIO Page 16 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 Febr
26. S T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor 1 5 PO MDS TI module control functions module control functions implemented through Local Bus mapped set registers incorporated into the on board PLD device The corresponding software has the opportunity to control 1 framer setting 2 DS3 T3 framer setting 3 SLIC SLAC modem LM card setting 4 Additional functions like Board identification number Board revision number PLD revision number TI El Framer MCLK and REFCLKIO Source Framer Configuration Pin Settings Framer Tx and SYSCLK Source 1 1 Framer TSSYNC Source 1 1 Framer TCLK TSYNC RSYNC TSER RSER sources 5 SLIC SLAC modem LM card TDM channel selection 6 and or DS3 E3 modem disabling 1 6 PO MDS TI module visual indicators Operating mode 1 1 DS3 T3 LED s are populated on the board RLOS LED s provide Receive Syncro Clock Loss visual indication of the each framer s corresponding channel LED Connection used to confirm correct and reliable interconnection between PQ MDS T1 and the PQ MDS PIB boards 1 7 PO MDS TI module main circuit elements The following main circuit elements are used in the module design Framer DS26528 from Dallas Semi DS3 T3 Framer
27. TION TP69 049 TP68 TP67 TP66 AT GND 12V 3V3 GP51 j O000000000000000000000000Cf n 000000000000000000000000 O OD25 ooooooooooooooooooooooooaQn TEE E EE UE E EE EE E EE EE EE E E EE ooo 4 d 95 1 5 F Be eee B e gl SLIC SLAC Module assembled Cim CH1 TR CH1 RC Figure 9 Page 30 of 46 PQ MDS T1 084 00214 20 Last Update 9 February 2006 Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com C104 C103 co RLE8 1018 RLOS8 om 1016 ES 057 LD15 RLF6 F 1014 RLOS3 p7 RLF2_ pg RLOS2 mee 1 5 Version 1 1 Freescale Semiconductor Inc 6501 William Cannon Drive West MD 58 Austin TX 78735 www freescale com 2 freescale semiconductor 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 T P M K H F D B U3 UU TIX ZUA 0 0 212 o gt O 0 zJ C120 AF AE R128 Figure 10 Page 31 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semiconductor 0 uUum 4 BRUM a P2 GND CH 5 CH 6 CH 7 CH 8
28. UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale 4 5 SLIC SLAC LM card possible scenario The corresponding data clock flow for Channel E represented in the Figure 6 Setting PLD for this mode represented in the Table 7 2 048MHZ 2 048 2 048MHZ E TXD0 LM Card Connector E_TXCLK E RXCLK SPI CLK SPI DIN SPI SEL IRQY E_TSYNC E_RSYNC Host PMC Connectors Figure 6 Page 25 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor Table 7 I 5_ 2008 TCSR2 Drive TCLK5 8 with 2 048MHz 2009 TSYNCSI 0x00 TSYNCI 8 are Output TSER1 8 are connected to Host TDM TXD A H correspondingly 3 Disables the 053 framer Transmit Output Drivers 3 state DATA bus Nibble normal mode configured 200B 0x62 external interface type selected Drive SLIC SLAC mom card with EI BPCLK and connect to Host TDM Channel E instead of T1 E1 framer channel 5 Page 26 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58
29. V 2 Ap6 _ 23 Ap5 __ a ADS _ 25 AD ARXCIK 16 GND GND mao RS _ 29 ADSI A TXCLK 30 AD0 _ 31 49 GND 34 HTXD ______ _ 35 __ 47 ETSYN 36 AD _ 37 __ ERXDO 158 GND GND 39 vido 33V ao _ 41 ADs ETXD 12 aR 43 CRXCLLK 44 GND GND 45 GND GND 47 AD39 48 ADN 49 GND 52 AD6 5 54 982 n 57 33V 18 AD2 759 PCLRSRVD D RXD0 60 SPESEL SL GND 63 _______ Ca Wo n D_RX P D T AELK PCI RSRVD Page 38 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com gt z freescale semwconductor Continue Table 8 ree Function Function Function HTPER LB LBDO 1801 6 _ 1 HH p 5 vo 6 10 7 10 LBD 18 10 BD 1 rO ro pumam I 29 10 18 2 9 10 GND X LL vo 20001 _ 533
30. _TSER3 OL p eo RSER3 gt OUTPUT gt O 3 RSYNC4 lt TDM_TSER4 QM e RSER4 gt OUTPUT TO 3 STATE 5 TDM TSER5 OM e 5 v EO RSER5 v EC RSYNC6 TDM TSER6 On gt O RSER6 O OUTPUT gt C 3 STATE RSYNC7 lt TDM_TSER7 TSER7 G RSER7 n OUTPUT gt O 3 STATE RSYNC8 TDM_TSER8 Ou z TSER8 RSER8 0 gt O x Bit 1 NEN Bit 0 Bit 7 NEN Bit 6 Figure 22 Page 45 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com T 2 freescale sermmoonductor Board RESET signals generated by PLD mapped glue logic like shows in the Figure 23 User has opportunity to RESET each framer SLIC SLAC module separately or provide general SW HW RESET by control corresponding bits in the PLD mapped registers any time he need it DS26528_RST PINSET Bit 7 HOST RESET AUX HW RST GR Bu gt LM_RST _Bit7 gt GCR Bit 2 id XRT79L72 RST 1 DS3SET_Bit 7 gt Figure 23 PLD internal divider like shows in the Figure 24 used to provide 8 192MHz 4 006MHz and 2 048MHz clock to corresponding parts The source of the divider is external oscillator 16 384MHz p 16
31. age 35 of 46 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West OE58 Austin TX 78735 www freescale com gt gt freescale semwconductor Section8 PQ MDS T1 PMC connectors pin mapping Pin mapping of the PQ MDS T1 mezzanine card set connectors used to interface to PQ MDS PIB board represented the Table 8 Table 8 Standard Module Note Standard Module Note fexto Function ______ function dm Optional DFT usage 12 12V Check m gt oss 3 GND 4 GRSYNC _____ 5 2 7 5 1 __ 8 SV 9 MNT PCHSRVD C TSYNC uj GND 33Vax B 4 GND 7 15 GND GND 6 CRD 17 REQH GIXCLK 18 5 11 19 33V 20 ADI 21 22 J s 23 ADS GND _ _ 25 GND GND 26 __ _ 27 AD2 28 ADD mm _3 33V 91 ADI7 s FRAME ERXDL aN _35 GND GND 36 37 DEVSELA 4 47 239 GND _41 PCERSRVD 242 PCLRSRVD _ 43 PAR GND _ 5 6 _ 47 ADI BRxDO 48 ADI ______ _ 4
32. ale com 2 freescale semwconductor e TSYNCSI Register Name TSYNCSI n 1 to 4 Register Description D826528 TSYNC and TSER Source Ports 1 8 Register Address 2009 Reset value 1s 00h PLDBit 1 1 5 1 4 1 LSB Name Setar rs TSERSRC Defaut 0 PLD Bit 0 DS26528 Port 1 8 TSYNC State TSSTATE 0 0 TSYNC1 8 3 State TSYNC1 8 are OUTPUT 1 TSYNCI are INPUT Bit 1 DS26528 Ports 1 8 TSYNC Source TSSRC 1 0 TSYNCI 8 are connected to RSYNCI 8 correspondingly 1 TSYNCI 8 are connected to GND Bit 6 DS26528 Ports 1 8 TSER State TSERSTATE 6 0 TSERI 8 are INPUT 1 TSERI 8 are 3 State Disconnected Bit 7 DS26528 Ports 1 8 TSER Source TSERSRC 7 0 TSERI 8 are connected to Host TDM A H correspondingly 1 TSER1 8 are connected to RSER1 8 correspondingly Page 18 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor e DS3SET Register DS3SET Register Description DS3 E3 Framer Configuration pin setting Register Address 200A Reset value is 00h 1 PLD Bit ts 6 Deae 9 9 9 9 o o fo fo PLD Bit 0 XRT79L72 TXON pin 0 Disables the Transmit Output Drivers In this setti
33. ary 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com T 2 freescale Section4 PQ MDS T1 Configuration scenario s 4 1 1 mode possible scenario The corresponding data clock flow for 1 channel represented in the Figure 2 Setting PLD for this mode represented 1 the Table 3 1 544MHZ TXDA RXDA TSYNCA RSYNCA TCLKA Host PMC Connectors 1 544MHz Figure 2 Table 3 Comment Setting 1 Framer DIGIO and TXEN pins are active Drive MCLK and REFCLKIO with 1 544MHz Drive TSYSCLK and RSYSCLK with 1 544MHz Not using transmit side elastic store TSSYNCIO pin Output Drive TCLK1 4 with 1 544MHz 2008 TCSR2 Drive TCLKS 8 with 1 544MHz 2009 200 DS3SET TSYNCSI 0x00 PQ MDS T1 084 00214 2UM TSYNCI 8 are Output TSERI 8 are connected to Host TDM TXD A H correspondingly Disables the DS3 framer Transmit Output Drivers 3 state DATA bus Nibble normal mode configured external interface type selected Drive SLIC SLAC card with 1 544MHz and disconnect from Host TDM Page 21 of 46 Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com gt 2 4 2 mode possible scenario The corresponding data clock flow for 1 channel represented the Figure 3
34. equirements Detects and Clears LOS as per G 775 Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation Compliant with jitter transfer template outlined in ITU G 751 G 752 6 755 and GR 499 CORE 1995 standards Meets ETSI TBR 24 and GR 499 Jitter Transfer Requirements On chip B3ZS HDB3 encoder and decoder that can be either enabled or disabled On chip clock synthesizer provides the appropriate rate clock from a single 12 288 MHz Clock On chip advanced crystal less Jitter Attenuator Jitter Attenuator can be selected 1 Receive or Transmit paths 16 or 32 bits selectable FIFO size Meets the Jitter and Wander specifications described 1 T1 105 03b ETSI TBR 24 Bellcore GR 253 and GR 499 standards Jitter Attenuator can be disabled Maximum power consumption 1 7W DS3 framer supports both M13 and C bit parity Page 5 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semiconductor DS3 framer meets ANSI T1 107 and T1 404 standards Detects OOF LOF AIS and RDI FERF alarms Generation and Insertion of FEBE on received parity errors supported e Automatic insertion of RDI FERF on alarm status framer meets G 832 G 751 standards Framers can be bypassed Page 6 of 46 PQ MD
35. ler Subscriber Line Access Controller module serves as a platform for S W and H W development around the 83xx host device Using MPC83xxE MDS PB PQ MDS PIB on board resources and PQ MDS T1 module T1 E1 DS3 T3 and or Voice Over IP dual interfaces a developer able to load his code run it set breakpoints display memory and registers and debug his own proprietary software This module may be used as an evaluation and demonstration tool 1 e application S W may be programmed into MPC83xxE MDS PB on board flash memory and run at university s sites exhibitions etc 1 2 PO MDS TI module features PMC mezzanine card form factor Compatibility with PQ MDS PIB 8 EI TI channels 2 DS3 T3 channels Legerity Line Module Le71 HR0826 LM interconnection compatible connector to provide all the necessary dual channel voice interface functions from the high voltage subscriber line to the CPU digital interface Full board SW programmable control Network Interface Protection for Over voltage and Over current Events Page 3 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com 2 freescale semwconductor 1 3 PO MDS TI Host interface PQ MDS T1 interconnects with PQ MDS PIB through PMC standard connectors set 8 Host TDM channels operate with the card PQ MDS TI1 SW control provided
36. nd ESF Support 1 G 704 and CRC 4 Multiframe TI to El Conversion Page 4 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com T 2 freescale Semiconductor 1 4 2 Dual DS3 T3 framer Dual DS3 E3 chip include Framing Line Interface Unit with Jitter Attenuator A flexible parallel microprocessor interface 1s provided for configuration and control The main features are Integrated T3 E3 Line Interface Unit ntegrated Jitter Attenuator that can be selected either in Receive or Transmit path Flexible integrated Clock Multiplier that takes single frequency clock and generates either DS3 or E3 frequency e Operates in either in Serial or the Nibble Parallel mode Contains on chip 16 cell FIFO configurable in depths of 4 8 12 or 16 cells in both the Transmit TxFIFO and Receive Directions RxFIFO Contains on chip 54 byte Transmit and Receive OAM Cell Buffer for transmission reception and processing of OAM Cells Supports M13 and Parity Framing Formats Supports DS3 E3 Clear Channel Framing Includes PRBS Generator and Receiver Supports Line Cell and PLCP Loop backs Interfaces to 8 Bit wide Intel Motorola or PowerPC On chip Clock and Data Recovery circuit for high input jitter tolerance Meets E3 DS3 Jitter Tolerance R
37. ng the TTIP and TRING output pins will be tri stated 1 Enables the Transmit Output Drivers if the individual register bits are set to 1 In this setting the TTIP and TRING output pins will be enabled Bit 1 XRT79L72 NibbleIntf pin 0 configures each of Transmit Payload Data Input Interface and the Receive Payload Data Output Interface blocks to operate 1n the Nibble Parallel Mode 1 Configures each of Transmit Payload Data Input Interface and the Receive Payload Data Output Interface blocks to operate the Serial Mode Bit 2 XRT79L72 DBEN pin 0 Tri states the Bi directional Data Bus 1 Enables the Bi directional Data bus Bit 3 XRT79L72 MODE 0 Enables normal operation mode 1 Enables local timing mode CLKOUT used as TXINCLK Bit 6 XRT79L72 TRST 0 Enables normal operation mode 1 Provide TRST signal to XRT79L72 device Bit 7 XRT79L72 RST 0 Enables normal operation mode Provide RESET signal to XRT79L72 device Page 19 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com freescale e GCR Register Name GCR Register Description General Control Register Register Address 200B Reset value 15 00h mi b Name LCC3 _ Default 0 PLD Bit 0 Board External In
38. terface Type BEIT 0 Enables 1 1 external interface type 1 Enables DS3 E3 external interface type Bit 1 SLIC SLAC Legerity Card Clock Enable LCE 0 Line Module Le71HR0826 clock disabled Log 0 1 Drive Line Module Le71 HR0826 with the 1 1 framer BPCLK signal Bit 2 SLIC SLAC Legerity Card Reset LRST 0 Enables normal operation mode 1 Provide RESET signal to Line Module Le71 HR0826 Bit 3 6 SLIC SLAC Legerity Card Channel Connection LCC 0 3 0 Disconnect Line Module Le71 HR0826 from Host TDM default 0001 LM card connected to Host TDM channel A instead of T1 E1 framer channel 1 1001 LM card connected to Host TDM channel B instead of T1 E1 framer channel 2 0101 LM card connected to Host TDM channel C instead of T1 E1 framer channel 3 1101 LM card connected to Host TDM channel D instead of T1 E1 framer channel 4 0011 LM card connected to Host TDM channel E instead of T1 E1 framer channel 5 1011 LM card connected to Host TDM channel F instead of T1 E1 framer channel 6 0111 LM card connected to Host TDM channel instead of T1 E1 framer channel 7 1111 LM card connected to Host TDM channel instead of T1 E1 framer channel 8 Bit 7 Board RESET BRST 0 Enables normal operation mode 1 Provide RESET signal to the following board populated components 1 1 framer DS3 T3 framer and LM card Page 20 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 Febru
39. uary 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freescale com L z freescale semwconductor e TCSR2 Register Name TCSR2 n 5 to 8 Register Description D826528 TCLK Source Ports 5 8 Register Address 2008 Reset value 1s 00h LBBi 7 6 5 4 3 2 1 PLD Bit 1 2 3 4 5 6 _ IB LSB 10581 Defaut 0 PLD Bits 0 1 DS26528 Port 5 TCLK Source TDS 50 51 00 Drive TCLKS with the 1 544MHz clock 10 Drive TCLKS with the 2 048MHz clock 01 Drive TCLK5 with RCLK5 11 Drive TCLK5 with REFCLKIO Bits 3 2 DS26528 Port 6 TCLK Source TDS 60 61 00 Drive TCLK6 with the 1 544MHz clock 10 Drive TCLK6 with the 2 048MHz clock 01 Drive TCLK6 with RCLK6 11 Drive TCLK6 with REFCLKIO Bits 5 4 DS26528 Port 7 TCLK Source TDS 70 71 00 Drive TCLK7 with the 1 544 clock 10 Drive TCLK7 with the 2 048MHz clock 01 Drive TCLK7 with RCLK7 11 Drive TCLK7 with REFCLKIO Bits 7 6 DS26528 Port 8 TCLK Source TDS 80 81 00 Drive TCLKS with the 1 544MHz clock 10 Drive TCLKS with 2 048MHz clock 01 Drive TCLK8 with RCLKS 11 Drive TCLK8 with REFCLKIO Page 17 of 46 PQ MDS T1 084 00214 2UM Version 1 1 Last Update 9 February 2006 Freescale Semiconductor Inc 6501 William Cannon Drive West MD OE58 Austin TX 78735 www freesc
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