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AGX User`s Manual

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1. COL 1 AN COL 2 4 3 6 ADSmartlO Signal Cross Reference The ADSmartIO microcontroller serves many functions in the AGX The following table illustrates how the microcontroller ports are utilized for ADSmartIO functionality on the AGA Entries in parentheses indicate indirect connections to the listed pin e g through voltage dividers or additional circuits Signals with conventional protection circuits are considered directly connected I input O output Pot Pin Tpe Fumetion Keypad A D or digital I O Analog inputs ANINI 3 Page 34 ADS document 110115 40012 preliminary Applieddata net 4 4 4 4 1 4 4 2 Entitet Greywin Spini Feature Reference Function Port Pin PBI IO BE mw 1 PBs O A9 IRQ OPU 2 PB4 SFM PBS RX MOSI SPI communication PB6 TX MISO withcontroller CPLD LPB7 OK Keypad rows or digital I O PCS I Pixeleloek wg ooo IO PDO O Passive panel enable PNL_ENA PDI PD2 I Powerenable from system Keypad column or digital I O Keypad rows or digital I Os Audio The AGX includes an AC97 codec for stereo audio input and output Electrical specifications for the audio system are listed in section 6 2 10 Microphone Pre amps The AGX supports the connection of a stereo electret microphone to the MIC_R and MIC_L inputs on J10 The audio signals run thr
2. 76 LPCLK O 77 LBIS O 78 CS22 O Controller CPLD chip select 79 CH O 6USBchipselecr 80 C4 O Etheretchipselet Real Time Clock RTC The AGX uses the DS1307 real time clock chip to maintain the system date and time when the system is powered down The operating system typically reads the RTC on boot and wakeup and sets the RTC when the system time or date is changed The system communicates with the RTC on the DC bus section 4 5 5 The RTC is powered by a long life 3 V battery As a factory option the battery can be removed from the AGX and the RTC can be powered via the BATPOS input on J40 pin 14 See section 6 2 2 for electrical specifications ADSmartlO ADSmartIO is a RISC microcontroller on the AGX that is programmed with ADS firmware This device provides additional I O functionality for specialized tasks Your application software can configure the standard ADSmartIO for a variety of functions such as digital I O PWM A D FC keypad scan and PS 2 keyboard operation Overview The ADSmartIO controller has four eight pin I O ports named PA PB PC and PD Some of these ports pins are used internally while others are available for user applications See the signal cross reference in section 4 3 6 for details Generally ADSmartIO ports are referenced by port and pin number e g PA2 but I O signals may go by several names based on its functionality See the
3. Applieddata net Embedded Computer Systems AGX User s Manual ADS document 110115 40012 preliminary Applied Data Systems www applieddata net 9140 Guilford Road Columbia MD 21046 USA 301 490 4007 O 2003 ADS Applieddata net Febediog Cogan Span AGX User s Manual About the Cover Image The cover image shows a fully populated Rev 2 AGX Printing this Manual This manual has been designed for printing on both sides of a 8 5x11 inch paper but can be printed single sided as well It has also been optimized for use in electronic form with active cross reference links for quick access to information Revision History The following list summarizes the changes that have been made between released revisions of the manual DESCRIPTION BY first preliminary release Chapter 3 only 7 28 03 ak second preliminary release 10 6 03 ak ADS document 110115 40012 preliminary Page i Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page ii ADS document 110115 40012 preliminary Applieddata net Eebrdieg Computer Fut AGX User s Manual Table of Contents bout the COVER ITIIMe aaa i odo orte tica i Penta this Manta iv Ad DEL Les Op PECES i Revision Esto M e OmM i WAND TOES Oud im RENE c UN ii 1 et ONG EO ended oido dois l I as A e e o aside dus dd l IN EE l E e 0 IO EE l Lee Ee l 12 5 Memo aod
4. Page 42 Discrete I Os This section describes discrete signals on the AGX that can be used for control input or output Digital I Os The ADSmartIO system controller and Epson display controller supply discrete digital I Os on the AGX Each discrete digital signal can be configured as an input or an output The ADSmartIO digital I Os are available on header J14 3 4 12 and are described in section 4 3 3 The seven system controller digital I Os CPLDIOn are available on headers J8 3 4 6 and J14 3 4 12 See section 6 2 7 for electrical specifications When installed the Epson display controller supplies the digital I Os available on header J8 3 4 6 See section 6 2 4 for electrical specifications Analog Inputs The inputs on the ADSmartIO controller can be configured as analog inputs These are known as ANINI to ANING on header J8 3 4 6 See ADSmartIO section 4 3 4 for details In addition one input on the touch panel controller can also be used as an analog input This signal is called ANINO and is found on header J8 3 4 6 Analog Outputs PWM The AGX has two analog outputs These are used to control LCD backlighting and contrast section 4 8 3 Touch Panel The AGX supports four and five wire analog resistive touch panels Five wire panels are a factory option Connect the touch panel to the inputs on connector J3 The touch panel controller can wake the system from sleep section 5 2 4 Electrical details
5. Vee and Vcon are used to control the contrast of passive panels Many passive panels require a positive or negative bias voltage in the range of fifteen to thirty volts to bias the passive LCD display Some displays include a Vee generator and simply require a low voltage analog signal to control the contrast The Vcon output is a PWM controlled output that can be used for this purpose Electrical specifications for Vee and Vcon are listed in section 6 2 4 Using Analog Displays The AGX can support several analog display types when the Epson display controller is installed The signals for VGA and CRT output are available on header J9 3 4 7 For the analog display modes supported these signals are mapped as follows J9 Signal EE A VGA_VSYNC VGA HSYNC Horiz retrace pO A A OC 8 VGA BLUE Blue Chrominance 10 VGA GREEN Green Composite 12 VGARED Rd Lumimance ADS document 110115 40012 preliminary Page 45 Applieddata net AGX User s Manual Feeder Coapite Spem 4 8 5 4 9 4 9 1 4 9 2 Page 46 Developing Display Drivers ADS provides display timings for supported displays on request For displays not yet supported ADS has a panel configuration service to creates panel timings and cable drawings Contact ADS Sales for further details EMI RFI and ESD Protection The AGX board incorporates a number of industry leading features that protect it from electrostatic
6. Page 48 and returned to the Run state by initiating a system wakeup using one of the methods described in section 5 2 3 Architectural Overview and Power Management Features This section provides an overview of the architecture of the AGX power supply and a description of the various features of the AGX power management systems Power Supply Architecture The AGX power supply is laid out as shown in the following diagram Vcc AEN IN ji 3 3V_IN 1 O 2 Les JP2 3 3 V t gt switcher Vddx 3 usd a SW VPERM 1 linear O JP14 Vddi gt Vddi switcher to CPU core Vee 7 Vee SE gt to display 412V IN to backlight inverter connector Vddi is a variable voltage power supply controlled by the XScale I C bus 4 5 5 6 2 2 This voltage scaling feature allows the operating system to manage power consumption over the full range of CPU clock rates Factory options available are indicated by dashed lines in the diagram above The options shown are available for production customers but are outside the scope of this manual Contact your ADS sales representative if you believe one or more of these options is required for your application Specifications for the AGX power supply are listed in section 6 2 2 Subsystem Partitioning The AGX can selectively turn off power to subsystems on the board This load shedding feature can extend batter
7. 485 J1708 logic level serial IIDA USB host client USB and On The Go ports Ethernet CAN bus and TE 4 5 1 Serial Ports The AGX has seven serial ports three from the XScale processor and four from a quad UART The serial ports can be configured as follows Standard Factory options J14 JP5 7 EIA TIA 232 1P10 13 BIA TIA 422 485 11 09 95 V CMOS JP4 J14 EIA TIA 232 SSES J15 U22 IDA 3 3 V CMOS Reader for IrDA XScale UART The XScale processor supplies three standard serial ports The Bluetooth UART is Serial 1 on the AGX the IrDA UART is AGX Serial 2 and the Full featured UART is AGX Serial 3 The Serial 2 IrDA signals are on J15 When Serial 2 is operated in IrDA mode the serial driver should enable the IrDA transmitter with IIDAOn signal The IrDA transceiver is normally mounted on the board 3 2 4 but as a factory option a header can replace the transceiver for cabling to another location Electrical specifications are listed in section 6 2 8 The Serial 2 CTS and RTS serial handshaking signals are XScale GPIO lines that must be controlled by the software drivers when Serial 2 is operated as EIA TIA 232 or 3 3 V CMOS ADS document 110115 40012 preliminary Page 37 Applieddata net AGX User s Manual Feeder Coapite Spem 4 5 2 xix i 3 4 Page 38 Ports that are configured for 3 3 V CMOS operation connect directly to the XScale and should be treated electrically as GPIOs
8. ADS development systems include the Sharp LQ64D343 5V TFT VGA display which draws about one watt and the Xentek LS520 backlight inverter which draws about six watts at full intensity Symbol Parameter Min Typ Max Units Sleep mode power poo JL mw Pide Idle mode power note 9 ed mW Run mode power note 10 o qu AA Turbo mode consumption note 11 mW Notes Power consumption was measured on a fully populated 64 MiB AGX with no peripheral connections under the following conditions 9 System running only the Windows CE desktop predominantly in Idle mode 596 CPU utilization 10 Full 95 100 processor utilization in Run mode achieved by running multiple instances of a graphical application under Windows CE 11 Full 95 100 processor utilization in Turbo mode achieved by running multiple instances of a graphical application under Windows CE ADS document 110115 40012 preliminary Applieddata net Iebedde Computer yata wi System Specifications 6 2 4 Display LCD display panels have a wide range of voltage and data requirements The AGA has a number of adjustable voltages to support these requirements as well as controls for brightness backlight and contrast passive panels only See section 4 8 for further details The AGX has the factory option to install the Epson SID13806 display controller see section 4 8 2 for details The digital I Os listed are
9. PCBAI PCBA2 PCBA3 Address 0 6 PCBA4 PCBAS PCBA 3 3V CARDBON CARDBVCC CARDBIRQ CARDBMWR CARDBIOWR CARDBIORD PCBA7 PCBAS PCBA9 Address 7 10 PCBA10 CARDBMRD CARDB_VS CARDBCE2 CARDBCE PCBDIS5 PCBDI4 PCBD13 Data 11 15 PCBDI2 PCBDII 3 I d EEN EA E RE MEE UA M N PCBD7 PCBD6 PCBD5 Data 3 7 PCBD4 PCBD3 CARDBDETI Card Detect 1 CARDBON 3P3V 3 3 V Power Control 3 4 5 J7 Ethernet Board Connector RJ 45 with integrated magnetics and LEDs Location on board A7 Name ETHPI O JTransmt S ETHP2 O J Transmit O ETHP3 I n n n a C ETHP6 1 fRecive 6 de n ADS document 110115 40012 preliminary Page 17 Applied net AGX User s Manual Devbecdded Exeter Spite 3 4 6 Page 18 I O Analog Inputs USB Function Port Board Connector 2x15 header 2 mm spacing Samtec STMM 115 02 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 115 02 F D 500 Location on board A1 Bl Pin Name Pin Type Description 10 A Graphics controller digital I Os 6 2 4 GC GPIOS 4 10 _ GCGPIO7 6 10 EOD MEE OO LEE E Analog input 4 6 2 AL RAS FARZA Analog inputs 4 6 2 FC Bus 4 5 5 _ or ADSmartlO 4 3 6 Ma eee CPLDIOO 18 10 CPLD I Os E sE B TC NEM S deme HE Secondary codec signals USBVCC
10. an AC 97 stereo codec with dual audio input and output channels The AGX adds an output power amplifier National LM4863LQ and a microphone pre amp with power for electret microphones The output amplifier supports differential and single ended modes When the HP IN signal is greater than V HP IN the amplifier is in single ended mode when lower it is in differential mode The following diagram illustrates the relationship of the AGX signal amplifiers to the codec from power controller Line out L Line in L Line out R Line in R CS4202 The AGX microphone circuitry can be factory configured to support line in inputs 1 Vrms with no electret pull ups and different input gain and filtering If a special configuration needed for your project consult ADS Sales with information about your requirements Absolute Maximum Ratings Var Ri e EE 5 Vdc Symbol Parameter i Max Units DVdd codec digital supply voltage Avdd codec analog supply voltage fso sample rate output kHz sample rate input note 28 kHz Audio Input Vin mic Gain mic fo mic Rin mic Cin mic Vmicpwr Rmicpwr Audio Output signal input voltage pre amp gain pre amp low pass cutoff note 29 input impedance DC blocking capacitor microphone power MIC_L R microphone power series resistance speaker load Vout Zspkr 40 differential mode MEA Vdc DC bias differentialmode 05 Avdd Pspk X oufputpowerea chann
11. indicate the direction of both signal flow and of power management V V Backlight Inverter Touch Panel SA 1111 gt ADSmartlO PCMCIA and CF gt RUN 3 3V SUSPEND 5V vam On Off RUN OFF a N Brightness PWM IDLE OFF SUSPEND lt eee PXA255 Core Display Power amp DRAM gt Data Signals ON OFF mn ENT BUN Display Controller eit meires Min IDLE gt if installed SUSPEND ON OFF Flash PXA255 I Os Ls Contrast Vee READ WRITE pu ON gt ON STANDBY OFF OFF POWER DOWN Touch Screen gt RUN Power POWER DOWN 3 3V Vddx Controller RUN Switcher SUSPEND Linear gt AC97 Codec amp Mic Pre amps Vddi CPU ON lt T ON OFF OFF ON A 2 Audio Amplifier ON POWER DOWN Ethernet o RS 232 Buffers ON L gt Serial 3 A amp B OFF ON CAN bus POWER DOWN e IrDA Transceiver ON gt OFF ON OFF System Sleep This section describes several methods for putting the system into Sleep mode Section 5 2 4 describes how to return the system to its operating state RQOnOff Input Operating systems and applications can configure the RQONOFF signal J9 15 to put the system to sleep In conjunction with the wakeup function section 5 2 4 below the RQONOFF input can
12. specifications are listed in section 6 2 11 I http www usb org developers onthego ADS document 110115 40012 preliminary Page 39 Applieddata net AGX User s Manual Feeder Coapite Spem 4 5 5 Page 40 IFC Bus Master and SMBus FC Inter IC Bus is a multi master two wire synchronous serial bus developed by Philips for communications between integrated circuits ICs The bus master addresses devices using the data line and provides a synchronous clock for reading and writing devices Client devices respond only when queried by the master device Philips has developed many IC devices but other organizations have adopted IC as a convenient means for addressing peripherals in a system FC on the AGX The AGX uses an DC bus to communicate with onboard peripherals The XScale processor is the primary bus master with an option to use the ADSmartIO controller as a secondary DC bus master in custom applications The AGX uses the IC interface to communicate with the real time clock section 4 2 and the CPU core voltage controller I C can also be used to communicate with external devices The following diagram illustrates the DC architecture on AGX Vddx XScale S Voltage Control J8 SCL LIN T SCA A RTC XScale FC The XScale typically controls all DC peripherals on the AGX Its IC signals are routed to header J8 via low impe
13. 26 PI EDT USB function port data 4 5 2 BE 39 40 29 GND P ground TL ADS document 110115 40012 preliminary Applieddata net 3 4 7 3 4 8 Fabela a open Hardware Reference J9 PS 2 Keyboard VGA Output Ethernet System Reset Board Connector 2x15 header 2 mm spacing Samtec STMM 115 02 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 115 02 F D 500 Location on board A2 B2 Pin Name Pin Type BDescipion 3 VGA_VSYNC GA_HSYNC GND RT VC V C C E Analog Display Signals 4 8 4 1 13 PS2VCC PO PS keyboardpower 5V fused ROONOFF OCI Request On Off Switch Input RESET _ M ETH LEDIA E E LEDI ETH LEDIK xternal Ethernet anode cathode 9 ER Ethernet 4 5 3 SS mc 30 AAA J10 PCMCIA Board connector AMP 535655 2 ejector hardware is a factory option Location on board A3 A5 The 68 pin PCMCIA socket conforms to the PCMCIA standard revision 2 1 for 5 V tolerant Type II cards The socket can also run at 3 3 V The socket is normally de energized the operating system is responsible for turning on the socket when a card is inserted and turning it off when the card is removed bh ESA NAN ESA EA Ea ESE E ESA NE RES p E RENI L 9g ERES e ES PA ESA Vpp pins 18 and 52 which is 12 V in older PCMCIA implementations is left unconnected in this i
14. 3 Designing for Optimal Power Management 52 SOL Create Power Budget for PeripBerals aa aset sana aana rones clio 52 3 3 V Loads 5 V Loads Loads on Main Supply e Power Loads During Sie doc 57 Oyster ODECIMICAU OMS 5 eos oce EE 55 Gils Mechanical Specifications idol E do RP Ld a 55 Gel Mechanical DES WINS AS A ee ee 55 O2 Mounin HOoleS aseene e e e tard eiectus 55 Gb A a RR UR 56 6 14 Production Opinas 56 6 2 Mating Headers on Underside of Board Removal of PCMCIA Header Connector Plating TEE ONS ee EE 57 6 2 1 Reset Sleep Wakeup Temperatura AO dp RU SEE NRI 57 0232 POWER WIDI sanad aaa aa mas te eq edm uM ad ac eee NUM EN ED UM I C eus 58 06 2 9 FOW COUPON een a AU RESI Mu TI QUU eed RE Ec 58 024 Poir e c 59 6 25 Touch Panel Controller lid 60 620 ADSimartl O ENEE 60 E E E e ee E aaa aaa TE 61 0230 Seal LORA aii 61 MAD MEME Sl ge rr c TC T AN 61 LLO EE 61 EUN CAN DU a es ua Os 62 iz AU o ai 62 62 15 PANI Process a sd 64 6 2 14 Crystal Prequencle S a io 64 ADS document 110115 40012 preliminary Applieddata net Perl Gegner Gemen AGX User s Manual 6 2 15 PCMCIA and CompactFlash Controller 65 f Board Revision Historia 67 TI Jd nt byins the Doard TIO Mi 67 12 ANG VISION HSO eei oibus eeu A EA Ba an eto A a erii etes AK uM UD DES ie SUELE 67 Ti KENS ION ESA lcd a a a a aa aan a GG 67 ADS document 110115 40012 preliminary Page vii Applieddata net AGX User s Manual E
15. 4 6 3 Analog Outputs PW M us ae b tstate t t anana iO 42 dur bhouch Pane looo dtt ES ga aa DENEA SOEN END a S Tag BAN toten a d ga KATA tod tuas etes ades metr SN eda 42 To Display Controller odo 43 AS heXscale Display Controller ada 43 4 95 2 The BpsomDisplas COontrollet dieere o edet ast in cas ica 43 403 Wsmethe LCD Display Signals ani nia dio QU DE dade 43 Panel Voltages LCD Signals Creating LCD Display Cables LVDS for LCD Displays Brightness Control Backlight Contrast Control Vee and Vcon 4 8 4 Using Analog RA EE 45 AS Developine Display DE VEL dd da 46 49 EMURE Land ESD PrOtC CHO escindida 46 AON O 46 49 2 Protecting the Power Supply TE g ietie ageet eeh gedd deeg 46 ADS document 110115 40012 preliminary Page v AGX User s Manual Page vi Applieddata net Emkbgiltzgz Cepia Syriam Power aud Power Maha semelang aaa ge ag Ga t peu uia a a a ium etd tasti a a ed adeat utra 4 SJ Power Management E 4 SLI XScale Power Management Modest 47 52 Power Management on the AGA 47 5 2 Architectural Overview and Power Management Features 48 3 2 h COWOrSUDDLy Architect e 48 3 24 2 AUS Ste Par ONDE o ues a d oro a 48 SE SEM TU m Dom TE 50 RQOnOff Input Software Control PME CBS RTT TI ME 51 RQOnOff Input Touch Panel Timed Wakeup ADSmartIO 32 54 Back Henr POWER OC IPP PODIO REO E ala docete iot oco oi csset rap Cea od 51 520 Power SuppL Ee EMCICNCY uti raa a ad rt am A A ed uia ti adt 51 5
16. CF supply voltage note 32 gt 3 3V 3 3 V socket power EN 5 V socket power E 3 3 5 0 Card detect 1 amp 2 and voltage NN sense VS1 4 2 pull ups note 33 we 3 3 5 0 2 2 Card detect and voltage sense pull up voltage Digital Outputs Ep deux 0 E MON A A Digital Inputs Vddx 3 3 V Vddx 3 3 V 5 5 Notes 32 The PCMCIA port supply voltage is selected programmatically 33 Each card inserted in a PCMCIA or CF slot can drain up to 0 4 mW when the system is in Sleep mode 4 Vddx Rpcmcia ADS document 110115 40012 preliminary Page 65 Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page 66 ADS document 110115 40012 preliminary Applieddata net 7 Board Revision History 7 1 Identifying the board revision The product revision number of the AGX is etched on the underside of the printed circuit board That number is 170115 4000x where x 1s the board revision 1 2 Revision History 7 2 1 Revision 2 Initial release The design was based on the SA 1110 Advanced Graphics Client product ADS document 110115 40012 preliminary Page 67 Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page 68 ADS document 110115 40012 preliminary
17. CMOS operation in volume production Jumpers JP6 JP7 and JP10 through JP13 select between RS 232 and RS 485 422 mode and set the duplex mode of RS 485 422 RS 422 and RS 485 are differential serial protocols with the same voltage characteristics RS 422 is a point to point protocol while RS 485 turns off the transmitter when not in use allowing multi drop installations Each can be configured in half or full duplex mode The Graphics Client Plus supports RS 422 by leaving the transmitter enabled all the time In half duplex mode TX RX and TX RX are shorted together Half duplex devices can see their own transmissions Connect to either the or connection on J7 but make sure to observe correct polarity You may find the following RS 485 422 signal locations helpful for diagnostic purposes JP6 2 TX JP6 1 RX JP7 2 TX JP7 1 RX JP11 1 RX enable JP12 1 TX enable Headers shaded gray in the following table are not relevant to the mode listed but are shown for reference JP6 JP7 1 1 1 1 3 E 3 E JP10 JP11 JP12 JP13 JP6 JP7 RS 485 422 Half Dupl ra Hae JP10 JP11 JP12 JP13 JP6 JP7 RS 485 422 JP10 JP11 JP12 JP13 ADS document 110115 40012 preliminary Page 13 Applied net AGX User s Manual Embedded Creador yatim 3 3 3 3 8 3 3 9 3 3 10 Page 14 JP9 Vee Polarity Select Type 3 post header 2mm Location on board C6 This jumper selects the polarity of Vee the
18. MMcCS0 12 O Chipselec poor 13 MMCCD 1 Card Detect ES 15 MCCCMD O Command Dino 14 PI Beate clock backup battery ae ie Headphone connected Lu one avec USB On The Go 4 5 2 Ss EE NEN BEEN NEN Pi EA EE E Serial A 4 5 1 EA EA VO E EE Z EE PA A Serial B 4 5 1 E NI MS Kg Page 26 ADS document 110115 40012 preliminary p 39 Eu E AY o 31 DTRA 35 DSRA 37 RA TXDB 26 E p 20 22 25 TXDA RTB 30 DTRB 32 DCDB 34 RB 38 GNDCOMB Applieddata net Fabela a open Hardware Reference Pin Name Pin Type Description pg Serial C 4 5 1 additional signals above EE RXDD 42 TXDD a On 46 Ve AM RTSD 48 additional signals above GNDCOMD 50 ADS document 110115 40012 preliminary Page 27 Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page 28 ADS document 110115 40012 preliminary Applieddata net Entera Cepia Friemt 4 Feature Reference 4 1 4 1 1 This chapter provides details about the architecture and many features of the AGX and how they can fit together to create a system that meets your application needs System Architecture Boot Code The AGA uses the first block of onboard flash to store the boot
19. See section 6 2 13 for GPIO electrical specifications and 6 2 8 for serial port specifications Quad UART AGX includes a UART with four full featured ports The ports are factory configured for either EIA TIA 232 or 3 3 V CMOS operation Ports that are configured for 3 3 V CMOS operation connect directly to the UART and should be treated carefully See section 6 2 8 for serial port electrical specifications USB The AGX includes signals for USB 1 1 Host Function and On The Go ports The USB Host downstream signals are on socket Jl and header J15 the USB Function signals are on header J8 and the USB On The Go signals are on header J40 The PXA255 controls the USB Function port while the Philips ISP1362 controls the USB Host and On The Go ports The AGX can be configured as a self powered hub with one Host and one Client port To create a USB connection you must wire a standard USB socket as described in the following sections For each type of connector pin numbering is as follows Pin USB signal USB PWR GND USB Host Port The AGX USB Host port allows you to connect one USB device to the AGX USB mouse and keyboard are the most common client devices but you can connect any USB function device that has USB drivers installed on the AGX The AGX includes Type A USB connector J1 for the host signals You can also wire your own USB connector using the signals on J15 section 3 4 13 The mating face of such a socket is
20. code At the factory boot code is loaded using the JTAG interface J6 section 3 4 10 Most ADS AGX boot loaders are field upgradeable using a flash card on either the CompactFlash or PCMCIA port oynchronous DRAM One bank of synchronous DRAM SDRAM can be populated for a system total of 16 32 64 or 128 MiB of RAM The data bus width is 32 bit The memory clock speed is one half the CPU core clock speed Typical memory bus operation is at 99 5 MHz The self refreshed RAM consumes most of the system sleep current Sleep current increases roughly in direct proportion to the amount of RAM installed Non Volatile Memory There are several ways to store data on the AGX that will survive a power failure Some devices can only be accessed through operating system drivers and not all are available for application data storage Flash Memory Flash memory is the primary site for non volatile data storage The AGX includes a bank of flash memory for non volatile data storage The board supports 8 16 or 32 MiB of installed flash The data bus width is 32 bit ADS systems store the operating system applications and system configuration settings in the onboard flash Most operating systems configure a portion of the flash as a flash disk which acts like a hard disk drive ADSmartlO EEPROM The ADSmartIO controller includes 256 bytes or more of EEPROM storage ADS reserves a portion of this memory for future use Drivers may not be availab
21. contrast control voltage for passive LCD displays Vee 1s controlled with a PWM signal from the ADSmartIO See section 4 8 3 for further details Jumper setting Vee JP14 Source of Sleep Mode Power Type 3 post header 2mm Location on board C6 This jumper selects the source of power to back up the AGX when it is in sleep mode See chapter 5 for further details Jumper setting Voltage Selected JP36 LCD UD Signal Type 2 post header 2mm Location on board A6 This jumper determines the voltage for the PNL UD signal on J11 and J19 On some active matrix LCD displays the PNL_UD signal flips the displayed image bottom to top Jumper setting Connects UD to n c PNL PWR JP37 LCD RL Signal Type 2 post header 2mm Location on board A6 This jumper determines the voltage for the PNL_RL signal on J11 and J19 On some active matrix LCD displays the PNL_RL signal flips the displayed image right to left Jumper setting Connects RL to n c PNL PWR ADS document 110115 40012 preliminary Applieddata net 3 4 3 4 1 3 4 2 Enketa Ernzer Padmi Hardware Reference Signal Headers The following tables describe the electrical signals available on the connectors of the AGA Each section provides relevant details about the connector including part numbers mating connectors signal descriptions and references to related chapters For information about the location of the connectors on the AGX re
22. header unshrouded 2mm Location on board B2 This header selects the communications mode of Serial Port 2 of the PXA255 The operating system must configure the processor for the target serial mode The table below lists the standard voltages to expect on the transmit line of the port when the transmitter is idle Important When using Serial 2 as IrDA make sure that the operating system configures the port as IrDA Otherwise the transmitter may be turned on continuously which will drain significant amounts of power and may damage the IrDA transmitter Serial 2 Mode JP7 Shunt Settings 1 2 3 4 7 8 9 10 AN 11 12 15 16 17 18 ibd 1 3 6 10 JP5 RS 485 Terminator Type 2 post header 2mm Location on board Bl Typical idle voltages are listed Actual voltages may vary The IrDA transceiver is enabled with the IrDAOn signal from the system controller CPLD ADS document 110115 40012 preliminary Applieddata net 3 3 6 Febedied Computer Fut Hardware Reference Install this jumper to make the AGX the last device in an RS 485 network Shorting the pins of this header places a 120 Q termination resistor across the RS 485 RX lines Jumper setting RS 485 Terminator JP6 7 JP10 13 Serial Port 1 Mode Select Type 3 post headers 2mm Location on board B1 C2 Serial port 1 can be field configured for operation in RS 232 RS 422 and RS 485 modes It can also be factory configured for J1708 or 3 32 V
23. shown at left The USB standard also permits directly wiring the USB signals to the target USB device e g USB mouse To connect more than one USB client device to the AGX use a USB hub The USB protocol allows client devices to negotiate the power they need from 100 mA to 500 mA in 100 mA increments The AGX supplies 5 V power through the USB PWR pin Make sure to account for power used through USB in your AGX power budget section 5 3 1 It is recommended that you use a power switch Electrical specifications are in section 6 2 9 USB Function Port The AGX includes a USB Function or Client port This interface allows the AGX to appear as a client device to USB Host devices such as desktop and laptop computers The USB Function signals are available on connector J8 section 3 4 6 Connect these signals to a USB client Type B socket mating face shown at left The USB standard also permits directly wiring the USB signals to the host or to a host connector e g USB mouse The AGX supports the full USB connection speed 12 Mbit s It indicates this to the host device with a 1 5 kQ pull up on the USB signal ADS document 110115 40012 preliminary Applieddata net Entitet Greywin Spini Feature Reference USB VCC is power supplied from the host computer Since the AGX is self powered not powered by the USB host USB VCC is not needed as a power input However USB VCC tells the AGX when a USB cable is connected so incl
24. to ground The series resistance limits the dc current that any one pin can source or sink 22 TC outputs PC6 and PC7 are directly connected to UO controller without external protection 23 Control pull up resistors by writing to bits of IO port when the port is configured as a digital input bit mask 1 enable O disable ADS document 110115 40012 preliminary Applieddata net Ebeda Gout nien oystem Specifications 6 2 7 6 2 8 6 2 9 6 2 10 24 Digital noise on the board may degrade analog performance under some conditions 25 ADSmartlO A D inputs include an input voltage divider of 33 2k series with 10k to ground 26 Vref is usually turned off when the system is in Sleep mode section 5 2 2 27 Specifications based on ADSmartlO release 1010 rev 2 ADS release 7001 14 10102 oystem Controller A Xilinx XCR3256XL CPLD on the AGX provides system logic for chip selects power management interrupt decoding clock generation PCMCIA logic and other system control functions It is programmed at the factory using the JTAG interface 3 4 14 Absolute Maximum Ratings Input voltage digital I O pins 0 5 to 5 5 V tbd Output current continuous digital VO DNS ai 100 to 100 mA tbd Symbol Parameter Min Max Units a ame IIT NE Digital Outputs DigtalOuputs gt tod pOr AL T 94 AE AAA CC 24 Y Digital Inputs Digital Inputs gt tod Eos 3 E E NA C Ne qe O AL NA S
25. 012 preliminary Page 1 Applieddata net AGX User s Manual Feeder Coapite Spem 1 2 4 Communications e USB 1 1 Host port low 1 5 Mbit s and full 12 Mbit s speeds e Full speed Client port e USB On the Go e Seven Serial Ports Serial 1 EIA TIA 232 3 3V CMOS 5 wire EIA TIA 422 485 or J1708 Serial 2 EIA TIA 232 3 3 V CMOS 5 wire or IrDA Serial 3 EIA TIA 232 or 3 3 V CMOS 9 wire Serial A and B EIA TIA 232 or 3 3V CMOS 9 wire Serial C and D 3 3V CMOS 9 wire e 10 100BT Ethernet RJ45 e CAN bus e CompactFlash Interface card guides not included and PCMCIA 1 2 5 User Interface and Display e Flat Panel Interface e Option for External Frame Buffer for extended performance e Backlight Control Signals for Intensity and On off e Software Controlled VEE Generator for passive LCD contrast control e Analog Touch Panel Interface four or five wire options e External PS 2 Keyboard Support 1 2 6 Discrete I O e Sixteen ADSmartlO ports configurable for digital I O and or up to 8x8 matrix keypad e Ten additional general purpose digital I Os e Four A D inputs 1 2 7 Audio Interface e AC 97 Codec e Stereo Microphone Input e Stereo IW Speaker Outputs e Headphone Output Page 2 ADS document 110115 40012 preliminary Introduction 1 3 Block Diagram The following diagram illustrates the system organization of the AGX RS 232 422 RS 232 IrDA UART Ports Digital I Os TouchPad Analog Inp
26. DF9B 31P 1V Recommended Mating Cable tbd Location on board B6 underside of board Hardware Reference This header can be used to directly connect to some Sharp active TFT displays and products that are compatible with them The signals on this connector are a subset of the signals on J11 See section 3 4 9 for more detailed descriptions of the signals Name N PNL PIXCLK PNL HSYN PNL VSYNC 4 GND PNL REDO 2 Q O A N NL_RED NL_RED NL_RED PNL RED5 GND PNL GREENO PNL GREENI PNL GREEN2 PNL GREEN PNL GREENA PNL GREEN5 N PNL BLUEO NL BLUE NL BLUE NL BLUE NL BLUE PNL BLUE GND PNL LBIAS N PNL_PWR PNL_RL PNL_UD Zeg Bed ol Ze S O NI Go BOTS M M M 12 LA we Q No al heed heed le O FA Go hop M Q NO gt Qo bo bh ho ho bh Pin EA EE ee ES EA p 9 zim a DNE s E AA ET iii x ES AA EA ETRE ADS document 110115 40012 preliminary Type Page 25 Applied net AGX User s Manual Devbecdded Exeter Spite 3 4 18 J40 Expanded I O Board Connector 2x25 header 2 mm spacing Samtec STMM 125 02 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 125 02 F D 500 Location on board B6 D6 Pin Name Pin Type Descipion Serial C 4 5 1 additional signals below Serial D 4 5 1 additional signals below GEM Multimedia Card MMC
27. ESET IN 3 6 V note 1 Symbol Parameter Min Typ Max Units Temperature Trun operating temperature 40 85 C Vrst tiggervotage NoOe2 27 V Vpst pull up voltage 1 Vdx V Rpst pull up resistance TI 47 k Sleep 5 2 3 Sleep trigger voltage Note 3 54 58 V Sleep trigger release hysteresis Vsleep hyst Note 4 0 25 V Wakeup RqOnOff 5 2 5 wakeup pulse duration Note 5 oull up voltage c pull up resistance LE El maximum input voltage LE trigger voltage BEE 1 The reset controller can support operating voltages up to 10 VDC However such high voltages on Vddx through the pull up resistor may damage the system 2 Short Reset_In to GND to reset system 3 This is the voltage at VBATT POS at which the DC GOOD signal 4 3 6 changes from high to low which can trigger the system to go into Sleep mode Sleep trigger at DCIN POS is Vsleep Vdin 6 2 2 4 Important Once Vsleep has been triggered the input voltage must rise at least Vsleep hyst above Vsleep before the voltage detector will restore the DC GOOD signal Make sure that your input voltage is designed to always run above Vsleep Vsleep hyst or systems that go to sleep may not be able to wake again 5 Short RqOnOff to GND to for at least irg to wake up system A low level voltage on RqOnOff initiates wakeup ADS document 110115 40012 preliminary Pag
28. LCD Signals LVDS Board Connector 2x10 header 2 mm spacing Molex 87331 2020 Recommended mating connector tbd Location on board A7 B7 J12 supplies the LCD signals in LVDS format The LCD signals on each differential pair are listed in the table below data is clocked out MSB first but is listed LSB first below Additional details about LVDS are listed in section 4 8 3 PNL_PWR Display power 5 RXINO O LVDS data 0 6 RXINO O R4 RO R1 R2 R3 R4 GO 8 RXINI O LVDS data 1 9 RXINI O G1 G2 G3 G4 G5 B4 B0 RXIN2 O LVDS data 2 RXIN2 O B1 B2 B3 B4 HSync VSync DE GND CKIN O Ce E ima 3 4 11 J13 Serial 3 Board Connector 2x5 header 2mm spacing Samtec STMM 105 01 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 105 02 F D 500 tbd Location on board B7 C7 Data Terminal Ready Ring Indicator Serial 3 ground ADS document 110115 40012 preliminary Page 21 Applied net AGX User s Manual Devbecdded Exeter Spite 3 4 12 Page 22 J14 ADSmartlO Serial 1 and 2 EIA 422 485 I O Board Connector 2x20 header 2 mm spacing Samtec STMM 120 02 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 120 02 F D 500 Location on board B1 D1 Pin Name Pin Type Description ADSmartlO 9 ROWA Keypad rows
29. O A UD aa dE l L2 EE 2 p25 User Intertace and RE EE 2 A IN aa aa ab aaa Tu 2 pom udi a adt esa aac CODICE Ii CON Sou SHOE ENIRO E CIN cup Sed 2 1 33 BOCA IDI ST AN osea a e ats dba en cf onte qux PE sad 3 2 Geine A AG 5 24 Development ege ee ee ees 5 Shake A EEE 5 Za Frequently Asked EE 5 2 Organizavion Or hs MaMa eege 6 2 4 Errata Addenda and Further Informapnon eere en retentis 7 3 Hardware Rele ren CC tans an a buta umb o e o ss ag ee ee 9 Sch Jdent byine COHHIeCLOES eeh 9 Sell OGAK onmnec OL Sa ipa a Sg do a pa Ced foto cive pa a Ka ui a ap A A nat a a uix cd ag d RE dU kan 9 34572 Determine Pin Numb eK au eee reor ata tera be out LA me no a gah cue a aa ak abi aa ah 9 3 2 Switches Controls and Indcatorg cece cee ceeceeccecceccsccccccccsccsccsccescsceccescesccsscescscesceees 10 zal DF BS rico NT cT cT 10 E LS boot i oerte DEE gena aa nag eer ooi toes iis 10 292 LEE eer 10 Software Controllable LEDs Ethernet LEDs USB LED Sele MIDA rans CC1v Errata rad rd 11 232 3 VEL Veo Contrast Ad D SUMET anana sasana eno eod fuiste cacaos D aana aii aneka en anan 11 ADS document 110115 40012 preliminary Page iii AGX User s Manual Page 1v Applieddata net Febedieg Conter Syriam Deo MAPEO CUMS E 11 Sod JPL ECD Display POW serbios 11 332 JP2 SOUfce of 3 3 V Power Vda 11 35 0 JP LED Display Data Volare entradas 12 9 294 JP Serial 2 Mode ele Choco licita 12 O IES IR
30. S 6 EMO 12 336 JP6 7 IPTO 15 Serial Port 1 Modesto 13 Sow JE Ves Polatity Seleet eio o NR S desse I ER ba Nt 14 3 545 AMPLIA Source ot sleep Node PONE ru Upton EOM EE RU INTE 14 So PI IED UDS oo Bana SU E iip 14 SID JPST EE Ee 14 BA Signal Header di iio 15 Sud JE USB H st POE td bad 15 Az P InpatBoWer C ONC ClO EE 15 BAS las BacklteHt Inverter ioo petite Race ben Du Eo up ga adas cos 16 344 JA Compactrlash Expansion BUS er a eon Pa ot a eun Came Feet i etna 16 SO Js EDENO ds oot tme hd det ao 17 346 J8 VO Analog Inputs USB Function Port oommonnnnnnnnnnnincccnnnonocccnnnnnccanccannnons 18 3 4 7 J9 PS 2 Keyboard VGA Output Ethernet System Reser 19 E MO PCMCIA A a 19 349 J11 LCD Display 34 pin esca ii ii 20 SANO ILL LED Sienmals ENDS ada deine uni qu a et in a eiut emis 21 SI JS SCTE Ds nain gana a aa ana an a 21 3 4 12 J14 ADSmartIO Serial 1 and 2 EIA 422 485 UO 22 3 4 13 J15 Audio Touch Panel Backlight CAN Serial 3 IrDA USB Host 23 3 4 14 J16 Manufacturing Test Connector 24 SAS JM CAN DU A 24 SAMO TES ouch Pan tia 24 S412 M9 ECD Display Hirose EE 25 SAWS MO Expanded O WE 26 Feature EE HEED EE 29 A Sy SCCM ono ro DUEC ur orato Lies doo ott oco eM opa cu C E OHIO abah 20 Aba BOC uc T 29 4 1 2 synchronous DRAM aaa panga aaa add 29 4 1 3 Nom Volatille ME DEN sasinan aaa aan gg Yaad aaa aana a a Ba aa a ana a adakan d aa pn Ba kaa a
31. able of Contents Section titles include connector designators and their function 2 Follow cross references between sections 3 View and search this manual in PDF format ADS document 110115 40012 preliminary Entera Cee Syrum Applieddata net Getting Started 2 4 Errata Addenda and Further Information Errata and addenda to this manual are posted on the ADS support forums along with the latest release of the manual Consult the support forums any time you need further information or feel information in this manual is in error You may access the forums from the ADS support site http www AppliedData net Support In addition to manuals the support forums include downloads troubleshooting guides operating system updates and answers to hundreds of questions about developing applications for ADS products You may also post questions you have about ADS products on the forums ADS document 110115 40012 preliminary Page 7 Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page 8 ADS document 110115 40012 preliminary Embed Zap Spam 3 Hardware Reference 3 1 3 1 1 ADS document 110115 40012 preliminary This section gives an overview of the hardware features of the AGX This overview includes a description of the switches jumper settings connectors and connector pinouts Identifying Connectors The section describes how to locate connectors o
32. adara 29 Flash Memory ADSmartlO EEPROM CompactFlash and PCMCIA ATA Cards RTC NVRAM ZU EIERE 30 4 1 5 CompactFlash Expansion Bus ccccccccnnncnnnnnnoonnnnnnnnnnnnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnos 30 Ao PXA2535 GPIO Cross Reference italia 30 A2 Reallime Clock RIC EE 32 MES Ub virile cr 92 SOM UE D TES 32 AD PTO lS MVC ROTE E TM 33 kaa O A REN 33 ADS document 110115 40012 preliminary Applieddata net Perl Gegner Gemen AGX User s Manual ASA Analog Inputs qo Disses ie dpa iet tht piu DES iii 33 A AC SCAM AAA i Aa aa a a KA attt E Aa a a b a ta de DU etui estos UE 33 43060 ADSmartl0O Signal Cross Reference mii ci n 34 A i MED e te cp RE 35 44 Microphone EEN 35 4 4 2 Audio Outputs Speakers and Headphones oooonnnccccncccnccccononononnnnnnnnnnnnnnnnononnnnnnnnnnos 35 Connecting Speakers Connecting Headphones Using Stereo Headphones and Speakers in the Same System 4 5 DAA E 37 4 5 1 SETIA pO E catu n ELM Ld cuu x Ee M PTS TONE a a LEM 37 XScale UART Quad UART A Ui MDC Km T aa NEPANG 38 USB Host Port USB Function Port USB On The Go LED Activity Indicator A A ERR 39 kid E E Mm 39 ASS IC Bus Master and SMBUSS oii deii retta etie aout act 40 FC on the AGX XScale C ADSmartlO PC SMBus 4 5 6 Multimedia Card MMC Controller ds 41 tO Re etate duorum a a KK EE an I dup ai 42 Ad KE RE dacs daana aaa nana anara Nb nagan Ba UE addu ad 42 407 Annalo TOPS cuite pn aan aa pa AE 42
33. ailable for external A D use see section 4 3 6 for port assignments The A D inputs on the AGX go through voltage dividers before reaching the pins See the electrical specifications listed in section 6 2 6 for details Keypad Scan The ADSmartIO can scan a matrix keypad up to four by five keys in size Matrix keypads are simpler and cost less than full keyboards and can be easily customized for your application You can also create a keypad matrix from a collection of normally open switches When configured to scan a keypad the ADSmartIO configures the ROWn lines as inputs with software pull ups enabled and configures the COL n lines as outputs set to 1 high For the scan the keypad scanner sets successive COL n outputs to O0 Iow then looks for a 0 on one of the ROWn inputs The scanner re reads the pressed key after a delay to debounce the key press Unused row and column lines can be used for general purpose I O or A D ADS document 110115 40012 preliminary Page 33 Applied net AGX User s Manual Frec Cragin ism The following diagram illustrates how to connect a 3x3 keypad matrix The pull ups are the software activated internal resistors of the ADSmartIO while the series resistors are part of the AGX AGX ADSmartlO Controller 3 x 3 Keypad ROW 0 AAN SW1 SW SW3 Sr br tr lt ROW 1 O MENSES i TE Lor LF LSP lt lt oo P PoP RP EP
34. anical drawing specifies the dimensions of the AGX as well as locations of key components on the board The PCMCIA ejector can be detached from the board header and is a factory option All dimensions are in inches This image is an excerpt from the full mechanical drawings ADS document number 630115 40001 a ro e c r d 2 QI ee oe i Te 2 138 AE ae Se ga 4 PLES Jl z J xm Eu 3 A 3 ikan DIE Pu Pa L LO rn Le Un 4 22 L 5 215 A EA rra SSA eee E a ee aiaa Mounting Holes Four holes are provided one on each corner for mounting The diameter of the holes is 0 138 in Mounting holes are plated through and connected to the AGX ground plane For reliable ground connections use locking washers star or split when securing a AGX in an enclosure Make sure that washers do not extend beyond the limits of the pads provided ADS document 110115 40012 preliminary Page 55 Applieddata net AGX User s Manual Crbrdieg Cogita Spine 6 1 3 Page 56 Clearances The AGX has a low profile It can fit in an enclosure with inside dimensions as thin as 0 853 inch 21 7 mm Key clearances are as follows e Highest component 0 561 inch 14 2 mm top 0 130 inch 3 3 mm bottom e Board thickness 0 062 inch 1 57 mm e Clearance over top and bottom 0 05 inch 1 3 mm each Note Selection of connectors and wiring harnesses will determine height of final assembly P
35. anual Feeder Coapite Spem 5 3 9 3 1 Designing for Optimal Power Management Designing a system for optimal power management requires careful attention to many details This section provides some guidelines and tips for best power management Create a Power Budget for Peripherals Embedded system designers using the AGX should have a clear understanding of how power usage will be allocated in the system they design Designers should create a power budget that takes into account the types of devices that are expected to be used with the AGX The following lists detail some of the typical external loads that can be placed the AGX power supplies Baseline power consumption of the AGX is listed in section 6 2 3 3 3 V Loads Typical external loads on the 3 3 V power supply include the following e Display e Personality Board e CF and some PCMCIA cards 5 V Loads 5 V loads come from both onboard and external devices Typical loads include the following External e Display e Many PCMCIA cards e USB devices e PS 2 keyboard e Speaker s Assume 80 efficiency Onboard e 3 3 V Supply Multiply by 115 to account for 3 3 V power supply efficiency Loads on Main Supply The main 5 V power supply is loaded by the and 3 3 V supplies as indicated in the diagram of section 5 2 1 Assume 85 efficiency for external loads that cascade through the 5 V supply Consider these loads when creating your power budget 5 3 2 Power Loads D
36. are listed in section 6 2 5 ADS document 110115 40012 preliminary Applieddata net 4 8 4 8 1 4 8 2 4 8 3 Entitet Greywin Spini Feature Reference Display Controller The AGX can be factory configured to use either the integrated XScale display controller or the Epson S1D13806 controller This section describes both controllers and the AGX features they use in common The XScale Display Controller The XScale controller uses system memory for the display frame buffer It can drive VGA 640x480 and SVGA 800x600 displays easily Larger displays will work with the XScale with some constraints imposed by the controller architecture The ADS Support Forums provide details about the design tradeoffs that are required to support larger displays Key features of the XScale controller include e Frame buffer stored in system DRAM e DMA from RAM to LCD controller e Dual 16 x 8 byte display data FIFOs The Epson Display Controller The Epson controller has its own frame buffer which reduces the load on the system bus for displays with larger dimensions and higher refresh rates The controller also includes analog CRT outputs suitable for connecting to NTSC and PAL television monitors Features of the controller include e 1280 kiB frame buffer e Digital LCD output e Analog CRT or TV NTSC PAL Composite S Video output e Hardware display rotation swivel e Dual and Virtual display support e Hardware cursor m
37. be used as an on off button for some systems Electrical specifications are listed in section 6 2 1 RqOnOff PowerOn gt LCD Display ADS document 110115 40012 preliminary Applieddata net 9 2 4 5 2 5 5 2 6 Ebet Cette Fraen Power and Power Management Software Control Applications can put the system to sleep programmatically Operating systems may also put the system to sleep if the system has not been used for a certain amount of time or for other reasons In remote battery powered applications software Sleep can be used in conjunction with the Timed Wakeup feature section 5 2 4 for minimum power consumption System Wakeup This section describes several mechanisms for waking an AGX system that has been placed in Sleep mode section 5 2 3 The system will resume operation in Run mode unless the power supply voltage is lower than Vsleep section 6 2 1 If the input voltage is too low the system will not wake under any circumstances This protects the RAM from getting corrupted by an undervoltage condition RQOnOff Input Shorting the RQONOFF signal section 5 2 3 above to ground will wake the system The signal is connected to the system controller Electrical specifications are listed in section 6 2 7 Touch Panel The touch panel controller interrupts the processor when touch panel events occur Before going to sleep the processor can place the
38. connector pinouts to cross reference ADSmartIO signal names ADS document 110115 40012 preliminary Applieddata net 4 3 2 4 3 3 4 3 4 4 3 0 Entitet Greywin Spini Feature Reference Electrical specifications for the ADSmartIO are listed in section 6 2 4 The ADSmartIO Programmer s Reference ADS document 110110 4004 gives information about how to use the ADSmartIO features ADSmartlO Features The following are some of the functions that the ADSmartIO can perform The functions actually implemented depend on the firmware loaded on your system e General purpose digital I O and A D e Keypad scan section 4 3 5 e PS 2 keyboard input e Backlight on off and brightness control section 4 8 3 e Contrast control for display enabled only when pixel clock is running section 4 8 3 e Read setreal time clock RTC section 4 2 e Wakeup via RQONOFF signal section 5 2 3 e Monitor system power e Reset CPU Digital I Os All available ports on the ADSmartIO controller can be individually configured as inputs or outputs If you write a 1 to an I O port when it is configured as an input it enables a pull up resistor Electrical specifications are listed in section 6 2 4 Analog Inputs A D Each of the Port A I Os PAO PA7 includes an analog to digital A D converter The converters give full scale readings when the voltage at the pin is equal to voltage reference Vref e g V Vrefereading 1023 Not all ports are av
39. controller in a low power sleep mode When a touch event occurs the controller still generates an interrupt which can wake the system Timed Wakeup The XScale can wake up at a predetermined time This feature is controlled by software ADSmartlO The ADSmartIO controller controls the wakeup signal to the XScale For production applications ADS can configure the ADSmartIO to wake up the system on specific events Contact ADS Sales 1f your application requires a special wakeup event Backlight Power The AGX provides software control of Backlight Intensity and On Off Power for the backlight 1s routed through the board from header J2 This provides the greater flexibility when selecting backlight inverters for an application See section 4 8 3 for further details about backlight control Power Supply Efficiency The AGX power supply achieves high efficiency through several means First it utilizes high efficiency switching regulators These regulators use conventional step down switchers under operating load conditions but are configured by the system for linear and burst mode operation during low load conditions that occur during system sleep Additionally there is only one level of cascaded regulation reducing the losses that multiply through each stage I Burst mode in this context is a registered trademark of Linear Technology Corporation ADS document 110115 40012 preliminary Page 51 Applieddata net AGX User s M
40. d pad on each connector is pin 1 Switches Controls and Indicators This section describes various switches controls and indicators on the AGX board The location indicated for each item refers to the grid diagram of the AGX in section 3 1 1 S1 DIP Switch Location on board D6 Sl is a four position DIP switch When in the ON position switches are closed and connect to ground Otherwise they are pulled up The DIP switches connect to the system controller Most operating systems on the AGX reserve these switches for their use Consult the operating system manual for details SW1 Reset Switch Location on board A6 SWI is the reset button for the AGA This switch issues a hardware reset to the PXA255 and system peripherals Press this button to restart the AGX without cycling power Most operating systems clear the contents of DRAM when a hardware reset occurs Pressing SWI shorts the RESET_IN signal J9 pin 16 to ground If your peripherals need to be reset when this button is pressed use the RESET OUT signal on J9 pin 29 You can hold the AGX in reset by pressing and holding this button LED Indicators The AGX has several onboard light emitting diodes LEDs to indicate system operation Some are software controllable while others indicate the status of specific functions Software Controllable LEDs Location on board D6 Three LEDs are controlled by the CPU section 4 1 6 and are used to indicate boot and operat
41. dance resistors The XScale I C bus can be disconnected from the external bus and the real time clock for custom applications Specifications are listed in section 6 2 13 ADSmartlO FC The ADSmartIO emulates an UC bus master using PC6 as SCL and PC7 as SDA These signals are available on J8 for expansion to off board devices Specifications are listed in section 6 2 6 The ADSmartIO is connected to the I C bus for backward compatibility with previous ADS designs but is not recommended for new designs To indicate this status ADSmartIO I C is erayed out in the diagram above Use the XScale DC controller for new applications ADS document 110115 40012 preliminary Applieddata net Entitet Greywin Spini Feature Reference 4 5 6 SMBus SMBus System Management Bus is a protocol developed by Intel that is similar to C Some laptop and desktop computers use SMBus to manage system power using the ACPI standards A subset of SMBus the Smart Battery protocol uses SMBus to communicate with intelligent batteries and chargers Key differences between C and SMBus include e Bus speed The SMBus clock rate must be between 10 kHz and 100 kHz while DC can run between DC and 400 kHz e Timeout SMBus slave devices time out and reset their communication interfaces if there is more than a 35 ms delay in the clock I C doesn t have a timeout e Current draw on bus SMBus devices must draw between 100 and 350 uA DC devices ca
42. discharge ESD and suppress electromagnetic and radio frequency interference EMI RFI Transient voltage suppressors EMI fences filters on I O lines and termination of high frequency signals are included standard on all systems For details see electrical specifications for subsystems of interest Agency Certifications Many products using ADS single board computers have successfully completed FCC and CE emissions testing as a part of their design cycle Because ADS supplies only the single board computer and not fully integrated systems ADS cannot provide meaningful system level emissions test results The crystal frequencies section 6 2 14 and electrical specifications listed in Chapter 6 may provide helpful information for agency certifications Protecting the Power Supply Inputs It is the responsibility of the designer or integrator to provide surge protection on the input power lines This is especially important if the power supply wires will be subject to EMI RFI or ESD ADS document 110115 40012 preliminary Applieddata net Entera Cepia Friemt 5 Power and Power Management 5 1 9 1 1 Power management is especially critical in portable and handheld applications where battery power is at a premium The AGX includes advanced power management features including the low power XScale CPU and partitioned power distribution The AGX can also operate as a conventional single board computer taking advantage of the in
43. driven by the Epson controller The LVDS signals are driven by the National Semiconductor DS90C363A LVDS transmitter Symbol Parameter LCD 4 8 3 LCD voltage note 12 P pnl pwr LCD power note 13 V pnl data LCD data voltage note 14 Scan Direction active displays 3 3 9 3 3 10 4 8 4 Rpnlscan Pull up resistance 47 Iw Vpnl scan Pull upvoltage 0 Vpnl Vpnl j V Contrast Control passive displays 3 2 5 3 3 7 4 8 3 note 15 Vee Contrast adjust R 5kO JP9 1 2 30 15 Vee Vcon Low voltage contrast adjust note 15 0 0 75 Brightness Control backlight 4 8 3 RbacklightOn Pul up pp aos V backlightOn With pull up note 16 Oooo p 12 No pull up factory option note 17 V backlightPWM PWM note 18 R backlightPWM PWM series resistance note 19 LVDS 4 8 3 R term V lvds Digital I Os J8 3 4 6 4 6 1 note 20 Voh High level output voltage 30 Vol Low level output voltage O03 lgcio X SinkSowcecuret 6 6 mA Notes 12 Jumper JP1 3 3 1 selects the display voltage 13 Total power available depends on system power budget 14 Systems are configured at the factory with buffers for 3 3 or 5 V panel data Jumper JP3 3 3 3 selects the voltage for those buffers 5 V displays with Vih lt 0 6 Vpnl pwr 3 0 V will work reliably with 3 3 V data 3 3 V buf
44. e MICI IN MIC2 IN AGND NO N 2 D Pin Pin DL a Lm a p MN ES p AA Le s p NEN 8 a L p EA HEN MEAN p p MAA Pani MIN p p DT AY pl p MEINE m LL E pu p p p AE m ERN p NEN A E p NE Pahan ADS document 110115 40012 preliminary Page 23 Applied net AGX User s Manual Devbecdded Exeter Spite 3 4 14 J16 Manufacturing Test Connector Board Connector 2x5 header unshrouded 2mm spacing Samtec TMM 105 01 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 105 02 F D 500 tbd Location on board C7 This header is used during manufacturing to program the boot flash onboard logic and ADSmartIO firmware It includes both JTAG and SPI signals and is intended for factory use AVR SPI for in system programming 3 4 15 J17 CAN Bus Board Connector 1x2 header 0 1 inch spacing Molex 22 23 2021 Recommended Mating Connector tbd Location on board D7 Pin Name Type Description CANHIGH 3 4 16 J18 Touch Panel Board Connector 1x4 or 1x5 header 0 100 inch spacing Molex 22 23 2051 5 pin Recommended Mating Connector tbd Location on board D7 Pin Name Type Description Touch screen n a Page 24 ADS document 110115 40012 preliminary Applieddata net Entera Cee Syrum 3 4 17 J19 LCD Display Hirose Board Connector Hirose
45. e 57 Applieddata net AGX User s Manual Feeder Coapite Spem 6 2 2 6 2 3 Page 58 Power Supply The AGX is powered from a 5 V DC supply It generates additional voltages for onboard logic The 5 V and 3 3 V supplies are available on the AGX output connectors and are limited to the current draws specified below The system time is maintained by a DS1307 real time clock and powered by a long life battery Symbol Parameter i Max Units System Power VDDX 3 3 V onboard supply 3 3 V available for display PCMCIA external peripherals etc Note 6 5 V available for display and external peripherals note 7 RTC Backup Power 4 2 V BATPOS real time clock battery backup BATPOS RTC current note 8 Vddx 6 During Sleep mode Vddx is powered by a linear regulator which draws from the 5V supply 7 n addition to the external 5V IN power supply the 5 V output is limited by the trace widths on the printed wiring board 8 Vddx 0V Vbatpos 3 2 V source DS1307 data sheet Power Consumption The following table lists typical power consumption for the AGX with varying activity levels Power consumption varies based on peripheral connections components populated on the system and the LCD panel connected Input voltage temperature and the level of processor activity affect power consumption to a lesser extent LCD displays and backlights add significantly to the total power consumption of a system
46. ecifications are listed in section 6 2 15 ADS document number 640111 8000 available on the ADS Support Forums is the schematic for the Bitsy Personality Board design which illustrates how to use the CF bus either as a CompactFlash socket or for an Ethernet controller Additional documents are available on the ADS support web site section 2 4 that illustrate how to use the CF bus PXA255 GPIO Cross Reference The following table describes how the AGX utilizes the XScale GPIO lines GPn They are offered for reference purposes only Most operating systems make this information transparent to developers Signal Name Function connector section Wakeup from ADSmartIO EM eine and debounced RqOnOff 6 2 1 IRQ CPLD CPLD interrupt CTS2 O0 Serial 2 CTS 4 5 1 USB DET USB function port detect connection IRO TS Touch panel interrupt 35 USB RECONN O USB function port disconnect reconnect 6 MMCCLK O MMcCclock J7Z 45 6 8 MMCCSO O MMCchipselectO J7 45 6 9 MMCCSI O MMCchipselect 1 7 45 6 Important The PXA255 has restrictive constraints concerning timing of successive interrupts While you may configure one or more XScale GPIOs as interrupt sources it s possible to create a condition under which interrupts in rapid succession can cause the processor to lock up ADS document 110115 40012 preliminary Applieddata net Fabela a open Feature Reference Function con
47. el note30 TI 1 1 ADS document 110115 40012 preliminary Applieddata net Fekete Computer Firda System Specifications Symbol Parameter Min Typ Max Units differential THD N 10 RI4 10 27 w differential THD N 1 RI920 10 034 w single ended THD N 0 5 RI320 75 85 mW single ended THD N 1 RI 80 II 240 mW single ended THD N 10 RIBO 440 mW 100 ka VHP IN thresholdvoltage 1 4 V Notes 28 The output sample rate is fixed but the input sample rate can be set to 8 11 025 22 05 or 44 1 kHz 29 Pre amp anti aliasing filter rolls off at 3dB octave first order filter 30 Typical values are guaranteed to National Semiconductor s AOQL Average Outgoing Quality Level Operating above typical values for a sustained period of time may result in thermal shutdown of the amplifier ADS document 110115 40012 preliminary Page 63 Applieddata net AGX User s Manual Feeder Coapite Spem 6 2 13 PXA255 Processor The XScale PXA255 core can change system voltage Vddi 6 2 2 dynamically to achieve lower power consumption at high clock rates It uses voltage Vddx to power its interface I Os The EIOn digital I Os include series resistance and ESD protection Serial ports configured for 3 3 V CMOS operation run directly to the processor section 4 5 1 These lines should be treated as digital I Os and protected for over curre
48. en running applications from RAM e Turbo mode runs the processor core at up to three times the Run mode speed Since external memory fetches are still performed at the memory bus frequency Turbo mode is best used when running the application entirely from cache Power Management on the AGX The AGX can actively be configured to be in XScale Run Turbo or Sleep modes Idle mode is controlled by the operating system or application and is typically transparent to the application In Turbo Run and Idle modes the power supplies are in their standard full power state and applications run normally on the system Specific subsystems as described in section 5 2 2 may be selectively disabled to conserve power during these states The operating system is responsible for adjusting the core voltage Vddi for optimal power consumption in each mode In Sleep mode sometimes called Suspend mode the processor puts the SDRAM in a low power self refresh mode the processor core shuts off most peripheral sub systems are shut down and the power supplies drop into low power states or turn off entirely see the diagram in section 5 2 2 for details In this state the AGX consumes very little power most of which is dedicated to the maintenance of the RAM see section 6 2 3 for specifications The system can be awakened ADS document 110115 40012 preliminary Page 47 Applieddata net AGX User s Manual Feed Computer Spem 5 2 9 2 1 9 2 2
49. erial Ports The AGX supports several serial port as described in section 4 5 1 Serial ports 1 through 3 are controlled by the XScale processor Serial ports A through D are controlled by an Exar ST16C554 or compatible quad UART EIA 232 signals are generated using charge pump devices e g Sipex SP3232 and SP3243 Signals 422 485 J1708 are buffered with the Maxim MAX491 IrDA signals from the XScale are converted to IrDA using a Vishay TFDU6100 infrared transceiver Symbol ME Parameter J Min Max Units Logic voltage CMOS serial ports EBENEN E NI ERN ET IrDA 4 5 1 VecRxirda Receiver voltage LL 33 V RvocRxirda Reciever power series resistance 10 Q VccTxirda Transmitter voltage J 33 _ V RvocTxlrda Transmitter power series resistance 36 Q Piirda Transmiterpower 330 630 mA USB The AGX supports USB operation as described in section 4 5 2 Ethernet The AGX uses an SMSC LAN91C111 10 100 BT Ethernet controller The MAC Media Access Control address is stored in a serial EPROM connected to the controller ADS document 110115 40012 preliminary Page 61 Applieddata net AGX User s Manual Devbecdded Exeter Spite 6 2 11 6 2 12 Page 62 CAN Bus The AGX uses the SJA1000T CAN controller with the Intel 82C251 CAN transceiver for its CAN bus capabilities Audio For its audio sub system the AGX uses the Crystal CS4202
50. estions The following are some of the most commonly asked questions for development systems Q When I plug in power my screen is white and nothing comes up on it A Check the connector seating The flat panel connector may have come loose in shipping Press it firmly into the panel and reapply power to your system Q When I plug in power the LED doesn t turn on A Your system may still be booting The LED is software controlled and is not necessarily turned on at boot Q Do I have to turn off the system before I insert a PCMCIA or CompactFlash card A No The AGX supports hot swapping of PCMCIA and CompactFlash cards Consult the operating system documentation for details Q Do I need to observe any ESD precautions when working with the system A Yes If possible work on a grounded anti static mat At a minimum touch an electrically grounded object before handling the board or touching any components on the board ADS document 110115 40012 preliminary Page 5 Applieddata net AGX User s Manual Frec Cragin ism 2 3 Page 6 Q What do I need to start developing my application for the system A You will need a flash ATA card 16 MiB or larger 32 MiB recommended and the cables supplied with your system to interface your development station to the system For further direction consult the ADS guide for the installed operating system Q Who can I call if I need help developing my application A ADS pr
51. fer to section 6 1 1 For details about how to determine pin numbers of a header see section 3 1 The location indicated for each item refers to the grid diagram of the AGX in section 3 1 1 Legend n c Not connected GND AGxX ground plane 3 3 8 Reference section for signals Signal Types I signal is an input to the system O signal is an output from the system IO signal may be input or output P power and ground A analog signal OCI open collector open drain input OC open collector open drain output J1 USB Host Port Board connector USB Type A Amp 787616 1 Location on board A1 Connector J1 provides the signals for USB host connectivity USB mice keyboards and other USB function devices may be plugged in Pin Name _ Type Description DC Power Input USB host J2 Input Power Connector Board Connector 1x6 Molex 22 23 2061 0 1 inch spacing Recommended mating connector Molex tbd Location on board A2 J2 supplies power to the AGA 45V IN is the main power supply with a factory option to supply 3 3 V to the system as well See section 5 2 1 for an overview of how the AGX power supply is structured Pin Name Type Description 5V input power 12V_IN 12V input power for backlight POWERON LSO Output for power supply management 5 2 1 ee VPERM Permanent voltage 5 2 1 ADS document 110115 40012 preliminary Page 15 Applied net AGX User s Manual Devbecdded Exete
52. fers can be run at 5 V for test purposes but if your application requires 5 V data contact ADS Sales to ensure the correct buffers are used for your display 15 Vcon is the filtered low voltage PWM signal used to control Vee It can be used directly with some passive displays to control contrast Vcon and Vee are controlled by PXA255 PWMO Vcon is the 3 3 V PWM signal RC filtered with a 25 20k 6 8kQ voltage divider 16 The 12 V voltage is supplied at power header J2 pin 4 The BacklightOn signal is an open collector output managed by the system controller CPLD 17 Asafactory option the pull up resistor can be removed for use with an external pull up resistor The maximum voltage rating of the transistor is listed 18 The standard configuration for BacklightPWM signal is as an open collector output with a 5 V pull up The output can also be factory configured as 5 or 12 V open collector or 3 3 V push pull CMOS output with or without an output filter capacitor The 12 V voltage is supplied at power header J2 pin 4 19 The backlight PWM output is driven by PXA255 PWM1 20 These digital l Os are available only if the Epson display controller is installed ADS document 110115 40012 preliminary Page 59 Applieddata net AGX User s Manual Feeder Coapite Spem 6 2 5 6 2 6 Page 60 Touch Panel Controller The AGX uses touch panel controllers from Burr Brown It uses the ADS7846 to support four wire analog re
53. hanging the position of a shunt The location indicated for each item refers to the grid diagram of the AGX in section 3 1 1 JP1 LCD Display Power Type 3 post header 2mm Location on board A6 This jumper selects the supply voltage for the LCD display The voltage selected here is passed to the PNL PWR pins on J11 and J19 Voltage Selected WARNING Make sure you have selected the correct voltage before connecting the panel Flat panels can be irreparably damaged by incorrect voltages JP2 Source of 3 3 V Power Vddx Type 3 post header 2mm Location on board A2 ADS document 110115 40012 preliminary Page 11 Applied net AGX User s Manual Fredes Credo yatim 3 3 3 3 3 4 3 3 5 Page 12 This jumper selects the source of 3 3 V power Vddx for the system Standard production systems include an onboard 3 3 V regulator but an external 3 3 V supply 3 3V_IN from J2 can alternatively be used Jumper setting Vddx is supplied by JP3 LCD Display Data Voltage Type 3 post header 2mm Location on board A6 This jumper selects the voltage for the data signals to the LCD display Important These jumpers are set at the factory to match the panel and drivers shipped with the system You may damage the panel or panel drivers if you change this jumper setting Tip Most 5 V panels will run correctly with 3 3 V data Jumper setting Data to display is JP4 Serial 2 Mode Select Type 2x9
54. herently low power consumption of the system This chapter describes the architecture of the AGX power supply factors affecting power consumption and reference designs to get you started For information about how much power the AGX consumes consult the electrical specifications in section 6 2 3 Power Management Modes Most handheld and portable systems available today never really turn off They make use of power management algorithms that cycle the electronics into standby and sleep modes but never fully remove power from the full system This section describes the various power management modes of the XScale processor and how the AGX makes use of them XScale Power Management Modes The XScale PXA255 processor supports four operational modes Turbo Run Idle and Sleep e Sleep mode uses the least amount of electrical power The processor core is powered off and only a few processor peripherals RTC I Os and interrupt control remain active The transition back to Run mode may take a few hundred milliseconds as clocks must stabilize and hardware that was powered off must be reinitialized e Idle mode reduces power consumption by pausing the processor core clock Processor peripherals remain enabled This mode is used for brief periods of inactivity and offers a quick transition back to Run mode e Run mode is the typical mode used when applications are running It offers the best MIPS mW performance vs power performance wh
55. ing system status These LEDs can often be used by applications to indicate operational status Signal Name LEDOUTO D Green LEDOUTI D8 Amber LEDOUT2 The LEDs are driven by the same buffers as the display driver data lines so will be off when the display buffers are disabled see power management section 5 2 2 The LEDs are ADS document 110115 40012 preliminary Applieddata net 3 2 4 3 2 5 3 3 3 3 1 3 3 2 Enketa Ernzer Padmi Hardware Reference Ethernet LEDs Location on board D7 on Ethernet socket J7 Two LEDs on Ethernet socket J7 indicate when a valid Ethernet connection has been made and when there is activity on the bus USB LED Location on board B6 This LED indicates when there is activity on Philips USB ports On The Go or host See section 4 5 2 for further details Signal Name USB GL IrDA Transceiver Location on board D1 D2 U22 is an IrDA transceiver that converts Serial 2 electrical signals to infrared light pulses for IrDA communications See section 4 5 1 for further details VR1 Vee Contrast Adjustment Location on board C7 Vee 1s the contrast adjustment voltage required for most passive LCD displays VR1 and a PWM signal set the output voltage for Vee See section 4 8 3 for further details Jumper Settings Jumpers on the AGX select a variety of operational modes All use 2mm shorting blocks shunts to select settings Turn off power to the AGX before c
56. ing LCD Display Cables ADS has designed cables for a wide variety of displays See the list of supported displays on the ADS support forums Cable drawings for supported displays are available on request While ADS does not provide support to customers to create their own cables designers with LCD display experience may be able to design their own For those that do so a key point to keep in mind is that the PXA255 LCD interface maps its display controller pins differently based on LCD technology and color palette size The following table illustrates how they are mapped for some of the more common technologies Consult the PXA255 User s Manual for more information XScale je Mono Passive Seen p i DPD LDDO0 BO BO D LDD4 B4 G4 E NUN R Single z Q Ci 1 Q Seed J OX Urn Single DI 2 we jp wih A iii O 3 qum O M E Go ROT ka UY 2 LDDI4 R3 R3 LDDIS R4 PD PCLK LCLK FCLK SATATA TA KANAKA KA KANAN cola oae IS ESSI ES LA E D D D D D D 1 2 3 4 0 1 2 3 4 5 0 1 2 3 4 NIAJ 16 Intel PXA255 Processor Developer s Manual Order number 278693 001 March 2003 pp 7 20 to 7 22 Double pixel data DPD mode 1 ADS document 110115 40012 preliminary Applieddata net 4 8 4 Entitet Greywin Spini Feature Reference LVDS for LCD Displays The AGX includes an LVDS Low Voltage Differential Signaling driver su
57. itable for driving some LCD displays LVDS multiplexes digital signals together onto differential pairs LVDS has the advantage of using fewer wires longer cable lengths and lower radiated noise LVDS signals are available on header J12 The table in section 3 4 10 illustrates how the display signals are multiplexed onto the LVDS differential pairs Electrical specifications for the LVDS transmitter are provided in section 6 2 4 Brightness Control Backlight Most LCD displays include one or more cold cathode fluorescent lamp CCFL tubes to backlight the displays Some LCDs such as passive transflective displays can be viewed in daylight without backlighting Panel backlights are driven by backlight inverters These circuits are typically external to the display and generate the several hundred volts required to drive the CCFL tubes Backlights can easily become the greatest source of power consumption in a portable system Fortunately most backlight inverters include control signals to dim and turn off the backlight The AGX supplies two signals for backlight control BacklightPWM and BacklightOn The signals are found on both J3 and J15 BacklightPWM is a filtered PWM signal from the PXA255 that supplies an analog output voltage to control the intensity of the backlight The BacklightOn signal is an open collector output to turn the backlight on and off See section 6 2 4 for electrical specifications Contrast Control Vee and Vcon
58. le for all operating systems CompactFlash and PCMCIA ATA Cards CF and ATA cards provide removable storage in a wide variety of capacities These cards can be cost effective means to expand system storage capacity for applications that provide access to the PCMCIA and CF slots 128 MiB SDRAM was not yet commercially available as of April 2003 ADS document 110115 40012 preliminary Page 29 Page 30 Applied net AGX User s Manual Fe beclied Cougar Pada mi RTC NVRAM The real time clock chip includes 56 bytes of non volatile RAM The RAM is maintained as long as main or backup power is provided to the chip Drivers are not currently available to access this feature Contact ADS Sales if your application requires this feature Interrupts The AGX includes several sources for external interrupts The following table summarizes the external interrupt sources and the devices to which they are connected Interrupt Signal Pin IRQ Handler RqOnOff J9 15 PXA255 GP 0 EXT IRQ J8 24 Controller CPLD CARDBIRO J4 37 PCMCIA CPLD XScale GPIOs XScale CPU Your operating system may not include drivers for all interrupt sources CompactFlash Expansion Bus The AGX makes its CompactFlash bus signals available on J4 3 4 4 These signals can be used to add a CompactFlash socket to a daughter board or to expand the capabilities of the AGX as a digital expansion bus The voltage of the bus signals is fixed at 3 3 V Electrical sp
59. mplementation See section 6 2 15 for electrical specifications ADS document 110115 40012 preliminary Page 19 Applied net AGX User s Manual Devbecdded Exeter Spite 3 4 9 J11 LCD Display 34 pin Board Connector 2x17 header 2mm spacing STMM 117 02 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 117 02 F D 500 Location on board A6 B6 The following table describes the signals on the LCD interface connector Signal names shown are for TFT active matrix color LCDs at 16 bpp bit per pixel For other color depths and LCD technologies consult the table in section 4 8 3 Signals from the XScale are buffered and RFI filtered before reaching Jl See section 4 8 for further details about displays EAR Color Active TFT Display at 16bpp Signal Name ADS Signal Name 1 5 PNLVEE Veglcontrast seeJP9 WER GND 3 LPCLK PNLPIXCIK Pixel Clock ground L ES aie L _DDI5 REDS ata SR Rat TT a TT EMEN PNL_PWR Vee 5 V or 3 3 V JP3 Horizontal Mode Select Go Rote Qo NO M Vertical Mode Select ENECUM set by JP36 CPLD PNL ENA Panel enable signal low voltage adjust for contrast Qo ho E aH ur EE 10 WC EA 15 ECN E 18 Be 20 22 23 E24 EN L2 Page 20 ADS document 110115 40012 preliminary Applieddata net Fabela a open Hardware Reference 3 4 10 J12
60. n bsdteg Gregwin Setzen This page intentionally blank Page viii ADS document 110115 40012 preliminary Applieddata net 1 1 1 1 2 1 2 1 1 2 2 1 2 3 Febedieg Cepia Friemt Introduction Overview The AGX is a full featured single board computer using the PXA255 XScale RISC microprocessor The AGX is designed to meet the needs of embedded and graphical systems developers This manual applies to the most current revision of the AGX listed in the Revision History Chapter 7 Features Processor e PXA255 32 bit XScale e Clock rates up to 400 MHz e Voltage and frequency scaling Power Supply e 5 V Main Power e System Backup and Real Time Clock Power Inputs Memory e 616 32 64 or 128 MiB synchronous DRAM e 8 16 32 or 64 MiB flash RAM e PCMCIA and CompactFlash CF Type I and II 3 3 and 5 V The AGX supports 128 MiB SDRAM However those components are not yet commercially available as of April 2003 MiB is the IEC abbreviation for mebibyte 2 byte 1 048 576 byte The kibi and mebi abbreviations are based on the 1998 IEC standard for binary multiples For further reading see the US NIST web site http physics nist gov cuu Units binary html The BitsyX supports synchronous and asynchronous flash The 64 MiB flash option is available only in synchronous flash CompactFlash is a trademark of the CompactFlash Association http www compactflash org ADS document 110115 40
61. n draw up to 3 mA The AGX implementation of DC will work with most SMBus devices The most likely point of conflict is in the AGX IC bus current draw see the pull up resistor specifications in section 6 2 6 and 6 2 13 If your configuration will use DC as an SMBus controller contact ADS Sales to discuss the AGX configuration you ll require Multimedia Card MMC Controller The XScale MMC controller provides a serial interface to MMC cards The controller supports up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps The MMC controller has FIFOs that support DMA access to and from memory This interface can also be used to access Secure Digital SD Memory Cards and Secure Digital I O SDIO cards See Intel Application Note 278533 for details and pitfalls Signals for the MMC Controller are brought out to header J7 See the XScale Developer s Manual for details about how to use the MMC interface Drivers for MMC may not be available for all operating systems Contact ADS for driver availability for the operating system you are using 12 ACPI Advanced Configuration and Power Interface http www acpi info P Smart Battery Implementers Forum http www sbs forum org Maxim application note 356 http dbserv maxim ic com appnotes cfm appnote_number 356 ADS document 110115 40012 preliminary Page 41 Applieddata net AGX User s Manual Feeder Coapite Spem 4 6 4 6 1 4 6 2 4 6 3 4 7
62. n the board and how to determine how each header 1s numbered Locating Connectors The following diagram illustrates the location of key components on the AGX For example the PXA255 processor is located at C4 and the reset button is at A6 Component listings in this chapter refer to this diagram 1 2 6 7 a my B8 rE OL J8 Hr g B NM JP5 JP6 JP7 gu OT NT a ga C eie eL s En E O 4 IR D II AM a c i UFa Determining Pin Numbers The pins of headers and connectors on ADS products are numbered 2 sequentially Double row headers place even pins on one side and odd pins on the other The diagram at right indicates how pins are numbered as seen from the component side of the board To locate pin 1 of a connector or jumper try the following The component side of the AGX is the one on which the PCMCIA ejector is installed As a factory option some through hole connectors may be installed on the bottom side of the AGX Page 9 Applieddata net AGX User s Manual Feeder Coapite Spem 3 2 3 2 1 3 2 2 3 2 3 Page 10 1 Look for a visible number or marking on the board that indicates connector pin numbering A notch or dot usually indicates pin 1 2 Look at the underside of the board The square pad is pin 1 3 Download the mechanical drawing of the AGX from the ADS Support site section 2 4 The square or indicate
63. nector section 12 MMCCD O MMcCcarddetect J7 4 5 6 15 CSI O Asynchronous flash chip select 16 VEEPWM O PWMoOcontrolofVeevoliage PWMI backlight brightness control RDY Variable latency access CPU ready LEDI LEDO RD LED2 22 S Y 3 SCLK C M NO Oo 0 Onboard LED outputs 1 unused 4 SFRM C 5 TXDC RXD C 1 1 SYNC 32 RTS2 CS_GC SPI to touch panel controller Reset ADSmartlO controller 2 2 2 2 2 2 2 2 2 3 AC97 Codec 9 0 3 23 KS Ai ECH 30 31 32 ERE Serial 2 RTS 4 5 1 Graphics controller chip select Full featured UART J13 J15 4 5 1 4I PERIS 42 BTRXD 1 I 45 BTRIS O IR RXD IR TXD O Infrared Serial 2 J14 J15 4 5 1 48 POE 49 PWE 50 MIOR 51 iow EE MM PCMCIA CF Card interface 54 PSKTSEL 55 PREG 56 want 57 NO0ISI6 Bluetooth UART J14 4 5 1 A ADS document 110115 40012 preliminary Page 31 Applied net AGX User s Manual En bsdteg Gregwin yadimi 4 2 4 3 4 3 1 Page 32 Function connector section 58 LDDO O 59 NDT Ji 60 LDD2 O Ol AD p 39 62 LDD4 O 63 LDDS O 64 L n O 65 LDD7 O 66 LDD8 O 69 LDDII O 70 LDDI2 O oad p LOD O 72 LDDI4 O EE O 74 LFCLK O 75 LICLK O
64. nt and over voltage accordingly Absolute Maximum Ratings Input voltage digital I O pins 3 6 V Symbol Parameter i Max Units Digital Outputs Voh A AN Von pup AAA Digital Inputs 12C Bus 4 5 5 bus clock note 31 po buffersize pull up on SDA SCK resistance to ADSmartlO bus Notes 31 The PXA255 supports standard and fast I2C speeds of 100 and 400 kHz 6 2 14 Crystal Frequencies Agencies certifying the AGX for compliance for radio frequency emissions typically need to know the frequencies of onboard oscillators The following table lists the frequencies of all crystals on the AGX Device Typ Units ADSmartlO microcontroller 3 6864 System clock generator 16 000 XScale RTC 32 768 Page 64 ADS document 110115 40012 preliminary Applieddata net Entera Cee Syrum System opecifications 6 2 15 PCMCIA and CompactFlash Controller AGX PCMCIA and CompactFlash control logic is managed by a Xilinx XCR3032XL CPLD with firmware developed by ADS The signals run through buffers before going to the PCMCIA J10 3 4 8 and CompactFlash J4 3 4 4 headers On the AGX the CompactFlash CF port can be used as a digital expansion bus See section 4 1 5 for details Absolute Maximum Ratings Input voltage port I O pins eeessssssss 6 5 V Symbol Parameter Min Typ Max Units PCMCIA CF buffer power CMC C PCMCIA and
65. or digital I O Serial 2 EIA 232 Serial 1 EIA 232 with 3 3 V CMOS factory option PA ADSmartlO Keypad columns or digital I Os 3 COL7 RX422 22 I TX4224 26 O Serial 1 EIA 422 485 TX42 28 O CPLDIOS 36 IO e E I E ADSmartIO A D reference voltage 5V 3 3 V HE a o ADS document 110115 40012 preliminary Applieddata net Fabela a open Hardware Reference 3 4 13 J15 Audio Touch Panel Backlight CAN Serial 3 IrDA USB Host Board Connector 2x20 header 2 mm spacing Samtec STMM 120 02 T D Recommended Mating Cable Samtec TCSD Series Recommended Board to Board Connector ESQT series e g ESQT 120 02 F D 500 Location on board B2 D2 Name CANHIGH CANLOW USB_M_VCC USB_M_UDC USB_M_UDC USB M GN TSPX TSPY TSMX TSMY WIPER GND RIB3 DCD3 TXD RXD3 CTS3 RTS3 DSR3 Type 70 CAN bus 4 5 4 USB Host AIO bottom lef LL Touch screen Backlight on off 4 8 3 Backlight intensity control 4 8 3 PO 12 V power for backlight from J2 3 4 2 E Stereo speaker right channel E Stereo speaker left channel Serial 3 ground EPOR oO IrDA 4 5 1 o LIN M Z Qo 4 IO IO nh N u o M LA Qo M BacklightOn BacklightPWM 12V y O SPKR SPKR SPKL SPKL GNDCOM3 VCCTXIRDA RXIRDA TXIRDA VCCRXIRDA IRDAON AGND NO No p gt gt gt D gt Soolo Y o D gt gt Bol lig
66. ough pre amplifiers that low pass filter and boost the signal before being passed on to the audio codec When connecting external electret microphones to the AGX use the MIC_GND analog ground plane for improved signal to noise ratio The AGX includes pull ups to power electret microphones Audio Outputs Speakers and Headphones The AGX audio amplifier supports both differential and single ended output devices Differential or bridge drive delivers greater output power and is suitable for speakers which can be wired independently from each other Single ended mode is used for devices like headphones which have a common ground between output channels I PC6 and PC7 are used for the UC bus master interface See section 4 5 5 for details These pins can be reconfigured as digital I Os for custom production applications ADS document 110115 40012 preliminary Page 35 Applieddata net AGX User s Manual Errdie Comidas pada mi The HP IN input J3 32 determines the output mode of the amplifier When HP IN is high the audio output drive is single ended when HP IN is low the output drive is differential An on board pull up normally keeps HP IN high Connecting Speakers When using the AGX to drive speakers short the HP IN signal to ground This places the output amplifier in differential mode Connect speakers to the SPKR_L and SPKR R outputs on J10 Connecting Headphones Standard headphones use a plug wired as shown a
67. ouse e 2D display engine e General purpose digital I Os Standard development systems make use of the basic features of the display controller Contact ADS Sales 1f your application requires use of the advanced features of this controller Electrical specifications for the controller are listed in section 6 2 4 Using the LCD Display Signals This section describes the features of the AGX used to control LCD displays LCD display signals are found on headers J3 J11 J12 J15 and J19 Panel Voltages The AGX supplies 3 3 V or 5 V power to the LCD display Select this voltage with JP1 section 3 3 1 Please observe the cautions listed with the JP1 settings P Currently posted at http www applieddata net forums topic asp topic_id 580 ADS document 110115 40012 preliminary Page 43 Page 44 Applied net AGX User s Manual Febre Saad Fatini LCD Signals The LCD signals are driven by either the XScale or the Epson controller The signals are named using the XScale conventions L_DDn L DDO through L DD15 as well as the pixel clock vertical sync and horizontal sync are all buffered at a factory set voltage See section 6 2 4 for full specifications The PNL RL and PNL UD signals are for active TFT displays that support changing the scan direction This feature allows the display to be flipped right to left RL or up and down UD by changing the voltage on these signals See section 6 2 4 for full specifications Creat
68. ovides technical support to get your development system running For customers who establish a business relationship with ADS we provide support to develop applications and drivers Q Is there online support A Yes Information about the AGX hardware and software is available on the ADS support site at http www applieddata net support See section 2 4 for further details Q Can I upgrade the version of the operating system A Yes ADS provides regular operating system updates on its developers web site For operating systems not maintained by ADS contact the operating system vendor Q I would like to interface to a different display panel How can I do this A ADS may have already interfaced to the panel you are interested in Consult ADS for availability Organization of this Manual The manual organizes information in five key sections Introduction Provides an overview of the functionality and organization of the AGX as well as how to use this manual Hardware Reference Describes the configuration settings and pinouts for all connectors and jumpers on the AGX Feature Reference Gives details about the various subsystems of the AGX Power Management Provides key information about power management tips for system integration and electrical and mechanical interface specifications Specifications Electrical and mechanical interface specifications To locate the information you need try the following 1 Browse the T
69. r Spite 3 4 3 J3 Backlight Inverter Board Connector Molex 53261 0790 Recommended mating connector tbd Location on board A2 A3 Pin Name Type Description Power supply for backlight inverter also available on J15 pins 23 and 24 l On off control for backlight inverter E also available on J15 pin 21 l Brightness control for backlight inverter ES Ge also available on J15 pin 22 3 4 4 J4 CompactFlash Expansion Bus Board Connector Samtec ASP 100925 01 Recommended Mating Connector see below Recommended Board to Board Connector none Location on board A3 A4 The AGX makes its CompactFlash bus signals available on this header These signals can be used to add a CompactFlash socket to a daughter board or to expand the capabilities of the AGX as a digital expansion bus See section 4 1 5 for details Although the header included on the AGX does not include guide rails you can plug a CompactFlash card directly onto this socket for testing purposes The top of the card should face the PCMCIA header Support the card mechanically to avoid bending the pins Pin E Data 8 10 NC AE 8 Data0 2 Pin MEM vi e IO IO IO IO IO IO 1 1 CARDBSPK CARDBREG ESA EE Lo VCC I EA LS O I V CARDBWAIT j CARDBRES CARDBVS2 Y Page 16 ADS document 110115 40012 preliminary Applied net Febediog Cogan Span Hardware Reference Name Type PCBAO
70. re The corner frequency for the low pass filter created by the capacitor and the headphone speaker is calculated as fo 1 2TTR C A 330 uF capacitor into a 32 ohm headphone speaker will give a low cutoff frequency of 15 Hz Use electrolytic capacitors rated for at least 6 3 V The pull down resistors shown in the diagram drain any charge that builds up on the headphone outputs when headphones are not connected Use 1 kQ resistors Page 36 ADS document 110115 40012 preliminary Applieddata net Entitet Greywin Spini Feature Reference Using Stereo Headphones and Speakers in the Same System Some applications use both headphones and speakers You can wire the headphone jack to automatically switch the amplifier to single ended sent mode when a headphone plug is inserted in the jack This will disable the drive to any speakers that are m wired into the system Headphone jack Most headphone jacks include mechanical switches that indicate when a headphone plug has been inserted The diagram at right shows a circuit that pulls down the HP IN signal when a headphone plug is removed For this circuit to work reliably in differential mode the HP IN signal must remain below Vyp m through the largest output voltage swings of SPKR_L Use of 1 kQ resistors meets this requirement 4 5 Data Communications The AGX has several built in channels for communication with peripheral and peer devices These include EIA TIA 232 422 and
71. roduction Options The AGX has a number of production options detailed throughout this manual This section describes options that most significantly affect the mechanical design of the board These options are generally available only for volume production orders Mating Headers on Underside of Board The four system signal headers J1 J3 J9 and J10 can be mounted on the underside of the AGX This allows the AGX to sit on top of another board Important When the headers are placed on the underside of the board the pin numbers will not correspond to the signals as described in this manual Lay out the mating board with this in mind Hemoval of PCMCIA Header Systems can be produced without the PCMCIA header However since most ADS operating system ports rely on the header for file updates this option is not recommended A special operating system build may be needed if the PCMCIA header is removed Connector Plating Most connectors on the AGX come standard with tin plating which is suitable for most applications For applications where the headers will go through many insertion removal cycles ADS can populate headers with gold or other suitable platings The PCMCIA header comes standard with gold plating ADS document 110115 40012 preliminary Applieddata net Enbecitnd Computer ratum System Specifications 6 2 Electrical Specifications 6 2 1 Reset Sleep Wakeup Temperature Absolute Maximum Ratings Reset Input R
72. sistive touch panels and the ADS7845 to support five wire panels The system is factory configured for use with four wire panels All touch panel signals are ESD and RF protected The touch panel controller is powered during sleep mode and can generate an interrupt to wake the system Symbol Parameter Min Typ Max Units Vdd Supplyvoltage 1 Vdx V A D sample resolution en es ae oe ADSmartlO Controller The ADSmartIO Controller is a second RISC microcontroller on the AGX designed to handle I O functions autonomously The AGX communicates with the ADSmartIO controller via the system controller CPLD On the AGX ADSmartIO is implemented with the Atmel AVR 8535 microcontroller which has 512 bytes EEPROM Absolute Maximum Ratings Input voltage any pin eese 3 8 V Input voltage A D inputs PA5 PA7 note 25 15 V Symbol Parameter Min Typ Max Units Vdd Rs Vprot V Digital Outputs 4 3 3 V V lt lt sink see notes 21 22 source see notes 21 22 Digital Inputs 4 3 3 Bel AA Software selectable pull ups to 3 3 V see note 23 n resolution note 24 Rin input impedance note 25 Vin Vref kret Vref 12C Bus 4 5 5 note 27 Bus clock Lal iputbuffersze LL 32 bye Tpaketsize T 32 byte pde 4 4r ka iios E 1 298 EN Notes 21 Row and column l Os have series resistance and overvoltage protection
73. t right Three rings on the plug provide right and left channels and a common return Mono headphones do not include the center ring Fina left channel Tip right channel or mono The mating headphone jacks include spring contacts to make an electrical connection with the headphone and to mechanically hold the plug in place Some jacks include a mechanical switch suitable for use with the HP IN signal that is activated when a plug is inserted into the jack Mono Headphones You can connect mono headphones directly to the Gen HPN AGX as shown at right Keep in mind that the resulting impedance of the parallel connected SPKR R 3 headphone speakers is half that of a single Headphone jack headphone speaker See the audio driver specifications in section 6 2 10 for details about the minimum impedance an audio output channel can drive SPKR Lt 4 Stereo Headphones ML When wiring for stereo headphones wire blocking SPAR ni capacitors in series with the AGX SPKR signals as Headphone jack shown at right These capacitors block the DC component of the audio signal and complete the conversion from differential to single ended output drive Leave the HP IN signal pulled high to enable headphone output Select blocking capacitor size based on the lowest frequency your application will need to play out Larger capacitors give improved bass response lower frequency cutoff but are physically larger and cost mo
74. ude it when connecting the USB signals to the AGX The AGX includes the capability to simulate a Function port cable disconnection This feature can be used to force the host to re enumerate the AGX e g after wakeup USB On The Go The USB controller on the AGX supports USB On The Go This standard has the following features to better support mobile devices e Limited host capability to communicate with selected other USB peripherals e Asmall USB connector to fit the mobile form factor e Low power features to preserve battery life USB On The Go signals are on header J40 section 3 4 18 Contact ADS Sales if your application requires USB On The Go as drivers may not be available for all operating systems LED Activity Indicator LED D20 3 2 3 blinks to indicate when there is activity on the Philips USB ports 4 5 3 Ethernet The AGX includes a 10 100 BT Ethernet controller with an RJ 45 socket J7 The Ethernet signals are also available on header J9 3 4 7 for connection to an off board socket Details and electrical specifications are listed in section 6 2 10 4 5 4 CAN Bus CAN bus Controller Area Network is a protocol developed for the automotive industry that 1s increasingly being used in industrial control and automation applications The AGX includes a CAN controller suitable for connection to a wide range of CAN networks The CAN signals are available on headers J15 3 4 13 and J17 3 4 15 Details and electrical
75. uring Sleep Page 52 When designing systems for minimal power consumption during Sleep mode make sure to consider DC losses to external connections The following are a few of the ways your system may leak when asleep e PCMCIA and CF cards Cards in place when the system is asleep can drain power through the Card Detect and Voltage Sense lines Assume that all four lines ground the AGX PCMCIA pull ups section 6 2 15 while the card 1s inserted ADS document 110115 40012 preliminary Applieddata net Ebet Cette Fraen Power and Power Management e Digital I Os Review digital I O connections for potential voltage differences from external connections when the AGX is asleep e USB Depending on how USB devices are powered and how the operating system handles USB USB devices may draw power during Sleep ADS document 110115 40012 preliminary Page 53 Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page 54 ADS document 110115 40012 preliminary Applied net Entera Cepia Friemt 6 System Specifications 6 1 6 1 1 Mechanical Specifications The AGX is 4 0 inches by 7 0 inches in size This section describes the component dimensions and mounting of the board Detailed drawings are available on the support forums section 2 4 and 3D models are available from ADS in electronic format for production customers Mechanical Drawing The following mech
76. uts CompactFlash Connector LCD Panel r Touch Screen 4 or 5 wires USB IF USB OTG USB HOST CAN Bus d USB Slave Audio Output Audio Input ADS document 110115 40012 preliminary Page 3 Applieddata net AGX User s Manual En bsdteg Gregwin Setzen This page intentionally blank Page 4 ADS document 110115 40012 preliminary Applieddata net Febedieg Cepia Friemt 2 Getting Started 2 1 Development Systems AGX boards are shipped as development systems designed to get the developer up and running quickly To use the system simply plug power supply into the mini DIN 8 receptacle on the system If the screen does not display anything after five to ten seconds check the Frequently Asked Questions below Most operating systems cold boot within twenty seconds 2 1 1 System Components A typical development system 1s shown at right system shown includes a BitsyX It consists of the following components tbd e AGX single board computer e Flat panel display and cable e Backlight inverter and cable e Touch screen and cable e 120 VAC power adapter e Plexiglas mounting e Developer s Cable Kit including e Serial Port DB9 adapter ADS cable 610111 80001 e DB9F F null modem cable e Operating system of your choice e User s Guide this document and operating system guide Please make sure you have received all the components before you begin your development 2 2 Frequently Asked Qu
77. y life Applications and the operating system determines how selective power management is utilized ADS document 110115 40012 preliminary Applieddata net Entera Cee Syrum Power and Power Management AGX systems that can be selectively disabled include the following LCD display panel power and signal buffers Display controller if installed Backlight Vee contrast Audio codec and microphone pre amps Audio output amplifier Serial A B and 3 IrDA transceiver In addition the AGX also controls its core power supplies to support sleep operation Vddx 3 3 V Vddi processor core The following diagram illustrates the architecture of the AGX power management system At the heart of the system is a power controller that controls the state of the various power subsystems of the AGX Under control of the XScale processor this controller can manage most of the power distribution of the board The XScale PowerEnable signal controls the rest of the subsystems 18 I5 The controller inverts the PowerEnable signal for use with some subsystems This details is not shown in the diagram ADS document 110115 40012 preliminary Page 49 AGX User s Manual A plieddata net Febedieg Cepia Spd ami 5 2 9 Page 50 Power Management Flow PC Card AGX In the diagram the power management modes of each subsystem are indicated in gray Arrows

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