EVBUM2305 - NB752MMNGEVB Evaluation Board User`s Manual
Contents
1. the SMA connectors and is not to be confused with the device ground VEF DUTGND SMAGND and DUTGND can be connected in a single supply application The power pin layout and typical connection for the evaluation board is shown in Figure 7 It 1s recommended to add bypass capacitors to reduce unwanted noise from the power supplies Connect 0 1 UF capacitors from Vcc and VEE DUTGND to SMAGND Output Loading Termination CML Outputs For the termination of CML outputs operation with negative supply voltages is recommended to enable the use of the 50 62 internal impedance of an oscilloscope or other measurement instrument Since CML output termination requires 50 Q to Vcc off setting the power supply such that Vcc 0 V and DUTGND 2 5 V or 1 8 V will allow oscilloscope and VCC to be at the same potential CML outputs can now be conveniently terminated using the 50 Q internal impedance of oscilloscope or other measurement instrument Installing SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given device Each input and output requires one SMA connector Install all the required SMA connectors onto the board and solder the center signal conductor pin to the board on JI through J16 Please note that the alignment of the signal connector pin of the SMA connector to the metal trace on the board can influence lab results The launch and reflection of the signals are largel2. L Interface 1 ji NB7V52M Zo Q D CLK R 50 0 CML Driver 50 Q D CLK R Zo 50 4 VTX VTX Vcc GND VEE GND VEE NOTE X D CLK R amp X D CLK R Figure 11 Standard 50 CML Interface www onsemi com 7 SMAGND SMAGND SMAGND SMAGND NB7V52MMNGEVB O O O O SMAGND SMAGND SMAGND SMAGND VCC 10 uF 2 z SMAGND 1 0 1 uF 1 2 NB7V52M 3 4 T 0 1 uF LO co N 00 gt SMAGND 10 uF Her V VEE DUTGND SMAGND SMAGND SMAGND SMAGND Figure 12 NB7V52MNGEVB Schematic www onsemi com 8 SMAGND SMAGND SMAGND SMAGND NB7V52MMNGEVB TYPICAL OUTPUT WAVEFORMS File Edit View Setup Utilities Applications He Tektronix qa etere Fred 1 n 300 1398MHz Ampl CIA AT BABY Dty CIA 49 74024 Freq C2 A 4998992MHz Ampl C2 TE 405 2031my B 0ty C2 A 50 386669 lo a 100 0 sti 280 0r 260 0rny E va main a a i 000ps 5 450n El pr 5 00 PM 6 17 2015 Figure 13 Typical O amp Q at Fin 1 GHz Vee 1 8 V 25 C File Edit View Setup Utilities Applications Help Triggered Tektronix X Acq Mode Average gt Tria External Direct 202 rni 3 i fut zal pa gt eg s sk ze MA por ila 100 On Wi l 10D Dr wdi F
3. NB7V52MMNGEVB NB752MMNGEVB Evaluation Board User s Manual Introduction ON Semiconductor has developed the QFNI6EVB evaluation board for its high performance devices packaged in the 16 pin QFN This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the operation of various ON Semiconductor products Many QFN16EVBs are dedicated with a device already installed and can be ordered from www onsemi com at the specific device web page Evaluation Board Manual Contents e Information on16 Lead QFN Evaluation Board e Assembly Instructions e Appropriate Lab Setup e Board Schematic e Bill of Materials This user s manual provides detailed information on board contents layout and its use This manual should be used in conjunction with NB7V52M data sheet which contains full technical details on the device specifications and operations Board Layout The QFN16 Evaluation Board provides a high bandwidth 50 Q controlled impedance environment and is implemented in four layers The first layer or primary trace layer is 0 008 thick Rogers RO4003 material and is designed to have equal electrical length on all signal traces from the device under test DUT pins to the SMA connectors The second layer is the 1 0 oz copper ground plane and is primarily dedicated for the SMA connector ground plane FR4 dielectric material is placed between the second and third layers and betw
4. RATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2305 D
5. appropriate input levels 4 Connect NB7V52M outputs Q amp Q to appropriate oscilloscope channel Board does not have 50 02 output termination resistors thus internal 50 Q of oscilloscope can be used to properly terminate outputs 5 Connect internal 50 62 pins VTCLK VTCLK VTD VTD VTR and VTR to appropriate levels See Figures 9 11 for appropriate Input level interface 6 Connect R amp R Input Output select values to appropriate levels See Table 3 for levels NOTE See NB7V52M data sheet for D to CLK set up and hold times Power Up Sequence 1 Turn On DUT Power Supply 2 Enable Generator Outputs 3 Monitor Q amp Q Outputs with Oscilloscope www onsemi com 5 NB7V52MMNGEVB Table 2 POWER SUPPLY LEVELS Table 3 RESET INPUT OUTPUT SELECT TRUTH TABLE Table 4 NB7V52M CML OUTPUTS SPLIT POWER SUPPLY CONFIGURATION Dual Power Supplies DUTGND SMAGND 12 5 V www onsemi com 6 NB7V52MMNGEVB 1 NB7V52M D CLK R 2 LVDS Driver 50 Q L o 4 D CLK R lt J Zo 50 Q ee V J GND VEE VIX VIX GND VEE NOTE X D CLK R8X D CLK R Figure 9 LVDS Interface ji 4 NB7V52M Z0 502 lo ar gt 500 LVPECL VIX Driver VTX 50 z D CLK R HI J 202509 L i VTX VTX Vec 2 V GND VEE GND VEE NOTE X D CLK R amp D CLK R Figure 10 LVPEC
6. e DUT pin which provides an option of placing a termination resistor on the board bottom depending on the input output configuration See Table 1 Example Configuration List Table 5 contains the Bill of Materials for this evaluation board The QFNI6EVB was designed to accommodate a custom OFN 16 socket Therefore some external components are installed on the bottom side of the board Solder the Device on the Evaluation Board The soldering of a device to the evaluation board can be accomplished by hand soldering or solder reflow techniques using solder paste Make sure pin 1 of the device is located properly and all the pins are aligned to the footprint pads Solder the QFN 16 device to the evaluation board As mentioned earlier many QFNI6EVB s are dedicated with adevice already installed and can be ordered from www onsemi com at the specific device webpage Connecting Power and Ground On the top side of the evaluation board solder the four surface mount test pint clips anvils to the pads labeled Vcc VEE DUTGND SMAGND and ExPad ExPad is connected to the exposed flag and is typically recommended to be tied to VEE DUTGND the negative supply of the device The positive power supply connector is labeled Vcc Depending on the device the negative power supply nomenclature is labeled either GND or VEE To help avoid confusion with the use of this board the negative supply connector is labeled VEF DUTGND SMAGND is the ground for
7. een third and fourth layers The third layer is also 1 0 oz copper plane A portion of this layer is designated for the device VCC and DUTGND power planes The fourth layer is the secondary trace layer Semiconductor Components Industries LLC 2015 1 July 2015 Rev 0 ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL Figure 1 NB7V52MMNGEVB Evaluation Board Top View MN NB7V52M EER ROHS COMPLIANT REV F Figure 2 NB7V52MMNGEVB Evaluation Board Bottom View Publication Order Number EVBUM2305 D NB7V52MMNGEVB Figure 3 Enlarged Bottom View Pin 12 Pin 1 Pin 11 Pin 2 Pin 10 Pin 3 Pin 9 Pin 4 Figure 4 Enlarged Bottom View of Evaluation Board SILKSCREEN TOP SIDE LAYER 1 TOP SIDE 1 OZ V ROGERS 4003 0 008in 7 Y Y LAYER 2 GROUND PLANE P1 1 OZ 0 062 0 007 Z FR 40 020in LAYER 3 GROUND VCC VEE PLANE P2 1 OZ L FR 40 025in 44 LAYER 4 BOTTOM SIDE 1 OZ Figure 5 Evaluation Board Layout 4 Layer www onsemi com 2 NB7V52MMNGEVB Top View TEWPE AZ 85242 US 0 001 438 1112 A FAK HT 1 800 437 8833 P N IM00AB2C21B35 REV C s Bottom View Figure 6 Evaluation Board Layout Evaluation Board Assembly Instructions The QFN 16 evaluation board 1s designed for characterizing devices in a 50 Q laboratory environment using high bandwidth eguipment Each signal trace on the board has a via at th
8. ntial or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITE
9. req ci Thy 4 9555 06 Hz Ampl C1 404 2969mMY 5 Ampi C2 A Dty CIA AF 15479 389 EdEdrnv Dty 2 Freq C2 A i 57 23231 c a KI E 2 225 Om ua 5 8 T 0000p TEE 160 E 454 PM 6 18 2015 Figure 14 Typical Q amp Q at Fin 10 GHz Vec 1 8 V 25 C www onsemi com 9 NB7V52MMNGEVB BILL OF MATERIALS Table 5 NB7V52MMNGEVB BILL OF MATERIALS SMA Connector 14 SMA Connector Side Rosenberger 32K243 40ME3 www rosenberger com Launch Gold Plated Surface Mount SMT Miniature Test Point Keystone 5015 www keyelco com Test Points ON Semiconductor and the are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special conseque
10. y influenced by imperfect alignment and soldering of the SMA connector Validating the Assembled Board After assembling the evaluation board it Is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process Time Domain Reflectometry TDR is another highly recommended validation test www onsemi com 3 NB7V52MMNGEVB Table 1 NB7V52M EVALUATION BOARD CONFIGURATION ma Tele eo Telo le re o lo ee C CH u e NOTE Exposed Pad DUTGND Exopsed Pad should be tied to VEE DUTGND Install 0 1 uF Decoupling Capacitors Bottom View Install 0 1 uF Decoupling Top View Capacitors Figure 7 Power Supply Configuration for NB7V52MMNGEVB www onsemi com 4 NB7V52MMNGEVB QUICK START LAB SET UP USER S GUIDE Equipment Required 1 DC Power Supply 2 Generator 3 Oscilloscope 4 DC Power Supply Connectors 5 50 62 SMA Connectors for I O s Block Diagram Signal Generator Power Supply Oscilloscope CH1 CH2 CH3 CH4 Q NB7V52M Q i Figure 8 NB7V52MMNGEVB Test Block Diagram Test and Measurement Setup Procedures 1 Connect VCC SMAGND and Vgg DUTGND of the NB7V52M to a DC power supply See Table 2 for appropriate levels 2 Connect output of generator to CLK amp CLK with 50 92 connectors to DUT See NB7V52M data sheet for appropriate input levels 3 Connect output of generator to D amp D with 50 Q connectors to DUT See NB7V52M data sheet for
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