Rev. 1.1 manual - Paul Scherrer Institut
Contents
1. 5 R7 R3 BN 8 8 Lise 5 g E c12 c6 WAM HH Cuors cuors 23 e c la 3 3 C Ga wo 3 5 3 C 86 86 e siz 38 38 a 25 48 35 2g wleb o eb 4 B 19 io 3E 7 AL M lt T 12 5n 8 78 alg 4 oR ols 85 8 lt 55 ao ww g UND g 28 x iani 5 5 R8 1 4 vio 2 24 3 Ja 5lela 8 z z R gt f z m 5 29 8 gt gt 16 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual T v L 2 3 zm gt 9 4 gt gt 4 8 1 i c22 100n P 1 4 9 9 A D e o N54 N5 M N64 o 2 O 1 18 2 4 9 S d G de om 3 4 E M 2 1 3 8 N 4 i tou g 4 teen 15 79 A c21 3 Em lt sl SMITH c 5 a Qv amp 28 5 5 gs 0 23 92. These vias should be solder filled or plugged The maximum power dissipation of the DRS4 chip is not critical 350 mW but an improved thermal stability helps the performance of any analog chip To maximize the coverage and adhesion between the DRS4 and the PCB the copper plane could be partitioned into several uniform sections providing several tie points during the reflow process 3 2 Analog Input If non differential signals should be digitized with the DRS4 chip they must be converted into differential signals for the DRS4 inputs The simplest solution is to connect the IN inputs to AGND and to connect the signals directly to the IN inputs This method has however the disadvantage that the crosstalk and noise immunity of the DRS4 chip are worsened The evaluation board uses passive transformers ADT1 1WT from Mini Circuits for this purpose While this is a good solution to reduce the power consumption of the board such that it can be powered from the USB power 500 mA 5V it has the disadvantage that it reduces the analog bandwidth of the system to about 200 MHz 3 dB The reason for this is the dynamic capacitive load of the DRS4 inputs which must be driven by the signal source Since the input impedance of the DRS4 becomes very small at high frequencies the signal height drops if only driven passively Better performance is achieved with active differential drivers Tests have been made with the THS4513 from Texas Instruments g
3. USB Je a 1818 15 1818181 51818 3188 8 88 88 5 4 424 1 N gt 55 5 OJ39 8 om ig C 0 2410 s gt 9 233v Bs d PAS 8 3ND 5 Y sel 35400 0144 2 as 510 c WCCO n 0 8 1 Ho 8 9 2 4 918 a OR eua gt 4 gt 999999 mu 26 po 1 aor x PBO FDd 25 Gx 2710 y 2 49 RESETE PB1 FD128 ay as J 35 po d si PB2 FD2 27 2 i 30 PND AKEUP m 3 5 G PBA FD4 2 m 32 0 5 4 LKOUT 0 32 224 0 PB6 FDI 34 0 EM 0 PB7 FD 22 3s FUGA H7 TLO FLAGA PDO FDi 35 po nace 148 37 FLAGB 0 5 2 Be ER E FLAGC PD2 FD1 8 99999 Z masc ppsi rFD1139 FoI 8 8 e RR tubus 40 Paasto Q5 5 013 7 JP2 Serial 2 ER DE ko PAT i 42 PAINTI PD6 FD14 3 1014 2448128 SN 024 518 420 2442 PA2 sLoE PD7 FD1 LI ia WP master mm AS WU2 mede mme me is 1 44 2 P 8 48 8 124 44 lal E FFOADRT 45 PAS FIFOADR1 scH 8 47 A6 PKTEND 5 34
4. root user can directly access USB devices Some systems can be configured to allow non root access via the udev system but the exact instructions vary from distribution to distribution and can therefore not be given here usr local drs 1 0 drscl DRS command line tool Revision 12949 Type help for a list of available commands Found mezz board 0 on USB serial 2006 firmware revision 10901 B0 same commands as in the Windows version can now be entered such as the info command B0 info Mezz Board index 0 DRS type DRS4 Board type Serial number 2006 Firmware revision 10901 Page 12 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Temperature 30 8 Status reg 00000002 PLL locked Control reg 00000000 DMODE single shot Frequency 0 000 GHz If this works the oscilloscope application drsosc can be started It will open a X window and show exactly the same functionality as its Windows counterpart Y Shell Konsole Session Edit View Bookmarks Settings Help drs 1 0 drsosc v Trigger Stop Single Force Trigger Normal z Auto Horizontal 4 100 ns div n 2 4 IE il Shell Scale Scale Scale Scale rzy Cursor Snap to
5. J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual DRS4 Evaluation Board User s Manual Board Revision 1 1 as of Dec 2008 Last revised Dec 15 08 Stefan Ritt Paul Scherrer Institute CH 5232 Villigen PSI Switzerland Email stefan ritt 9 psi ch Phone 41 56 310 3728 Please check for possible updates of this manual under http drs web psi ch datasheets PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Revision History Date Modification 12 Dec 08 Initial Revision 15 Dec 08 Added firmware register mapping Page 2 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Table of Contents Revision E m 2 PAB Ie Ol Contents EE 3 Te Introduction ee R ASES 4 1 1 Board d sctiptoN 4 1225 Firmware 5 scis do at 7 2 12 Windows 7 2 2 Ane 11 Development aus diio a eA caged 14 3 1 Power SUDD S 14 2 2 Analog noti P 15 3 3 Control Volta cT 15 3 4 OE Siu 15 4 DRS4Evaluation Board Schemati6s 5 eere doe tone 16 Please check for possible updates of this manual under http drs web psi ch datashee
6. Status reg 46666668 Domino wave running PLL locked Control reg 68 E6661 DMODE circular TRANSP_MODE enabled Hardwar trigger enabled Readout from stop Frequency 9 999 GHz The second application is an program which connects to the DRS4 board and works pretty much like a normal oscilloscope You can select the trigger mode trigger level and trigger source On Rev 1 1 of the DRS4 evaluation board only CHI can be selected as trigger source You enable a channel by clicking on the number 1 to 4 There are two cursors and a few utilities You can save a waveform in an ASCII format After you opened a file each trigger will write the waveform of the active channel s to that file When you are continuously running the file will grow very quickly x Stop Single 1 gt Force Trigger Normal Auto Horizontal 100 ns div Vertical EGGS Scale Scale Scale Scale JL v Snap to waveforms Utilit Save Print Config Measure About Exit Connected to USB board serial 2009 Firmware revision 10901 The picture above shows an un calibrated evaluation board which shows a noise level of about 7 mV RMS Future version of the firmware and drivers will contain calibration routines which bring down the noise by more than one order of magnitude Page 10 of 21 J
7. 5 5 ADC DAC 2 5V AVDD DRS4 analog 2 5V DVDD DRS4 FPGA digital 1 2V FPGA INT FP2 bu FIDUCIAL_ POINT DRS4 Evaluation Board 1 Paul Scherrer Institut Department TEM Lab for Electronics 1414 5232 Villigen PSI Rev POWER 14 Date July 2008 Drawn by HU14 RS14 Filename DRS4 USB BOX sch Sheet 6 of 6 Please check for possible updates of this manual under http drs web psi ch datasheets
8. NIS I EXE gt r3 gt m Please check for possible updates of this manual under http drs web psi ch datasheets v 3 gni FADC 8181 14 2 ADC 3 26 Bs sl s s CAP 1206 8 8 8 Fr LJ 5 5 id mm 33 8888 8131513 3 R 8 REST al 8 oes a ae 8 2 5555 5 0 J i D R17 D 22 D ud 2 T D 8 8 o amp R19 Z 6 ocam 3 He d d 3 14 5ST s ADCCLK g 47 44 2 ADCCUK m EEPROM Temp Sensor 54 PAUL SCHERRER INSTITUT 16 bit DAC rd 42 Vref 015 temp CS vec SQ Hold WP SCKL S 3 NN vour vss SI 25LC1024SM 2 T 8 LTC2600 N ADS 1 1 DRS4 Evaluation Board 1 Scherer 1 ADC DAC EEPROM 1 1 Dote July 2008 Drawn by HU14 RS14 Filename 0854 USB Sheet 3 of 6 0854 Evaluation Board User s Manual n Page 18 of 21 J PAUL SCHER
9. calib sig for DRS chips 0 0x02 21 transp mode 1 DRS inputs to outputs transparent mode 0 0x02 22 enable trigger write 1 to enable hardware trigger 0 0x02 23 readout mode O start from first bin 1 start from domino stop 0 0x02 24 neg trigger 1 trigger on high to low transition 0 0x02 25 acalib write 1 to enable amplitude calibration 0 0x02 27 dactive 0 5 domino wave during readout 1 keep it running 0 0x02 28 standby 1 put chip in standby mode 1 0 04 31 16 DACO Set DAC 0 2A ROFS 1 0x06 15 0 DAC1 Set DAC 1 B CMOFS 2 0x08 31 16 DAC2 Set DAC 2 CAL 2 0 0 15 0 Set DAC 3 D CAL 3 0 0 31 16 DAC4 Set DAC 4 BIAS 3 OxOE 15 0 DAC5 Set DAC 5 TLEVEL 4 Ox10 31 16 DAC6 Set DAC 6 2G O OFS 4 0 12 15 0 DAC7 Set DAC 7 5 0x14 31 24 configuration Bito DMODE Bit1 Bit2 WSRLOOP 5 0 14 23 16 channel config 121x8k 0x1122x4k 0x3324x2k 0xFF28x1k 5 0x16 7 4 first chn first channel address to read out 0 9 5 0x16 3 0 last chn last channel address to read out 1 9 6 Ox18 31 16 trigger delay trigger delay in ticks of roughly 0 56 ns 6 15 0 sampling freq sampling frequency in ticks 1024 fsamp 0 120 2 While the mapping of the status registers 1s like this Comment 31 16 OxCODE Magic number for DRS board identification board type 5 f
10. usr local ed drs 1 0 usr local drs 1 0 make g g 02 Wall Wuninitialized fno strict aliasing Iinclude DOS LINUX Please check for possible updates of this manual under http drs web psi ch datasheets 49 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual DHAVE LIBUSB c src musbstd c g g 02 Wall Wuninitialized fno strict aliasing Iinclude DOS LINUX DHAVE LIBUSB c src mxml c Now you can connect the DRS4 board to the PC On systems where the lsusb tool is installed one should be able to find the DRS4 evaluation board after connecting it with following command usr local drs 1 0 sbin lsusb d 04b4 1175 v Bus 005 Device 005 ID 04b4 1175 Cypress Semiconductor Corp Device Descriptor bLength 18 bDescriptorType 1 bcdUSB 2 00 bDeviceClass Defined at Interface level bDeviceSubClass 0 bDeviceProtocol 1 bMaxPacketSize0 64 idVendor 0x04b4 Cypress Semiconductor Corp idProduct 0x1175 0 01 iManufacturer T Ritt PSI iProduct 2 0854 Evaluation Board iSerial 3 bNumConfigurations Configuration Descriptor bLength 9 bDescriptorType 2 wlotalLength 46 bNumInterfaces 1 bConfigurationValue al iConfiguration 0 bmAttributes 0x80 MaxPower 500mA If the board is correctly recognized one can access it with the command line program Under most Linux distributions however only the
11. waveforms Utility Save Print Config Measure About Exit Connected to USB board serial 2006 firmware revision 10901 2 B Shell Konsole 17 30 Us n e amp 5 3 4 DRS Oscilloscope s 2008 12 11 Please check for possible updates of this manual under http drs web psi ch datasheets J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 3 Development Hints The idea behind the evaluation board is to make first steps in using the DRS4 chip but then develop your own custom electronics around the chip The first thing to do there is to study carefully the DRS4 data sheet which can be obtained from http drs web psi ch datasheets Then have a look at the DRS4 Evaluation Board Reference Design which schematics is supplied at the end of this document When you start to design your own electronics there are however some important points which are not necessarily obvious from the data sheet or from the reference design These points together with some design tips are explained in this section 3 1 Power Supply As with any analog design the quality of the power supply is very important since it has an influence of the noise level measured by the DRS4 chip Low noise linear regulators together with the usual decoupling capacitors are recommended for all power supplies The analog power supply AVpp powers only the domino circuit of the DRS4 ch
12. 5 2 PAT 1A7 FLAGD SLCS ar ws ax far X opLug 15 aw io S RoYe sL RD pminug 18 8 8 sw 125 DY1 SLWR 12 20 11 726 4 XTALOU 21 RESERVED 15 E XN JTAG FPGA Platform Flash 55 222222 5 8 24MHz an 49399 8 5 ue 194 55 95 55 TDI 8 oof 8 TCK B GND GNO GNO IGND TMS 2 TS Vref DONE 025 020 Sis Ies B m DRS4 Evaluation Board 1 3 Scherer m 0 USB FPGA 1 1 5232 Villigen PSI 90 Date July 2008 Drawn by HU14 RS14 Filename 0854 USB Sheet 5 of 6 5 Page 20 of 21 qe 27 1 3 3 Qo PAUL SCHERRER INSTITUT IND 1812 REG1117 3 5 5 5 5 022 1210 28 1 3 3V Ors DRS4 Evaluation Board User s Manual 675 CAP 0805 8 1 2985 3 3 2 5 023 livin vour NI 4 N OFF BY 2 5 7a LP2985 2 5 Livin VOUT ND N OFF BYPB 4 1 CAP 10m 79 8 30 1 2 5 D 2 5V_DRS_A Quo 1208 REG1117 2 5 1 2 U25 CAP 0805 1 1 2 31 1 2 ed LiNo REG1117 1 2 8 CAP 1208 R31 FIDUCIAL_ POINT 3 3V CPU FPGA ADC digital
13. PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual For test purposes an internal 240 MHz referenc clock signal can be connected to channel 4 via the Config menu f E DRS Oscilloscope Trigger Run Single 12 Force Trigger ONormal wn Voltage Calibration Volageon 0 Timing Calibration waveforms Connect reference clock to channel 4 5i Print display Display Date Time j Measure Display raw waveforms 100 mv div Connected to USB board serial 2009 Firmware revision 10901 This application will be constantly updated so please check for updates regularly on the DRS web site 2 2 Linux The drivers and applications are distributed for Linux in source code and must be compiled on each system First untar the tar ball usr local tar xzvf drs 1 0 tar gz 1 0 rs 1 0 doc rs 1 0 doc DRS4_rev06 pdf 1 0 doc manual pdf rs 1 0 include rs 1 0 include ConfigDialog h rs 1 0 include DOFrame h rs 1 0 include DOScreen h R n eee eee aS 1 Then change the directory and do a make Note that to compile the oscilloscope application it is necessary to have the wxWidgets package version 2 8 9 or later installed You can obtain this package in source form from http www wxwidgets org downloads If this package is present you can change to the drs directory and issue a make
14. RER INSTITUT DRS4 Evaluation Board User s Manual is A gt gt as gt J BR Rui m Eie 1 34 OJ6 H U7 8 O24 pigs 0 c c 7025 j w t 1 0026 s t 10027 10012 10028 s ND ND OJ29 1 1 14 1 OU30 70 15 OU31 Gis 70 16 117 10 018 71 t 10 19 1020 7021 10022 1023 2 2 E EIN us als S 28 Jg 5 S 4 UJ gt 8 o 92 el m EN 25 916 5 2 25 Please check for possible updates of this manual under http drs web psi ch datasheets PAUL SCHERRER INSTITUT 0854 Evaluation Board User s Manual v EC U16 VBUS 4 0 5
15. asiest way to generate this phase shift is to use the digital clock managers DCM in the FPGA as it is done on the evaluation board Rev 1 1 Since the DCMs have however an inherent phase jitter of 150ps this introduces some noise in form of a baseline variation when sampling a DC signal in the order of up to a few mV If this becomes a problem it is recommended to generate the phase shift between these two clocks with a low jitter delay circuit Please check for possible updates of this manual under http drs web psi ch datasheets DRS4 Evaluation Board User s Manual PAUL SCHERRER INSTITUT 4 DRSA Evaluation Board Schematics 9 25 MO o 5 Ils gt ES R5 R1 2 je 4 D E 8 w teen cH AAAF c5 4 al on g co 8 o ES o cuors gt 9 D R6 2 Fe 4 H H H E QS 2 en R9 Geje ol ES g 3 N sd gt y Ld y o 5 5 E z lt P U o L L wo es Te
16. hus making it easy to port it to other FPGA devices such as Altera or Lattice Only a few Xilinx basic components such as clock managers and I O blocks have been instantiated and must be adapted when another FPGA manufacturer than Xilinx is chosen The FPGA source code is contained in several files with following contents src drs4_evall vhd Top level entity Routing of clock signals global reset signal LEDs and LEMO input src drs4_evall_app vhd Main file containing state machines for DRS4 readout serial interface to DAC EEPROM and temperature sensor trigger logic and reference clock generation src usb_dpram vhd Instantiates block ram for waveform storage src usb racc vhd Interface to CY2C68013A microcontroller in slave FIFO mode Implements a set of status and control registers through which the main application can be controlled src usr clocks vhd Generates 66 MHz 132 264 MHz and a phase shifted 66 clock out of the 33 MHz quartz input frequency via the Xilinx Digital Clock Managers DCM ucf drs4 evall ucf Constraint file Assigns package pins and defines clock constraints 3s400 drs4 evall ise Xilinx ISE 9 21 project file 3s400 drs4 evall bit Compiled firmware image directly for Spartan 35400 FPGA 3s400 drs4 evall mcs Compiled firmware image for FPGA EEPROM XCF02S 3s400 drs4 evall ipf Xilinx Impact project file to program FPGA via download cable The fi
17. inputs between the input connectors and a reference voltage generated by the on board 16 bit DAC for calibration purposes The 54 is read out by a 14 bit ADC AD9245 from Analog Devices and a FPGA Xilinx Spartan 3 The USB connection is implemented with a micro controller Cypress CY2C68013A The high speed modus of the USB 2 0 bus allows for data transfer rates of more than 20 MB sec ces TSCS i N T deve 1 M x i zu TUTTI 5 it mit LI Figure 1 Picture of the DRS4 Evaluation Board with different components Page 4 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual For trigger purposes a 50 Ohm terminated TTL compatible input is implemented Lemo connector A on board discriminator with programmable level allows for self triggering on any of the four input channels An 1 MBit EEPROM 25LC1025 from Microchip is used to store the board serial number and calibration information Two 14 pin headers carry all important logical signals which allow easy debugging with a logic analyzer or oscilloscope A JTAG adapter can be used to update the FPGA firmware through a Xilinx Platform Cable Adapter 1 2 Firmware Description Both the Windows and the Linux distribution contain a subdirectory firmware which contains the FPGA and Microcontroller firmware for the DRS4 Evaluation Board The FPGA firmware is written in pure VHDL t
18. ip and directly influences the jitter of the sampling frequency Long term variations in this power supply seconds are regulated by the on chip PLL but high frequency noise in the MHz region leads directly to an increase of the PLL jitter Therefore the evaluation board contains two separate 2 5V linear regulators for the DRS4 chip one for the AVpp power and one for the DVpp power Although the DVpp power is called digital power it powers also the analog output buffers of the DRS4 chip and needs the same good quality than the AVpp power in order to minimize the noise of the board The DRS4 chip also contains two grounds and DGND They can be either routed separately on the board and be connected at the power source or they can be directly connected to an overall dedicated ground plane of the PCB Tests have been shown that the latter choice gives slightly less noise The bottom of the QFN76 package of the DRS4 has an exposed paddle connected to the internal DGND It is recommended that this paddle is matched by a PCB pad of similar size connected to analog ground to achieve the best electrical and thermal performance of the DRS4 The copper plane should have several vias to achieve a good heat dissipation to flow through the PCB as shown in Figure 2 1 EH ii 4 Figure 2 PCB pad under the DRS4 chip Page 14 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual
19. iving a bandwidth of 450 MHz and the ADA4937 from Analog Devices giving 700 MHz A small bypass capacitor 1pF in the feedback loop of the buffer adds a high frequency pole which shows up as a peak in the response function but then pushes the bandwidth to 750 MHz The peaking can be reduced by adding a series resistor of a few Ohm between the buffer output and the DRS4 input The usual design rules like proper termination and matched impedance PCB traces apply as in any high frequency analog design 3 3 Control Voltages The DRS4 chip requires certain control voltages ROFS O OFS and BIAS The latter two are generated internally with some default voltage but can be overwritten by an external low impedance source It is recommended to connect these lines to an external 16 bit DAC so that the DRS4 input range can be fine tuned on board by board basis to compensate for chip variations The ROFS signal should be driven by a high speed low noise buffer If this signal would be directly connected to the DAC output the signal height would change slightly during the chip readout and the measurement would show a varying baseline level 3 4 ADC Clock There is a very strict relation between the DRS4 output shift register clock SRCLK and the ADC clock see DRS4 data sheet WAVEFORM READOUT In order to reduce the noise due to aperture jitter the phase shift between these two clocks must be fixed and contain very small jitter 10ps The e
20. or DRS4 USB Evaluation Board 1 1 drs type 4 for DRS4 0 0 0 0 04 0 0 2 i 31 16 temperature 0 0625 deg C units 31 16 Serial number CMC board firmware version SVN revision 0 0 0 0 2 2 2 X X X X X X X Page 6 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual All registers are implemented as 32 bit registers so they can be mapped easily into some VME address space for example if one decides to build a VME board containing the DRS4 2 Installation 2 1 Windows XP Under MS Windows it is important to install the necessary driver before connection the DRS4 Evaluation Board with the PC The current distribution can be downloaded from http drs web psi ch download The Windows version contains a single program drs xx exe where xx is the version which can be executed to install the driver applications documentation and source code Executing this file starts the installer DRS Setup Welcome to the DRS Setup Wizard This wizard will quide you through the installation of DRS It is recommended that you close all other applications before starting Setup This will make it possible to update relevant system files without having to reboot your computer Click Next to continue DRS Setup Choose Components Choose which Features of DRS you want to install This will install the DRS software on your computer Select which optional things yo
21. rmware for the USB microcontroller from Cypress is written in C and must be compiled with the Keil 8051 C compiler It contains the standard include and library files from the Cypress EZ USB development kit plus some DRS specific files CY7C68013A drs_eval c Main micro controller firmware file CY7C68013A dscr a51 USB descriptor tables CY7C68013A drs eval hex Compiled firmware file Intel HEX format Please check for possible updates of this manual under http drs web psi ch datasheets ED PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual CY7C68013A drs_evall iic Compiled firmware file For Cypress EZ USB Console download CY7C68014A kit Remaining files are standard files from EZ USB development The FPGA firmware implements a set of control and status registers through which the DRS4 can be controlled and read out The mapping of the control registers is as follows Ofs Bit Name Comment 0 0x00 0 start trig write a 1 to start the domino wave 0 0x00 1 reinit trig write a 1 to stop amp reset the DRS chip 0 0x00 2 soft trig write a 1 to stop the DRS chip amp read the data to RAM 0 0x00 3 flash trig Flash contents of RAM into EEPROM 0 0x02 18 led 1 O blinks once at beginning of DRS chip readout 0 0x02 19 tcal en switch on 1 off 0 264 MHz
22. talling the software for 0854 evaluation board Click Finish to close the wizard And a new group in your Start Menu ORS Oscilloscope Command Line Interface 7 0854 Datasheet Evaluation Board Manual AllPrograms fig Uninstall DRS Software A Log Off Shut Down 12 start Clicking DRS Command Line Interface will start a simple application which connects to the 54 Evaluation Board If it finds the board it displays the board serial number and firmware revision as on the following screen shot DRS Command Line Interface mif x DRS command line tool Revision 12947 Type help for list of available commands Found mezz board on USB serial 2009 firmware revision 10901 Ba Now you are ready to issue your first command info which shows some more information like the current board temperature The temperature sensor is on the bottom side just below the DRS4 chip If you keep issuing info commands and touch that sensor with your finger you should see the temperature increase Please check for possible updates of this manual under http drs web psi ch datasheets J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual DRS command line tool Revision 12947 for a list of available commands board on USB serial 2009 firmware revision 10901 DRS4 5 Serial number 2009 Firmware revision 16961 38 4 C
23. ts JJ PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 1 Introduction The DRS4 chip which has been designed at the Paul Scherrer Institute Switzerland by Stefan Ritt and Roberto Dinapoli is a Switched Capacitor Array SCA capable of digitizing eight channels at sampling speeds up to 6 GSPS This chip is available through the PSI technology transfer program for other institutes and organizations In order to simplify the design process to integrate the DRS4 chip into custom electronics an evaluation board has been designed which demonstrates the basic operation of the chip It has SMA connectors for four input channels CH1 to CH4 an USB 2 0 connector and a LEMO trigger input Figure 1 The board is powered through the USB port and contains an on board trigger logic It comes with MS Windows and Linux drivers and two application programs It is basically equivalent to a four channel 5 GSPS digital oscilloscope This manual describes the software installation the usage of the application programs and gives hints for developers seeking to build new electronics around the DRS4 chip 1 1 Board description Since the DRS4 chip has differential inputs the board uses four transformers ADT1 1WT from Mini Circuits to converted the 50 Ohm terminated single ended inputs into differential signals The transformers are followed by analog switches ADG936 form Analog Devices These switches allow the multiplexing of the DRS4
24. u want installed Select components to install DRS software required ise it pm v Start Menu Shortcuts ESSI DEOR DRS source code see its des Space required 2 8MB Please check for possible updates of this manual under http drs web psi ch datasheets J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Then you can select the installation directory DRS Setup Choose Install Location Choose the folder in which to install DRS Choose a directory to install in to Destination Folder Space required 2 8MB Space available 148 3GB Installation Complete Setup was completed successfully Completed Show details DRS Setup Setup has completed You can now connect the DRS4 evaluation board Welcome to the Found New Hardware Wizard This wizard helps you install software for 0854 evaluation board If your hardware came with an installation CD QP or floppy disk insert it now What do you want the wizard to do O Install from a list or specific location Advanced Click Next to continue Where you can click Install the software automatically and then click Next Page 8 of 21 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual After successful installation of the driver you will see the following window Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished ins
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