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RX220 Group Renesas Peripheral Driver Library User`s Manual

1. Program example RO1US0059EG0111 Aug 01 2014 Rev 1 11 PDL_INTC_NMI NMI interrupt pin data2 The status flags shall be stored in the following format For an IRQ pin b7 b4 b3 b2 bi bO Detection condition Current level Status 00 Low level 0 01 Falling edge 0 Low 0 Not detected 10 Rising edge 1 High 1 Detected 11 Both edges For the NMI interrupt b7 b6 b5 b4 b3 b2 b1 bO Other interrupt request NMI pin Underflow Oscillation Current Detection HD2 D IWDT stop level condition Request status 0 Not detected 0 Low 0 Falling 0 Not detected 1 Detected 1 High 1 Rising 1 Detected Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control Reference R_INTC_ControlExtInterrupt Remarks e The MPC registers are used to determine which pin is used for IRQn e If this function is called from within a callback function the input detection status will be 0 Clear the NMI status flags using R_INTC_ControlExtinterrupt RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t irq_status Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL_INTC_IRQ5 amp irg_status RX220 Group The INTC Read Write and Modify functions use one of the following register defi
2. Select the pins for TMRI3 Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateChannel R_ TMR_CreateUnit RO1USOO59EG0111 Rev 1 11 REN ESAS Page 184 of 429 Aug 01 2014 RX220 Group 4 Library Reference Remarks e Before calling any R_TMR_Create function call this function to configure the relevant pins e Call this function multiple times if more than one channel is to be configured e Pins which are not used for the TMR functions may be omitted e The configurations are based on the 100 Pin package device Some pin options are not available on smaller device packages Please refer to the Multifunction Pin Controller MPC section in the RX220 Hardware Manual for details of pin selection Program example include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure the applicable TMR pins R_TMR_Set 0 PDL_TMR_TMRO_TMOO_PB3 PDL_TMR_TMRO_TMCIO_PB1 PDL_TMR_TMRO_TMRIO_PA4 R01US0059EG0111 Rev 1 11 Page 185 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_TMR _CreateChannel Synopsis Configure a timer TMR channel Prototype bool R_TMR_CreateChannel uint8_t data1 Channel selection uint32_t data2 Configurati
3. PDL_INTC_VECTOR_OVIO PDL_INTC_VECTOR_TGIW5 channel 5 Compare match or Input capture W PDL_INTC_VECTOR_OEI1 Port Output Input level sampling or output level PDL_INTC_VECTOR_OEI2 Enable comparison detection PDL_INTC_VECTOR_CMIAO 8 bit timer TMR Compare match A PDL_INTC_VECTOR_CMIBO channel 0 Compare match B Overflow PDL_INTC_VECTOR_CMIA1 PDL_INTC_VECTOR_CMIB1 PDL_INTC_VECTOR_OVI1 8 bit timer TMR channel 1 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA2 PDL_INTC_VECTOR_CMIB2 PDL_INTC_VECTOR_OVI2 8 bit timer TMR channel 2 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA3 PDL_INTC_VECTOR_CMIB3 PDL_INTC_VECTOR_OVI3 8 bit timer TMR channel 3 Compare match A Compare match B Overflow PDL_INTC_VECTOR_DMACOI PDL_INTC_VECTOR DMAC1I PDL_INTC_VECTOR DMAC2I PDL_INTC_VECTOR DMACSI Direct memory access controller Transfer complete or Transfer escape end PDL_INTC_VECTOR EXDMACOI PDL_INTC_VECTOR_ERIO PDL_INTC_VECTOR EXDMACII PDL_INTC_VECTOR_RXIO External DMAC Transfer complete or Transfer escape end Error in data received Data received PDL_INTC_VECTOR_TXI9 PDL_INTC_VECTOR_TEI9 PDL_INTC_VECTOR_TXIO SCI channel0 Start of next data transfer PDL_INTC_VECTOR_TEIO End of
4. fecike MHz Equation 12 5 12 8 1 TIN _ 80ns 83 3ns 125ns Srcrxe 92 T MAX_CHANNEL 167 7ms 174 8ms 262ms Srcuxs 22 TMAX_UNIT 42 9s 44 7s 67 1s Socixe include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Output a pulse and wait for 40ms R_TMR_CreateOneShot PDL_TMR_TMRO PDL_TMR_OUTPUT_HIGH 40E 3 PDL_NO_FUNC 0 2tEN ESAS Page 196 of 429 RX220 Group 4 Library Reference 6 R_TMR_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a TMR timer unit bool R_TMR_Destroy uint8_t data Unit selection Shut down a TMR timer unit data The timer unit n where n 0 or 1 Unit 0 comprises channels TMRO and TMR1 Unit 1 comprises channels TMR2 and TMR3 True Timer TMR None e The timer unit is put into the stop state to reduce power consumption RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_TMR_Destroy 0 R01US0059EG0111 Aug 01 2014 Rev 1 11 RENESAS Page 197 of 429 RX220 Group 7 Synopsis Prototype Description Return value
5. Callback done static void Callback void data_sent true Figure 41 Example of SCI in IIC mode using DMAC R01US0059EG0111 Rev 1 11 Page 387 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 11 SCl in IIC Mode using DTC This shows the setting of SCI channel 9 in to IIC mode and then a read from an IIC EEPROM using the DTC PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_dtc h PDL device specific definitions include r_pdl_definitions h static void CallbackRx void SCI IIC Channel define CHANNEL SCI_IIC 9 TIC Slave address of EEPROM define SLAVE _ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 Flag volatile uint8_t data_received Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 void main void Data Buffer volatile uint8_t IIC_Buffer 10 DTC needs to write dummy data to SCI TDR when reading uint8_t IIC_Dummy_value OxFF Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clo
6. PDL_DMAC_TRIGGER_SCI6_RX or PDL_DMAC_TRIGGER_SCI9_RX or PDL_DMAC_ TRIGGER SCI12_RX or Receive buffer full on SCI unit n n 1 5 6 9 or 12 PDL_DMAC_TRIGGER_SCI1_TX or PDL_DMAC_TRIGGER_SCI5_TX or PDL_DMAC_TRIGGER_SCI6_TX or Transmit buffer empty on SCI unit n PDL_DMAC_TRIGGER_SCI9_TX or PDL_DMAC TRIGGER SCI12 TX or n 1 5 6 9 or 12 PDL_DMAC_TRIGGER_IICO_RX or Receive buffer full on 12C channel 0 PDL_DMAC_TRIGGER_lICO_TX Transmit buffer empty on 12C channel 0 data4 The source start address data5 The destination start address data6 The number of transfers to take place For normal mode valid between 0 and 65535 0 free running mode For repeat and block mode valid between 0 and 1023 0 1024 transfers 2tENESAS Page 123 of 429 RX220 Group Description 2 3 4 Library Reference data7 The repeat or block size for each transfer For repeat and block mode valid between 0 and 1023 0 1024 units Ignored in normal mode data8 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected data9 7 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat function is not required for the source address data
7. Enable the IRQ1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ1 PDL_INTC_FALLING PDL_INTC_DMAC_TRIGG PDL_NO_FUNC 0 Enable channel 0 AC _Control 0 PDL_DMAC_ENABL PDL_NO_PTR PDL_NO_PTR PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT Enable and start channel 1 AC _Control 1 PDL _DMAC_ENABLE PDL_DMAC_ START PDL_NO_PTR PDL_NO_PTR PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT Read the status for channel 0 R_DMAC_GetStatus 0 amp StatusValue amp SourceAddr amp DestAddr amp TransferCount amp SizeCount R01US0059EG0111 Rev 1 11 Page 331 of 429 Aug 01 2014 RENESAS RX220 Group while 1 void DMACO_transfer_end_handler void Invert the port pin R_IO_PORT_Modify PDL_IO PORT 1_5 PDL_IO PORT _XOR 1 Stop all channels R_DMAC_Control DL_DMAC_SUSPEND DL_NO_PTR DL_NO_PTR DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA 0 P P P P P P P P Shutdown channel 0 R_DMAC_Destroy 0 di Figure 12 Two examples of DMAC use 5 Usage Examples R01US0059EG0111 Rev 1 11 2tEN ESAS Aug 01 2014 Page 332 of 429 RX220 Group 5 Usage Examples 5 10 Data Transfer Controller 5 10 1 Block transfer mode Figure 13 shows an example of Data Transfer
8. PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_ENABLE TRGnAN on a TCNT underflow Disable or link interrupt PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_ENABLE TRGnBN on a TCNT underflow Disable or link interrupt PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_ENABLE TRGnAN ona TGRA compare match PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN on a TGRA compare match Control ADC triggers Valid for n 4 in complementary PWM mode unless stated otherwise PDL_MTU2_ADC_TRIG_A_DOWN_DISABLE or PDL_MTU2_ADC_TRIG_A_DOWN_ENABLE Disable or enable ADC trigger TRGnAN requests during down count operation PDL_MTU2_ADC_TRIG_B_DOWN_DISABLE or PDL MTU2 ADC_TRIG_B DOWN ENABLE requests during down count operation PDL_MTU2_ADC_TRIG_A_UP_DISABLE or PDL_MTU2_ADC_TRIG_A_UP_ENABLE Disable or enable ADC trigger TRGnBN Disable or enable ADC trigger TRGnAN requests during up count operation This option can be selected in other modes PDL_MTU2_ADC_TRIG_B_UP_DISABLE or PDL_MTU2_ADC_TRIG_B_UP_ENABLE Disable or enable ADC trigger TRGnBN requests during up count operation This option can be selected
9. PDL_MTU2_MODE_PWM_COMP 1 or Complementary PWM mode 1 2 or 3 PDL_MTU2_MODE_PWM_COMP2 or Valid for n 3 Select Normal operation when PDL_MTU2 MODE _PWM_COMP3 configuring channel 4 R01US0059EG0111 Rev 1 11 Page 154 of 429 Aug 01 2014 RENESAS RX220 Group Description 2 9 Synchronous mode Valid for n 0 to 4 4 Library Reference PDL_MTU2_SYNC_DISABLE or PDL_MTU2 SYNC_ENABLE clearing Disable or enable synchronous pre setting DMAC DTC event trigger control Valid for n 0 to 4 unless stated otherwise PDL_MTU2_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRA_DMAC_TRIGGER_ENABLE or PDL_MTU2_TGRA_DTC_TRIGGER_ENABLE TGRA compare match or input capture PDL_MTU2_TGRB_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRB_DTC_TRIGGER_ENABLE TGRB compare match or input capture PDL_MTU2_TGRC_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRC_DTC_TRIGGER ENABLE TGRC compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_TGRD_DTC_TRIGGER_DISABLE or PDL MTU2 TGRD DTC TRIGGER ENABLE TGRD compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_TCIV_DTC_TRIGGER_DISABLE or PDL_MTU2_TCIV_DTC_TRIGGER_ENABLE Counter overflow or underflow Valid for n 4 DTC event trigger control Valid for n 5 PDL_MTU2_TGRU_DTC_TRIGGER_DISABLE or PDL_MTU2 TGRU DTC TRIGGER ENABLE TGRU compare match o
10. Prototype Description Control the Port Output Enable module bool R_POE_Control uint8_t data1 uint16_t data2 uint8_t data3 Control options Control options Control options Change the state of output pins status flags and interrupt control data1 Manual high impedance control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required e MTU channel high impedance control PDL_POE_MTU3_MTU4_HI_Z_ON or Control the high impedance state of the MTU3 and PDL_POE_MTU3 MTU4_HI_Z OFF MTU4 outputs PDL_POE_MTUO_HI_Z ONor Control the high impedance state of the MTUO PDL_POE_MTUO_HI_Z OFF outputs data2 Event flag control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required PDL_POE_FLAG_POEO CLEAR PDL_POE_FLAG_POE1_CLEAR PDL_POE_FLAG_POE2_CLEAR PDL_POE_FLAG_POE3_CLEAR PDL_POE_FLAG_POE8_CLEAR PDL_POE_FLAG_OSTSTF_CLEAR PDL_POE_FLAG_SHORT_3_ 4 CLEAR Select the flags to be cleared data3 Interrupt control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required e High impedance request response
11. Return value Control the SCI channel bool R_SCI_Control uint8_t data1 Channel selection uint16_tdata2 Channel control Control the SCI channel data1 Select channel SCIn where n 1 5 6 9 or 12 data2 Not IIC Mode Control the channel If multiple selections are required use to separate each selection Select the process to be stopped Stop the transmission process PDL_SCI_STOP_TX If a reception process is active the transmit output will not become idle until the reception process has stopped Stop the reception process If a transmission process is active the receive error flags PPE Ses Eps may be set erroneously These can be ignored and will be cleared when a new reception process is started The option PDL_SCI_STOP_TX_AND_RX can be used to select both processes If both processes are selected transmission and reception will stop immediately Generate a Space or Mark signal when idle Only applicable in Async and Async Multi Processor Modes Set the idle output to Space logic 0 RDE id alae ec This can be used to generate a Break condition PDL SCI _OUTPUT_MARK Set the idle output to Mark logic 1 e Error flag control PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS Try to clear the receive error flags e Manual SCK control PDL_SCI_GSM_SCK_STOP or Disable or enable the clock output can be use
12. void main void const uint8_t eeprom_data_array_1 4 0x00 0x01 0x02 0x03 uint8_t data_storage 3 uint32_t status_flags 0 uint1l6_t TxChars Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Select IIC Pins R_IIC_Set PDL_IIC_PIN_SDA_P13 PDL_IIC_PIN_SCL_P12 Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 300 lt lt 16 200 f Send the sub address and 3 bytes to the EEPROM using polling if R_IIC_MasterSend 0 PDL_NO_DATA EEPROM_ADDRESS eprom_data_array_l e 4 PDL_NO_FUNC 0 false Read the channel and transfer status R_IIC_GetStatus 0 r amp status_flags amp TxChars PDL_NO_PTR R01US0059EG0111 Rev 1 11 Page 392 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Review the flags and transmit count to decide on the next action else Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot E 3 DL_NO_FUNC Figure 45 Configure the I C channel and write 3 data bytes to the first locations 2 Reception Continuing from above the memory address pointer of an EEPROM will be modified and then a Repeat Start condi
13. Configure SinglePort 0 as PB_0 Toggle output on event R_ ELC Control PDL_ELC_SINGLE_PORT PDL_ELC_SINGLE_PORT_O PDL_ELC_PIN_PORT_B_O PDL_ELC_PIN_OUTPUT_TOGGLI Enable All Links iC_Control PDL_ELC_ENABL PDL_NO_DATA PDL_NO_DATA PB L will be toggling while 1 Figure 16 Example of Event Link Controller R01US0059EG0111 Rev 1 11 Page 338 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 13 Multi Function Timer Pulse Unit 5 13 1 PWM mode 1 This example shows a usage of Multi Function Timer Pulse Unit with PWM mode 1 Peripheral driver function prototypes include r_pdl_mtu2 h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void main void R_MTU2_Create_structure create_parameters R_MTU2_ControlChannel_structure control_parameter Prepare the main clock settings R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_RESONATOR 20 20 201 201 201 DAAAD A PLEBA BA R Select the Main as the clock source R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_NO_DATA Allow 100us for the main clock to stabilise R_CMT_CreateOneShot 0 PDL_NO_ 100E 6 PDL_NO_FUNC 0 Select the Main as the clock source
14. Description Read the status for an 12C channel bool R_IIC_GetStatus uint8_t data1 Channel selection uint32_t data2 Status flags uint16_t data3 Transmitted bytes uint16_t data4 Received bytes Read the status registers for the selected 1 C channel data1 Select channel ICn where n 0 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b31 b18 b17 b16 Buffer status 0 Transmit Receive 0 Full 0 Empty 1 Empty 1 Full b15 bi4 b13 b12 b11 b10 b9 b8 Bus state Pin level Event detection 0 Not detected 1 detected 0 Idle Stop Start eae f 1 Busy SCL SDA NACK condition condition Arbitration lost Timeout b7 b6 b5 b4 b3 b2 bi bO Transmission Mode Address detection 0 Not detected 1 detected 0 Active 0 Receive Slave 1 Idle 1 Transmit SMBus host Device ID General call 5 1 0 data3 The address for storing the number of bytes that are have been transmitted in the current transfer Specify PDL_NO_PTR if this information is not required data4 The address for storing for the number of bytes that are have been received in the current transfer Specify PDL_NO_PTR if this information is not required Return value True if all parameters are valid otherwise false Category 2C
15. Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Declared in the R_DTC_Create example extern uint32_t dtc_cmt0O_transfer_data void func void uintl6_t StatusValue uint32_t SourceAddr Read the status and current source address for the CMTO transfer E R_DTC_Get Status dtc_cmt0O_transfer_data amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R01US0059EG0111 Rev 1 11 Page 140 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 2 13 1 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 Event Link Controller R_ELC Create Enable the ELC module bool R_ELC_Create void func1 ELC Interrupt1 callback function uint8_t data1 ELC Interrupt Interrupt priority level Enable the ELC module and provide callback function registration func1 The function to be called when an ELC Interrupt ELSR181 occurs Specify PDL_NO_FUNC if not required data1 The interrupt priority level for Interrupt1 If using Interrupti select between 1 lowest priority and 15 highest priority otherwise set to 0 True if all parameters are valid otherwise false Event Link Controller R_ELC_ Control e Call this fu
16. Program example R_IWDT_Set must be used first to configure the timer unless using Initial Setting Memory using R_ MCU_OFS to enable the IWDT from reset RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h void func void Refresh the IWDT R_IWDT_Control PDL_IWDT_REFRESH R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 234 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description Return value Category Reference Remarks Program example R_IWDT_Read Read the watchdog timer status and counter bool R_IWDT_Read uinti6_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 Refresh Error Underflow 0 No refresh error 0 No underflow 1 Refresh error 1 Underflow b13 b0 Down Counter Value True Independent Watchdog Timer None If the Underflow flag is set to 1 it shall be automatically cleared to 0 by this function Ifthe Refresh flag is set to 1 it shall be automatically cleared to 0 by this function RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h uintl6_t Statu
17. Pointer to the variable where the status value shall be stored data1 The status flags shall be stored in the format below b7 b4 b3 b2 b1 bO Overflow Measurement Frequency error Operation 0 0 Not detected 0 No event 0 Not detected 0 Disabled 1 Detected 1 Completed 1 Detected 1 Enabled data2 Where the upper limit value register CAULVR value shall be stored Specify PDL_NO_PTR if it is not required data3 Where the lower limit value register CALLVR value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the counter buffer register CACNTBR value shall be stored Specify PDL_NO_PTR if it is not required True Clock frequency accuracy measurement circuit None e None RPDL definitions include r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t Status_flags R_CAC_GetStatus amp Status_flags PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR 2tENESAS Page 108 of 429 RX220 Group 4 2 8 1 Low Power Consumption R_LPC_Create Synopsis Prototype Description 1 3 R01US0059EG0111 Aug 01 2014 Configure the MCU low power conditions bool R_LPC_Create uint32_t data1 Configuration options 4 Library Reference uint16_t data2 Main oscillator waiting time uint16_t data3 Sub clock oscillat
18. Prototype Description Return value Category Reference Remarks Program example R_CAC_Destroy Stop the clock accuracy circuit bool R_CAC_Desiroy void No parameter is required Disable and shutdown the Clock frequency accuracy measurement circuit True Clock frequency accuracy measurement circuit None e The CAC module is halted to reduce the current consumption RPDL definitions include r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h void func void Disable the CAC R_CAC_Destroy R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 105 of 429 RX220 Group 3 Synopsis Prototype Description 1 2 4 Library Reference R_CAC_Conitrol Control the clock accuracy circuit bool R_CAC_Conirol uint8_t data1 Control options uint32_t data2 Operation changes uint16_t data3 Upper limit value uinti6_tdata4 Lower limit value Modify the Clock frequency accuracy measurement circuit operation data1 Control options All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA Flag clearing control PDL_CAC_CLEAR_FREQUENCY_ERROR PDL_CAC_CLEAR_MEASUREMENT Clear any selected flag PDL_CAC_CLEAR_OVERFLOW e
19. R01US0059EG0111 Rev 1 11 Page 240 of 429 Aug 01 2014 RENESAS RX220 Group Description 3 4 RO1US0059EG0111 Aug 01 2014 Rev 1 11 Options which are available in IIC mode e Noise Filter Clock Select 4 Library Reference PDL_SCI_IIC_FILTER_DISABLED or The noise filter is disabled PDL_SCI_IIC_FILTER_CLOCK_DIV1 or PDL_SCI_IIC_FILTER_CLOCK_DIV2 or The clock signal 1 2 4 or 8 is used with the PDL_SCI_IIC_FILTER_CLOCK_DIV4 or noise filter PDL_SCI_IIC_FILTER_CLOCK_DIV8 e SSDA Delay Output Select Delay on SDA Pin relative to SCL pin PDL_SCI_IIC_DELAY_SDA_0_1 or PDL_SCI_IIC_DELAY_SDA_1_2 or PDL_SCI_IIC_DELAY_SDA_2 3or Sequence continues PDL_SCI_IIC_DELAY_SDA_30_31 PDL_SCI_IIC_DELAY_SDA_29_30 or 0 to 1 cycle delay 1 to 2 cycle delay 2 to 3 cycle delay 29 to 30 cycle delay 30 to 31 cycle delay Options which are available in Smart Card Interface mode Data inversion PDL_SCI_INVERSION_OFF or PDL _SCI_INVERSION ON PDL_SCI_BCP_32 or PDL_SCI_BCP_64 or PDL_SCI_BCP_93 or PDL_SCI_BCP_128 or PDL_SCI_BCP_186 or PDL_SCI_BCP_256 or PDL_SCI_BCP_372 or PDL _SCI_BCP_512 e Base clock pulse cycle count Control data inversion transmission and reception The number of base clock cycles in a 1 bit data transfer period e Parity selection PDL_SCI_PARITY_EVEN or PDL_SCI_PARITY_ODD Select even or odd pa
20. The interrupt handler should clear the detected status error so read until it is clear Read the status registers do R_BSC_Get Status amp status amp bad_address 3 while status 0 while 1 R01US0059EG0111 Rev 1 11 Page 426 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples void BSC_error_handler void rror_detected true Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR PDL _BSC_DISABLE__ Figure 61 Example of BSC R01US0059EG0111 Rev 1 11 Page 427 of 429 Aug 01 2014 RENESAS RX220 Group 6 RX specific notes 6 RX specific notes 6 1 Interrupts and processor mode The RX CPU has two processor modes supervisor and user The API driver functions may be executed by the CPU in either mode However any callback functions which are called by the API interrupt handlers will always be executed by the CPU in supervisor mode This means that the privileged CPU instructions RTFI RTE and WAIT can be executed by the callback function and any function that is called by the callback function The user must 1 Avoid using the RTFI and RTE instructions These instructions are issued by the API interrupt handlers so there should be no need for the user s code to use these instructions 2 Use the wait intrinsic function with caution This instruction is used by some API functions as part of power management
21. data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid otherwise false Compare Match Timer R_CMT_Create e Ifthe flag is read and is set to 1 it shall be automatically cleared to 0 by this function RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uintl6_t Counter void func void Read the channel 2 values R_CMT_Read 2 amp Flags amp Counter R01US0059EG0111 Rev 1 11 REN ESAS Page 214 of 429 Aug 01 2014 RX220 Group 4 2 18 1 Real time Clock R_RTC_Create Synopsis Prototype Description 1 3 R01US0059EG0111 Aug 01 2014 bool R_RTC_Create uint32_t data1 Configuration selection uint32_t data2 Current time uint32_t data3 Current date uint16_t data4 Periodic configuration uint32_t datad Alarm Time uint32_t data6 Alarm Date void func1 Callback function uint8_t data7 Interrupt priority level void func2 Callback function uint8_t data8 Interrupt priority level data1 Configure the clock options To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults if not enabling the alarm 12 or 24 hour mode 4
22. Gets the value of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value will be between 0x00 and OxFF for a port O or 1 for a pin If the I O port specification is incorrect false is returned otherwise true is returned I O port R_IO_PORT_Set e If an invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of port pin P12 R_IO_PORT_Read PDL_IO_PORT_1_2 amp data i Get the value of port 4 R_IO_PORT_Read PDL_IO_PORT_4 amp data i RO1US0059EG0111 Aug 01 2014 Page 82 of 429 RX220 Group 4 Library Reference 5 Synopsis Prototype Description Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 R_lO_PORT_Write Write data to an I O port bool R_IO_PORT_Write uint16_tdata1 Port or port pin selection uint8_t data2 The data to be written to the I O port or port pin Write data to an I O port or I O port pin data1 Use
23. OxAAFF 0x100 0x5600 R01US0059EG0111 Rev 1 11 REN ESAS Page 201 of 429 Aug 01 2014 RX220 Group 4 Library Reference 9 Synopsis Prototype Description R_TMR_ControlPeriodic Control periodic operation bool R_TMR_ConirolPeriodic uint8_t data1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection double data3 The new period or frequency double data4 The new pulse width or duty cycle Modify a periodic timer operation data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n 0 or 1 to be PDL_TMR_TMR3 or configured PDL_TMR_UNITO or PDL_TMR_UNIT 1 data2 Select the options to be modified Use to separate each selection e Period or frequency calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either PDL_TMR_FREQUENCY period and pulse width or frequency and duty cycle Output pin control PDL_TMR_OUTPUT_ENABLE or Enable or disable the periodic output on pin TMOn PDL_TMR_OUTPUT_DISABLE For 16 bit operation the pin shall be TMO2 when n 1 Counter stop start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source data3 The new period or frequency This will be ignored if a timing change is not requested data4 The new pul
24. PDL_LPC_SOFTCUT_HOCO_LVD Power is not supplied to HOCO in software standby mode The voltage detection circuit LVD is stopped and the power consumption reduction function by the power on reset circuit POR is enabled Rev 1 11 RENESAS Page 109 of 429 RX220 Group Description 2 3 RO1US0059EG0111 Aug 01 2014 4 Library Reference data2 Select the main clock oscillator waiting time If no selections are required specify PDL_NO_DATA e Main clock oscillator waiting time PDL_LPC_MAIN_2 or PDL_LPC_MAIN_4 or PDL_LPC_MAIN_8 or PDL_LPC_MAIN_16 or PDL_LPC_MAIN_32 or PDL_LPC_MAIN_256 or PDL_LPC_MAIN_512 or PDL_LPC_MAIN_1024 or Select the oscillation settling time of the main clock oscillator before the CPU resumes after exiting from software standby mode PDL_LPC_MAIN_2048 or i f PDL LPC MAIN 4096 or eU this value the main clock oscillator must be PDL LPC _MAIN_16384 or PDL_LPC_MAIN_ 32768 or PDL_LPC_MAIN_ 65536 or PDL_LPC_MAIN_ 131072 or PDL_LPC_MAIN_ 262144 or PDL_LPC_MAIN 524288 data3 Select the sub clock oscillator waiting times If no selections are required specify PDL_NO_DATA e Sub clock oscillator waiting time PDL_LPC_SUB_2 or PDL_LPC_SUB_4 or PDL_LPC_SUB 8 or PDL_LPC_SUB_16 or PDL_LPC_SUB_32 or PDL_LPC_SUB_64 or PDL_LPC_SUB_512 or PDL_LPC_SUB_1024 or PDL_LPC_SUB_2048 or PDL_LPC_SUB_4096 or PDL_LPC_SUB_16384 or PDL_LPC_SUB_32768 or P
25. func1 The function to be called when an enabled request on pins POEO to POE3 or an output short on MTU channels 3 or 4 occurs Specify PDL_NO_FUNC if not required func2 The function to be called when a request on pin POE8 occurs Specify PDL_NO_FUNC if not required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for all parameters func1 and func2 True if all parameters are valid and exclusive otherwise false Category Port Output Enable Reference R_POE_Set R_POE_GetStatus Remarks e Use R_POE_GetStatus to determine the interrupt cause e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 179 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void POEO_handler void void func void Assign the callback function for pin POEO R_POE_Create PDL_POE_IRQ_HI_Z_0_3_ENABLE POEO_handler PDL_NO_FUNC 0x01 R01US0059EG0111 Rev 1 11 Page 180 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 3 R_POE Conirol Synopsis
26. uint32_t master_rx_data 4 0x00000000 RO1USO059EG0111_ Rev 1 11 Page 415 of 429 Aug 01 2014 RENESAS RX220 Group 0x00000000 0x00000000 0x00000000 Initialise the system clocks NOTE refer to 5 1 Clock Generation Circuit Configure SPI Pin R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL_SPI_MISOA_PAT7 PDL_SPI_MOSIA_PA6 Con R_SPI figure the master SPI channel Create STER_CHANNEL L_SPI_MODE_SPI_MASTI L_SPI_PIN_SSLO L_SPI_PIN_SSL2 L_SPI_FRAME_4 L_NO_DATA L_SPI_PIN_SSL1 L_SPI_PIN_SSL3_1 NO Uo ty UW tg tg AOUUOUYD oD i Prepare the transfer with slave 0 R_SPI_Command MASTER_CHANNI 0 PDL PD PD SPI_CLOC E_O L_SPI_ASSE 0 L_NO_DATA PDL_SPI_LSB_FIRST PDL_SPI_LENGTH_8 i Prepare the transfer with slave 1 R_SPI_Command MASTER_CHANNEL 1 PDL PD PD SPI_CLOC L_SPI_ASSE L_NO_DATA MODE_O _SSL1 PDL_SPI_LSB_FIRST PDL_SPI_LENGTH_9 transfer with slave 2 Prepare the R_SPI_Command MASTER_CHANNEL 2 PDL PD PD SPI_CLOC L_SPI_ASSE L_NO_DATA MODE_O _SSL2 PDL_SPI_LSB_FIRST PDL_SPI_LENGTH_15 i Prepare the transfer with slave 3 R_SPI_Command MASTER_CHANNI 3 PDL PD PD SPI_CLOC EO L_SPI
27. uinti6 _t T 4RC_TGRU_value Register value uinti6 _t T 4RD_TGRV_value Register value uint16_t T 4RE_TGRW_value Register value uint16_t T 4RF_TADCORA value Register value uint16_t TADCORB_ value Register value uint16_t TADCOBRA_value Register value uinti6 _t TADCOBRB_ value Register value void funct Callback function void func2 Callback function void func3 Callback function void func4 Callback function uint8_t interrupt_priority_1 Interrupt priority level void func5 Callback function void func6 Callback function void func7 Callback function void func8 Callback function uint8_t interrupt_priority_2 Interrupt priority level Description 1 9 Set up a 16 bit MTU2 channel data1 The channel number n where n 0 to 5 channel_mode Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold e Operation mode Valid for n 0 to 4 unless stated otherwise PDL MTU2 MODE_NORMAL or Normal operation PDL_MTU2_MODE_PWM1 or Pulse Width Modulation PWM mode 1 Pulse Width Modulation PWM mode 2 PDL_MTU2_MODE_PWM2 or Valid for n 0 1 and 2 PDL_MTU2_MODE_PHASE1 or PDL_MTU2_MODE_PHASE2 or Phase counting mode 1 2 3 or 4 PDL_MTU2_MODE_PHASES or Valid for n 1 and 2 PDL_MTU2 MODE_PHASE4 or PDL_MTU2 MODE PWM_RS or Reset synchronised PWM mode Valid for n 3
28. Program example Shut down the ADC unit bool R_ADC_12_Desiroy uint8_t data ADC unit selection Put the ADC into the Power down state with minimal power consumption data Select the ADC unit to be shut down This must always be 0 True if a valid unit is selected otherwise false 12 bit ADC None e This function includes a 1ms delay to allow the ADC to stop any current scan cycle RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the ADC unit R_ADC_12_Destroy 0 Aug 01 2014 RX220 Group 4 Library Reference 5 Synopsis Prototype Description Return value Category Reference Remarks Program example R_ADC_12_Conirol Start or stop an ADC unit bool R_ADC_12_Control uint8_t data Conversion unit control Controls start stop operation of the specified ADC data To select multiple options at the same time use to separate each value On off control PDL_ADC_12_0 ONor Start a software triggered conversion or re enable the trigger PDL_ADC_12_0_OFF Stop the conversion and disable all triggers Control the CPU during the ADC conversion Stop the CPU when the scan conversion process starts ig hate aes Gd The CPU will re start when any valid inter
29. to separate each selection All settings are optional Specify PDL_NO_DATA if none are required e High impedance request detection PDL_POE_HI_Z REQ _8 ENABLE If a request is detected on pin POE8 place the MTU channel 0 I O pins in the high impedance state POL POE Hl Z REO MTIOCOA Select the MTU channel 0 I O pins that shall be PDL_POE_HI_Z REQ MTIOCOB eg controlled by the high impedance request software PDL POE HIZ Bee Mie control or the oscillation stop detection flag PDL_POE_HI Z REQ MTIOCOD Select the MTIOCOA MTIOCOB MTIOCOC MTIOCOD MTIOC3B MTIOC3D MTIOC4A PDL_POE_HI_Z_ REQ_OSTSTE MTIOC4B MTIOC4C and MTIOC4D pins in high impedance on detection that oscillation has stopped Output short detection If a short is detected place the all the selected MTU ecg die alla ALHLZ channel 3 and 4 pins in the high impedance state PDL_POE_SHORT_MTIOC4BD_A Select the MTU channel I O pin pairs that shall be PDL_POE_SHORT_MTIOC4AC_A_ controlled by the short detection response software PDL_POE SHORT _MTIOC3BD_A_ control or the oscillation stop detection flag Return value True if all parameters are valid and exclusive otherwise false Category Port Output Enable Reference R_POE_GetStatus Remarks e Do not select MTU pins that are not used e Use R_POE_GetStatus to get the oscillation stop detection flag Program
30. void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Select IIC Pins R_IIC_Set PDL_IIC_PIN SDA P13 PDL _IIC_ PIN SCL P12 Select IIC mode at 100kHz R_IIC_Create SLAVE_CHANNEL L_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 TIC_SLAVE_0O_ENABLE_7 AVE_ADDRESS DL_NO_DATA DL_NO_DATA 00E3 D D Start monitor the channel R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_NO_DATA Rx_Buffer RX_BUFFER_SIZE slave_callback 7 The rest is interrupt driven while 1 R_IIC_SlaveMonitor or R_IIC_SlaveSend callback static void slave_callback void uint32_t status_flags 0 R01US0059EG0111 Rev 1 11 Page 403 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples uintl6_t tx_count uintl6_t rx count bool bStartMonitor true Read the status R_IIC_GetStatus SLAVE_CHANNEL status_flags amp tx_count amp rx_count Has the master just completed a write if rx_count 0 StoreData rx_count Start monitoring again bStartMonitor true Has the master just completed a read else if tx_count 0 Increment the current index by the amount the master read data_storage_index tx_count Start monitoring again bStartMonitor
31. PDL IIC_SDA DELAY DIV 1 or PDL_IIC_SDA_DELAY DIV 2 Select the clock source internal reference clock 1 or 2 for the SDA output delay counter 2tENESAS Page 264 of 429 RX220 Group 4 Library Reference Description 2 3 e Noise filter control PDL_IIC_NF_DISABLE or PDL_IIC_NF_1 or PDL_IIC_NF_2 or Select the number of stages in the noise filter PDL_IIC_NF_3or PDL_IIC_NF_4 data3 Detection settings Specify PDL_NO_DATA to use the defaults e NACK Transmission Arbitration Lost Detection control PDL_IIC_NTALD_DISABLE or Disable or enable arbitration to be lost when an ACK is PDL_IIC_NTALD_ENABLE detection during transmission of a NACK in receive mode e Slave Arbitration Lost Detection control PDL_IIC_SALD_DISABLE or Disable or enable arbitration to be lost when a mismatch PDL_IIC_SALD_ENABLE occurs during slave data transmission e Slave address detection control PDL_IIC_SLAVE_0_DISABLE or Disable or enable detection of slave address 0 in PDL_IIC_SLAVE_0 ENABLE _7 or 7 bit or PDL_IIC_SLAVE_0 ENABLE_10 10 bit format PDL_IIC_SLAVE_1_DISABLE or Disable or enable detection of slave address 1 in PDL_IIC_SLAVE_1_ENABLE _7 or 7 bit or PDL_IIC_SLAVE_1_ENABLE_10 10 bit format PDL_IIC_SLAVE_2 DISABLE or Disable or enable detection of slave address 2 in PDL_IIC_SLAVE_2 ENABLE 7 or 7 bit or PDL_IIC_SLAVE_2 ENABLE _ 10 10 bit format PDL
32. PDL_MTU2_A_IC_RISING_EDGE or PDL_MTU2_A_IC_FALLING_EDGE or PDL_MTU2_A_IC_BOTH_EDGES or Input capture at MTIOCnA rising edge Input capture at MTIOCnA falling edge Input capture at MTIOCnA both edges PDL_MTU2_A_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 PDL_MTU2_A_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1 PDL_MTU2_B_OC DISABLED or PDL_MTU2_B_OC LOW or PDL_MTU2_B_OC_ LOW_CM HIGH or PDL_MTU2_B_OC_LOW_CM_INV or PDL_MTU2_B_OC_HIGH_CM_LOW or PDL_MTU2_B_OC_HIGH or PDL_MTU2_B_OC_HIGH_CM_INV or Input capture output compare control for register TGRB MTIOCnB output disabled MTIOCnB output low MTIOCnB initial output low goes high at compare match MTIOCnB initial output low toggles at compare match MTIOCnB initial output high goes low at compare match MTIOCnB output high MTIOCnB initial output high toggles at compare match PDL_MTU2_B_IC_RISING_EDGE or PDL_MTU2_B_IC_FALLING_EDGE or PDL_MTU2_B_IC_BOTH EDGES or Input capture at MTIOCnB rising edge Input capture at MTIOCnB falling edge Input capture at MTIOCnB both edges PDL_MTU2_B_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 PDL_MTU2_B_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1
33. PDL_SCI_PIN_SCI6_RXD6 PBO PDL_SCI_PIN_SCI6_TXD6 PBI PDL_SCI_PIN_SCI6_SCK6 PB3 Set CI_Set SLAVE_CHANNEL PDL_SCI_PIN_SCI9_RXD9 aster Channel 9 pin options PB6 PDL_SCI_PIN_SCI9_TXD9 PB7 PDL_SCI_PIN_SCI9_SCK9 PBS Create Clock master channel for Rx and Tx R_SCI_Create Creat NOTE the expected baud rate MASTER_CHANNEL PDL_SCI_SYNC PDL_SCI_TX_CONN ECT ED PDL_SCI_CLK_INT_OUT PDL_SCI_RX_CONN ECT 19200 1 Slav R_SCI_Create SLAVE_CHANNEL PDL_SCI_SYNC 0x80000000 Channel PDL_SCI_CLK_ 19200 Even though using an external clock the driver needs to know Bit 31 is set to signify not generating baud T7 R01US0059EG0111 Aug 01 2014 Rev 1 11 Page 377 of 429 RX220 Group 5 Usage Examples First setup the slave to send data_sent false R_SCI_Send SLAVE_CHANNEL PDL_NO_DATA Slave DATA_LENGTH SCI_Tx_Callback Setup master to receive Non polling NOTE No clocks pulses will be generated until R_SCI_Send is called data_received false R_SCI_Receive MASTER_CHANNEL PDL_NO_DATA rx_buffer DATA_LENGTH SCI_Rx_Callback PDL_NO_FUNC Dummy send so the Slave Tx and Master Rx will happen R_SCI_Send MASTER_CHANNEL P
34. func1 The function to be called if a frequency error is detected Specify PDL_NO_FUNC if not required data6 The frequency error interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter funct func2 The function to be called when the measurement has ended Specify PDL_NO_FUNC if not required data7 The measurement complete interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 func3 The function to be called if the measurement counter overflows Specify PDL_NO_FUNC if not required data8 The counter overflow interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func3 True if all parameters are valid and exclusive and the selected clocks have been set otherwise false Category Clock frequency accuracy measurement circuit References R_CGC_ Set RO1USO059EG0111 Rev 1 11 REN ESAS Page 103 of 429 Aug 01 2014 RX220 Group Remarks Program example RO1US0059EG0111 Aug 01 2014 modi 4 Library Reference e If the external input CACREF pin is selected the Multifunction Pin Control registers are fied to enable the selected pin e Before using this func
35. include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Enter software standby mode R_LPC_Control PDL _LPC_MODE_SOFTWARE_STANDBY di Rev 1 11 RENESAS Page 114 of 429 RX220 Group 4 Library Reference 3 R_LPC_GetStatus Synopsis Prototype Description Return value Category References Remarks Program example Read the status flags bool R_LPC_GetStatus uint16_t data Data pointer Read the Low power status flags data The status flags shall be stored in the format below b15 b9 b8 Operating Power Control Mode transition flag 0 0 Transition completed 1 During Transition b7 b4 b3 b2 bi bO Event detection flags 0 not detected 1 detected 0 Lvb2 LvD1 LvDo_ Power on reset True LPC R_LPC_Create R_LPC_Control e Ifa flag is set to 1 it shall be automatically cleared to 0 by this function apart from the Power on reset flag which can be cleared only by a hardware reset RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t status_flags Read the low power status flag R_LPC_GetStatus status_flags i R01US0059EG0111 Rev 1 11 REN ESAS Page 115 of 429 Aug 01 2014 RX220 Group
36. A pointer to the data storage location uint32_t data3 A pointer to the data storage location uint32_t data4 A pointer to the data storage location Read the Clock counters registers and status flags in binary count mode data1 The clock status shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 Interrupt requests 0 Carry Periodic Alarm 0 Idle 1 Occurred b3 b2 b1 bO Status 0 Reset Clock 0 Normal operation 0 Stopped 1 Reset in progress 1 Running data2 The current count in 32 bits binary display Specify PDL_NO_PTR if it is not required data3 The alarm count in 32 bits binary display Specify PDL_NO_PTR if it is not required data4 The alarm mask data in 32 bits binary display Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid otherwise false Category Real time clock Reference R_RTC_ReadBinary Remarks e This function is not available in calendar count mode e Call R_RTC_CreateBinary or R_RTC_CreateWarm first before using this function e Ifan interrupt request flag is set to 1 it shall be automatically cleared to 0 by this function e lf the Carry flag is read as 1 the current counts were updated during the read process and should be re read e This function is not required when using 48 pin package RO1US0059EG0111 Page 229 of 429 Aug 01 2014 RX220 Gr
37. include lt stddef h gt include lt string h gt const uint8_t string Hello from Renesas RX220 SCI DMAC r n uint8_t SCI_status void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Set Channel 1 pin options R_SCI_Set 1 PDL_SCI_PIN_SCI1_RXD1_P30 PDL_SCI_PIN_SCI1_TXD1_P26 Set up SCIL Async 8N1 19200 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 19200 1 Configure channel 3 of DMAC to be triggered by SCI1 Tx R_DMAC_Create 3 PDL_DMAC_REPEAT PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIXED PDL _DMAC_SIZI PDL_DMAC_TRIGGER_SCI1_TX string Source const char amp SCI1 TDR Destination 1 uintl6_t strlen char string PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 Enable DMAC AC_Control 3 PDL_DMAC__ PDL_NO PT PDL_NO PT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT R01US0059EG0111 Rev 1 11 Page 373 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Start transmission R_SCI_Send 1 PDL_SCI_DMAC_TRIGGER_ENABLE PDL_NO_PTR PDL_NO_DATA No data as using DMAC PDL_NO_FUNC KK IK KR RR A A A RA A A A A IA A A IA I A I A I A A A I A a A I A
38. 1 IIC_Buffer 2 TIc_Buffer 3 4 5 r IIC_Buffer IIC_Buffer Setup DMAC to write data to IIC Configure channel 3 of DMAC to be triggered by SCI9 Tx R_DMAC_Create 3 PDL_DMAC_REPEAT PDL _DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIXED PDL_DMAC_SIZE_8 PDL_DMAC_IRQ PDL_DMAC_TRIGGER_SCI9_TX IIC_Buffer Source R01US0059EG0111 Rev 1 11 Page 386 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples uint8_t amp SCI9 TDR Dest 1 6 Data length Address in EEPROM 5 Data PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Callback Callback done function 7 Interrupt priority Enable DMAC channel 3 AC_Control 3 PDL_DMAC_ENABI PDL_NO_PTR PDL_NO_PTR PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT Clear flag data_sent false Start IIC Write R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_SCI_TIC_DMAC_TRIGGER_ENABLE SLAVE_ADDRESS PDL_NO_DATA No data length as using DMAC PDL_NO_DATA No buffer as using DMAC PDL_NO_FUNC Wait for write to complete while false data_sent Because using DMAC need to manually send a stop to end the transfer R_SCI_Control CHANNEL_SCI_IIC PDL_SCI_IIC_STOP
39. Description Return value Category Reference Remarks Program example Write data into the CRC calculation register bool R_CRC_Write uint8_t data The data to be used for the calculation Write the data into the data input register data The data to be written into the register True CRC R_CRC_Create e None RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Write FOh into the CRC calculation register R_CRC_Write OxFO i R01US0059EG0111 Rev 1 11 2tEN ESAS Aug 01 2014 4 Library Reference Page 294 of 429 RX220 Group 4 Library Reference 4 R_CRC Read Synopsis Read the CRC calculation result Prototype bool R_CRC_Read uint8_t data1 Control uint1i6_t data2 Data storage location Description Reads and stores the CRC calculation result data1 Control the behaviour of the CRC unit The default setting is shown in bold Specify PDL_NO_DATA to use the default e Result register clearing PDL_CRC_CLEAR_RESULT or PDL_CRC_RETAIN_ RESULT Clear or retain the value in the result register data2 The address of the location where the result shall be stored For the 8 bit polynomial the results are stored in the lower order byte Return value True Category CRC R
40. PDL functions include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h PDL device specific definitions include r_pdl_definitions h void main void volatile uint32_t date time Prepare the LOCO settings R_CGC_Set DL_CGC_CLK_LOCO DL_NO_DATA 25E3 25E3 D 2 2 D pP F Prepare the Sub clock settings R_CGC_Set PDL_CGC_CLK_SUB_CLOCK L_CGC_SUB_CLOCK_CL_STANDARD D D 2768 2768 DL_NO_DATA 2768 PCLKB clock sub clock when sub clock is source clock 2768 DL_CGC_SUB_32768 Generate the 2s delay befor nabling RTC by CGC_Control R_CMT_CreateOneShot 0 PDL_NO_DATA 240 PDL_NO_FUNC 0 Select the HOCO as the clock source R_CGC_Control PDL_CGC_CLK_SUB_CLOC PDL_NO_DATA PDL_CGC_RTC_TO_BE_US If Cold start is detected the RTC clock should be re started R_RTC_Create PDL_NO_DATA 04110710 WED 11 07 10 20140116 20140116 L_NO_DATA L_NO_DATA L_NO_DATA L_NO_FUNC L_NO_DATA L_NO_FUNC x x U Ig t o t g o oO R01US0059EG0111 Rev 1 11 Page 351 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples PDL_NO_DATA while 1 R_RTC_Read PDL_RTC_READ_CURRI PDL_NO_PTR amp time amp date Figure 25 Example of configuration CGC and RTC counting by sub clock
41. PDL_SCI_PIN_SCI6_TXD6_PB1 PDL_SCI_PIN_SCI6_SCK6_PB3 Create SPI master R_SCI_Create 6 PDL_SCI_SYNC PDL_SCI_SPI_MODE PDL_SCI_RX_DISCONNECTED PDL_SCI_CLK_INT_OUT 19200 T Start sending data R_SCI_SPI_Transfer 6 PDL_NO_DATA 5 12345 SCItx PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC Wait for data to be sent while data_sent false Close this channel R_SCI_Destroy 6 static void SCItx void data_sent true Figure 39 Example of SCI in SPI mode R01US0059EG0111 Rev 1 11 Page 383 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 9 SCI in IIC Mode This shows the setting of SCI channel 9 into IIC mode and then a write and read to an IIC EEPROM PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h SCI IIC Channel define CHANNEL _SCI_IIC 9 IIC Slave address of EEPROM define SLAVE_ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 Value to be written to the EEPROM define EEPROM_VALUE OxAA void main void Data Buffer volatile uint8_t IIC_Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R_C
42. PDL_SPI_SSLA2_ PAl1 PDL_SPI_SSLA3_PA2 RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 280 of 429 RX220 Group 4 Library Reference 2 R_SPI_Create Synopsis Configure an SPI channel Prototype bool R_SPI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Data format uint32_t data4 Extended timing control uint32_t data5 Bit rate or register value Description 1 3 Set up the selected SPI channel data1 Select channel SPIn where n 0 only data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold Connection mode PDL_SPI_MODE_SPI_MASTER or PDL_SPI_MODE_SPI_MULTI_MASTER or The required SPI four wire or Clock PDL_SPI_MODE_SPI_SLAVE or synchronous three wire operation PDL_SPI_MODE_SYNC_MASTER or connection type PDL_SPIl_MODE_SYNC_SLAVE e Reception control PDL_SPI_FULL_DUPLEX or PDL_SPI_TRANSMIT_ONLY Enable or disable reception operations e Pin control If output signal SSLx where x 0 1 2 or 3 is used call function R_SPI_Set to select the respective output pin PDL_SPI_PIN_SSLO_LOW or Select active low or active high PDL_SPI_PIN_SSLO_HIGH or for output signal SSLO PDL_SP
43. Remarks Program example bool R_IIC_Set uint8_t data Pin selection Set up the selected I C channel data Configure the IC pins Use to separate each selection e SDApin selection PDL_IIC_PIN_SDA_P13 or PDL_IIC_PIN SDA P17 Select the pin for SDA SCL pin selection PDL_IIC_PIN_SCL_P12 or PDL_IIC_PIN SCL _P16 Select the pin for SCL True if all parameters are valid exclusive and achievable otherwise false C R_IIC_Create e Before calling R_IIC_Create call this function to configure the relevant pins e Some pin options are not available on smaller device packages RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Configure the applicable IIC pins R_IIC_Set PDL_IIC_PIN SDA P13 PDL _IIC PIN _SCL_P12 i R01US0059EG0111 Rev 1 11 REN ESAS Page 263 of 429 Aug 01 2014 RX220 Group 2 Synopsis Prototype Description 1 3 RO1US0059EG0111 Aug 01 2014 Rev 1 11 R_IIC_Create l2 C channel setup bool R_IIC_Create uint8_t data1 uint32_t data2 uint32_t data3 uint16_t data4 uint16_t datad uint16_t data6 uint32_t data7 uint32_t data8 Set up the selected 1 C channel data1 Select channel ICn where n 0 data2 4 Library Reference Channel selection Channel configurati
44. bool R_SCI Send uint8_t data1 Channel selection uint16_t data2 Channel configuration and Target Station ID uint8_t data3 Data start address uinti6_t data4 Data count void func Callback function Transmit data on the specified serial channel data1 Select channel SCIn where n 1 5 6 9 or 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SCI_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_SCI_DTC_TRIGGER_ENABLE transmitted e ID transmission control valid only in Multi processor mode Transmit the upper byte as the ID byte pee eee The valid ID range is 0 to 255 data3 The start address of the data to be sent Specify PDL_NO_PTR for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data4 For sending binary data set this to the number of bytes to be sent The valid range is 1 to 65535 Set this to 0 for transmission of a null terminated character string For the ID cycle in Multi processor mode specify 0 If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Use R_SCI_Control to terminate this o
45. to separate each value If no change is required specify PDL_NO_DATA e Auto Error Adjustment PDL_RTC_ERROR_AUTO_ADJUST_DISABLE or Enable or disable automatic PDL_RTC_ERROR_AUTO_ ADJUST ENABLE error adjustment e Auto Error Adjustment Period PDL_RTC_ERROR_AUTO_ADJUST_PERIOD_ 32S or Select the automatic error PDL_RTC_ERROR_AUTO ADJUST PERIOD 8S adjustment period e Auto Error Adjustment Addition or subtraction selection PDL_RTC_ERROR_ADJUST_PLUS or PDL_RTC_ERROR_ADJUST_MINUS Select if the adjustment value will be added or subtracted from the count Rev 1 11 REN ESAS Page 225 of 429 RX220 Group Description 2 2 Update the Error Adjustment value 4 Library Reference PDL_RTC_ERROR_UPDATE_ERROR_ADJUST_VALUE Select to specify a new error adjustment value Error Adjustment Value Valid Range 0 to 3Fh New automatic error adjustment value ignored if not selected above data6 Configure the clock periodic interrupt Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256 HZ or PDL_RTC_PERIODIC_128 HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32 HZ or PDL_RTC_PERIODIC_16_HZ or PDL_RTC_PERIODIC_8 HZ or PDL_RTC_PERIODIC_4 HZ or PDL_RTC_PERIODIC_2 HZ or PDL_RTC_
46. void func void Write data to register PDIPFS R_MPC_Write PDL_MPC_REG_PD1PFS OxFF R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 90 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description Return value Category References Remarks Program example R_MPC_Modify Modify an MPC register bool R_MPC_Modify uint8_t data1 MPC register selection uint8_t data2 Logical operation uint8_t data3 Modification value Write the value to an MPC register data1 One of the definition values from 4 2 4 data2 e The logical operation to be applied to the register contents PDL_MPC_AND or PDL_MPC_OR or Select between AND amp OR or Exclusive OR PDL_MPC_XOR data3 The value to be used for the modification True if a valid MPC register is specified otherwise false MPC registers None The MPC registers are modified by other driver functions Take care to not overwrite existing settings e Refer to the hardware manual for valid values for each register RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void Set bit 6 in P12PFS to 1 R_MPC_Modify PDL_MPC_REG_P12PFS PDL_MPC_OR 0x40 R01US0059EG0111 Aug 01 2014 Rev
47. 2768 2768 D 2 2 D Pp L_NO_DATA 768 PCLKB clock sub clock when sub clock is source clock 768 L_CGC_SUB_32768 Generate the 2s delay befor nabling RTC by CGC Control R_CMT_CreateOneShot 0 PDL_NO_DATA 2 PDL_NO_FUNC 0 Select RTC to be used R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_CGC_RTC_TO_B If Cold start is detected the RTC clock should be re started R_RTC_CreateBinary PDL_NO_DATA Configuration 0x12345678 Current_count PDL_NO_DATA Periodic PDL_NO_DATA Alarm_count PDL_NO_DATA Alarm_mask PDL_NO_FUNC Alarm handler R01US0059EG0111 Rev 1 11 Page 349 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples L NO_DATA Alarm priority L NO_FUNC Periodic Handler L_NO_DATA Periodic priority while 1 R_RTC_ReadBinary amp flags amp count amp alarm amp r_mask Figure 24 Example of configuration CGC and RTC counting by sub clock Only RTC count source in Binary count mode R01US0059EG0111 Rev 1 11 Page 350 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 3 Configuration CGC and RTC counting by sub clock both RTC count source and System clock in calendar count mode Figure 25 shows an example of sub clock used as both RTC count source and system clock in Calendar count mode
48. 4 Library Reference R_TMR_ControlChannel Write to timer channel registers bool R_TMR_ControlChannel uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 Counter register value uint8_t data4 Compare match A register value uint8_t data5 Compare match B register value Modify a timer channel s operation counter and compare registers data1 The channel number n where n 0 1 2 or 3 data2 The channel settings to be modified If multiple selections are required use to separate each selection Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A_ Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B_ Update the timer compare match B register TCORB Counter stop in response to ELC PDL_TMR_ELC_COUNT_STOP Stop a counter that was started by the ELC data3 The counter value This will be ignored if the register is not selected data4 The compare match A value This will be ignored if the register is not selected data5 The compare match B value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateC
49. Check the status of a DMA channel bool R_DMAC_GetStatus uint8_t data1 uint8_t data2 uint32_t data3 uint32_t data4 uint16_t data5 uint16_t data6 Channel number Status flags pointer Current source address pointer Current destination address pointer Current transfer count pointer Current Repeat or Block size count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 3 data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read 4 Library Reference b7 b5 b4 b3 b2 b1 bO Transfer Escape Transfer End Status Mranster Interrupt End interrupt ESIF interrupt DTIF ACT enang 0 request DTE IR 0 Idle 0 Idle 0 Idle 0 Disabled 1 Generated 1 Generated 1 Operating 1 Enabled data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required data6 Where the current repeat or block size count shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false DMA controller Reference R_DMAC_ Create Remarks Ifthe Int
50. IMPORTANT The SCI module does not know when the DMAC has finished therefore we must tell it using the R_SCI_Control function FER AR AA AR A AA AAA AA A A A A IA I A I A A A I A I A I a ee He ae Wait for the SCI transmission to end do R_SCI_GetStatus 1 amp SCI_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR di While the Transmit status BIT_2 is not reporting idle jwhile SCI_status amp 0x04 0 Stop the SCI R SCI Control 1 PDL_SCI_STOP_TX Send using polling mode R_SCI_Send 1 PDL_NO_DATA Hello from Renesas RX220 SCI Polling r n PDL_NO_DATA PDL_NO_FUNC Figure 34 Example of SCI Asynchronous operation using DMAC R01US0059EG0111 Rev 1 11 Page 374 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 4 Synchronous Transmission and Reception This shows the configuration of SCI channel 6 as the clock master and channel 9 as the slave The master transmits data to the slave The slave receive function call uses interrupts to call a callback function on completion Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h SCI channel selection define MASTER _CHANNEL 6 define SLAVE_CHANNEL 9 Rx complete flag volatile uint8_t data_received Callback function prototype
51. MTU4 TADCORB and MTU4 TCNT PDL_ADC_12_GP_TRIGGER_MTU_TRG4BN or compare match interrupt skipping function 1 MTU4 TADCORA and MTU4 TCNT compare match and MTU4 TADCORB and MTU4 TCNT compare match interrupt skipping function 1 PDL_ADC_12_GP_TRIGGER_ELC Trigger from the ELC PDL_ADC_12_GP_TRIGGER_MTU_TRGOBN or PDL_ADC_12_GP_TRIGGER_MTU_TRGAN or PDL_ADC_12_GP_TRIGGER MTU_TRG4ABN or e DTC DMAC trigger control PDL_ADC_12_GP_DMAC_DTC_TRIGGER_DISABLE or PDL_ADC_12_GP_DMAC_TRIGGER_ENABLE or PDL_ADC_12_GP_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC data5 The data to be used for the sampling state register value calculations for self diagnosis or internal reference voltage depending on the input source parameter of data2 If PDL_ADC_12_ADSSTR_SPECIFY is selected for parameter data2 the value should not be less than 12 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTR uint8_t data6 The data to be used for the disconnecting detection control register value calculations If PDL_ADC_12_ADDISCR_SPECIFY is selected for data2 the value should not be 0 or more than 15 Data use Parameter type The timer period in seconds or double The value to be put in register ADDISCR uint8_t func1 The function to be called when the ADC conversion scan cycle is complete in single scan mo
52. Operation control PDL_CAC_DISABLE Stop the measurement operation PDL_CAC_ENABLE Re start the measurement operation data2 Operation control options All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA Reference signal selection PDL_CAC_REFERENCE_MAIN or Select the main clock oscillator PDL_CAC_REFERENCE_SUB_ CLOCK or sub clock oscillator PDL_CAC_REFERENCE_HOCO or high speed on chip oscillator PDL_CAC_REFERENCE_LOCO or low speed on chip oscillator or PDL_CAC_REFERENCE_IWDTLOCO or IWDT low speed on chip oscillator or PDL_CAC_REFERENCE_CACREF input to pin CACREF as the reference signal Reference signal edge selection PDL_CAC_REFERENCE_ RISING or Select rising edges PDL_CAC_REFERENCE_FALLING or falling edges or PDL_CAC_REFERENCE_BOTH both rising and falling edges to be valid e Reference signal division selection Se ee If an internal clock is used as the reference PDL CAC REFERENCE DIV 1024 or signal divide it by 32 128 1024 or 8192 PDL GAC REFERENCE DIV 8192 Ignored if the CACREF input is selected e Measured clock selection PDL_CAC_MEASURE_MAIN or Select the main clock oscillator PDL_CAC_MEASURE_SUB_CLOCK or sub clock oscillator PDL_CAC_MEASURE_HOCO or high speed on chip oscillator PDL_CAC_MEASURE_LOCO or low speed on chip oscillator or PDL_CAC_MEASURE_
53. PDL_RTC_CLOCK_STOP or PDL_RTC_CLOCK_START Stop or re start the clock 30 second adjustment control PDL_RTC_ADJUST_START Start the 30 second adjustment process Reset control PDL_RTC_RESET_START Start the reset process Page 221 of 429 RX220 Group 4 Library Reference Description 2 3 data2 Select the values to be changed To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA Select the time counters to be updated using values supplied in parameter data3 PDL_RTC_UPDATE_CURRENT_ HOUR PDL_RTC_UPDATE_CURRENT_MINUTE All three can be selected using PDL_RTC_UPDATE_CURRENT_TIME PDL_RTC UPDATE CURRENT SECOND e Select the date counters to be updated using values supplied in parameters data3 and data4 PDL_RTC_ UPDATE CURRENT YEAR All four can be selected using PDL_RTC_UPDATE_CURRENT_ MONTH PDL_RTC_UPDATE_CURRENT_DATE PDL_RTC_UPDATE_ CURRENT DAY Parameter data3 is used for the day of the PDL_RTC_UPDATE_CURRENT_ DOW week e Select the alarm time counters to be updated using values supplied in parameter data5 PDL_RTC_UPDATE_ALARM_ HOUR PDL_RTC_UPDATE_ALARM_MINUTE PDL_RTC_UPDATE_ALARM_SECOND All three can be selected using PDL_RTC_UPDATE_ALARM_TIME Select the alarm date counters to be updated using values supplied in p
54. PDL_VERSION 3 2 1 Bit definitions The definitions BIT_n and INV_BIT_n where n 0 to 31 are available to the user R01US0059EG0111 Rev 1 11 Page 46 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 1 API List by Peripheral Function 4 Library Reference Table 2 lists the Renesas Embedded APIs by peripheral function Table 2 Renesas Embedded API List Category tend Name Description Clock G ti 1 R_CGC_Set Configure the clock generation circuit Bea eneraton 2 R_CGC_Control Modify the clock generation circuit operation 3 R_CGC_GetStatus Read the status of the clock generation circuit 1 R_INTC_SetExtinterrupt Select the external interrupt pins 2 R_INTC_CreateExtInterrupt Configure an external interrupt signal 3 anni Enable use of the software interrupt 4 R_INTC_CreateFastInterrupt Assign handlers for the fixed vector interrupts ee control 5 Urge aes ae Enable faster interrupt processing for one interrupt 6 R_INTC_ControlExtinterrupt External interrupt control R_INTC_GetExtInterruptStatus Read the external interrupt status R_INTC_Read Read an interrupt register R_INTC_Write Update an interrupt register 0 R_INTC_Modify Modify an interrupt register R_IO_PORT_Set Configure an I O port R_IO_PORT_ReadControl Read an I O port s control registers IO _ PORT _ModifyControl Modify an I O port s control registers O PORT Rea
55. R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_NO_DATA U2_Set 3 PDL MTU2_ PIN 3A P14 Load the defaults R_MTU2_Create_load_defaults amp create_parameters create_parameters channel_mode PDL_MTU2_MODE_PWM1 create_parameters counter_operation PDL_MTU2_CLK_PCLK_DIV_256 PDL_MTU2_CLK_RISING PDL_MTU2_CLEAR_TGRA create_parameters TGR_A_B_ operation PDL_MTU2_A_OC_HIGH PDL_MTU2_B_OC_LOW create_parameters TGRA_TCNTV_value 39062 R01US0059EG0111 Rev 1 11 Page 339 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples create_parameters TGRB_TCNTW_value 33000 R_MTU2_Create 3 amp cre ate_ parameters control_parameter control_setting PDL_MTU2_START control_parameter register_selection PDL_NO_DATA R_MTU2_ControlChannel 3 amp control_parameter while 1 Figure 17 Example of MTU PWM mode 1 R01US0059EG0111 Rev 1 11 Page 340 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 13 2 Reset synchronized PWM mode This example shows a usage of Multi Function Timer Pulse Unit with Synchronized PWM mode Peripheral driver function prototypes include r_pdl_mtu2 h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h Global struct to avoid unwanted initial value R_MTU2_ControlUnit_structure control_unit_para
56. Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for all parameters func 1 to 4 func5 For n 0 The function to be called when a TGRE event occurs Specify PDL_NO_FUNC if not required func6 For n 0 The function to be called when a TGRF event occurs Specify PDL_NO_FUNC if not required func7 For n 0 to 3 The function to be called when an overflow occurs For n 4 The function to be called when an overflow or underflow occurs Specify PDL_NO_FUNC if not required func8 For n 1 or 2 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required interrupt_priority_2 The interrupt priority level for TGRE TGRF overflow or underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for all parameters func 5 to 8 True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_Set R_MTU2_ControlChannel R_MTU2_ControlUnit RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 162 of 429 RX220 Group 4 Library Reference Remarks e If an external clock input pin MTCLKx or I O pin MTIOCnx is made active this function will configure that pin for input or output and disable other functions on that pin e The alternative pins are assigned usin
57. To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA 12 or 24 hour mode Change clock settings and update the time or date in calendar count mode PDL_RTC_24 HOUR_MODE or PDL_RTC_12 HOUR_MODE Select 12 or 24 hour mode Alarm control PDL_RTC_ALARM_HOUR_DISABLE or PDL_RTC_ALARM HOUR ENABLE PDL_RTC_ALARM_MINUTE_DISABLE or PDL_RTC_ALARM_MINUTE_ENABLE PDL_RTC_ALARM_SECOND_DISABLE or PDL_RTC_ALARM SECOND ENABLE All three can be controlled using PDL_RTC_ALARM_TIME_DISABLE or PDL_RTC_ALARM_TIME_ENABLE PDL_RTC_ALARM_YEAR_DISABLE or PDL_RTC_ALARM_YEAR ENABLE PDL_RTC_ALARM_MONTH_DISABLE or PDL_RTC_ALARM_MONTH_ENABLE PDL_RTC_ALARM_DAY_DISABLE or PDL_RTC_ALARM_ DAY ENABLE PDL RTC ALARM DOW DISABLE or PDL_RTC_ALARM_DOW_ENABLE All four can be controlled using PDL_RTC_ALARM_DATE_DISABLE or PDL_RTC_ALARM_DATE_ENABLE Clock output control RTC counting will be stopped temporarily during the writing of RTCOE bit PDL RTC OUTPUT DISABLE or PDL_RTC_OUTPUT_ENABLE Disable or enable the 1 Hz 64 Hz clock output on the RTCOUT pin Clock RTCOUT output period Select RTC counting will be stopped temporarily during the writing of RTCOS bit PDL_RTC_OUTPUT_RTCOS_1HZ or PDL_RTC_OUTPUT_RTCOS_64HZ RTCOUT outputs 1 Hz RTCOUT outputs 64 Hz Clock control
58. e Cascade input capture control Valid in cascade mode for n 1 Channel n forms the higher 16 bits and channel n 1 forms the lower 16 bits PDL_MTU2 CASCADE _AL_IC_INC_H PDL_MTU2_CASCADE_AL_IC_EXC_H or Exclude or include pin MTIOCnA in the TGRA input capture conditions for channel n 1 PDL_MTU2 CASCADE BL_IC_INC_H PDL_MTU2_CASCADE_BL_IC_EXC_H or Exclude or include pin MTIOCnB in the TGRB input capture conditions for channel n 1 PDL_MTU2_CASCADE_AH_IC_INC_L PDL_MTU2_CASCADE_AH_IC_EXC_L or Exclude or include pin MTIOC n 1 A in the TGRA input capture conditions for channel n PDL_MTU2_CASCADE_BH_IC_INC_L PDL_MTU2_CASCADE_BH_IC_EXC_L or Exclude or include pin MTIOC n 1 B in the TGRB input capture conditions for channel n Rev 1 11 2tENESAS Page 158 of 429 RX220 Group Description 6 9 TGR_C_D_operation RO1US0059EG0111 Aug 01 2014 4 Library Reference Configure the operation for general registers TGRC and TGRD Valid for n 0 3 and 4 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRC PDL_MTU2_C_OC DISABLED or PDL_MTU2_C_OC_ LOW or PDL_MTU2_C_OC_LOW_CM HIGH or PDL_MTU2_C_OC_LOW_CM_INV or PDL_MTU2_C_OC_HIGH_CM_LOW or PDL_MTU2_C_OC_HIGH or PDL_MTU2_C_OC_HIGH_CM_IN
59. nop Figure 29 Example of using RTC is used and wake up from sleep mode R01US0059EG0111 Rev 1 11 Page 362 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 2 Wake up from software standby mode Figure 30 shows an example of using the RTC wake up from software standby mode The HOCO is used as system and and sub clock as RTC count source include lt stdio h gt include lt string h gt PDL functions include r_pdl_cgc h include r_pdl_lpc h include r_pdl_cmt h include r_pdl_mcu h include r_pdl_rtc h include r_pdl_sci h PDL device specific definitions include r_pdl_definitions h define RSK_SCI_CHANNEL 1 static void SetClocks void static void Alarm_handler void volatile bool bSoftStdbyEnter false void main void uintl6_t status 0 uint8_t flags uint32_t time uint32_t date uint8_t buffer 50 uint32_t time_previous 0 Sets system clock SetClocks Create async for debug output R_SCI_Set RSK_SCI_CHANNEL PDL_SCI_PIN_SCI1_RXD1 PDL_SCI_PIN_SCI1_TXD1 R_SCI_Create RSK_SCI_CHANNEL PDL_SCI_8N1 PDL_SCI_ASYNC 9600 1 Check warm cold start flag CWSF 1 call R_RTC_CreateWarm to start up the RTC if warm cold start flag is detected power ON from warm start Get Reset Status Flag R_MCU_Get Status PDL_NO_PTR amp status PDL_NO_PTR PDL_NO_PTR i
60. s build environment you need to a Unzip the RPDL distribution b Copy the required source header and library files into your project folder c Include the required source files d Add the driver library file to the linked files list The instructions to follow for stand alone use start are given below 1 Unzip the RPDL files Double click on the file RPDL_RX220 exe to unpack the files The default location is C Renesas RPDL_RX220 R01US0059EG0111 Rev 1 11 Page 2 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 2 Copy the files into your project area Navigate to where the RPDL files were unpacked fe RPDL I 3 Fie Edit View Favorites Tools Help d Address C Renesas RPDL_RX220 Go Common Device specific E Copy_RPDL_RX220 bat 3objects 3 88 KB My Computer Double click on Copy __RPDL_RX220 bat to start the copy process Bic Renesas RPDL for R8220 copy utility Please enter a number to select the device package and endian option 166 pins little endian 166 pins big endian 64 pins little endian 64 pins big endian 48 pins little endian 48 pins big endian Select the device package option by pressing a number and then press Enter BEE Renesas RPDL for R8220 copy utility Please enter a number to select the device package and endian option 1 166 pins little endian 166 pins big endian 64 pins little endian 64 pins big endian 48 pins little
61. start Valid for n 0 to 4 PDL_MTU2_STOP Stop the count operation PDL_MTU2_ START Start the count operation e Counter stop Start Valid for n 5 PDL_MTU2_ STOP_U PDL_MTU2 STOP_V Stop the count operation PDL_MTU2 STOP_W PDL_MTU2 START _U PDL MTU2_START_V Start the count operation PDL_MTU2 START _W register_selection The channel registers to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no register change is required e The registers to be modified Forn 0to 4 PDL_MTU2_REGISTER_COUNTER Timer counter register TCNT PDL_MTU2_ REGISTER_TGRA General register A PDL_MTU2_REGISTER_TGRB General register B PDL_MTU2_ REGISTER_TGRC General register C Valid for n 0 3 or 4 PDL_MTU2_ REGISTER_TGRD General register D Valid for n 0 3 or 4 PDL_MTU2_REGISTER_TGRE General register E Valid for n 0 PDL_MTU2_REGISTER_TGRF General register F Valid for n 0 ADC start request cycle set buffer A PDL_MTU2_REGISTER_TADCOBRA Valid for n 4 PDL_MTU2_REGISTER_TADCOBRB ADC start request cycle set buffer B Valid for n 4 R01US0059EG0111 Rev 1 11 REN ESAS Page 165 of 429 Aug 01 2014 RX220 Group Description 2 2 4 Library Reference Forn 5 Return value PDL_MTU2_REGISTER_COUNTER_U Timer counter U r
62. to separate each selection e Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source e The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A_ Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B_ Update the timer compare match B register TCORB data3 The 16 bit counter value This will be ignored if the register is not selected data4 The 16 bit compare match A value This will be ignored if the register is not selected data5 The 16 bit compare match B value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateUnit Remarks e For unit 0 the upper byte is the value for TMRO and the lower byte is the value for TMR1 For unit 1 the upper byte is the value for TMR2 and the lower byte is the value for TMR3 RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 200 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Load the unit 1 counter and constants R_TMR_ControluUnit 1 PDL_TMR_ COUNTER PDL_TMR TIME _CONSTANT_A PDL_TMR_TIME_CONSTANT_B
63. 0 external variables Options C C cpu rx200 dbl_size 8 include PROJDIRJSAPDL include PROJDIR output obj CONFIGDIR FILELEAF obj debug goptimize nologo R01US0059EG0111 Rev 1 11 Page 10 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction ii Linker Select the Link Library tab Use the key sequence Y O O to show the optimisation options If the Eliminate dead code option is not enabled from the Optimize drop down list select Custom and enable the option RX Standard Toolchain Configuration C C Assembly Link Library Standard Library ATos gt Debug zi Category Optimize z T All Loaded Projects iy Ee Show entries for C source file Optimize items 7 C source file ai mi Assembly source file Optimize KETA Eliminated size 0x001E TAAA Linkage symbol file Eliminate dead code runs am Lu JOptimize branches JUse short disp imm Options Link Library noprelink rom D R D_1 R_1 D_2 R_2 nomessage list CONFIGDIR PROJECTNAME map optimize symbol_delete R01US0059EG0111 Rev 1 11 Page 11 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction b Set the floating point precision The wide range of possible internal clock frequencies requires double precision floating point number storage Select the CPU tab Click on the Details button to open the CPU details
64. 38400 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 Wait while send message R_SCI_Send 1 PDL_NO_DATA r nHello Type 5 characters and I will echo them back r n 0 PDL_NO_FUNC Wait for message to be sent while false data_sent Wait for 5 characters to be read R_SCI_Receive 1 PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC PDL_NO_FUNC Echo the 5 characters back R_SCI_Send 1 PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC while 1 Figure 32 Example of SCI asynchronous operation using polling R01US0059EG0111 Rev 1 11 Page 370 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 2 SCI Asynchronous Using Interrupts This shows the setting of SCI channel 1 and the transmission and reception of data using interrupts Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void SCIrx void gt void SCItx void volatile bool data_received volatile bool data_sent volatile uint8_t rx_buffer 5 void main void Initialise flags data_sent false data_received false Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Pleas refer to 5 1 Clock Generation Circuit Set channel 1 pin options R_SCI_Set 1
65. All selections are optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop control PDL_MTU2_ STOP_C PDL_MTU2_ STOP_C PDL_MTU2_STOP_C HO H1 PDL_MTU2_STOP_CH 2 H3 H4 PDL_MTU2_STOP_C Stop the count operation for the selected channels e Counter start control PDL_MTU2_START_C PDL_MTU2_START_C PDL_MTU2_START_C HO H1 PDL_MTU2_START_CH 2 H3 H4 PDL_MTU2_START_C Start the count operation for the selected channels RX220 Group Description 2 4 RO1US0059EG0111 Aug 01 2014 output_control The output control settings to be modified All settings are optional If multiple selections are required use to separate each selection Rev 1 11 Output control To apply output control make sure the operation of t Select one option for each output 4 Library Reference he corresponding channel is stopped PDL_MTU2_OUT_P_PHASE_1_ENABLE or PDL_MTU2 OUT _P_PHASE_1 DISABLE MIOCSB PDL MTU2 OUT N PHASE 1 DISABLE MTIOCSD POL WTO OUT ERASE SUSE T aioow PDL MTU2 OUT N PHASE 2 DISABLE MTIOCAC PDL MTU2 OUT P PHASE 3 DISABLE MTIOC4B PDL MTU2 OUT N PHASE 3 DISABLE MTIOC4D Or all six phase outputs can be contro
66. Between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false I O port R_IO_PORT_Set If an invalid port or pin is specified the operation of the function cannot be guaranteed e This function waits for the I O port or port pin value to match the comparison data If the I O port s control registers are directly modified by the user this function may lock up The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Wait until pin P05 reads as 0 R_IO_PORT_Wait PDL_IO_PORT_0_5 0 i Wait until port 5 reads as 0x55 R_IO PORT Wait PDL_IO_PORT_5 0x55 i RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 86 of 429 RX220 Group 4 Library Reference 9 R_IO_PORT_NotAvailable Synopsis Prototype Description Return value Category References Remarks Program example Configure I O port pins that are not available bool R_IO_PORT_NotAvailable void No parameter is required Set the port pins that are not available on smaller packages to the recommended state True I O port None All pins that are not available on the selected package will be configured for CMOS type low level output RPDL defini
67. Both RTC count source and System clock in Calendar count mode R01US0059EG0111 Rev 1 11 Page 352 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 4 Configuration CGC and RTC counting by sub clock both RTC count source and System clock in binary count mode Figure 26 shows an example of sub clock used as both RTC count source and system clock in Binary count mode PDL functions include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h PDL device specific definitions include r_pdl_definitions h void main void volatile uint8_t flags volatile uint32_t count alarm r_mask Prepare the LOCO settings R_CGC_Set DL_CGC_CLK_LOCO DL_NO_DATA 25E3 25E3 D 2 2 D pP f Prepare the Sub clock settings R_CGC_Set PDL_CGC_CLK_SUB_CLOCK DL_CGC_SUB_CLOCK_CL_STANDARD 2768 2768 D 2 2 D L_NO_DATA 768 PCLKB clock sub clock when sub clock is source clock 768 L_CGC_SUB_32768 Generate the 2s delay befor nabling RTC by CGC_Control R_CMT_CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 Select the HOCO as the clock source R_CGC_Control PDL_CGC_CLK_SUB_CLOC PDL_NO_DATA PDL_CGC_RTC_TO_BE_US If Cold start is detected the RTC clock should be re started R_RTC_CreateBinary PDI DATA Configuration 0 345678 Curren
68. Callback function void func2 Callback function Register the user functions to be called by the fixed vector and software interrupts func1 The function to be called when a privileged instruction is detected while in user mode Specify PDL_NO_FUNC if no callback function is required func2 The function to be called when an undefined instruction is detected Specify PDL_NO_FUNC if no callback function is required True Interrupt control None Please see the notes on callback function use in 6 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void UndefinedInstruction void void func void Assign a function to manage undefined instruction errors R_INTC_CreateExceptionHandlers PDL_NO_FUNC UndefinedInstruction Rev 1 11 REN ESAS Page 65 of 429 RX220 Group 4 Library Reference 6 R_INTC_ConitrolExiinterrupt Synopsis External interrupt control Prototype bool R_INTC_ConitrolExitInterrupt uint8_t data1 Pin selection uint32_t data2 Control Description Modifies the specified external interrupt data1 Choose the interrupt pin to be controlled PDL_INTC_IRQn n 0 to 7 or IRQn interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 Select the controls If multiple selections are required use t
69. Description Set up the global TMR options data1 The channel number n where n 0 1 2 or 3 data2 Configure the TMR input and output pins for the channel Use to separate each selection e Validwhenn 0 PDL_TMR_TMRO_TMOO_P22 or PDL_TMR_TMRO_TMOO_PB3 or Select the pins for TMOO PDL_TMR_TMRO_TMOO_PH1 PDL_TMR_TMRO_TMCIO_P21 or PDL_TMR_TMRO_TMCIO_PB1 or Select the pins for TMCIO PDL_TMR_TMRO_TMCIO_PH3 PDL_TMR_TMRO_TMRIO_P20 or PDL_TMR_TMRO_TMRIO_PA4 or Select the pins for TMRIO PDL_TMR_TMRO_TMRIO_PH2 e Valid when n 1 PDL_TMR_TMR1_TMO1_P17 or PDL_TMR_TMR1_TMO1_P26 PDL_TMR_TMR1_TMCI1_P12 or PDL_TMR_TMR1_TMCI1_P54 or Select the pins for TMCI1 PDL_TMR_TMR1_TMClI1_PC4 PDL_TMACTMRT_TMRN_P24 or Select the pins for TMA Select the pins for TMO1 e Valid when n 2 PDL_TMR_TMR2_TMO2_P16 or PDL_TMR_TMR2_TMO2_PC7 PDL_TMR_TMR2_TMCI2_P15 or PDL_TMR_TMR2_TMCI2_P31 or Select the pins for TMCI2 PDL_TMR_TMR2_TMCl2_PC6 PDL_TMR_TMR2_TMRI2_P14 or PDL_TMR_TMR2_TMRI2_PC5 Select the pins for TMO2 Select the pins for TMRI2 e Valid whenn 3 PDL_TMR_TMR3_TMO3_P13 or PDL_TMR_TMR3_TMO3_P32 or Select the pins for TMO3 PDL_TMR_TMR3_TMO3_P55 PDL_TMR_TMR3_TMCI3_P27 or PDL_TMR_TMR3_TMCI3_P34 or Select the pins for TMCI3 PDL_TMR_TMR3_TMCI3_PA6 PDL_TMR_TMR3_TMRI3_P30 or PDL_TMR_TMR3_TMRI3_ P33
70. Library Reference Configuration selection 16 bit counter register value 16 bit compare match A register value 16 bit compare match B register value Overflow callback function Compare match A callback function Compare match B callback function Interrupt priority level The unit number n where n 0 or 1 data2 Set up a timer TMR unit in 16 bit count mode Configure the unit If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Counter clock source selection PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or The external clock signal TMCIx x 1 or 3 for n PDL_TMR_CLK_EXT_FALLING or 0 or 1 is used with rising falling or both edges PDL_TMR_CLK_EXT_BOTH or detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL TMR CLK PCLK DIV 32 or peer mae signal PCLKB 1 2 8 32 64 PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 Counter clearin PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn
71. PDL_MTU2 PIN 4D PE4 Select the P24 PAO PB3 or PE2 pin for MTIOC4A Select the P25 PB1 PE1 or PES pin for MTIOC4C Select the P31 P55 PC3 PD2 or PE4 pin for MTIOC4D Valid when n 5 PDL_MTU2_ PIN 5U_PA4 or PDL_MTU2 PIN 5U PD7 PDL_MTU2_PIN_5V_PA6 or PDL_MTU2 PIN 5V_PD6 PDL_MTU2_PIN_5W_PBO or PDL_MTU2_PIN_5W_PD5 Select the PA4 or PD7 pin for MTIOC5U Select the PA6 or PD6 pin for MTIOCS5V Select the PBO or PD5 pin for MTIOC5W Valid when n 0 1 2 3 or 4 PDL_MTU2_PIN_CLKA P14 or PDL_MTU2_PIN_CLKA_P24 or PDL_MTU2_PIN_CLKA_PA4 or PDL_MTU2_PIN_CLKA_PC6 PDL_MTU2_PIN_CLKB_ P15 or PDL_MTU2_PIN_CLKB_P25 or PDL_MTU2_PIN_CLKB_PA6 or PDL_MTU2 PIN CLKB PC7 Select the P14 P24 PA4 or PC6 pin for MTCLKA Select the P15 P25 PA6 or PC7 pin for MTCLKB Valid when n 0 or 2 PDL_MTU2_PIN CLKC_P22 or PDL_MTU2_PIN_CLKC_PA1 or Select the P22 PA1 or PC4 pin for MTCLKC PDL_MTU2_PIN_CLKC_PC4 PDL_MTU2_PIN_CLKD_P23 or PDL_MTU2_PIN_CLKD_PA or PDL_MTU2_PIN_CLKD_PC5 Select the P23 PA3 or PC5 pin for MTCLKD When n 2 required in Phase Counting Mode only Return value True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_Create Remarks e Before calling R MTU2_Create c
72. PDL_NO_DATA PDL_PO ther interrupts and try to clear the flag FLAG_PO E8_CL EAR PDL_POE IRQ_HI_Z_8_DISABLI Figure 15 Example of Port Output Enable function R01US0059EG0111 Rev 1 11 Aug 01 2014 2 ENESAS Page 337 of 429 RX220 Group 5 Usage Examples 5 12 Event Link Controller In this example the Event Link Controller links the 8 bit Timer with an I O pin Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_tmr h include r_pdl_io_port h include r_pdl_elc h RPDL device specific definitions include r_pdl_definitions h void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set pin B_O as an output pin R_IO_PORT_Set PDL_IO_PORT_B_0 PDL_IO_PORT_OUTPUT Configure TMR channel 0 R_TMR_CreateChanneli 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_NO_DATA 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 i Enable the module no ELC interrupts required iC_Create PDL_NO_FUNC PDL_NO_DATA Create link between event TMR Channel 0 and module SinglePort 0 R_ELC_Control PDL_ELC_CREATE_LINK iC_LINK DULE_SINGLE_PORT_O PDL_ PDL_ELC_LINK ENT_TMR_CHANNEL_0O_COMPARE_MATCH_AO
73. PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRIx x 0 or 2 for n O or 1 is high Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_TMR_CM_A_DTC_TRIGGER_ENABLE when a Compare Match A occurs Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_TMR_CM_B DTC_TRIGGER_ENABLE when a Compare Match B occurs Rev 1 11 2tENESAS Page 189 of 429 RX220 Group Description 2 2 Return value Category Timer TMR Reference R_TMR_Set Remarks e Please use R_TMR_Set to select the input TMCIn TMRIn and output TMOn pins as required This function will return false if a pin is enabled but is not set properly e The output will be high impedance when PDL_TMR_OUTPUT_IGNORE_CM_A and PDL_TMR_OUTPUT_IGNORE_CM B are selected e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R01US0059EG0111 Rev 1 11 Page 190 of 429 Aug 01 2014 data3 Configure the output control If multiple selections are required use to separate each selection The default se
74. RPDL device specific definitions include r_pdl_definitions h void main void Set the LOCO clock settings the clock source used after a power on reset ICLK 125 kHz PCLKB 125 kHz FCLK 125 kHz R_CGC_Set PDL_CGC_CLK_LOCO PDL_NO_DATA 125E3 125E3 PDL_NO_DATA 125E3 125E3 Configure main clock operation using an external 20 0 MHz clock ICLK 20 MHz PCLKD 20 4 MHz PCLKB 20 8 MHz FCLK 20 16 MHz R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_RESONATOR 201 201 201 201 201 HA ew DAAAD mop an Select the Main clock as the clock source R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA L_NO_DATA Figure 3 Example of Clock configuration and control R01US0059EG0111 Rev 1 11 Page 318 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 2 Interrupt control Figure 4 shows an example of external interrupt use Pin IRQ1 on port pin P31 is used to detect a falling edge and generates an interrupt The interrupt handler inverts the edge detection and disables further interrupts Pin IRQ3 on port pin P33 is used to detect a falling edge and generates an interrupt Pin IRQ4 on port pin P34 is used to detect low level state and generates an interrupt Peripheral driver function prototypes include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback func
75. R_RWP_Control PDL_RWP_ENABLE_CGC_WRI PDL_RWP_ENABLE_MODE_RES PDL _ RWP_ENABLE_ LVD_WRI PDL_RWP_ENABLE_MPC_WRI Get sta protection R_RWP_GetS amp prcer amp pwpr Turn on all register write protection R_RWP_Control PDL_RWP_DISABLE_CGC_WRITE PDL_RWP_DISABLE_MODE_RES PDL _RWP_DISABLE_LVD_WRITE PDL_RWP_DISABLI _MPC_WRIT Get status of protection R_RWP_Get Status amp prcr amp pwpr Figure 11 Examples of Register Write Protection R01US0059EG0111 Rev 1 11 Page 329 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 9 DMA controller The following example shows the use of triggers by software and IRQ pin edge detection Channel 0 will copy the string Renesas RX220 into the destination area when a falling edge occurs on pin IRQ1 P31 Channel 1 will copy the string Hello World into the destination area as soon as it is enabled PDL functions and definitions include r_pdl_dmac h inelude rjpdl_intc h include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Callback function prototype void DMACO_transfer_end_handler void Data source and destination declaratio
76. References None Remarks lf a reset detection flag is set to 1 it shall be automatically cleared to 0 by this function R01US0059EG0111 Rev 1 11 Page 93 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void uint1l6_t status Read the MCU status registers R_MCU_Get Status amp status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR 3 R01US0059EG0111 Rev 1 11 Page 94 of 429 Aug 01 2014 RENESAS RX220 Group 3 R_MCU_OFS Synopsis Prototype Description 1 2 R01US0059EG0111 Aug 01 2014 R_MCU_OFS uint32_t data1 uint32_t data2 uint32_t data3 data1 Select the post reset IWDT configuration settings If multiple selections are required use to separate each selection Auto start control Configure the device start up operation 4 Library Reference WDT configuration options LVD configuration options CGC configuration options Select the auto start settings to be stored in registers OFSO and OFS1 PDL_MCU_OFS_IWDT HALTED or PDL_MCU_OFS_IWDT AUTOSTART Disable or enable the IWDT auto start mode If auto start mode is enabled select one setting from each of the following Rev 1 11 Timeout period PDL_
77. data1 Select channel ICn where n 0 data2 Select the operation options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_RX_DMAC_TRIGGER_ENABLE or DMAC or DTC when a byte is PDL_IIC_RX_DTC_TRIGGER_ENABLE received PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_TX_DMAC_TRIGGER_ENABLE or PDL_IIC_TX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for data transmission data3 The start address of the storage area for any received data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data4 The number of bytes in the storage area If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC If not using the DMAC or DTC this function will continue until a Stop or Re Start condition is detected or the master tries to read Polling data from this slave If using the DMAC or DTC the function will return after detecting a slave address match so that the DTC DMAC can complete the transfer The function to be called when a Stop or Re Start condition is detected or Return value Interrupts the master tries to re
78. disabled e The Disable operation is executed at the start of this function The Enable operation is executed at the end Therefore both options can be selected together with operation changes in one function call e Ifthe Disable and or Enable operation is selected this function will wait for the operation to complete before continuing To prevent lockup ensure that an enable disable operation is not also performed from a callback function at the same time Ifthe CACREF input is selected the digital filter setting used in R_CAC_Create will be retained RPDL definitions include r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h void func void Clear the measurement complete flag without stopping R_CAC_Control PDL_CAC_CLEAR_ MEASUREMENT PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Rev 1 11 REN ESAS Page 107 of 429 RX220 Group 4 Synopsis Prototype Description Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 Rev 1 11 R_CAC_GetStatus Read the clock accuracy circuit status bool R_CAC_GetSiatus uint8_t data1 uint16_t data2 Data storage location uint16_t data3 Data storage location uint16_t data4 Data storage location Read the status limit and counter registers 4 Library Reference
79. e The maximum number of characters to be received is 65535 e Wait until a transmission on the same channel is complete before calling this function e Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed e This function unless configured not to will by default automatically start a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_IIC_ReadLastByte or R_SCI_Control function to manually generate a stop e The last byte of a master read will automatically be NACK d However if using DMAC or DTC this will not happen If a NACK is required then use the DMAC DTC to read all the data except for the last byte and then use function R_SCI_IIC_ReadLastByte to read the last byte e If a callback function is specified and the interrupt priority level is zero this function will return false PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 9 define SLAVE_ADDRESS OxAO Buffer for IIC data extern uint8_t IIC_Buffer 10 void func void Wait while read 10 bytes R_SCI_IIC_Read CHANNEL _SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIC_Buffer PDL_NO_FUNC R01US0059EG0111 Rev
80. func3 Callback function Error Perform an SPI transfer This may be sending receiving or both sending and receiving data data1 Select channel SCIn where n 1 5 6 9 or 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_SPI_TX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_TX_DMAC_TRIGGER_ENABLE or the DMAC or DTC whena PDL_SCI_SPI_TX_DTC_TRIGGER_ENABLE data byte is transmitted DMAC DTC trigger control PDL_SCI_SPI_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_RX_DMAC_TRIGGER_ENABLE or the DMAC or DTC whena PDL_SCI_SPI_RX_DTC_TRIGGER_ENABLE data byte is received data3 The number of bytes that must be transferred either transmitted received or both before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data func1 Transmit callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until
81. operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control 2 Disabling DMA channels that are no longer required and enabling low power mode 3 Control of a channel 4 Reading the status and operation registers of a channel R01US0059EG0111 Rev 1 11 Page 30 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 14 Data Transfer Controller Driver The driver functions support the control of the Data Transfer Controller providing the following operations 1 Setting the central options 2 Configuration for use including support for chain transfers 3 Disabling the controller 4 Starting stopping or modifying the operation of the controller 5 Reading the status flags and data transfer registers R01US0059EG0111 Rev 1 11 Page 31 of 429 Aug 01 2014 RENESAS RX220 Group 2 15 Event Link Controller The driver functions support the control of the Event Link Controller providing the following operations RO1US0059EG0111 Aug 01 2014 As 2 Enabling the module Disabling the module Linking events with modules Configuring Timer output Setting and controlling port groups 2 Driver Page 32 of 429 RX220 Group 2 Driver 2 16 Multi Function Timer Pulse Unit Driver The driver functions support the use of the six 16 bit timers providing the following operations 1 Selection of the MTU pins for use 2 Configuration for use includi
82. r_pdl_definitions h void func void Select P30 for IRQO and P31 for IRQ1 R_INTC_SetExtInterrupt PDL_INTC_IRQO_P30 PDL_INTC_IRQ1_P31 R01US0059EG0111 Rev 1 11 Page 58 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_INTC_CreateExtinterrupt Synopsis Prototype J Description 1 2 R01US0059EG0111 Aug 01 2014 Configure an external interrupt signal bool R_INTC_CreateExtinterrupt uint8_t data1 Signal selection uint32_t data2 Configuration void func Callback function uint8_t data3 Interrupt priority level data1 Choose the interrupt signal to be configured Sets the specified interrupt detection and control PDL_INTC_IRQn n 0 to 7 or PDL_INTC_NMI data2 Choose the settings If multiple selections are required use to separate each selection The default settings are shown in bold Digital filter selection IRQn n 0 to 7 interrupt pin or NMI PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC FILTER DIV 64 The interrupt pin input can be unfiltered or sampled using the peripheral clock PCLKB divided by 1 8 32 or 64 For the NMI signal this selection is ignored if the NMI pin is not enabled Options which only apply to the IRQ pins Input sense selection PDL_INTC_LOW or PDL_INTC_
83. selecting the clock source This function can not be used if ROM Flash Program Erase mode is set or if an operating power mode transition is in progress This function will return false if this is detected Calling R_RTC_Create after using option PDL_CGC_RTC_TO_BE_USED Make sure PCLKB clock frequency 2 RTC count source clock frequency Call R_CGC_Set once to set sub clock frequency before call R CGC_Control with option PDL_CGC_RTC_TO_BE_USE Sub clock oscillator is not available for 48 pin package RPDL definitions r pdl_cgce h RPDL device specific definitions r pdl_definitions h void func void Rev 1 11 Stop the sub clock oscillator R_CGC_Control PDL_NO_DATA PDL_NO_DATA PDL_CGC_SUB_CLOCK_DISABLE Select the Main clock R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_NO_DATA RX220 Group 4 Library Reference 3 R_CGC_GetStatus Synopsis Prototype Description Return value Category References Remarks Program example Read the status of the clock generation circuit bool R_CGC_GetStatus uint16_t data Pointer to the variable where the status value shall be stored 5 Read the clock status register data The status flags shall be stored in the format below b15 b14 b13 b12 b11 b10 b9 b8 HOCO Clock control 0 power HOCO IWDTLOCO LOCO Sub
84. so there should be no need for the user s code to use this instruction More information on the processor modes can be found in 1 4 of the RX Family software manual R01US0059EG0111 Rev 1 11 Page 428 of 429 Aug 01 2014 RENESAS RX220 Group 6 RX specific notes 6 2 Interrupts and DSP instructions The accumulator ACC register is modified by the following instructions i DSP MACHI MACLO MULHI MULLO MVTACHI MVTACLO and RACW ii Multiply and multiply and accumulate EMUL EMULU FMUL MUL and RMPA The accumulator ACC register is not pushed onto the stack by the API interrupt handlers If DSP instructions are being utilised in the users code callback functions which are called by the API interrupt handlers should either a Avoid using instructions which modify the ACC register b Take acopy of the ACC register and restore it before exiting the callback function R01US0059EG0111 Rev 1 11 Page 429 of 429 Aug 01 2014 RENESAS RX220 Group Revision History Revision History RX220 Group User s Manual imi Sep 18 2013 Apr 01 2014 R01US0059EG0111 Rev 1 11 Aug 01 2014 Summary R_CGC_Control Added missing options R_RWP_GetStatus Change PDL_NO_DATA to PDL_NO_PTR Add the 1 2 Compiler options when you use this product Change 1 3 2 content into Using RPDL stand alone Add content Copy folder RPDL into the folder project workspace created Example C WorkSpace r
85. static void SCI9RxFunc void void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Set Master Channel 6 pin options R_SCI_Set MASTER_CHANNEL PDL_SCI_PIN_SCI6_RXD6 PDL_SCI_PIN_SCI6_TXD6 PDL_SCI_PIN_SCI6_SCK6 Set Master Channel 9 pin options R_SCI_Set SLAVE_CHANNEL PDL_SCI_PIN_SCI9_RXD9 PDL_SCI_PIN_SCI9_TXD9 PDL_SCI_PIN_SCI9_SCK9 Create Master Channel R_SCI_Create MASTER_CHANNEL PDL_SCI_SYNC PDL_SCI_RX_DISCONNE PDL_SCI_CLK_INT_OUT 19200 1 Create Channel slave NOTE Even though using an external clock the driver needs to know the expected baud rate Bit 31 is set to signify not generating baud R_SCI_Create SLAVE_CHANNEL PDL_SCI_SYNC PDL_SCI_TX_DISCONNE PDL_SCI_CLK_EXT 0x80000000 19200 R01US0059EG0111 Rev 1 11 Page 375 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Set flag to wait on data_received false Setup a read on channel slave R_SCI_Receive SLAVE_CHANNEL PDL_NO_DATA rx_buffer 5 SCI9RxFunc PDL_NO_FUNC Send the data from the master R_SCI_Send MASTER_CHANNEL PDL_NO_DATA WL2345 5 PDL_NO_FUNC Wait
86. using pulse width or duty cycle as an input e Automatic interrupt control Configuration for as a one shot timer including Automatic clock setting using pulse width as an input Automatic interrupt control CPU sleep option Automatic support for using two channels as a single 16 bit timer Disabling channels that are no longer required and enabling low power mode Control of a single timer channel Control of two timer channels when configured as one 16 bit channel Control of channels in periodic mode enabling pulse width modulation PWM output 10 Reading the registers of a single timer channel 11 Reading the registers of a 16 bit timer channel pair Note The Clock Generation Circuit must be configured before configuring any timer channel R01US0059EG0111 Rev 1 11 REN ESAS Page 35 of 429 Aug 01 2014 RX220 Group 2 Driver 2 19 Compare Match Timer Driver The driver functions support the use of the two 16 bit timers providing the following operations 1 Configuration for use including e Automatic clock setting using frequency or period as an input e Manual clock setting using register values as inputs e Automatic interrupt control 2 Configuration for use as a one shot timer 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer including constant register updates change of frequency 5 Reading the counter value and status flag Note The Clock Gener
87. 0 b31 b16 b15 bO The SCL rise time in nanoseconds The SCL fall time in nanoseconds Valid from 0 to 65535 Valid from 0 to 65535 Return value True if all parameters are valid exclusive and achievable otherwise false Category 2C Reference R_CGC_Set R_IIC_Set Remarks e Function R_CGC_Set must be called with the current clock source selected before using this function Function R_IIC_Set must be called before any use of this function This function configures each I C pin that is required for operation It also disables the alternative modes on those pins e The 7 or 10 bit slave addresses should use the format b15 b8 b7 b1 bO 7 7 bit address b15 b11 b10 b1 bO 10 bit address The timing limits depend on the frequency of the internal reference clock IRC 1 tse t an UCBRH Ite CBRL It re The maximum transfer rate is given when ICBRH ICBRL 0 the minimum when ICBRH ICBRL 31 Transfer _ rate The absolute limits with zero rise and fall times are fpcikp MHz firc 50 48 12 5 12 32 8 f 1 781 kbps to 750 kbps to 195 kbps to 187 5 kbps to 500 kbps to 125 kbps to verre 25 0 Mbps 24 0 Mbps 6 25 Mbps 6 0 Mbps 16 0 Mbps 4 00 Mbps fPcLke 2 391 kbps to 375 kbps to 97 7 kbps to 93 75 kbps to 250 kbps to 62 5 kbps to 12 5 Mbps 12 0 Mbps 3 13 Mbps 3 0 Mbps 8 00 Mbps
88. 01 2014 2 ENESAS RX220 Group 4 Library Reference Serial Peripheral Interface 1 R_IIC_Set Configure the 12C pin selection 2 R_IIC_Create l2C channel setup 3 R_IIC_Destroy Disable an 2C channel 4 R_IIC_MasterSend Write data to a slave device 5 R_IIC_MasterReceive Read data from a slave device 2C bus interface 6 R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process 7 R_IIC_SlaveMonitor Monitor the bus and receive data from a master 8 R_IIC_SlaveSend Write data to a master device 9 R_IIC_Control lC channel control 10 R_IIC_GetStatus Read the status for an I2C channel 1 R_SPI_Set Configure the SPI pin selection 2 R_SPI_Create Configure an SPI channel R_SPI_Destroy Shutdown an SPI channel R_SPIl_Command Configure an SPI command R_SPI_Transfer Transfer data over an SPI channel R_SPI_Control Control an SPI channel R_SPI_GetStatus Check the status of an SPI channel CRC calculator R_CRC_Create Configure the CRC calculator R_CRC_Destroy Shut down the CRC calculator 12 bit Analog to Digital converter R_CRC_Write Write data into the CRC calculation register R_CRC_Read Read the CRC calculation result R_ADC_12_ Set Select the I O pins for the 12 bit ADC R_ADC_ 12 CreateUnit Configure the 12 bit ADC unit R_ADC_12 CreateChannel Configure 12 bit ADC analog c
89. 1 4 8 or 32 e Limit value calculation PDL_CAC_LIMIT_TOLERANCE or PDL_CAC_LIMIT_REGISTER Parameters data4 and data5 will contain either the tolerance or the limit register values Page 102 of 429 RX220 Group Description 2 2 Return value 4 Library Reference data2 Choose the CACREF input settings Use to separate each selection If the CACREF input is not required specify PDL_NO_DATA e External input configuration PDL_CAC_CACREF_PORT_A 0 or Select the pin to be used for signal CACREF PDL_CAC_CACREF_PORT_C 7 or Parameter data3 contains the frequency of PDL_CAC_CACREF_PORT_H_0 the signal applied to this pin PDL_CAC_CACREF_FILTER_DISABLE or PDL_CAC_CACREF_FILTER_DIV_1 or PDL_CAC_CACREF_FILTER_DIV_4 or PDL_CAC_CACREF_FILTER_DIV_16 If used the CACREF signal can be unfiltered or sampled using the clock to be measured divided by 1 4 or 16 data3 If the CACREF input will be used specify the input clock frequency in Hz Use PDL_NO_DATA if not required data4 Specify either a the maximum positive deviation for the measured clock as a percentage or b the upper count limit for the measured clock where the maximum value is 65535 data5 Specify either a the maximum negative deviation for the measured clock as a percentage or b the lower count limit for the measured clock where the maximum value is 65535
90. 1 11 REN ESAS Page 91 of 429 RX220 Group 4 Library Reference 4 2 5 MCU operation 1 R_MCU _Conirol Synopsis Prototype Description Control the operation of the MCU bool R_MCU_Control uint8_tdata Control options Modify the MCU control registers data Select the operation states All selections are optional If multiple selections are required use to separate each selection e Software reset control PDL_MCU_RESET_START Start a software reset of the MCU PDL_MCU_WARM_START Set the Start type status flag to Warm True if a valid register is specified otherwise false Program example e Start type flag control Return value Category MCU registers References R_CGC_Set R_RTC_Create Remarks The PDL_MCU_WARM_START is used after the initialization of cold start caused by a power on reset has completed This is to indicate the next reset processing is warm start Caused by a reset signal during operation RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void Reset the MCU R_MCU_Control PDL_MCU_RESET_START R01US0059EG0111 Rev 1 11 REN ESAS Page 92 of 429 Aug 01 2014 RX220 Group 4 Library Reference 2 R_MCU_GetStatus Synopsis Read the MCU status Pro
91. 256 Clock division ratio selection The IWDTCLK clock 1 16 32 64 128 or 256 Time out control PDL_IWDT_TIMEOUT_NMI or PDL_IWDT_TIMEOUT_RESET If the IWDT times out select if a Reset or an NMI Interrupt will be generated Window Start Position PDL_IWDT_WIN_START_25 or PDL_IWDT_WIN_START_50 or PDL_IWDT_WIN_START_75 or PDL_IWDT_WIN_START_100 start position e Window End Position The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window PDL_IWDT_WIN_END_0 or PDL_IWDT_WIN_END_ 25 or PDL_IWDT_WIN_END_50 or PDL_IWDT_WIN END 75 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Hence specifying 0 is equivalent to no window end position e Sleep Mode Count Stop PDL_IWDT_STOP_DISABLE or PDL_IWDT_STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode or all module clock stop mode Return value True if all parameters are valid and exclusive otherwise false Category Independent Watchdog Timer Reference R_MCU_OFS R_CGC_Set R_CGC_Control R_INTC_CreateExtInterrupt Remarks e If using the Initial Setting Memory using R MCU_OFS to enable the IWDT
92. 5 Portpin PE PDL IO PORT 3 4 Portpin P34 PDL_IO PORT E 6 Portpin PEs PDL_IO PORT 35 PortpinP3s PDL_IO PORT B_0 Portpin PBo PDL_IO PORT E 7 Portpin PE7 PDL IO PORT 3 6 PortpinP3 PDL IO PORT B1 Portpin PB PDL IO PORT 3 7 PortpinP37 PDL IO PORT B 2 PortpinPB gt PDL_IO PORT HO Portpin PHo PDL IO PORT B 3 Portpin PB PDL IO PORT H 1 Portpin PH PDL_IO PORT B 4 Portpin PB PDL_IO PORTH 2 Portpin PH gt PDL_IO PORT B 5 Portpin PBs PDL_IO_PORT_H 3 Portpin PHs PDL_IO PORT B 6 Port pin PBe PDL IO PORT B 7 PortpinPB7 PDL_IO PORT J 1 Portpin PJ PDL IO PORT J 3 Portpin PJs Note Refer to the hardware manual for the port pins which are available on the device that you have selected R01US0059EG0111 Rev 1 11 Page 75 of 429 Aug 01 2014 RENESAS RX220 Group 1 Synopsis Prototype Description Return value Category References Remarks RO1US0059EG0111 Aug 01 2014 4 Library Reference R_lO_PORT_Set Configure an I O port bool R_IO_PORT_Set uint16_t data1 Port pin selection uint16_tdata2 Configuration Set the operating conditions for I O port pins data1 Select the port pins to be configured from 4 2 3 Do not use any whole port definitions Multiple pins on the same port may be specified using to separate each pin data2 Choose the pin settings Use
93. Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system eval
94. Alarm in another 10 seconds DATA DATA Error Adjust DATA Periodic p p H E yuurtuouvyul else If Cold start is detected the RTC clock should be re started R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA r nRTC Start in Cold start mode Initailize RTC r n 0 PDL_NO_FUNC if R_RTC_Create PDL_RTC_ALARM_ TIME ENABLE PDL_RTC_ALARM DATE _ENABL OxFF114250 Automatic day of week 11 42 50 0x20131118 18 Nov 2013 PDL_NO_DATA Periodic OxFF114300 Alarm in 10 seconds 0x20131118 18 Nov 2013 Alarm_handler 15 PDL_NO_FUNC PDL_NO_DATA false R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA r nRTC_Create error in Cold start mode r n 0 PDL_NO_FUNC while 1l After the complete initialization Set the warm start indicator R01US0059EG0111 Rev 1 11 Page 359 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples R_MCU_Controli PDL_MCU_WARM_START de This call should cancel the settings made in above call to R_LPC_Create R_LPC_Create PDL_LPC_MIDDLE_SPEED_MODE_B PDL_NO_DATA L_NO_DATA L_NO_DATA R_RTC_Read PDL_RTC_READ_CURR PDL_NO_PTR amp time amp date Enter sleep mode after alarm in 10sec whil bEnterSleepMode false Enter sleep mode A
95. Controller usage with a single block transfer Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve 16 bytes for the IRQl triggered transfer data area uint32_t dtc_irgl_transfer_data 4 Data source and destination declarations const char source_string_1 Renesas RX220 volatile uint8_t destination_string_1 Callback function prototype void IRQ1_ handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Enable control of R_IO_PORT_Set DG IO PORT 1_5 DL_IO_PORT_OUTPU t the DTC options Set DL_NO_DATA tce_vector_table Configure the DTC for IRQ1 R_DTC_Create PDL_DTC_BLOCK PDL_DTC_DESTINATION PDL_DTC_SOURCE_ADDRESS_ PLUS PDL _DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_IRQ_COMPLETE PDL_DTC_TRIGGER_IRQ1 dtc_irgl_transfer_data source_string_l destination_string_l 1 uint8_t strlen char source_string_1 Set IRQ pin to P31 R_INTC_SetExtInterru
96. DTC example Using chain transfer Transfer 1 is triggered by a software interrupt and copies data from ROM into RAM On completion of transfer 1 transfer 2 is started On completion of transfer 2 transfer 3 is started Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve three contiguous groups of 16 bytes full address mode for the transfer data areas uint32_t dtc_sw_transfer_data 4 3 const char source_string_1 Renesas RX220 const char source_string_2 DTC example const char source_string_3 using chain transfer volatile char destination string 1 Tires irea tae woe ees We volatile char destination_string_2 ewcccacaac cece weee seen t ae Ws volatile ghar destination string 3f Mews esse sdp da wise oes Mo volatile uint8_t transfer_complete void main void Enable software interrupts R_INTC_CreateSoftwareInterrupt PDL_INTC_DTC_SW_TRIGGER_ENABLE PDL_NO_FUNC 0 Configure the controller R_DTC_Set PDL_DTC_ADDRESS_FULL R01US0059EG0111 Rev 1 11 Page 335 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples
97. Driver 2 21 Independent Watchdog Timer Driver The driver functions support the use of the independent watchdog timer providing the following operations 1 Configuring the timer for use 2 Refreshing the timer to prevent the reset operation 3 Reading the timer status and counter register R01US0059EG0111 Rev 1 11 Page 38 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 22 Serial Communication Interface Driver The driver functions support the use of the serial communication SCI channels providing the following operations 1 Selection of the SCI pins for use 2 Configuration for use including Automatic baud rate clock calculations Automatic interrupt control Automatic I O pin configuration Supporting the following modes o Asynchronous Multi Processor Clock Synchronous Smart Card Interface Simple IIC Simple SPI O O O 0 O 3 Disabling channels that are no longer required 4 Transmitting data with polling or interrupt mode automatically selected 5 Receiving data with polling or interrupt mode automatically selected 6 Transmitting and or receiving data in SPI mode with polling or interrupt mode automatically selected 7 Transmitting data in simple IIC mode with polling or interrupt mode automatically selected 8 Receiving data in simple IIC mode with polling or interrupt mode automatically selected 9 Transmitting the last byte of data in simple IIC mode 10 Control the channel operati
98. E T av gates Pat ates a andes wd 127 FAD ERE EE o S E A E E ET AA A E EA A AT 130 Data Transfer COo Of aeaa r aaa ea a aaa a a e aaa AEE a e an aa eE ARANA EEEn aaay 132 RAAE EE EE ETT A E AAEE 132 PRE OTC Create n e eaaa a A E vd atta AR e EE AE EE A EREA aa 133 ADIKON BEKON E AA E A A A A E AT 136 DALEN TELE LA AT A E EA ITT 137 RMD EG GEASS a e s aeea EEan E AEE E thes AaS AE LAEE F AEN AREPA E NSA A naik 139 Event a egia E APEE AEE ATE E A T O EEA O AS 141 RASKERE T ATE EEA A E EAT 141 RELO DoS MOV onrera s a n E ARAE EE aE EEA E AE AA EEE a TEE SASEA Eeay 142 TARO aiT o EARE A EAA R A T A AT 143 RARAN E EE E A EAE EA E A AE A A E ETAS 144 REL Control ono a aA E tenet thas 145 Multi Function Timer Pulse Uniit ccccccsssesesesesesesesssessseseeeseesseesseesseeeeeeeesseseesesaeesseeeees 151 RMU 2 Se aaa teak a ove hel sath oak a A a ha ee Za 151 PREM TU2 GOIE AR OEE A A EA 154 PREM TUZ DOSWOV aieia ra E AEE A ee eee aad 164 R_MTU2_ControlChannnel eeraa R EEEE AARE RKE EEEE EEEE A 165 PEMTUZ COMTO oesi e a E A E A 168 R_MTU2_ R adChanel as a a a a aaa a aaa a aetate aa a a 173 RMTU2 Read UNI a a a a sect a a aaa tha eek a io ee eee 176 Port OutputEnable mynnent na a eee ate a see Me a aae a eat at 177 Re ROBE SC AEA sree eta teac oc AE fa E ath oh oak ees ha EAE 177 Ri ROE Creates ax EAE EEE peek aE SUS ore teks Bbc peek el REA Sot io Beal aa oa 179 R2POE2GControll coreene nina a enaa a a a Mae hail pene ei it a Maes
99. GSI COM N E ATE aac TE sass cates avs E E dav oe ta anaes TE A E 259 TI RES Cl GOtSLats sa aa aa E A EEE A A ese te SAn A AEAEE eraen tess te Aa aria 261 0 B2 RER e E e VERAI O E E EEA EAEE N E A E EET 263 T RIG o eea a T A 263 2 REE H ET E E EE A E E E A A A A EAE 264 CD AMRA m Sa E BIERO I E E A E T E A A 268 4 RuG M ster Send a a eek eke aaa a aaa aaa eek aT a iare ee a 269 5 RYC Master ROCO NO a a aa aaa a a eens a aaa aaa Mesa a io eee ah 271 6 RoIG Mast rRec ivelaSt indiaidh aa aa a a aanta ied aitekin 273 7 RGC Slave MON O raa a a a aa is Bla 2 aa Bua eee ee ees 274 8 RUllG SlaveSend RARE TEA E AE A T EE E EA 276 Oy e EE e A E E T E E E E E A E ahd 277 10y RING Geia ana a a EE E A 278 4 2 22 Serial Peripheral Interface 0 ccscceesceceeeeeeeeeeeeeeeeeeeeeeeaeeeenaeseeeeeceaeeseaesseaaesgeeeseaeeesaesseneeesaees 280 Ti ROPE eaa a a a A Gaga dtaceh te baw esate Oath aad 280 2 RASPI Orea a saad a eshte sia a are esata a aAa eee ae 281 3 RSP DESMO a isles cert ater a a ac ANAL a aa ae a ae e Tea aai 284 4 RSP Command di na ietie ieee a NE eased Mae el et ae 285 5 RSP iransferi snra a a Rael T A nie aie Ea 287 6 RSP Control amar ein a ees ee eee eee I ee 289 7 RSP GetStatus aimn eda a e ata Peed Bae ee ae I ee es 291 4 2 23 CRC calculator at Senn elit aed eeu eons ei ie dene ee 292 1 RiGRG Createssncrsnctd es wisievehaed e ea ee ae es 292 2 R CRG Destroy sncunvsiceiee alee AAA een tava a ee 293 3 RICRCUW r
100. Handle Error Figure 40 Example of SCI in IIC mode R01US0059EG0111 Rev 1 11 Page 385 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 10 SCl in IIC Mode using DMAC This shows the setting of SCI channel 9 in to IIC mode and then a write to an IIC EEPROM using the DMAC PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h static void Callback void SCI IIC Channel define CHANNEL SCI_IIC 9 TIC Slave address of EEPROM define SLAVE_ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 volatile bool data_sent false void main void Data Buffer volatile uint8_t IIC_Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Set Channel 9 pin options R_SCI_Set CHANNEL SCI_IIC PDL_SCI_PIN_SCI9_RXD9_PB6 PDL_SCI_PIN_SCI9_TXD9_PB7 Configure the SCI IIC Channel R_SCI_Create CHANNEL _SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 Setup date to write to EEPROM Address in EEPROM TIC_Buffer 0 EEPROM_ADDRESS Data to store in EEPROM IIc_Buffer 1
101. Ox55AA PDL_NO_FUNC 0 Rev 1 11 REN ESAS Page 208 of 429 RX220 Group 2 Synopsis Prototype Description Return value 4 Library Reference R_CMT_CreateOneShot Configure a CMT channel as a one shot event bool R_CMT_CreateOneShot uint8_t data1 Timer channel selection uint16_t data2 Configuration selection double data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Control the CPU during the one shot operation PDL_CMT_CPU_ONor _ Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts PDTOMT_GPU_DEF The CPU will re start when any valid interrupt occurs DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends If you specify PDL_NO_FUNCG this function will wait for the timer to complete before returning You should always
102. PDL_INTC_VECTOR_TCIU1 Multi function Timer Pulse Unit channel 1 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR_TGIA2 PDL_INTC_VECTOR_TGIB2 PDL_INTC_VECTOR_TCIV2 PDL_INTC_VECTOR_TCIU2 Multi function Timer Pulse Unit channel 2 Compare match or Input capture A Compare match or Input capture B Overflow Underflow RO1US0059EG0111 Aug 01 2014 Rev 1 11 2 ENESAS Page 62 of 429 RX220 Group 4 Library Reference Description 2 2 PDL_INTC_VECTOR_TGIA3 PDL_INTC_VECTOR_TGIB3 PDL_INTC_VECTOR_TGID3 PDL_INTC_VECTOR_TGIC3 PDL_INTC_VECTOR_TCIV3 Multi function Timer Pulse Unit channel 3 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR_TGIA4 PDL_INTC_VECTOR_TGIB4 PDL_INTC_VECTOR_TGIC4 PDL_INTC_VECTOR_TGID4 PDL_INTC_VECTOR_TCIV4 Multi function Timer Pulse Unit channel 4 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR_TGIU5 PDL_INTC_VECTOR_TGIV5 Multi function Timer Pulse Unit Compare match or Input capture U Compare match or Input capture V
103. PDL_MCU_OFS_IWDT STOP_DISABLE or PDL_MCU_OFS_IWDT STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode or all module clock stop mode 2tENESAS Page 95 of 429 RX220 Group Description 2 2 Category References Remarks Program example 4 Library Reference data2 Select the post reset LVD configuration settings e Auto start control PDL_MCU_OFS_LVD_0_DISABLE or Disable or enable the Voltage monitor 0 auto start PDL_MCU_OFS _LVD_0 ENABLE mode If auto start mode is enabled select one setting from the following e Voltage threshold selection PDL_MCU_OFS_LVD_0_ 380 or PDL_MCU_OFS_LVD_0_ 280 or Select 3 80V 2 80V 1 90V or 1 72V as the voltage PDL_MCU_OFS_LVD_0_190 or monitor 0 detection level PDL_MCU_OFS LVD_0 172 data3 Select the post reset CGC configuration settings e Auto start control PDL_MCU_OFS_CGC_HOCO_DISABLE or PDL_MCU_OFS_CGC_HOCO_ENABLE Disable or enable the HOCO after a reset MCU registers R_IWDT_Set R_CGC_ Set e This is a macro not a function call There is no error checking or return value e The auto start setting for each parameter must be selected RPDL definitions include r_pdl_mcu_ofs h E
104. PDL_POE_1 MODE_LOW_16 or PDL_POE_1 MODE_LOW_128 PDL POE 2 PDL POE 2 MODE_EDGE or MODE_LOW 8 or PDL_POE_2 MODE_LOW_16 or PDL_POE_2 MODE_LOW_128 PDL_POE_3_ PDL_POE_3 MODE_EDGE or MODE_LOW_8 or PDL_POE_3 MODE_LOW_16 or PDL_POE_3 MODE_LOW_128 PDL_POE_8 MODE_EDGE or For each pin POEO to POE3 and POE8 select falling edge or low level for 16 samples at PCLKB 8 16 or 128 PDL_POE_8_MODE_LOW_8 or PDL_POE_8 MODE_LOW_16 or PDL_POE_8 MODE _LOW_128 data2 Allocate the pins for signals POEO to POE3 and POE8 If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required PDL_POE_0 PORT_C 4 or i PDL POE 0 PORT D 7 Pin POEO input selection PDL_POE_1_PORT_B _5or PDL POE 1 PORT D 6 Pin POE1 input selection PDL_POE_2 PORT_3 4or PDL_POE_2 PORT_A 6or Pin POE2 input selection PDL POE 2 PORT D 5 PDL_POE_3_PORT_3_3 or PDL_POE_3 PORT_B 3or Pin POE3 input selection PDL_POE_3 PORT D 4 PDL_POE_8 PORT_1_7 or PDL_POE_8 PORT_3 Oor PDL POE 8 PORT D 3or Pin POE8 input selection PDL POE 8 PORT E 3 Reval A RENESAS Page 177 of 429 RX220 Group 4 Library Reference Description 2 2 data3 Configure pin output control If multiple selections are required use
105. PDL_SCI_CYCLE_BIT_8 Select 16 or 8 base clock cycles for one bit period e CKS selection required if the on chip baud rate generator is selected as the data clock source PDL_SCI_PCLK_DIV_1 or PDL_SCI_PCLK_DIV_4 or Select the internal clock signal PCLKB 1 4 16 or 64 as PDL_SCI_PCLK_DIV_16 or the baud rate generator clock source PDL_SCI_PCLK_DIV_64 e BRR setting required if the on chip baud rate generator is selected as the data clock source The BRR register value between 0 and 255 data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter may be zero if the following functions will not be used with a callback function R_SCI_Send R_SCI_ Receive R_SCI_SPI_ Transfer R_SCI_IIC_Write and R_SCI_IIC_Read True if all parameters are valid exclusive and achievable otherwise false Category SCI Reference R_CGC_Set R_SCI_Set R_SCl_Send R_SCI_ Receive R_SCI_ Control RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 242 of 429 RX220 Group 4 Library Reference Remarks Function R_CGC_Set must be called with the current clock source selected before using this function Function R_SCI_ Set must be called before any use of this function if using SCI channels 1 5 or 6 This function configures each SCI pin that is required for operation It also disables the a
106. PDL_SCI_PIN_SCI1_RXD1_P30 PDL_SCI_PIN_SCI1_TXD1_P26 Set up SCI channel 1 Async 8N1 38400 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 Send message register callback to say when sent R_SCI_Send 1 PDL_NO_DATA r nHello Type 5 characters and I will echo them back r n 0 SCItx Wait for message to be sent while false data_sent Start a pending read of 5 characters R_SCI_Receive 1 PDL_NO_DATA rx_buffer 5 SCIrx PDL_NO_FUNC Wait for characters to be received while false data_received R01US0059EG0111 Rev 1 11 Page 371 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Echo the 5 characters back R_SCI_Send 1 PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC Callback function for Rx void SCIrx void data_received true Callback function for Tx void SCItx void data_sent true Figure 33 Example of SCI Asynchronous operation using interrupts R01US0059EG0111 Rev 1 11 Page 372 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 3 SCI Asynchronous Using DMAC This shows the setting of SCI channel 1 and transmission of data using the DMAC Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h
107. PDL_SPI_MODE_SYNC_MASTER L_SPI_FRAME 1 4 __NO_DATA E6 Configure the Master R_SPI_Command MASTER_CHANNEL 0 PDL_SPI_CLOCK_MOD PDL_SPI_LENGTH_32 PDL_SPI_LSB_FIRST PDL_NO_DATA i master_transfer_complete false Transfer all t data once R_SPI_Transfer MASTER_CHANNEL PDL_NO_DATA master_tx_data master_rx_data 1 spi_master_callback 15 while master_transfer_complete false for i 0 i lt 4 i Did the Master input match the Slave output if master_rx_data i slave_tx_data i Handle the error while 1 while 1 void spi_master_callback void uintl6_t StatusValue 0 uintl6_t Sequence_count Read the master channel status R_SPI_Get Status MASTER_CHANNEL amp StatusValue amp Sequence_count No errors if StatusValue amp 0x000Du 0x0u master_transfer_complete true R01US0059EG0111 Rev 1 11 Page 407 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples else Handle the error while 1 Figure 51 Example of Serial Peripheral Interface Transfer of 32 bit Data by Master R01US0059EG0111 Rev 1 11 Page 408 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Figure 52 shows how four 32 bit words are transmitted and received simultaneously by the slave The received data is then checked to confir
108. Power Consumption control Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_lpc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h static void SWl_handler void void main void Set Switchl SW1 interrupt R_INTC_SetExtInterrupt PDL_INTC_IRQ1_P31 Enable the switch SW1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ1 PDL_INTC_FALLING SWl_handler T5 Select the default options R_LPC_Create PDL_NO_DATA PDL_NO_DATA PDL_NO DATA PDL_NO_DATA Enter software standby mode R_LPC_Control PDL _LPC_MODE_SOFTWARE_STANDBY Normal execution will resume after switch SW1 is pressed while 1 static void SWl_handler void Figure 10 Example of Software Standby Mode R01US0059EG0111 Rev 1 11 Page 328 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 8 Register Write Protection The following example shows the use of Register Write Protection PDL functions and definitions include r_pdl_cgc h include r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t prer uint8_t pwpr Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Turn off all register write protection
109. R_CPA_Create 4 Library Reference Synopsis Prototype Description Return value Category RO1US0059EG0111 Aug 01 2014 Rev 1 11 Configure the Comparator A module bool R_CPA_Create uint8_t data1 uint16_t data2 void func uint8_t data3 Comparator A channel selection Configuration for Comparator A Callback function pointer for Comparator A Interrupt priority Set up Comparator A enable the interrupt register and callback functions data1 The comparator A channel number n where n 0 to 1 data2 Configure the Comparator A channel To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Operation PDL_CPA_MONITOR_ONLY or PDL_CPA_INTERRUPT_RESET_ENABLE Select no action for monitor only enable interrupt reset for comparator A e Digital filter PDL_CPA_FILTER_DISABLE or PDL_CPA_FILTER_LOCO_DIV_1 or PDL_CPA_FILTER_LOCO_DIV_2 or PDL_CPA_FILTER_LOCO_DIV_4 or PDL_CPA_FILTER_LOCO_DIV_8 Configure the digital filter for comparator A Mode Select Not valid for monitor only operation selected PDL_CPA_MODE_SELECT_INTERRUPT or PDL_CPA_MODE_SELECT_RESET Select mode for comparator A Reset negation Select Valid for reset mode selected PDL_CPA_NEGATION_AFTER_RESET or PDL_CPA_NEGATION_AF
110. R_MTU2_Create_structure create_parameters R_MTU2_ControlChannel_structure control_parameter void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set channel 3 output pins MTIOC3B MTIOC3D R_MTU2_Set 3 PDL_MTU2_PIN_3B_ P17 PDL _MTU2_PIN_3D_P16 Set channel 4 output pins MTIOC4A MTIOC4C MTIOC4B MTIOC4D R_MTU2_Set 4 PDI TU2_PIN_4A PE2 PDL_MTU2_PIN_4C_PE1 PDI U2_PIN_4B PC2 PDL_MTU2_PIN_4D_PC3 Load the defaults R_MTU2_Create_load_defaults amp create_parameters Set the non default options create_parameters channel_mode PDL_MTU2_MODE_NORMAL create_parameters TGRA_TCNTV_value 30000 create_parameters TGRB_TCNTW_value 20000 R_MTU2_Create 4 amp create_ parameters i Load the defaults R_MTU2_Create_load_defaults amp create_parameters Set the non default options create_parameters channel_mode PDL_MTU2_MODE_PWM_RS create_parameters counter_operation PDL_MTU2_CLK_PCLK_DIV_64 PDL_MTU2_CLEAR_TGRA create_parameters TGRA_TCNTV_value 48000 TGRA create_parameters TGRB_TCNTW_value 35000 TGRB R_MTU2_Create 3 amp create_parameters control_unit_para simultaneous_control control_unit_para buffer_control 0 control_unit_para brushless_DC_
111. Reference Description 2 2 Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 data3 The IRQn interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func This value does not apply to the NMI and is ignored True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_SetExtInterrupt Function R_INTC_SetExtInterrupt must be called before any use of this function e The selected interrupt is enabled automatically Please see the notes on callback function use in 6 e The NMI callback function should not return It should stop operation or reset the system e Ifthe NMI interrupt fails to initialise this function will return false RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function void CallBackFunc void void func void Configure the IRQ1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IROQ1 PDL_INTC_FALLING CallBackFunc 7 Configure the NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING CallBackFunc 15 Configure the NMI triggered by the IWDT only no NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INT
112. Reference R_DTC_GetStatus R_DMAC_GetStatus Remarks The flags are not modified by this function The event detection flags are cleared as required by the driver for correct operation The transfer count values are cleared when a new transfer is started e If using the DTC or DMAC to transfer data the transfer count values will not be valid The R_DTC_GetStatus or RLDMAC_GetStatus functions can be used to calculate the transfer count Note If the DTC DMAC transfer does not fully complete then the count reported by the DTC DMAC for a slave transmission will be one greater than the actual number of bytes read by the master Transmit mode is set when the master has started a master read transfer RO1US0059EG0111 Page 278 of 429 Aug 01 2014 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t status_flags uintl6_t tx_count Read the status of channel 0 R_IIC_GetStatus 0 amp status_flags amp tx_count PDL_NO_PTR R01US0059EG0111 Rev 1 11 Page 279 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 2 22 Serial Peripheral Interface 1 R_SPI Set Synopsis Configure the SPI pin selection Prototype bool R_SPI_Set uint32_t data Pin selection Description Set up the global SPI options
113. Register ODR1 Register ODRO True if all parameters are valid and exclusive otherwise false Category I O port References None Remarks Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver Create functions Take care to not overwrite existing settings e Pin P35 is fixed as an input and cannot be modified RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 80 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO PORT 1 PDL_IO_ PORT DIRECTION PDL_IO _PORT_OR Ox0F Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_IO_PORT A 3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR 1 R01US0059EG0111 Rev 1 11 Page 81 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 RIO PORT Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read data from an I O port bool R_IO_PORT_Read uint16_tdata1 Port or port pin selection uint8_t data2 Pointer to the variable in which the value shall be stored
114. SPI channel data Select channel SPIn where n 0 only Return value True if all parameters are valid otherwise false Category SPI Reference None Remarks e The SPI channel is put into the power down state Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SPI channel 0 R_SPI_Destroy 0 R01US0059EG0111 Rev 1 11 Page 284 of 429 Aug 01 2014 RENESAS RX220 Group 4 Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 Rev 1 11 R_SPI_Command Configure an SPI command bool R_SPIl_Command uint8_t data1 uint8_t data2 uint32_t data3 uint8_t data4 Select the options for a command data1 4 Library Reference Channel selection Command selection Command options Extended timing control Select channel SPIn where n 0 only data2 Select command n where n 0 to 7 data3 Select the command options If multiple selections are required use to separate each selection The default settings are shown in bold Clock phase and polarity Idle clock Data sampling edge PDL_SPI_CLOCK_MODE_0 or Low Rising PDL_SPI_CLOCK_MODE_1 or Falling PDL_SPI_CLOCK_MODE 2 or High Rising PDL_SPI_CLOCK_MODE_3 g Falling e Clock di
115. Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid and exclusive otherwise false Real time clock R_CGC_ Set R_CGC_Control e The function is called only at warm start up e This function is not required when using 48 pin package RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void alarm_function void void func void Reconfigure RTC intterupt R_RTC_CreateWarm alarm_function TS PDL_NO_FUNC PDL_NO_DATA Rev 1 11 REN ESAS Page 231 of 429 RX220 Group 4 Library Reference 4 2 19 Independent Watchdog Timer 1 R_IWDT_Set Synopsis Prototype Description Configure the Independent Watchdog operation bool R_IWDT_Sei uint32_t data Configuration selection Select the operation of the Independent Watchdog timer and start it data Configure the timer options Use to separate each value Counter selection PDL_IWDT_TIMEOUT_1024 or PDL_IWDT_TIMEOUT_4096 or PDL_IWDT_TIMEOUT_8192 or PDL_IWDT_TIMEOUT_16384 The number of cycles of the selected clock before the reset occurs PDL_IWDT_CLOCK_OCO_1 or PDL_IWDT_CLOCK_OCO_16 or PDL_IWDT_CLOCK_OCO_32 or PDL_IWDT_CLOCK_OCO_64 or PDL_IWDT_CLOCK_OCO_ 128 or PDL_IWDT_CLOCK_OCO_
116. True if all parameters are valid and exclusive and a selected clock source has been configured otherwise false Clock generation circuit CGC_Set R_LPC_GetStatus R_LPC_Create Remarks Program example RO1US0059EG0111 Aug 01 2014 include include Use R_CGC_Set to configure a clock source before calling this function While the main clock Oscillation Stop Detection feature is enabled the LOCO is started and cannot be stopped Clearing the main clock Oscillation Stop Detection flag will not succeed until a clock source other than the main oscillator is selected using parameter data1 If the main clock Oscillation Stop Detection flag is cleared the interrupt output is also disabled Use this function to re enable the interrupt output after the main clock oscillation has been restored Do not stop a clock that is in use Do not change the clock source if an Operating Power Control Mode transition is taking place see R_LPC_GetStatus If low speed operating mode 2 is selected see R_LPC_Create disable the HOCO If middle speed operating modes 1 or 2 are selected seeR_LPC_Create do not change the HOCO power state If the main clock oscillator pins will be used as general 1 O call this function with PDL_CGC_MAIN_DISABLE and PDL_CGC_MAIN_FORCED_DISABLE selected in parameter data2 If this function is used to enable a clock oscillator wait for the required settling time before
117. Turn on LEDO and LED1 R01US0059EG0111 Rev 1 11 Page 345 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples R_IO_PORT_Write PDL_IO_POR R_IO_PORT_Write PDL_IO_POR T Configure CMT channel 0 for 1kHz operation but not start CMT first R_CMT_Create 0 PDL_CMT_FREQUENCY PDL_CMT_STOP 1E3 CMTO_handler 7 Configure CMT channel 1 at 0 1 second period and start CMT R_CMT_Create 1 PDL_CMT_PERIOD 1E 1 CMT1l_handler 7 Change CMT channel 0 configuration frequency to 5Hz R_CMT_Control 0 PDL_CMT_FREQUENCY 5E0 Read flag and count value T_Read 0 PDL_NO_PTR PDL_NO_PTR MT_Read 1l amp flags amp counter R_C R_C Wait for 1s R_CMT_CreateOneShot 2 PDL_NO_DATA 1E0 PDL_NO_FUNC 0 Start CMT channel O R_CMT Control 0 PDL CMT START PDL _NO DATA Stop CMT channel 1 R_CMT Control 1 PDL CMT STOP PDL _NO DATA Wait for 1s R_CMT_CreateOneShot 2 PDL_NO_DATA 1E0 PDL_NO_FUNC 0 Destroy CMT unit 0 channel 0 and 1 R_CMT_Destroy 0 Main loop while 1 void CMTO_handler void Toggle LEDO R_IO_PORT_Modify PDL_IO_PORT_1_4 PDL_IO_PORT_XOR 1 void CMT1_handler void Toggle LEDI R_IO_PORT_Modify PDL_IO_PORT_1_5 PDL_IO_PORT_XOR 1 Figure 22 Example of Compare Mat
118. a ee a 337 S12 Event Link Controle iana a S aa A A A aa 338 5 13 Multi Function Timer Pulse Unit ccccecccececeeeeeeeceeeeeeeeeeceeeeeeaaeeeeeeeseeeeeseaeeeeaaeseeeeeseaeeesaeeseaeeseeeees 339 SISA PWM MOde IS on a EA a A a 339 5 13 2 Reset synchronized PWM mode eeecceeeeeneceeeenneeeeeeaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeenaeeeeneaas 341 S E o 1an RTA aE E E A E ETT 343 SAAT FPerodie opatatOn aranera iane a E AAAA AEE SA T eee tea eee 343 5 15 Compare Match TIMer mues a ue esaea aina aa iaaea aaia daaa AA Aea E EAEan aa AAE oaia naa ia MAKEAA 345 5 16 Realtime Clock ccisiisscccsisssececszaseczeaasscccatassecevaasceceazasseezeaassceazasceseatassaseaaassacaaaaacaaeeaacsesaazassaaeazassaeaaas 5 347 5 16 1 Use case of RTC configuration and use CaSe cceceeeseeceeeeeeeeeeeaeeeeaeeseeeeeeaeeesaeeseneeees 5 347 1 Configuration CGC and RTC counting by sub clock only RTC count source in calendar count mode 5 347 2 Configuration CGC and RTC counting by sub clock only RTC count source in binary count mode 5 349 3 Configuration CGC and RTC counting by sub clock both RTC count source and System clock in calendar COU Od E choad Taa Aarra aa a aa r ea a a a aa n ae a aei a aeai aAa 5 351 4 Configuration CGC and RTC counting by sub clock both RTC count source and System clock in pinar COUNT modes a eree Ea EERE e E EAE ASEE A AEREN a EREA TAE SEAE EE A EEEE den R ANEREN TE EIS 5 353 5 16 2 Initializ
119. bus data bus and chip select pins and handling any bus errors 11 DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 12 Data Transfer Controller These driver functions are used for configuring and controlling the transfer of data triggered by peripheral interrupts 13 Event Link Controller These driver functions are used for configuring and controlling the event links 14 Multi Function Timer Pulse Unit These driver functions are used for configuring and controlling the multi function timers 15 Port Output Enable These driver functions are used for additional configuring and controlling of the timer outputs 16 8 bit Timer These driver functions are used for configuring and controlling the timers 17 Compare Match Timer These driver functions are used for configuring and controlling the timers R01US0059EG0111 Rev 1 11 Page 18 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 18 Real time Clock These driver functions are used for configuring and controlling the real time clock timer 19 Independent Watchdog Timer These driver functions are used for configuring and controlling the timer 20 Serial Communication Interface These driver functions are used to configure the serial channels and manage the transmission and or reception of data across them 21 2C Bus Interface These driver functions are used for controlling
120. clock Reference R_RTC_Create RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 227 of 429 RX220 Group 4 Library Reference Remarks Program example e This function is not available in Binary count mode Call R_RTC_Create or R_RTC_CreateWarm first before using this function e If an interrupt request flag is set to 1 it shall be automatically cleared to 0 by this function e Refer to R_RTC_Create for the time and date formats e If the Carry flag is read as 1 the current time and date were updated during the read process and should be re read e The year returned will be in the range 0 to 99 The hundreds and thousands units are not stored e This function is not required when using 48 pin package RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint32_t CurrentTime void func void Read the current time and flags R_RTC_Read PDL_RTC_READ CURRENT amp Flags amp CurrentTime PDL_NO_PTR RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 228 of 429 RX220 Group 7 Synopsis Prototype Description 4 Library Reference R_RTC_ReadBinary Read the Real time clock status flags and counters bool R_RTC_ReadBinary uint8_t data1 A pointer to the flags storage location uint32_t data2
121. data Configure the SPI input and output pins Use to separate each selection Settings for RSPCKA MOSIA and MISOA are compulsory e Pin selection PDL_SPI_RSPCKA_PA5 or PDL_SPI_RSPCKA_PBO or Select the RSPCKA pin PDL_SPI_RSPCKA_PC5 PDL_SPI_MOSIA_P16 or PDL_SPI_MOSIA_PA6 or Select the MOSIA pin PDL_SPI_MOSIA_PC6 PDL_SPI_MISOA_P17 or PDL_SPI_MISOA_PA7 or Select the MISOA pin PDL_SPI_MISOA_PC7 PDL_SPI_SSLAO_PA4 or PDL_SPI_SSLAO_ PC4 PDL_SPI_SSLA1_PAO or PDL_SPI_SSLA1_PCO PDL_SPI_SSLA2_PA1 or PDL_SPI_SSLA2_PC1 PDL_SPI_SSLA3_PA2 or PDL_SPI_SSLA3_PC2 Select the SSLAO pin optional Select the SSLA1 pin optional Select the SSLA2 pin optional Select the SSLA3 pin optional Return value True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks e Before calling R_SPI_Create call this function to configure the relevant pins e Pins which are not used for the SPI functions may be omitted Some pin options are not available on smaller device packages Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configure the applicable SPI pins R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PA7 PDL_SPI_SSLAO_PA4 PDL_SPI_SSLA1 PAO
122. data transfer PDL_INTC_VECTOR_ERI5 Error in data received PDL_INTC_VECTOR_RXI5 SCI channel 5 Data received PDL_INTC_VECTOR_TXI5 Start of next data transfer PDL_INTC_VECTOR_TEI5 End of data transfer PDL_INTC_VECTOR_ERI6 Error in data received PDL_INTC_VECTOR_RXI6 SCI channel 6 Data received PDL_INTC_VECTOR_TXI6 Start of next data transfer PDL_INTC_VECTOR_TEI6 End of data transfer PDL_INTC_VECTOR_ERI9 Error in data received PDL_INTC_VECTOR_RXI9 Data received SCI channel 9 Start of next data transfer End of data transfer PDL_INTC_VECTOR ERI12 PDL_INTC_VECTOR_RXI12 PDL_INTC_VECTOR TxI12 PDL_INTC_VECTOR TEI12 PDL_INTC_VECTOR_SCIX0O PDL_INTC_VECTOR_SCIX1 PDL_INTC_VECTOR_SCIX2 PDL_INTC_VECTOR_ICEEIO PDL_INTC_VECTOR_ICRXIO SCI channel 12 PDL_INTC_VECTOR_SCIX3 Extended serial mode Valid edge 12C bus interface Error in data received Data received Start of next data transfer End of data transfer Extended serial mode Break field Extended serial mode Control field Extended serial mode Bus collision Transfer error or event generation Data received PDL_INTC_VECTOR_ICTXIO channel 0 Start of next data transfer PDL_INTC_VECTOR_ICTEIO End of data transfer RO1USO059EG0111 Rev 1 11 REN ESAS Page 63 of 429 Aug 01 2014 RX220 Group 4 Library Reference Return value Category Refe
123. data1 PDL_ELC_PORT_CONTROL data2 e Select a port grou PDL_ELC_PORT_B Select the port group to control data3 Set configuration To set multiple options at the same time use to separate each value Input Group edge control PDL ELC PORT GROUP INPUT RISING EDGE or PDL ELC PORT GROUP INPUT FALLING EDGE or EE A ee PDL ELC_PORT_GROUP_INPUT_ANY_EDGE g e Input Group port buffer control PDL_ELC_PORT_GROUP_INPUT_ BUFFER ENABLE or ore ae PDL ELC PORT GROUP INPUT BUFFER DISABLE P y input port group e Output Group output control PDL_ELC_PORT_GROUP_OUTPUT_0 or PDL_ELC_PORT_GROUP_OUTPUT_1 or If an output port group PDL_ELC_PORT_GROUP_OUTPUT_TOGGLE or configure the output when an PDL_ELC_PORT_GROUP_OUTPUT_BUFFER or event occurs PDL_ELC_PORT_GROUP_OUTPUT_ROTATE Operation data1 PDL_ELC_SINGLE_PORT data2 e Single port configuration PDL_ELC_SINGLE_PORT_0 or PDL_ELC_SINGLE_PORT_1 Select the single port to define configure data3 Set configuration A pin selection and a single port control value must both be specified use to separate each value e Pin selection PDL_ELC_PIN_PORT_B 0 or PDL_ELC_PIN_PORT_B_1 or PDL_ELC_PIN_PORT_B 2 or PDL_ELC_PIN_PORT_B 3or Select the pin that will be assigned to the PDL_ELC_PIN_PORT_B 4 or single port PDL_ELC_PIN_PORT_B 5 or PDL
124. dtc_vector_tabl de Configure the DTC for Software trigger R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_ PLUS PDL _DTC_DESTINATION_ADDRESS_ PLUS PDL _DTC_SIZE_8 PDL_DTC_CHAIN_O PDL_DTC_TRIGGER_SW dtc_sw_transfer_data source_string_l destination_string_l 1 uint8_t strlen source_string_1 Configure the DTC for chain transfer R_DTC_Create PDL _DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_ PLUS PDL _DTC_DESTINATION_ADDRESS_ PLUS PDL _DTC_SIZE_8 PDL_DTC_CHAIN_0O PDL_DTC_TRIGGER_CHAIN dtc_sw_transfer_data 4 source_string_2 destination_string_2 1 uint8_t strlen source_string_2 Configure the DTC for chain transfer R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_ PLUS PDL _DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CHAIN dtc_sw_transfer_data 8 source_string_3 destination_string_3 1 uint8_t strlen source_string_3 Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Generate a software interrupt request R_INTC_Write PDL_INTC_REG_SWINTR 1 while 1l Figure 14 Example of DTC chain transfer R01US0059EG0111 Rev 1 11 Page 336 of 429 Aug 01 20
125. either one of the following definition values from 4 2 3 e One port definition or e One port pin definition data2 The value must be between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false I O port None e If an invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the output of port pin P05 R_IO_PORT_Write PDL_IO_PORT_0_5 0 i Set the output of port 6 R_IO_PORT_Write PDL_IO_PORT_6 0x55 i Rev 1 11 REN ESAS Page 83 of 429 RX220 Group 4 Library Reference 6 R_IO_PORT_Compare Synopsis Prototype Description Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 Check the pin states on an I O port bool R_IO_PORT_Compare uint16_t data1 Input port or port pin selection uint8_t data2 Comparison value void func Function pointer Read the input state of an I O port or I O port pin and call a function if a match occurs data1 Use either one of the following definition values from 4 2 3 e One port definition or e One port pin definition data2 The value to be compared with e Fora port 0x00 OxFF e Forapin 0or1 fu
126. enable and set it to pre charge or discharge mode Sampling time calculation for internal reference voltage PDL_ADC_12 ADSSTR_CALCULATE or PDL_ADC_12 ADSSTR_SPECIFY Select whether parameter data5 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR Pre charging or discharging time calculation for disconnection detection PDL_ADC_12 ADDISCR_CALCULATE or PDL_ADC_12_ADDISCR_SPECIFY Select whether parameter data6 is used to calculate the ADDISCR value or contains the value to be stored in register ADDISCR Valid unless PDL_ADC_12_DDA_DISABLE is selected RO1US0059EG0111 Aug 01 2014 Rev 1 11 2tENESAS Page 298 of 429 RX220 Group 4 Library Reference Description 3 4 data3 data4 Trigger source selection To set multiple options at the same time use to separate each value e Trigger selection Valid only if PDL_ADC_12_SYNC_TRIGGER_ENABLE is selected TRGA input capture compare match A PDL_ADC_12_GP_TRIGGER_MTU_TRGOAN or from MTUO TRGB input capture compare match B from MTUO TRGA input capture compare match or MTU4 TCNT underflow trough in complementary PWM mode from MTUO to MTU4 PDL_ADC_12_GP_TRIGGER_MTU_TRGOEN or TRGE compare match from MTUO PDL_ADC_12_GP_TRIGGER_MTU_TRGOFN or TRGF compare match from MTUO MTU4 TADCORA and MTU4 TCNT PDL_ADC_12_GP_TRIGGER_MTU_TRG4AN or compare match interrupt skipping function 1
127. endian 48 pins big endian 3 Please enter the path where you wish RPDL for R8220 to be installed Type the full path to the folder where you wish RPDL to be copied to and then press Enter The utility will create a folder in the location that you specified and copy the files into the new folder d Aa ee 11 Rev 1 11 REN ESAS Page 3 of 429 RX220 Group 1 Introduction ct C WINDOWS system32 cmd exe Renesas RPDL for R8220 copy utility Please enter a number to select the device package and endian option E 166 pins little endian 166 pins big endian 64 pins little endian 64 pins big endian 48 pins little endian 48 pins big endian 3 Please enter the path where you wish RPDL for R8220 to be installed C my_project_folder Creating the destination directory C my_project_folder RPDL Copying the generic files Copying the files for a 64 pin package with little endian support Finished Press any key to continue Press any key to close the window Copy folder RPDL into the folder project workspace created Example C WorkSpace rpdl_lib_test rpdl_lib_test R01US0059EG0111 Rev 1 11 Page 4 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 3 Include the new directory Use the key sequence Alt B R to open the RX Standard Toolchain window Select the C C tab Use the key sequence S to show the included file directories Click on the Add button In th
128. example RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void Configure POE pins 0 and 3 R_POE_Set PDL _POE_0_MODE_EDGE PDL POE 3 MODE LOW 128 PDL_POE_O_PORT_D_7 PDL_POE_3_PORT_D_4 PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 178 of 429 Aug 01 2014 RENESAS RX220 Group 2 Synopsis Prototype Description Return value 4 Library Reference R_POE_Create Configure the Port Output Enable event handling bool R_POE_Create uint8_t data1 Input configuration selection void funct Callback function void func2 Callback function uint8_t data2 Interrupt priority level Enable interrupts and register callback functions data1 Interrupt selection If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e High impedance request response PDL_POE_IRQ_HI_Z_0 3 DISABLE or PDL_POE_IRQ_HI_Z 0 3 ENABLE Disable or enable an interrupt on detection of any high impedance request on pins POEO to POE3 Output short detection response Disable or enable an interrupt on detection of ag Sete a ag ty ty a short on any MTU channel 3 or 4 two phase OY Pa output pair
129. exclusive otherwise false Category Data Transfer Controller Reference R_DTC_Create RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 137 of 429 RX220 Group 4 Library Reference Remarks e This function must be called in order to start the DTC R_DTC_Create must be called at least once before starting the DTC Start the DTC before generating a transfer trigger Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Update the parameters for CMT0 triggered transfers R_DTC_Control PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDATE_COUNT dtc_cmt0O_transfer_data PDL_NO_PTR void 0x0000BB00 100 PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 138 of 429 Aug 01 2014 RENESAS RX220 Group 5 Synopsis Prototype Description 4 Library Reference R_DTC_GetStatus Check the status of the Data Transfer Controller bool R_DTC_GeiSiatus uint32_t data1 Transfer data start address uint16 _t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count
130. following condition Timer cycle data register value gt Timer dead time data register value x 2 2 Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU2_ControlUnit_structure unit0O_parameters unitO_parameters simultaneous_control PDL_MTU2_START_CH_0O PDL_MTU2_START_CH_1 unitO_parameters output_control PDL_MTU2_OUT_P_PHASE_ALL_HIGH_LOW unitO_parameters general_control PDL_MTU2_DEAD_TIME_ENABLE unitO_parameters register_selection PDL_MTU2_REGISTER_DEAD_TIME PDL_MTU2_REGISTER_CYCLE_DATA unitO_parameters TDDR_value OxFFDD unitO_parameters TCDR_value 0x0100 Modify the operation of unit 0 R_MTU2_ControlUnit 0 amp unit0_parameters Rev 1 11 REN ESAS Page 172 of 429 RX220 Group 4 Library Reference 6 R_MTU2_ReadChannel Synopsis Read from MTU channel registers Prototype bool R_MTU2_ReadChannel uint8_tdata1 Channel selection uint8_t data2 A pointer to the data storage location
131. for channel slave to receive while data_received false Process the received data here while 1 SCI channel 9 receive complete handler static void SCI9RxFunc void Set flag data_received true Figure 35 Example of Synchronous Transmission and Reception code R01US0059EG0111 Rev 1 11 Page 376 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 5 Synchronous Full Duplex Operation This shows the configuration of SCI channel 6 as a clock master with both Rx and Tx data pins enabled Data is received at the same time as data is transmitted Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h SCI channel selec define MASTER _CHANN define SLAVE_CHANNEL tion EL 6 9 define DATA_LENGTH 5 Complete flags volatile uint8_t data_received volatile uint8_t data_sent Callback function prototype static void SCI_Rx_Callback void static void SCI Tx Callback void void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Pleas Set Master R_SCI_Set MASTER_CHANNEL Channel 6 pin options R_S
132. in this function Note that the file resetorg c Supplied when a new project is created requires editing to remove the comment identifiers for the two lines below extern void HardwareSetup void HardwareSetup 1 initialisation of pins that are not available For pins that are not available on the selected MCU package type set the control registers to the recommended values using R_IO_PORT_NotAvailable This function can be called even if the largest device has been selected This will allow for the user s code to be ported to another project that does use a smaller MCU package 2 initialisation of the sub clock oscillator if not used If the sub clock oscillator will not be used it should be put into a stable state Please refer the program in Section 5 16 2 R01US0059EG0111 Rev 1 11 Page 15 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 1 4 Document structure The drivers are summarised in section 2 and explained in detail in section 4 Section 5 provides usage examples Section 6 provides details which are specific to the RX CPU R01US0059EG0111 Rev 1 11 Page 16 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 1 5 List of Abbreviations and Acronyms Abbreviation Full form LSB All trademarks and registered trademarks are the property of their respective owners R01US0059EG0111 Rev 1 11 Page 17 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 Drive
133. measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of wea
134. pin for MTIOC1B e Valid when n 2 PDL_MTU2 PIN 2A P26 or PDL_MTU2 PIN 2A PB5 PDL_MTU2 PIN 2B P27 or PDL_MTU2 PIN 2B PE5 Select the P26 or PB5 pin for MTIOC2A Select the P27 or PE5 pin for MTIOC2B Valid when n 3 PDL_MTU2 PIN 3A _P14or PDL_MTU2 PIN 3A P17 or PDL_MTU2_PIN 3A _PC1 or Select the P14 P17 PC1 PC7 or PJ1 pin for MTIOC3A PDL_MTU2_PIN_3A_PC7 or PDL_MTU2 PIN 3A _PuJ1 PDL_MTU2 PIN 3B P17 or PDL_MTU2 PIN 3B P22 or PDL_MTU2_PIN 3B _PB7 or PDL_MTU2 PIN 3B PC5 PDL_MTU2_PIN 3C P16 or PDL_MTU2_PIN 3C_PCO or PDL_MTU2_PIN_ 3C_PC6 or PDL _MTU2 PIN 3C PJ3 PDL_MTU2_ PIN 3D P16 or PDL_MTU2_ PIN _3D_ P23 or PDL_MTU2_PIN_3D_PB6 or PDL_MTU2 PIN 3D PC4 Select the P17 P22 PB7 or PC5 pin for MTIOC3B Select the P16 PCO PC6 or PJ3 pin for MTIOC3C Select the P16 P23 PB6 or PC4 pin for MTIOC3D RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 151 of 429 RX220 Group 4 Library Reference Description 2 2 Valid when n 4 PDL_MTU2_PIN_4A P24 or PDL_MTU2_PIN_4A_PAO or PDL_MTU2_PIN 4A PB3 or PDL_MTU2 PIN 4A PE2 PDL MTU2 PIN 4B P30 or PDL MTU2 PIN 4B P54 or PDL_MTU2_PIN 4B PC2 or Select the P30 P54 PC2 PD1 or PE3 pin for MTIOC4B PDL_MTU2 PIN 4B PD1 or PDL_MTU2 PIN 4B PE3 PDL MTU2 PIN 4C P25 or PDL_MTU2_PIN_4C PB1 or PDL_MTU2 PIN 4C PE1 or PDL_MTU2 PIN 4C_PE5 PDL MTU2 PIN 4D P31 or PDL_MTU2_PIN 4D P55 or PDL_MTU2 PIN 4D_PC3 or PDL_MTU2_PIN 4D PD2 or
135. port buffer for the specified port data1 e Port selection PDL_ELC_PORT_B Select the port whose buffer should be read data2 Address where the port buffer value will be stored True if all parameters are valid and exclusive otherwise false Event Link Controller R_ELC Create R_ELC_Control None include r_pdl_elc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t value R_ELC_Read PDL_ELC_PORT_B amp value Page 143 of 429 RX220 Group 4 Library Reference 4 R_ELC_Write Synopsis Prototype Description Return value Category Reference Remarks Program example Write to the ELC port buffer bool R_ELC_ Write uint8_t data1 Port uint8_t data2 Value Write to the ELC port buffer of the specified port data1 e Port selection PDL_ELC_PORT_B Select the port whose buffer should be written to data2 Value to write True if all parameters are valid and exclusive otherwise false Event Link Controller R_ELC Create R_ELC_Control e If an event occurs while updating a port with bit rotation enabled abnormal operation may occur include r_pdl_elc h RPDL device specific definitions include r_pdl_definitions h void func void R_ELC_Write PDL_ELC_PORT_B OxAA R01US0059EG0
136. process Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available True if all parameters are valid and the operation completed false if a parameter was out of range or the RX pin has not been selected by using the R_SCI_ Set and or R_SCI_ Create functions Category SCI R01US0059EG0111 Rev 1 11 REN ESAS Page 261 of 429 Aug 01 2014 RX220 Group 4 Library Reference Reference R_SCI_ Receive R_SCI_ Set Remarks e The error flags are not modified by this function They are cleared when a new reception process is started e For channels SCI1 SCI5 and SCI6 if the RxD pin to be used has not been specified using R_SCI_Set before calling this then the RxD pin level will always be read as low Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h uint8_t StatusValue uintl6_t TxChars uintl6_t RxChars void func void Read the status of SCI channel 1 R_SCI_GetStatus 1 amp StatusValue PDL_NO_PTR amp TxChars amp RxChars R01US0059EG0111 Rev 1 11 Page 262 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 2 21 l2C Bus Interface 1 R_IIC Set Synopsis Configure the I C pin selection Prototype Description Return value Category Reference
137. read_eeprom_data void bus_busy true Read data from the ROM using the R_IIC_MasterReceive IIC_CHANNEL PDL_IIC_DMAC_TRIGG EPROM_ADDRESS DL_NO_PTR L_NO_FUNC while bus_busy true void iic_tx_dmac_end_handler void uint32_t status_flags 0 Wait for the transmission to complete do R01US0059EG0111 Rev 1 11 Page 396 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples R_IIC_GetStatus IIC_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x0080u Ox0u Issue a Stop condition BR TIC Control TIC_CHANNEL PDL_IIC_STOP bus_busy false void iic_rx_dmac_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR PDL_NO_PTR Read one more byte with NACK condition and R_IIC_MasterReceiveLast TIC_CHANNEL uint8_t DestAddr bus_busy false Figure 48 An example of writing data to and reading data from an EEPROM using two DMAC channels R01US0059EG0111 Rev 1 11 Page 397 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 19 3 Master mode with DTC In the following example data is written to an EEPROM in two bursts The DTC is used to handle the data transfer T
138. see the notes on callback function usage in 6 e Ifthe Start condition is enabled and the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated e Ifthe Start condition is disabled the slave address will not be transmitted e If no callback function is specified for transmission completion this function will monitor the status flags to manage the data transmission If the 1 C channel s registers are modified directly by the user this function may lock up e If false is returned use R_IIC_GetStatus to check if an unexpected event on 1 C bus was the cause of the failure If the transfer has ended prematurely use R_IIC_Control to issue a Stop condition e False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create e False will be returned if the bus is busy due to another master on the bus e When using the DMAC or DTC a stop condition will not be generated Hence if one is required it must be manually generated using R_IIC_Control when it has been detected that the last byte has been sent RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Send 5 bytes to device 0x0A0 on channel 0 using polling R_IIC_MasterSend 0 PDL_NO_DATA 0x0A0 data_array 5 PDL_NO_FUNC 0 R01US0059EG0111 Rev 1 11 z
139. selections are required use to separate each selection If no selections are required specify PDL_NO_DATA Monitor control PDL_LVD_DISABLE Disable monitor 2 operation e Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 2 change detection flag Return value True Category Voltage detection circuit References R_LVD_Create Remarks Other operation changes require the shutdown of both voltage monitors If such changes are required call R_LVD_Create with the new settings Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions include r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void func void Disable monitor 1 clear the monitor 2 flag R_LVD_Control PDL_LVD_DISABLE PDL_LVD_CLEAR_DETECTION 3 Rev 1 11 REN ESAS Page 100 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description R_LVD_GetStatus Check the status of the voltage detection module bool R_LVD_GetStatus uint8_t data Status flags pointer 5 Return the status flags Program example data The Monitor 1 and Monitor 2 status flag shall be stored in the following format b7 b6 b5 b4 b3 b2 b1 bO Monitor 2 Monitor 1 Status Change S
140. settling time use R_CGC_Control to select the desired clock source If the sub clock oscillator is not fitted use R_CGC_Control to disable the oscillation circuit The registers MOSCWTCR main clock and SOSCWTCR sub clock provide stabilisation delays for the respective oscillator and must be written to while that clock is stopped If any of these registers needs to be modified stop the clock using R_CGC_Control and call R_LPC_Create to set the new value If the IWDTLOCO is selected specify PDL_NO_DATA for parameters data2 and data4 to data7 If the HOCO is selected the HOCO power must not be turned off If the sub clock will be selected while in low speed operating mode 2 see R_LPC_Create ficLk Sub clock ANd frcLk sub clock MUSt equal fsus cLock Make sure PCLKB clock frequency 2 RTC count source clock frequency When RTC is not to be used call R_CGC_Control with option PDL_CGC_RTC_NOT_USE after calling this function to configure the RTC count source Sub clock oscillator is not available for 48 pin package RPDL definitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void R_CGC_Set Configure main clock operation using a 20 0 MHz crystal ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_RESONATOR 20E6 20E6 20E6 20E6 20E6 PDL_NO_DATA Co
141. status and registers 1 R_RTC_ Create Configure the Real time clock in calendar count mode 2 R_RTC_CreateBinary Configure the RTC module in binary count mode 3 R_RTC_Destroy Shut down the Real time clock 4 R_RTC_Control Modify the RTC clock operation in calendar count mode 5 R_RTC_ControlBinary Modify the RTC module operation in binary count mode Real time Clock Read the Real time clock status flags and counters in 6 R_RTC_Read calendar count mode 7 R_RTC_ReadBinary Read the RTC module status flags and counters in binary count mode Reconfigure RTC interrupt setting at warm start up in RATC CreateWarm calendar count or mode binary count mode Independent 1 R_IWDT_Set Configure the Independent Watchdog operation Watchdog Timer 2 R_IWDT_Control Control the Independent Watchdog operation 3 R_IWDT_Read Read the watchdog timer status and counter 1 R_SCI_Set Configure the SCI pin selection 2 R_SCl_Create SCI channel setup 3 R_SCI_Destroy Shut down a SCI channel 4 R_SCl_Send Send a string of characters Serial 5 R_SCI_Receive Receive a string of characters Communication 6 R_SCI_SPI_Transfer Perform an SCI SPI transfer Interface 7 R_SCI_IIC_Write Perform an SCI IIC master write 8 R_SCI_IIC_Read Perform an SCI IIC master read 9 R_SCI_IIC_ReadLastByte Finish an SCI master read if using DMAC or DTC 10 R_SCI_ Control Control the SCI channel 11 R_SCI_GetStatus Check the status of an SCI channel R01US0059EG0111 Rev 1 11 Page 48 of 429 Aug
142. the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period RPDL definitions yr pdl_cmt h include RPDL device specific definitions include r_pdl_definitions h void func void Use CMT channel 0 for a ims pause R_CMT_CreateOneShot Rev 1 11 0 E 3 DL_NO_DATA P 1 PDL_NO_FUNC 0 2tENESAS Page 210 of 429 RX220 Group 4 Library Reference 3 R_CMT_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a CMT unit bool R_CMT_Desiroy uint8_t data Unit selection Shut down a CMT unit data The timer unit n where n 0 or 1 Unit 0 comprises channels CMTO and CMT1 Unit 1 comprises channels CMT2 and CMT3 True if the unit selection is valid otherwise false Compare Match Timer R_CMT_Create e The timer unit is put into the stop state to reduce power consumption RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_CMT_Destroy 0 R01US0059EG0111 Aug 01 2014 Rev 1 11 RENESAS Page 211 of 429 RX220 Group 4 Synopsis Prototype Description Return value 4 Library Re
143. the time if 0 flags amp BIT_6 Has time changed if time amp OxFFFFFF time_previous amp OxFFFFFF time_previous time sprintf char buffer Time d d d d d d r n int time amp 0xF00000 gt gt 20 int time 0x0F0000 16 int time 0x00F000 I2 int time 0x000F00 8 int time 0x0000F0 4 int time 0x00000F 0 R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA buffer 0 PDL_NO_FUNC static void SetClocks void Prepare the LOCO settings R_CGC_Set PDL_CGC_CLK_LOCO PDL_NO_DATA 125E3 125E3 PDL_NO_DATA 125E3 125E3 R01US0059EG0111 Rev 1 11 Page 365 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples PDL_NO_DATA Configure the HOCO settings R_CGC_Set PDL_CGC_CLK_HOCO L_CGC_HOCO_50000 6 6 L_NO_DATA 6 6 D D 01 5 D 5 5 D L_NO_DAT Prepare the Sub clock settings R_CGC_Set PDL_CGC_CLK_SUB_CLOCK DL_CGC_SUB_CLOCK_CL_STANDARD 2768 2768 D 2 2 D L_NO_DATA 768 PCLKB clock sub clock when sub clock is source clock 768 L_CGC_SUB_32768 Wait for the Subclock stabilisation time 2 seconds minimum NOTE As curently running from the Sub clock the R_CMT_CreateOneShot max time limit is gt 2 Secs R_CMT_CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 Select the HOCO as th
144. to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read b7 b4 b3 b2 bi bO 0 ELC count state Overflow Compare match B_ Compare match A data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required Return value True Category Timer TMR Reference R_TMR_CreateChannel Remarks e Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 Program example RO1US0059EG0111 Aug 01 2014 Rev 1 11 by this function e The ELC count flag is valid only when n 0 or 2 include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint8_t Counter uint8_t CompareMatchA uint8_t CompareMatchB void func void Read the status flags and registers for TMRO R_TMR_ReadChannel 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB RENES S Page 204 of 429 RX220 Group 4 Library Reference 11 R_TMR_ReadUnit Synopsis Prototype Description Read from timer unit registers bool R_TMR_Readunit uint8_t data1 Unit selection ui
145. to separate each selection Each selection is optional If a selection is not made the control setting will be left unchanged Direction control PDL_IO_PORT_INPUT or PDL_IO_PORT_OUTPUT Input or output e Output type control PDL_IO_PORT_TYPE_CMOS or Select CMOS push pull output Available on PDL_IO_PORT_TYPE_NMOS or N channel open drain selected pins PDL_IO_PORT_TYPE_PMOS or P channel open drain or Available on pin PDL_IO PORT _TYPE_ HI Z high impedance PE1 only e Input pull up resistor control PDL_lIO_PORT_PULL_UP_ON or PDL IO PORT PULL _UP_OFF On or off e Drive capacity control PDL_IO_PORT_DRIVE_NORMAL or Normal or high current drive PDL_IO_ PORT _DRIVE_HIGH Valid for ports 1 B and C True if all parameters are valid and exclusive otherwise false I O port R_IO_PORT_NotAvailable Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver functions Take care to not overwrite existing settings Pin P35 is fixed as an input and cannot be modified All pins that are not available on the selected package can be set to the required state using the R_IO_PORT_NotAvailable function When a package with less than 100 pins has been chosen the following port pins are mutually exclusive If the user s code tries to configure both pins the port pin selected in the
146. value shall be stored Get the value of an MPC register data1 One of the definition values from 4 2 4 data2 The value read from the register True if a valid MPC register is specified otherwise false MPC registers None e None RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of register PO7PFS R_MPC_Read PDL_MPC_REG_PO7PFS amp data Rev 1 11 REN ESAS Page 89 of 429 RX220 Group 4 Library Reference 2 Synopsis Prototype Description Return value Category References Remarks Program example R_MPC Write Write to a MPC register bool R_MPC_Write uint8_t data1 MPC register selection uint8_t data2 Data to be written to the MPC register Write the value to an MPC register data1 One of the definition values from 4 2 4 data2 The value to be written to the register True if a valid MPC register is specified otherwise false MPC registers None The MPC registers are modified by other driver functions Take care to not overwrite existing settings e Refer to the hardware manual for valid values for each register RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h
147. wil ieee ee 181 R POE lt GetStatuis fa o a tes AEN a a Ue ae eid ieee Rabe 183 B Dit TIMEN aiea aat a e eel a a a ie elec ee eI ea aLa 184 RELMRe Setiiieccntccine Banca ie a Qe ets ital he a ee ae 184 RolMR GreateChanine li i sic dteanediccn etiiesnad eieetivenie lie del el Patel iain inna At 186 R TMR Greate W nite nicecivstiugs in n a E N N E EAS Ge Maeda E A 189 RMR GreatePariodi Cnn aa I eed a ke 192 R TMR GreateOneShob ariin r a thie ee as eee eee 195 ReSEMR DeSthOy iinr tiid a a a ened See ee Aa eas 197 RATMReContral hannelissyicicieuiesascdefeiesnieh N e a WW alone da iera a eA E 198 RAEMR ControlU Nits aaen aati ania aa a aan aaa a a ei ee Ie 200 Re TMRe ControlPerioGic iseenda aeaeaie 202 R TMR R a adGChannel aoee taae ios eren Ena a eaea aae aa eE AA aa E Dde aa ataata aaaea 204 R TMR R d UNE e a aan rara taer a aaan tbat neath iis aaan a a a an ta aa aa aaaea a 205 4 2 17 Compare Match Timer ciiid diidiis iii ad aiii i idis 207 1 RaEGMT Create ax iem i a a a ai ta i a a EA 207 2 REGMTCreateOne Sholecisien eieae a eia he til aaa iaa a a E a aia 209 SB RECME DEStOy ieten ihmisii isidi aiaiai feel ade i ei a en 211 ari REIGM Te COn olaer iuen Serart ar e a eE EE E E E e e 212 By SREGMT SROs oe aE e E E A E e EEE A EEGA 214 4 218 Realtime ClO CK a es a a a a a a ai dE a obasOA 215 1 R RTG Creaton acn Niinan a a a i A ta a a tiene bdoh 215 2 RRFC GreateBiNary sereisas iida idii didaa iieii iai iiaii 218 3ye RER
148. window Use the drop down menu to select Double precision CPU details Detail PIC PID Round to Precision of double Sign of char Sign of bit field unsigned v Bit field order Right 7 Width of divergence of function 24 bit F Denormalized number allower as a result l Replace from int with short I enum size is made the smallest I Pack struct union and class I Use try throw and catch of C F Use dynamic_cast and typeid of C r The saved and restored code of the accumulator in interrupt function Click on OK to close the window Click on OK to return to the main HEW window 10 Build the project No further configuration should be required Simply build the project R01US0059EG0111 Rev 1 11 Page 12 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 11 Using library with debug information RPDL library with debug information should be chosen in order to step in the RPDL source code for debugging Unzip the RPDL source zip file e g RPDL_RX220_CS x xx_source zip into a folder e g C my_project_folder Set a breakpoint at the RPDL API to be debugged When the program breaks at the RPDL API press F11 key to step in the function A pop up window will appear to request for the location of the corresponding RPDL source file Look in e my_project_folder e ef ea QRPoL lem RPDL_RX220_CS x xx_source File name R_CR C_Write
149. 1 ADC unit selection uint8_t data2 Analog channel selection uint16_t data3 Channel configuration double data4 Sampling time Channel specific control Used to complement R_ADC_12_CreateUnit to configure 12 bit ADC analog channels if analog channels are selected as the input source data1 Select the ADC unit This must always be 0 data2 Select the analog input channel This must be from 0 to 15 data3 Channel options To set multiple options at the same time use to separate each value The default settings are shown in bold e Group selection PDL_ADC_12_CH_GROUP_Aor Assign the channel to Group A or PDL_ADC_12_CH_GROUP_B Group B e Value addition control PDL_ADC_12_CH_VALUE_ADDITION_DISABLE or PDL_ADC_12 CH VALUE ADDITION ENABLE Enable or disable value addition e Double trigger control PDL_ADC_12_CH_DOUBLE_TRIGGER_DISABLE or PDL_ADC_12_CH_DOUBLE_TRIGGER_ENABLE Enable or disable double trigger e Sampling time calculation PDL_ADC_12_CH_ADSSTR_CALCULATE or PDL_ADC_12 CH ADSSTR_SPECIFY Select whether parameter data4 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR data4 The data to be used for the sampling state register value calculations If PDL_ADC_12_CH_ADSSTR_SPECIFY is selected for data3 the value should not be less than 12 or more then 255 Data use Parameter type The timer period in se
150. 1 2014 R_INTC_Read Read an interrupt register bool R_INTC_Read uint16_tdata1 Register selection uint8_t data2 Data storage location Read an interrupt register and store the value data1 e The register to be read PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register DTC Activation Enable register data2 The location where the register s value shall be stored True if all parameters are valid and exclusive otherwise false Interrupt control None For register select one of the registers listed in the tables starting on page 69 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t ipl Read the IPL bits R_INTC_Read PDL_INTC_REG_IPL amp ipl Rev 1 11 REN ESAS Page 72 of 429 RX220 Group 4 Library Reference 9 R_INTC_Write Synopsis Update an interrupt register Prototype bool R_INTC_Write uint16_tdata1 Register selection uint8_t data2 Register value Description Write the new value to an interrupt register data1 e T
151. 1 Aug 01 2014 include yr pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Rev 1 11 Configure TMR unit 0 R_TMR_CreateUnit 0 PDL_TMR_CLK_PCLK_DIV_1 0 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 2tENESAS PCLKB PDL_TMR_CLI EAR_CM_A 4 Library Reference clear after a compare match A Page 191 of 429 RX220 Group 4 Library Reference 4 R_TMR_CreatePeriodic Synopsis Prototype Description Select periodic operation bool R_TMR_CreatePeriodic uint8_t data1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection double data3 Period or frequency double data4 Pulse width or duty cycle void func1 Pulse width interval callback function void func2 Periodic interval callback function uint8_t data5 Interrupt priority level Set up a TMR timer channel or unit for periodic operation and start the timer data1 PDL_TMR_TMRO or PDL TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR UNIT1 The channel n n 0 1 2 or 3 or unit n 0 or 1 to be configured data2 Configure the timer If multiple selections are required use to separate each selection The default settings are shown in bold Period or frequency calculation PDL_TMR_FREQU
152. 1 11 REN ESAS Page 257 of 429 Aug 01 2014 RX220 Group 4 Library Reference 9 R_SCIIIC_ReadLastByte Synopsis Prototype Description Return value Category Reference Remarks Program example Read the last byte of an IIC read transfer bool R_SCI_IIC_ReadLastByte uint8_t data1 Channel selection uint8_t data2 Buffer to receive byte If R_SCI_IIC_Read has been used to start an IIC read where the DMAC or DTC will read all the data except for the last byte this function can be used to read the last byte ANACK will then be generated followed by a stop condition unless the original transfer request asked for the stop condition to be omitted data1 Select channel SCIn where n 1 5 6 9 or 12 data2 The address of the buffer that will receive the byte True SCI R_SCI_IIC_Read None PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 9 Buffer for IIC data extern uint8_t IIC_Buffer 10 void func void Read the last byte of the IIC read operation R_SCI_IIC_ReadLastByte CHANNEL_SCI_IIC amp IIC_Buffer 9 R01US0059EG0111 Rev 1 11 REN ESAS Page 258 of 429 Aug 01 2014 RX220 Group 4 Library Reference 10 R_SCI_Control Synopsis Prototype Description
153. 1 Rev 1 11 Page 1 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 1 1 Tool chain requirements This RPDL library has been built and tested using the C C Compiler Package for RX Family V 1 02 Release 01 It cannot be used with older versions of the tool chain The latest version of the tool chain can be downloaded from the Renesas Web site Home Products Software and Tools Coding Tools C C Compilers and Assemblers C C Compiler Package for RX Family 1 2 Compiler options when you use this product 1 The options which must be specified in your project are listed below The options other than cpu dbl_size are the default setting of the compiler cpu rx200 round nearest denormalize off dbl_size 8 unsigned_char unsigned_bitfield bit_order right unpack noexception rtti off fint_register 0 branch 24 2 The options which must NOT be specified in your project are listed below As the default setting of the compiler the following options are not specified int_to_short auto_enum base patch pic pid nouse_pid_register Save_acc 1 3 Using the library within your project The driver library can be used in two ways 1 3 1 Via the PDG graphical utility PDG can be downloaded from www renesas com pdqg The directions for use of the PDG utility are given in the PDG manual 1 3 2 Using RPDL stand alone To add the driver library to your project
154. 10 The destination address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat function is not required for the destination address func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data11 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference None Remarks lf another peripheral will be used to trigger a DMA transfer call this function before calling the Create function for the peripheral Some peripheral channels are not available on some device packages Please check the hardware manual Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 124 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Configure DMA channel 2 R_DMAC_Create 2 PDL_DMAC_NORMAL PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZE_8 P
155. 111 Rev 1 11 2tEN ESAS Aug 01 2014 Page 144 of 429 RX220 Group 5 R_ELC _Conirol Synopsis Prototype bo Description 1 5 Se R01US0059EG0111 Aug 01 2014 Control the ELC ol R_ELC_Control uint16_t data1 uint32_t data2 uint32_t data3 tup and then control the ELC data1 Operation selection 4 Library Reference Operation to perform Operation specific configuration Operation specific configuration PDL_ELC_ENABLE or Enable the linkage of all configured events PDL_ELC_DISABLE or Disable the linkage of all events PDL_ELC_CREATE_LINK or Create a link between an event and a module This function must be called for each link required PDL_ELC_REMOVE_LINK or Remove a link previously created PDL_ELC_TIMER_OPERATION or Configure the operation of a timer when triggered by an event PDL_ELC_PORT_GROUP or Define a port group by selecting the pins within a port that make up the group PDL_ELC_PORT CONTROL or Input and output control options for a port group PDL_ELC_SINGLE_PORT or Selection of a single port and configuration of it when used as an event generator and or a triggered module PDL_ELC_SOFTWARE_EVENT or Generate a software event PDL_ELC_TRIGGER Set DTC trigger from ELC Interrupts options NOTE The specification of parameters data2 and data3 de
156. 14 RENESAS RX220 Group 5 Usage Examples 5 11 Port Output Enable Figure 15 shows a usage example of Port Output Enable function PDL functions include r_pdl_poe h PDL device specific definitions include r_pdl_ definitions h void POEO_3 handler void void POE8_handler void void main void Configure POE R_POE n 10 t PO PO PO PO POR PO POR PO POR PO HI_Z_R PO HI ZR ouu oooon0nouoo ol PO HIAR PDL_POE E_ Create pD LOW_8 LOW_128 x IRQ_HI_Z_0_3_ENABLE 15 while 1l Read the POEO_3_ handler POE8_handler EO 3 handler void t1l6_t StatusFlags POE status R_POE_GetStatus amp StatusFlags POEO request if StatusFlags amp BIT_O 0x0u PDL_POE_IRQ_SHORT_3_4 ENABLE Prevent further interrupts and try to clear the R_POE_Control PDL_NO_DATA PDL_POE FLAG_POEO_CLEAR PDL_POE IRQ_HI_Z_0_3_DISABL Read the E8_handler void tl16_t StatusFlags POE status R_POE_GetStatus amp StatusFlags Prevent fur R_POE_Control
157. 1_P31 PDL_SCI_PIN_SCI1_RTS1_P14 or RTS1 PDL_SCI_PIN_SCl1_RTS1_P31 PDL_SCI_PIN_SCI1_SS1_P14 or Sst PDL_SCI_PIN_SCl1_SS1_P31 Rev 1 11 REN ESAS Page 236 of 429 RX220 Group RO1US0059EG0111 Aug 01 2014 Valid when n 5 4 Library Reference PDL_SCI_PIN_SCI5_RXD5_PA2 or PDL SCI PIN_SCI5_RXD5_PA3 or RXD5 PDL SCI PIN_SCI5_RXD5_PC2 PDL SCI PIN_SCI5_SMISO5_PA2 or PDL SCI PIN_SCI5_SMISO5_PA3 or SMISO5 PDL_SCI_PIN SCI5 SMISO5 PC2 PDL SCI PIN SCI5 SSCL5 PA2 or PDL_SCI_PIN SCI5 SSCL5 PAS or SSCL5 PDL_SCI_PIN SCI5 SSCL5 PC2 PDL SCI PIN SCI5 TXD5 PA4 or a PDL_SCI_PIN SCI5_TXD5_PC3 PDL SCI_PIN SCI5 SMOSI5 PAd or PDL_SCI_PIN SCI5 SMOSI5 PC3 SCIS SMOSI5 PDL SCI PIN SCI5 SSDA5 PA or E PDL_SCI_PIN SCI5 SSDA5 PC3 PDL SCI_PIN SCI5 SCK5 PAt or PDL_SCI_PIN SCI5 SCK5 PC1 or SCK5 PDL_SCI_PIN SCI5 SCK5 PC4 PDL SCI PIN SCI5 CTS5 PAG or ae PDL SCI PIN SCI5 CTS5 PCO PDL SCI PIN SCI5 RTS5 PAG or ae PDL_SCI_PIN SCI5_RTS5 PCO PDL SCI PIN SCI5 SS5 PAG or ce PDL SCI PIN SCI5_SS5 PCO Valid when n 6 PDL SCI PIN SCl6_RXD6 P33 or EAE PDL SCI PIN_SCI6_RXD6_PB0 PDL SC
158. 2 4 Library Reference data3 For n 0 to 4 A pointer to where the TNCT register value shall be stored For n 5 A pointer to where the TNCTU register value shall be stored Specify PDL_NO_PTR if it is not required data4 For n 0 to 4 A pointer to where the TGRA register value shall be stored For n 5 A pointer to where the TNCTV register value shall be stored Specify PDL_NO_PTR if it is not required data5 For n 0 to 4 A pointer to where the TGRB register value shall be stored For n 5 A pointer to where the TNCTW register value shall be stored Specify PDL_NO_PTR if it is not required data6 For n 0 3 or 4 A pointer to where the TGRC register value shall be stored For n 5 A pointer to where the TGRU register value shall be stored Specify PDL_NO_PTR if it is not required data7 For n 0 3 or 4 A pointer to where the TGRD register value shall be stored For n 5 A pointer to where the TGRV register value shall be stored Specify PDL_NO_PTR if it is not required data8 For n 0 A pointer to where the TGRE register value shall be stored For n 5 A pointer to where the TGRW register value shall be stored Specify PDL_NO_PTR if it is not required data9 For n 0 A pointer to where the TGRF register value shall be stored Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid and exclusive otherwise false C
159. 2 00 Mbps feciks 4 195 kbps to 187 5 kbps to 48 8 kbps to 46 875 kbps 125 kbps to 31 3 kbps to 6 25 Mbps 6 0 Mbps 1 56 Mbps to 1 5 Mbps 4 00 Mbps 1 00 Mbps fecika 8 97 7 kbps to 93 75 kbps to 24 4 kbps to 23 4 kbps to 62 5 kbps to 15 6 kbps to 3 13 Mbps 3 0 Mbps 781 kbps 750 kbps 2 00 Mbps 500 kbps fpcLkg 16 48 8 kbps to 46 875 kbps to 12 2 kbps to 11 71 kbps to 31 3 kbps to 7 81 kbps to 1 56 Mbps 1 5 Mbps 391 kbps 375 kbps 1 00 Mbps 250 kbps fPcLkg 32 24 4 kbps to 23 4 kbps to 6 10 kbps to 5 86 kbps to 15 6 kbps to 3 91 kbps to 781 kbps 750 kbps 195 kbps 187 5 kbps 500 kbps 125 kbps feck 64 12 2 kbps to 11 71 kbps to 3 05 kbps to 2 93 kbps to 7 81 kbps to 1 95 kbps to 391 kbps 375 kbps 97 7 kbps 93 75 kbps 250 kbps 62 5 kbps fectka 128 6 10 kbps to 5 86 kbps to 1 53 kbps to 1 46 kbps to 3 91 kbps to 977 bps to 195 kbps 187 5 kbps 48 8 kbps 46 875 kbps 125 kbps 31 3 kbps RO1USO059EG0111 Rev 1 11 REN ESAS Page 266 of 429 Aug 01 2014 RX220 Group The actual rise and fall times will not be zero Using the limits from the 1 C specification Rise time rate lt 100 kbps 1000 ns 100 kbps lt rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Fall time rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Maximum rate 1 Mbps The achievable transfer rates are 4 Library Reference Program example R
160. 2014 RENESAS RX220 Group 4 Library Reference Description 3 3 Update the Error Adjustment value PDL_RTC_ERROR_UPDATE_ERROR_ADJUST_VALUE Select to specify a new error adjustment value e Error Adjustment Value New automatic error Valid Range 0 to 3Fh adjustment value ignored if not selected above data8 Configure the clock periodic interrupt e Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256_HZ or PDL_RTC_PERIODIC_128 HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32_HZ or PDL_RTC_PERIODIC_16_HZ or PDL_RTC_PERIODIC_8 HZ or PDL_RTC_PERIODIC_4 HZ or PDL_RTC_PERIODIC_2_ HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC_PERIODIC_ 2S The frequency or interval for periodic interrupt requests Return value True if all parameters are valid and exclusive otherwise false Category Real time clock Reference R_RTC_Create R_ RTC_Read Remarks e This function is not available in binary count mode e Refer to R_RTC_Create for the time and date formats e If the current time or date values are updated the clock is stopped during the update e f the day of week is updated using automatic calculation the most recent year month and date will be used e The range checking for either day value uses the most recent year and month values e If entering software standby mode soon after modifying the RTC values use
161. 24 Hour Mode b31 b24 b23 b16 b15 b8 b7 b0 Day of week Hours Minutes Seconds Valid from 0 to 6 0 Sunday Specify OxFF for Valid from O Valid from O Valid from automatic calculation using the values in data3 to 23 to 59 0 to 59 12 Hour Mode b31 b24 b23 b22 b16 b15 b8 b7 b0 Day of week Valid from 0 to 6 0 Sunday AM Pe aah es Specify OxFF for automatic z arn ASOM rem 1 PM 1 to 12 0 to 59 0 to 59 calculation using the values in data3 data3 The current year month and day BCD format is used If not required specify PDL_NO_DATA b31 b16 b15 b8 b7 b0 Year Month Day Valid from 0 to 9999 Valid from 1 to 12 data4 Configure the clock periodic interrupt The default setting is shown in bold e Periodic interrupt selection Valid from 1 to the number of days in the month PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256_HZ or PDL_RTC_PERIODIC_128 HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32 HZ or PDL_RTC_PERIODIC_16_HZ or PDL_RTC_PERIODIC_8 HZ or PDL_RTC_PERIODIC_4 HZ or PDL_RTC_PERIODIC_2 HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC_ PERIODIC 2S The frequency or interval for periodic interrupt requests data5 The alarm day of the week and time in hours minutes and seconds BCD format is used If not required specify PDL_NO_DATA The format is dependent upon if using 12 hour or 24 hour mode 24 Hou
162. 2_CHANNEL_2_COMPARE_MATCH_2A or PDL ELC LINK EVENT MTU2 CHANNEL _2 COMPARE MATCH 2B or PDL ELC LINK EVENT MTU2_CHANNEL_2_ OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_2_ UNDERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_3 COMPARE_MATCH_3A or PDL ELC LINK EVENT MTU2_CHANNEL_3 COMPARE MATCH 3B or PDL ELC LINK EVENT MTU2_CHANNEL_3_COMPARE_MATCH_3C or PDL ELC LINK EVENT MTU2_ CHANNEL 3 COMPARE MATCH 3D or PDL ELC LINK EVENT MTU2_CHANNEL_3_OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_4_COMPARE_MATCH_4A or PDL ELC LINK EVENT MTU2_CHANNEL_4_COMPARE_MATCH_4B or PDL ELC LINK EVENT MTU2_CHANNEL_4_COMPARE_MATCH_4C or PDL ELC LINK EVENT MTU2_CHANNEL_4_COMPARE_MATCH_4D or PDL ELC LINK EVENT MTU2_CHANNEL_4 OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_4_UNDERFLOW or PDL ELC LINK EVENT TMR_CHANNEL_0_COMPARE_MATCH_AO or PDL ELC LINK EVENT TMR_CHANNEL 0 COMPARE MATCH B0 or PDL ELC LINK EVENT TMR_CHANNEL_0_OVERFLOW or PDL ELC LINK EVENT TMR_CHANNEL_2 COMPARE_MATCH_A2 or PDL ELC LINK EVENT PDL ELC LINK EVENT TMR_CHANNEL_2 COMPARE MATCH_B2 or TMR_CHANNEL_2 OVERFLOW or PDL ELC LINK EVENT SCI5_ ERROR or PDL ELC LI
163. 2rCENESAS C O D ae on lt a S C D Renesas Peripheral Driver Library User s Manual RX220 Group All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http Awww renesas com nenesa E GCIONICS Rev 1 11 Aug 2014 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement
164. 4 Example of External Interrupt R01US0059EG0111 Rev 1 11 ET REN ESAS Page 320 of 429 RX220 Group 5 3 I O Port Figure 5 shows examples of I O port configuration reading and writing Peripheral driver function prototypes include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t result uintl6_t direction Set all reserved I O port pins to the recommended state R_IO_PORT_NotAvailable Configure port 4 as an input R_IO_PORT_Set PDL_IO_PORT_ PDL_IO_PORT_ PDL_IO_PORT_ PDL_IO PORT 4 6 PDL_IO_PORT_INPUT PDL_IO_PORT_ PDL_IO_PORT_ PDL_IO_PORT_ PDL_IO_PORT 0 2 4 6 P Configure port pin P30 as an open drain output R_IO_PORT_Set PDL_IO_PORT_3_0 PDL_IO_PORT_OUTPUT PDL_IO_PORT_TYPI Read the value of all the pins on port 4 R_IO_PORT_Read PDL_IO_PORT_4 amp result Set pin P30 to output high R_IO_PORT_Write PDL_IO_PORT_3_0 1 i Invert pin P30 R_IO_PORT_Modify PDL_IO_PORT_3_0 PDL_IO_PORT_XOR 1 And the value on port 4 with 55h R_IO_PORT_Modify PDL_IO_PORT_4 PDL_IO_PORT_AND 0x55 Read the control registers for port Pl R_IO_PORT_ReadControli PDL_IO_PORT_1 PDL_IO_PORT_DIRECTION amp direction Set the lower 4 bits on port Pi to output R_IO_
165. 4 Library Reference 4 2 9 Register Write Protection 1 R_RWP Control Synopsis Prototype Description Return value Category References Remarks Program example Control register write protection bool R_RWP_Conirol uint8_t data Configuration selection Control register write protection data Write enable control To set multiple options at the same time use to separate each value e Register write control PDL_RWP_ENABLE_CGC_WRITE or Enable or disable writing to CGC PDL_RWP_DISABLE_CGC_WRITE registers PDL_RWP_ENABLE_MODE_RESET_WRITE or Enable or disable writing to Mode and PDL_RWP_DISABLE_MODE_RESET_WRITE Reset registers PDL_RWP_ENABLE_LVD_WRITE or Enable or disable writing to LVD PDL_RWP_DISABLE_LVD_WRITE registers PDL_RWP_ENABLE_MPC_WRITE or Enable or disable MPC Register PDL_RWP_DISABLE_MPC_WRITE access True if the parameter is valid otherwise false RWP None To allow for nested function calls the access to the enabling disabling of register protection is done using a reference counting method Hence a call to disable a register access may only decrement a reference counter and not actually apply the write protection Other RPDL functions automatically enable and disable access to registers as required so this function is normally not required RPDL definitions include
166. 8V the callback function is called Peripheral driver function prototypes include r_pdl_lvd h PDL device specific definitions include r_pdl_definitions h static void Callback_LVD void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Setup VDET2 to call a function if VCC drops below 3 1V R_LVD_Create PDL_NO_DATA PDL_NO_DATA PDL_LVD_INTERRUPT_MI_DETECT_FALL PDL_LVD_FILTER_LOCO_DIV_2 PDL_LVD_VDET2_PIN_VCC PDL_LVD_VOLTAGE_LEVEL_310 PDL_NO_FUNC PDL_NO_DATA Callback_LVD 15 Low Voltage Callback function static void Callback_LVD void uint8_t status Read status R_LVD_GetStatus amp status User Handle Low Voltage Detection Figure 7 Example of Voltage Detection Circuit use R01US0059EG0111 Rev 1 11 Page 324 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 5 2 Non maskable interrupts This shows an example of Voltage detection circuit usage An NMI is generated if the supply voltage drops below 3 1V Peripheral driver function prototypes include r_pdl_lvd h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h static void Callback NMI void void main void Initialise the system clocks NOTE The code to initialise the syst
167. 9 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Priority Frequency error callback void CAC_frequency_error void uint8_t Status_flags uintl6_t upper_limit uint1l6_t lower_limit uintl6_t counter R_CAC_GetStatus amp Status_flags amp upper_limit amp lower_limit amp counter 3 Clear the error flag R_CAC_Control PDL_CAC_CLEAR FREQUENCY__ PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA i TODO Handle the frequency error void CAC_measurement_complete void uint8_t Status_flags uintl6_t upper_limit uint1l6_t lower_limit uintl6_t counter R_CAC_GetStatus amp Status_flags amp upper_limit amp lower_limit amp counter i Clear the measurement complete flag and stop the CAC R_CAC_Control PDL_CAC_DISABLE PDL_CAC_CLEAR_MEASUREMENT PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Overflow callback void CAC_overflow void Clear the overflow flag R_CAC_Control PDL_CAC_CLEAR_OVERFLOW PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA TODO Handle the overflow error Figure 9 Example of Clock Frequency measurement use R01US0059EG0111 Rev 1 11 Page 327 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 7 Low Power Consumption 5 7 1 Software Standby Mode Figure 10 shows an example of entering Software Standby mode through Low
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169. 9EG0111 Rev 1 11 Page 286 of 429 Aug 01 2014 RENESAS RX220 Group 5 Synopsis Prototype Description 4 Library Reference R_SPI_Transfer Transfer data over an SPI channel bool R_SPI_Transfer uint8_t data1 Channel selection uint8_t data2 DMAC DTC control uint32_t data3 Transmit data start address uint32_t data4 Receive data start address uint16_t data5 Sequence loop count void func Callback function uint8_t data6 Interrupt priority level In Master mode transfer the data to and or from the Slave device In Slave mode transfer the data under control of the Master device data1 Select channel SPIn where n 0 only data2 Select the automatic data transfer options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_SPI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SPI_DMAC_TRIGGER_ENABLE or DMAC or DTC for data transmission PDL_SPI_DTC_TRIGGER_ENABLE and reception data3 The start address of the data to be transmitted The data must be stored as 32 bit values Specify PDL_NO_PTR if no data is to be transmitted or if the data content is not important or if the DMAC or DTC shall be used to handle the data transfer data4 The start address of the data to be received The data will be stored as 32 bit values Specify PDL_NO_PTR if no da
170. AC_BLOCK PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIXED PDL_DMAC_SIZE_ PDL_DMAC_IRQ_END PDL_DMAC_TRIGGER_SW data Source void amp DOC DODIR Destination T Transfer Count DATA_COUNT Data length PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Callback_Done Callback done function 7 Interrupt priority Enable and start the DMAC AC_Control DMAC_CHANNEL PDL_DMAC_ENABL PDL_DMAC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT R01US0059EG0111 Rev 1 11 Page 423 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Wait for the DMAC to complete while false g_bCallbackDone Read the result including checking for overflow R_DOC_Read amp status amp result Figure 59 Example of DOC R01US0059EG0111 Rev 1 11 Page 424 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 25 Multi Function Pin Controller Figure 60 shows an example of Multi Function Pin Controller usage Peripheral driver function prototypes include r_pdl_mpc h PDL device specific definitions include r_pdl_definitions h void main void uint8_t data Write data to register PO7PFS R_MPC_ Write PDL_MPC_REG_PO7PEFS Oxc5 i Set bit 3 in PO7PFS to 1 R_MPC_Modify PDL_MPC_REG
171. ATE_REPEAT_ SOURCE using parameter data8 Destination address extended repeat area using parameter data9 PDL_DMAC_UPDATE_REPEAT_DESTINATION data3 The new source address Specify PDL_NO_PTR if not required data4 The new destination address Specify PDL_NO_PTR if not required data5 The transfer count value Specify PDL_NO_DATA if not required R01US0059EG0111 Rev 1 11 Page 127 of 429 Aug 01 2014 RENESAS RX220 Group Description 2 2 4 Library Reference data6 The repeat or block size for each transfer Valid between 0 and 1023 0 1024 units Ignored in normal mode Specify PDL_NO_DATA if not required data7 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected Specify PDL_NO_DATA if not required data8 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if not required data9 The destination address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if not required Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_ Create Remarks e The Software trigger control is valid only if the Software trigger option has been selected e This function must be called in order to star
172. A_Create R_LVD_Create and R_LVD_Control e This function should not be called before R_CPA_Create e Donotuse VDET1 module and Comparator A channel 0 VDET2 and comparator A channel 1 at same time because they share the same registers See R_LVD_Create and R_LVD_ Control e The LVDi reset or LVDi non maskable interrupt should not be generated during flash memory programming erasure RPDL definitions include r_pdl_cpa h RPDL device specific definitions include r_pdl_definitions h void func void Disable Comparator A channel 0 R_CPA_Control 0 PDL_CPA_LVD_CIRCUIT_DISABLE Rev 1 11 REN ESAS Page 308 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description R_CPA_GetStatus Check the status of the Comparator A module bool R_CPA_GetStatus uint8_t data Status flags pointer Return the status flags Return value Category Reference Remarks Program example data The comparator A status flag shall be stored in the following format b7 b6 b5 b4 b3 b2 bi bO Status Change Status Change 0 0 CMPA2 lt CVREFA 0 None 0 0 CMPA1 lt CVREFA 0 None 1 CMPA2 2 CVREFA 1 Detected 1 CMPA1 2 CVREFA 1 Detected True Comparator A None e If the voltage change detection flag is set it is automatically cleared by this function RPDL d
173. All c Files of type Source File c Cancel Select the folder where you unzip the RPDL source file and open the source file under respective module folder Once the correct source file is selected user could step in to the file and step through the function R01US0059EG0111 Rev 1 11 Page 13 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 1 3 3 Header file inclusion The RPDL folder contains a header file iodefine_RPDL h This file is included by the RPDL source files and will also be included by any user generated files that call RPDL functions The main HEW project folder may contain the header file iodefine h This file is normally used if access to the I O registers in the MCU is required For any user generated files that call RPDL functions there is no need to include this file iodefine h 1 3 4 Header file order The file r_pdl_definitions h must be included after any peripheral specific header file For example Peripheral driver function prototypes and definitions include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h R01US0059EG0111 Rev 1 11 Page 14 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 1 3 5 Recommended initialisation code The RX tool chain has a designated function for MCU initialisation HardwareSetup During the MCU initialisation phase it is recommended that the following functions are placed
174. C trigger control R_MTU2_Create Revised restriction for buffer operation R_MTU2_ControlUnit Revise description of compare match clearing control to RO1USO059EG0111 Rev 1 11 Revision History 2 Aug 01 2014 RENESAS RX220 Group Revision History Description applies only to complementary PWM modes 1 R_MTU2_ControlUnit Add remark for the condition of TCDR and TDDR R_RTC_Create add new option Clock RTCOUT output period Select R_RTC_Create revise remarks gt Deleted remarks a Before calling this function the sub clock must be enabled and stable Hence use R_CGC_Set or R_CGC_Control to enable the sub clock and then allow the clock stabilization time to pass before calling this function If this function has been used and then a warm reset is performed it is not necessary to call this function again to continue using the RTC However if this function is to be called it is necessary to call R CGC_Set or R_CGC_Control to enable the sub clock even if it is already enabled before calling this function Call R_CGC_Set to set PCLKB clock frequency sub clock frequency when sub clock is source clock Call R_CGC_Set to set PCLKB clock frequency 2 sub clock frequency when sub clock is not source clock gt Add remarks a Before calling this function the count source must be enabled and stable Refer R_CGC_Set and R_CGC_Control for count source and stabilization time configuration b This function is called to use RTC afte
175. CNTV 1 Ignored for n 1 or 2 TGRE_TGRW_value For n 0 The register TGRE value For n 5 The register TGRW value If the corresponding channel is stopped make sure the value is not TCNTW 1 Ignored for n 1 2 3 or 4 TGRF_TADCORA_value For n 0 The register TGRF value For n 4 The register TADCORA value Ignored for n 1 2 3or5 TADCORB_value The register TADCORB value ignored for n 4 TADCOBRA_value The register TADCOBRA value ignored for n 4 TADCOBRB_value The register TADCOBRB value ignored for n 4 2tENESAS Page 161 of 429 RX220 Group Description 9 9 Return value 4 Library Reference func1 For n 0 to 4 The function to be called when a TGRA event occurs For n 5 The function to be called when a TGRU event occurs Specify PDL_NO_FUNC if not required func2 For n 0 to 4 The function to be called when a TGRB event occurs For n 5 The function to be called when a TGRV event occurs Specify PDL_NO_FUNC if not required func3 For n 0 3 or 4 The function to be called when a TGRC event occurs For n 5 The function to be called when a TGRW event occurs Specify PDL_NO_FUNC if not required func4 For n 0 3 or 4 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required interrupt_priority_1 The interrupt priority level for TGR A to D or U to W events
176. C_Create R01US0059EG0111 Rev 1 11 Page 347 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples PDL_NO_DATA 0x04110710 WED 11 07 10 0x20140116 20140116 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO DATA while 1 R_RTC_Read PDL_RTC_READ_CURR PDL_NO_PTR amp time amp date Figure 23 Example of configuration CGC and RTC counting by sub clock Only RTC count source in Calendar count mode R01US0059EG0111 Rev 1 11 Page 348 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 2 Configuration CGC and RTC counting by sub clock only RTC count source in binary count mode Figure 24 shows an example of sub clock used as count source and main clock used as system clock before using the Real time clock in Binary count mode PDL functions include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h PDL device specific definitions include r_pdl_definitions h void main void volatile uint8_t flags volatile uint32_t count alarm r_mask Prepare the main clock settings ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_ RESONATOR 20E6 20E6 20E6 20E6 20E6 PDL_NO_DATA Prepare the Sub clock settings R_CGC_Set DL_CGC_CLK_SUB_CLOCK DL_CGC_SUB_CLOCK_CL_STANDARD
177. C_ERROR_CLEAR R01US0059EG0111 Rev 1 11 Page 120 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 R_BSC_GetStatus Read the External Bus Controller status registers bool R_BSC_GetStatus uint8_t data1 The status register 1 storage location uint16_t data2 The status register 2 storage location Read the BSC status registers data1 The status flags shall be stored according to register BERSR1 format as below Specify PDL_NO_PTR if this information is not required b7 b6 b4 b3 b1 bO The bus master that caused the error Illegal address access 0 000 CPU 0 0 None 011 DTC or DMAC 1 Occurred data2 The status flags shall be stored according to register BERSR2 format as below Specify PDL_NO_PTR if this information is not required b15 b3 b2 b0 The upper 13 bits of the address that was accessed when the bus error occurred in units of 512 Kbytes True Bus Controller R_BSC_Control Call R_BSC_Control to clear the status registers after reading the status RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t statusl
178. C_IWDT_ENABLE CallBackFunc 10 Rev 1 11 REN ESAS Page 60 of 429 RX220 Group 4 Library Reference 3 R_INTC_CreateSoftwarelnterrupt Synopsis Enable use of the software interrupt Prototype bool R_INTC_CreateSoftwarelnierrupt uint8_t data1 Configuration void func Callback function uint8_t data2 Interrupt priority level Description Configure and enable the software interrupt data1 Choose the pin settings The default setting is shown in bold e DTC trigger control PDL_INTC_DTC_SW_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_INTC_DTC_SW_TRIGGER_ENABLE when a software interrupt is generated func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no interrupt is required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid otherwise false Category Interrupt control Reference R_INTC_Write Remarks Please see the notes on callback function use in 6 Specifying PDL_NO_FUNC for the callback function allows the software interrupt to be used as a DTC trigger e Use R_INTC_Write to generate the software interrupt Program example RPDL definitions include r_pdl_
179. C_READ_SKIP_ENABLE when the vector numbers match e Address size control PDL_DTC_ADDRESS_FULL or PDL_DTC_ ADDRESS SHORT Select 32 bit full or 24 bit Short address mode data2 The first address of the area of on chip RAM where the DTC vector table shall be stored The address must be on 1024 bytes boundary True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create Before calling R_DTC_Create call this function RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00000400 uint32_t dtc_vector_table 256 void func void Configure the controller R_DTC_Set PDL_DTC_ADDRESS_SHORT dtc_vector_table Rev 1 11 REN ESAS Page 132 of 429 RX220 Group 2 4 Library Reference R_DTC_Create Synopsis Configure the Data Transfer Controller for a transfer Prototype bool R_DTC_Create uint32_t data1 Configuration selection uint32_t data2 Transfer data start address void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint8_t data6 Block size Description 1 3 Configure DTC activation for one trigger source data1 Configuration selections If multiple sel
180. DL_DMAC_TRIGGER_IRQO void 0x0000AA00 void 0x0000BB00 10 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 R01US0059EG0111 Rev 1 11 Page 125 of 429 Aug 01 2014 RENESAS RX220 Group 2 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference R_DMAC_Desiroy Disable the DMA controller bool R_DMAC_Destroy uint8_t data Channel number J Shutdown the DMAC module data The channel number n where n 0 to 3 True if the shutdown succeeded otherwise false DMA controller R_DMAC_Create If all channels have been suspended the DMAC module will be shut down e Disabling the DMAC module will also shut down the DTC e If another peripheral is being used to trigger a DMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown DMAC channel 2 R_DMAC_Destroy 2 Rev 1 11 REN ESAS Page 126 of 429 RX220 Group 4 Library Reference 3 R_DMAC Conirol Synopsis Control the DMA controller Prototype bool R_DMAC_Control uint8_t data1 Channel number u
181. DL_INTC_NMI PDL_INTC_FALLING PDL_INTC_LVD2_ENABL NMI_handler_cpa 7 Non Maskable Interrupt Digital Filter interrupt enable LOCO_div_2 R_CPA_Create R01US0059EG0111 Rev 1 11 Page 420 of 429 Aug 01 2014 RENESAS RX220 Group L_ CPA_FILTER_LOCO_DIV_2 L_NO_FUNC FlagsNonMASKABL do if FlagsNonMASKABL break while 1l Disable comparator A channel R_CPA_Control 1 PDL_CPA_LVD_CIRCUIT_DISABL Maskable Interrupt Digital Filter R_CPA_Create 1 PDL_CPA_FILTER_LOCO_DIV_2 5 Usage Examples PDL_CPA_INTERRUPT_R PDL_CPA_INTERRUPT_RESET_ENABL PDL_CPA MASKABLE INTERRUPT CPA1_handler Get status LVDiDET LVDiMON R_CPA_GetStatus amp FlagsStatus while 1 Comparator A channel 0 void CPAO_handler void uint8_t FlagsStatus Get status LVDiDET LVDiMON R_CPA_GetStatus amp FlagsStatus Toggle the LED state R_IO_PORT_Modify PDL_IO_PORT L_IO_PORT_XOR R_IO_PORT_Modify PDL_IO_PORT L_IO_PORT_XOR Comparator A channel 1 void CPA1_handler void uint8_t FlagsStatus Get status LVDiDET LVDiMON R_CPA_GetStatus amp FlagsStatus Toggle the LED state L_IO_PORT_XOR R_IO_PORT_Modify PDL_IO_PORT R_IO_PORT_Modify PDL_IO_P
182. DL_LPC_SUB_65536 or PDL_LPC_SUB_131072 or PDL_LPC_SUB_262144 or PDL_LPC_SUB_524288 Select the oscillation settling time of the sub clock oscillator before the CPU resumes after exiting from software standby mode When updating this value the sub clock oscillator must be stopped Rev 1 11 REN ESAS Page 110 of 429 RX220 Group 4 Library Reference Description 3 3 data4 Select the HOCO oscillator waiting times If no selections are required specify PDL_NO_DATA e HOCO oscillator waiting time PDL_LPC_HOCO_40 or PDL_LPC_HOCO_72 or PDL_LPC_HOCO_104 or PDL_LPC_HOCO_136 or PDL_LPC_HOCO_180 or PDL_LPC_HOCO_200 or PDL_LPC_HOCO_232 or PDL_LPC_HOCO_264 or PDL_LPC_HOCO_296 or PDL_LPC_HOCO_ 328 or PDL_LPC_HOCO_360 or PDL_LPC_HOCO_392 or PDL_LPC_HOCO_424 or PDL_LPC_HOCO_456 or PDL_LPC_HOCO_488 or PDL_LPC_HOCO_520 or PDL_LPC_HOCO_ 3072 or PDL_LPC_HOCO_5120 or d PDL_LPC_HOCO_7168 or Stopped PDL_LPC_HOCO_9216 or PDL_LPC_HOCO_11264 or PDL_LPC_HOCO_13312 or PDL_LPC_HOCO_15360 or PDL_LPC_HOCO_17408 or PDL_LPC_HOCO_19456 or PDL_LPC_HOCO_21504 or PDL_LPC_HOCO_23552 or PDL_LPC_HOCO_25600 or PDL_LPC_HOCO_27648 or PDL_LPC_HOCO_29696 or PDL_LPC_HOCO_ 31744 or PDL_LPC_HOCO_ 33792 Select the oscillation settling time of the HOCO oscillator before the CPU resumes after exiting from software standby mode When updating this value the HOCO oscillator must be Ret
183. DL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or Select no action a reset PDL_LVD_INTERRUPT_NMI_DETECT_RISE or on low voltage detection PDL_LVD_INTERRUPT_NMI_DETECT_FALL or or an interrupt when a PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_FALL or specified voltage event is PDL_LVD_INTERRUPT_MI_DETECT_RISE or detected PDL_LVD_INTERRUPT_MI_DETECT_FALL or PDL_LVD_INTERRUPT MI DETECT RISE_AND_ FALL Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL LVD FILTER_LOCO DIV 2or PDL LVD FILTER_LOCO DIV 4or PDL_LVD_FILTER LOCO DIV 8 Configure the digital filter data2 Monitor 1 voltage detection level Specify PDL_NO_DATA if not required PDL_LVD_VOLTAGE_LEVEL_415 or PDL_LVD_VOLTAGE_LEVEL_400 or PDL LVD VOLTAGE LEVEL 385 or PDL LVD VOLTAGE LEVEL 370 or PDL LVD VOLTAGE LEVEL 355 or PDL LVD VOLTAGE LEVEL 340 or PDL LVD VOLTAGE LEVEL 325 or PDL LVD VOLTAGE LEVEL 310 or PDL LVD VOLTAGE LEVEL 295 or PDL LVD VOLTAGE LEVEL 280 or PDL LVD VOLTAGE LEVEL 265 or PDL LVD VOLTAGE LEVEL 250 or PDL LVD VOLTAGE LEVEL 235 or PDL LVD VOLTAGE LEVEL 220 or PDL LVD VOLTAGE LEVEL 205 or PDL LVD_VOLTAGE LEVEL 190 Set the voltage detection level For example PDL_LVD_VOLTAGE_LEVEL_415 4 15V Required only if the monitor is enabled Rev 1 11 RX220 Group Description 2 2 RO1US0059EG0111 Aug 01 2014 4 Library Reference
184. DL_MTU2 OUT BUFFER_N PHASE 2 HIGH PDL_MTU2_OUT BUFFER P_PHASE 3 LOWor MTIOC4B PDL_MTU2 OUT BUFFER P PHASE 3 HIGH PDL_MTU2_OUT BUFFER N_PHASE_3 LOWor MTIOC4D e Set the transfer timing In complementary PWM modes PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU2_OUT_BUFFER_TRANSFER_CREST or PDL_MTU2 OUT BUFFER TRANSFER BOTH Disable or enable on detection of crest PDL_MTU2_OUT_BUFFER_TRANSFER_TROUGH or trough or both In Reset synchronised PWM mode PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU2 OUT BUFFER TRANSFER CLEAR Disable or enable on counter clear e Buffer transfer to temporary transfer control Applicable for complementary PWM modes PDL_MTU2_BUFFER_TRANSFER_DISABLE or PDL_MTU2_BUFFER_TRANSFER_ENABLE or PDL MTU2 BUFFER TRANSFER LINK ski Disable transfers enable without linking to interrupt pping or enable and link to interrupt pping brushless _DC_motor_control Brushless DC motor control settings All settings are optional If multiple selections are required use to separate each selection Applies only to reset synchronised or complementary PWM modes e Brushless DC motor waveform control PDL_MTU2_BDCM_ENABLE or PDL_MTU2 BDCM_DISABLE Enable or disable brushless DC motor control PDL_MTU2_BDCM_P_PHASE_DISABLE positive PDL_MTU2_BDCM_P_PHASE_ENABLE or Enable or disable PWM outputs on the phase output pins PDL_MTU2
185. DL_NO_DATA Dummy DATA_LENGTH PDL_NO_FUNC Wait for Rx to finish while data_received false Process the received data here while 1 Callback function for Rx static void SCI_Rx_Callback void data_received true Callback function for Tx static void SCI_Tx_Callback void data_sent true Figure 36 Example of Synchronous Full Duplex operation R01US0059EG0111 Rev 1 11 Page 378 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 6 SCI Reception in Asynchronous Multi Processor mode This shows the setting of SCI channel 9 and the Multi Processor mode reception of data using interrupts and polling PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h y id SCIrx veid void SCIEr void define NUM_DATA 50 volatile uint8_t data_received volatile uint8_t error_happen volatile uint8_t receive_data_0 NUM_DATA volatile uint8_t receive_data NUM_DATA void main void uint8_t i bool id_received Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Pleas refer to 5 1 Clock Generation Circuit Initialise the receive buffer for i 0 i lt NUM_DATA i receive_data i 0 Set Channel 9 pin opt
186. DL_SP _LOOPBACK_DISABLE or PDL_SPI_LOOPBACK_DIRECT or PDL_SP _LOOPBACK_REVERSED Disable or enable loopback in direct or reversed mode data3 Extended timing control optional All items apply only to Master mode Specify PDL_NO_DATA if not required If multiple selections are required use to separate each selection Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK_DELAY_8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or The number of bit clock periods between the end of PDL_SPI_SSL_DELAY_4 or RSPCK oscillation and the negation of the active SSL PDL_SPI_SSL_DELAY_5 or pin PDL_SPI_SSL_DELAY_6 or Ignored in Slave mode PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY_8 Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 The number of bit clock periods plus two cycles of the peripheral clock between the end of one frame and the s
187. DL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT1 The channel n n 0 1 2 or 3 or unit n n 0 or 1 to be configured data2 Configure the timer Use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Output pin control For the duration of the one shot period generate a PDL_TMR_OUTPUT_HIGH or high level output PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PULSE_DTC_TRIGGER_ENABLE DTC when the one shot period ends e Control the CPU during the one shot operation PDL_TMR_CPU_ON or Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts The CPU will re start when any valid interrupt occurs PDL_TMR_CPU_OFF data3 The one shot time period in seconds func The function to be called when the one shot period ends Specify PDL_NO_FUNC for this function to wait for the timer to complete before returning You should always specify a function if PDL_TMR_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This param
188. DTC R_IIC_MasterReceive IIC_CHANNEL PDL_IIC_DTC_TRIGG EEPROM_ADDRESS PDL_NO_PTR 0 iic_rx_end_handler 7 while g_IIC_Rx_busy true This callback is registerd with R_IIC_MasterSend We have configured the DTC to pass on the interrupt when it has transfered all data to the IIC so this will be called then This will also get called when the last byte has been transmitted by the IIC When the last byte has been sent it is our job to issue a IIC stop void iic_tx_end_handler void Process according to state switch g_IIC_Tx_State case IIC_TX_STATE_WAIT_DTC DTC has finished transfer so now wait for last byte to be transmitted g_IIC_Tx_State IIC_TX_STATE_WAIT_LAST_BYTE break case IIC_TX_STATE_WAIT_LAST_BYTE uint32_t status_flags 0 Wait for the transmission to fully complete do R_IIC_GetStatus TIC_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x0080u 0x0u Issue a Stop condition R_IIC_Control IIC_CHANNEL PDL_IIC_STOP R01US0059EG0111 Rev 1 11 Page 401 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples This master write has completed g_IIC_Tx_State IIC_TX_STATE_FINISHED break default Not expected hi This callback is registerd with R_IIC_
189. DTC DMAC does not ensure the end of transmission e After using this function use R_SPI_GetStatus to check for and clear any error flags Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t transmit_data 8 uint32_t receive_data 8 Transmit and receive all enabled frames onc R_SPI_Transfer 0 PDL_NO_DATA transmit_data receive_data 1 PDL_NO_FUNC 0 Rev 1 11 2tENESAS 4 Library Reference e The amount of data for must match the total number of transfer frames refer to parameter Page 288 of 429 RX220 Group 4 Library Reference 6 Synopsis Prototype Description Return value Category R_SPI_Conirol Control an SPI channel bool R_SPI_Control uint8_t data1 uint8_t data2 uint32_t data3 Channel selection Control options Extended timing control Modify the operation of the selected SPI channel data1 Select channel SPIn where n 0 only data2 Control the channel If multiple selections are required use to separate each selection All items are optional Specify PDL_NO_DATA if not required e Channel control PDL_SPI_ DISABLE Disable and partially initialise the SPI channel e Loopback control P
190. DTC_TRIGGER_TGICO or PDL_DTC_TRIGGER_TGIC3 or PDL_DTC TRIGGER TGIC4 or Compare match or input capture C on MTU channel n n 0 3 or 4 PDL_DTC TRIGGER TGIDO or PDL_DTC TRIGGER TGID3 or PDL DTC TRIGGER TGID4 or Compare match or input capture D on MTU channel n n 0 3 or 4 PDL_DTC_TRIGGER_TGIU5 or Compare match or input capture U on MTU channel 5 PDL_DTC_TRIGGER_TGIV5 or Compare match or input capture V on MTU channel 5 PDL_DTC_TRIGGER_TGIW5 or PDL_DTC_TRIGGER_TCIV4 or Compare match or input capture W on MTU channel 5 Counter over or underflow on MTU channel 4 PDL_DTC_TRIGGER_CMIAO or PDL_DTC_TRIGGER_CMIA1 or PDL_DTC_TRIGGER_CMIA2 or PDL_DTC_TRIGGER_CMIA3 or PDL_DTC_TRIGGER_CMIBO or PDL_DTC_TRIGGER_CMIB1 or PDL_DTC_TRIGGER_CMIB2 or PDL_DTC_TRIGGER_CMIB3 or Compare match A on TMR channel n n 0 to 3 Compare match B on TMR channel n n 0 to 3 PDL_DTC_ TRIGGER DMACIO or PDL_DTC TRIGGER DMACI1 or PDL_DTC TRIGGER _DMACI2 or PDL_DTC TRIGGER DMACI3 or Transfer complete on DMAC channel n n 0 to 3 PDL_DTC_TRIGGER_RXI1 or PDL_DTC_TRIGGER_RXI5 or PDL_DTC_TRIGGER_RXI6 or Receive buffer full on SCI channel n PDL_DTC_TRIGGER_RXI9 or PDL_DTC_TRIGGER_RXI12 or n 1 5 6 9 or 12 PDL_DTC_TRIGGER_TXI1 or PDL DTC TRIGGER TXI5 or PDL_DTC TRIG
191. ELC Control Control the ELC 1 R_MTU2 Set Configure the Multi function Timer Pulse Units 2 R_MTU2_ Create Configure a MTU channel Multi function 3 R_MTU2_Destroy Disable a Multi function Timer Pulse Unit Timer pulse unit 4 R_MTU2_ControlChannel Control an MTU channel l 5 R_MTU2_ControlUnit Control a Multi function Timer Pulse Unit 6 R_MTU2_ReadChannel Read from MTU channel registers 7 R_MTU2_ReadUnit Read from MTU registers 1 R_POE_Set Configure the Port Output Enable module Port Output Enable 2 R_POE_Create Configure the Port Output Enable event handling 3 R_POE Control Control the Port Output Enable module 4 R_POE_GetStatus Check the module status 1 R_TMR_Set Configure the optional TMR pins 2 R_TMR_CreateChannel Configure a TMR timer channel 3 R_TMR_CreateUnit Configure a TMR timer unit 4 R_TMR_CreatePeriodic Select periodic operation 5 R_TMR_CreateOneShot Configure and use a one shot timer 8 bit Timer 6 R_TMR_Destroy Disable a TMR timer unit 7 R_TMR_ControlChannel Write to timer channel registers 8 R_TMR_ControlUnit Write to timer unit registers 9 R_TMR_ControlPeriodic Control periodic operation 10 R_TMR_ReadChannel Read from timer channel registers 11 R_TMR_ReadUnit Read from timer unit registers 1 R_CMT_Create Configure a CMT channel Compare Match 2 R_CMT_CreateOneShot Configure a CMT channel as a one shot event Timer 3 R_CMT_Destroy Disable a CMT unit 4 R_CMT_Control Control CMT operation 5 R_CMT_Read Read CMT channel
192. ENCY and pulse width or frequency and duty cycle PDL_TMR_PERIOD or The parameters data3 and data4 will contain either period Output pin control PDL_TMR_OUTPUT_HIGH or Start with a high level or PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 Pulse DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PULSE_DTC_TRIGGER_ENABLE DTC at the pulse width interval Period DTC trigger control PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR PERIOD DTC TRIGGER ENABLE DTC at the periodic interval data3 The period in seconds or frequency in Hz data4 The pulse width in seconds or duty cycle func1 The function to be called at the pulse width interval Use PDL_NO_FUNC if not required func2 The function to be called at the periodic interval Use PDL_NO_FUNC if not required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_ FUNC is specified for both parameters func1and func2 Return value Category RO1US0059EG0111 Aug 01 2014 True if all parameters are valid and exclusive otherwise false Timer TMR Rev 1 11 REN ESAS Page 192 of 429 RX220 Group 4 Library
193. ER TMR2 CMIB PDL_INTC_REG DTCER_ICU_IRQ7 PDL_INTC_REG DTCER TMR3 CMIA PDL_INTC_REG DTCER S12AD_S12ADI PDL_INTC_REG DTCER TMR3 CMIB PDL_INTC_REG DTCER S12AD GBADI PDL_INTC_REG DTCER DMAC_DMACOI PDL_INTC_REG DTCER ELC ELSRi18l PDL_INTC_REG DTCER DMAC_DMACII PDL_INTC_REG DTCER MTUO TGIA PDL_INTC_REG DTCER DMAC_DMAC2I PDL_INTC_REG DTCER MTUO TGIB PDL_INTC_REG DTCER DMAC_DMACSI PDL_INTC_REG_DTCER_MTUO_TGIC PDL_INTC_REG DTCER SCI1_RxI PDL_INTC_REG DTCER MTUO TGID PDL_INTC_REG DTCER MTU1_TGIA PDL_INTC_REG DTCER SCI1_ TX PDL_INTC_REG DTCER SCI5 RxI PDL_INTC_REG_DTCER_MTU1_TGIB PDL_INTC_REG DTCER SCI5 TXI PDL_INTC_ REG DTCER MTU2 TGIA PDL_INTC_REG DTCER SCI6 RxI PDL_INTC_REG DTCER MTU2 TGIB PDL_INTC_REG DTCER SCI6_TXI PDL_INTC_REG DTCER MTU3 TGIA PDL_INTC_REG DTCER SCI9 RxI PDL_INTC_REG DTCER MTU3 TGIB PDL_INTC_ REG DTCER SCI9 TXI PDL_INTC_REG_DTCER_MTU3_TGIC PDL_INTC_REG DTCER SCI12 RxI PDL_INTC_REG DTCER MTU3 TGID PDL_INTC_REG DTCER SCI12 TI R01US0059EG0111 Rev 1 11 Aug 01 2014 PDL_INTC_REG DTCER IICO_RXI PDL_INTC_REG_DTCER_IICO_TXI 2tENESAS Page 71 of 429 RX220 Group 4 Library Reference 8 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 0
194. FALLING or PDL_INTC_RISING or PDL_INTC_BOTH Select Low level Falling edge Rising edge or Falling and rising edge detection DMAC DTC trigger control Not enabled if low level detection is selected PDL_INTC_DMAC_DTC_TRIGGER_DISABLE or PDL_INTC_DMAC_TRIGGER_ENABLE or PDL_INTC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a valid edge transition is detected on a valid IRQn pin Options which only apply to the NMI e Pin enable and input sense selection PDL_INTC_FALLING or PDL_INTC_RISING Enable the NMI pin and select falling or rising edge detection Required only if the NMI pin is to be used Internal detection control PDL_INTC_OSD_DISABLE or PDL_INTC_OSD_ENABLE Disable or enable the NMI signal when the oscillation stop detection interrupt occurs PDL_INTC_IWDT_DISABLE or PDL_INTC_IWDT_ENABLE Disable or enable the NMI signal when an IWDT underflow interrupt occurs PDL_INTC_LVD1_ DISABLE or PDL_INTC_LVD1_ ENABLE Disable or enable the NMI signal when a low voltage detection 1 interrupt occurs PDL_INTC_LVD2_DISABLE or PDL_INTC_LVD2_ENABLE Disable or enable the NMI signal when a low voltage detection 2 interrupt occurs func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no IRQn interrupt is required A function must be specified for the NMI Rev 1 11 RX220 Group 4 Library
195. GC_Set is omitted her refer to 5 1 Clock Generation Circuit Set Channel 9 pin options R_SCI_Set CHANNEL SCI_IIC PDL_SCI_PT SCI9_RXD9_PB6 PDL SCI PI SCI9_TXD9_PB7 Configure the SCI IIC Channel R_SCI_Create CHANNEL _SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 Set up data buffer for the write Address in EEPROM ITIC_Buffer 0 EEPROM_ADDRESS Data to write IIC_Buffer 1 EEPROM VALUE IIC write R_SCI_IIC_Write CHANNEL _SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 2 IIc_Buffer PDL_NO_FUNC Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 0 R01US0059EG0111 Rev 1 11 Page 384 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples E 3 DL_NO_FUNC Confirm this write worked by reading back the data from the El 1 Set current EEPROM address IIC_Buffer 0 EEPROM_ADDRESS R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 1 IIc_Buffer PDL_NO_FUNC 2 Read data from current address R_SCI_IIC_Read CHANNEL SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 1 IIc_Buffer PDL_NO_FUNC Confirm the value written is the same as the value read if IIC_Buffer 0 EEPROM_VALUE User
196. GER TXI6 or Transmit buffer empty on SCI channel n PDL_DTC_ TRIGGER TXI9 or PDL DTC TRIGGER TXI12 or n 1 5 6 9 or 12 PDL_DTC_TRIGGER_IICO_RX or Receive buffer full on 12C channel 0 PDL_DTC TRIGGER IICO TX Transmit buffer empty on 2C channel 0 Rev 1 11 2tENESAS Page 134 of 429 RX220 Group Description 3 3 Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 Rev 1 11 4 Library Reference data2 The start address of the transfer data area It must be a multiple of 4 For short address mode 12 bytes are required to store the transfer data For full address mode 16 bytes are required data3 The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers data6 The size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Set R_DTC_Control e If address increment or decrement is selected the addr
197. GTH 25 const char master_data_to_be_sent SPI master const char slave_data_to_be_sent SPI slave void main void uint32_t master_tx_data BUFFE uint32_t master_rx_data BUFFE static uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Configure the slave SPI IO pin R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PAT7 i Configure the master SPI channel R_SPI_Create STER_CHANNEL L_SPI_MODE_SYNC_MASTER L_SPI_FRAME 1 1 __NO_DATA E6 Configure the Master R_SPI_Command MASTER_CHANNE 0 PDL_SPI_CLOC E_1 PDL_SPI_LENGTH_8 PDL_SPI_LSB_FIRST PDL_NO_DATA Clear the receive buffers for i 0 i lt BUFFER_LENGTH i master_rx_data i 0x00000000 Copy the source data into the transmit buffers for i 0 i lt strlen master_data_to_be_sent i R01US0059EG0111 Rev 1 11 Page 411 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples master_tx_data i uint32_t master_data_to_be_sent i Transfer all data once by polling R_SPI_Transfer MASTER_CHANNE PDL_NO_DATA master_tx_data master_rx_data uint16_t strlen master_data_to_be_sent PDL_NO_FUNC 0
198. HANNEL 2 or PDL_ELC_LINK_MODULE_MTU2_CHANNEL_3 or PDL_ELC_LINK_MODULE_MTU2_CHANNEL 4 or PDL_ELC_LINK_MODULE_TMR_CHANNEL_0 or PDL_ELC_LINK_MODULE_TMR_CHANNEL_2 or Select the module to PDL_ELC_LINK_MODULE_ADC12 or remove the link from PDL_ELC_LINK_MODULE_INTERRUPT_1 or PDL_ELC_LINK_MODULE_OUTPUT_PORT_B_ GROUP or PDL_ELC_LINK_MODULE_INPUT_PORT_B_ GROUP or PDL_ELC_LINK_MODULE_SINGLE_PORT_0 or PDL_ELC_LINK_MODULE_SINGLE_PORT_1 or Operation data1 PDL_ELC_TIMER_OPERATION data2 Timer selection PDL_ELC_TIMER_MTU2_CHANNEL_1 or PDL_ELC_TIMER_MTU2_CHANNEL 2 or PDL_ELC_TIMER_MTU2_CHANNEL _3 or PDL_ELC_TIMER_MTU2_CHANNEL 4 or PDL_ELC_TIMER_TMR_CHANNEL_O or PDL_ELC_ TIMER_TMR CHANNEL 2 Select the timer to configure data3 e Timer operation PDL_ELC_TIMER_COUNT_START or PDL_ELC_TIMER_COUNT_RESTART or PDL_ELC_TIMER_EVENT_COUNTER or Select the timer operation when triggered PDL_ELC_TIMER_INPUT_CAPTURE or PDL_ELC_TIMER_EVENT_DISABLE Operation data1 PDL_ELC_PORT_GROUP data2 e Select the port PDL_ELC_PORT_B Select a port whose bits will make up a port group data3 e Select the bits which define the port group b31 b8 b7 b0 Not used Bit mask where a high bit selects the bit as part of the port group R01US0059EG0111 Rev 1 11 REN ESAS Page 147 of 429 Aug 01 2014 RX220 Group 4 Library Reference Description 4 5 Operation
199. I PIN SCI6 SMISO6 P33 or PDL_SCI_PIN SCI6 SMISO6 PBO SMISO6 PDL SCI PIN SCI6 SSCL6 P33 or a PDL_SCI_PIN SCI6 SSCL6_PBO PDL SCI PIN SCI6 TXD6 P32 or ane PDL_SCI PIN SCI6 TXD6 PB1 PDL SCI PIN SCI6 SMOSI6 P32 or PDL SCI PIN_SCI6_SMOSI6_PB1 Sa SMOSI6 PDL SCI PIN SCI6 SSDA6 P32 or Ronee PDL_SCI_PIN SCI6 SSDA6 _PB1 PDL SCI PIN SCI6 SCK6 P34 or ae PDL SCI PIN SCI6 SCK6 PB3 PDL SCI_PIN SCI6 CTS6 PB or ae PDL SCI PIN SCI6 CTS6 PJ3 PDL SCI PIN SCI6 RTS6 PB2 or ae PDL SCI PIN SCI6 RTS6 PU3 PDL SCI PIN SCI6 SS6 PB2 or PDL SCI PIN SCI6 SS6 PJ3 Valid when n 9 PDL_SCI PIN SCI9_RXD9_PB6 RXD9 PDL SCI PIN_SCI9_SMISO9_PB6 SMISO9 PDL SCI PIN_SCI9_SSCL9_PB6 SSCL9 PDL SCI PIN_SCI9_TXD9_PB7 TXD9 PDL SCI PIN SCI9 SMOSI9 PB7 Sai SMOSI9 PDL SCI PIN SCI9 SSDA9 PB7 SSDAQ PDL SCI PIN SCI9_SCK9 PB5 SCK9 PDL SCI PIN SCI9 CTS9 PB4 CTS9 PDL SCI PIN_SCI9_RTS9_PB4 RTS9 PDL SCI PIN_SCI9_S59_PB4 S59 Rev 1 11 REN ESAS Page 237 of 429 RX220 Group 4 Library Reference Description 2 2 e Valid when n 12 PDL_SCI_PIN_SCl12_RXD12_PE2 PDL_SCI_PIN_SCl12_SMISO12_PE2 PDL_SCI_PIN_SCl12_SSCL12_PE2 PDL_SCI_PIN_SCl12_TXD12_PE1 PDL_SCI_PIN_SCl12_SMOSI12_PE1 PDL_SCI_PIN_SCl12_SSDA12_PE1 PDL_SCI_PIN_SCl12_SCK12_ PEO PDL_SCI_PIN_SCl12_CTS12_PE3 PDL_SCI_PIN_SCl12_RTS12_PE3 PDL_SCI_PIN_SCl12_SS12_PE3 SCl12 RXD12 SMI
200. IIC Mode selected Use the functions R_SCI_IIC_Read and R_SCI_IIC_Write not R_SCl_Send or R_SCI_ Receive Options which are available in Clock Synchronous and SPI mode e Data clock source selection Select the On chip baud rate generator PDL_SCI_CLK_INT_OUT or The SCKn pin outputs the bit clock In SPI Mode this is Master mode Input the clock to the SCKn pin In SPI Mode this is Slave mode PDL_SCI_CLK_EXT SPI Clock Polarity Inversion PDL_SCl_CLOCK_POLARITY_INVERTED The SCK clock is inverted SPI Clock Phase Dela PDL_SCI_CLOCK_PHASE_DELAYED The SCK clock is delayed Options which are available in Clock Synchronous mode Not SPI or IIC Hardware Flow Control Select the Hardware Flow Control Option Notes PDL_SCI_HW_FLOW_NONE or PDL_SCI_HW_FLOW_CTS or PDL_SCI_HW_FLOW_RTS e CTS can only be selected if using an internal clock source for SCLK e RTS can only be selected if using external clock source for SCLK Options which are available in SPI mode e SPI SS Pin PDL_SCI_SPI_SS_DISABLE or The SS pin is not used Single master or single slave environment The SS pin is used PDL_SCI_SPI_SS_ENABLE Note This option is not available if using SPI Master mode if selected the function will return false Data inversion PDL_SCI_INVERSION_OFF or PDL_SCI_INVERSION_ON Control data inversion transmission and reception
201. INTC_REG_IPR_SCI12_SCIX1 PDL_INTC_REG_IPR_RTC_ALM PDL_INTC_REG_IPR_SCl12_SCIX2 PDL_INTC_REG_IPR_RTC_PRD PDL_INTC_REG_IPR_SCI12_SCIX3 PDL_INTC_REG_IPR_S12AD_S12ADI PDL_INTC_REG_IPR_IICO_EEI PDL_INTC_REG_IPR_S12AD_GBADI PDL_INTC_REG_IPR_IICO_RXI PDL_INTC_REG_IPR_ELC_ELSR18I PDL_INTC_REG_IPR_IICO_TXI PDL_INTC_REG_IPR_MTU0O_TGIAD PDL_INTC_REG_IPR_IICO_TEIl PDL_INTC_REG_IPR_MTUO_TCIVF R01US0059EG0111 Rev 1 11 RENESAS Aug 01 2014 Page 70 of 429 RX220 Group DTCER register definitions 4 Library Reference PDL_INTC_REG DTCER ICU_SWINT PDL_INTC_REG_DTCER_MTU4_ TGIA PDL_INTC_REG_DTCER_CMT0O_CMI PDL_INTC_REG_DTCER_MTU4 TGIB PDL_INTC_REG DTCER CMT1_CMI PDL_INTC_REG_DTCER_MTU4_TGIC PDL_INTC_REG DTCER CMT2 CMI PDL_INTC_REG_DTCER_MTU4 TGID PDL_INTC_REG DTCER CMT3 CMI PDL_INTC_REG_DTCER_MTU4_TCIV PDL_INTC_REG DTCER SPIO _SPRI PDL_INTC_REG_DTCER_MTU5_TGIU PDL_INTC_REG_DTCER_SPI0_SPTI PDL_INTC_REG_DTCER_ICU_IRQO PDL_INTC_REG_DTCER_MTU5_TGIV PDL_INTC_REG_DTCER_MTU5_TGIW PDL_INTC_REG_DTCER_ICU_IRQ1 PDL_INTC_REG DTCER TMRO CMIA PDL_INTC_REG DTCER ICU_IRQ2 PDL_INTC_REG DTCER TMRO CMIB PDL_INTC_REG_DTCER_ICU_IRQ3 PDL_INTC_REG DTCER TMR1 CMIA PDL_INTC_REG_DTCER_ICU_IRQ4 PDL_INTC_REG DTCER_TMR1_CMIB PDL_INTC_REG_DTCER_ICU_IRQ5 PDL_INTC_REG DTCER TMR2 CMIA PDL_INTC_REG_DTCER_ICU_IRQ6 PDL_INTC_REG DTC
202. INT_OUT or baud rate generator SCKn pin SCI bit clock output Input a clock of 8 or 16 times the desired bit rate to the ea ae eed SCKn pin See parameter data3 for the multiplier selection For SCI5 select Timer output TMOO0 TMO1 For SCI6 select Timer output TMO2 TMO3 For SCI12 select Timer output TMOO TMO01 The SCKn pin is set to high impedance PDL_SCI_CLK_TMR Data length PDL_SCI_8 BIT_LENGTH or PDL_SCI_7_BIT_LENGTH 8 or 7 bit data length Rev 1 11 REN ESAS Page 239 of 429 RX220 Group 4 Library Reference Description 2 4 e Parity mode PDL_SCI_PARITY_NONE or No parity bit even parity bit or odd parity bit PDL_SCI_PARITY_EVEN or Note Do not set parity bit for Multi Processor PDL_SCI_PARITY_ODD Asynchronous mode e Start bit edge detection PDL_SCI_START_DETECT_LOW_LEVEL or The low level or a falling edge on the PDL_SCI_START_DETECT_FALLING_EDGE RXDn pin is detected as the start bit e Stop bit length PDL_SCI_STOP_1 or PDL_SCI_STOP_2 One or two stop bits The option PDL_SCI_8N1 can be used to select 8 bit data length no parity and one stop bit Options which are available in all Clock Synchronous modes including IIC and SPI e SPI mode selection PDL_SCI_SPI_ MODE SPI Mode selected Use the R_SCI_SPI_Transfer function not R_SCI_ Send or R_SCI_ Receive IIC mode selection PDL_SCI_IIC_MODE
203. IWDTLOCO IWDT low speed on chip oscillator for measurement RO1USO059EG0111 Rev 1 11 REN ESAS Page 106 of 429 Aug 01 2014 RX220 Group 4 Library Reference Description 2 2 Measured clock division selection Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 PDL_CAC_MEASURE_DIV_1 or PDL_CAC_MEASURE_DIV_4 or Divide the clock to be measured by 1 4 8 or PDL_CAC_MEASURE_DIV_8 or 32 PDL_CAC_MEASURE_DIV_32 Limit value calculation PDL_CAC_LIMIT_TOLERANCE or Parameters data3 and data4 will contain either PDL_CAC_LIMIT_REGISTER the tolerance or the limit register values data3 If selected in parameter data2 specify either a the maximum positive deviation for the measured clock as a percentage or b the upper count limit for the measured clock where the maximum value is 65535 If not required specify PDL_NO_DATA data4 If selected in parameter data2 specify either a the maximum negative deviation for the measured clock as a percentage or b the lower count limit for the measured clock where the maximum value is 65535 If not required specify PDL_NO_DATA True if all parameters are valid and exclusive otherwise false Clock frequency accuracy measurement circuit R_CAC_Create e If signal selection or limit value changes are required the measurement operation must be
204. I_PIN_SSL1_LOW or Select active low or active high PDL_SPI_PIN_SSL1_HIGH or for output signal SSL1 PDL_SPI_PIN_SSL2_LOW or Select active low or active high PDL_SPI_PIN_SSL2_HIGH or for output signal SSL2 PDL_SPI_PIN_SSL3_LOW or Select active low or active high PDL_SPI_PIN_SSL3_HIGH or for output signal SSL3 PDL_SPI_PIN_MOSI_IDLE_LAST or cig PDL SPI PIN MOSI IDLE LOW or T output state when no SSLn pin is PDL_SPI_PIN_MOSI_IDLE_HIGH R01US0059EG0111 Rev 1 11 REN ESAS Page 281 of 429 Aug 01 2014 RX220 Group Description 2 3 RO1US0059EG0111 Aug 01 2014 data3 Configure the data format If multiple selections are required use to separate each selection The default settings are shown in bold 4 Library Reference Buffer size PDL_SPI_BUFFER_64 or Select a buffer size of 64 bits up to four 16 bit frames or PDL_SPI_BUFFER_128 128 bits up to four 32 bit frames Frame configuration selection refer to Table 29 4 in the hardware manual Number of Number of frames in Number of Selection command each command transfer transfers transfer frames PDL_SPI_FRAME_1_1 or 1 1 1 PDL_SPI_FRAME_1 2 or 1 2 2 PDL_SPI_FRAME_1_3 or 1 3 3 PDL_SPI_FRAME_1_ 4 or 1 4 4 PDL_SPI_FRAME_2_1 or 2 1 2 PDL_SPI_FRAME_2 2 or 2 2 4 PDL_SPI_FRAME_3 or 3 1 3 PDL_SPI_FRAME_4 or 4 1 4 PDL_SPI_FRAME_5 or 5 1 5 PDL_SPI_FRAME_6 or 6 1 6 PDL_SPI_FRAME_7 or 7 1 7 PDL_SPI_FRAME_8 8 1 8 Parity bit
205. I_Send RSK_SCI_CHANNEL PDL_NO_DATA r nRTC Start in Cold start mode Initialize RTC r n 0 PDL_NO_FUNC if R_RTC_Create PDL_RTC_ALARM_ TIME ENABLE PDL_RTC_ALARM DATE _ENABL OxFF114250 Automatic day of week 11 42 50 0x20131118 18 Nov 2013 PDL_NO_DATA Periodic OxFF114300 Alarm in 10 seconds 0x20131118 18 Nov 2013 Alarm_handler 15 PDL_NO_FUNC PDL_NO_DATA false R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA r nRTC_Create error in Cold start mode r n 0 PDL_NO_FUNC while 1 After the complete initialization Set the warm start indicator R_MCU_Control PDL_MCU_WARM_START R01US0059EG0111 Rev 1 11 Page 364 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples This call should cancel the settings made in above call to R_LPC_Create R_LPC_Create PDL_LPC_MIDDLE_SPEED_MODE_A PDL_NO_DATA L_NO_DATA PDL_NO_DATA R_RTC_Read PDL_RTC_READ_CURRI PDL_NO_PTR amp time amp date Enter software standby mode after alarm in 10sec while bSoftStdbyEnter false Enter software standby mode An internal reset will occur if false R_LPC_Control PDL_LPC_MODE_SOFTWARE_STANDBY while 1 while 1 Read time R_RTC_Read PDL_RTC_READ_CURRENT amp flags amp time amp date If no carry error output
206. If using an event to start the 8 Bit Timer then to stop it use function R_ TMR_ControlChannel with PDL_LTMR_ELC_COUNT_STOP selected e If another peripheral or port will be used to generate an event or to be triggered by an event then that peripheral or port must be configured accordingly before calling this function e Only the following events can be selected to trigger an ELC Interrupt PDL_ELC_LINK_EVENT_INPUT_PORT_GROUP_B or PDL_ELC_LINK_EVENT_SINGLE_INPUT_PORT_0 or PDL_ELC_LINK_EVENT_SINGLE_INPUT_PORT_1 or PDL_ELC_LINK_EVENT_SOFTWARE_EVENT e An ELC interrupt can trigger the DTC or the DMAC but not both at the same time If triggering the DTC use PDL_ELC_TRIGGER to enable the DTC trigger Some peripheral channels and port pins are not available on some device packages Please check the hardware manual e The event signals selected by PDL_ELC_LINK_EVENT_SCI5 RECEIVE_DATA_FULL and PDL_ELC_LINK_EVENT_SCI5_ TRANSMIT_DATA_EMPTY depend on the SCI5 operation mode Please refer to section 27 12 in the RX220 hardware manual e Event PDL_ELC_LINK_EVENT_SCI5 RECEIVE_DATA_FULL cannot be used if SCI5 is configured for IIC Mode This function will return false if this condition is detected e Event PDL_ELC_LINK_EVENT_SPI_TRANSMIT_END cannot be used if RSPI is in slave mode of clock synchronous operation This function will return false if this condition is detected e If a timer event link is no longer required use PDL_ELC_TIMER_EVENT_DISABLE to disab
207. L_INTC_REG_IER1C PDL_INTC_REG_IEROE PDL_INTC_REG_IER1D PDL_INTC_REG_IEROF PDL_INTC_REG_IER1E PDL_INTC_REG_IER1F IPR register definitions PDL_INTC_REG_IPR_BSC_BUSERR PDL_INTC_REG_IPR_MTU1_TGIAB PDL_INTC_REG_IPR_FCU_FIFERR PDL_INTC_REG_IPR_MTU1_TCIVU PDL_INTC_REG_IPR_FCU_FRDYI PDL_INTC_REG_IPR_MTU2_TGIAB PDL_INTC_REG_IPR_ICU_SWINT PDL_INTC_REG_IPR_MTU2_TCIVU PDL_INTC_REG_IPR_CMTO_CMI PDL_INTC_REG_IPR_MTU3_TGIAD PDL_INTC_REG_IPR_CMT1_CMI PDL_INTC_REG_IPR_MTU3 TCIV PDL_INTC_REG_IPR_CMT2_CMI PDL_INTC_REG_IPR_MTU4_TGIAD PDL_INTC_REG_IPR_CMT3_CMI PDL_INTC_REG_IPR_MTU4_TCIV PDL_INTC_REG_IPR_CAC_FERRF PDL_INTC_REG_IPR_MTU5_TGl PDL_INTC_REG_IPR_CAC_MENDF PDL_INTC_REG_IPR_POE_OEI1 PDL_INTC_REG_IPR_CAC_OVFF PDL_INTC_REG_IPR_POE_OEIl2 PDL_INTC_REG_IPR_SPIO PDL_INTC_REG_IPR_TMRO PDL_INTC_REG_IPR_DOC_DOPCF PDL_INTC_REG_IPR_TMR1 PDL_INTC_REG_IPR_RTC_CUP PDL_INTC_REG_IPR_TMR2 PDL_INTC_REG_IPR_ICU_IRQO PDL_INTC_REG_IPR_TMR3 PDL_INTC_REG_IPR_ICU_IRQ1 PDL_INTC_REG_IPR_DMAC_DMACOI PDL_INTC_REG_IPR_ICU_IRQ2 PDL_INTC_REG_IPR_DMAC_DMAC1I PDL_INTC_REG_IPR_ICU_IRQ3 PDL_INTC_REG_IPR_DMAC_DMAC2I PDL_INTC_REG_IPR_ICU_IRQ4 PDL_INTC_REG_IPR_DMAC_DMAC3I PDL_INTC_REG_IPR_ICU_IRQ5 PDL_INTC_REG_IPR_SCI1 PDL_INTC_REG_IPR_ICU_IRQ6 PDL_INTC_REG_IPR_SCI5 PDL_INTC_REG_IPR_ICU_IRQ7 PDL_INTC_REG_IPR_SCI6 PDL_INTC_REG_IPR_LVD_LVD1 PDL_INTC_REG_IPR_SCI9 PDL_INTC_REG_IPR_LVD_LVD2 PDL_INTC_REG_IPR_SCI12 PDL_INTC_REG_IPR_CMPA_CMPA1 PDL_INTC_REG_IPR_SCI12_SCIX0 PDL_INTC_REG_IPR_CMPA_CMPA2 PDL_
208. Library Reference Configure the Real time clock in calendar count mode Set up and start the Real time clock in calendar count mode PDL_RTC_24 HOUR_MODE or PDL_RTC_12 HOUR MODE Select 12 or 24 hour mode Alarm enabling PDL_RTC_ALARM_HOUR ENABLE PDL_RTC_ALARM_MINUTE_ENABLE PDL_RTC_ALARM SECOND ENABLE All three can be enabled using PDL_RTC_ALARM_TIME_ENABLE PDL RTC ALARM YEAR ENABLE PDL_RTC_ALARM MONTH ENABLE PDL_RTC_ALARM DAY ENABLE PDL_RTC_ALARM DOW ENABLE All four can be enabled using PDL_RTC_ALARM_DATE_ENABLE Clock output control PDL_RTC_OUTPUT_DISABLE or PDL_RTC_OUTPUT_ENABLE Disable or enable the 1 Hz 64 Hz clock output on the RTCOUT pin Clock RTCOUT output period Select PDL_RTC_OUTPUT_RTCOS_1HZ or PDL_RTC_OUTPUT_RTCOS_64HZ RTCOUT outputs 1 Hz RTCOUT outputs 64 Hz Configure RTCOUT Pin Select PDL_NO_DATA if no pins are required PDL_RTC_OUTPUT_ENABLE will not be a valid option if select PDL_NO DATA PDL_RTC_PIN_RTCOUT_P16 or PDL_RTC_PIN_RTCOUT_P32 If using the RTCOUT pin then select the port to use for it Rev 1 11 2 ENESAS Page 215 of 429 RX220 Group Description 2 3 data2 4 Library Reference The current day of the week DOW and time in hours minutes and seconds BCD format is used The format is dependent upon if using 12 hour or 24 hour mode
209. M RY_ADDRESS_UPPER 0x00 define EEPROM RY_ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM_MEMORY_ADDRESS_UPP define IIC_CHANNEL 0 volatile uint8_t bus_busy volatile uint8_t data_storage 20 void main void define ARRAY_1_ SIZE 6 5 Data bytes 1 address define ARRAY_2_ SIZE 11 10 Data bytes 1 address const uint8_t eeprom_data_array_1 ARRAY_1_S1ZI EEPROM_MEMORY_ADDRESS_LOWER 0x11 0x22 0x33 0x44 0x55 const uint8_t eeprom_data_array_2 ARRAY_2_SIZE EEPROM MEMORY_ADDRESS_LOWER 5 0x06 0x07 0x08 0x09 0x0A 0x0B Ox0C 0x0D 0x0 Ox0F uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Select IIC Pins R_IIC_Set PDL_IIC_PIN_SDA_ P13 PDL_IIC_PIN_SCL_P12 Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_NORMAL PDL_DMAC_SIZE_8 PDL IAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIX PDL_DMAC_IRQ_END DL_DMAC_TRIGGER_IICO_TX eprom_data_array_l uint8_t amp RIICO ICDR 1 RRAY_ 1 SIZE DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA c_tx_dmac_end_handler aH tU UU tO SP OU H Set up a DMAC channel for IIC reception This will re
210. MCU_OFS_IWDT TIMEOUT_1024 or PDL_MCU_OFS_IWDT TIMEOUT_4096 or PDL_MCU_OFS_IWDT TIMEOUT_ 8192 or PDL_MCU_OFS_IWDT TIMEOUT_16384 Timeout period specified in cycles of the divided clock as specified in the Clock division selection below Clock division PDL_MCU_OFS_IWDT CLOCK_LOCO_1 or PDL_MCU_OFS_IWDT CLOCK_LOCO_16 or PDL_MCU_OFS_IWDT CLOCK_LOCO_32 or PDL_MCU_OFS_IWDT CLOCK_LOCO_64 or PDL_MCU_OFS_IWDT CLOCK_LOCO_128 or PDL_MCU_OFS_IWDT CLOCK_LOCO_256 The selected clock The LOCO 1 16 32 64 128 or 256 Window end position PDL_MCU_OFS_IWDT_WIN_END_75 or The window end position specified as a PDL_MCU_OFS_IWDT_WIN_END_50 or percentage of the down counter 0 is when PDL_MCU_OFS_IWDT_WIN_END_25 or the down counter would underflow Selecting PDL_MCU_OFS_IWDT_WIN_END_0 0 is equivalent to no window end position Window start position PDL MCU OFS IWDT WIN START 25 or The window start position epee asa PDL MCU OFS IWDT WIN START 50 or percentage of the down counter 0 is PDL MCU OFS IWDT WIN START 75 or when the down counter would underflow PDL MCU OFS IWDT WIN START 100 Selecting 100 is equivalent to no window start position Underflow action PDL_MCU_OFS_IWDT_NMI or Select an NMI or reset when the IWDT PDL_MCU_OFS_IWDT_RESET down counter underflows Count stop mode
211. MR n 1 PDL_TMR_CLK_TMR2_CM_A Valid for n 1 or 3 e Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL TMR CLEAR RESET RISING or ag by arising edge on the external reset pin PDL TMR CLEAR RESET HIGH oe when the external reset pin TMRIn is Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_TMR_CM_A_DTC_TRIGGER_ENABLE when a Compare Match A occurs Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_TMR_CM_B DTC_TRIGGER_ENABLE when a Compare Match B occurs RO1USOO59EG0111 Rev 1 11 REN ESAS Page 186 of 429 Aug 01 2014 RX220 Group Description 2 2 data3 4 Library Reference Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Output control for pin TMOn PDL_TMR_OUTPUT_IGNORE_CM_A or PDL_TMR_OUTPUT_LOW_CM_ Aor PDL_TMR_OUTPUT_HIGH_CM Aor PDL_TMR_OUTPUT_INV_CM_A No change if a compare match A occurs 0 is output if a compare match A occurs 1 is output if a compare match A occurs The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNO
212. MasterReceive void iic_rx_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DTC_GetStatus dtc_iicl_rx_transfer_data PDL_NO_PTR PDL_NO_PTR tAddr PDL_NO_PTR PDL_NO_PTR Read one more byte with NACK condition and stop R_IIC_MasterReceiveLast IIC_CHANNEL uint8_t DestAddr g_IIC_Rx_busy false Figure 49 An example of writing data to and reading data from an EEPROM using the DTC R01US0059EG0111 Rev 1 11 Page 402 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 19 4 Slave mode In this example the MCU behaves as a virtual slave memory device on channel 0 It will respond to 7 bit address 0001001b The sample is interrupt driven after the initial setup Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h Define the size of the virtual memory define STORAGE SIZE 0x100 define RX _BUFFER_SIZE STORAGE SIZE 1 fine SLAVE HANNEL 0 iC define SLAVE_ADDRESS 0xBO static void slave_callback void static void StoreData uintl6_t count Current memory address volatile uint8_t data_storage_index 0 volatile uint8_t data_storage STORAGE_SIZ volatile uint8_t Rx_Buffer RX_BUFFER_SIZ
213. NK EVENT SCI5_RECEIVE_DATA_FULL or PDL ELC LINK EVENT SCI5_TRANSMIT_DATA_EMPTY or PDL ELC LINK EVENT SCI5_TRANSMIT_END or PDL ELC LINK EVENT IIC_ERROR_OR_EVENT or PDL ELC LINK EVENT IIC_RECEIVE_DATA_FULL or PDL ELC LINK EVENT IIC_TRANSMIT_DATA_EMPTY or PDL ELC LINK EVENT IIC_TRANSMIT_END or PDL ELC LINK EVENT SPI_ERROR or PDL ELC LINK EVENT SPI_IDLE or PDL ELC LINK EVENT SPI_RECEIVE_DATA_FULL or PDL ELC LINK EVENT SPI_TRANSMIT_DATA_EMPTY or PDL ELC LINK EVENT SPI_TRANSMIT_END or PDL ELC LINK EVENT ADC12_CONVERSION_END or PDL ELC LINK EVENT LVD1_VOLTAGE_DETECTION or PDL ELC LINK EVENT DTC_TRANSFER_END or or PDL ELC LINK EVENT INPUT_PORT_GROUP_B or PDL ELC LINK EVENT SINGLE_INPUT_PORT_0 or PDL ELC LINK EVENT SINGLE_INPUT_PORT_1 or PDL ELC LINK EVENT SOFTWARE_EVENT or PDL ELC LINK EVENT DOC Select the event that will trigger the module Rev 1 11 2 ENESAS Page 146 of 429 RX220 Group 4 Library Reference Description 3 5 Operation data1 PDL_ELC_REMOVE_LINK data2 e Module Selection PDL_ELC_LINK_MODULE_MTU2_CHANNEL_1 or PDL_ELC_LINK_MODULE_MTU2_C
214. NNEL PDL_NO_DATA slave_tx_data slave_rx_data 1 spi_slave_callback 15 slave_transfer_complete false while slave_transfer_complete false for i 0 i lt 4 i Did the Master output match the Slave input if master_tx_data i slave_rx_data i Handle the error while 1 while 1 void spi_slave_callback void uintl6_t StatusValue 0 uintl6_t Sequence_count Read the slave channel status R_SPI_Get Status SLAVE_CHANNEL amp StatusValue amp Sequence_count No errors if StatusValue amp 0x000Du 0x0u slave_transfer_complete true else Handle the error while 1l Figure 52 Example of Serial Peripheral Interface Transfer of 32 bit Data by Slave R01US0059EG0111 Rev 1 11 Page 410 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 20 2 Synchronous transfer with 8 bit data Figure 53 shows how strings of 8 bit data are copied into 32 bit buffers then transmitted and received simultaneously by the master The received data is then checked to confirm that the transfer was successful Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_spi h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt define MASTER_CHANNEL 0 define BUFFER_LEN
215. NO_FUNC 0 Select the HOCO as the clock source R_CGC_Control PDL_CGC_CLK_HOCO PDL_NO_DATA L_CGC_SUB_CLOCK_DISABLE PDL_CGC_RTC_NOT_USI Figure 28 Example of initialization of not using RTC without providing clock R01US0059EG0111 Rev 1 11 Page 357 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 16 3 Use case of RTC over reset and power comsumption 1 Wake up from sleep mode Figure 29 shows an example of using the Real time Clock wake up from sleep mode The sub clock is used as RTC count source and HOCO is set as system clock include lt stdio h gt include lt string h gt PDL functions include r_pdl_cgc h include r_pdl_lpc h include r_pdl_cmt h include r_pdl_mcu h include r_pdl_rtc h include r_pdl_sci h PDL device specific definitions include r_pdl_definitions h define RSK_SCI_CHANNEL 1 static void SetClocks void static void Alarm_handler void volatile bool bEnterSleepMode false void main void uint8_t flags uint32_t time uint32_t date uint32_t time_previous 0 uint8_t buffer 50 uintl6_t status 0 Sets system clock SetClocks Create async for debug output R_SCI_Set RSK_SCI_CHANNEL PDL_SCI_PIN_SCI1_RXD1 PDL_SCI_PIN_SCI1_TXD1 R_SCI_Create RSK_SCI_CHANNEL PDL_SCI_8N1 PDL_SCI_ASYNC 9600 1 Check warm cold star
216. N_ANO10_PE2 Select PE2 for ANO10 PDL_ADC_12_PIN_ANO11_PE3 Select PE3 for ANO11 PDL_ADC_12_PIN_ANO12_PE4 Select PE4 for ANO12 PDL_ADC_12_PIN_ANO13_PE5 Select PE5 for ANO13 PDL_ADC_12_PIN_ANO14_ PE6 Select PE6 for ANO14 PDL_ADC_12_PIN_ANO15_PE7 Select PE7 for ANO15 PDL_ADC_12_PIN_ADTRGO_P07 or PDL_ADC_12_PIN_ADTRGO_P16 or Select P07 P16 or P25 for ADTRGO PDL_ADC_12_PIN_ADTRGO_P25 Return value True if all parameters are valid and exclusive otherwise false Category 12 bit ADC Reference R_ADC_12_CreateUnit Remarks e If there are I O pins to be used call this function before calling R ADC_12_CreateUnit e Device packages with 64 or fewer pins do not have all of the pin options Program example RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Set analog channel ANOOO R_ADC_12_Set PDL_ADC_12_ PIN_ANOOO0_P40 R01US0059EG0111 Rev 1 11 Page 296 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_ADC_12_CreateUnit Synopsis Prototype Description 1 4 R01US0059EG0111 Aug 01 2014 Configure the 12 bit ADC unit bool R_ADC_12_CreateUnit Unit selection Unit specific options Options for Group A Options for Group B uint8_t data1 uint32_t data2 uint32_t data3 uint32_t data4 ference volta
217. O1US0059EG0111 Aug 01 2014 fpciks MHz IRC 50 48 12 5 12 32 8 PCLKB 1 658 kbps to 635 6 kops 175 kbps to 168 5 kbps to 446 kbps to 116 kbps to 1 Mbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps PCLKB 2 316 kbps to 306 kbps to 86 7 kbps to 83 6 kbps to 217 kbps to 57 8 kbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps PCLKB 4 175 kbps to 168 5 kbps 45 9 kbps to 44 2 kbps to 116 kbps to 30 0 kbps to 1 Mbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 806 kbps PCLKB 8 86 7 kbps to 83 6 kbps to 23 7 kbps to 22 7 kbps to 57 8 kbps to 15 3 kbps to 1 Mbps 1 Mbps 658 kbps 635 6 kbps 1 Mbps 446 kbps PCLKB 16 45 9 kbps to 44 2 kbps to 12 0 kbps to 11 5 kbps to 30 0 kbps to 7 73 kbps to 1 Mbps 1 Mbps 316 kbps 306 1 kbps 806 kbps 217 kbps PCLKB 32 23 7 kbps to 22 7 kbps to 6 06 kbps to 5 8 kbps to 15 3 kbps to 3 89 kbps to 658 kbps 635 6 kbps 175 kbps 168 5 kbps 446 kbps 116 kbps PCLKB 64 12 0 kbps to 11 5 kbps to 3 04 kbps to 2 9 kbps to 7 73 kbps to 1 95 kbps to 316 kbps 306 1 kbps 86 7 kbps 83 6 kbps 217 kbps 57 8 kbps PCLKB 128 6 06 kbps to 5 82 kbps to 1 52 kbps to 1 5 kbps to 3 89 kbps to 975 bps to 175 kbps 168 5 kops 45 9 kbps 44 2 kbps 116 kbps 30 0 kbps RPDL definitions include r_pdl_iic h RPDI include void func void Rev 1 11 Select IIC mode at 100kHz R_IIC_Create 0 PDL_IIC_MOD PDL_NO_DAT PDL_NO_DATA PDL_NO_DATA PDL_N
218. OCO_POWER_ON or PDL_CGC_HOCO POWER OFF Control the HOCO power supply e Main clock oscillator control PDL_CGC_MAIN_ENABLE or PDL_CGC_MAIN DISABLE Enable or disable the main clock oscillator e Main clock Oscillation Stop Detection contro PDL_CGC_OSC_STOP_ENABLE or Enable without or with interrupt request output PDL_CGC_OSC_STOP_INTERRUPT or or disable the oscillation stop detection function PDL_CGC_OSC_STOP_DISABLE for the main clock oscillator e Main clock Oscillation Stop Detection flag control PDL CGC OSC STOP CLEAR FLAG id the main clock oscillation stop detection data3 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection e Sub clock oscillator control Ignore for 48 pin package PDL_CGC_SUB_CLOCK_ENABLE or PDL_CGC_SUB_CLOCK_DISABLE Enable or disable the sub clock oscillator e IWDT dedicated low speed on chip oscillator control PDL_CGC_IWDTLOCO_ENABLE or PDL_CGC_IWDTLOCO_ DISABLE Enable or disable the IWDTLOCO Rev 1 11 REN ESAS Page 54 of 429 RX220 Group Description 2 2 4 Library Reference RTC initialization control PDL_CGC_RTC_TO_BE_USED or PDL_CGC_RTC_NOT_ USE Select whether RTC will be used Return value Category References R
219. ORT L_IO_PORT_XOR void NMI_handler_cpa void uint8_t irq_status R01US0059EG0111 Rev 1 11 Aug 01 2014 RENESAS interrupt enable 1 1 1 1 LOCO_div_2 Page 421 of 429 RX220 Group 5 Usage Examples Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL_INTC_NMI irg_status FlagsNonMASKABLE Figure 58 Example of Comparator A R01US0059EG0111 Rev 1 11 Page 422 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 24 Data Operation Circuit This shows the configuration of the DOC and the DMAC to sum an array of numbers PDL functions include r_pdl_doc h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h define DMAC_CHANNEL 0 define DATA_COUNT 10 extern void Callback_Done void Data to calculate sum of static uint1l6_t data DATA_COUNT 1 2 3 4 5 6 7 8 9 10 Callback Flag static volatile bool g_bCallbackDone false void main void uint8_t status uintl6_t result Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Setup the DOC in addition mode initial value 0 R_DOC_Create PDL_DOC_MODE_ADD 0 PDL_NO_FUNC 0 Setup DMAC to write data to the 16bit DOC Input register R_DMAC_Create DMAC_CHANNEL PDL_DM
220. O_DATA 100E3 100 lt lt 16 A f E_IIC L device specific definitions r pdl_definitions h PDL_IIC_INT_PCLK_DIV_8 100 Select IIC mode with two slave addresses R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_SLAVE_0O_ENABLE_7 0x0020 0x0056 PDL_NO_DATA 100E3 300 lt lt 16 200 2tENESAS PDL _IIC_SLAVE 1_ENABLE 100ns rise and fall times Page 267 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 R_lIC_Destroy Disable an 2C channel bool R_IIC_Destroy uint8_t data Channel selection Shut down the selected I2C module data Select channel IICn where n 0 True if the parameter is valid otherwise false 2C None The l C module is put into the power down state RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown IIC channel 0 R_IIC_Destroy 0 3 Rev 1 11 RENESAS Page 268 of 429 RX220 Group 4 Library Reference 4 R_IIC_MasterSend Synopsis Write data to a slave de
221. P34PFS PDL_MPC_REG_PD3PFS PDL_MPC_REG_P40PFS PDL_MPC_REG_PD4PFS PDL_MPC_REG_P41PFS PDL_MPC_REG_PD5PFS PDL_MPC_REG_P42PFS PDL_MPC_REG_PD6PFS PDL_MPC_REG_P43PFS PDL_MPC_REG_PD7PFS PDL_MPC_REG_P44PFS PDL_MPC_REG_PEOPFS PDL_MPC_REG_P45PFS PDL_MPC_REG_PE1PFS PDL_MPC_REG_P46PFS PDL_MPC_REG_PE2PFS PDL_MPC_REG_P47PFS PDL_MPC_REG_PE3PFS PDL_MPC_REG_P54PFS PDL_MPC_REG_PE4PFS PDL_MPC_REG_P55PFS PDL_MPC_REG_PES5PFS PDL_MPC_REG_PAOPFS PDL_MPC_REG_PE6PFS PDL_MPC_REG_PA1PFS PDL_MPC_REG_PE7PFS PDL_MPC_REG_PA2PFS PDL_MPC_REG_PHOPFS PDL_MPC_REG_PA3PFS PDL_MPC_REG_PH1PFS PDL_MPC_REG_PA4PFS PDL_MPC_REG_PH2PFS PDL_MPC_REG_PA5PFS PDL_MPC_REG_PH3PFS PDL_MPC_REG_PA6PFS PDL_MPC_REG_PJ1PFS PDL_MPC_REG_PA7PFS PDL_MPC_REG_PJ3PFS R01US0059EG0111 Rev 1 11 Aug 01 2014 2 ENESAS Page 88 of 429 RX220 Group 1 Synopsis Prototype Description Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference R_MPC_Read Read an MPC register bool R_MPC_Read uint8_t data1 MPC register selection uint8_t data2 Pointer to the variable where the MPC register s
222. PDATE SOURCE aoo Address register using parameter PDL_DTC_UPDATE_DESTINATION Wa a Address register using parameter PDL_DTC_UPDATE_COUNT The Transfer Count register using parameter data5 PDL_DTC_UPDATE_BLOCK_SIZE The Block Size register using parameter data6 e Transfer trigger control When the transfer count specified in R_DTC_Create is completed the DTC will ignore further interrupts from that trigger source If you require the interrupt to trigger another transfer specify the trigger used in the relevant call of R_DTC_Create data2 If transfer registers are to be modified specify the start address of the transfer data area the same as that declared in R_DTC_Create If no registers are to be modified specify PDL_NO_PTR data3 The new source start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data4 The new destination start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data5 The new number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers Specify PDL_NO_DATA if not required data6 The new size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode Specify PDL_NO_DATA if not required True if all parameters are valid and
223. PDL_POE_IRQ_HI_Z_0 3 DISABLE PDL_POE_IRQ_HI_Z_0 3 ENABLE Control interrupts on detection of any high impedance request on pins POEO to POES PDL_POE_IRQ_HI_Z_8 DISABLE PDL_POE_IRQ_HI_Z_ 8 ENABLE Control interrupts on detection of a high impedance request on pin POE8 Output short detection response PDL_POE_IRQ_SHORT_3 4 DISABLE PDL_POE_IRQ_SHORT_3_4 ENABLE Control interrupts on detection of a short on any MTU channel 3 or 4 two phase output pair Return value True if all parameters are valid and exclusive otherwise false Category Port Output Enable Reference Remarks Call R_POE_Create before using this function e Clearing a level triggered event flag will fail if the trigger is still asserted e Interrupt disabling is processed at the start of the function and enabling is processed at the end This allows a flag to be cleared and the interrupt re enabled in one function call R01US0059EG0111 Rev 1 11 Page 181 of 429 Aug 01 2014 2 ENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void Select high impedance on the MTUO I O pins R_POE_Control PDL_POE_MTUO_HI_Z_ON PDL_NO_DATA PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 182
224. PERIODIC_1_HZ or PDL_RTC_ PERIODIC 2S The frequency or interval for periodic interrupt requests Real time clock True if all parameters are valid and exclusive otherwise false R_RTC_CreateBinary R_RTC_ReadBinary This function is not available in calendar count mode If the current count values are updated the RTC is stopped during the update If entering software standby mode soon after modifying the RTC values use R_RTC_ReadBinary first to confirm that the values are correct If the output of the RTCOUT pin is enabled or disabled the clock is stopped during the update This function is called after R_RTC_CreateBinary or R_RTC_CreateWarm This function is not required when using 48 pin package RPDL definitions include r_pdl_rtc h RPDI void func void Rev 1 11 L device specific definitions include r_pdl_definitions h Disable the alarm and update the alarm count R_RTC_ControlBinary PDL_NO_DATA PDL_NO_DATA 0x23456789 update the alarm count PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA RX220 Group 4 Library Reference 6 Synopsis Prototype Description Return value R_RTC_Read Read the Real time clock status flags and counters bool R_RTC_Read uint8_t data1 Specify what to read uint8_t data2 A pointer to the flags storage location uint32_t data3 A pointer to t
225. PORT_ModifyControl R01US0059EG0111 Rev 1 11 Aug 01 2014 RENESAS 5 Usage Examples Page 321 of 429 RX220 Group 5 Usage Examples PDL_IO_PORT_ PDL_IO_POR ECTION PDL_IO_PORT_OR Ox0F Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL IO PORT _A_ 3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR Figure 5 Examples of I O Port Operations R01US0059EG0111 Rev 1 11 Page 322 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 4 MCU Operation Figure 6 shows an example of MCU usage It detects if a Cold start has occurred Peripheral driver function prototypes include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void main void uint1l6_t mode_status uintl6_t reset_status Read the MCU status registers R_MCU_Get Status mode_status amp reset_status PDL_NO_PTR PDL_NO_PTR Cold start if reset_status amp BIT_8 0 Set the warm start indicator R_MCU_Control PDL_MCU_WARM_START Reset the MCU R_MCU_Control PDL_MCU_RESET_START Figure 6 Example of MCU operation R01US0059EG0111 Rev 1 11 Page 323 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 5 Voltage Detection Circuit 5 5 1 Maskable interrupts This shows an example of Voltage detection circuit usage If the supply voltage drops below 2
226. R 0x50 RENES S Page 74 of 429 RX220 Group 4 Library Reference 4 2 3 1 O Port I O Port functions may operate on a complete port or on individual port pins The available definitions are listed below I O port definitions PDL_IO_PORT_0 Port PO PDL_IO_PORT_5 Port P5 PDL_IO_PORT_D Port PD PDL_IO_PORT_1 Port P1 PDL_IO_PORT_A Port PA PDL_IO_PORT_E Port PE PDL_IO_PORT 2 Port P2 PDL_IO_PORT_B Port PB PDL_IO_PORT_H Port PH PDL_IO_PORT_3 Port P3 PDL_IO_PORT_C Port PC PDL_IO_PORT_J Port PJ PDL_IO_PORT_4 Port P4 Note Refer to the hardware manual for the ports which are available on the device that you have selected I O port pin definitions PDL IO_ PORT 0 3 PortpinPO PDL_IO PORT 4 0 PortpinP4 PDL_IO PORT C_0 Portpin PCo PDL_IO_PORT_0 5 PortpinPOs PDL IO PORT 41 PortpinP4 PDL IO PORT C1 Portpin PC PDL IO PORT 0 7 Portpin PO PDL IO PORT 4 2 PortpinP42 PDL_IO PORT C 2 PortpinPC2 PDL_IO PORT 4 3 PortpinP4 PDL_IO PORT C3 Portpin PC PDL IO PORT 1 2 PortpinP12 PDL IO PORT 4 4 PortpinP4 PDL_IO PORT C 4 Portpin PC PDL_IO PORT 1 3 PortpinPis PDLIO PORT 45 P
227. RE_CM_B or PDL_TMR_OUTPUT_LOW_CM Bor PDL_TMR_OUTPUT_HIGH_CM_B or PDL_TMR_OUTPUT_INV_CM_B No change if a compare match B occurs 0 is output if a compare match B occurs 1 is output if a compare match B occurs The output toggles if a compare match B occurs data4 The counter value data5 The compare match A value data6 The compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for all parameters func1 func2 and funcs Return value Category Timer TMR Reference R_TMR_Set Remarks e Please use R_TMR_Set to select the input TMCIn TMRIn and output TMOn pins as required This function will return false if a pin is enabled but is not set properly e A closed clock loop will be created if The overflow signal from TMR1 is selected for TMRO and the compare match A signal from TMRO is selected for TMR1 or The overflow signal from TMR3 is selected for TMR2 and the compare match A signal from TMR2 is selected for TMR3 Either case should be avoided e The output will be
228. RIGGER_SW or By software PDL_DTC_TRIGGER_CMTO0 or PDL_DTC_TRIGGER_CMT1 or PDL_DTC_TRIGGER_CMT2 or PDL_DTC_TRIGGER_CMT3 or Compare match on channel CMTn n 0 to 3 PDL_DTC_TRIGGER_SPIO_RX or Receive buffer full on SPI channel 0 PDL_DTC_TRIGGER_SPIO_TX or Transmit buffer empty on SPI channel 0 RO1USO059EG0111 Rev 1 11 REN ESAS Page 133 of 429 Aug 01 2014 RX220 Group 4 Library Reference Description 2 3 PDL_DTC_TRIGGER_IRQO or RO1US0059EG0111 Aug 01 2014 PDL_DTC_TRIGGER_IRQ1 or PDL_DTC TRIGGER_IRQ2 or PDL_DTC_TRIGGER_IRQ3 or PDL_DTC_TRIGGER_IRQ4 or PDL_DTC_TRIGGER_IRQ5 or PDL_DTC_TRIGGER_IRQ6 or PDL_DTC_TRIGGER_IRQ7 or Valid edge detected on pin IRQn n 0 to 7 PDL DTC TRIGGER _ADC12 or Conversion completed on the 12 bit ADC unit PDL_DTC_TRIGGER_ADC12_GBADI or Conversion completed on group B of the 12 bit ADC unit PDL_DTC TRIGGER ELSR18I or Event link interrupt PDL_DTC_TRIGGER_TGIAO or PDL DTC TRIGGER TGIA1 or PDL_DTC_TRIGGER_TGIA2 or PDL_DTC_TRIGGER_TGIA or PDL_DTC_TRIGGER_TGIA4 or Compare match or input capture A on MTU channel n n 0 to 4 PDL_DTC_TRIGGER_TGIBO or PDL_DTC TRIGGER TGIB1 or PDL_DTC_TRIGGER_TGIB2 or PDL_DTC_TRIGGER_TGIB3 or PDL_DTC_TRIGGER_TGIB4 or Compare match or input capture B on MTU channel n n 0 to 4 PDL_
229. R_RTC_Read first to confirm that the values are correct e If the output of the RTCOUT pin is enabled or disabled the clock is stopped during the update e This function is called after R_RTC_Create or R_RTC_CreateWarm e This function is not required when using 48 pin package R01US0059EG0111 Rev 1 11 Page 223 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the alarm calendar and update the alarm time R_RTC_Control PDL_RTC_ALARM_DATE_DISABLE L_RTC_UPDATE_ALARM_TIME L_NO_DATA L_NO_DATA x00105300 Alarm at 10 53 L_NO_DATA L_NO_DATA L_NO_DATA Oo Uw vuNtronttw s e e a Change the day to the 23rd R_RTC_Control PDL_NO_DATA PDL_RTC_UPDATE_CURRENT_DOW PDL_RTC_UPDATE_CURRENT_DAY OxFFO00000 0x00000023 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO DATA R01US0059EG0111 Rev 1 11 Page 224 of 429 Aug 01 2014 RENESAS RX220 Group 5 Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 4 Library Reference R_RTC_ControlBinary Modify the RTC operation in binary count mode bool R_RTC_ConitrolBinary uint32_t data1 Control sel
230. R_SCIl12_RXI PDL_INTC_REG_IR_MTU1_TCIU PDL_INTC_REG_IR_SCl12_TXI PDL_INTC_REG_IR_MTU2_TGIA PDL_INTC_REG_IR_SCl12_TEl PDL_INTC_REG_IR_MTU2_TGIB PDL_INTC_REG_IR_SCl12_SCIXO PDL_INTC_REG_IR_MTU2_TCIV PDL_INTC_REG_IR_SCl12_SCIx1 PDL_INTC_REG_IR_MTU2_TCIU PDL_INTC_REG_IR_SCl12_SCIX2 PDL_INTC_REG_IR_MTU3_TGIA PDL_INTC_REG_IR_SCl12_SCIX3 PDL_INTC_REG_IR_MTU3_TGIB PDL_INTC_REG_IR_IICO_EEI PDL_INTC_REG_IR_MTU3_TGIC PDL_INTC_REG_IR_IICO_RXtI PDL_INTC_REG_IR_MTU3_TGID PDL_INTC_REG_IR_IICO_TXI PDL_INTC_REG_IR_MTU3_TCIV PDL_INTC_REG_IR_IICO_TEI R01US0059EG0111 Rev 1 11 RENESAS Aug 01 2014 4 Library Reference Page 69 of 429 RX220 Group IER register definitions 4 Library Reference PDL_INTC_REG_IER02 PDL_INTC_REG_IER10 PDL_INTC_REG_IERO3 PDL_INTC_REG_IER11 PDL_INTC_REG_IER04 PDL_INTC_REG_IER15 PDL_INTC_REG_IERO5 PDL_INTC_REG_IER16 PDL_INTC_REG_IERO7 PDL_INTC_REG_IER17 PDL_INTC_REG_IER08 PDL_INTC_REG_IER18 PDL_INTC_REG_IEROB PDL_INTC_REG_IER19 PDL_INTC_REG_IEROC PDL_INTC_REG_IER1B PDL_INTC_REG_IEROD PD
231. Reference Reference R_CGC_Set R_TMR_CreateChannel R_TMR_CreateUnit Remarks e Function R_CGC_Set must be called with the current clock source selected before using this function e This function is an alternative to R TMR_CreateChannel and R_TMR_CreateUnit e Please use R_TMR_Set to select the output TMOn pin as required This function will return false if a pin is enabled but is not set properly e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 e The timing limits depend on the peripheral module clock PCLKB fecike MHz Equation 12 5 12 1 Timer resolution 80ns 83 3ns 125ns Jpc 2 Periodmin 160ns 166 7ns 250ns Jpc 2 Period MAX_CHANNEL 167 7ms 174 8ms 262ms frcr xe 32 Period MAX_UNIT 42 9s 44 7s 67 1s Srcrxs Width min Period min Width max_cHaNNeL Periodmax CHANNEL Width max_unit Period max_uNIt fmax dats 6 25 MHz 6 MHz 4 MHz MIN_CHANNEL dego 5 96 Hz 5 7 Hz 3 81 Hz MIN_UNIT L 0 0232 Hz 0 0224 Hz 0 0149 Hz e f the requested period is not a multiple of the timer resolution the actual time period will be more than the requested time period e The actual duty cycle will be less than the requested duty cycle if the resulting pulse width is not a multiple of the timer resolution e Acallback function is executed by the interrupt processing function This means
232. S Page 205 of 429 Aug 01 2014 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint1l6_t Counter uintl6_t CompareMatchA uintl6_t CompareMatchB void func void Read the status flags and registers for TMR unit 0 R_TMR_ReadUnit 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB R01US0059EG0111 Rev 1 11 Page 206 of 429 Aug 01 2014 RENESAS RX220 Group 4 2 17 1 Synopsis Prototype Description Return value 4 Library Reference Compare Match Timer R_CMT_Create Configure a CMT channel bool R_CMT_Create uint8_t data1 Timer channel selection uint16_t data2 Configuration selection double data3 Period frequency or register data void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold e Clock calculation The parameter data3 will specify the timer period PDL_CMT_PERIOD or The counter clock source and compare match value will be calculated by this function The parameter data3 wi
233. SO12 SSCL12 TXD12 SMOSI12 SSDA12 SCK12 CTS12 RTS12 SS12 True if all parameters are valid and exclusive otherwise false Program example Return value Category SCI Reference R_SCI_Create Remarks e Before calling R_SCI_Create if using SCI channel 1 5 6 9 or 12 call this function to configure the relevant pins e Pins which are not used for the SCI functions may be omitted e This function configures each specified SCI pin It also disables the alternative modes on those pins e Please refer to the Multifunction Pin Controller MPC section in the RX220 Hardware Manual for details of SCI pin selection e Not all pins are available on all device package sizes include r_pdl_sci h void func void Configure RXD1 and TXD1 pins R_SCI_Set 1 PDL_SCI_PIN_SCI1_RXD1_P15 PDL_SCI_PIN_SCI1_TXD1_P16 3 RO1US0059EG0111 Aug 01 2014 Rev 1 11 2tENESAS Page 238 of 429 RX220 Group 2 Synopsis Prototype Description 1 4 RO1US0059EG0111 Aug 01 2014 4 Library Reference R_SCI_Create SCI channel setup bool R_SCI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Bit rate or register value uint8_t data4 Interrupt priority level Set up the selected SCI channel data1 Select chan
234. SPI channel 0 Transmit buffer empty PDL_INTC_VECTOR_SPIIO Idle PDL_INTC_VECTOR_DOPCF Data operation Condition detection PDL_INTC_VECTOR_CUP Carry PDL_INTC_VECTOR_ALM Real time clock Alarm PDL_INTC_VECTOR_PRD Periodic PDL_INTC_VECTOR_IRQO PDL_INTC_VECTOR_IRQ1 PDL_INTC_VECTOR_IRQ2 PDL_INTC_VECTOR_IRQ3 Interrupt Valid edge or level detected on an PDL_INTC_VECTOR_IRQ4 controller external interrupt pin PDL_INTC_VECTOR_IRQ5 PDL_INTC_VECTOR_IRQ6 PDL_INTC_VECTOR_IRQ7 PDL_INTC_VECTOR_LVD1 Low voltage Voltage detection PDL_INTC_VECTOR_LVD2 detection Voltage detection PDL_INTC_VECTOR_CMPA1 Comparator A Voltage detection PDL_INTC_VECTOR_CMPA2 Voltage detection PDL_INTC_VECTOR_S12ADI0 12 bit ADC Conversion completed PDL_INTC_VECTOR_GBADI Group B scan completed PDL_INTC_VECTOR _ELSRi8I ee ie Event interrupt PDL_INTC_VECTOR_TGIAO PDL_INTC_VECTOR_TGIBO PDL_INTC_VECTOR_TGICO PDL_INTC_VECTOR_TGIDO PDL_INTC_VECTOR_TCIVO PDL_INTC_VECTOR_TGIEO PDL_INTC_VECTOR_TGIFO Multi function Timer Pulse Unit channel 0 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow Compare match E Compare match F PDL_INTC_VECTOR_TGIA1 PDL_INTC_VECTOR_TGIB1 PDL_INTC_VECTOR_TCIV1
235. Select a low power consumption mode Consumption 5 R_LPC_GetStatus Read the status flags Register Write 1 R_RWP_Control Control register write protection Protection 2 R_RWP_GetStatus Get the status of the register protection 1 R_BSC_ Set Configure the internal bus operation Bus Controller 2 R_BSC_Create Configure the external bus controller 5 R_BSC_Control Modify the External Bus Controller operation 7 R_BSC_GetStatus Read the External Bus Controller status flags 1 R_DMAC_ Create Configure the DMA controller DMA Controller 2 R_DMAC_Destroy Disable a DMA channel 3 R_DMAC_ Control Control the DMA controller 4 R_DMAC_GetStatus Check the status of the DMA channel R01US0059EG0111 Rev 1 11 Page 47 of 429 Aug 01 2014 2tENESAS RX220 Group 4 Library Reference 1 R_DTC Set Set the Data Transfer Controller options Data Transfer 2 R_DTC_ Create Configure the DTC for a transfer Controller 3 R_DTC_Destroy Shutdown the Data Transfer Controller 4 R_DTC_Control Control the Data Transfer Controller 5 R_DTC_GetStatus Check the status of the Data Transfer Controller 1 R_ELC Create Enable the ELC module Event Link 2 R_ELC_ Destroy Disable the ELC module Controller 3 R_ELC Read Read the ELC port buffer 4 R_ELC Write Write to the ELC port buffer 5 R_
236. SlaveMonitor 276 277 R_IIC_SlaveSend R_IIC_Control R_IIC_GetStatus 278 Channels 1 and 3 are not available with the 80 pin and 100 pin packages This function will return false in this case 300 R_ADC_12_CreateUnit Add remark 301 R_ADC_12_CreateChannel Add remark 304 R_ADC_12_ Control Add remark Do not select CPU Off unless there is any interrupt to wake up the CPU 305 R_ADC_12_Read Add remark for self diagnosis result format 307 R_CPA_Create Revise example 318 427 Add cross reference for chapter 5 319 320 INTC Update usage example 321 322 I O PORT Update usage example 323 MCU Update usage example 326 327 CAC Update usage example 333 336 DTC Update usage example 341 342 MTU2 Add sample code for Reset Synchronized PWM mode 343 344 TMR Update usage example 347 367 RTC Update usage example 370 390 SCI Update usage example 409 412 SPI Update usage example 420 422 CPA Revise sample code 425 Add usage example for MPC 426 427 Add usage example for BSC 149 R_ELC_ Control Revised remark Old Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the 1 11 Aug 01 2014 RSPI This function will return false if this condition is detected New Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the RSPI RO1USO059EG0111 Rev 1 11 Rev
237. Station ID 0x0A using interrupts R_SCI_Send 9 PDL_NO_DATA send_data0 0 SCItx R01US0059EG0111 Rev 1 11 Page 381 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples tx_ Async MP mode data Transmission by polling a NOTE The receiving side must be ready before this ID is transmitted Send Target Station ID 0x01 by internal polling R_SCI_Send 9 0x0100 PDL_SCI_MP_ID_CYCL PDL_NO_PTR 0 PDL_NO_FUNC Send data to Target Station ID 0x01 by polling R_SCI_Send 9 PDL_NO_DATA send_data 0 PDL_NO_FUNC void SCItx void tx_end true Figure 38 Example of SCI Transmission code in Asynchronous Multi Processor mode R01US0059EG0111 Rev 1 11 Page 382 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 8 SCI in SPI Mode This shows the setting of SCI channel 6 in to SPI master mode and the transmission of data using interrupts PDL functions include r_pdl_sci h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h static void SCItx void volatile bool data_sent false void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Set Channel 6 pin options R_SCI_Set 6 PDL_SCI_PIN_SCI6_RXD6_PBO
238. TC_ PIN RTCOUT P32 port to use for it data2 The current count value Count seconds in 32 bits binary display data3 Configure the clock periodic interrupt The default setting is shown in bold Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256 HZ or PDL_RTC_PERIODIC_128 HZ or PDL_RTC_PERIODIC_64_ HZ or PDL_RTC_PERIODIC_32_HZ or ee PDL RTC PERIODIC 16 HZ or The frequency or interval for periodic interrupt PDL_RTC_PERIODIC_8 HZ or requests PDL_RTC_PERIODIC_4_HZ or PDL_RTC_PERIODIC_2_HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC_PERIODIC_2S data4 The alarm count value Setting the alarm register corresponding to 32 bit binary counter If not required specify PDL_NO_DATA data5 The alarm mask value in 32 bits binary format Setting the alarm enable corresponding to 32 bit binary alarm counter If not required specify PDL_NO_DATA R01US0059EG0111 Rev 1 11 REN ESAS Page 218 of 429 Aug 01 2014 RX220 Group Description 2 2 Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference func1 The function to be called when an alarm occurs Specify PDL_NO_FUNC if not required data6 The alarm interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for p
239. TER_DETECT Select reset negation for comparator A Interrupt Event Generation Condition Select Valid for interrupt mode selected PDL_CPA_IRQ_BELOW_CVREFA or Select Interrupt Event Generation PDL_CPA_IRQ_ABOVE_N_ EQUAL_CVREFAor Condition of above and equal below or PDL_CPA_IRQ_CROSS_CVREFA cross CVREFA for comparator A e Interrupt Type Valid for interrupt mode selected PDL_CPA_NONMASKABLE_INTERRUPT or PDL_CPA_MASKABLE_INTERRUPT Select non maskable interrupt Select maskable interrupt or ELC event func The function to be called when a maskable interrupt request from comparator A except ELC is used Specify PDL_NO_FUNC if PDL_CPA_NONMASKABLE_INTERRUPT ELC Event Generation Condition Selection or monitor only operation are selected data3 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Comparator A ztENESAS Page 306 of 429 RX220 Group 4 Library Reference Reference R_CGC_ Set R_LVD_Create R_LVD_Control and R_CPA_GetStatus Remarks Do not use VDET1 and Comparator A channel 0 VDET2 and comparator A channel 1 at same time because they share same registers See R_LVD_Create and R_LVD_Control e Function R_CGC_Set must be called with the current clock source selec
240. TOSDESTOY a aiai diodai ada aiaia idii ta ay ad diii d a as 220 ar RAR ECE Controleren earn tiae a EE AE EE N E 221 5 R REC ControlBinary e aeiu idiin ad ii i a i d iiia 225 6 WRERTP CRAG reetis e e E ae Er aa EESE a EAE ECA EA A AENEA EEN r DAES KETLERS ASEET se 227 7 ARORTO ReadBNaAry eeter tecieyeetebeesecetuetetedsnaredeatiny ata ae a aa aaan a eaaa aSa Tan EBAN 229 8 onL EEEN Tia O A AAE A E E A 231 4 2 19 Independent Watchdog Timer cccceecccceceeccceeseeeceeeeeeceeeeeaeeeeenseaeeeeeaeeeeseaeeeeeeeeeeeeneeaeeeees 232 We ARLIWDW Seier a e eE ea E vacuazas A EAE A E ee ENEA rA E EE EEEE EAR 232 2 RIWDOF OOMTO eke eeaeee ENa AES e OEE Eea EEEE EAE EEEE EA ar E AE EAEE EEA 234 2 AOWD R als tea ee E erasa EE a E ee EEN A rA E Esa 235 4 2 20 Serial Communication INTEPFACE Lecce ceessececececeesseaececesececeeseusecececeesceeeusececeeseeeseseeaeeeeeeseeeaes 236 TW gt E E A E PEA AEA EAE I E E EE 236 2 mA ET I EE E E E T A EA oe ganas Oat newton EAE 239 AAEE eI E BEE oN AE E A T distinc ea nied 244 N o E E EE e E A E A TE E E E A ATE EA E AT T E EAS 245 5 E A R n E1 EEA A A A E EE A ETE 248 6 RE AE AAN E E E A A ATE E A A E 251 Wyo RSG UCE Write ar sets saa dart sats EE dares AEE Ea Aa E ARAE A iS 254 A ET E REA ITE a ATEA E EE IE A TE E AAT TE A A TE E ETTET 256 9 R SC UC ReadLastByle icicscasactesscsackscdesaices std axiesdacastavnes asta tia ddhtedaaariesstdaseesdacasdasedenetatdaaiiteteeday 258 TO e RAS
241. UT_P_PHASE_ 3 LOW_HIGH PDL_MTU2_OUT_N_PHASE_3_HIGH_LOW or MTIOC4D PDL_MTU2 OUT_N_PHASE_3 LOW_HIGH Write access control applies only to reset synchronised or complementary PWM modes PDL_MTU2_OUT_LOCK_ENABLE Prevent further changes to the phase output control Toggle output control applies only to reset synchron ised or complementary PWM modes PDL_MTU2_OUT_TOGGLE_ENABLE or Enable or disable toggle output PDL_MTU2 OUT TOGGLE DISABLE synchronised with the PWM cycle 2tENESAS Page 169 of 429 RX220 Group Description 3 4 RO1US0059EG0111 Aug 01 2014 buffer_control The buffer control settings to be modified All settings are 4 Library Reference optional If multiple selections are required use to separate each selection Output level buffer control applies only to reset synchronised or complementary PWM modes To apply output control make sure the operation of the corresponding channel is stopped Set the output control to be transferred to the output PDL_MTU2_OUT_BUFFER_P_PHASE_1_LOW or PDL_MTU2 OUT_BUFFER_N_PHASE_3_ HIGH PDL_MTU2 OUT BUFFER P_PHASE_1 HIGH MTIOCSB PDL MTU2 OUT BUFFER N PHASE 1 LOWor MTIOC3D PDL_MTU2 OUT BUFFER_N PHASE _1_HIGH PDL_MTU2 OUT BUFFER P_PHASE 2 LOWor MTIOC4A PDL_MTU2 OUT BUFFER P_PHASE_2 HIGH PDL_MTU2_OUT_ BUFFER N_PHASE_2 LOW or MTiocac P
242. V or MTIOCnC output disabled MTIOCnC output low MTlOCnC initial output low goes high at compare match MTlOCnC initial output low toggles at compare match MTlOCnC initial output high goes low at compare match MTIOCnC output high MTlOCnC initial output high toggles at compare match PDL_MTU2_C_IC_RISING_EDGE or PDL_MTU2_C_IC_FALLING_EDGE or PDL_MTU2_C_IC_BOTH_EDGES or Input capture at MTIOCnC rising edge Input capture at MTIOCnC falling edge Input capture at MTIOCnC both edges PDL_MTU2_C_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 e Input capture output compare control for register TGRD PDL_MTU2_D_OC_ DISABLED or PDL_MTU2_D_OC LOW or PDL_MTU2_D_OC_LOW_CM HIGH or PDL_MTU2_D_OC_LOW_CM_INV or PDL_MTU2_D_OC_HIGH_CM_LOW or PDL_MTU2_D_OC_HIGH or PDL_MTU2_D_OC_HIGH_CM_INV or MTIOCnD output disabled MTlOCnD output low MTIOCnD initial output low goes high at compare match MTIOCnD initial output low toggles at compare match MTIOCnD initial output high goes low at compare match MTIOCnD output high MTlOCnD initial output high toggles at compare match PDL_MTU2_D_IC_RISING_EDGE or PDL_MTU2_D_IC_FALLING_EDGE or PDL_MTU2_D_IC_BOTH_EDGES or Input capture at MTIOCnD rising edge Input capture at MTIOCnD falling edge Input capture at MTIOCnD both edges PDL_MTU2_D_IC_COUNT Input captu
243. VEL_205 or PDL_LVD_VOLTAGE_LEVEL_190 Set the voltage detection level For example PDL_LVD_VOLTAGE_LEVEL_415 4 15V Required only if the monitor is enabled and the VCC pin is selected func1 The function to be called when a Monitor 1 maskable interrupt occurs Specify PDL_NO_FUNC if not required data5 The interrupt priority level for the Monitor 1 interrupt If specifying a callback function in func1 then select between 1 lowest priority and 15 highest priority Set to 0 if using LVD to trigger the ELC without generating an interrupt see Remarks for details func2 The function to be called when a Monitor 2 maskable interrupt occurs Specify PDL_NO_FUNC if not required data6 The interrupt priority level for the Monitor 2 interrupt If specifying a callback function in func2 then select between 1 lowest priority and 15 highest priority Rev 1 11 REN ESAS Page 98 of 429 RX220 Group Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference True if the parameters are valid otherwise false Voltage detection circuit R_INTC_CreateExtInterrupt R_ CGC_Set R_CGC_Control R_LPC_GetStatus R MCU_OFS If a non maskable interrupt will be generated call R_INTC_CreateExtInterrupt to set up the NMI handler and to accept LVD based interrupt signals The LVD shares its registe
244. Wait 10 ms for data completely sent out R_CMT_CreateOneShot 0 PDL_NO_DATA 10E 3 PDL_NO_FUNC 0 i 0 i lt strlen slave_data_to_be_sent i Did the Master input match the Slave output if uint8_t master_rx_data i slave_data_to_be_sent i Handle the error while 1 Figure 53 Example of Serial Peripheral Interface Transfer of 8 bit data by Master R01US0059EG0111 Rev 1 11 Page 412 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Figure 54 shows how strings of 8 bit data are copied into 32 bit buffers then transmitted and received simultaneously by the slave The received data is then checked to confirm that the transfer was successful Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_spi h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt void spi_slave_callback void volatile bool slave_transfer_complete false define SLAVE_CHANNEL 0 define BUFFER_LENGTH 25 const char master_data_to_be_sent SPI master const char slave_data_to_be_sent SPI slave void main void uint32_t slave_tx_data BUFF uint32_t slave_rx_data BUFF uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refe
245. _ASS 3 L_NO_DATA PDL_SPI_LSB_FIRST PDL_SPI_LENGTH_24 Transfer all data once R_SPI_Transfer MASTER_CHANNI PDL_NO_DATA master_tx_da master_rx_da RO1US0059EG0111 Aug 01 2014 5 Usage Examples The code to initialise the system clock using R_CGC_Set is omitted her Page 416 of 429 RX220 Group 5 Usage Examples 1 PDL_NO_FUNC Figure 55 Example of multiple slaves Serial Peripheral Interface use R01US0059EG0111 Rev 1 11 Page 417 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 21 CRC calculator Figure 56 shows an example of CRC usage The payload and CRC checksum have been received from a remote unit The CRC calculator is used to check that the payload is correct Peripheral driver function prototypes include r_pdl_crce h RPDL device specific definitions include r_pdl_definitions h void main void uintl6_t crc_result Configure the CRC to use the CCITT polynomial R_CRC_Create PDL_CRC_POLY_CRC_CCITT PDL_CRC_LSB_FIRST Write the payload data R_CRC_Write OxFO Write the first half of the CRC checksum R_CRC_Write Ox8F Write the second half of the CRC checksum R_CRC_Write OxF7 3 Read the CRC calculation result Expected result is 0 R_CRC_Read PDL_NO_DATA amp crc_result Shutdown the CRC unit R_CRC_Destroy
246. _BDCM_N_PHASE_ENABLE or Enable or disable PWM outputs on the PDL_MTU2_ BDCM_N_PHASE_DISABLE negative phase output pins PDL_MTU2_BDCM_OPS_FB or Use input capture signals for output switch PDL_MTU2_BDCM_OPS_101 or PDL_MTU2_BDCM_OPS_110 or PDL_MTU2_ BDCM_OPS_111 control or PDL_MTU2_BDCM_OPS_000 or PDL_MTU2_BDCM_OPS_001 or PDL_MTU2_BDCM_OPS_010 or PDL_MTU2_BDCM_OPS_011 or Set the outputs according to table 21 39 in PDL_MTU2_BDCM_OPS_100 or the hardware manual Page 170 of 429 RX220 Group 4 Library Reference Description 4 4 general_control General control settings All settings are optional If multiple selections are required use to separate each selection e Interrupt skipping control PDL_MTU2_INT_SKIP_TROUGH_DISABLE or PDL_MTU2_INT_SKIP_TROUGH_1 or PDL_MTU2_INT_SKIP_TROUGH_2 or PDL_MTU2_INT_SKIP_TROUGH_3 or PDL_MTU2_INT_SKIP_TROUGH_4 or PDL_MTU2_INT_SKIP_TROUGH_5 or PDL_MTU2_INT_SKIP_TROUGH_6 or PDL_MTU2_INT_SKIP_TROUGH_7 PDL_MTU2_INT_SKIP_CREST_DISABLE or PDL_MTU2_INT_SKIP_CREST_1 or PDL_MTU2_INT_SKIP_CREST_2 or PDL_MTU2_INT_SKIP_CREST_3 or PDL_MTU2_INT_SKIP_CREST_4 or PDL_MTU2_INT_SKIP_CREST_5 or PDL_MTU2_INT_SKIP_CREST_6 or PDL_MTU2_INT_SKIP_CREST_7 Disable TCNT underflow TCIV interrupt skipping or set the skip count between 1 and 7 Disable TGRA compare match TGIA interrupt skipp
247. _CLOCK PDL_CGC_SUB_CLOCK_CL_STANDARD 32768 32768 PDL_NO_DATA 32768 PCLKB clock sub clock when sub clock is source clock 32768 PDL_CGC_SUB_32768 Generate the 2s delay befor nabiling RTC by CGC Control R_CMT_CreateOneShot 0 PDL_NO_DATA 240 PDL_NO_FUNC 0 Select the HOCO as the clock source R_CGC_Control PDL_CGC_CLK_HOCO PDL_NO_DATA L_CGC_RTC_NOT_USI R01US0059EG0111 Rev 1 11 Page 355 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples while 1 Figure 27 Example of initialization of not using RTC with available sub clock R01US0059EG0111 Rev 1 11 Page 356 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 2 Initialize RTC without providing clock Figure 28 shows an example of initialization in case of RTC is not used and RTC count source is not defined PDL functions include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h void main void Prepare the LOCO settings R_CGC_Set PDL_CGC_CLK_LOCO PDL_NO_DATA 125E 125E PDL TA 125E 125E PD Configure the HOCO settings R_CGC_Set PDL_CGC_CLK_HOCO PDL_CGC_HOCO_50000 50E6 25E6 PDL_NO_DATA 25E6 25E6 PDL_NO_DAI Generate the 2s delay before disabling RTC by CGC_Control R_CMT_CreateOneShot 0 PDL_NO_DATA 20 PDL_
248. _ELC_PIN_PORT_B 6 or PDL_ELC_ PIN PORT B 7 e Single port control ee ee Select the single port operation If the pin is PDL_ELC_PIN_OUTPUT_1 or ia A gep A Aa a PDL_ELC_PIN_OUTPUT_TOGGLE or SD Nese oe AM OLIPU DIN TASWE GUIDU PDL ELC PIN EVENT RISING EDGE or can be configured If the pin is being used PDL ELC_PIN_EVENT FALLING EDGE or as an input pin the edge that will cause an PDL_ELC_PIN EVENT ANY EDGE event can be configured R01US0059EG0111 Rev 1 11 Page 148 of 429 Aug 01 2014 RENESAS RX220 Group Description 5 5 Return value 4 Library Reference Operation data1 PDL_ELC_SOFTWARE_EVENT data2 Not used Specify PDL_NO_DATA data3 Not used Specify PDL_NO_DATA Operation data1 PDL_ELC_TRIGGER data2 e DTC Trigger setup If multiple selections are required use to separate each selection PDL_ELC_INTERRUPT_1_TRIGGER_DTC_ENABLE or Enable or disable a DTC trigger PDL_ELC_INTERRUPT_1_TRIGGER_DTC_DISABLE from an ELC Interrupt data3 Not used Specify PDL_NO_DATA True if all parameters are valid and exclusive otherwise false Category Event Link Controller Reference R_ELC_Create R_ TMR_ControlChannel Remarks e Each time this function is called a particular control operation is performed Call this function as many times as is required to complete the necessary configuration e
249. _IIC_SLAVE_GCA_DISABLE or Disable or enable detection of the General Call PDL_IIC_SLAVE_GCA_ENABLE address Device ID detection control PDL_IIC_DEVICE_ID_DISABLE or Disable or enable detection of the Device ID PDL_IIC_DEVICE_ID ENABLE address 1111 100b e Host Address detection control PDL_IIC_HOST_ADDRESS_DISABLE or Disable or enable detection of the SMBus host PDL_IIC_HOST_ADDRESS_ENABLE address data4 Slave address 0 Ignored if slave address 0 detection is disabled data5 Slave address 1 Ignored if slave address 1 detection is disabled data6 Slave address 2 Ignored if slave address 2 detection is disabled data7 Transfer rate control Either The maximum bit rate in bits per second For Master mode the clock division values will be calculated using a 50 duty cycle For Slave mode the rate will be used to calculate the clock stretching period Or b31 b30 b13 b12 b8 b7 b5 b4 b0 A i Bit rate high level register 7 Bit rate low level register ICBRH value ICBRL value R01US0059EG0111 Rev 1 11 REN ESAS Page 265 of 429 Aug 01 2014 RX220 Group Description 3 3 4 Library Reference data8 Rise and fall time compensation If the transfer rate is specified in bits per second the high level and low level durations can be adjusted to allow for application dependent rise and fall times If unsure use
250. _INTC_NMI PDL_INTC_FALLING PDL_INTC_LVD1_ENABLE NMI_handler_cpa 7 Non Maskable Interrupt Comparator A channel 0 Digital Filter interrupt enable LOCO_div_2 R_CPA_Create 0 PDL_CPA_FILTER_LOCO_DIV_2 PDL_CPA_INTERRUPT_RESET_ENABLE PDL_NO_FUNC 0 Maskable Interrupt Comparator A channel 1 Digital Filter interrupt enable LOCO_div_1 R_CPA_Create 1 PDL_CPA_FILTER_LOCO_DIV_1 PDL_CPA_INTERRUPT_RESET_ENABLE PDL_CPA_IRQ_CROSS_CVREFA PDL_CPA MASKABLE INTERRUPT CPAi_handler 7 Rev 1 11 REN ESAS Page 307 of 429 RX220 Group 4 Library Reference 2 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 R_CPA_Control Control the Comparator A module bool R_CPA_Conirol uint8_t data1 Comparator selection uint8_t data2 Settings for Comparator Control Comparator A1 or A2 data1 The comparator A channel number n where n 0 to 1 data2 Disable the Comparator A Comparator circuit option Valid for interrupt and reset mode PDL_CPA_LVD_CIRCUIT_DISABLE Disable comparator A circuit True if all parameters are valid and exclusive otherwise false Comparator A R_CP
251. _IR_DOC_DOPCF PDL_INTC_REG_IR_TMR1_OVI PDL_INTC_REG_IR_RTC_CUP PDL_INTC_REG_IR_TMR2_CMIA PDL_INTC_REG_IR_ICU_IRQO PDL_INTC_REG_IR_TMR2_CMIB PDL_INTC_REG_IR_ICU_IRQ1 PDL_INTC_REG_IR_TMR2_OVI PDL_INTC_REG_IR_ICU_IRQ2 PDL_INTC_REG_IR_TMR3_CMIA PDL_INTC_REG_IR_ICU_IRQ3 PDL_INTC_REG_IR_TMR3_CMIB PDL_INTC_REG_IR_ICU_IRQ4 PDL_INTC_REG_IR_TMR3_OVI PDL_INTC_REG_IR_ICU_IRQ5 PDL_INTC_REG_IR_DMAC_DMACOI PDL_INTC_REG_IR_ICU_IRQ6 PDL_INTC_REG_IR_DMAC_DMAC1I PDL_INTC_REG_IR_ICU_IRQ7 PDL_INTC_REG_IR_DMAC_DMACal PDL_INTC_REG_IR_LVD_LVD1 PDL_INTC_REG_IR_DMAC_DMAC3I PDL_INTC_REG_IR_LVD_LVD2 PDL_INTC_REG_IR_SClI1_ERI PDL_INTC_REG_IR_CMPA_CMPA1 PDL_INTC_REG_IR_SCI1_RXI PDL_INTC_REG_IR_CMPA_CMPA2 PDL_INTC_REG_IR_SCI1_TXI PDL_INTC_REG_IR_RTC_ALM PDL_INTC_REG_IR_SCI1_ TEI PDL_INTC_REG_IR_RTC_PRD PDL_INTC_REG_IR_SCI5_ERI PDL_INTC_REG_IR_S12AD_S 12ADI PDL_INTC_REG_IR_SCI5_RXI PDL_INTC_REG_IR_S12AD_GBADI PDL_INTC_REG_IR_SCI5_TXI PDL_INTC_REG_IR_ELC_ELSR18I PDL_INTC_REG_IR_SCI5_TEl PDL_INTC_REG_IR_MTUO_TGIA PDL_INTC_REG_IR_SCI6_ERI PDL_INTC_REG_IR_MTU0O_TGIB PDL_INTC_REG_IR_SCI6_RXI PDL_INTC_REG_IR_MTU0_TGIC PDL_INTC_REG_IR_SCI6_TXI PDL_INTC_REG_IR_MTU0O_TGID PDL_INTC_REG_IR_SCI6_TEI PDL_INTC_REG_IR_MTUO_TCIV PDL_INTC_REG_IR_SCI9_ERI PDL_INTC_REG_IR_MTU0O_TGIE PDL_INTC_REG_IR_SCI9_RXI PDL_INTC_REG_IR_MTU0_TGIF PDL_INTC_REG_IR_SCI9_TXI PDL_INTC_REG_IR_MTU1_TGIA PDL_INTC_REG_IR_SCI9_TEl PDL_INTC_REG_IR_MTU1_TGIB PDL_INTC_REG_IR_SCl12_ERI PDL_INTC_REG_IR_MTU1_TCIV PDL_INTC_REG_I
252. _NO_DATA 0x00120000 Alarm at 12 noon PDL_NO_DATA alarm_function t5 PDL_NO_FUNC PDL_NO_DATA Rev 1 11 RENESAS Page 217 of 429 RX220 Group 4 Library Reference 2 R_RTC_CreateBinary Synopsis Prototype Description 1 2 Configure the RTC module in binary count mode bool R_RTC_CreateBinary uint32_t data1 Configuration selection uint32_t data2 Current count uint16_t data3 Periodic configuration uint32_t data4 Alarm count uint32_t datad Alarm mask void func1 Callback function uint8_t data6 Interrupt priority level void func2 Callback function uint8_t data7 Interrupt priority level Set up the RTC operation in Binary count mode data1 Configure the clock options To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Clock output control PDL_RTC_OUTPUT_DISABLE or Disable or enable the 1 Hz 64 Hz clock PDL_RTC_ OUTPUT ENABLE output on the RTCOUT pin Clock RTCOUT output period Select PDL_RTC_OUTPUT_RTCOS_1HZ or RTCOUT outputs 1 Hz PDL_RTC_OUTPUT_RTCOS 64HZ RTCOUT outputs 64 Hz Configure RTCOUT Pin Select PDL_NO_DATA if no pins are required PDL_RTC_OUTPUT_ENABLE will not be a valid option if select PDL_NO DATA PDL_RTC_PIN_RTCOUT_P16 or If using the RTCOUT pin then select the PDL_R
253. _PO7PFS PDL_MPC_OR 0x08 Get the value of register PO7PFS R_MPC_Read PDL_MPC_REG PO7PFS amp data Figure 60 Example of MPC R01US0059EG0111 Rev 1 11 Page 425 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 26 Bus Controller Figure 61 shows an example of Bus Controller usage Peripheral driver function prototypes include r_pdl_bsc h include r_pdl_io_port h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h bool error_detected void BSC_error_handler void void main void uint8_t status uintl6_t bad_address volatile uint8_t temp uint8_t address_pointer Toggle the priority to the Internal Peripheral Bus 1 between Main Bus 1 and Main Bus 2 R_BSC_Set PDL_BSC_PRIORITY_PB1_MB1 Check priority register is as expected if BSC BUSPRI WORD BIT_4 while 1 Address that will generate an error S table Types Of Bus Error address_pointer uint8_t 0x000C0000u1 Configure the bus controller Enable illegal address detection and register a callback R_BSC_Create PDL _BSC_ERROR_ILLEGAL_ADDRESS_ENABL BSC_error_handler 15 rror_detected false Generate an illegal address error xaddress_pointer OxAA temp address_pointer Wait for interrupt to set this while error_detected false
254. _PTR if it is not required data3 Where the Timer Interrupt Skipping Counter register TITCNT value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit None None RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h uint1l6_t S b count uint8_t Skip_count void func void Read the counter registers for unit 0 R_MTU2_ReadUnit 0 amp Sub_count amp Skip_count Rev 1 11 REN ESAS Page 176 of 429 RX220 Group 4 2 15 1 Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 Port Output Enable R_POE_Set Configure the Port Output Enable module bool R_POE_Set uint32_t data1 uint16_t data2 uint16_t data3 Input configuration selection Input POEn pin selection Output configuration selection Initialise the POE pins data1 Configure the input pin detection for pins POEO to POE3 and POE8 If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required 4 Library Reference PDL_POE_0_ PDL_POE_0O MODE_EDGE or MODE_LOW_8 or PDL_POE_0O MODE_LOW_16 or PDL_POE_0 MODE_LOW_128 PDL_POE_1_ PDL_POE_1 MODE_EDGE or MODE_LOW_8 or
255. _definitions h void func void Allocate a copy of the structure for the selected channel R_MTU2_Create_structure ch4_parameters Load the defaults R_MTU2_Create_load_defaults amp ch4_parameters Set the non default options for channel 4 ch4_parameters channel_mode PDL_MTU2_MODE_NORMAL PDL_MTU2_SYNC_ENABLE PDL_MTU2_TGRA_DTC_TRIGGER_ENABLE h4_parameters counter_operation PDL_MTU2_CLK_PCLK_DIV_4 h4_parameters buffer_operation PDL_MTU2_BUFFER_AC_CM_A h4_parameters TGR_C_D_operation PDL_MTU2_C_OC_HIGH_CM_LOW h4_parameters TCNT_TCNTU_value 0 h4_parameters RA_TCNTV_value 199 h4_parameters RB_TCNTW_value 99 h4_parameters RC_TGRU_value 50 h4_parameters RD_TGRV_value 100 h4_parameters RE_TGRW_value 0 h4_parameters GUGU A QQ QAANAAAARAAA RF_TADCORA_value 0 R_MTU2_Create 4 amp ch4_parameters Rev 1 11 REN ESAS Page 163 of 429 RX220 Group 4 Library Reference 3 R_MTU2_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a Multi function Timer Pulse Unit bool R_MTU2_Destroy uint8_t data Unit selection Shut down a timer pulse unit data The multi function timer pulse unit n where n 0 Unit 0 comprises channel
256. _pdl_cgc h PDL device specific definitions include r_pdl_definitions h Callback functions void CAC_frequency_error void void CAC_measurement_complete void void CAC_overflow void void main void Configure the IWDTLOCO clock settings R_CGC_Set PDL_CGC_CLK_IWDTLOCO PDL_NO_DATA Reserved 125000 IWDTLOCO PDL_NO_DATA ICLK PDL_NO_DATA PCLKD PDL_NO_DATA PCLKB PDL_NO_DATA ECLK Configure the main clock settings R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_RESONATOR 20 20 20 20 20 Main ICLK PCLKD PCLKB FCLK oa a a Al AAA et m Select the main Clock as the clock source and enable the IWDT Clock R_CGC_Control PDL_CGC_CLK_MAIN PDL_CGC_MAIN_ENABL PDL_CGC_IWDTLOCO_ Use the main clock to check the IWDTLOCO accuracy 10 R_CAC_Create PDL_CAC_REFERENCE_MAIN PDL_CAC_REFERENCE_RISING PDL_CAC_REFERENCE_DIV_8192 PDL_CAC_MEASURE_IWDTLOCO PDL_CAC_MEASURE_DIV_1 PDL_CAC_LIMIT_TOLERANCE PDL_NO_DATA Not using CACREF pin PDL_NO_DATA Not using CACREF pin 10 10 tolerence 10 10 tolerence CAC_frequency_error 5 f PELOLItY CAC_measurement_complete 6 Priority CAC_overflow R01US0059EG0111 Rev 1 11 Page 326 of 42
257. a Operation Circuit bool R_DOC_Destroy void Disable and enable the DOC module stop state True DOC None None include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void R_DOC_Destroy Page 312 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description R_DOC_ Control Control the Data Operation Circuit bool R_DOC_Conirol uint8_t data1 Configuration uint16_t data2 Data Control the DOC Module data1 Control operation To set multiple options at the same time use p to separate each value If no selection is made specify PDL_NO_DATA the control setting will be left unchanged Operation Mode PDL DOC COMPARISON MATCH or PDL_DOC_COMPARISON_MISMATCH or PDL_DOC_MODE_ADD or PDL_DOC_ MODE SUBTRACT If required specify a new mode of operation to change to DOC Flag PDL_DOC_FLAG CLEAR Clear the DOC flag If this flag is set when interrupts are enabled an interrupt will be generated Note The DOC flag is automatically cleared when the callback function is called e Interrupt control PDL_DOC_INTERRUPT_ENABLE or PDL_DOC_INTERRUPT_DISABLE Enable or disable the DOC interrupt e Update the DOC data value PDL_DOC_DATA_UPDATE Update the DOC with the value specified in data2 See d
258. a to the Data Operation Circuit bool R_DOC_Write uint16_t data1 Pointer to buffer holding data to write uint16_t data2 Number of 16 bit words to write data1 The start address of the data to be written data2 The number of 16 bit words to write True DOC None e This function will not return until all the supplied data has been written to the DOC The DMAC DTC can be used to write data to the DOC independently of this function RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t data 10 1 2 3 4 5 6 7 8 9 10 Write 10 numbers to the DOC R_DOC_Write data 10 Rev 1 11 RENESAS Page 316 of 429 RX220 Group 5 Usage Examples 5 Usage Examples This chapter shows programming examples for each driver in this library R01US0059EG0111 Rev 1 11 Page 317 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 1 Clock Generation Circuit Figure 3 shows an example of configuring the clock generation circuit After a power on reset the main clock oscillator is switched off The MCU is using the LOCO as the clock source The calls to R_CGC_Set configure the LOCO dividers and enable the main clock oscillator R_CGC_ Control is used to select the Main clock as the clock source Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_cmt h
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260. able value addition mode Value addition count select PDL_ADC_12_VALUE_ADDITION_0 or PDL_ADC_12_VALUE_ADDITION_1 or PDL_ADC_12_VALUE_ADDITION_2 or PDL_ADC 12 VALUE ADDITION 3 Set the conversion to be 1 time 2 time addition once 3 time addition twice or 4 time addition three times Data alignment PDL_ADC_12_DATA_ALIGNMENT_RIGHT or PDL_ADC_12_DATA_ALIGNMENT_LEFT The alignment of the 12 bit ADC conversion result within the 16 bit register Ignored for channels using value addition mode the 14 bit result is always left aligned 2tENESAS Page 297 of 429 RX220 Group 4 Library Reference Description 2 4 Self diagnostic control PDL_ADC_12 SELF_DIAGNOSTIC_DISABLE or PDL_ADC_12 SELF _DIAGNOSTIC_VREFHO_ ZERO or PDL_ADC_12 SELF DIAGNOSTIC_VREFHO HALF or x0 PDL_ADC_12 SELF DIAGNOSTIC_VREFHO FULLor x PDL ADC 12 SELF DIAGNOSTIC _VREFHO ROTATED Disable the self diagnostic function or enable and use the voltage on pin VREFHO x1or automatically rotated voltage Result register clearing PDL_ADC_12_RETAIN_RESULT or PDL_ADC_12_CLEAR_RESULT Retain or clear the value in each result register after it has been read Disconnection detection assist function control PDL_ADC_12 DDA DISABLE or PDL ADC 12 DDA PRECHARGE or PDL_ADC_12 DDA_DISCHARGE Disable the disconnection detection assist function or
261. ad back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DMAC_Create R01US0059EG0111 Rev 1 11 Page 394 of 429 Aug 01 2014 RENESAS RX220 Group 2 PDL_DMAC_NORMAI PD L L_DMAC_SOURC PDL_DMAC_SIZE_8 E ADDRESS_FIXED PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_IRQ_END DMAC_TRIGGER_IICO_RX nt8_t amp RIICO ICDRR a_storage RAY_1_SIZE 2 L_NO_DATA L_NO_DATA O_DATA O_DATA c_rx_dmac_end_handler L c o B w Aa hh H o w uya pe CE ae nd Select I C mode at 100kHz R_IIC_Create IIC_CHANNEL PDL_IIC_MODE_IIC 0 0 0 0 100E3 300 lt lt 16 300ns rise time PDL_IIC_INT_PCLK_DIV_8 200 Write the data into the write_eeprom_data EPROM Prepare the next data for writing to the DMAC_Control W _DMAC_SUSPEND PDL_DMAC __ DMAC_UPDATE_SOURCE eprom_data_array_2 _NO_PTR RAY_2_ SIZE L_NO_DATA O_DATA NO_DATA L_NO_DATA ENABLE i DL DI Li L d L 3 P P P A P P P P Write write_eep the da rom_da ta into the EEPROM ta Clear for i the da Oe 1 lt ta storage area 20 i data_storage i 0x00 Reset R_IIC_MasterSend IIC_CHANNEL PDL_IIC_STOP_DISABL EPROM_ADDRESS
262. ad data from this slave DMAC or DTC The function to be called when a Stop or Re Start is detected data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false Category 2C Reference R_IIC_GetStatus R_IIC_SlaveSend R_DMAC_Create R01US0059EG0111 Page 274 of 429 Aug 01 2014 RX220 Group 4 Library Reference Remarks Program example If a callback function is specified interrupts are used Use R_IIC_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 If using polling mode When the function returns use R_IIC_GetStatus to identify the activity that has occurred Call this function for each transfer required even if the master has ended the previous transfer with a repeat start If the DMAC or DTC is not being used to perform a slave transmission then if a slave transmission is required function R_IIC_SlaveSend must be called to send the data Note If R_IIC_GetStatus reports that the slave is in transmit mode then a slave transmission is required If the master sends more data than is expected and the DMAC DTC trigger is disabled this function will issue a NACK to the master If using the DMAC or DTC for transferring data then
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265. aging the transfer of data on the interface including e Automatic interrupt control e Automatic DMAC DTC control 6 Control of special modes such as loopback 7 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any SPI channel R01US0059EG0111 Rev 1 11 REN ESAS Page 41 of 429 Aug 01 2014 RX220 Group 2 Driver 2 25 CRC Calculator Driver The driver functions support the CRC calculator providing the following operations 1 Configuration for use including e Polynomial selection e Bit order selection e Preparation for a new calculation 2 Disabling the calculator and enabling low power mode 3 Writing data to be used for the calculation 4 Reading the calculation result R01US0059EG0111 Rev 1 11 Page 42 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 26 12 bit Analog to Digital Converter Driver The driver functions support the use of the 12 bit ADC unit providing the following operations 1 Selection of the pins to be used as ADC inputs 2 Configuration of the ADC unit 3 Configuration of the channels for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control e Sampling time control 4 Disabling the unit when no longer required and enabling low power mode 5 Control the ADC unit including e CPU sleep option 6 Reading the conversion results with support for polling or interrupts Note The Cloc
266. all this function to configure the relevant pins e Make sure no more than one peripheral function is assigned to a single pin e Make sure the configuration of MTCLK pins is consistent for all the channels e Device packages with 64 or fewer pins do not have all of the pin options R01US0059EG0111 Rev 1 11 Page 152 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference Program example include r_pdl_mtu2 h void func void Configure the MTU pins R_MTU2_Set 0 PDL_MTU2_PIN_0A_P34 i RO1US0059EG0111_ Rev 1 11 Page 153 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_MTU2 Create Synopsis Configure an MTU channel Prototype bool R_MTU2_Create uint8_t data1 Channel selection R_MTU2_Create_structure data2 A pointer to the structure R_MTU2_Create_structure members uint32_t channel_mode Configuration selection uint32_t counter_operation Configuration selection uint32_t ADC_trigger_operation Configuration selection uint16_t buffer_operation Configuration selection uint32_t T R_A_B_ operation Configuration selection uint32_t T R_C_D_ operation Configuration selection uint32_t T R_U_V_W_operation Configuration selection uint16_t noise_filter_operation Configuration selection uint16_t TCNT_TCNTU_value Register value uint16_t T RA_TCNTV_value Register value uint16_t TGRB_TCNTW_value Register value
267. am Erase mode is set or if an operating power mode transition is in progress This function will return false if this is detected b Calling R_RTC_Create after using option PDL_CGC_RTC_TO_BE_USED c Make sure PCLKB clock frequency 2 RTC count source clock frequency d Call R_CGC_Set once to set sub clock frequency before call R_CGC_Control with option PDL_CGC_RTC_TO_BE_USE e Sub clock oscillator is not available for 48 pin package R_MCU_Control a Remove On chip RAM control b Replace remark by The PDL_MCU_WARM_START is used after the initialization of cold start caused by a power on reset has completed This is to indicate the next reset processing is warm start Caused by a reset signal during operation R_LVD_Create Add remark User wants to use both LVD1 and LVD2 user must configure both LVD1 and LVD2 simultaneously R_LPC_Control Change PDL_LPC_SLEEP_RETURN_CHANGE_DISABLE to not default option R_LPC_Control Remarks Add Do not try to change operating mode if ROM Program Erase mode is set or a mode transition is already in progress This function will return false if this is detected R_ELC Control Add remark Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the RSPI This function will return false if this condition is detected R_MTU2_Create add This option can be selected in other modes For AD
268. arameter funct func2 The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data7 The periodic interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid otherwise false Real time clock R_RTC_ReadBinary If entering software standby soon after starting the RTC use R_RTC_ReadBinary first to confirm that the values are correct The oscillation accuracy of the sub clock is affected when an on chip debugger emulator is connected and the sub clock drive setting is low Before calling this function the count source must be enabled and stable Refer R_ CGC_Set and R_CGC_Control for count source and stabilization time configuration e This function is called to use RTC after setting option PDL_CGC_RTC_TO_BE_USED in R_CGC_Control at cold start e This function is not required when using 48 pin package RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void alarm_function void void func void Configure the count for an alarm at 0xXXXX4321 are matched R_RTC_CreateBinary PDL_NO_DATA 0x12345678 The current count in 32 bits binary display PDL_NO_DATA Periodic Interrupt Select 0x87654321 The alarm count in 32 bits binary display Ox0000ffff T
269. arameters Set the control options for channel 3 ch3_parameters control_setting PDL_MTU2_START ch3_parameters register_selection PDL_MTU2_REGISTER_COUNTER PDL_MTU2_REGISTER_TGRB ch3_parameters TCNT_TCNTU_value OxFFDD ch3_parameters TGRB_TCNTW_value 0x0020 Modify the operation of channel 3 R_MTU2_ControlChannel 3 amp ch3_parameters R01US0059EG0111 Rev 1 11 Page 167 of 429 Aug 01 2014 RENESAS RX220 Group 5 Synopsis Prototype Description 1 4 RO1US0059EG0111 Aug 01 2014 Rev 1 11 R_MTU2_ControlUnit 4 Library Reference Control a Multi function Timer Pulse Unit bool R_MTU2_ConirolUnit uint8_t data1 Unit selection R_MTU2_ControlUnit_structure data2 A pointer to the structure R_MTU2_ControlUnit_structure members uint16_t simultaneous_control Control selection uint32_t output_control uint32_t buffer_control Control selection Control selection uint16_t brushless DC_motor_control Control selection uint32_t general_control uint8_t register_selection uinti6_t TDDR_value uint16_t TCDR_value uint16_t TCBR_value Modify a timer unit s registers data1 The unit number n where n 0 simultaneous_control Control selection Register selection Register value Register value Register value Simultaneous stop start control
270. arameters data5 and data6 PDL_RTC_UPDATE_ALARM_YEAR All four can be selected using PDL_RTC_UPDATE_ALARM_ MONTH PDL_RTC_UPDATE_ALARM_DATE PDL_RTC_UPDATE_ALARM_DAY Parameter data5 is used for the day of the PDL_RTC_UPDATE_ALARM_DOW week data3 The new day of the week and time Ignored if not selected above See R_RTC_Create for the format data4 The new year month and day Ignored if not selected above See R_RTC_Create for the format data5 The new alarm day of the week and time Ignored if not selected above See R_RTC_Create for the format data6 The new alarm year month and day Ignored if not selected above See R_RTC_Create for the format data7 Configure the Error Adjustment options To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA e Auto Error Adjustment PDL_RTC_ERROR_AUTO_ADJUST_DISABLE or Enable or disable automatic PDL_RTC_ERROR_AUTO_ ADJUST _ENABLE error adjustment e Auto Error Adjustment Period PDL_RTC_ERROR_AUTO_ADJUST_PERIOD_60S or Select the automatic error PDL_RTC_ERROR_AUTO_ ADJUST _PERIOD_10S adjustment period e Auto Error Adjustment Addition or subtraction selection PDL_RTC_ERROR_ADJUST_PLUS or PDL_RTC_ERROR_ADJUST_MINUS Select if the adjustment value will be added or subtracted from the count R01US0059EG0111 Rev 1 11 Page 222 of 429 Aug 01
271. ata2 description for meaning data2 This meaning of this parameter depends upon the Operation Mode Operation Mode Description Comparison The comparison value Addition The initial output value before additions are made Subtraction The initial output value before subtractions are made Return value True if all parameters are valid and exclusive otherwise false Category DOC References R_DOC_Create Remarks e Interrupts can only be enabled if a callback was registered using R_DOC_Create RO1US0059EG0111 Page 313 of 429 Aug 01 2014 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void Change to subtraction mode with initial value 500 R_DOC_Controli PDL_DOC_MODE_SUBTRACT PDL_DOC_DATA UPDATE 500 R01US0059EG0111 Rev 1 11 Page 314 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 Synopsis Prototype Description R_DOC_Read Read the Data Operation Circuit result bool R_DOC_Read uint8_t data1 uint16_t data2 Pointer to status storage location Pointer to value storage location Read the DOC status and output data1 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b7 b1
272. ategory Multi function Timer Pulse Unit Reference None Remarks e Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to 0 by this function RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 174 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint1l6_t General_A uint1l6_t General_D void func void Read the status flags and registers of channel 3 R_MTU2_ReadChannel 3 amp Flags PDL_NO_PTR amp General_A PDL_NO_PTR PDL_NO_PTR amp General_D PDL_NO_PTR PDL_NO_PTR R01US0059EG0111 Rev 1 11 Page 175 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 7 Synopsis Prototype Description Return value Category Reference Remarks Program example R01US0059EG0111 Aug 01 2014 R_MTU2_ReadUnit Read from MTU registers bool R_MTU2_ReadUnit uint8_tdata1 Unit selection uint16_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location Read any of the timer unit s counter registers data1 The unit number n where n 0 data2 A pointer to where the Timer subcounter register TCNTS value shall be stored Specify PDL_NO
273. ation Circuit must be configured before configuring any timer channel R01US0059EG0111 Rev 1 11 REN ESAS Page 36 of 429 Aug 01 2014 RX220 Group 2 Driver 2 20 Real time Clock Driver The driver functions support the use of the real time clock providing the following operations There are 2 count modes calendar count mode and binary count mode For calendar count mode 1 Configuring the clock for use including Alarm configuration Optional day of week calculation 12 or 24 hour mode selection Automatic alarm and periodic interrupt control 2 Disabling the clock 3 Control of the clock including e Changing the alarm settings e Changing the current date or time e Error adjustment 4 Reading the clock status flags current time and date alarm time and date 5 Reconfigure callback function and priority setting of alarm and periodic interrupts at warm start up For binary count mode 1 Configuring the count for use including e Set current count e Set alarm count e Set alarm mask 2 Disabling the count 3 Control of the count including Changing the current count value Changing the alarm count value Changing the alarm mask value Error adjustment 4 Reading the count status flags current count alarm count and alarm mask 6 Reconfigure callback function and priority setting of alarm and periodic interrupts at warm start up R01US0059EG0111 Rev 1 11 Page 37 of 429 Aug 01 2014 RENESAS RX220 Group 2
274. ation in case Of RTC is NOt USE eeeccceesceceeseeceeesseeeeeeseeeeeceseeeaecscseeaeesseeaeeeseneaeess 5 355 1 Initialize RTC with providing sub clock use case sub clock is available 5 355 2 Initialize RTC without providing clock ccccceeeeeeeeeeeeeeeeeeeeeseeeeeceaeeesaaeeeeaeeseaeeesaeeeeaaeseeeeeseas 5 357 5 16 3 Use case of RTC over reset and power COMSUMMPTION ecccceeeeeeeeeeeeeeteeeeeteaeeetaeeteneeees 5 358 1 Wake up from sleep mode ccecececeeeeeeteeeeeeeeceeeeeeeaeeeeaaeeeeeeesaeeeeaeeeeaaeseeeeeseeeesaeeseaaesseneeees 5 358 6 2 Wake up from software standby mode ceccceeeeeceeeeeeeeeeeeeeeeeceaeeesaaeeeeaeeseaeeesaeeesaaeeeeneeeaas 5 363 5 17 Independent Watchdog Timer c ce eeecceceeeeeneeeeeeneeeeeeaeeeeeeaaeeeeeeaaeeeeeeaeeeseeaaeeeseeaaeeeeeeaaeeeseeaaeeeeseaas 368 5 18 Serial Communication Interface ccceccceceeeceeeeeeeeeeceeeee cee eeeaaeeseaeeseeeeesaeeeeaaeseeeeeseeeesaeeseeeeeenees 370 5 18 1 SCI Asynchronous Using Polling 0 ccccceeeeeeceeee cece eeeeaeeeeeeeceaeeecaaeeesaaeseeeeseeeesaeessaeeneaeeenaees 370 5 18 2 SCI Asynchronous Using Interrupts ceeeeeeeeeeeeeeeeaeeeeaee scenes ceaeeeeaaeeeeaeeseeeeesaeeesaeeseneeeeaees 371 5 18 3 SCI Asynchronous Using DMAC 00 cccececeeeeceeeee cece eeeeaeeeeeeeceaeeecaaeeeeaaeseeeseeeeesaeeseaeeseneeenaes 373 5 18 4 Synchronous Transmission and Reception cccccceecceeeee
275. ave Address uint16_t data4 Number of bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master write data1 Select channel SCIn where n 1 5 6 9 or 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage e Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL _SCI_IIC_10 BIT SLAVE ADDRESS Specify the slave address width e Repeated Start PDL_SCI_IIC_RESTART The transfer will start with a re start rather than the default behaviour of a start condition e Stop Condition selection PDL_SCI_IIC_NOSTOP By default the transfer will end with a stop condition Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 bi b0 7 bit address b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that contai
276. ave channel status R_SPI_Get Status SLAVE_CHANNEL amp StatusValue amp Sequence_count No errors if StatusValue amp 0x000Du 0x0u slave_transfer_complete true else Handle the error while 1 Figure 54 Example of Serial Peripheral Interface Transfer of 8 bit Data by Slave R01US0059EG0111 Rev 1 11 Page 414 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 20 3 Master operation with multiple slaves This is an example of Serial Peripheral Interface usage where one SPI master communicates with four SPI slaves Each slave requires different data bit lengths RSPCKB A MOSIB A MISOB A SPI channelo SSLBO A SSLB1 A SSLB2 A SSLB3 A Master Slave 0 8 bit data words Slave 1 9 bit data words Slave 2 15 bit data words 7 Slave 3 24 bit data words Figure 55 shows how data of appropriate bit lengths is transferred to each SPI slave Commands 0 to 3 are executed in sequence with each command asserting the appropriate SSL pin Peripheral driver function prototypes include r_pdl_spi h include r_pdl_cgc h include r pdl cmth PDL device specific definitions include r_pdl_definitions h define MASTER_CHANNEL 0 void main void const uint32_t master_tx_data 4 Ox000000A4 8 bit data 0x00000132 9 bit data 0x00007F34 15 bit data 0x00345678 24 bit data
277. bO a Flag see remarks data2 This meaning of this parameter depends upon the Operation Mode as specified in the table below Specify PDL_NO_PTR if this information is not required Operation Mode Description Return value Category References Remarks Program example Comparison The set comparison value Addition The addition result Subtraction The subtraction result True DOC None e In Addition Mode the flag is set if the result of the addition exceeds FFFFh In Subtraction the flag is set if the result of the subtraction is less than zero In Comparison Mode the flag is set when the comparison criteria Match Mismatch is met If the flag is set it is automatically cleared by this function If using interrupts the flag is automatically cleared when the interrupt is handled RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t status uintl6_t result Read result R_DOC_Read amp status result R01US0059EG0111 Aug 01 2014 Rev 1 11 ztENESAS Page 315 of 429 RX220 Group 4 Library Reference 5 Synopsis Prototype Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 R_DOC_Write Write dat
278. back function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of bytes Pollin ong has been received or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is received or PDL_NO_FUNC Return value R01US0059EG0111 Aug 01 2014 DMA if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false Rev 1 11 REN ESAS Page 271 of 429 RX220 Group 4 Library Reference Category Reference Remarks Program example 12C R_IIC_MasterReceiveLast R_IIC_GetStatus RDMAC_Create If a callback function is specified reception interrupts are used Please see the notes on callback function usage in 6 e If the previous transfer did not issue a Stop condition a Repeated Start condition shall be generate
279. be used to transfer the data specify PDL_NO_PTR data5 The number of bytes to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling bytes has been sent or another event occurs Interrupts The function to be called when bus activity has stopped DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used The function to be called at the interval specified in R_DTC_Create This DTC function will in addition also be called when the last byte has been transmitted RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 269 of 429 RX220 Group Description 2 2 Return value Category Reference Remarks Program example 4 Library Reference data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable and a normal transfer completed otherwise false 12C R_IIC_GetStatus R_IIC_GetStatus R_DMAC_Create e If a callback function is specified transmission interrupts are used Please
280. ch Timer use R01US0059EG0111 Rev 1 11 Page 346 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 16 Real time Clock 5 16 1 Use case of RTC configuration and use case These examples show initialization procedure of simple RTC use case 1 Configuration CGC and RTC counting by sub clock only RTC count source in calendar count mode Figure 23 shows an example of sub clock used as count source and main clock used as system clock before using the Real time clock in Calendar count mode PDL functions include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h PDL device specific definitions include r_pdl_definitions h void main void volatile uint32_t date time Prepare the main clock settings ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_ RESONATOR 20E6 20E6 20E6 20E6 20E6 PDL _NO_DATA Configure the sub clock settings R_CGC_Set PDL_CGC_CLK_SUB_CLOCK PDL_CGC_SUB_CLOCK_CL_STANDARD 32768 32768 32768 32768 32768 PDL_CGC_SUB_2 Generate the 2s delay befor nabling RTC by CGC_Control R_CMT_CreateOneShot 0 PDL_NO_DATA 2 PDL_NO_FUNC 0 Select RTC to be used R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_CGC_RTC_TO_BE If Cold start is detected the RTC clock should be re started R_RT
281. cillator Return value True if all parameters are valid and exclusive otherwise false For RX220 the following rules shall be checked e fain_cLock_osciLLator lt 20 MHz 2 1 MHz if a resonator is used fick lt 32 MHz fects lt 32 MHz fpcikp lt 32 MHz fectk lt 32 MHz The frequencies of the internal clocks ICLK PCLKB PCLKD and FCLK are achievable selected clock source 1 2 4 8 16 32 or 64 Category Clock generation circuit References R_CGC_Control R_MCU_GetStatus R_LPC_Create RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 52 of 429 RX220 Group Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference Call this function once to set the clock frequency for each clock source whether it is used as system clock or RTC count source If the current clock source is selected in parameter data1 the frequencies of the internal clocks will be changed by this function Because this can not be done if ROM Flash Program Erase mode is set or if an operating power mode transition is in progress this function will return false if this is detected After a power on reset the MCU selects the LOCO as the clock source This function must be called before configuring clock dependent modules This function will enable the selected clock but will not select it as the current clock source After the required
282. ck Generation Circuit Set Channel 9 pin options R_SCI_Set CHANNEL SCI_IIC PDL_SCI_PIN_SCI9_RXD9_PB6 PDL_SCI_PIN_SCI9_TXD9_PB7 Setup the SCI IIC channel R_SCI_Create CHANNEL _SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 all Configure the DTC controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table Set current EEPROM address IIC_Buffer 0 EEPROM_ADDRESS R01US0059EG0111 Rev 1 11 Page 388 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Use blocking function for this DTC will be used for the data part R_SCI_IIC_Write CHANNEL SCI_IIC PDL_SCI_IIC_NOSTOP SLAVE_ADDRESS 1 IIC_Buffer PDL_NO_FUNC Set flag data_received false Read data from current EEPROM address using DTC Start with an IIC Re start DTC on Rx R_DTC_Create PDL_DTC_NORMA PDL_DTC_DESTINATION_ADDRESS_PLUS PDL _DTC_SOURCE_ADDRESS FIXED PDL_DTC_SIZE_8 PDL_DTC_IRQ_COMPL PDL_DTC_TRIGGER_RXI9 dtc_iicl_rx_transfer_data uint8_t amp SCI9 RDR Source IIC_Buffer Destination Data length is one less than we want to read as use R_SCI_IIC_ReadLastByte 4 PDL_NO_DATA DTC on Tx To write the dummy data out Data length is 2 less than we want to read as first dummy by
283. ck source switching PDL_LPC_SLEEP_RETURN_CHANGE_DISABLE or PDL_LPC_SLEEP_RETURN_CHANGE_HOCO or PDL_LPC_SLEEP_RETURN_CHANGE_MAIN Control clock source switching at cancellation of sleep mode e All module clock stop cancellation modification POL EP G_TMROOFF or Select whether the TMR units can PDL_LPC_TMR_UNIT_0 or PDL LPC TMR UNIT 1 or be used to exit from All module clock stop mode PDL_LPC_TMR_BOTH Return value True if all parameters are valid and exclusive otherwise false Category LPC References R_LPC_Create RO1USOO59EG0111 Rev 1 11 REN ESAS Page 113 of 429 Aug 01 2014 RX220 Group 4 Library Reference Remarks Sleep mode is utilised by some peripheral drivers to turn off the CPU when required When entering software standby the oscillation stop detection function is disabled The detection is re enabled if software standby mode is interrupted If Sleep mode return clock source switching has been enabled the only possible clock sources are the LOCO or sub clock oscillator When PDL_LPC_SLEEP_RETURN_CHANGE_HOCO is selected the frequencies of the internal clocks ICLK PCLKD PCLKB and FCLK must be no more than the selected clock source frequency 2 before a transition is made to sleep mode The sleep mode return clock source switching function and clock source switching function by the ELC cannot be used at the same time Do not set u
284. clock Main clock 0 Power on 0 Operating 1 Power off 1 Stopped b7 b6 b4 b3 b2 bi bO Selected clock source Main clock oscillation stop detection 000b LOCO 0 001b HOCO 0 0 Disabled 0 Normal operation 010b Main clock 1 Enabled 1 Stop detected 011b Sub clock True Clock generation circuit R_CGC_Control e Use R_CGC_Control to clear the main clock oscillation stop detection flag RPDL definitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t Status_flags R_CGC_Get Status amp Status_flags R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 56 of 429 RX220 Group 4 Library Reference 4 2 2 Interrupt Control Unit 1 R_INTC_SetExilnterrupt Synopsis Select the external interrupt pins Prototype bool R_INTC_SetExtinterrupt uint32_t data Pin selection Description 1 2 Assign the external interrupt pins data Allocate the pins for signals IRQO to IRQ7 All selections are optional If multiple selections are required use to separate each selection If no pins are required specify PDL_NO_DATA PDL_INTC_IRQO_P30 or PDL_INTC_IRQO_P10 or PDL_INTC_IRQO_PDO PDL_INTC_IRQ1_P31 or PDL_INTC_IRQ1_P11 or PDL_INTC_IRQ1_PD1 PDL_INTC_IRQ2_P32 or PDL_INTC_IRQ2_P12 or PDL_INTC_IRQ2 PD2 PDL_INTC_IRQ3_P33 o
285. cluding switching between comparison addition and subtraction modes Writing data to the DOC Reading result from DOC Rev 1 11 2tENESAS Page 45 of 429 RX220 Group 3 Types and definitions 3 Types and definitions 3 1 Data types This section describes the data types used in this library For details about the setting values refer to the section 4 2 Description of Each API The header files stdint h and stdbool h are included with the Renesas RX compiler Table 1 Data types Type Defined in Description Range bool stdbool h Boolean 0 false to 1 true double C Floating point 64 bits uint8_t Unsigned 8 bits 0 to 255 uint16 t Unsigned 16 bits 0to2 1 r 4 Stdint h signed 19 bis ee int32_t Signed 32 bits 27 to2 1 uint32_t Unsigned 32 bits 0to27 1 3 2 General definitions e PDL_NO_FUNC Used as a parameter when there is no applicable function e PDL_NO_PTR Used as a parameter when there is no applicable data location e PDL_NO_DATA Used as a parameter when there is no applicable data value e PDL_MCU_GROUP The MCU group supported by this build of the driver library It is defined as RX220 A usage example is if PDL_MCU_GROUP RX220 error Wrong RPDL endif e PDL_VERSION The version number of the RPDL library The number is stored in BCD format xx xx For example 0100h is v1 00 A usage example is const uintl6_t rpdl_version_number
286. conds or double The value to be put in register ADSSTR uint8_t True if a valid unit is selected otherwise false Category 12 bit ADC Reference R_ADC_12_CreateUnit Remarks e lf analog channels are used as the input sources call this function after calling R_ADC_12_CreateUnit e Function R_CGC_Set must be called with the current clock source selected before using this function e Make sure no more than 1 channel is configured with the parameter of PDL_ADC_12_CH_DOUBLE_TRIGGER_ENABLE e Channels 8 15 share the same ADSSTR register Once set sampling time for each of them the same setting applies to all the other channels Alater setting overwrites the previous one e Make sure sampling time calculated or specified for channel 0 and self diagnosis are the same RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 301 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Configure ANOOO R_ADC_12_CreateChannel 0 0 PDL_ADC_12_CH_GROUP_A PDL_ADC_12_CH_ADSSTR_CALCULAT 5E 6 PI R01US0059EG0111 Rev 1 11 Page 302 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 R_ADC_12_ Destroy Synopsis Prototype Description Return value Category Reference Remarks
287. configured with a 25 to 75 window and to generate an NMI Interrupt if it does time out Because the watchdog timer is not refreshed it does time out and the NMI_handler function is called Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_io_port h include r_pdl_intc h include r_pdl_iwdt h PDL device specific definitions include r_pdl_definitions h Bit mask for underflow and refesh error flags define BIT_MASK_REFEF_UNDFF 0xC000 static void NMI_handler void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Enable the IWDTCLK clock R_CGC_Set PDL_CGC_CLK_IWDTLOCO L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA Gouno Set output pins for LED R_IO_PORT_Set PDL_IO_PORT_1_5 PDL IO PORT OUTPUT LI Turn off LEDI R_IO_PORT_Write PDL_IO PORT_1_5 1 Enable the NMI interrupt for IWDT R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_IWDT_ENABLE NMI_handler 7 Configure WDT with a 75 to 25 window generate NMI on time out R_IWDT_Set PDL_IWDT_TIMEOUT_8192 PDL_IWDT_CLOCK_OCO_16 PDL_IWDT_WIN_START_75 PDL_IWDT_WIN_END_25 PDL_IWDT_TIMEOUT_NMI Wait for time out while 1 s
288. control PDL_SPI_PARITY_NONE or PDL_SPI_PARITY_EVEN or Disable or enable the addition of the parity bit PDL_SPI_ PARITY ODD data4 Extended timing control optional All items apply only to Master mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA if not required Rev 1 11 Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK_DELAY_8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or PDL_SPI_SSL_DELAY_4 or PDL_SPI_SSL_DELAY_5 or PDL_SPI_SSL_DELAY_6 or PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY_8 Extended next access delay The number of bit clock periods between the end of RSPCK oscillation and the negation of the active SSL pin Ignored in Slave mode PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 The number of bit clock periods plus two cycles of the peripheral cloc
289. cquires the channel status and the byte counts data1 Select channel SCIn where n 1 5 6 9 or 12 data2 The status flags shall be stored in one of the following formats depending on the current mode Note Some bits are Not Applicable NA in all modes see descriptions Asynchronous or Synchronous modes Not IIC Mode b7 b6 b5 b4 b3 b2 bi bO Reception error detection RxD pin level Framing Parity Transmit p NA to SPI 0 Overrun Async Mode Async Mode status o mode Only Only 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High Smart card mode b7 b6 b5 b4 b3 b2 bi bO Error detection RxD pin 7 Transmit status 0 Overrun Error signal Parity 0 level 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High IIC Mode b7 b1 bO ACK NACK flag 0 This is updated every time an ACK or NACK is received 0 ACK received 1 NACK received data3 The storage location for the last byte that was received Specify PDL_NO_PTR if this information is not required data4 The storage location for the number of characters that are have been transmitted in the current transmission Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available data5 The storage location for the number of characters that are have been received in the current reception
290. d The last byte to be read shall be completed with a NACK signal e If no callback function is specified this function will operate in polling mode The status flags will be used to manage the data reception If the I2 C channel s control registers are directly modified by the user this function may lock up If an error occurs during this polling process the function will terminate Ifthe DMAC or DTC is used use R_IIC_MasterReceiveLast to complete the transfer e Use R_IIC_GetStatus to determine if the transfer was successful e False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create e False will be returned if the bus is busy due to another master on the bus RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 5 bytes from device 0xAA on channel 0 using polling R_IIC_MasterReceive 0 PDL_NO_DATA OxAA data_array 5 PDL_NO_FUNC 0 R01US0059EG0111 Rev 1 11 ztEN ESAS Page 272 of 429 Aug 01 2014 RX220 Group 6 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process bool R_IIC_MasterReceiveLast u
291. d Read data from an I O port I O port O_PORT_ Write Write data to an I O port O PORT Compare Check the pin states on an I O port O PORT Modify Modify the pin states on an I O port O_PORT_Wait Wait for a match on an I O port O PORT _NotAvailable Configure I O port pins that are not available Multifunction Pin Controller MPC_Write Read a PFC register Write to a PFC register MPC_ Modify Modify a PFC register MCU_ Control Control the operation of the MCU MCU operation MCU_GetStatus Read the MCU status MCU_OFS Configure the device start up operation LVD_Create Configure the voltage detection circuit Voltage Detection R_ R_ R_ R_ R_ R_ R_ R_MPC_ Read R R_ R RI R_ R_ R_ LVD_Control Control the voltage detection circuit Circuit R_LVD_GetStatus Check the status of the voltage detection module W PO PO CO PO OO CO N O1 BR Co PO gt O OO IN Clock Frequency R_CAC_Create Configure the clock accuracy circuit Accuracy 2 R_CAC_Desiroy Stop the clock accuracy circuit Measurement 3 R_CAC_Control Control the clock accuracy circuit Circuit 4 R_CAC_GetStatus Read the clock accuracy circuit status 1 R_LPC_ Create Configure the MCU low power conditions Low Power 2 R_LPC_ Control
292. d delay between the assertion of the SSL pin and the start of PDL_SPI_CLOCK_DELAY_EXTENDED RSPCK oscillation e SSL negation delay Select the minimum or extended delay between PDL_SPI_SSL_DELAY_MINIMUM or Pie PDL SPI SSL DELAY EXTENDED the end of RSPCK oscillation and the negation of the active SSL pin e Next access delay PDL_SPI_NEXT_DELAY_MINIMUM or 2000 the minimum or extended delay between PDL_SPI_NEXT DELAY EXTENDED e end oi one trame and the start OF the ne frame Return value True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks e For Slave mode operation configure command 0 e When Clock synchronous Slave mode is used avoid selecting mode 0 or mode 2 e f parity is enabled while in Master mode both the frame data length and data transfer format should be the same for each command Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configure SPI channel 0 commands 0 and 1 R_SPI_Command 0 r 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_ASSERT_SSLO PDL_SPI_LENGTH_8 PDL_SPI_MSB_ FIRST PDL_NO_DATA R_SPI_Command 0 1 PDL_SPI_CLOCK_MODE_1 PDL_SPI_ASSERT_SSL1 PDL_SPI_LENGTH_8 PDL_SPI_LSB_ FIRST PDL_NO_DATA R01US005
293. d while PDL_SCI_GSM_SCK_START GSM mode is enabled data2 IIC Mode only Control the channel e Stop condition generation PDL_SCI_IIC_STOP A stop will be output on the bus e Clock Synchronisation Disable or enable the IIC clock PDL_SCI_IIC_CLOCK_SYNC_DISABLE or synchronisation PDL_SCI_IIC_CLOCK_SYNC_ENABLE Note Clock synchronisation is enabled by default as required for normal operation True if all parameters are valid otherwise false Category SCI Reference None Remarks None R01US0059EG0111 Rev 1 11 REN ESAS Page 259 of 429 Aug 01 2014 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Terminate SCI reception on channel 1 R_ SCT Control 1 PDL_SCI_STOP_RX R01US0059EG0111 Rev 1 11 Page 260 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 11 R_SCI_GetStatus Synopsis Check the status of an SCI channel Prototype bool R_SCI_ GetStatus uint8_t data1 Channel selection uint8_t data2 Status flags uint8_t data3 Last byte received uinti6_t data4 Bytes transmitted uint16_t data5 Bytes received Description A
294. data3 Monitor 2 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or Select no action a reset PDL_LVD_INTERRUPT_NMI_DETECT_RISE or on low voltage detection PDL_LVD_INTERRUPT_NMI_DETECT_FALL or or an interrupt when a PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_FALL or specified voltage event is PDL_LVD_INTERRUPT_MI_DETECT_RISE or detected PDL_LVD_INTERRUPT_MI_DETECT_FALL or PDL_LVD_INTERRUPT MI DETECT RISE_AND_ FALL e Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FILTER_LOCO_DIV_4 or PDL_LVD_FILTER_LOCO _DIV_8 Pin selection PDL_LVD_VDET2_PIN_VCC or Monitor VCC or the PDL_LVD_VDET2_PIN_CMPA2 CMPA2 pin data4 Monitor 2 voltage detection level Specify PDL_NO_DATA if not required PDL_LVD_VOLTAGE_LEVEL_415 or PDL_LVD_VOLTAGE_LEVEL_400 or PDL_LVD_VOLTAGE_LEVEL_385 or PDL_LVD_VOLTAGE_LEVEL_370 or PDL_LVD_VOLTAGE_LEVEL_355 or PDL_LVD_VOLTAGE_LEVEL_340 or PDL_LVD_VOLTAGE_LEVEL_325 or PDL_LVD_VOLTAGE_LEVEL_310 or PDL_LVD_VOLTAGE_LEVEL_295 or PDL_LVD_VOLTAGE_LEVEL_280 or PDL_LVD_VOLTAGE_LEVEL_265 or PDL_LVD_VOLTAGE_LEVEL_250 or PDL_LVD_VOLTAGE_LEVEL_235 or PDL_LVD_VOLTAGE_LEVEL_220 or PDL_LVD_VOLTAGE_LE
295. ddress const uint8_t eeprom_data_array_1 ARRAY_1_ SIZ EPROM_MEMORY_ADDRESS_LOWER 0x11 0x22 0x33 0x44 0x55 const uint8_t eeprom_data_array_2 ARRAY_2_SIZE EEPROM_MEMORY_ADDRESS_LOWER 5 0x66 0x77 0x88 0x99 OxAA OxBB OxCC OxDD Ox OxFF uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Select IIC Pins R_IIC_Set PDL_IIC_PIN_SDA P13 PDL_IIC PIN SCL P12 Configure the DTC controller R_DTC_Set PDL_DTC_ADDRESS_FULL R01US0059EG0111 Rev 1 11 Page 398 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples dtc_vector_table Set up a DTC channel for IIC transmission R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_ FIX PDL_DTC_SIZE_8 PDL_DTC_IRQ_ COMPLETE PDL_DTC_TRIGGER_IICO_TX dtc_iicl_tx_transfer_data eeprom_data_array_l uint8_t amp RIICO ICDRT A P RRAY_1 SIZE TA C channel for IIC reception This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DTC_Create DIC_NORMAL DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_PLUS DIC_SIZE_8 DTC_IRQ_COMPLETE DIC_TRIGGER_IICO_RX _iicl_rx_transf
296. de Figure 56 Example of CRC calculation R01US0059EG0111 Rev 1 11 Page 418 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 22 12 bit Analog to Digital Converter Figure 57 shows ADC_ 12 used in single scan mode with a software trigger and a specified sampling time Peripheral driver function prototypes include r_pdl_adc_12 h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h Array used to read the ADC results uintl6_t ADC_12_result 16 void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Configure analog input for ANO15 R_ADC_12_Set PDL_ADC_12_ PIN_ANO15_PE7 Configure ADC for single scan R_ADC_12_CreateUnit 0 p DL_ADC_12_SCAN_SINGLE DL_ADC_12_ADSSTR_CALCULATI PDL_NO_DATA D pP TA f PDL_NO_FUNC PDL_NO_FUNC Configure ADC on ANO15 R_ADC_12_CreateChannel 0 15 PDL_NO_DATA 5E 6 Start ADC R_ADC_12_ Control PDL_ADC_12_0_ON Read ADC result R_ADC_12_Read 0 ADC_12_result PDL_NO_PTR Shut down ADC R_ADC_12_Destroy 0 Figure 57 Example of ADC_12 R01US0059EG0111 Rev 1 11 Page 419 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 23 Comparat
297. de and continuous scan mode or when the ADC conversion scan cycle is complete for Group A in group scan mode Specify PDL_NO_FUNC if no callback function is required R01US0059EG0111 Rev 1 11 Page 299 of 429 Aug 01 2014 RENESAS RX220 Group Description 4 4 Return value Category References Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func2 The function to be called when the ADC conversion scan cycle is complete for Group B in group scan mode Specify PDL_NO_FUNC if no callback function is required data8 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid and exclusive otherwise false 12 bit ADC R_CGC_Set e Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 6 e If an external trigger is used the low level pulse width must be at least 1 5 PCLKD cycles e This function brings the converter unit out of the power down state e Acallback function is executed by the interrupt processing function This means tha
298. e Add include file directory window enter the details as shown Add include file directory Base path Project directory i WorkSpace rpdl_lib_test rpdl_lib_test Sub Directoryy RPDL Cancel Click on OK to close the window Click on the Add button In the Add include file directory window enter the details as shown X Click on OK to close the window R01US0059EG0111 Rev 1 11 Page 5 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 4 Add the RPDL library file The library file is added to the list used by the linker application Select the Link Library tab From the Show entries for drop down menu select Library files Click on the Add button In the Add library file window select Project directory and enter RPDL RX220_library as the File path Add library file Base path Project directory X i WorkSpace rpdl_lib_test rpdl_lib_test File path RPD LARX lt 220_library Cancel To use library with debug information enter RPDL RX220_library__debug as the File path Modify library file Base path Project directory v i WorkSpace rpdl_lib_test rpdl_lib_test File path RPD LAAX220_library_debug Cancel Click on OK to close the window Click on OK to return to the main HEW window R01US0059EG0111 Rev 1 11 Page 6 of 429 Aug 01 2014 RENESAS RX220 Gro
299. e products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved
300. e calling this function e Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed e This function unless configured not to will by default automatically start a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_ Control function to manually generate a stop e If a callback function is specified and the interrupt priority level is zero this function will return false e The SCI IIC module is always configured to use Reception and Transmission interrupts IICINTM bit 1 rather than ACK NACK interrupts This means that if using the DMAC or DTC to transmit then all data will be transmitted even if the slave device fails to ACK PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 9 define SLAVE_ADDRESS OxAO Buffer for IIC data extern uint8_t IIC_Buffer 10 void func void Wait while send 10 bytes R_SCI_IIC_Write CHANNEL _SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIc_Buffer PDL_NO_FUNC Rev 1 11 REN ESAS Page 255 of 429 RX220 Group 8 Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 4 Library Refe
301. e clock source R_CGC_Control PDL_CGC_CLK_HOCO PDL_NO_DATA PDL_CGC_RTC_TO_B void Alarm_handler void uint8_t flags uint32_t time uint32_t date uint8_t buffer 50 Read time R_RTC_Read PDL_RTC_READ_CURRENT amp flags amp time amp date sprintf char buffer Time d d d d d d r n int time amp OxF00000 gt gt 20 int time amp 0x0F0000 gt gt 16 int time amp 0x00F000 gt gt 12 int time amp 0x000F00 gt gt 8 int time amp 0x0000F0 gt gt 4 int time amp 0x00000F gt gt 0 R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA buffer 0 PDL_NO_FUNC Configure the clock R01US0059EG0111 Rev 1 11 Page 366 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples R_RTC_Control PDL_NO_DATA PDL RTC_UPDATE_ALARM_ TIME PDL_NO_DATA PDL_NO_DATA time 0x10 Alarm in another 10 seconds PDL _NO_DATA PDL_NO_DATA Error Adjust PDL_NO_DATA Periodic Enter software standby mode true bSoftStdbyEnter bSoftStdbyEnter true Figure 30 Example of using RTC is used and wake up from software standby mode R01US0059EG0111 Rev 1 11 Page 367 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 17 Independent Watchdog Timer Figure 31 shows an example of Independent Watchdog timer usage The watchdog timer is
302. ection uint32_t data2 Current count uint32_t data3 Alarm count uint32_t data4 Alarm mask uint16_t datad Error Adjustment uint16_t data6 Periodic configuration Change RTC settings and update counter in binary count mode data1 Change the clock operation To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA e Clock output control PDL_RTC_OUTPUT_DISABLE or Disable or enable the 1 Hz 64 Hz clock output PDL_RTC_OUTPUT_ENABLE on the RTCOUT pin Clock RTCOUT output period Select RTC counting will be stopped during writing RTCOS PDL_RTC_OUTPUT_RTCOS_1HZ or RTCOUT outputs 1 Hz PDL_RTC_OUTPUT_RTCOS 64HZ RTCOUT outputs 64 Hz e Clock control PDL_RTC_CLOCK_STOP or PDL_RTC_CLOCK_START Stop or re start the clock Reset control PDL_RTC_ RESET START Start the reset process data2 The new current count value Count seconds in 32 bits binary display If not required specify PDL_NO_DATA data3 The new alarm count value Setting the alarm register corresponding to 32 bit binary counter If not required specify PDL_NO_DATA data4 The new alarm mask value in 32 bits binary format Setting the alarm enable corresponding to 32 bit binary alarm counter If not required specify PDL_NO_DATA data5 Configure the Error Adjustment options To set multiple options at the same time use
303. ections are required use to separate each selection The default settings are shown in bold e Transfer mode selection PDL_DTC_NORMAL or Normal or PDL_DTC_REPEAT or Repeat or PDL_DTC_BLOCK Block mode PDL_DTC_SOURCE or If Repeat or Block mode is selected select the source PDL_DTC_DESTINATION or destination side to be the Repeat or Block area e Address direction selection PDL_DTC_SOURCE_ADDRESS_FIXED or After a data transfer leave the source PDL_DTC_SOURCE_ADDRESS_PLUS or address unchanged increment it or PDL_DTC_SOURCE_ADDRESS_MINUS decrement it PDL_DTC_DESTINATION_ADDRESS FIXED or After a data transfer leave the PDL_DTC_DESTINATION_ADDRESS_ PLUS or destination address unchanged PDL_DTC_DESTINATION_ADDRESS_MINUS increment it or decrement it e Transfer data size Se a a a or 4 bytes to be transferred in one PDL_DTC_SIZE 32 P i e Chain transfer control PDL_DTC_CHAIN_DISABLE or Disable chain transfer operation PDL_DTC_CHAIN_CONTINUOUS or Perform continuous chain transfers or PDL_DTC_CHAIN_0 Perform a chain transfer when the transfer counter is changed from 1 to 0 or 1 to transfer size block size e Interrupt generation PDL_DTC_IRQ_COMPLETE or Select interrupt request generation when the PDL_DTC_IRQ_TRANSFER transfer sequence completes or for every transfer e Trigger selection Name Trigger cause PDL_DTC_TRIGGER_CHAIN or Chain transfer PDL_DTC_T
304. eeeeeceeeeeceeeeeeaeeseaeeseeeeessaeeesseeeeenees 375 5 18 5 Synchronous Full Duplex Operation cceccceeeccecececeeeeeeeeeeeceeeeecaeeesaaeeeeaeeseeeesaeeesaeeneneeseaees 377 5 18 6 SCI Reception in Asynchronous Multi Processor mode 0 cccccceceeseeceessseeeeeeeseeeeeesaeeeeeeaas 379 5 18 7 SCI Transmission in Asynchronous Multi Processor MOG cccceeeeeeeeceeeeeeeeeeeesaeeteneeeeaees 381 518 8 SSGMASPlMOdG ci nc hit eed uti a hat on tpeeate Gade a a eneee ataa ae aa eiea tadel 383 518 9 SSCA MG MOC tein euceeh cputedieie Geld aae a aa ai e ear a aaae aaa aeda aael 384 5 18 10 SCl in IIC Mode using DMAC ssssssseesseeeseessesssressrssrnssrnssrnsssrnssrnssrnsttnsrnnstnsstnnstnnstnnsnnnsnnnsnnn tt 386 5 18 11 SCI in HC Mode Using DTO srsisi iiianoe aa a EA ATE 388 5 19 FC Bus INC ace aie aiaa a e teat a a a a da eta besten aae aaae ae aaaea 391 S19 MaS MODS ine e a ps a a e A EE a aaae E a a 391 1 Configuration and transmission ccccccccesseceeseneeeeeeeaeceseesaeeecsesaeeessesaeseesesaeeeeseaeeesseneeeeseaas 392 2 EIRE IC i EE E Manet TT E E E E E E T 393 5 19 2 Master mode with DMAC c cccccececeeeceeeneeeeeeeeeeeeceaeeecaaeeeeaaeseeeeecaeeesaaesseneeseeeeeseaeeesaeeseaeesnaees 394 5 19 3 Master mode with DTC 00 cceeeceeecceceeeeeeeeeeeaeeeeeeeceaeeeeaaeseeeeeeeaeeesaaeseeaaeseeeeeecaeeesaeeesaeeseneessaees 398 519 4 Slave MOC naereid e a aa eaa a rat Gaus egal aE aS aaa aaa ad aaa ee r
305. eeeeeseeeesaeeseaeeseenees 429 REVISION HISTOL Y isar orra Sa ees EA ca as E A Se Fe ete esd EEA E Se ed estes te ee a A 1 RX220 Group 1 Introduction 1 Introduction The Renesas Peripheral Driver Library RPDL is a unified API for controlling the peripheral modules on the microcontrollers made by Renesas Electronics Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 1 System configuration with all peripherals supported by RPDL Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 2 System configuration with middleware taking direct control of some peripherals The library is packaged as a A binary file containing all of the peripheral driver functions b Header files containing the information that the user needs to call any of the functions from their own application code and c Interrupt handlers supplied as source code For best use of this library it is required that the user will have the following documents as a minimum i The hardware schematic diagram ii The MCU hardware manual jii This RPDL API User s manual The binary file is produced using the Renesas RX C tool chain It should be usable by another linker that conforms to the Renesas Application Binary Interface RPDL has not been designed to be compatible for use with an RTOS The coding standards and naming conventions are specified by Renesas R01US0059EG011
306. eference R_CRC_Create R_CRC_Write Remarks e None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t CRCresult Read the CRC result and clear it R_CRC_Read PDL_CRC_RETAIN_RESULT amp CRCresult R01US0059EG0111 Rev 1 11 Page 295 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 2 24 12 bit Analog to Digital Converter 1 R_ADC_12 Set Synopsis Select the I O pins for the 12 bit ADC Prototype bool R_ADC_12_Set uint32_tdata ADC unit selection Description Select the I O pins for the12 bit ADC data Select the pin set options To set multiple options at the same time use to separate each value e Pin selection PDL_ADC_12_PIN_ANOOO_ P40 Select P40 for ANOOO PDL_ADC_12_PIN_ANO0O1_P41 Select P41 for ANOO1 PDL_ADC_12_PIN_ANO02_P42 Select P42 for AN002 PDL_ADC_12_PIN_ANO03_P43 Select P43 for ANOO3 PDL_ADC_12_PIN_ANO04 P44 Select P44 for ANO04 PDL_ADC_12_PIN_ANO05 P45 Select P45 for ANOOS5 PDL_ADC_12_PIN_ANO06_P46 Select P46 for ANOO6 PDL_ADC_12_PIN_ANO07_P47 Select P47 for ANOO7 PDL_ADC_12_PIN_ANO08 PEO Select PEO for ANOO8 PDL_ADC_12_PIN_ANOO9 PE1 Select PE1 for ANOO9 PDL_ADC_12_PI
307. efinitions include r_pdl_cpa h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t StatusFlags Read the CPA status R_CPA_GetStatus amp StatusFlags R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 309 of 429 RX220 Group 4 2 26 1 Synopsis Prototype Description Return value Category References Remarks RO1US0059EG0111 Aug 01 2014 4 Library Reference Data Operation Circuit R_DOC Create Configure the Data Operation Circuit bool R_DOC_Create uint8_tdata1 Configuration uinti6 tdata2 Output value void func Callback function uint8_t data3 Interrupt priority level Enable the DOC module and set the operating conditions data1 Operation Mode PDL_DOC_COMPARISON_MATCH or PDL_DOC_COMPARISON_MISMATCH or PDL_DOC_MODE_ADD or PDL_DOC_MODE_SUBTRACT Specify the mode of operation data2 This meaning of this parameter depends upon the Operation Mode Operation Mode Description Comparison The comparison value Addition The initial output value before any additions are made Subtraction The initial output value before any subtractions are made func The function to be called when a DOC interrupt is generated Specify PDL_NO_FUNC if no callback function is required data3 The interrupt pr
308. egister TCNTU PDL_MTU2_ REGISTER _COUNTER_V Timer counter V register TCNTV PDL_MTU2_REGISTER_COUNTER_W_ Timer counter W register TCNTW PDL_MTU2_REGISTER_TGRU General registerU PDL_MTU2_REGISTER_TGRV General register V PDL_MTU2_REGISTER_TGRW General register W TCNT_TCNTU_ value For n 0 to 4 The timer counter TCNT value For n 5 The timer counter TCNTU value This will be ignored if the register is not selected TGRA_TCNTV_value For n 0 to 4 The register TGRA value For n 5 The timer counter TCNTV value This will be ignored if the register is not selected TGRB_TCNTW_ value For n 0 to 4 The register TGRB value For n 5 The timer counter TCNTW value This will be ignored if the register is not selected TGRC_TGRU_value For n 0 3 or 4 The register TGRC value For n 5 The register TGRU value If the corresponding channel is stopped make sure the value is not TCNTU 1 This will be ignored if the register is not selected TGRD_TGRV_value For n 0 3 or 4 The register TGRD value For n 5 The register TGRV value If the corresponding channel is stopped make sure the value is not TCNTV 1 This will be ignored if the register is not selected TGRE_TGRW_ value For n 0 The register TGRE value For n 5 The register TGRW value If the corresponding channel is stopped make sure the value is not TCNTW 1 This will be ignored if
309. em clock using R_CGC_Set is omitted here Configure the NMI to be triggered by the LVD1 signal only no NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_LVD1_ENABL Callback_NMI PDL_NO_DATA Setup VDET1 to callback if VCC drops below 3 1V R_LVD_Create PDL _LVD_INTERRUPT_NMI_DETECT_FALL PDL_LVD FILTER DISABLI PDL_LVD_VOLTAGE_LEVEL_310 PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA NMI Callback function static void Callback_NMI void uint8_t status Read the NMI status R_INTC_GetExtInterruptStatus PDL_INTC_NMI amp status Did an LVD1 trigger occur if status amp BIT_6 0 Clear the LVD monitor 1 flag R_LVD_Control PDL_LVD_CLEAR_DETECTION PDL_NO_DATA Clear the NMI LVD1 flag R_INTC_ControlExtInterrupt PDL_INTC_NMI PDL_INTC_CLEAR_LVD1_FLAG Figure 8 Example of Voltage Detection Circuit use R01US0059EG0111 Rev 1 11 Page 325 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 6 Clock Frequency Accuracy Measurement Circuit Figure 9 shows an example of clock frequency measurement usage The main clock is used as the reference to measure the IWDT LOCO frequency Peripheral driver function prototypes include r_pdl_cac h include r
310. ensure they are configured correctly before calling this function False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create Normally bus activity for other slaves is ignored with no CPU involvement However in the specific case where a callback function is specified and the DTC or DMAC is specified for data transmission then any stop condition on the bus will cause the callback function to be called before any data has been transfered This function should then be called again to continue monitoring the bus RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Monitor channel 0 using polling R_IIC_SlaveMonitor 0 fd PDL_NO_DATA data_array 5 PDL_NO_FUNC 0 R01US0059EG0111 Rev 1 11 REN ESAS Page 275 of 429 Aug 01 2014 RX220 Group 4 Library Reference 8 R_IIC_SlaveSend Synopsis Write data to a master device Prototype bool R_IIC_SlaveSend uint8_t data1 Channel selection uint8_t data2 Data start address uint16_tdata3 Data count Description Transmit data on the specified channel data1 Select channel IICn where n 0 data2 The start address of the data to be sent data3 The number of bytes available to be sent Return value True if all parameters are valid exclusive and achievable o
311. eprom_data_array_l the EEPROM sub address to 0 DL_NO_FUNC e 1 P 0 Read data from the read_eeprom_data EPROM using the DMAC Prepare to read the next data PDL_DMAC_UPDATE_COUNT 5 Usage Examples Array size written sub address byte last byte 200ns fall time EPROM PDL_DMAC_CLEAR_DTIF using polling This will read back the bytes previously written except the last one RO1US0059EG0111 Aug 01 2014 Page 395 of 429 RX220 Group 5 Usage Examples which will be read using R_IIC_MasterReceiveLast _DMAC_Control L_DMAC_SUSPEN PDL_DMAC_ ENABLE PDL_DMAC_UPDAT ESTINATION PDL_DMAC_UPDATE_COUNT L_NO_PTR ata_storage ARRAY_1_SIZE 1 RRAY_2_SIZE 2 Array size written sub address byte last byte L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA Read data from the EEPROM using the DMAC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the using the DMAC R_IIC_MasterSend TIC_CHANNEL PDL_IIC_DMAC_TRIGG EPROM ADDRESS DL_NO_PTR r L_NO_FUNC while bus_busy true Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 i E 3 DL_NO_FUNC static void
312. er_data nt8_t amp RIICO ICDRR ta_storage RAY_1_SIZE 2 Array size written sub address byte last byte L_NO_DATA Gch ooo oe o Mate w H uvuUPpanrathbtutut t ow Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create ITIC_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E3 300 lt lt 16 200 Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Write the data into the EEPROM write_eeprom_data Prepare the next data to write to the EEPROM R_DTC_Control PDL_DTC_UPDATE_ SOURCE PDL_DTC_UPDATE_COUNT dtc_iicl_tx_transfer_data eeprom_data_array_2 PDL_NO_PTR ARRAY 2 SIZE PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 399 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend TIC_CHANNEL PDL_IIC_STOP_DISABL EPROM_ADDRESS eprom_data_array_l e 1 PDL_NO_FUNC 0 Read data from t read_eeprom_data EPROM using t
313. errupt request flag is set to 1 the flag will be cleared to 0 by this function RO1USO059EG0111 Rev 1 11 Page 130 of 429 Aug 01 2014 2tENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t StatusValue uint32_t SourceAddr Read the status and current source address for channel 2 R_DMAC_GetStatus 2 amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R01US0059EG0111 Rev 1 11 Page 131 of 429 Aug 01 2014 RENESAS RX220 Group 4 2 12 1 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference Data Transfer Controller R_DTC_Set Set the Data Transfer Controller options bool R_DTC_ Set uint8_t data1 Configuration options uint32_t data2 Vector table base address Set the global options for the Data Transfer Controller data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Read skip control PDL_DTC_READ_ SKIP_DISABLE or Disable or enable skipping of transfer data read PDL_DT
314. errupt_CP4_LYD c Interrupt_DMAC c Interrupt_DOC c Interrupt_ELC c Interrupt_IIC c Interrupt INTC c Interrupt MTU2 c Interrupt_not_RPDL c Interrupt_POE c Interrupt_RATC c Interrupt_SCl c Interrupt_SPl c Interrupt_TMF c resetprg c rpdl_lib_test c sbrk c E vecttbl c Download modules Dependencies Gero a a Aea Ready Ed E3 ES ES Default1 h Bl z p z e z z z B z 4 i TE R01US0059EG0111 Rev 1 11 Aug 01 2014 RENESAS 1 Introduction Page 9 of 429 RX220 Group 1 Introduction 9 Set the build options Use the key sequence Alt B R to open the RX Standard Toolchain window In this section only options which you must change from the default settings are described If you add RPDL in existing project see also 1 2 Compiler options when you use this product a Set the optimisation To avoid linking unused RPDL functions adjust the Compiler and Linker settings i Compiler Select the C C tab Use the key sequence Y O O to show the optimisation options Ensure that the Inter module optimization option is enabled RX Standard Toolchain Configuration C C Assembly Link Library Standard Library RTOS al gt Debug S Category v E a All Loaded Projects EES Optimize level C source file 2 Details C source file Assembly source file Speed or size Linkage symbol file Optimize for size V Inter module optimization
315. eseeeeeseeeeesaeessaeeseneeees 61 4 FP_INTC_CreateFastinterrupt 0 ccccccceseeceeeeeeeeeceeeeeeeaeeeeaaeeseaeeceeeeeseaeeeseaesseaeeseaeeesaeeeeaeseeeeesaas 62 5 R_INTC_CreateExceptionHandlerS cccccecsceceeceececeecceeeeeaaeeeeeeeceeeeecaaeeseaeeseeeeesaeeesaeeseeeeeaees 65 6 R_INTC_ControlEXxtinterrupt cccccceceeecceeeeeeeeeeeeeceeeeeceaeeeeaaeeseeeeeaeeesaaeeseaaeseeeeseaeeesaeeeeeeseaees 66 7 P_INTC_GetExtlnterruptStatus 20 00 ceccce cece eeeeeeeeeeee cee eeceaeeeeeeeseeeeeceaeeeeaaeseeeeeseaeeeseaeeseaeeseeeeeeaees 68 8 SREINDG Read maranan armi eano anane cated ack saad a sh gutting ota coh tee cant ae aa aa a AA AAE a 72 QO R NTC MO fees escapes cde e a A tae dest E a Sees aaa a A saute ote cols aA Aa EAA Aaa 73 TO RINTE MOAI oria Qetccelica tives scapes tas dente tastes uaa gente ea hesstcayeitdacqdavstesvipaatarfesetensthtsesaite aAa 74 A273 2 WOM OM aes rebates Sea haa essen ade Sasa ath toe devt deta feta sande A E tee ante tiaees 75 TH RE1OzPORT SOU cigs dics vets aaaea a dentey a a Eora ENa Ea aAA a AE AEA ARa ea A EAA RAES 76 2 R IO PORT Redad GON Oi eara a are aa r aa a Taa aea e e ATA a ArT eaa e n AE AE aSk E EE iasta 78 3 RilO PORT MOdihyC Ontrol grie eere san Ea ea Naa a aE AET E rantaa ERARE SASAE TEE 80 A o mRUI SPORM ARCA sf crit a a a a a ea a a a a a a isadte 82 Dyn RO FOR TWE e a a are tac tal a a a a em ahez hg 83 6 RIOPORT COMDATE er E A visi desteatiavaiiilastyg
316. ess changes according to the number of bytes 1 2 or 4 in each transfer Before calling this function call R_DTC_Set e Call this function before configuring the peripherals that will be involved in the data transfer e Call this function once for each peripheral that will trigger a transfer and for each chained transfer e For chain transfers each transfer data area in the chain must be contiguous e When all calls to this function are complete call R_DTC_Control to start the DTC RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve 16 bytes full address mode for the CMTO triggered transfer data area Use a 32 bit type to make the address a multiple of 4 uint32_t dtc_cmtO_transfer_data 4 void func void Configure the DTC for CMTO R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CMTO dtc_cmt0O_transfer_data void 0x0000A400 void 0x0000BB00 100 0 RX220 Group 4 Library Reference 3 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 R_DTC_Destroy Disable the Data Transfer Controller bool R_DTC_Destroy void No parameter is requi
317. eter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_CGC_Set R_TMR_CreateChannel R_TMR_CreateUnit RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 195 of 429 RX220 Group Remarks Program example RO1US0059EG0111 Aug 01 2014 Rev 1 11 4 Library Reference e Function R_CGC_Set must be called with the current clock source selected before using this function e This function is an alternative to R_ TMR_CreateChannel and R_TMR_CreateUnit e Please use R_TMR_Set to select the output TMOn pin as required This function will return false if a pin is enabled but is not set properly e This function stops the timer on completion so no other TMR function calls are required e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 e If no callback function is specified this function waits for the CMIB flag to indicate that the one shot time delay is complete If the timer s control registers are directly modified by the user this function may lock up e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e The timer period limits depend on the peripheral module clock PCLKB
318. event R_ELC_Control PDL_ELC_SINGLE_PORT PDL_ELC_SINGLE_PORT_0O PDL_ELC_PIN_PORT_B_0 PDL_ELC_PIN_OUTPUT_TOGGLE Enable all Links R_ELC_Control PDL_ELC_ENABLE PDL_NO_DATA PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 150 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 2 14 1 Synopsis Prototype Description 1 2 Multi Function Timer Pulse Unit R_MTU2_Set Configure the Multi function Timer Pulse Unit bool R_MTU2_Set uint8_t data1 Channel selection uint32_t data2 Configuration for a channel Set up the global MTU options data1 The channel number n where n 0 to 5 data2 Pin configuration for the channel Use to separate each selection e Valid when n 0 PDL_MTU2_PIN_0A_P34 or PDL_MTU2 PIN 0A PB3 PDL_MTU2_PIN_0B P13 or PDL_MTU2_PIN_0B P15or Select the P13 P15 or PA1 pin for MTIOCOB PDL_MTU2 PIN 0B PA1 PDL_MTU2_PIN_0C_P22 or PDL_MTU2 PIN OC PB1 PDL_MTU2_PIN_0D_P33 or PDL_MTU2 PIN OD PA3 Select the P34 or PB3 pin for MTIOCOA Select the P32 or PB1 pin for MTIOCOC Select the P33 or PA3 pin for MTIOCOD Valid when n 1 PDL_MTU2_ PIN_1A_P20 or PDL_MTU2 PIN 1A PE4 PDL_MTU2_ PIN_1B P21 or PDL_MTU2 PIN 1B PB5 Select the P20 or PE4 pin for MTIOC1A Select the P21 or PB5
319. f status amp BIT_8 uint16_t BIT_8 amp amp RTC RCR2 BIT START 0 If warm start is detected and RTC is running then warm start R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA r nRTC Start in Warm start mode Control to change time r n 0 PDL_NO_FUNC R01US0059EG0111 Rev 1 11 Page 363 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Warm wake up Read time R_RTC_Read PDL_RTC_READ_CURRENT amp flags amp time amp date sprintf char buffer RTC Time before changing d d d d d d r n int time amp OxF00000 gt gt 20 int time amp 0x0F0000 gt gt 16 int time amp 0x00F000 gt gt 12 int time amp 0x000F00 gt gt 8 int time amp 0x0000F0 gt gt 4 int time amp 0x00000F gt gt 0 R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA buffer 0 PDL_NO_FUNC R_RTC_CreateWarm Alarm_handler Alarm handler 15 Alarm priority PDL_NO_FUNC Periodic Handler PDL_NO_DATA Periodic priority i R_RTC_Read PDL_RTC_READ_CURRI PDL_NO_PTR amp time amp date Configure the clock R_RTC_Control p _ DATA UPDATE_ALARM_TIMI DATA DATA 0x10 Alarm in another 10 seconds DATA DATA Error Adjust DATA Periodic ee yyurtu uuvu ul else If Cold start is detected the RTC clock should be re started R_SC
320. f the register is not selected TCDR_value The cycle data register value This will be ignored if the register is not selected TCBR_value The cycle buffer register value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_ControlChannel RO1USO059EG0111 Rev 1 11 REN ESAS Page 171 of 429 Aug 01 2014 RX220 Group 4 Library Reference Remarks e Either this function or R MTU2_ControlChannel must be used to start the timers e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call e The register access enable operation is executed at the start of this function The register access disable operation is executed at the end Therefore both options can be selected together with other changes in one function call e If the noise filter is enabled before starting the timer make sure at least 2 cycles of the selected noise filter clock has elapsed after the timer configuration use R_MTU2_Create e When generating PWM waveforms in complementary PWM mode 1 to complementary PWM mode 3 set the timer cycle data registers TCDR and timer dead time data registers TDDR to values that satisfy the
321. ference R_CMT_Control Control CMT operation bool R_CMT_Control uint8_t data1 Channel selection uint16_t data2 Configuration selection double data3 Period frequency or register data Modify the operation of a CMT channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer channel To set multiple options at the same time use to separate each value Counter stop re start PDL_CMT_STOP Disable the counter clock source PDL_CMT_START Enable the counter clock source e Value change request PDL_CMT_PERIOD or The parameter data3 will contain the new period PDL_CMT_FREQUENCY or frequency PDL_CMT_CONSTANT or constant register CMCOR or PDL_CMT_COUNTER counter register CMCNT value data3 The new period frequency or register value This will be ignored if a value change is not requested Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in the selected register uint16_t True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CMT_Create Remarks e R_CMT_Create must be used first to configure the channel e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with a value change in one function call To a
322. from reset this function will have no affect and can be omitted The IWDTCLK must be enabled using R_CGC_Set or R_CGC_Control e If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for IWDT The IWDT counter frequency must not be greater than the PCLB 4 Set the IWDTCLK division ratio accordingly This function will return false if this condition is detected R01US0059EG0111 Rev 1 11 Page 232 of 429 Aug 01 2014 2tENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h void func void Configure the IWDT R_IWDT_Set PDL_IWDT_TIMEOUT_16384 PDL_IWDT_CLOCK_OCO_256 R01US0059EG0111 Rev 1 11 Page 233 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_IWDT_Control Synopsis Prototype Description Return value Category Reference Control the Independent Watchdog operation bool R_IWDT_Control uint8_t data Control selection Modify the operation of the Independent Watchdog timer data Control the timer e Counter start refresh PDL _IWDT_REFRESH Start or refresh the counter by re loading the timeout value True if the parameter is valid otherwise false Independent Watchdog Timer R_IWDT_Set Remarks
323. g function R_MTU2_ Set Either R MTU2_ControlChannel or R_MTU2_ControlUnit must be used to start the timers e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e If the channel is configured for phase counting mode the counter clock source setting is ignored If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC e If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD e If synchronous mode is required at least two channels must be enabled for synchronous operation e Acompanion function R LMTU2_Create_load_defaults can be used to load the default values into the structure e Ifthe channel operation mode will be changed ensure that the timer is stopped use R_MTU2_ControlChannel or R_MTU2_ControlUnit e Ifthe noise filter is enabled wait for 2 cycles of the selected noise filter clock before starting the timer use R_LMTU2_ControlChannel or R_MTU2_ControlUnit Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl
324. ge time for disconnection detection double data5 Sampling time for internal re double data6 Pre charging or discharging void func1 Callback function for Group A uint8_tdata7 Interrupt priority for Group A void func2 Callback function for Group B uint8_t data8 Interrupt priority for Group B Set the ADC mode and operating condition data1 Select the ADC unit to be configured This must always be 0 data2 Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Rev 1 11 Input source PDL_ADC_12_INPUT_AN or PDL_ADC_12_INPUT_REF the internal reference voltage Select input from analog channels or Scan mode PDL_ADC_12_SCAN_SINGLE or PDL_ADC_12_SCAN_CONTINUOUS or PDL_ADC_12_SCAN_GROUP Select single scan continuous scan or group scan mode Trigger sources enable Not valid if PDL_ADC_12 SCAN GROUP is selected for data2 PDL_ADC_12_ASYNC_TRIGGER_ENABLE or PDL_ADC_12_SYNC_TRIGGER_ENABLE Enable the ADC to be started by asynchronous or synchronous trigger sources If neither option is selected only software will be used as the trigger source Value addition control for internal reference voltage Not valid if PDL_ADC_ 12 INPUT AN is selected for data2 PDL_ADC_12_REF_ADDITION_DISABLE or PDL_ADC_12 REF ADDITION ENABLE Disable or en
325. hannel Remarks e PDL_TMR_STOP is to disable the counter clock source but PDL_TMR_ELC_COUNT_STOP is to stop the counter triggered by the ELC If PDL_TMR_ELC_COUNT_STOP is selected the counter is stopped but the clock source is still running The system will wait for the next ELC event to trigger the counter again RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 198 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Load the counter on channel TMRO R_TMR_ControlChannel 0 PDL_TMR_COUNTER OxFF PDL_NO_DATA PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 199 of 429 Aug 01 2014 RENESAS RX220 Group 8 Synopsis Prototype Description Return value 4 Library Reference R_TMR_ControlUnit Write to timer unit registers bool R_TMR_ConirolUnit uint8_t data1 Unit selection uint32_t data2 Configuration selection uint16_tdata3 16 bit counter register value uint16_t data4 16 bit compare match A register value uint16_tdata5 16 bit compare match B register value Modify a timer units counter and compare registers data1 The unit number n where n 0 or 1 data2 The channel settings to be modified If multiple selections are required use
326. hannels R_ADC_12_ Destroy R_ADC_12_ Control Shut down the ADC unit Start or stop the ADC unit R_ADC_12_Read Read the ADC conversion results Comparator A R_CPA_Create Configure the Comparator A module R_CPA_Control Control the Comparator A module R_CPA_GetStatus Check the status of the Comparator A module Data Operation Circuit R_DOC_ Create Configure the Data Operation Circuit R_DOC_Destroy Disable the Data Operation Circuit R_DOC_Control Control the Data Operation Circuit R_DOC_Read Read the Data Operation Circuit result AJA CO PO DO OD OT BH OO PO BR CO PO NJ on BY R_DOC Write Write data to the Data Operation Circuit RO1US0059EG0111 Aug 01 2014 Rev 1 11 2tENESAS Page 49 of 429 RX220 Group 4 Library Reference 4 2 Description of Each API This section describes each API and explains how to use them showing a program example for each The description of each API is divided into the following items Synopsis Summarises processing by the API function Prototype The function format and a brief explanation of the arguments Description Explains how to use the API function and shows assignable parameters separating each argument with argumeni Return value Describes the returned value of the API function Ca
327. hat no other interrupt can be processed until the callback function has completed If reception is enabled and receive errors occur transmission will be blocked until the errors are cleared In Multi processor mode R_SCI_Send is to be called in pair the first one is to send ID ID cycle the second one is to send data Data cycle For ID transmission it will be sent by internal polling operation For Data transmission it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to section 5 18 7 For ID cycle the DMAC DTC trigger control and the callback function will be ignored Do not use this function in SPI mode use R_SCI_SPI_Transfer Do not use this function in IIC mode use R_SCI_IIC_Write When using interrupts to manage the transfer if the channel is operating in synchronous mode transmit only and with an external clock the TXD pin may need to be held active for longer up to half a bit period to avoid violating the data hold time for the receiving device If a delay is required the user should refer to the comments in the Transmit End interrupt processing routines in the file Interrupt_SCl c in the i_src folder and implement the delay in a way that is suitable for their application If using the DMAC or DTC this module does not know when the transmission has ended Therefore when it has completed the user must call the R_SCI_Control function with option PDL_SCI_STOP_TX to manually di
328. he DTC Prepare to read the next data R_DTC_Controli PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDAT dtc_iicl_rx_transfer_data PDL_NO_PTR amp data_storage ARRAY_1_SIZE 1 ARRAY_2_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA Read data from the EEPROM using the DTC read_eeprom_data static void write_eeprom_data void Set state variable so callback function will no how to behave g_IIC_Tx_State IIC_TX_STATE_WAIT_DTC Send data to the EEPROM using the DTC R_IIC_MasterSend IIC_CHANNEL PDL_IIC_DTC_TRIGG EEPROM_ADDRESS PDL_NO_PTR 0 iic_tx_end_handler 7 while g_IIC_Tx_State IIC_TX_STATE_FINISH uint32_t iic_flags uint16_t uint32_t uint32_t uintl6_t R_DTC_GetStatus dtc_iicl_tx_transfer_data flags Src dest counter amp flags ESTC amp dest amp counter PDL_NO_PTR R_IIC_GetStatus RO1US0059EG0111 Aug 01 2014 IIC_CHANN Rev 1 11 EL RENES AS Page 400 of 429 RX220 Group 5 Usage Examples amp iic_flags PDL_NO_PTR PDL_NO_PTR Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 E 3 DL_NO_FUNC static void read_eeprom_data void g_IIC_Rx_busy true Read data from the EEPROM using the
329. he alarm mask in 32 bits to enable alarm alarm_function 15 PDL_NO_FUNC PDL_NO_DATA Rev 1 11 RENESAS Page 219 of 429 RX220 Group 4 Library Reference 3 Synopsis Prototype Description Return value Category Reference Remarks Program example R_RTC_Destroy Shut down the Real time clock bool R_RTC_Desiroy void Stop the RTC counter and disable the sub clock to the RTC True RTC None e This function is available for both calendar count mode and binary count mode e This function is not required when using 48 pin package RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the RTC R_RTC_Destroy j RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 220 of 429 RX220 Group 4 R_RTC_Control Synopsis Prototype Description 1 3 R01US0059EG0111 Aug 01 2014 Modify the Real time clock operation bool R_RTC_Control uint32_t data1 Control selection uint16_t data2 Update selection uint32_t data3 Current time uint32_t data4 Current date uint32_t datad Alarm Time uint32_t data6 Alarm Date uint16_t data7 Error Adjustment 4 Library Reference uint16_t data8 Periodic configuration data1 Change the clock operation
330. he data storage location uint32_t data4 A pointer to the data storage location Read the Clock counters registers and status flags in calendar count mode data1 Specify what to read PDL_RTC_READ_CURRENT or PDL_RTC_READ ALARM Specify which time to read data2 The format of data2 is dependent upon data1 Format if datai PDL_RTC_READ_CURRENT The clock status shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 Mode Interrupt requests 6 42 hour cany Periodic Alarm 1 24 hour 1 Occurred b3 b2 bi bO Status 0 30 second adjustment Reset Clock 0 Normal operation 0 Normal operation 0 Stopped 1 Adjustment in progress 1 Reset in progress 1 Running Format if datai PDL_RTC_READ_ALARM The enable bits for the alarm shall be stored in the following format 1 enabled meaning the unit is part of the alarm setting 0 disabled meaning the unit is ignored Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 b3 b2 b1 bO 0 Year Month Day Day of week Hours Minutes Seconds data3 The day of the week and time Specify PDL_NO_PTR if it is not required See R_RTC_Create for the format data4 The year month and day Specify PDL_NO_PTR if it is not required See R_RTC_Create for the format True if all parameters are valid otherwise false Category Real time
331. he format below Specify PDL_NO_PTR if this information is not required b15 b14 b12 b11 b10 b8 0 Error command 0 Command pointer b7 b6 b5 b4 b3 b2 b1 bO NECES Transmit Parity error Mode fault Bus state Overrun buffer 0 buffer 0 error 0 Empty 0 Full 0 No error 0 No fault 0 Idle 0 No error 1 Full 1 Empty 1 Detected 1 Detected 1 Active 1 Detected data3 The storage location for the number of sequence loops that have been completed in the current transfer Specify PDL_NO_PTR if this information is not required True if all parameters are valid otherwise false SPI None e If the status flags are read and an error or fault flag is set to 1 the flag will be cleared to 0 by this function RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t StatusValue Read the status of channel 0 R_SPI_GetStatus 0 amp StatusValue PDL_NO_PTR RX220 Group 4 Library Reference 4 2 23 CRC calculator 1 R_CRC _Create Synopsis Prototype Description Return value Category References Remarks Program example Configure the CRC calculator bool R_CRC_Create uint8_t data Configuration Enable the CRC and set the operating conditions data Calculation optio
332. he register to be updated PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register or DTC Activation Enable register or PDL_INTC_REG_SWINTR Software interrupt activation register data2 The value to be written to the register Return value True if the parameter is within range otherwise false Category Interrupt control Reference None Remarks e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 69 e Write 1 to the SWINTR register to generate a software interrupt request Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set the IPL to 6 R_INTC_Write PDL_INTC_REG_IPL 6 Set the IR for IRQO to 0 R_INTC_Write PDL_INTC_REG_IR_ICU_IRQO 0 R01US0059EG0111 Rev 1 11 Page 73 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 10 R_INTC_Modify Synopsis Prototype Descri
333. he same EEPROM address locations are then read out in two bursts The DTC is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic tx end handler v id void iic rx_end handler void define EEPROM_MEMORY_ADDRESS_UPPER 0x00 define EEPROM_MEMORY_ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM_MEMORY_ADDRESS_UPP define IIC_CHANNEL 0 The Tx callback must process the following states typedef enum IIC_TX_STATE TIE E_FINISHED IIc WAIT_DTC IIC_TX E_WAIT_LAST_BYT IIC_TX_STATE X_ X static IIC_TX_STATE g_IIC_Tx_State IIC_TX_STATE_FINISHI volatile uint8_t g_IIC_Rx_busy volatile uint8_t data_storage 20 Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00002000 uint32_t dtc_vector_table 256 Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 void main void define ARRAY_1 SIZE 6 5 Data 1 address define ARRAY_2_ SIZE 11 10 Data 1 a
334. hen power on The standard load capacitance is for the case the sub clock resonator is not fitted PDL_CGC_SUB_CLOCK_CL_LOW or Adjust the drive level for a crystal with low or PDL_CGC_SUB_CLOCK_CL_STANDARD standard load capacitance data3 The frequency of the selected clock source in Hertz data4 The desired frequency of the System clock ICLK in Hertz data5 The desired frequency of the Peripheral module D clock PCLKD in Hertz data6 The desired frequency of the Peripheral module B clock PCLKB in Hertz Rev 1 11 REN ESAS Page 51 of 429 RX220 Group Description 2 2 4 Library Reference data7 The desired frequency of the Flash memory interface clock FCLK in Hertz data8 Select the sub clock oscillator stabilization times If no selections are required specify PDL_NO_DATA e Sub clock oscillator waiting time Compulsory option if PDL_CGC_CLK_SUB_CLOCK is selected ignore for 48 pin package Make sure to set the option whether Sub clock is used or not based on the actual board situation PDL_CGC_SUB_2 or PDL_CGC_SUB_4 or PDL_CGC_SUB 8 or PDL_CGC_SUB_16 or PDL_CGC_SUB_32 or PDL_CGC_SUB_64 or PDL_CGC_SUB_512 or PDL_CGC_SUB_1024 or PDL_CGC_SUB_2048 or PDL_CGC_SUB_4096 or PDL_CGC_SUB_ 16384 or PDL_CGC_SUB_32768 or PDL_CGC_SUB_65536 or PDL_CGC_SUB_131072 or PDL_CGC_SUB_ 262144 or PDL_CGC_SUB_524288 Select the oscillation settling time of the sub clock os
335. high impedance when PDL_TMR_OUTPUT_IGNORE_CM_A and PDL_TMR_OUTPUT_IGNORE_CM_B are selected e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R01US0059EG0111 Rev 1 11 Page 187 of 429 Aug 01 2014 2 ENESAS True if all parameters are valid and exclusive otherwise false RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure TMRO PCLKB clear after a compare match A R_TMR_CreateChannel 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_NO_DATA 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 R01US0059EG0111 Rev 1 11 Page 188 of 429 Aug 01 2014 RENESAS RX220 Group 3 R_TMR_CreateUnit Synopsis Prototype uint8_t data1 uint32_t data2 uint8_t data3 uint16_t data4 uint16_t datad uint16_t data6 void func void func2 void func3 uint8_t data7 Description 1 2 R01US0059EG0111 Aug 01 2014 data1 bool R_TMR_CreateUnit Configure a timer TMR unit Unit selection Output control 4
336. i rE A A A E A EA AE E E E EES 317 5 1 Glok Generation GGuits rererere aie a aa ia e e iee ea eiee eki 318 52 HINTErUpECONUO Acco a a a a a aa a aea a i e a 319 58 VO POfli nenii Aen a a a ee ae ae 321 54e MEUrOperationss iaaa a a a a a a Aat 323 5 5 Voltage Detection Circuit miraiet tananan naiai aaae aa aa E aA ees eed 324 5 5 Maskablesinte rrupts darain npani aiaa aap tee aai A as ad ai aaan aa aAa AAR AAAA 324 5 5 2 Non maskable Mterr ptS miraiant aaa aiaa arani anaa aAa a Raia 325 5 6 Clock Frequency Accuracy Measurement Circuit c cccccceeceeceeeeeeeeeee eee eeeeaeeeeeeeseaeeetaeeseaeeeeeeeee 326 5 7 LOW Powel CONSUMPTION siiscecsiecsaxectet a a r daw either a a aaa a A ar aaa a Ea aaa aE 328 Tek Software Standby MO s arra aa e aaa ra aa Ea ae aa a Ea aE aAa a ar Ea aSa taaan Naa 328 5 8 Register Write Protection ccccccceccceceeeeeeee cece ener ee eeeeaaaeee cess ee caaaaaaeee sees egeeeeaeaeeeseseegeeeaeaeeeeeeeeeee 329 DOr OMA CO OE See cg aieee inte a ease ctete teeta aa a a a dant a A e gees aai 330 5 10 Data Transier COntroller svccccias scgcssaeatecevss evaded devtecavaadedesduuetcdaats coedeecasthhdevietavuidede stn aa aTe a 333 510 1 Block transfer MOUS ciroen ane eE ddeesssgeleatansdecavhoaniede ea a ae e esie eane a 333 5 10 2 Chain transfer operation ccccceccceceeeceeeeeeeeseeeeeeeeceaeeeeaaeeeeaeecaeeeceaesseaaeseeeeeseaeeesaaeeseaeeseneessaees 335 511 Port Output Enablen ea e a
337. iahatiies 84 A mREIOTPORT MOGI Vaaa aeaa ea a aa torte ae Al a eet Za 85 8j HREIOSZROR MU Walt aa r eaa a a aa satan omer Nas R a 86 9 RJIO PORT NotAvailable iz s aa a aaa aa Gang the Ata a GL Ta 87 4 2 4 Multifunction Pin Controller ccscceccceceececeeeeeeeeeeeeeee eee ee seas eeeeeeseneeesaeeesaaeseeeeeseeeeesaeseeeeseeeees 88 yt ROMP CLRGAG a a oetcea ates a Abed stoune Mie SAC cede ANE Als orae Ma 89 2 me MPC WE a a5 geet mee ASS crac cnt as set aac eee a aa mad een tea at eat ah adh 90 ys ARMIRCuMOGITy 2 ahcsls cess cataatta te esos Sasi ANCL seen ar a eee A a ie a ONE deca hat 91 42 5 _ IMGUOperatio ns ste sicme axe hacia a sates Sta cce cde teva teen Rb dl aucemt mands acces ake a aaa 92 1 RuMGl COMTO ninnaa a eet ei tied SRE eed eee aE attest ee 92 2 RUMCW sGetStatus sites ok cacti Allee Rae Sa tin el ne Re ee 93 SB REIMCUSOFS izing a thie a ea eee ee 95 4 2 6 Voltage Detection Girc it seniseid eid uga viaaa ia doida aaa doaa 97 1 RLV Dt Creates nta e a aa R a lee dia ee a ae 97 2 R EVD Controlix rar nee ein aie a a Pee Se Cae a ae 100 A N w ie o o oO co N gt a gt A 0 ANDNTAWNANAWNANAN OTA WNANGTAWNANGTAWBNANMNARWNANAWBNANNYANwWDNANA DONA o x nna YS rere wH YS re N a a a aa YS YS rrr aa YS Terr TE we YS HY wa YS DH YH WH YK WH St R LVD GetStatU Saai a a i a ls a a ae a a aa 101 Clock Frequency Accuracy Measurement CirCuit ccccccecsscceceesnecece
338. ile assan r Ae eles Rael Mt ode eea Rnd an E a RO os 294 A R amp ECRG Read asiaa Ar helen ROA els A ees WO IN ead tease eed 295 4 2 24 12 bit Analog to Digital Converter cece cee eeeceeceeeee cent eeeeaeeeeeeeeeeeeeeeaeeesaaeseeeeeseaeeesaeeseneeenaees 296 Do RADG 122 S Ob xceccsctinsdicteigurcuctven secre tcl viendo ocesicant deel aiaaed ete eteieesae Wd a AAA 296 2 Ri ADC 12 Cr eateU nitetse ite weit Gia Pela ee Se A ea Ss 297 3 R ADC 12 CreateChannel cc 2i2 cists stares tahiti a a aa ieee oth ieee that ede 301 4 RADO 12 DOSO aeiia ti E EE eed HOS ua Bian aE heh ew dudes Ae E A aA EEE e 303 5 Re ADCO 12 Control tasaa eaii on al A ee a ye 304 6 ReADG2 1 2 ROA sas i ieam ied e a a ina One aa aaa a a EL ale aes 305 42 25 Comparator Arrera dii eat ieat aidai ag de Mi a aia ia ia ad i aA 306 1 ReiG PA Create esintisi n a i A N i a a Meee MS 306 2 RCRA Control ie iira iaaii i aioa i a i dias ad a bee aia iid a a a 308 3 R CPAS GetStatus he Kinia ie aa eeii a Aa ei a id a a 309 4 2 26 Data Operation CirCUit misaeni diaii iindern iiag iadi ai iaaii d ai iias 310 1 R DOC Create ie mnan ia Alben a i MAG a a ee e 310 2 R DOG DESV OY ocio i iiiaio ates aa Kiai iii iiaa iii toa i aii beeen 312 3 i R DOGCControlissiiniii iei ii ii iad idat a i eas 313 4 R DOGC Readiris iiid i iiaii ai Gay ad aban aiii ney ie OE 315 5 R DOC Write pisteiden eenid edin eaii A E a aiai iea ad aan ae 316 Usage EXamMPIGS een
339. in other modes 2 ENESAS Page 156 of 429 RX220 Group 4 Library Reference Description 4 9 RO1US0059EG0111 Aug 01 2014 buffer_operation Configure the buffer operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Rev 1 11 Control the cycle set buffer transfer timing Valid for n 4 PDL_MTU2_CSB_DISABLE or Select no transfer PDL_MTU2_CSB_CREST or transfer on crest detection PDL_MTU2_CSB_ TROUGH or transfer on trough detection or PDL_MTU2 CSB BOTH transfer on crest and trough detection PDL_MTU2_CSB_TROUGH and PDL_MTU2_CSB_BOTH are available only in complementary PWM mode Buffer operation PDL_MTU2_BUFFER_AC_DISABLE or PDL_MTU2_ BUFFER_AC_ ENABLE Disable or enable buffer operation for registers TGRA and TGRC Valid for n 0 3 and 4 PDL_MTU2_BUFFER_BD_DISABLE or PDL_MTU2 BUFFER BD ENABLE Disable or enable buffer operation for registers TGRB and TGRD Valid for n 0 3 and 4 PDL_MTU2_BUFFER_EF_DISABLE or PDL_MTU2 BUFFER EF ENABLE Disable or enable buffer operation for registers TGRE and TGRF Valid for n 0 Buffer data transfer PDL_MTU2_BUFFER_AC_CM_Aor PDL_MTU2_BUFFER_AC_TCNT_CLR Transfer the data from TGRC to TGRA when a compare match A occurs or when TCNT is cleared in each cha
340. ing or set the skip count between 1 and 7 Dead time generation control applies only to complementary PWM modes PDL_MTU2_DEAD_TIME_DISABLE or Disable or enable dead time PDL_MTU2 DEAD TIME ENABLE eneration e Waveform retention control applies only to complementary PWM modes PDL_MTU2_WAVEFORM_RETAIN_DISABLE or Disable or enable waveform output PDL_MTU2_WAVEFORM_RETAIN ENABLE retention e Compare match clearing control applies only to complementary PWM modes 1 PDL_MTU2_CNT_CLEAR_CM_A_DISABLE or Disable or enable counter clearing on PDL_MTU2_CNT_CLEAR_CM_A_ ENABLE TGRA compare match e Reset synchronised or complementary PWM control PDL_MTU2_PWM_RS_COMP_ENABLE Enable reset synchronised or complementary PWM mode e Register protection PDL_MTU2 ACCESS_DISABLE Control access to the registers and PDL MTU2 ACCESS_ENABLE counters in channels 3 and 4 register_selection The unit registers to be modified If multiple selections are required use to separate each selection e The registers to be modified These apply only to complementary PWM mode PDL_MTU2_ REGISTER _DEAD_ TIME Update the dead time data register TDDR PDL_MTU2_ REGISTER_CYCLE_ DATA Update the cycle data register TCDR PDL_MTU2 REGISTER_CYCLE_ BUFFER Update the cycle buffer register TCBR TDDR_value The dead time data register value This will be ignored i
341. ing the operation Reading the status Rev 1 11 2tENESAS Page 26 of 429 RX220 Group 2 Driver 2 10 Low Power Consumption Driver The driver functions support access to the registers which select the lower power modes of operation for the microcontroller These functions support 1 Configuring the state while in standby mode and the activity that can be used to resume operation 2 Selecting one of the low power modes 3 Determining the cause of the exit from the lowest power mode R01US0059EG0111 Rev 1 11 Page 27 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 11 Register Write Protection Driver The driver functions support the control of the Register Write Protection providing the following operations 1 Enabling or disabling writing to the registers 2 Reading the status of the write protection R01US0059EG0111 Rev 1 11 Page 28 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 12 Bus Controller Driver The driver functions support the control of the external bus providing the following operations 1 Setting the internal bus operation 2 Configuration of the controller 3 Controlling the bus controller 4 Reading the status of the controller RO1USO059EG0111 Rev 1 11 REN ESAS Page 29 of 429 Aug 01 2014 RX220 Group 2 Driver 2 13 DMA Controller Driver The driver functions support the control of the Direct Memory Access DMA controller providing the following
342. int16_t data2 Control options void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint16_t data6 Repeat or Block size int32_t data7 Address offset uint32_t data8 Source address extended repeat area uint32_t data9 Destination address extended repeat area Description 1 2 Change the state of a DMA controller channel data1 The channel number n where n 0 to 3 data2 Control the channel operation If multiple selections are required use to separate each selection e Enable suspend control PDL_DMAC_ENABLE Enable re enable DMA transfers PDL_DMAC_SUSPEND Suspend DMA transfers e Software trigger control PDL_DMAC_START or Start a DMA transfer PDL_DMAC_START_RUN or Start DMA transfers until stopped PDL_DMAC_STOP Stop software triggered transfers e Transfer end interrupt flag control PDL_DMAC_CLEAR_DTIF Clear the Transfer End flag PDL_DMAC_CLEAR_ESIF Clear the Transfer Escape End flag The values to be modified PDL_DMAC_UPDATE_SOURCE Source address using parameter data3 PDL_DMAC_UPDATE_DESTINATION ny tala address using parameter PDL_DMAC_UPDATE_COUNT Transfer count using parameter data5 PDL_DMAC_UPDATE_ SIZE Pia or Block size using parameter PDL_DMAC_UPDATE_OFFSET Address offset using parameter data7 Source address extended repeat area PDL_DMAC_UPD
343. int8_t data1 Channel selection uint8_t data2 Data storage address Read one data byte with NACK and stop data1 Select channel ICn where n 0 data2 The storage location for the data byte True if all parameters are valid and the function completed otherwise false 12C R_IIC_GetStatus e This function must only be used to terminate a Read process that has used the DMAC or DTC e Use R_IIC_GetStatus to determine if the transfer was successful e Please specify one byte less in the Transfer Count when using with the DMAC or DTC RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 1 byte on channel 0 and stop R_IIC_MasterReceiveLast 0 amp data_array 4 Rev 1 11 REN ESAS Page 273 of 429 RX220 Group 4 Library Reference 7 Synopsis Prototype Description R_IIC_SlaveMonitor Monitor the bus bool R_IIC_SlaveMonitor uint8_t data1 Channel selection uint16_t data2 Channel configuration uint8_t data3 Receive data start address uint16_t data4 Receive threshold void func Callback function uint8_t data5 Interrupt priority level Monitor the bus until an address match occurs and store any data received Register the storage area and transfer method for data received on the selected I C channel
344. intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the software interrupt handler R_INTC_CreateSoftwarelInterrupt PDL_NO_DATA CallBackFunc 7 R01US0059EG0111 Rev 1 11 Page 61 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 R_INTC_CreateFasiInterrupt Synopsis Prototype uint8_t data Description 1 2 data bool R_INTC_CreateFastinterrupt The interrupt to be selected Enable faster interrupt processing for one interrupt Choose the interrupt vector to be processed using the fast interrupt process Name Module Interrupt cause PDL_INTC_VECTOR_BUSERR External bus Error illegal access or timeout PDL_INTC_VECTOR FIFERR PDL_INTC_VECTOR_FRDYI Flash memory Error Ready PDL_INTC_VECTOR_SWINT Interrupt control Software interrupt PDL_INTC_VECTOR_CMTO PDL_INTC_VECTOR_CMT1 PDL_INTC_VECTOR_CMT2 PDL_INTC_VECTOR_CMT3 Compare match timer Compare match PDL_INTC_VECTOR FERRF Clock frequency Frequency error PDL_INTC_VECTOR_SPTIO PDL_INTC_VECTOR_MENDF accuracy Measurement end PDL_INTC_VECTOR_OVFF measurement Overflow PDL_INTC_VECTOR_SPEI0 Error PDL_INTC_VECTOR_SPRIO Receive buffer full
345. interrupt can be processed until a callback function has completed In Multi processor mode R_SCI_ Receive is to be called in a pair the first one is to receive ID ID cycle the second one is to receive data Data cycle For ID reception it could be done by reception interrupt by specifying func or by internal polling operation without specifying func1 For Data reception it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to section 5 18 6 For the ID cycle the DMAC DTC trigger control will be ignored In synchronous mode if both the Tx Data and the Rx Data pins have been enabled when R_SCI_Create was called then a reception must be performed in conjunction with a corresponding transmission This is achieved by calling R_SCI_ Receive in non polling mode and then R_SCI_ Send Please refer to the usage example in Section5 18 5 Do not use this function in SPI mode use R_SCI_SPI_ Transfer Do not use this function in IIC mode use R_SCI_IIC_ Read If using the DMAC or DTC this module does not know when the reception has ended Therefore when it has completed the user must call the R_SCI_ Control function with option PDL_SCI_STOP_RX to manually disable the reception If a callback function is specified and the interrupt priority level is zero this function will return false If PDL_SCI_RX_CONTINUOUS_ENABLE is selected when next group of data is received after callback f
346. ions R_SCI_Set 9 PDL_SCI_PIN_SCI9_RXD9_PB6 PDL_SCI_PIN_SCI9_TXD9_PB7 Configure the RS232 port specify Async MP mode R_SCI_Create 9 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 9600 15 i p ay es Async MP mode data Reception by CPU ISR 7 data_received false error_happen false Wait by CPU ISR until receive matching Station ID 0x0A R_SCI_Receive 9 O0x0A00 PDL_SCI_MP_ID_CYCL PDL_NO_PTR 0 SCIrx SCIEr fl R01US0059EG0111 Rev 1 11 Page 379 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples while data_received false data_received false Receive data ID 0x0A by CPU ISR R_SCI_Receive 9 PDL_NO_DATA receive_data 29 SCIrx SCIEr while data_received false wy Hes Async MP mode data Reception by polling pe a aes ey id_received false Wait by polling until receive matching Station ID 0x01 id_received R_SCI_Receive 9 0x0100 PDL_SCI_MP_ID_CYCL PDL_NO_PTR 0 PDL_NO_FUNC SCIEr if id_received true Receive data ID 0x01 by polling R_SCI_Receive 9 PDL_NO_DATA receive_data 21 PDL_NO_FUNC SCIEr void SCIrx void data_received true void SCIEr void error_happen true Figure 37 Example of SCI Reception code in Asynchronous Mul
347. iority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for func True if all parameters are valid and exclusive otherwise false DOC None In Addition Mode an interrupt is generated if the result of the addition exceeds FFFFh In Subtraction Mode an interrupt is generated if the result of the subtraction is less than zero In Comparison Mode an interrupt is generated when the comparison criteria Match or Mismatch is met e This function brings the DOC module out of the power down state e If a callback function is specified then interrupts will be automatically enabled e After calling a callback function the DOC flag is automatically cleared Rev 1 11 RENESAS Page 310 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void Callback void void func void Setup DOC in addition mode R_DOC_Create PDL_DOC_MODE_ADD 0 Callback 15 R01US0059EG0111 Rev 1 11 ztEN ESAS Page 311 of 429 Aug 01 2014 RX220 Group 4 Library Reference 2 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 R_DOC_Desiroy Disable the Dat
348. ision History 5 Aug 01 2014 RENESAS Renesas Peripheral Driver Library User s Manual RX220 Group Publication Date Rev 1 11 Aug 01 2014 Published by Renesas Electronics Corporation CENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http Awww renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 6503 0 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd Room 1709 Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100191 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886
349. k sub clock when sub clock is source clock D D 2 2 D 2 2 D L_CGC_SUB_32768 t for the Subclock stabilisation time 2 seconds minimum E As curently running from the Sub clock the R_CMT_CreateOneShot max time limit is gt 2 Secs R_CMT_CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 Select the HOCO as the clock source R_CGC_Control PDL_CGC_CLK_HOCO PDL_NO_DATA PDL_CGC_RTC_TO_B void Alarm_handler void uint8_t flags uint32_t time uint32_t date uint8_t buffer 50 Read time R_RTC_Read PDL_RTC_READ_CURRENT amp flags amp time sprintf char buffer Time int time amp 0xF00000 int time 0x0F0000 int time 0x00F000 int time 0x000F00 int time 0x0000F0 amp amp amp amp R01US0059EG0111 Rev 1 11 Page 361 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples int time amp 0x00000F gt gt 0 R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA buffer 0 PDL_NO_FUNC Configure the clock R_RTC_Control PDL_NO_DATA PDL RTC_UPDATE_ALARM_ TIME PDL_NO_DATA PDL_NO_DATA ime 0x10 Alarm in another 10 seconds L_NO_DATA L_ NO_DATA Error Adjust L NO_DATA Periodic P P P D D D Enter into sleep mode If true bEnterSleepMode bEnterSleepMode true
350. k between the end of one frame and the start of the next frame Ignored in Slave mode 2 ENESAS Page 282 of 429 RX220 Group Description 3 3 Return value Category Reference Remarks Program example 4 Library Reference data5 The format must be either The maximum required bit rate Or e b31 b30to b8 b7 b0 1 0 The SPBR register value If only Slave mode will be used specify PDL_NO_DATA True if all parameters are valid otherwise false SPI R_CGC_ Set R_SPI_ Set R_SPl_Command e Function R_CGC_Set must be called with the current clock source selected before using this function e Function R_SPI_Set must be called before any use of this function e The actual bit rate will be reduced if division gt 1 is specified in R_SPl_Command RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configure SPI channel 0 R_SPI_Create 0 PDL_SPI_MODE_SPI_MASTER PDL_SPI_PIN_SSLO_LOW PDL_SPI_FRAME_1_1 PDL_NO_DATA 2E6 R01US0059EG0111 Rev 1 11 Page 283 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 3 R_SPI_Destroy Synopsis Shutdown an SPI channel Prototype bool R_SPI_Destroy uint8_t data Channel selection Description Shutdown the selected
351. k Generation Circuit must be configured before configuring the ADC unit R01US0059EG0111 Rev 1 11 REN ESAS Page 43 of 429 Aug 01 2014 RX220 Group 2 Driver 2 27 Comparator A Driver Comparator A compares a reference input voltage and an analog input voltage The driver functions support the use of Comparator A1 and comparator A2 that share the voltage detection circuit with voltage monitor 1 and voltage monitor 2 Either comparator A1 and comparator A2 or voltage monitor 1 and voltage monitor 2 can be selected to use the voltage detection circuit Providing the following operations 1 Configuring two Comparator A including Individual Reference and Comparisoninput Select Comparison result monitor Comparison result output Interrupt or reset mode selection Reset Negation selection Non maskable or maskable interrupt Digital filter function and sample frequency Compares whether the analog input voltage has passed through the reference input voltage by rising or falling 2 Controlling two Comparator A e Enable disable comparator A 3 Reading the status flag R01US0059EG0111 Rev 1 11 Page 44 of 429 Aug 01 2014 RENESAS RX220 Group 2 28 Data Operation Circuit Driver The driver functions support the use of the DOC module providing the following operations RO1US0059EG0111 Aug 01 2014 1 2 Configuring and enabling the DOC Disabling the DOC 2 Driver Controlling operation in
352. l uint8_t data1 Channel selection uint8_t data2 Control options J Modify the operation of the selected 1 C channel data1 Select channel ICn where n 0 data2 Control the channel If multiple selections are required use to separate each selection Stop generation PDL_IIC_STOP Issue a Stop condition e NACK generation PDL_IIC_NACK Set the Acknowledge bit to the NACK state e Pin control PDL_IIC_SDA_LOW or set PDL_IIC_SDA HI Z Set the SDA pin to low level or high impedance PDL_IIC_SCL_LOW or l bind PDL IIC_SCL HI Z Set the SCL pin to low level or high impedance Extra clock cycle generation Generate an extra clock cycle on the SCL pin This can be used in PDL_IIC_CYCLE_SCL Master mode to try and unlock a slave device that is holding the SDA signal low e Reset control 5 7 PDL_IIC_RESET Carry out an internal reset of the 1 C module the settings are preserved True if all parameters are valid exclusive and achievable otherwise false 12C None None RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Issue a Stop condition on channel 0 R IIC Control 0 PDL_IIC_STOP R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 277 of 429 RX220 Group 4 Library Reference 10 R_IIC_GetStatus Synopsis Prototype
353. le the event e During software standby mode the voltage detection event triggers can be generated but they will not cause a trigger until software standby mode is exited e To enable the voltage detection event triggers enable the LVD first then enable the LVD event link function at the ELC To disable this function disable the LVD event link function at the ELC first then disable the LVD e For 64 pin package if port PCO and PC1 are selected in port switching register A input to ports PB6 and PB7 and the output port event function of the ELC cannot be used For 48 pin package if port PCO to PC3 are selected in port switching register B input to ports PBO PB1 PB3 and PB5 and the output port event function of the ELC cannot be used e Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the RSPI RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 149 of 429 RX220 Group 4 Library Reference Program example include r_pdl_elc h RPDL device specific definitions include r_pdl_definitions h void func void Create link between event TMR Channel 0 and module SinglePort 0 R_ELC_Control PDL_ELC_CREATE_LINK PDL_ELC_LINK_MODULE_SINGLE_PORT_0O PDL_ELC_LINK_EVENT_TMR_CHANNEL_0_COMPARE_MATCH_AO Configure SinglePort 0 as PB_0 Toggle output on
354. ll specify the timer frequency PDL_CMT_FREQUENCY or The counter clock source and compare match value will be calculated by this function Select the internal clock signal PCLKB 8 32 128 or 512 as the counter clock source The parameter data3 will be the register CMCOR value PDL_CMT_PCLK_DIV_8 or PDL_CMT_PCLK_DIV_32 or PDL_CMT_PCLK_DIV_128 or PDL_CMT_PCLK_DIV_512 e Counter start control PDL_CMT_START or PDL_CMT STOP Enable or disable the starting of the timer count operation e DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The data to be used for the register value calculations Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in register CMCOR uint16_t func The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CGC_Set R01US0059EG0111 Rev 1 11 REN ESAS Page 207 of 429 Aug 01 2014 RX220 Group 4 Library Refe
355. lled together b selecting one of each PDL_MTU2_OUT_P_PHASE_ALL_ENABLE or PDL MTU2 OUT_P_PHASE_ALL_DISABLE PDL_MTU2 OUT_N_PHASE_ALL_DISABLE All P phase outputs PDL_MTU2_OUT_N_PHASE_ALL_ENABLE or All N phase outputs Output inversion control applies only to reset synchronised or complementary PWM modes Each phase output can be configured for a initial high level active low level or b initial low level active high level If dead time is not generated the options for negative phases will be ignored as their outputs are always the inverse of the positive phases All six phase outputs can be controlled together by s electing one of each PDL_MTU2_OUT_P_PHASE_ALL_HIGH_LOW or PDL_MTU2_OUT_P_PHASE_ALL_LOW_HIGH PDL_MTU2 OUT_N_PHASE_ALL_LOW_HIGH Positive phase outputs PDL_MTU2_OUT_N_PHASE_ALL_HIGH_LOW or Negative phase outputs Or independently by selecting one option for each re quired output PDL_MTU2_OUT_P_PHASE_1_HIGH_LOW or MTIOC3B PDL_MTU2_ OUT_P_PHASE_1_LOW_HIGH PDL_MTU2_OUT_N_PHASE_1_HIGH_LOW or MTIOC3D PDL_MTU2 OUT_N_PHASE_1_LOW_HIGH PDL_MTU2_OUT_P_PHASE_2_ HIGH_LOW or MTIOC4A PDL_MTU2_ OUT_P_PHASE_2 LOW_HIGH PDL_MTU2_OUT_N_PHASE_2_HIGH_LOW or MTIOC4C PDL_MTU2 OUT_N_PHASE_2 LOW_HIGH PDL_MTU2_OUT_P_PHASE_3_HIGH_LOW or MTIOC4B PDL_MTU2_ O
356. lock frequency accuracy measurement circuit Choose the reference and measure clock settings Use to separate each selection e Reference signal selection PDL_CAC_REFERENCE_MAIN or PDL_CAC_REFERENCE_SUB_CLOCK or PDL_CAC_REFERENCE_HOCO or PDL_CAC_REFERENCE_LOCO or PDL_CAC_REFERENCE_IWDTLOCO or PDL_CAC_REFERENCE_CACREF Select the main clock oscillator sub clock oscillator high speed on chip oscillator low speed on chip oscillator or IWDT low speed on chip oscillator or input to pin CACREF as the reference signal PDL_CAC_REFERENCE_RISING or PDL_CAC_REFERENCE_FALLING or PDL_CAC_REFERENCE_BOTH Select rising edges falling edges or both rising and falling edges to be valid PDL_CAC_REFERENCE_DIV_32 or PDL_CAC_REFERENCE_DIV_128 or PDL_CAC_REFERENCE_DIV_1024 or PDL_CAC_REFERENCE_DIV_8192 Divide the reference signal by 32 128 1024 or 8192 Not required when the CACREF input is selected as the reference signal e Measured clock selection and division PDL_CAC_MEASURE_MAIN or PDL_CAC_MEASURE_SUB_CLOCK or PDL_CAC_MEASURE_HOCO or PDL_CAC_MEASURE_LOCO or PDL_CAC_MEASURE_IWDTLOCO Select the main clock oscillator sub clock oscillator high speed on chip oscillator low speed on chip oscillator or IWDT low speed on chip oscillator for measurement PDL_CAC_MEASURE_DIV_1 or PDL_CAC_MEASURE_DIV_4 or PDL_CAC_MEASURE_DIV_8 or PDL_CAC_MEASURE_DIV_32 Divide the clock to be measured by
357. lt or double trigger result is to be stored Refer to hardware manual Section 32 2 4 for the format of self diagnosis result True if a valid unit is selected otherwise false 12 bit ADC R_ADC_12_CreateUnit R_ADC_12_CreateChannel e From 1 to 16 valid conversion results will be read and stored to data2 The number depends on the parameters supplied to R ADC_12_CreateUnit and R_ADC_12_CreateChannel for configuration The data alignment is controlled using the R ADC_12_CreateUnit function e If the internal reference voltage is selected as the input source valid pointer should be supplied to data3 while data2 will be ignored e lf analog channels are selected as the input source valid array pointer should be supplied to data2 If double trigger or self diagnostic is enabled the respective result will be stored to data3 if a valid pointer is supplied e If no callback function is used this function waits for the IR flags to indicate that conversion is complete before reading the results If the ADC unit s control registers are directly modified by the user this function may lock up RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t ADCresult 16 uint1l6_t DIAGresult Read the ADC R_ADC_12_Read 0 ADCresult amp DIAGresult Rev 1 11 REN ESAS Page 305 of 429 RX220 Group 4 2 25 1 Comparator A
358. ltage detection 1 User wants to use both LVD1 and LVD2 user must configure both LVD1 and LVD2 simultaneously RPDL definitions include r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void Callback_LowVoltage void void func void Use Monitor 2 to generate an NMI when VCC drops below 4V R_LVD_Create PDL_NO_DATA PDL_NO_DATA PDL_LVD_INTERRUPT_NMI_DETECT_FALL PDL_LVD_FILTER_DISABLE PDL_LVD_VDET2_PIN_VCC PDL_LVD_VOLTAGE_LEVEL_400 4 00V PDL_NO_FUNC PDL_NO_DATA Callback_LowVoltage 15 od Rev 1 11 REN ESAS Page 99 of 429 RX220 Group 2 4 Library Reference R_LVD_Control Synopsis Control the voltage detection circuit Prototype bool R_LVD_Conirol uint8_t data1 Monitor 1 control uint8_t data2 Monitor 2 control 3 Description Control the voltage detection configuration data1 Monitor 1 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Disable monitor 1 operation e Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 1 change detection flag data2 Monitor 2 control All selections are optional If multiple
359. lternative modes on those pins SCI5 cannot be configured for IIC mode if the ELC event PDL_ELC_LINK_EVENT_SCI5_RECEIVE_DATA_FULL is being used This function will return false if this condition is detected In Async and Async MP modes the Tx pin is initially set to the Mark state The R_SCI_Control function can subsequently be used to set the Space state SPI Multi Master mode is not supported Hence in SPI Master mode the SS pin cannot be enabled If the option of using a delayed clock phase is selected in synchronous mode then a delay is required following the final receive interrupt before the operation can be completed This delay is implemented as a software loop in the SCI RXI interrupt routine See source file Interrupt_SCl c for details PDL_SCI_SPI_MODE cannot be selected for SCI Channel 12 The range of achievable bit rates bps is listed below Data clock ane fpcLke Moue source eat 32 MHz 12 5 MHz 12 MHz 8 MHz Internal Minimum 62 24 23 16 Asynchronous Niaximum 2 000 000 781 250 750 000 500 000 External 1 000 000 390 625 375 000 250 000 Internal Minimum 489 191 184 123 Synchronous icantly 4 000 000 1 562 500 1 500 000 1 000 000 External 5 333 333 2 083 333 2 000 000 1 333 333 Smart card Internal Mirimur 2 i 1 Maximum 500 000 195 312 187 500 125 000 Program example Aug 01 2014 RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_defi
360. lude r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void main void Initialise the system clocks NOTE The code to initialise the system clock is omitted here Please refer to 5 1 Clock Generation Circuit Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Configure TMR1 inpu output pins R_TMR_Set 1 PDL_TMR_TMR1_TMO1 PDL_TMR_TMR1_TMCI1_P12 PDL_TMR_TMR1_TMRI1_P24 Configure TMR1 inpu output pins R_TMR_Set 2 PDL_TMR_TMR2_TMO2 PDL_TMR_TMR2_TMCI2_PC6 PDL_TMR_TMR2_TMRI2_PC5 Configure TMR1 for 500ms pulse width 100ms on time R_TMR_CreatePeriodic PDL_TMR_TMRI1 PDL_TMR PERIOD PDL _TMR_OUTPUT_HIGH 500E 3 100E 3 PDL_NO_FUNC PDL_NO FUNC 0 Configure TMR2 for 1Hz frequency 50 duty cycle R_TMR_CreatePeriodic PDL _TMR_UNITI PDL _TMR_ FREQUENCY PDL_TMR_OUTPUT_HIGH EO PDL_NO_FUNC PDL_NO_FUNC Figure 19 Example of Pulse Output code R01US0059EG0111 Rev 1 11 Page 343 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples For full flexibility the R_TMR_CreateChannel function can be used In this example Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 200 ticks of PCLKB and a duty cycle of 50 Note that the output transitions and counter clea
361. ly turned on When one of the frequencies of the internal clocks ICLK PCLKD PCLKB and FCLk is set to 1 1 frequency division the PDL_LPC_SLEEP_RETURN_SWITCH_HOCO setting is prohibited R01US0059EG0111 Rev 1 11 Page 111 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Set main clock oscillator waiting time to 32 cycles R_LPC_Create PDL_NO_DATA PDL_LPC_MAIN_ 32 PDL_NO_DATA PDL_NO_DATA i R01US0059EG0111 Rev 1 11 Page 112 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_LPC Control Synopsis Select a low power consumption mode Prototype bool R_LPC_Control uint16_t data Mode selection Description Transition to one of the low power modes data Control selection All selections are optional The default settings are shown in bold If multiple selections are required use to separate each selection Mode selection PDL_LPC_MODE_SLEEP or PDL_LPC_MODE_ALL_MODULE_CLOCK_STOP or Select the mode to be entered PDL_LPC_MODE_SOFTWARE_STANDBY e Operating power control PDL_LPC_CHANGE_MIDDLE_SPEED_A or PDL_LPC_CHANGE_MIDDLE_SPEED_B or Select the operating power control PDL_LPC_CHANGE_LOW_SPEED_1 or mode PDL_LPC_CHANGE_LOW_SPEED 2 e Sleep mode return clo
362. m that the transfer was successful Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_spi h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h void spi_slave_callback void volatile bool slave_transfer_complete define SLAVE_CHANNEL 0 void main void const uint32_t master_tx_data 4 0x00000001 0x98765432 OxXABCDEF34 0x12345678 const uint32_t slave_tx_data 4 0x32323232 0x3456789A OxDEADBEEF OxFEEDCEDE uint32_t slave_rx_data 4 0x00000000 0x00000000 0x00000000 0x00000000 uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit Configure the slave SPI IO pin R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PA7 i Configure the slave SPI channel R_SPI_Create SLAVE_CHANNEL PDL_SPI_MODE_SYNC_SLAVE PDL_SPI_FRAME 1 4 PDL_NO_DATA PDL_NO_DATA Configure the slave R_SPI_Command SLAVE_CHANNEL 0 R01US0059EG0111 Rev 1 11 Page 409 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 1 SPI_CLOCK_MODE_1 PDL_SPI_LENGTH_32 PDL_SPI_LSB_FIRST L_NO_DATA Prepare the Slave for data transfer R_SPI_Transfer SLAVE_CHA
363. motor_control 0 control_unit_para general_control PDL_MTU2_PWM_RS_COMP_ENABL R01US0059EG0111 Rev 1 11 Page 341 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples control_unit_para register_selec control_unit_para output_control PDL_MTU2_0OU PHASE_3_ENABL 1 U2_OUT_N_PHAS PDL_MTU2_OUT PHASE_1_ENABLI 1 TU2_OUT_N_PHAS PDL_MTU2_0OU PHASE_2_ENABL 1 U2_OUT_N_PHAS PDL_MTU2_OU PHASE_ALL LOW_HIGH R_MTU2_ControlUnit 0 amp control_unit_para control_parameter control_setting PDL_MTU2_START control_parameter register_selection PDL_NO_DATA R_MTU2_ControlChanneli 3 amp control_parameter Figure 18 Example of MTU Reset Synchornized PWM mode R01US0059EG0111 Rev 1 11 Page 342 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 14 8 bit Timer 5 14 1 Periodic operation Timer channel 1 is configured to provide pulses on pin TMO1 with a pulse width of 500ms and an on time of 100ms Timer channel 2 is configured to provide pulses on pin TMO2 with a frequency of 1Hz and a duty cycle of 50 Notes When running this example with RSK the TMO1 and TMO 2 pins are configured to connect to LED 3 and LED 2 The LEDs will be lighted up when the pin output low level Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_cgc h inc
364. n internal reset will occur if false R_LPC_Control PDL_LPC_MODE_SLEEP while 1 It is correct to be here if have just woken from sleep mode while 1 Read time R_RTC_Read PDL_RTC_READ_CURRENT amp flags amp time amp date If no carry error output the time if 0 flags amp BIT_6 Has time changed if time amp OxFFFFFF time_previous amp OxFFFFFF time_previous time sprintf char buffer Time d d d d d d r n int time amp OxF00000 gt gt 20 int time 0x0F0000 gt gt 16 int time 0x00F000 gt gt 12 int time 0x000F00 gt gt 8 int time 0x0000F0 gt gt 4 int time 0x00000F gt gt 0 R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA buffer 0 PDL_NO_FUNC static void SetClocks void Prepare the LOCO settings R_CGC_Set PDL_CGC CLK_LOCO R01US0059EG0111 Rev 1 11 Page 360 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples PDL_NO_DA1 125E3 12553 PDL_NO_DA1 125E3 125E3 PDL_NO_DAT Configure the HOCO settings R_CGC_Set L_CGC_CLK_HOCO L_CGC_HOCO_50000 6 6 L_NO_DATA 6 6 D D 01 5 D 5 5 D U DNK YU U U L_NO_DAT Prepare the Sub clock settings R_CGC_Set PDL_CGC_CLK_SUB_CLOCK L_CGC_SUB_CLOCK_CL_STANDARD L_NO_DATA PCLKB cloc
365. n the following examples the bus activity will be illustrated using the following format ene e T T From the master A Acknowledge SDA held low Not Acknowledge SDA released high Erom ihe Save S Start condition P Stop condition Sr Repeated Start condition R Read SDA released high W Write SDA held low Figure 43 I C bus activity notation 5 19 1 Master mode In this example an EEPROM device has been connected to channel 0 The EEPROM responds to the 7 bit slave address 1010xxxb During a read process the bits xxx can be any value During a write process i The bits xxx represent the EEPROM memory address bits a10 a9 and a8 ii The first byte after the slave address is the EEPROM memory address bits a7 to a0 The EEPROM has a write cycle time of 5 ms The following examples illustrate the use of Master mode R01US0059EG0111 Rev 1 11 Page 391 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 1 Configuration and transmission The MCU s 12C channel 0 will be configured for Master operation and used to send 4 bytes to a slave seams r gt om Tom om Tr Figure 44 The bus activity showing 4 bytes being transmitted to the EEPROM Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h define EEPROM_ADDRESS 0xA0
366. nable the IWDT auto start mode Enable reset at VdetO Leave the HOCO disabled R_MCU_OFS PDL_ MCU_OFS_IWDT_AUTOSTAR PDL_MCU_OFS_IWDT_TIMEOUT_4096 PDL _MCU_OFS_IWDT_CLOCK_LOCO_16 PDL_MCU_OFS_IWDT_WIN_END_50 PDL_MCU_OFS_IWDT_WIN_START_75 PDL_MCU_OFS_IWDT_NMI PDL_ MCU_OFS_IWDT_STOP_DISABLE PDL_MCU_OFS_LVD_0_ENABLE PDL_ MCU_OFS_CGC_HOCO_DISABLE 3 R01US0059EG0111 Rev 1 11 RENESAS Page 96 of 429 Aug 01 2014 RX220 Group 4 2 6 1 Voltage Detection Circuit R_LVD_Create Synopsis Prototype Description 1 2 R01US0059EG0111 Aug 01 2014 Configure the voltage detection circuit bool R_LVD_Create 4 Library Reference uint16_t data1 Monitor 1 Configuration selection uint16_t data2 Monitor 1 Voltage selection uint16_t data3 Monitor 2 Configuration selection uint16_t data4 Monitor 2 Voltage selection void func1 Monitor 1 Callback function uint8_t data5 Monitor 1 Interrupt priority level void func2 Monitor 2 Callback function uint8_t data6 Monitor 2 Interrupt priority level Set the voltage detection configuration data1 Monitor 1 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection Operation PDL_LVD_MONITOR_ONLY or P
367. nc The function to be called if a match occurs True if the parameters are valid otherwise false I O port R_IO_PORT_Set e f an invalid port or pin is specified the operation of the function cannot be guaranteed e The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void IoHandlerl void IoHandler2 void func void Call function IoHandlerl if port pin P05 is high R_IO_PORT_Compare PDL_IO_PORT_0_5 1 ToHandlerl i Call function IoHandler2 if port 5 reads as 0x55 R_IO_PORT_Compare PDL_IO_PORT_5 0x55 ToHandler2 i Rev 1 11 REN ESAS Page 84 of 429 RX220 Group 4 Library Reference 7 RIO PORT Modify Synopsis Modify the pin states on an I O port Prototype bool R_IO_PORT_Modify uint16_tdata1 Output port or port pin selection uint16_t data2 Logical operation uint8_t data3 Modification value Description Read the output state of an I O port or I O port pin modify the result and write it back to the port data1 Use either one of the following definition values from 4 2 3 e One port definition or e One port pin definition data2 e The logical operation to be applied to the port or port pin PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or E
368. nce R_INTC_CreateExtInterrupt R_INTC_GetExtInterruptStatus Remarks e The NMI pin was enabled during R_INTC_CreateExtInterrupt and cannot be disabled an MCU design feature e When disabling an IRQn pin the Interrupt Request flag will be cleared automatically Acallback function may be called once more if a valid event occurs just before the interrupt pin is disabled R01US0059EG0111 Rev 1 11 Page 66 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the IRQ1 interrupt pin and clear the flag R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 PDL_INTC_DISABLE PDL_INTC_CLEAR_IR_FLAG R01US0059EG0111 Rev 1 11 Page 67 of 429 Aug 01 2014 RENESAS RX220 Group 7 R_INTC_GetExtinterruptStatus Synopsis Read the external interrupt status Prototype bool R_INTC_GetExtInterruptStatus uint8_t data1 Pin selection uint8_t data2 Description Acquire the status for the specified external interrupt data1 Choose the interrupt pin to be checked 4 Library Reference A pointer to the buffer where the status data shall be stored PDL_INTC_IRQn n 0 to 7 or IRQn n 0 to 7 interrupt pin or
369. nction before using any other ELC function e fusing ELC Interrupts use this function to register the callback functions and R_ELC_ Control to create a link include r_pdl_elc h RPDL device specific definitions include r_pdl_definitions h void Interruptl1_CallBack void void func void Enable the module and setup an Interruptl callback R_ELC_Create Interruptl_CallBack 5 Rev 1 11 REN ESAS Page 141 of 429 RX220 Group 4 Library Reference 2 Synopsis Prototype Description Return value Category Reference R_ELC_ Destroy Disable the ELC module bool R_ELC_Desiroy void No parameter is required 3 Disable all links and enable the ELC module stop state True Event Link Controller R_ELC_ Create Remarks Program example RO1US0059EG0111 Aug 01 2014 None include r_pdl_elc h RPDL device specific definitions include r_pdl_definitions h void func void R_ELC_Destroy Page 142 of 429 RX220 Group 3 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference R_ELC Read Read the ELC port buffer bool R_ELC_Read uint8_t data1 Port uint8_t data2 Storage Read the ELC
370. nel SCIn where n 1 5 6 9 or 12 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Operation mode PDL_SCI_ASYNC or Choose between Asynchronous PDL_SCI_SYNC or Clock synchronous includes SPI and IIC PDL_SCI_SMART or Smart Card Interface or PDL_SCI_ASYNC_MP Multi Processor Asynchronous operation e Transmit Receive connections Not applicable in IIC Mode option will be ignored PDL_SCI_TX_CONNECTED or PDL_SCI_TX DISCONNECTED The TXDn output is required not required PDL_SCI_RX_CONNECTED or PDL_SCI_RX_DISCONNECTED The RXDn input is required not required e Data transfer format Not applicable in IIC Mode option will be ignored PDL_SCI_LSB_ FIRST or er tog PDL SCI MSB FIRST Select least or most significant bit first Options which are available in Asynchronous mode or Multi Processor Asynchronous mode e Noise Filter PDL_SCI_RX_FILTER_DISABLE or Enable or disable the Digital Noise Filter on the PDL_SCI_RX_FILTER_ENABLE RXDn pin e Hardware Flow Control PDL_SCI_HW_FLOW_NONE or Select the Hardware Flow Control Option PDL_SCI_HW_FLOW_CTS or Note CTS and RTS functions cannot both be used PDL_SCI_HW_FLOW_RTS as they share the same pin Data clock source selection PDL_SCI_CLK_INT lO or Select the on chip SCKn pin available as an I O pin PDL_SCI_CLK_
371. nfigure HOCO operation ICLK 32 MHz PCLKD 32 MHz PCLKB 32 MHz FCLK 32 MHz PDL_CGC_CLK_HOCO PDL_CGC_HOCO_32000 32E6 32E6 32E6 32E6 32E6 PDL_NO_DATA Rev 1 11 REN ESAS Page 53 of 429 RX220 Group 2 Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 4 Library Reference R_CGC_Control Modify the clock generation circuit operation bool R_CGC_Conirol uint8_t data1 Clock selection uint32_t data2 Clock control options uint8_t data3 Clock control options Modify the clock control registers data1 Clock source selection If no change is required specify PDL_NO_DATA e Clock source selection PDL_CGC_CLK_LOCO or Select the low speed on chip oscillator LOCO PDL_CGC_CLK_HOCO or high speed on chip oscillator HOCO PDL_CGC_CLK_MAIN or main clock oscillator or PDL_CGC_CLK_SUB_CLOCK sub clock oscillator data2 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection e Low speed on chip oscillator control PDL_CGC_LOCO_ENABLE or PDL_CGC_LOCO DISABLE Enable or disable the LOCO e High speed on chip oscillator control PDL_CGC_HOCO_ENABLE or PDL_CGC_HOCO DISABLE Enable or disable the HOCO e High speed on chip oscillator power control PDL_CGC_H
372. ng e Access to all control bits e Automatic interrupt control e Automatic I O pin configuration 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer channel 5 Control of a timer unit 6 Reading the status flags and registers of a timer channel 7 Reading the status flags and registers of a timer unit Note The Clock Generation Circuit must be configured before configuring any timer channel RO1USO059EG0111_ Rev 1 11 REN ESAS Page 33 of 429 Aug 01 2014 RX220 Group 2 Driver 2 17 Port Output Enable Driver The driver functions support the use of the Port Output module providing the following operations 1 Configuring the pins for use 2 Configuring the interrupts and callback functions 3 Run time control of outputs interrupts and flags 4 Checking the module status RO1USO059EG0111 Rev 1 11 REN ESAS Page 34 of 429 Aug 01 2014 RX220 Group 2 Driver 2 18 8 bit Timer Driver The driver functions support the use of the four 8 bit timers providing the following operations As 2 9 Selection of the TMR pins for use Configuring a channel for use using register values which have been determined elsewhere Configuring two channels as a 16 bit pair using register values which have been determined elsewhere Configuration for as a periodic timer including e Automatic clock setting using frequency or period as an input e Automatic pulse width setting
373. nitions IR register definitions PDL_INTC_REG_IR_BSC_BUSERR PDL_INTC_REG_IR_MTU4_TGIA PDL_INTC_REG_IR_FCU_FIFERR PDL_INTC_REG_IR_MTU4_ TGIB PDL_INTC_REG_IR_FCU_FRDY I PDL_INTC_REG_IR_MTU4_TGIC PDL_INTC_REG_IR_ICU_SWINT PDL_INTC_REG_IR_MTU4_TGID PDL_INTC_REG_IR_CMT0O_CMI PDL_INTC_REG_IR_MTU4_TCIV PDL_INTC_REG_IR_CMT1_CMI PDL_INTC_REG_IR_MTU5_TGIU PDL_INTC_REG_IR_CMT2_CMI PDL_INTC_REG_IR_MTU5_TGIV PDL_INTC_REG_IR_CMT3_CMI PDL_INTC_REG_IR_MTU5_TGIW PDL_INTC_REG_IR_CAC_FERRF PDL_INTC_REG_IR_POE_OEI1 PDL_INTC_REG_IR_CAC_MENDF PDL_INTC_REG_IR_POE_OEl2 PDL_INTC_REG_IR_CAC_OVFF PDL_INTC_REG_IR_TMRO_CMIA PDL_INTC_REG_IR_SPIO_SPEI PDL_INTC_REG_IR_TMRO_CMIB PDL_INTC_REG_IR_SPIO_SPRI PDL_INTC_REG_IR_TMRO_OVI PDL_INTC_REG_IR_SPIO_SPTI PDL_INTC_REG_IR_TMR1_CMIA PDL_INTC_REG_IR_SPIO_SPIl PDL_INTC_REG_IR_TMR1_CMIB PDL_INTC_REG
374. nitions h void func void Configure SCI1 for asynchronous 38400 baud R_SCI_Create 1 PDL_SCI_ASYNC 38400 1 8N1 PDL_SCI_8N1 Configure SCI1 for asynchronous 8N1 register values supplied R_SCI_Create l PDL_SCI_ASYNC PDL_SCI_8N1 BIT_31 PDL_SCI_PCLK_DIV_1 PDL_SCI_CYCLE_BIT_16 115200 amp Ox00FFFF00 0x50 1 R01US0059EG0111 Rev 1 11 RENESAS Page 243 of 429 RX220 Group 4 Library Reference 3 R_SCI_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down a SCI channel bool R_SCI_Destroy uint8_t data Channel selection Stop data flow and shutdown the selected SCI channel data Select channel SCIn where n 1 5 6 9 or 12 True if all parameters are valid otherwise false SCI None e The SCI channel is put into the power down state RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SCI channel 1 R_SCI_Destroy 1 R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 244 of 429 RX220 Group 4 Synopsis Prototype Description Return value 4 Library Reference R_SCI Send Transmit data on a SCI channel
375. nnel Valid for n 0 3 and 4 PDL_MTU2_BUFFER_BD_CM Bor PDL_MTU2_BUFFER_BD_TCNT_CLR Transfer the data from TGRD to TGRB when a compare match B occurs or when TCNT is cleared in each channel Valid for n 0 3 and 4 PDL_MTU2_BUFFER_EF_CM_E or PDL_MTU2_BUFFER_EF_TCNT_CLR Transfer the data from TGRF to TGRE when a compare match E occurs or when TCNT is cleared in either channel Valid for n 0 Transfer on TCNT clear is available only in PWM mode 1 or 2 2tENESAS Page 157 of 429 RX220 Group Description 5 9 TGR_A_B_ operation RO1US0059EG0111 Aug 01 2014 4 Library Reference Configure the operation for general registers TGRA and TGRB Valid for n 0 to 4 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Input capture output compare control for register TGRA PDL_MTU2_A_OC_ DISABLED or PDL_MTU2_A_OC_LOW or PDL_MTU2_A_OC_LOW_CM HIGH or PDL_MTU2_A_OC_LOW_CM_INV or PDL_MTU2_A_OC_HIGH_CM_LOW or PDL_MTU2_A_OC_ HIGH or PDL_MTU2_A_OC_HIGH CM_INV or MTIOCnA output disabled MTIOCnA output low MTIOCnA initial output low goes high at compare match MTIOCnA initial output low toggles at compare match MTIOCnA initial output high goes low at compare match MTIOCnA output high MTIOCnA initial output high toggles at compare match
376. noise filter for MTIOCnA n 0 to 4 or TIOC5U n 5 PDL_MTU2_NF_B_V_DISABLE or PDL_MTU2_NF_B_V_ENABLE Enable or disable noise filter for MTIOCnB n 0 to PDL_MTU2_NF_C W DISABLE or PDL_MTU2 NF_C W ENABLE PDL_MTU2_NF_D_DISABLE or PDL_MTU2 NF_D ENABLE 4 or TIOC5V n 5 Enable or disable noise filter for MTIOCnC n 0 3 or 4 or TIOC5W n 5 Not valid for n 1 or 2 Enable or disable noise filter for MTIOCnD n 0 3 or 4 Not valid for n 1 2 or 5 e Noise filter clock select for register NFCRn PDL_MTU2_NF_PCLK_DIV_1 or PDL_MTU2_NF_PCLK_DIV_8 or PDL_MTU2_NF_PCLK_DIV_32 or PDL_MTU2 NF PCLK DIV_SRC Set the clock of the noise filter as PCLKB 1 8 32 or the count source TCNT_TCNTU_ value For n 0 to 4 The timer counter TCNT value For n 5 The timer counter TCNTU value TGRA_TCNTV_value For n 0 to 4 The register TGRA value For n 5 The timer counter TCNTV value TGRB_TCNTW_value For n 0 to 4 The register TGRB value For n 5 The timer counter TCNTW value TGRC_TGRU_ value For n 0 3 or 4 The register TGRC value For n 5 The register TGRU value If the corresponding channel is stopped make sure the value is not TCNTU 1 Ignored for n 1 or 2 TGRD_TGRV_value For n 0 3 or 4 The register TGRD value For n 5 The register TGRV value If the corresponding channel is stopped make sure the value is not T
377. ns const char source_string_1 Renesas RX220 const char source_string_2 Hello World volatile uint8_t destination_string_1 volatile uint8_t destination_string_2 void main void uint8_t StatusValue uint32_t SourceAddr uint32_t DestAddr uintl6_t TransferCount uintl6_t SizeCount Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Enable control of LEDI R_IO_PORT_Set PDL_IO PORT 1_5 PDL_IO PORT OUTPUT Switch on LED1 R_IO_PORT_Write PDL_IO_PORT_1_5 0 Configure channel 0 R_DMAC_Create 0 PDL_DMAC_BLOCK PDL_DMAC_SOURC ESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PL PDL_DMAC_SIZE_8 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_IRQ1 source_string_l destination_string_l 1 uintl6_t strlen source_string_1l PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 330 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples DMACO_transfer_end_handler 7 Configure channel 1 R_DMAC_Create 1 PDL_DMAC_BLOCK PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_STIZ I PDL_DMAC_TRIGGER_SW source_string_2 destination_string_2 1 uintl6_t strlen source_string_2 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 Set IRQ pin to P31 R_INTC_SetExtInterrupt PDL_INTC_IRQ1_P31
378. ns To set multiple options at the same time use to separate each value e Polynomial selection PDL_CRC_POLY_CRC_8or X X X 1 PDL_CRC_POLY_CRC_16 or xe x4 XP 4 4 PDL_CRC_POLY_CRC_CCITT xe x24 x4 4 e Bit order Senate Select LSB or MSB first operation True if all parameters are valid and exclusive otherwise false CRC None None RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Set up the CRC in 8 bit mode with LSB first R_CRC_Create PDL_CRC_POLY_CRC_8 PDL_CRC_LSB_FIRST R01US0059EG0111 Rev 1 11 REN ESAS Page 292 of 429 Aug 01 2014 RX220 Group 4 Library Reference 2 R_CRC_Destroy Synopsis Shut down the CRC calculator Prototype bool R_CRC_Destroy void No parameter is required Description Put the CRC calculator into the Power down state with minimal power consumption Return value True Category CRC Reference R_CRC_Create Remarks e None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the CRC R_CRC_Dest roy R01US0059EG0111 Rev 1 11 Page 293 of 429 Aug 01 2014 RENESAS RX220 Group 3 R_CRC_Write Synopsis Prototype
379. ns the data to be written Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to send the data Rev 1 11 REN ESAS Page 254 of 429 RX220 Group Description 2 2 4 Library Reference func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer Parameter method PDL_NO_FUNC This function will continue until the required number of bytes Pollin ering has been transferred or an error occurs Interrupts The function to be called when the transfer has completed or an error detected Either the function to be called when each byte is transferred or PDL_NO_FUNC Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 DMAC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_DMAC_Create R_DTC_Create R_SCl_Control The maximum number of characters to be transmitted is 65535 e Wait until a transmission on the same channel is complete befor
380. nt8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The unit number n where n 0 or 1 data2 The status flags shall be stored in the format below A flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read The unit 0 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMRO TMR1 0 Compare Compare 0 Compare Compare Overflow match B match A Overilow match B match A The unit 1 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 bi bO TMR2 TMR3 0 Compare Compare 0 Compare Compare eon match B match A Overlow match B match A data3 Where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required Return value True Category Timer TMR Reference R_TMR_CreateUnit Remarks e Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 by this function RO1USOO59EG0111 Rev 1 11 REN ESA
381. o separate each selection e Enable or disable the interrupt pin for the IRQ pins PDL_INTC_ENABLE or PDL_INTC_DISABLE Enable or disable the IRQn interrupt pin Digital filter selection PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC_FILTER_DIV_64 e Detection sense selection for the IRQ pins Disable the filter or select PCLKB divided by 1 8 32 or 64 PDL_INTC_LOW or Select Low level PDL_INTC_FALLING or Falling edge PDL_INTC_RISING or Rising edge or PDL_INTC_BOTH Falling and rising edge detection e Interrupt request clearing Clear the IRQ or NMI interrupt request flag This is not required if e Acallback function has been specified e The interrupt priority level is higher than 0 PDL_INTC_CLEAR_IR_FLAG e The processor interrupt priority level is lower than the interrupt priority level This operation should not be applied when low level detection is used PDL_INTC_CLEAR_OSD_FLAG Clear the Oscillation Stop detection NMI flag PDL_INTC_CLEAR_IWDT_FLAG Clear the IWDT event detection NMI flag PDL_INTC_CLEAR_LVD1_FLAG Clear the LVD1 event detection NMI flag PDL_INTC_CLEAR_LVD2_FLAG Clear the LVD2 event detection NMI flag Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control Refere
382. ode PDL_MTU2_CLK_RISING or PDL_MTU2_CLK_FALLING or PDL_MTU2 CLK BOTH The TCNT counter clock signal shall be counted on rising falling or both edges PDL_MTU2 CLEAR TGRA or TCNT counter clearing Valid for n 0 to 4 unless stated otherwise PDL_MTU2 CLEAR DISABLE or Clearing is disabled Cleared by TGRA compare match or input capture PDL_MTU2 CLEAR TGRB or Cleared by TGRB compare match or input capture PDL_MTU2_CLEAR_SYNC or Cleared by counter clearing on another channel configured for synchronous operation PDL_MTU2_CLEAR_TGRC or Cleared by TGRC compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_CLEAR TGRD Cleared by TGRD compare match or input capture Valid for n 0 3 and 4 RO1US0059EG0111 Aug 01 2014 Rev 1 11 2 ENESAS Page 155 of 429 RX220 Group 4 Library Reference Description 3 9 Counter clock source selection Valid for n 5 RO1US0059EG0111 Aug 01 2014 PDL_MTU2_CLKU_PCLK_DIV_1 or PDL_MTU2_CLKU_PCLK_DIV_4 or PDL_MTU2_CLKU_PCLK_DIV_16 or PDL_MTU2 CLKU_PCLK_DIV_64 Counter TCNTU is supplied by the internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLKV_PCLK_DIV_1 or PDL_MTU2_CLKV_PCLK_DIV_4 or PDL_MTU2_CLKV_PCLK_DIV_16 or PDL_MTU2_CLKV_PCLK_DIV_64 Counter TCNTV is supplied by the internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLKW_PCLK_DIV_1 o
383. of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 4 Synopsis Prototype Description Return value Category Reference Remarks Program example R_POE_GetStatus Check the status of the Port Output Enable module bool R_POE_GetStatus uint16_t data Status flags pointer Return the status flags data The status flags shall be stored in the following format b15 b14 b13 b10 b9 b8 Output short detection High impedance request detection more 0 MTU3 or MTU4 0 OSTSTF POE8 0 Not detected 0 No request 1 Detected 1 Requested b7 b6 b5 b4 b3 b2 b1 bO High impedance request detection on pin POEn POE3 POE2 POE1 POEO 0 0 No request 1 Requested True Port Output Enable R_POE_Control e Use R_POE_Control to clear the flags RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void uint1l6_t StatusFlags Read the POE status R_POE_GetStatus amp StatusFlags R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 183 of 429 RX220 Group 4 Library Reference 4 2 16 8 bit Timer 1 R_TMR Set Synopsis Configure the optional TMR pins Prototype bool R_TMR_Set uint8_t data1 Channel selection uint32_t data2 Configuration
384. of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat
385. oid func void uint8_t PRCR_value uint8_t PWPR_value Read the protection registers R_RWP_Get Status amp PRCR_value amp PWPR_value R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 117 of 429 RX220 Group 4 Library Reference 4 2 10 Bus Controller 1 R_BSC_Set Synopsis Configure the internal bus operation Prototype bool R_BSC_Set uint16_tdata Bus priority selection Description Configure the priority of the internal and external buses data e Bus priority control If multiple selections are required use to separate each selection The default settings are shown in bold Bus to be accessed Priority E a ead or RAM Fixed to internal main bus PDL_BSC_PRIORITY ROM MB2or poy ingesting CFU PDL_BSC_PRIORITY_ROM_CPU i PDL_BSC_PRIORITY_PB1_MB2 or Peripheral 1 PDL_BSC_PRIORITY_PB1_MB1 enpnera l l l PDL_BSC_PRIORITY_PB2_MB2 or F xed tp interna main Dus PDL_BSC_PRIORITY_PB2 _MB1 Fenpnerala 2 or toggled with internal PDL_BSC_PRIORITY_PB6_MB2 or manibus ts PDL_BSC_PRIORITY_PB6_MB1 Peripheral 6 Return value True if all parameters are valid and exclusive otherwise false Category Bus Controller Reference None Remarks e If it is necessary to call this function call it once only Ensure that both the DTC and DMAC are stopped Program example RPDL definitions include r_
386. on Detection configuration Slave address Slave address Slave address Transfer rate control Rise and fall time correction Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold e Bus mode selection PDL_IIC_MODE_IIC or PDL_IIC_MODE_SMBUS Choose between C Bus or SMBus mode Internal reference clock PDL_lIC_INT_PCLK_DIV_1 or PDL_IIC_INT_PCLK_DIV_2 or PDL_IIC_INT_PCLK_DIV_4 or PDL_lIC_INT_PCLK_DIV_8 or PDL_lIC_INT_PCLK_DIV_16 or PDL_lIC_INT_PCLK_DIV_32 or PDL_lIC_INT_PCLK_DIV_64 or PDL_lIC_INT_PCLK_DIV_128 The reference clock source derived from PCLKB used inside the l C module e Timeout detection control PDL_IIC_TIMEOUT_DISABLE or PDL_IIC_TIMEOUT_LOW or PDL_IIC_TIMEOUT_HIGH or PDL_lIC_TIMEOUT BOTH Disable timeout detection or enable for SCL stuck at a low level high level or both low and high level Timeout mode PDL_lIC_TIMEOUT_LONG or PDL_IIC_TIMEOUT_SHORT Select 16 bit long or 14 bit short mode e SDA output delay count PDL_IIC_SDA_DELAY_0or PDL_lIC_SDA_DELAY_1 or PDL_lIC_SDA_DELAY_2 or PDL_lIC_SDA_DELAY_3 or PDL_lIC_SDA_DELAY_4 or PDL_lIC_SDA_DELAY_5 or PDL_lIC_SDA_DELAY_6 or PDL_lIC_SDA DELAY 7 Select the number of cycles for the SDA output delay counter e SDA output delay clock source
387. on 11 Reading the status flags Note The Clock Generation Circuit must be configured before configuring any serial channel R01US0059EG0111 Rev 1 11 Page 39 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 23 lC Bus Interface Driver The driver functions support the use of the 12C module providing the following operations 1 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic interrupt control 2 Disabling the module that is no longer required and enabling low power mode 3 Transmitting data in Master mode 4 Receiving data in Master mode 5 Completing the reception of data in Master mode 6 Monitoring the bus and handling the reception of data in Slave mode 7 Transmitting data in Slave mode 8 Control of the unit including bus lock up recovery support 9 Reading the status of the module Note The Clock Generation Circuit must be configured before configuring the 12C module R01US0059EG0111 Rev 1 11 REN ESAS Page 40 of 429 Aug 01 2014 RX220 Group 2 Driver 2 24 Serial Peripheral Interface Driver The driver functions support the use of the SPI channels providing the following operations 1 Selection of the SPI pins for use 2 Configuration for use including e Automatic clock setting using transfer rate as an input 3 Disabling channels that are no longer required and enabling low power mode 4 Configuration of command sequence settings 5 Man
388. on selection uint8_t data3 Output control uint8_t data4 Counter register value uint8_t data5 Compare match A register value uint8_t data6 Compare match B register value void func Overflow callback function void func2 Compare match A callback function void func3 Compare match B callback function uint8_t data7 Interrupt priority level Description 1 2 Set up an 8 bit timer TMR channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Counter clock source selection PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK_EXT_BOTH or PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 or PDL_TMR_CLK_TMR1_OVERFLOW or The overflow signal from TMR n 1 PDL_TMR_CLK_TMR3_ OVERFLOW or Valid for n 0 or 2 The external clock signal TMCIn is used Select rising falling or both edges detected The internal clock signal PCLKB 1 2 8 32 64 1024 or 8192 PDL_TMR_CLK_TMRO_CM_Aor The compare match A signal from T
389. ontrol Drive capacity control PDL IO PORT_DRIVE Valid for ports 1 B and C data3 The address where the register value shall be stored using one of the formats below Pin not PE1 open drain control b15 b1 bO 0 Oor1 Pin PE1 open drain control b15 b2 b1 b0 0 0 to 3 Port not open drain control b15 b8 b7 b0 0 Register Port open drain control b15 b8 b7 b0 Register ODR1 Register ODRO True if all parameters are valid and exclusive otherwise false I O port None Ensure that the specified register is valid for the selected port or port pin RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 78 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t result Read the direction register for port C R_IO_PORT_ReadControl PDL_IO_PORT_C PDL_IO_PORT_DIRECTION amp result Read the output type for pin P13 R_IO_PORT_ReadControli PDL_IO_PORT_1_3 PDL_IO_PORT_TYPE amp result R01US0059EG0111 Rev 1 11 Page 79 of 429 Aug 01 2014 RENESAS RX220 Group 3 Synopsis Prototype Description Return value 4 Librar
390. or A Figure 58 shows an example of Comparator A usage Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_cpa h include r_pdl_intc h include r_pdl_io_port h PDL device specific definitions include r_pdl_definitions h void NMI_handler_cpa void void CPAO_ handler void void CPA1_handler void uint8_t FlagsNonMASKABLE false void main void uint8_t FlagsStatus Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit R_IO_PORT_Set PDL_IO_PORT_1 PDL_IO_POR R_IO_PORT_Set PDL_IO_PORT_1 PDL_IO_POR R_IO_PORT_Set PDL_IO_PORT_1_6 PDL_IO_POR R_IO_ PORT Write PDL_IO_PORT_1 4 1 R_IO_PORT_ Write PDL_IO_PORT_1_5 on R_IO_PORT_Write PDL_IO_PORT_1_6 0 on Monitoring Comparison A channel 0 results R_CPA_Create 0 PDL_NO_DATA PDL_NO_FUNC 0 Get status LVDiDET LVDiMON do R_CPA_GetStatus amp FlagsStatus if FlagsStatus amp 0x01 0x01 break while 1 Comparator A channel 1 interrupts using Digital Filter Enable the LOCO clock R_CGC_ControlAll PDL_CGC_CLK_LOCO PDL_CGC_LOCO_ENABLE PDL_NO_DATA Configure the NMI pin Non Maskable Interrupt for Comparator A channel 1 R_INTC_CreateExtInterrupt P
391. or waiting time uint32_t data4 HOCO oscillator waiting time data1 Select the required settings If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Operating power control Load the registers that control module or CPU operation PDL_LPC_MIDDLE_SPEED_MODE_A or PDL_LPC_MIDDLE_SPEED_MODE_B or PDL_LPC_LOW_SPEED_MODE_1 or PDL_LPC_LOW_SPEED_MODE 2 Select the operating power control mode Sleep mode return clock source switching PDL_LPC_SLEEP_RETURN_SWITCH_DISABLE or PDL_LPC_SLEEP_RETURN_SWITCH_HOCO or PDL_LPC_SLEEP_RETURN SWITCH MAIN Control clock source switching at cancellation of sleep mode Flash HOCO software standby control PDL_LPC_SOFTCUT_POR or Power is supplied to HOCO in software standby mode The voltage detection circuit LVD is active and the low power consumption function by the power on reset circuit POR is disabled PDL_LPC_SOFTCUT_HOCO_POR or Power is not supplied to HOCO in software standby mode The voltage detection circuit LVD is active and the low power consumption function by the power on reset circuit POR is disabled PDL_LPC_SOFTCUT_LVD or Power is supplied to HOCO in software standby mode The voltage detection circuit LVD is stopped and the power consumption reduction function by the power on reset circuit POR is enabled
392. ortpinP4s PDLIO PORT C 5 PortpinPCs PDL_IO PORT 14 PortpinP1 PDL IO PORT 4 6 PortpinP4 PDL_IO PORT C 6 Portpin PC PDL_IO PORT 1 5 PortpinP1s PDL IO PORT 4 7 PortpinP47 PDL IO PORT C7 PortpinPC7 PDL IO PORT 1 6 Portpin Pte PDLIO PORT 17 PortpinPi7 PDLIO PORT 50 PortpinP5 PDL IO PORT_D_0 Portpin PDo PDL_IO PORT 5 1 Portpin P5 PDL_IO PORT D 1 Portpin PD PDLIO_ PORT 2 0 PortpinP2 PDLIO_PORT_5_2 Portpin P52 PDL_IO PORT D 2 PortpinPD gt PDL IO PORT 2 1 PortpinP2 PDL IO PORT 53 PortpinP5 PDL_IO PORT D 3 Portpin PD PDL IO PORT 2 2 PortpinP2 PDL IO PORT 5 4 PortpinP5 PDL_IO PORT D 4 Portpin PD PDL IO PORT 2 3 PortpinP2 PDL IO PORT 55 PortpinP5 PDL_IO PORT D 5 Portpin PD PDL IO PORT 2 4 Portpin P24 PDL_IO PORT_D 6 Portpin PDs PDL_IO PORT 2 5 PortpinP2s PDL_IO PORT AO PortpinPAo PDL_IO PORT D7 PortpinPD7 PDL IO PORT 2 6 PortpinP2 PDL IO PORT A 1 Portpin PA PDL IO PORT 2 7 PortpinP27 PDL IO PORT A 2 PortpinPA2 PDL_IO PORT E 0 Portpin PEo PDL_IO PORTA 3 Portpin PAs PDL_IO PORT E 1 Portpin PE PDL IO PORT 3 0 PortpinP3 PDL_IO PORTA 4 Portpin PA PDL_IO PORT E 2 Portpin PE PDL_IO PORT 3 1 PortpinP3 PDLIO PORT A 5 PortpinPAs PDL_IO PORT E 3 Portpin PEs PDL IO PORT 3 2 PortpinP32 PDL_IO PORT A 6 Portpin PAs PDL_IO PORT E 4 Portpin PE PDL IO PORT 3 3 PortpinP3 PDL IO PORT A 7 PortpinPA PDL_IO PORT E
393. ot supported by the driver library these functions support 1 Reading from an MPC register 2 Writing to an MPC register 3 Modifying an MPC register R01US0059EG0111 Rev 1 11 Page 23 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 7 MCU Operation Driver The driver functions support access to the registers which select the mode of operation for the microcontroller These functions support 1 Controlling the MCU features and on chip ROM 2 Reading the MCU status flags 3 Setting the MCU start up options R01US0059EG0111 Rev 1 11 Page 24 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 8 Voltage Detection Circuit Driver The driver function supports configuration of VDET1 and VDET2 voltage detection circuits This function supports 1 Configuration of the voltage detection circuit including e Setting voltage thresholds e Defining a voltage event e Configuring a reset when supply voltage drops below a voltage threshold 2 Controlling the circuit operation 3 Reading the circuit status R01US0059EG0111 Rev 1 11 Page 25 of 429 Aug 01 2014 RENESAS RX220 Group 2 9 Clock Frequency Accuracy Measurement Circuit Driver 2 Driver The driver functions support access to the registers which control the Clock Frequency Accuracy Measurement Circuit These functions support R01US0059EG0111 Aug 01 2014 1 2 Configuring the operation Stopping the operation Modify
394. oup 4 Library Reference Program example RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint32_t Count uint32_t Alarm void func void Read count alarm and flags R_RTC_ReadBinary amp Flags amp Count amp Alarm PDL_NO_PTR i R01US0059EG0111 Rev 1 11 Page 230 of 429 Aug 01 2014 RENESAS RX220 Group 8 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference R_RTC_CreateWarm Reconfigure RTC interrupt setting at warm start up in calendar count or binary count mode bool R_RTC_CreateWarm void func1 Callback function uint8_t data1 Interrupt priority level void func2 Callback function uint8_t data2 Interrupt priority level Reconfigure RTC interrupt setting at warm start up func1 The function to be called when an alarm occurs Specify PDL_NO_FUNC if not required data1 The alarm interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func2 The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data2 The periodic interrupt priority level
395. p the DMAC and DTC to rewrite any registers related to WDT while the chip is in sleep mode If IWDT is stopped do not set up the DMAC and DTC to rewrite any registers related to IWDT while the chip is in sleep mode If a condition for the independent watchdog timer to stop counting applied at the time of a transition to all module clock stop mode using a reset from the independent watchdog timer to release the chip from all module clock stop mode is impossible because the independent watchdog timer is stopped The peripheral Create functions bring modules out of the clock stop state as required The peripheral Destroy functions put modules into the clock stop state as required When All Module Clock Stop mode is cancelled the peripherals that were active when that mode was entered will be re activated When one of the frequencies of the internal clocks ICLK PCLKD PCLKB and FCLKk is set to 1 1 frequency division the PDL_LPC_SLEEP_RETURN_CHANGE_HOCO setting is prohibited In all module clock stop mode while the POE interrupt is enabled the operation is not restored by POE interrupt occurance However the POE interrupt occurs after the operation is restored by another source Do nottry to change operating mode if ROM Program Erase mode is set or a mode transition is already in progress This function will return false if this is detected Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions
396. pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Toggle the priority to the Internal Peripheral Bus 1 between Main Bus 1 and Main Bus 2 R_BSC_Set PDL_BSC_PRIORITY_PB1_MB1 i R01US0059EG0111 Rev 1 11 Page 118 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 R_BSC Create Synopsis Configure the BSC error detection Prototype bool R_BSC_Create uint8_t data1 Error control void func Callback function uint8_t data2 Interrupt priority level Description 1 1 Configure the error detection and register the callback function data1 e Error monitoring PDL_BSC_ERROR_ILLEGAL_ADDRESS_ DISABLE or Disable or enable illegal PDL_BSC_ERROR_ILLEGAL_ADDRESS_ ENABLE address access detection func The function to be called when a bus error occurs Specify PDL_NO_FUNC if not required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclusive otherwise false Category Bus Controller Reference R_BSC_Set R_BSC_Control Remarks e If required call R_BSC_Set before using this function e Acallback function is executed by the interrupt processing function This means that no other interr
397. pdl_lib_test rpdl_lib_test Add content To use library with debug information enter RPDL RX220_library_debug as the File path Add content In this section only options which you must change from the default settings are described If you add RPDL in existing project see also 1 2 Compiler options when you use this product Add section 11 Using library with debug information R_IO_PORT_ReadControl correct typo error b7 b1 to b7 b0 R_IO_PORT_ModifyConitrol correct typo error b7 b1 to b7 b0 Add Please refer the program in Section 5 Real time Clock operation is not used and sub clock is not fitted on the board MCU overview Change to Controlling the MCU features and on chip ROM RTC Add Reconfigure callback function and priority setting of alarm and periodic interrupts at warm start up Table 2 Add R_RTC_CreateWarm R_CGC_Set a b Add new parameter data8 sub clock stabilization times c Revise description of the sub clock oscillator drive ability Delete Options which are applicable only when the sub clock oscillator is selected in parameter data1 d Add data8 description sub clock stabilization times R_CGC_Set Revise remarks gt Delete remark If the sub clock is selected the Start type status flag will be set to warm see R_MCU_GetStatus gt Change description Old Call this function once for each clock so
398. pends on the operation specified in parameter data1 Hence see the section below relating to the specific operation required Operation data1 PDL_ELC_ENABLE data2 data3 Operation data1 PDL_ELC_DISABLE data2 data3 Not used Specify PDL_NO_DATA Not used Specify PDL_NO_DATA Not used Specify PDL_NO_DATA Not used Specify PDL_NO_DATA Operation data1 PDL_ELC_CREATE_LINK d ata2 Module Selection PDL ELC LINK MODULE MTU2 CHANNEL 1 or PDL ELC LINK MODULE MTU2 CHANNEL 2 or PDL ELC _LINK_ MODULE MTU2 CHANNEL 3 or PDL ELC LINK MODULE MTU2 CHANNEL 4 or PDL_ELC_LINK_MODULE_TMR_CHANNEL_0 or PDL_ELC_LINK_MODULE_TMR_CHANNEL_2 or PDL_ELC_LINK_MODULE_ADC12 or PDL_ELC_LINK_MODULE_INTERRUPT_1 or PDL_ELC_LINK_MODULE_OUTPUT_PORT_B_GROUP or PDL_ELC_LINK_MODULE_INPUT_PORT_B GROUP or Select the module that will be triggered by the event PDL_ELC_LINK_MODULE_SINGLE_PORT_0 or PDL_ELC_LINK MODULE SINGLE _PORT_1 or Rev 1 11 2tENESAS Page 145 of 429 RX220 Group Description 2 5 RO1US0059EG0111 Aug 01 2014 data3 Event selection 4 Library Reference PDL ELC LINK EVENT MTU2_CHANNEL_1_COMPARE_MATCH_1A or PDL ELC LINK EVENT MTU2_CHANNEL_1_COMPARE_MATCH_1B or PDL ELC LINK EVENT MTU2_CHANNEL_1_OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_1_UNDERFLOW or PDL ELC LINK EVENT MTU
399. peration early R_SCI_GetStatus can be used to find out how many characters have been transmitted Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of bytes has been sent Interrupts The function to be called when the last byte has been sent DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R_LDMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create Polling True if all parameters are valid and the operation completed without errors False if a parameter was out of range or if the channel was already transmitting or if an error occurred during transmission Category SCI Reference R_SCl_Control R_SCl_GetStatus R01US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 245 of 429 RX220 Group 4 Library Reference Remarks The compiler adds a null character to the end of string constants If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the TXI and TEND flags will be used to manage the data transmission If the SCI channel s control registers are directly modified by the user this function may lock up The maximum number of characters to be transmitted is 65535 A callback function is executed by the interrupt processing function This means t
400. pheral Interface usage where one SPI master communicates with one SPI slave The 2 separate RSK evaluation boards are used to connect the SPI together RX220 MCU RX220 MCU SPI master SPI slave Figure 51 shows how four 32 bit words are transmitted and received simultaneously by the master The received data is then checked to confirm that the transfer was successful Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_spi h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h volatile bool master_transfer_complete void spi_master_callback void define MASTER_CHANNEL 0 void main void const uint32_t master_tx_data 4 0x00000001 0x98765432 OxABCDEF 34 0x12345678 const uint32_t slave_tx_data 4 0x32323232 0x3456789A OxDEADBEEF OxFEEDCEDE uint32_t master_rx_data 4 0x00000000 0x00000000 0x00000000 0x00000000 e8 ot as Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted her refer to 5 1 Clock Generation Circuit R01US0059EG0111 Rev 1 11 Page 406 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Configure the slave SPI IO pin R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSTIA_PA6 PDL_SPI_MISOA_PAT7 Configure the master SPI channel R_SPI_Create MASTER_CHANNEL
401. plicable interrupt pins Configuration of an external interrupt signal for use Enabling use of the software interrupt Assigning an interrupt to be processed using the Fast Interrupt route Assigning handlers for the fixed exception interrupts Controlling an external interrupt input Reading the status of an external interrupt Reading an interrupt register Writing to an interrupt register R01US0059EG0111 Rev 1 11 Aug 01 2014 2tENESAS Page 21 of 429 RX220 Group 2 Driver 2 5 1 0 Port Driver The driver functions support the use of the I O port pins providing the following operations As 2 Configuration for use Reading the pin or port configuration Modifying the pin or port configuration Reading a pin or 8 bit port value Writing to a pin or 8 bit port Comparing a pin or 8 bit port with a supplied value Modifying a pin or 8 bit port using a logical operation Waiting until a pin or 8 bit port matches a supplied value Configuring the pins that are not available on smaller packages to the required state R01US0059EG0111 Rev 1 11 Aug 01 2014 2tENESAS Page 22 of 429 RX220 Group 2 Driver 2 6 Multifunction Pin Controller Driver The driver functions support access to the Multifunction Pin Controller MPC registers which select the mode of operation for some I O pins The other driver functions modify the MPC registers automatically For peripherals that are n
402. pointer uint8_t data6 Current block size count pointer Return status flags and current channel registers data1 The start address of the transfer data area If all parameters data3 data4 data5 and data6 are not required specify PDL_NO_PTR data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the status flags are not required b15 b14 b8 b7 b0 0 Idle 1 A transfer is in progress 0 The trigger vector valid only when bit b15 1 data3 Where the current source address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data4 Where the current destination address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data5 Where the current transfer count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data6 Where the current block size count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR Return value True if all parameters are valid and exclusive otherwise false Category Data Transfer Controller Reference R_DTC_Create Remarks The start address of the transfer data area is the same as that declared in R_DTC_Create RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 139 of 429 RX220 Group 4 Library Reference
403. pons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on th
404. pt PDL_INTC_IRQ1_P31 R01US0059EG0111 Rev 1 11 Page 333 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Enable the SW1 IRQ1 interrupt TC_CreateExtInterrupt PDL_INTC_IRQ1 PDL_INTC_FALLING PDL_INTC_DTC_TRIGG IRQ1l_handler 7 Start the DTC R DTC Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Wait for user key press of SW1 while 1 void IRQ1_handler void uintl6_t StatusValue uint32_t SourceAddr uint32_t DestAddr uintl6_t TransferCount Read the status and current source address for the IRQ1 transfer R_DTC_Get Status dtc_irgl_transfer_data amp StatusValue amp SourceAddr amp DestAddr amp TransferCount PDL_NO_DATA 3 Invert the port pin R_IO_PORT_Modify PDL_IO PORT 1 5 PDL_IO PORT _XOR 1 Re enable IRQ1 as a DTC trigger R_DTC_Control PDL_DTC_TRIGGER_IRQ1 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Figure 13 Example of DTC use R01US0059EG0111 Rev 1 11 Page 334 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 10 2 Chain transfer operation Figure 14shows an example of Data Transfer Controller operation using chain transfer of blocks Address space destination_string_3 destination_string_2 destination_string_1 Renesas RX220
405. ption Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 Rev 1 11 Modify an interrupt register bool R_INTC_Modify uint16_tdata1 Register selection uint8_t data2 Logical operation uint8_t data3 Modification value Update the value in an interrupt register data1 e The register to be updated PDL_INTC_REG_IR_ register or Select the Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR register Interrupt Priority register data2 The logical operation to be applied to the register contents PDL_INTC_AND or PDL_INTC_OR or Select between AND amp OR or Exclusive OR PDL_INTC_XOR data3 The value to be used by the logical operation True if the parameter is within range otherwise false Interrupt control None e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 69 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set bits 6 and 4 in IERO8 to 1 R_INTC_Modify PDL_INTC_REG_IERO8 PDL_INTC_O
406. r 2 1 Overview This library provides a set of peripheral function control programs peripheral drivers for Renesas microcontrollers and allows the peripheral driver to be built into a user program 2 2 Control Functions summary This library has the following control functions available as peripheral drivers 1 Clock Generation Circuit These driver functions are used to configure the multiple internal clock signals 2 Interrupt These driver functions are used for configuring the external interrupt pins handling fixed interrupts and controlling the interrupt priority 3 1 0 Port These driver functions are used to configure the I O pins and provide data read write compare and modify operations 4 Multifunction Pin Controller These driver functions are used for configuring the I O pin optional functions 5 MCU Operation These driver functions are used for configuring the MCU operation 6 Voltage Detection Circuit These driver functions are used for configuring the low voltage detection response 7 Clock Frequency Accuracy Measurement Circuit These driver functions are used for configuring and using clock measurement 8 Low Power Consumption These driver functions are used for selecting lower power consumption 9 Register Write Protection These driver functions are used for controlling access to protected registers 10 Bus Controller These driver functions are used for configuring the external address
407. r PDL_INTC_IRQ3_P13 or PDL_INTC_IRQ3 PD3 PDL_INTC_IRQ4_PB1 or PDL_INTC_IRQ4_P14 or PDL_INTC_IRQ4_P34 or PDL_INTC_IRQ4_PD4 PDL_INTC_IRQ5_PA4 or PDL_INTC_IRQ5_P15 or PDL_INTC_IRQ5_PD5 or PDL_INTC_IRQ5 PES PDL_INTC_IRQ6_PA3 or PDL_INTC_IRQ6_P16 or PDL_INTC_IRQ6_PD6 or PDL_INTC_IRQ6_PE6 PDL_INTC_IRQ7_PE2 or PDL_INTC_IRQ7_P17 or PDL_INTC_IRQ7_PD7 or PDL_INTC_IRQ7_PE7 Select the pins to be used for signals IRQO to IRQ7 Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control References R_INTC_CreateExtInterrupt Remarks Before calling R_INTC_CreateExtinterrupt call this function to select the required pins The Multifunction Pin Control registers are modified to enable each selected IRQ pin and the I O Port PMR and PDR registers are modified to set the pin as an input Apin can be used both as an interrupt input and a peripheral or general purpose input or output apart from an analog input If the dual operation is required call this function before configuring the peripheral or I O port operation Some pin options are not available on smaller device packages R01US0059EG0111 Rev 1 11 Page 57 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include
408. r PDL_MTU2_CLKW_PCLK_DIV_4 or PDL_MTU2_CLKW_PCLK_DIV_16 or PDL_MTU2 CLKW_PCLK DIV 64 Counter TCNTW is supplied by the internal clock signal PCLKB 1 4 16 or 64 Counter clearing U V and W counters Va lid for n 5 PDL_MTU2_CLEAR_TGRU_DISABLE or PDL_MTU2_CLEAR_TGRU_ENABLE Disable or enable clearing of TCNTU by TGRU compare match or input capture PDL_MTU2_CLEAR_TGRV_DISABLE or PDL_MTU2 CLEAR TGRV_ENABLE Disable or enable clearing of TCNTV by TGRV compare match or input capture PDL_MTU2_CLEAR_TGRW_DISABLE or PDL_MTU2 CLEAR TGRW_ENABLE Disable or enable clearing of TCNTW by TGRW compare match or input capture ADC_trigger_operation Configure the ADC trigger operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e ADC conversion trigger control Valid for n 0 to 4 unless stated otherwise Rev 1 11 PDL_MTU2_ADC_TRIG_TGRA_DISABLE or PDL_MTU2_ADC_TRIG_TGRA_ENABLE Disable or enable ADC start requests on a TGRA compare match or input capture PDL_MTU2_ADC_TRIG_TROUGH_DISABLE or PDL_MTU2_ADC_TRIG_TROUGH ENABLE Disable or enable ADC start requests onaTCNT underflow Valid for n 4 in complementary PWM mode Control ADC trigger interrupt skipping Valid for n 4 in complementary PWM mode Disable or link interrupt
409. r Mode b31 b24 b23 b16 b15 b8 b7 b0 Day of week Hours Minutes Seconds Valid from 0 to 6 0 Sunday Specify OxFF for Valid from O Valid from O Valid from automatic calculation using the values in data5 to 23 to 59 0 to 59 12 Hour Mode b31 b24 b23 b22 b16 b15 b8 b7 b0 Day of week Valid from 0 to 6 0 Sunday PM Hours Minutes Seconds gt 0 AM Valid from Valid from Valid from Specify OxFF for automatic 1 PM 1 to 12 0 to 59 0 to 59 calculation using the values in data3 E R01US0059EG0111 Rev 1 11 REN ESAS Page 216 of 429 Aug 01 2014 RX220 Group Description 3 3 Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference data6 The alarm year month and day BCD format is used If not required specify PDL_NO_DATA b31 b16 b15 b8 b7 b0 Year Month Day Valid from 0 to 9999 Valid from 1 to 12 Valid from 1 to the number of days in the month func1 The function to be called when an alarm occurs Specify PDL_NO_FUNC if not required data7 The alarm interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func2 The function to be called at the periodic interval Specify PDL_NO_FUNC if no
410. r input capture PDL_MTU2 TGRV DTC TRIGGER DISABLE or PDL_MTU2 TGRV_DTC_TRIGGER_ENABLE TGRV compare match or input capture PDL MTU2 TGRW DTC TRIGGER DISABLE or TGRW compare match or input PDL_MTU2_TGRW_DTC_TRIGGER_ENABLE capture counter_operation Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults TCNT counter clock source selection Valid for n 0 to 4 unless stated otherwise Not effective for n 1 and 2 in Phase Counting Mode PDL_MTU2_CLK_PCLK_DIV_1 or PDL_MTU2_CLK_PCLK_DIV_4 or PDL_MTU2_CLK_PCLK_DIV_16 or PDL_MTU2_CLK_PCLK_DIV_64 or PDL_MTU2_CLK_PCLK_DIV_256 or The internal clock signal PCLKB 1 4 16 or 64 PCLKB 256 Valid for n 1 3 and 4 PDL_MTU2_CLK_PCLK_DIV_1024 or PCLKB 1024 Valid for n 2 3 and 4 PDL_MTU2 CLK MTCLKA or MTCLKA pin input Valid for n 0 to 4 PDL_MTU2 CLK MTCLKC or PDL_MTU2_CLK_MTCLKB or MTCLKB pin input Valid for n 0 to 4 MTCLKC pin input Valid for n 0 or 2 PDL_MTU2 CLK MTCLKD or MTCLKD pin input Valid for n 0 PDL_MTU2_CLK_CASCADE The overflow underflow signal from channel n 1 Valid for n 1 e TCNT counter clock edge selection Valid for n 0 to 4 Not effective for n 1 and 2 in Phase Counting M
411. r setting option PDL_CGC_RTC_TO_ BE USED in R_CGC_Control at cold start c This function is not required when using 48 pin package R_RTC_CreateBinary add new option Clock RTCOUT output period Select R_RTC_CreateBinary revise remarks gt Deleted remarks a Before calling this function the sub clock must be enabled and stable Hence use R_CGC_Set or R_CGC_Control to enable the sub clock and then allow the clock stabilization time to pass before calling this function b If this function has been used and then a warm reset is performed it is not necessary to call this function again to continue using the RTC However if this function is to be called it is necessary to call R_CGC_Set or R_CGC_Control to enable the sub clock even if it is already enabled before calling this function c Call R_CGC_Set to set PCLKB clock frequency sub clock frequency when sub clock is source clock d Call R_CGC_Set to set PCLKB clock frequency 2 sub clock frequency when sub clock is not source clock gt Add remarks a Before calling this function the count source must be enabled and stable Refer R_CGC_Set and R_CGC_Control for count source and stabilization time configuration b This function is called to use RTC after setting option RO1USO059EG0111 Rev 1 11 Revision History 3 Aug 01 2014 RENESAS RX220 Group Revision History Description PDL_CGC_RTC_TO_BE_USED in R_CGC_Control at cold start c This function is not requi
412. r to 5 1 Clock Generation Circuit Configure the slave SPI IO pin R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PAT7 i Configure the slave SPI channel R_SPI_Create SLAVE_CHANNEL L_SPI_MODE_SYNC_SLAV L_SPI_FRAME 1 1 _NO_DATA E6 Configure the slave R_SPI_Command SLAVE_CHANNEL 0 PDL_SPI_CLOCK_MOD PDL_SPI_LENGTH_8 PDL_SPI_LSB_FIRST PDL_NO_DATA Clear the receive buffers for i 0 i lt BUFFER_LENGTH i slave_rx_data i 0x00000000 Copy the source data into the transmit buffers R01US0059EG0111 Rev 1 11 Page 413 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples i lt strlen master_data_to_be_ sent i slave_tx_data i uint32_t slave_data_to_be_sent i Prepare the Slave for data transfer R_SPI_Transfer SLAVE_CHANNEL PDL_NO_DATA slave_tx_data slave_rx_data uint16_t strlen slave_data_to_be_sent spi_slave_callback 15 while slave_transfer_complete false for i 0 i lt strlen master_data_to_be_sent i Did the Master output match the Slave input if master_data_to_be_sent i uint8_t slave_rx_data i Handle the error while 1 while 1 void spi_slave_callback void uintl6_t StatusValue 0 uintl6_t Sequence_count Read the sl
413. r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h void func void Enable access to the LVD registers R_RWP_Control PDL_RWP_ENABLE_LVD_WRITE R01US0059EG0111 Rev 1 11 REN ESAS Page 116 of 429 Aug 01 2014 RX220 Group 4 Library Reference 2 Synopsis Prototype Description Get the status of the register protection R_RWP_GetStatus bool R_RWP_GetStatus uint8_t data1 uint8_t data2 J Get the status of the register protection Status flags pointer Status flags pointer Return value Category Reference Remarks Program example data1 The Protect Register PRCR If the value is not required specify PDL_NO_PTR b7 b4_ b3 b2 b1 bO LVD Mode and Reset CGC 0 0 Write Disabled 0 0 Write Disabled 0 Write Disabled 1 Write Enabled 1 Write Enabled 1 Write Enabled data2 The MPC Write Protect Register PWPR If the value is not required specify PDL_NO_PTR b7 b6 b5 b0 BOWI PFSWE 0 Writing to the PFSWE bit is enabled 0 Writing to the PFS register is disabled 0 1 Writing to the PFSWE bit is disabled 1 Writing to the PFS register is enabled True RWP None RPDL definitions include r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h v
414. re using this function gt Add remark This function is not required when using 48 pin package R_RTC_ReadBinary gt Change remark Call R RTC_CreateBinary or R_RTC_CreateWarm first before using this function gt Add remark This function is not required when using 48 pin package R_RTC_ReadBinary Add Program example R_RTC_CreateWarm new API added R_IWDT_Set gt Add remark The IWDT counter frequency must not be greater than the PCLB 4 Set the IWDTCLK division ratio accordingly This function will return false if this condition is detected gt Delete remark Call R_CGC_Set to set PCLKB clock frequency gt 4 times IWDTCLK clock frequency after division 237 238 R_SCI_Set Add pins selection for channel 9 12 248 249 R_SCI_Receive Add continuous receive mode option and remarks RO1USO059EG0111 Rev 1 11 Revision History 4 Aug 01 2014 RENESAS RX220 Group Revision History Description R_IIC_MasterSend gt Add option PDL_IIC_10_BIT_SLAVE_ADDRESS 270 gt Remove remark Channels 1 and 3 are not available with the 80 pin and 100 pin packages This function will return false in this case 271 R_IIC_MasterReceive gt Add option PDL_IIC_10_BIT_SLAVE_ADDRESS 272 gt Remove remark Channels 1 and 3 are not available with the 80 pin and 100 pin packages This function will return false in this case 273 275 Remove remark in R_IIC_MasterReceiveLast R_IIC_
415. re at channel n 1 up count or down count Valid only for n 0 Rev 1 11 2 ENESAS Page 159 of 429 RX220 Group Description 7 9 PDL_MTU2_W_IC_BOTH EDGES or Input capture at MTICnW both edges PDL_MTU2_W_IC_PWM_LOW_TROUGH or _ Input capture at trough PDL_MTU2_W_IC_PWM_LOW_CREST or crest or PDL_MTU2_W_IC_PWM LOW BOTH or both for low pulse width measurement PDL_MTU2_W_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU2_W_IC_PWM_HIGH_CREST or crest or PDL_MTU2_W_IC_PWM_HIGH BOTH both for high pulse width measurement RO1USOO59EG0111 Rev 1 11 Page 160 of 429 Aug 01 2014 TGR_U_V_W_ operation Configure the input capture compare match control for general registers TGRU TRGV and TGRW Valid for n 5 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults 4 Library Reference Input capture compare match control for register TGRU PDL_MTU2_U_CMor Compare match PDL_MTU2_U_IC_RISING_EDGE or PDL_MTU2_U_IC_FALLING_EDGE or Input capture at MTICnU rising edge Input capture at MTICnU falling edge PDL_MTU2_U_IC_BOTH_EDGES or Input capture at MTICnU both edges PDL_MTU2_U_IC_PWM_LOW_TROUGH or Input capture at trough PDL_MTU2_U_IC_PWM_LOW_CREST or crest or PDL_MTU2_U_IC_ PWM _LOW_BOTH or both for low pulse width measurement PDL_MTU2_U_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU2_U_IC_PWM_HIGH_CREST or cre
416. re the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that will receive the data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data Rev 1 11 REN ESAS Page 256 of 429 RX220 Group Description 2 2 Return value Category Reference Remarks Program example 4 Library Reference func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Polling PDL_NO_FUNC This function will continue until the required number of bytes has been transferred or an error occurs The function to be called when the transfer has completed or an error Interrupts detected Either the function to be called when each byte is transferred or DMAC PDL_NO_FUNC if the callback function specified in R_LDMAC_ Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_SCI_GetStatus R_SCI_IIC_ReadLastByte R_SCl_Control
417. rection selection PDL_DMAC_SOURCE_ADDRESS FIXED or Leave the source address unchanged PDL_DMAC_SOURCE_ADDRESS_PLUS or increment it decrement it or modify it by PDL_DMAC_SOURCE_ADDRESS_MINUS or the value specified in parameter data8 PDL_DMAC_SOURCE_ADDRESS_ OFFSET Address offset is valid only for n 0 PDL_DMAC_DESTINATION_ADDRESS FIXED or PDL_DMAC_DESTINATION_ADDRESS_PLUS or PDL_DMAC_DESTINATION_ADDRESS_MINUS or PDL_DMAC_DESTINATION_ADDRESS_OFFSET Leave the destination address unchanged increment it decrement it or modify it by the value specified in parameter data8 Address offset is valid only for n 0 e Transfer data size PDL_DMAC_SIZE_8 or PDL_DMAC_ SIZE 32 PDL_DMAC_SIZE_16 or Select 8 16 or 32 bits for the data to be transferred e Interrupt generation optional PDL_DMAC_IRQ_END Transfer completion PDL_DMAC_IRQ_ESCAPE_END Escape end PDL_DMAC_IRQ_REPEAT_SIZE_END 1 repeat size or 1 block data transfer completion PDL_DMAC_IRQ_EXT_SOURCE Extended repeat area overflow on the source PDL_DMAC_IRQ_EXT_DESTINATION destination Extended repeat area overflow on the Page 122 of 429 RX220 Group Description 2 3 e Start trigger forwarding 4 Library Reference RO1US0059EG0111 Aug 01 2014 Rev 1 11 PDL_DMAC_TRIGGER_CLEAR or PDL_DMAC_TRIGGER_ FORWARD When the DMAC transfer is complete clear the DMAC ac
418. red Shutdown the Data Transfer Controller True Data Transfer Controller R_DTC_Control e This function will also shut down the DMAC e Before calling this function i If another peripheral is being used to trigger a DTC transfer stop the triggers from that peripheral using Control or Destroy for that peripheral ii Use R_DTC_Control to stop the DTC iii Stop the DMAC RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the DTC amp DMAC R_DTC_Destroy Rev 1 11 REN ESAS Page 136 of 429 RX220 Group 4 Synopsis Prototype Description Return value 4 Library Reference R_DTC_Control Control the Data Transfer Controller bool R_DTC_Conirol uint32_t data1 Control options uint32_t data2 Transfer data start address void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint8_t data6 Block size Modify the operation of the Data Transfer Controller data1 Control the operation If multiple selections are required use to separate each selection e Stop Start control PDL_DTC_STOP or PDL_DTC_START Enable re enable or suspend DTC transfers The transfer registers to be modified using the selected parameters PDL_DTC_U
419. red when using 48 pin package R_RTC_Destroy add This function is not required when using 48 pin package R_RTC_Control add new option Clock RTCOUT output period Select R_RTC_Control revise remarks gt Deleted remark a Call R_RTC_Create first before using this function b If R_LRTC_Create has been used and then a warm reset is performed it is not necessary to call R_RTC_Create again before using this function However it is necessary to call R_ CGC_Control or R_CGC_Set to enable the sub clock even if it is already enabled before calling this function gt Add remarks a This function is called after R_LRTC_Create or R_RTC_CreateWarm b This function is not required when using 48 pin package R_RTC_ControlBinary add new option Clock RTCOUT output period Select R_RTC_ControlBinary revise remarks gt Deleted remark a Call R_RTC_CreateBinary first before using this function b If R RTC_CreateBinary has been used and then a warm reset is performed it is not necessary to call R_LRTC_CreateBinary again before using this function However it is necessary to call R_CGC_Control or R_ CGC_Set to enable the sub clock even if it is already enabled before calling this function gt Add remarks a This function is called after R_LRTC_CreateBinary or R_ RTC_CreateWarm b This function is not required when using 48 pin package R_RTC_Read gt Change remark Call R_RTC_Create or R_RTC_CreateWarm first befo
420. rence Remarks Program example RO1US0059EG0111 Aug 01 2014 True Interrupt control e The fast interrupt processing is allocated to only one interrupt handler Open the file r_pdl_user_definitions h and edit the definition FAST_INTC_VECTOR to give it the same value as the interrupt vector used in parameter data1 For example define FAST_INTC_VECTOR PDL_INTC_VECTOR_IRQ2 This will direct the compiler to generate the instructions required for a fast interrupt vector e This function uses an interrupt routine to modify the FINTV register If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Assign the fast interrupt to the handler for pin IRQ3 R_INTC_CreateFastInterrupt PDL_INTC_VECTOR_IRQ3 Remember to edit r_pdl_user_definitions h see remark 2 Rev 1 11 REN ESAS Page 64 of 429 RX220 Group 5 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference R_INTC_CreateExceptionHandlers Assign handlers for the fixed vector interrupts bool R_INTC_CreateExceptionHandlers void func1
421. rence Remarks lt Function R CGC_Set must be called with the current clock source selected before using this function Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Ensure that the timer channel is stopped before calling this function The timing limits depend on the frequency of the peripheral module clock PCLKB fpcLke MHz Equation 32 12 5 12 8 8 Periodmin 250ns 640ns 667ns 1 0us JT cies ga Periodmax 1 05s 2 68s 2 79S 4 19s freixe fmax Secre 4 0 MHz 1 56 MHz 1 5 MHz 1 0 MHz 8 fmin f 5 AAP 0 95 Hz 0 37 Hz 0 357 Hz 0 24 Hz Ifthe requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Configure CMT channel 0 for 10s operation R_CMT_Create 0 PDL_CMT_PERIOD 10E 6 PDL_NO_FUNC 0 Configure CMT channel 1 for 1kHz operation R_CMT_Create 1 PDL_CMT_FREQUENCY 1E3 PDL_NO_FUNC 0 Configure CMT channel 2 using register values R_CMT_Create 2 PDL_CMT_PCLK_DIV_32
422. rence R_SCI_IIC_Read Perform an IIC master read on an SCI channel bool R_SCI_IIC_Read uint8_tdata1 Channel selection uinti6 tdata2 Channel configuration uint16_t data3 Slave Address uinti6 tdata4 Number of bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master read data1 Select channel SClIn where n 1 5 6 9 or 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage e Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL _SCI_IIC_10 BIT SLAVE ADDRESS Specify the slave address width e Repeated Start PDL_SCI_IIC_RESTART The transfer will start with a re start rather than the default behaviour of a start condition Stop Condition selection By default the transfer will end with a stop condition PDL_SCI_IIC_NOSTOP Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address 7 b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred befo
423. ring occur after the compare match has occurred So the values for compare match A and compare match B should be 1 less than the required count Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_definitions h void main void Initialise the system clocks NOTE The code to initialise the system clock is omitted here Please refer to 5 1 Clock Generation Circuit Configure TMRO input and output pins R_TMR_Set 0 PDL_TMR_TMRO_TMOO_PB3 i Configure TMRO to clear on a compare match A output 1 at a compare match A and output 0 at a compare match B R_TMR_CreateChannel 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_TMR_OUTPUT_HIGH_CM_A PDL_TMR_OUTPUT_LOW_CM_B 0 200 173 200 2 1 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 Figure 20 Example of Pulse Output code Counter value Figure 21 Example of pulse output operation R01US0059EG0111 Rev 1 11 Page 344 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 15 Compare Match Timer Figure 22 shows an example of Compare Match Timer usage One channel is used to generate interrupts at regular intervals Channel 0 is used to generate interrupt using frequency configuration at 1 kHz then change to 5 Hz When channel 0 is created it will not start until 1 second delay passed Channel 1 is used to generate interrupt using period of 0 1 second Channel 1 start
424. rity bit Block transfer mode selection PDL_SCI_BLOCK_MODE_OFF or PDL_SCI_BLOCK_MODE_ON Control Block transfer mode e GSM mode selection PDL_SCI_GSM_MODE_OFF or PDL_SCl_GSM_MODE_ON Control GSM mode e SCKn pin output control Note how the default option changes depending upon the mode In Normal Mode the default is an I O Pin In GSM Mode the default is Fixed Low Normal mode GSM mode PDL_SCI_SCK_OUTPUT_OFF or I O pin Not applicable PDL_SCI_SCK_OUTPUT_LOW or Not applicable Fixed low PDL_SCI_SCK_ OUTPUT ON or Outputs the bit clock PDL_SCI_SCK_ OUTPUT HIGH Not applicable Fixed high REN ESAS Page 241 of 429 RX220 Group Description 4 4 Return value 4 Library Reference data3 Select the SCI transfer rate See the Remarks section for the maximum rate that the device can support The format may be either e The transfer bit rate in bits per second bps The clock division values will be calculated using this value This format is valid only when the on chip baud rate generator is selected as the data clock source in parameter data2 Or the following using to separate each selection e b31 b30 b24 b23 b0 A value between 256 0x100 and 16 776 960 OxFFFFOO that is 1 0 nearest to the expected transfer bit rate e ABCS selection required for asynchronous mode PDL_SCI_CYCLE_BIT_16 or
425. rs with Comparator A so both cannot be used at the same time If using the digital filter function R_CGC_Set must be called with the current clock source selected before using this function If using the digital filter the LOCO clock must be enabled Use R_CGC_Set with the LOCO selected Following a reset function R_LPC_GetStatus can be used to see what caused the reset If using a delay on Reset negation then the LOCO clock must be enabled See R_CGC_Set or R_CGC_Control If the CMPA2 pin input is selected the detection voltage is fixed at 1 33V The same voltage level must not be specified for more than one voltage monitor This includes voltage monitor 0 see R MCU_OFS If this condition is detected this function will return false To enable the LVD event link output function enable the LVD first then enable the LVD event link function at the ELC To disable this function disable the LVD event link function at the ELC first then disable the LVD It is possible to configure the LVD to trigger the ELC but not generate an interrupt itself To do this setup the LVD as required using one of the following operations PDL_LVD_INTERRUPT_MI_DETECT_RISE or PDL_LVD_INTERRUPT_MI_DETECT_FALL or PDL_LVD_INTERRUPT_MI_DETECT_RISE_AND_FALL Set the callback function as PDL_NO_FUNC and set the interrupt priority to 0 Disable the digital filter circuit when using voltage monitoring 1 and 2 circuit in software standby mode ELC is only valid for vo
426. runction the data will be stored to the top of receive buffer data3 Rev 1 11 REN ESAS Page 249 of 429 RX220 Group 4 Library Reference Program example RO1US0059EG0111 Aug 01 2014 PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t SCI1ReceiveBuffer 10 SCI channel 1 receive data handler void SCI1 RxFunc void SCI channel 1 error handler void SCI1I ErrFunc void void func void Rev 1 11 received on channel 6 uint8_t temp Wait for 1 character to b R_SCI_Receive 6 PDL_NO_DATA amp temp 1 PDL_NO_FUNC PDL_NO_FUNC Start the reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA SCI1ReceiveBuffer 9 SCI1RxFunc SCI1ErrFunc 2tENESAS Page 250 of 429 RX220 Group 4 Library Reference 6 Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 R_SCI_SPI_Transfer Perform an SPI transfer on an SCI channel bool R_SCI_SPI_Transfer uint8_tdata1 Channel selection uinti6 tdata2 Channel configuration uint16_t data3 Number of bytes to transfer uint8_t data4 Data transmit buffer void func Callback function Transmit Done uint8_t data5 Data receive buffer void func2 Callback function Receive Done void
427. rupt occurs True if all parameters are valid and exclusive otherwise false 12 bit ADC None e For single scan mode the ADC will stop automatically when the conversion is complete Do not select CPU Off unless there is any interrupt to wake up the CPU RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Start the ADC conversion process R_ADC_12 Control PDL_ADC_12_0_ON i RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 304 of 429 RX220 Group 4 Library Reference 6 Synopsis Prototype Description Return value Category Reference Remarks Program example RO1US0059EG0111 Aug 01 2014 R_ADC_12 Read Read the ADC conversion results bool R_ADC_12_Read uint8_t data1 ADC unit selection uint16_t data2 Pointer to the address where the results are to be stored uint16_t data3 Pointer to the address where the result is to be stored Reads the conversion values for an ADC unit data1 Select the ADC unit to be configured This must always be 0 data2 Specify a pointer to an array with 16 members where the converted values for analog input channels are to be stored data3 Specify a pointer to the address where the converted value for internal reference voltage diagnostic resu
428. s void func void Read the timer status R_IWDT_Read amp Status di RO1US0059EG0111 Aug 01 2014 Rev 1 11 RX220 Group 4 2 20 1 R_SCI Set Synopsis Prototype bool R_SCI Set uint8_t data1 uint16_t data2 3 Description 1 2 RO1US0059EG0111 Aug 01 2014 data1 Serial Communication Interface Channel selection Pin configuration The channel number n where n 1 5 6 9 or 12 The 48 pin package does not support SCI channel 9 data2 Configure the global options Use to separate each selection Valid when n 1 Configure I O pins All pins used must be specified There is no default option 4 Library Reference Configure the SCI pin selection for SCI channels where there is a choice of SCI pins PDL_SCI_PIN_SCl1_RXD1_P15 or PDL_SCI_PIN_SCl1_RXD1_P30 RADI PDL_SCI_PIN_SCI1_SMISO1_P15 or SMISO1 PDL_SCI_PIN_SCI1_SMISO1_P30 PDL_SCI_PIN_SCI1_SSCL1_P15 or SSCL1 PDL_SCI_PIN_SCl1_SSCL1_P30 PDL_SCI_PIN_SCI1_TXD1_P16 or TXD1 PDL_SCI_PIN_SCl1_TXD1_P26 PDL_SCI_PIN_SCI1_SMOSI1_ P16 or SMOSII PDL_SCI_PIN_SCI1_SMOSI1_ P26 scn PDL_SCI_PIN_SCI1_SSDA1_P16 or SSDA1 PDL SCI_PIN_SCI1_SSDA1_P26 PDL_SCI_PIN_SCI1_SCK1_P17 or SCK1 PDL_SCI_PIN_SCI1_SCK1_P27 PDL_SCI_PIN_SCI1_CTS1_P14 or CTS1 PDL_SCI_PIN_SCI1_CTS
429. s 0 to 5 True if the unit selection is valid otherwise false Multi function Timer Pulse Unit None e The unit is put into the stop state to reduce power consumption include r_pdl_mtu2 h void func void Shutdown MTU2 channels 0 to 5 R_MTU2_Destroy 0 R01US0059EG0111 Rev 1 11 REN ESAS Page 164 of 429 Aug 01 2014 RX220 Group 4 Library Reference 4 R_MTU2_ConitrolChannel Synopsis Control an MTU channel Prototype bool R_MTU2_ConitrolChannel uint8_t data1 Channel selection R_MTU2_ControlChannel_structure data2 A pointer to the structure R_MTU2_ControlChannel_structure members uint8_t control_setting Control settings uint16_t register_selection Register selection uinti6 _t TCNT_TCNTU_value Register value uinti6 _ t T 4RA_TCNTV_value Register value uinti6 _t T 4RB_TCNTW_value Register value uint16_t TGRC_TGRU_value Register value uint16_t T 4RD_TGRV_value Register value uint16_t TG RE_TGRW_value Register value uint16_t TGRF_value Register value uint16_t TADCOBRA_value Register value uint16_t TADCOBRB_ value Register value Description 1 2 Modify a timer channel s registers data1 The channel number n where n 0 to 5 control_setting The channel settings to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop
430. s right after it is created and stop when 1 second delay passed Both channel 0 and channel 1 will be destroyed before the main loop Channel 2 and channel 3 are used to create one shot delay PDL functions include r_pdl_cgc h include r_pdl_cmt h include r_pdl_intc h include r_pdl_io_port h PDL device specific definitions include r_pdl_definitions h void CMTO_handler void void CMT1_handler void void main void uint8_t flags uintl6_t counter Configure main clock operation using a 20 0 MHz crystal ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_MAIN_RESONATOR 20 20 20 20 201 DAOAAO a AAA Configure HOCO operation ICLK 32 MHz PCLKD 32 MHz PCLKB 32 MHz FCLK 32 MHz R_CGC_Set PDL_CGC_CLK_HOCO PDL_CGC_HOCO_32000 32 32 32 32 32 DAAAOD Hee oo Wait 100us for the main clock to stabilise R_CMT_CreateOneShot 3 PDL_NO_DATA 100E 6 PDL_NO_FUNC 0 Select HOCO as the clock source R_CGC_Control PDL_CGC_CLK_HOCO PDL_NO_DATA PDL_NO_DATA Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Configure port pins for output R_IO_PORT_Set PDL_IO_PORT_1_4 PDL_IO PORT OUTPUT R_IO_PORT_Set PDL_IO_PORT_1_5 PDL_IO_PORT_OUTPUT
431. sable the transmission If a callback function is specified and the interrupt priority level is zero this function will return false RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 246 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data_store 100 Send a string on channel 1 R_SCI_Send 1 PDL_NO_DATA Renesas RX 0 PDL_NO_FUNC Send 50 bytes of binary data on channel 1 R_SCI_Send 1 PDL_NO_DATA data_store 50 PDL_NO_FUNC Send the ID byte 0x0A shifted into the upper byte R SCI Send 1 PDL_SCI_MP_ID_CYCLE 0x0A00 PDL_NO_PTR 0 PDL_NO_FUNC T R01US0059EG0111 Rev 1 11 Page 247 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 5 Synopsis Prototype Description R_SCI_Receive Receive data on a SCI channel bool R_SCI_Receive uint8_tdata1 Channel selection uinti6 tdata2 Channel configuration and Station ID of receiving device uint8_t data3 Data start address uint16_t data4 Receive threshold void func Callback function void func2 Callback function Enable SCI reception and acquire any incoming data data1 Select channel SClIn where n 1 5 6 9 or 12 data2 Control op
432. se width or duty cycle This will be ignored if a timing change is not requested Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreatePeriodic Remarks e See the remarks for R_TMR_CreatePeriodic RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 202 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Change timer TMR1 to 600ns period 100ns pulse width R_TMR_ControlPeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD 600E 9 100E 9 R01US0059EG0111 Rev 1 11 Page 203 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 10 R_TMR_ReadChannel Synopsis Prototype Description Read from timer channel registers bool R_TMR_ReadChannel uint8_tdata1 Channel selection uint8_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location uint8_t data4 A pointer to the data storage location uint8_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 1 2 or 3 data2 The status flags shall be stored in the format below The flag will be set
433. second call of this function will be the one that is enabled 48 pin package 64 pin package PBO and PCO PB6 and PCO PB1 and PC1 PB7 and PC1 PB3 and PC2 PB5 and PC3 Rev 1 11 REN ESAS Page 76 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set up port pin P13 as an input port with the pull up on R_IO_PORT_Set PDL_IO_PORT_1_3 PDL_IO_PORT_INPUT PDL_IO_PORT_PULL_UP_ON R01US0059EG0111 Rev 1 11 Page 77 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 2 Synopsis Prototype Description Return value Category References Remarks R_lIO_PORT_ReadControl Read an I O port s control register bool R_IO_PORT_ReadControl uint16_t data1 Port or port pin selection uint8_t data2 Control register selection uint16_t data3 Data storage location Read an I O port pin control setting data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 e Select the register to be read PDL_IO_PORT_DIRECTION or Data direction PDL_IO_PORT_ MODE or General or Peripheral I O mode control PDL_IO_PORT_TYPE or Open drain control PDL_IO_PORT_PULL_UP or Pull up c
434. specify a function if PDL_CMT_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CGC_ Set R_CGC_Control RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 209 of 429 RX220 Group Remarks Program example RO1US0059EG0111 Aug 01 2014 4 Library Reference e Function R_CGC_Set must be called with the current clock source selected before using this function e Function R_CMT_Create is not required e Ensure that the timer channel is stopped before calling this function Note that the timer is stopped automatically when the one shot period is reached e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e The timing limits depend on the peripheral module clock PCLKB fpcLke MHZ Equation Fag 12 5 12 8 8 Tmn o 250ns 640ns 666 67ns tus pcik 9 Ta 1 05s 2 68s 2 795 4 195 X Fre e If
435. ssneeeeesseeeeesseeeensseeeeess 102 Re GAGs Create tenere deei iaa lee eaan ea a cued te aa ea d e a a dwn ea 102 RCAC DESTOY iii iaae iieiea adii dioiii iaia ad aii ai ai de Winn iiaia 105 RCAC CONI Oea a A ee a fe Me a Epai a E E LA A EE E EE A 106 RCAC GetStatus vis in e i i N a a a a a a aa 108 Low Power Consumption 0 ccccccceeececeeeeececeeeaeeeeeeeceeeeeaaeeseaaesecaeeceaeeeseaeedeaeeseeeesaeeseeeseeeees 109 Re LPC Croatan anhini eisini n Mine a a i N a a e a a Badd 109 RAERC CONTO ENA ia e na e d a naa seta e a a aa E a A a E a EEY 113 R EPC GStStAtUS uii a i a a datas a a e 115 Register Write Protection c ccccceceesceceeeeeeeeeeeeeeeeeceneeeeeaeeeseessaeeseesaeeeseeseeeesesseeeeeeenenaeeeenenees 116 RERWP2 Control reien sacle Odie cneited ts Mi e a core See eM pantie eddes Waste i aA 116 Ra BWP GetStatus EEE AEA E a ite itech epvatbechedtehlsbcnebictecbevbieestnelary ats send 117 B s Controller sev cee sdectscorkoies r a vabhhnad aa E beens a aaa a T araara aaea a aE a Taare Ea 118 aee Oe E A A A A A E ebeveleaucelare ceeskseeued 118 Re BSG Create E E E E A A E ebeebiedeattlace ebeetioaes 119 ReiBSG Control TE A A AE E 120 BENOE E EE AEEA A ctwxdsstien 121 DINIE ZELINIiKO T AT E E A EEA E 122 Re DMAG Greate EAE E E R A cars E E AE 122 R DMAG DesirOy igaren cheststzsecebnesccuatsnectegencs chestinsacebtesecuativergebents cdestuezceteaes EERE EENEN KEREN 126 REDMAG CONIO Aeara arar aea aae Soe der saz AEE A
436. st or PDL_MTU2_U_IC_PWM_HIGH BOTH both for high pulse width measurement Input capture compare match control for register TGRV PDL_MTU2_V_CMor Compare match PDL_MTU2_V_IC_RISING_EDGE or PDL_MTU2_V_IC_FALLING_EDGE or Input capture at MTICnV rising edge Input capture at MTICnV falling edge PDL_MTU2_V_IC_BOTH_ EDGES or Input capture at MTICnV both edges PDL_MTU2_V_IC_PWM_LOW_TROUGH or Input capture at trough PDL_MTU2_V_IC_PWM_LOW_CREST or crest or PDL_MTU2_V_IC_PWM_LOW_BOTH or both for low pulse width measurement PDL_MTU2_V_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU2_V_IC_PWM_HIGH_CREST or crest or PDL_MTU2_V_IC_PWM_HIGH_BOTH both for high pulse width measurement Input capture compare match control for register TGRW PDL_MTU2_ W_CMor Compare match PDL_MTU2_W_IC_RISING EDGE or PDL_MTU2_W_IC_FALLING_EDGE or Input capture at MTICnW rising edge Input capture at MTICnW falling edge 2 ENESAS RX220 Group Description 8 9 RO1US0059EG0111 Aug 01 2014 Rev 1 11 noise_filter_operation 4 Library Reference Noise filter control for register NFCRn n 0 to 5 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Noise filter control for register NFCRn PDL_MTU2_NF_A_U_DISABLE or PDL_MTU2_NF_A_U_ENABLE Enable or disable
437. t flag CWSF 1 call R_RTC_CreateWarm to start up the RTC if warm cold start flag is detected power ON from warm start Get Reset Status Flag R_MCU_Get Status PDL_NO_PTR amp status PDL_NO PTR PDL_NO_PTR status amp BIT_8 uint16_t BIT_8 amp amp RTC RCR2 BIT START 0 If warm start is detected and RTC is running then warm start R01US0059EG0111 Rev 1 11 Page 358 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA r nRTC Start in Warm start mode Control to change time r n 0 PDL_NO_FUNC Warm wake up Read time R_RTC_Read PDL_RTC_READ_CURRENT amp flags amp time amp date sprintf char buffer RTC Time before changing d d d d d d r n int time amp OxF00000 gt gt 20 int time amp 0x0F0000 gt gt 16 int time amp 0x00F000 gt gt 12 int time amp 0x000F00 gt gt 8 int time amp 0x0000F0 gt gt 4 int time amp 0x00000F gt gt 0 R_SCI_Send RSK_SCI_CHANNEL PDL_NO_DATA buffer 0 PDL_NO_FUNC R_RTC_CreateWarm Alarm_handler Alarm handler 15 Alarm priority PDL_NO_FUNC Periodic Handler PDL_NO_DATA Periodic priority i R_RTC_Read PDL_RTC_READ_CURR PDL_NO_PTR amp time amp date Configure the clock R_RTC_Control p DATA UPDATE_ALARM_ TIM DATA DATA 0x10
438. t independently If using the polling transfer mode for only one direction this function must not be called from an interrupt handler so that interrupts can still be serviced for the non polling transfer direction Rev 1 11 REN ESAS Page 252 of 429 RX220 Group Program example R01US0059EG0111 Aug 01 2014 PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t SCI1RxBuffer 10 const uint8_t SCI1TxBuffer 10 LI peg TS g TEE g OB gg OO gp OT a 8 OT ge OO g SO Ne SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCI1lErrFunc void void func void Wait while send 5 characters on channel 6 R_SCI_SPI_Transfer 6 PDL_NO_DATA 5 TI2345 PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC 4 Library Reference Start the transmission and reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA SCI1RxBuffer 9 SCI1RxFunc SCI1ErrFunc Rev 1 11 RENESAS Page 253 of 429 RX220 Group 7 Synopsis Prototype Description 1 2 R01US0059EG0111 Aug 01 2014 4 Library Reference R_SCI_IIC_Write Perform an IIC master write on an SCI channel bool R_SCI_lIC_Write uint8_tdata1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Sl
439. t no other interrupt can be processed until the callback function has completed e Function R_CGC_Set must be called with the current clock source selected before using this function e In group scan mode or continuous scan mode PDL_ADC_12_INPUT_REF cannot be selected e When the internal reference voltage is to be converted the disconnection detection assist function is not available e Allow 1us to elapse from the completion of this function to the start of the first conversion e Make sure sampling time calculated or specified for channel 0 and self diagnosis are the same e For more details of trigger sources please refer to the RX220 hardware manual RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h ADC callback function void ADCIntFunc void void func void Set up the ADC in single mode R_ADC_12_ CreateUnit L_ADC_12_SCAN_ SINGLE L_ADC_12_GP_TRIGGER_MTU_TRGOAN L_NO_DAT d L_NO_DAT L_NO_DAT CIntFunc DPP i D D D D D D DL_NO_FUNC DL_NO_DATA ao iiao BS a ao a ao o a S Rev 1 11 REN ESAS Page 300 of 429 RX220 Group 3 Synopsis Prototype Description Return value 4 Library Reference R_ADC_12_CreateChannel Configure 12 bit ADC analog channels bool R_ADC_12_CreateChannel uint8_t data
440. t required data8 The periodic interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid otherwise false Real time clock R_RTC_Read The check for days in the month allows for leap years e If entering software standby mode soon after starting the RTC use R_RTC_Read first to confirm that the values are correct e The oscillation accuracy of the sub clock is affected when an on chip debugger emulator is connected and the sub clock drive setting is low Before calling this function the count source must be enabled and stable Refer R_ CGC_Set and R_CGC_Control for count source and stabilization time configuration e This function is called to use RTC after setting option PDL_CGC_RTC_TO_BE_USED in R_CGC_Control at cold start e This function is not required when using 48 pin package RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void alarm_function void void func void Configure the clock for an alarm at 12 noon every day Using default 24 hour mode R_RTC_Create PDL_RTC_ALARM_HOUR_ENABLE PDL_RTC_ALARM_MINUTE_ENABLE PDL_RTC_ALARM_SECOND_ENABLE OxFF114200 Automatic day of week 11 42 00 0Ox20100916 16 Sep 2010 PDL
441. t the DMAC e The Suspend Enable and Start control is executed at the end of the function If a channel has completed a transfer parameters may be changed and the channel re enabled in one function call RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 128 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h include lt string h gt const char source_string_1 Renesas RX220 volatile char destination string 1 ai iset eu neea ead tea wie were gt void func void Re enable transfers on channel 2 R_DMAC_Control 2 DL_DMAC_ENABLE DL_NO_PTR DL_NO_PTR DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA P P P P P P P P Reload and trigger channel 1 R_DMAC_Control 1 PDL _DMAC_ENABLE PDL_DMAC_ START PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE_ DESTINATION PDL_DMAC_UPDATE_COUN PDL_DMAC_UPDATE_SIZE source_string_l destination_string_l 1 uintl6_t strlen source_string_1l PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R01US0059EG0111 Rev 1 11 Page 129 of 429 Aug 01 2014 RENESAS RX220 Group 4 R_DMAC GetStatus Synopsis Prototype Description Return value Category
442. tEN ESAS Page 270 of 429 Aug 01 2014 RX220 Group 5 Synopsis Prototype Description 4 Library Reference R_IIC_MasterReceive Read data from a slave device bool R_IIC_MasterReceive uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_t data5 Receive threshold void func Callback function uint8_t data6 Interrupt priority level Read data over an 12C channel and store it data1 Select channel llCn where n 0 data2 Configure the channel The default setting is shown in bold Specify PDL_NO_DATA to use the defaults e Slave address size override Specify this option if 10 bit address mode is to be PDL_IIC_10_BIT_SLAVE_ ADDRESS used instead of 7 bit mode when the slave address is lt FFh e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE received data3 The address of the slave device data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data data5 The number of bytes that must be received before the function completes or the call
443. t_RPDL c also contains handlers for the peripherals that are not supported by RPDL This allows the user to add handler code for these peripherals while supporting the Fast Interrupt feature see R_INTC_CreateFastInterrupt R01US0059EG0111 Rev 1 11 Page 7 of 429 Aug 01 2014 RENESAS RX220 Group 1 Introduction 8 Avoid conflicts with standard project files If the files intprg c or vecttbl c are included in the project remove or exclude them a Removal Use the key sequence Alt P R to open the Remove Project Files window Select the files and click on Remove Remove Project Files Project files Interrupt_CMT c C workspace A C Workspaces Cancel C Workspace C Wworkspace C tenere J C workspace C workspace C Workspace Remove All C workspace C workspace C Workspace C workspace C Workspace C Workspace tpdl_lib_test c sbrk c R01US0059EG0111 Rev 1 11 Page 8 of 429 Aug 01 2014 RENESAS RX220 Group b Exclusion Select the two files and use the key sequence Alt B to exclude them 3 rpdl_lib_test High performance Embedded Workshop SEE File Edit View Project Build Debug Setup Tools Test Window Help D ngs reju lal ANa A jome n 8 2 7 REHE E E E a Eh P ee xi QE pdl_lib_test rpdi_lib_test H E C source file dbsct c E Interrupt_4DC_12 c Interrupt_BSC c Interrupt_CAC c Interrupt_CMT c Int
444. t_count PDL_NO_DATA Periodic PDL_NO_DATA Alarm_count L_NO_DATA Alarm_mask L_NO_FUNC Alarm handler L_NO_DATA Alarm priority L_NO_FUNC Periodic Handler R01US0059EG0111 Rev 1 11 Page 353 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples PDL_NO_DATA Periodic pricrity while 1 R_RTC_ReadBinary amp flags amp count amp alarm amp r_mask Figure 26 Example of configuration CGC and RTC counting by sub clock Both RTC count source and System clock in Binary count mode R01US0059EG0111 Rev 1 11 Page 354 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 16 2 Initialization in case of RTC is not used 1 Initialize RTC with providing sub clock use case sub clock is available Figure 27 shows an example of initialization in case of RTC is not used and sub clock is available PDL functions include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h void main void Prepare the LOCO settings R_CGC_Set PDL_CGC_CLK_LOCO DL_NO_DATA 25E3 25E3 D 2 2 D f figure the HOCO settings R_CGC_Set L_CGC_CLK_HOCO L_CGC_HOCO_50000 6 6 6 6 D D 01 5 DL_NO_DATA 5 5 D WNN UNH oO td td L_NO_DAT Prepare the Sub clock settings R_CGC_Set PDL_CGC_CLK_SUB
445. ta is to be received or if the DMAC or DTC shall be used to handle the data transfer data5 The number of times that the command sequence will be executed The value should not be zero if the DMAC and DTC trigger are disabled func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Transfer method Parameter Pollin PDL_NO_FUNC This function will handle the data transfer until 9 completion or an error occurs The function to be called when the transfer has completed or an error has Interrupts occurred DMAC or DTC The function to be called if an error has occurred or when the DMAC or DTC passes on the transfer interrupt data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create R01US0059EG0111 Rev 1 11 REN ESAS Page 287 of 429 Aug 01 2014 RX220 Group Remarks data3 in R_SPI_Create e If a callback function is specified and DMAC DTC control is not used interrupts are used to handle the data transfer Please see the notes on callback function usage in 6 e When using transmit only in slave mode return of the function by using polling or trigger of interrupt by using interrupt or
446. ta3 Clock frequency double data4 System clock frequency double data5 Peripheral module clock D frequency double data6 Peripheral module clock B frequency double data7 Flash interface clock frequency uint16_t data8 Sub clock stabilization time Set a clock source frequencies and options data1 Clock source selection e Clock source selection PDL_CGC_CLK_LOCO or Select the low speed on chip oscillator LOCO PDL_CGC_CLK_HOCO or high speed on chip oscillator HOCO PDL_CGC_CLK_MAIN or main clock oscillator PDL_CGC_CLK_SUB_CLOCK or sub clock oscillator or WDT dedicated low speed PDL_CGC_CLK_IWDTLOCO clock on chip oscillator IWDTLOCO data2 Configuration settings Options which are applicable only when the HOCO is selected in parameter data1 e High speed on chip oscillator frequency selection PDL_CGC_HOCO_32000 or PDL_CGC_HOCO_ 36864 or Select the HOCO frequency PDL_CGC_HOCO_40000 or 32 0 36 864 40 0 or 50 0 MHz PDL_CGC_HOCO_ 50000 Options which are applicable only when the Main clock oscillator is selected in parameter data1 e Main clock oscillator type PDL_CGC_MAIN_RESONATOR or PDL_CGC_MAIN_EXTERNAL Select the oscillator type e Main clock oscillator drive type PDL_CGC_MAIN_CERAMIC_LEAD_16_20 Adjust the drive level when a 16 to 20 MHz lead type ceramic resonator is used e Sub clock oscillator drive ability select only once w
447. tart of the next frame Ignored in Slave mode True if all parameters are valid otherwise false SPI RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 289 of 429 RX220 Group 4 Library Reference Reference R_SPI Create Remarks e Ifa channel is disabled using PDL_SPI_DISABLE call R_SPI_ Create to resume channel operations Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Enable direct loopback mode R_SPI Control 0 PDL_SPI_LOOPBACK_DIRECT PDL_NO_DATA Change the extended timings R_SPI_Control 0 PDL_NO_DATA PDL_SPI_CLOCK_DELAY_8 PDL_SPI_SSL_DELAY_5 R01US0059EG0111 Rev 1 11 Page 290 of 429 Aug 01 2014 RENESAS RX220 Group 7 Synopsis Prototype Description Return value Category Reference Remarks Program example R01US0059EG0111 Aug 01 2014 Rev 1 11 4 Library Reference R_SPI_GetStatus Check the status of an SPI channel bool R_SPI_GetStatus uint8_t data1 Channel selection uinti6 _t data2 Status flags uint16_t data3 Sequence count Acquires the SPI channel status data1 Select channel SPIn where n 0 only data2 The status flags shall be stored in t
448. tatic void NMI_handler void uintl6_t status 0 Read the status of IWDT if false R_IWDT_Read amp status R01US0059EG0111 Rev 1 11 Page 368 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples while 1 switch BIT_MASK_REFEF_UNDFF amp status case 0x4000 Turn on LED1 to represent underflow error R_IO_PORT_Modify PDL_IO_PORT_1_5 PDL_IO_PORT_XOR 1 break default Error while 1 NMI callback function should not return It should stop operation or reset the system while 1 Figure 31 Example of Independent Watchdog Timer use R01US0059EG0111 Rev 1 11 Page 369 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 Serial Communication Interface 5 18 1 SCI Asynchronous Using Polling This shows the setting of SCI channel 1 and the transmission and reception of data using polling Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_sci h PDL device specific definitions include r_pdl_definitions h volatile uint8_t rx_buffer 5 void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Pleas refer to 5 1 Clock Generation Circuit Set pin options R_SCI_Set 1 PDL_SCI_PIN_SCI1_RXD1_P30 PDL_SCI_PIN_SCI1_TXD1_P26 Set up SCI channel 1 Async 8N1
449. tatus Change 0 0 VCC lt Vdet2 0 0 VCC lt Vdet1 1 VCC 2 Vdet2 0 None 1 VCC Vdet1 0 None or the monitor is 1 Detected or the monitor is 1 Detected disabled disabled Return value True Category LVD Reference R_LVD_Control R_LVD_Create Remarks e Use R_LVD_ Control to clear the detection flags e Adetection flag is not valid if Monitor only operation was selected in R_LVD_Create RPDL definitions include r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t StatusFlags Read the LVD status R_LVD_Get Status amp StatusFlags R01US0059EG0111 Aug 01 2014 Rev 1 11 RX220 Group 4 2 7 1 4 Library Reference Clock Frequency Accuracy Measurement Circuit R_CAC_Create Synopsis Configure the clock accuracy circuit Prototype bool R_CAC_Creaie uint32_t data1 uint8_t data2 double data3 uint16_t data4 uint16_t datad Signal selection External input timing Upper limit value Lower limit value void funct Callback function uint8_t data6 Interrupt priority level void func2 Callback function uint8_t data7 Interrupt priority level void func3 Callback function uint8_t data8 Description 1 2 R01US0059EG0111 Aug 01 2014 data1 Interrupt priority level External input configuration Configure the operation of the C
450. tcveived a eaten tededlec cilia hued 4 e desided a E E dc Gi ev aes ead 30 2 14 Data Transfer Controller Driver ccccceccececeeeeeeeeeeeeeeeeeeeeeceaeeeeaaeeeeeeeseaeeeseaeeseaaeseneeeseaeessaeeeeeeseeeees 31 2 15 Event Link COMTOR a talon citation aad a a ate 32 2 16 Multi Function Timer Pulse Unit Driver assine kan etait eA ESE REA E AAEN ENERE EKRAAN ERSEN REEE RAEN EKE 33 2 17 Port Output Enable Driver senicure edain ieai iiid aiiai 34 2418 8 Dt imer DIVE hara ted rosy ea e tae va gyed ace pads ous uated acu d aa aaa a ada A ni 35 2 19 Compare Match Timer Driver 0 ccceccceceeceeceeeeeaeeeeeeeeeeeee seas eeeaaeeeeeeeeeaeeeeaaeeseaaeseneeeseaeeesaeeseaeeeneeeess 36 2 20 Real time ClOCK Diver moi einga vd Bela cee adie vce Dida a Be a A udev valacn a Bede ees 37 2 21 Independent Watchdog Timer Driver eeeeecceeeeeneeeeeeneeeteeaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeseeaeeeeeeaas 38 2 22 Serial Communication Interface Driver ceccccccseeesceceeeeeceeeeeeeeeeeeeeceeeeesaaeeeeeaeseeeeeseaeeesaeeseeeeeneeess 39 2 235 G Bus Interface Driver uth acc ecannti etn A Au ee a tee tee iA 40 2 24 Serial Peripheral Interface Driver cceccceccceeeeseeceneeeeeeeecaeeeeaaeseeeeeceaeeesaaeeeeaaeseeeeeseaeeesaeeteaeeseeeeess 41 2 25 CRC CGalc lator DIVET arran aaa a a a a a a a aa 42 2 26 12 bit Analog to Digital Converter Driver cccccceceececeeeeeeeeeeeeeeeeeeeceaeeeeaaaeseeeeeseeeeee
451. te is written out by R_SCI_IIC_Read function and last one when we use R_SCI_IIC_ReadLastByte R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_FIXED PDL_DTC_SIZ PDL _DTC_IRQ_ COMPLETE PDL_DTC_TRIGGER_TXI9 dtc_iicl_tx_transfer_data amp IIC_Dummy_value Source uint8_t amp SCI9 TDR Destination 3y Data length PDL_NO_DATA Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Start the IIC Read R_SCI_IIC_Read CHANNEL SCI_IIC PDL_SCI_IIC_RESTART PDL_SCI_1IIC_DTC_TRIGGER_ SLAVE_ADDRESS PDL_NO_DATA No data length as using DTC PDL_NO_DATA No buffer as using DTC CallbackRx Wait for rx while data_received false Because using DMAC need to manually get the last byte R01US0059EG0111 Rev 1 11 Page 389 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples This will also generate the stop condition R_SCI_IIC_ReadLastByte CHANNEL_SCI_IIC amp IlIC_Buffer 4 i Callback function for Rx static void CallbackRx void data_received true Figure 42 Example of SCI in IIC mode using DTC R01US0059EG0111 Rev 1 11 Page 390 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 19 IPC Bus Interface I
452. ted before using this function e If using the digital filter the LOCO clock must be enabled see R_CGC_Set e Disable the digital filter circuit when using Comparator A interrupt to return from software standby mode e Use R_CPA_GetStatus to determine the interrupt cause Do not select PDL_CPA_NEGATION_AFTER_RESET if a transition to software standby is to be made e Must call R_INTC_CreateExtlnterrupt PDL_INTC_LVDi_ENABLE to enable the NMI before set PDL_CPA_INTERRUPT_NONMASKABLE Note Comparator Non Interrupt Callback function is created by this call e Set PDL_CPA_NEGATION_AFTER_RESET under the LOCO in operating The LVDi reset or LVDi non maskable interrupt should not be generated during flash memory programming erasure e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 To enable the CPA event link output function enable the CPA first then enable the CPA event link function at the ELC To disable this function disable the CPA event link function at the ELC first then disable the CPA Program example RO1US0059EG0111 Aug 01 2014 RPDL definitions include r_pdl_cpa h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void CPAi_handler void void NMI_handler_cpa void void func void Configure the NMI pin R_INTC_CreateExtInterrupt PDL
453. tegory Indicates the category of the API function Reference Indicates the API functions to be referred Remark Describes notes to use the API function Program example Represents how to use the API function by a program example Two examples of return value checking are shown below RPDL definitions include r_pdl_mpc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void bool result Write OxFF to register MPC1 result R_MPC_Write 1 OxFF i if result false Handle th rror here Keep trying to send a string if the channel is busy do result R_SCI_Send 2 Renesas RX NULL PDL_NO_FUNC whil result false For clarity the return value is not checked in the examples used in this manual The RPDL API is implemented using function macros To avoid the possibility of parameters being evaluated more than once do not use operators or function calls within the RPDL API parameter list R01US0059EG0111 Rev 1 11 Page 50 of 429 Aug 01 2014 RENESAS RX220 Group 4 2 1 1 4 Library Reference Clock Generation Circuit R_CGC_Set Synopsis Prototype Description 1 2 RO1US0059EG0111 Aug 01 2014 Configure the clock generation circuit bool R_CGC_Set uint8_t data1 Clock selection uint32_t data2 Configuration options double da
454. that are not required eee ee eeeeeeeeeeeeeeeeeeeeaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeseeaeeeeeeaas 7 7 Peripherals that are not supported by RPDL ce ecceee cence eeeeeeeeeeeeaeeeeeeaaeeeeeeaaeeeeeeaaeeeeeeaeeeeeeaas 7 8 Avoid conflicts with standard project files 22 0 0 eececcceceeeeeceeeeeeaeeeeeeeeeeeeecaaeeeeaaeseeeeesaeeesaeeeeneeseneeess 8 QO Set the build Opts na a a EO a I A a E En E E a aan eal 10 10 Build theproject an a a e ea A E a E E S aR 12 11 Using library with debug information ccecceceeeeeee ee eeeeeeeeeeeeeeeeceaeeeeaaeeeeaaeseeeeeseaeeesaeseeaeeeeeeeess 13 3 37 Header file INGlUuSiOni s c3 c sake lbs eens aa a Ae dene aie ais a aa A a eats adel 14 1 3 4 Header file order isscs cesesec ccs oith ccateced cavackscavaiahd neavivadcevoathexcedived cds odahd seadivadacneduhecestegel caveishd ceavevadgaherth 14 1 3 5 Recommended initialisation code ce eececeeeeeteeeeeeene eter ene ee eee aeee ee eaeeeeeeaeeeeeeaeeeeetaeeeeeeaeeeen 15 1 initialisation of pins that are not available eee cece eeeeeeeeeee eee eeeeaeeeeaeeseeeeesaeeesaeeseaeeeeeeeess 15 2 initialisation of the sub clock oscillator if NOt USCC ceceeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeaeeesaeeeeaaeseneeeeaas 15 124 Document Structures i iscsi sti aut steened eee Als EA AERES REETA ied E EERS TS 16 1 5 List of Abbreviations and ACrONYMS ccccecceeeeeeneeeeeeeeeeeee cae eeeaaeeeeeeeseeeeeeeaeee
455. that no other interrupt can be processed until the callback function has completed RO1USOO59EG0111 Rev 1 11 Page 193 of 429 Aug 01 2014 2 ENESAS RX220 Group Program example 4 Library Reference RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure pin TMO1 for 500ns period 200ns pulse width R_TMR_CreatePeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD PDL_TMR_OUTPUT_HIGH 500E 9 200E 9 PDL_NO_FUNC PDL_NO_FUNC 0 Configure pin TMO1 for 5MHz frequency 60 duty cycle R_TMR_CreatePeriodic PDL_TMR_TM R1 PDL_TMR_FREQUENCY PDL_TMR_OUTPUT_HIGH 5E6 60 PDL_NO_FUNC PDL_NO_FUNC 0 R01US0059EG0111 Rev 1 11 R Page 194 of 429 Aug 01 2014 sKENESAS RX220 Group 5 Synopsis Prototype Description Return value 4 Library Reference R_TMR_CreateOneShot Configure and use a one shot timer bool R_TMR_CreateOneShot uint8_t data1 8 bit channel or 16 bit unit timer selection uint32_t data2 Configuration selection double data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a TMR timer channel or unit for one shot operation and start the timer data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or P
456. the I2 C bus channels 22 Serial Peripheral Interface These driver functions are used for controlling the SPI channels 23 CRC calculator These driver functions are used for controlling the calculator 24 12 bit Analog to Digital Converter These driver functions are used for configuring the 12 bit ADC units controlling the units and reading the conversion results 25 Comparator A These driver functions are used for configuring the Comparator A module 26 Data Operation Circuit These driver functions are used for configuring the Data Operation Circuit module R01US0059EG0111 Rev 1 11 Page 19 of 429 Aug 01 2014 RENESAS RX220 Group 2 Driver 2 3 Clock Generation Circuit Driver The driver functions support the control of the internal clock generator providing the following operations 1 Configuration of the multiple clock outputs for system peripheral operation 2 Controlling the clock generator operation 3 Reading the Clock generator status flags Note Configuring the Clock Generation Circuit also provides information on clock frequencies that will be used by the integrated drivers for other peripherals R01US0059EG0111 Rev 1 11 Page 20 of 429 Aug 01 2014 RENESAS RX220 Group 2 4 Interrupt Control Driver 2 Driver The driver functions support the use of the interrupt controller providing the following operations Ais 2 10 Modifying an interrupt register Selecting the ap
457. the register is not selected TGRF_value For n 0 The general register TGRF value This will be ignored if the register is not selected TADCOBRA_value For n 4 ADC start request cycle set buffer A This will be ignored if the register is not selected TADCOBRB_ value For n 4 ADC start request cycle set buffer B This will be ignored if the register is not selected True if the channel number is valid otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_Create R_MTU2_ControlUnit Remarks Before calling this function use R_ MTU2_Create to configure the channel operation e Either this function or R MTU2_ControlUnit must be used to start the timers e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call e If noise filter is enabled before starting the timer make sure at least 2 cycles of the selected noise filter clock has elapsed after the timer configuration use R_MTU2_Create RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 166 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU2_ControlChannel_structure ch3_p
458. the required number of bytes has been sent Interrupts The function to be called when the last byte has been sent Either the function to be called when each byte is sent or PDL_NO_FUNC Polling DMAC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data5 The start address of the storage area for the expected data Specify PDL_NO_PTR if not receiving data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data Rev 1 11 REN ESAS Page 251 of 429 RX220 Group Description 2 2 4 Library Reference func2 Receive callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference Remarks RO1US0059EG0111 Aug 01 2014 Transfer Parameter method Polling PDL_NO_FUNC This function will continue until the required number of bytes has been received The function to be called when the number of received bytes reaches the nterrupts threshold number Either the function to be called when each byte is received or DMAC PDL_NO_FUNC if the callback function specified in R DMAC_ Create will be used DTC The function to be called at the interval specified in R_DTC_Create func3 The function to be called if a recei
459. therwise false If this function is not called from the R_IIC_SlaveMonitor callback function it will complete when a stop condition is detected Category 2C Reference R_IIC_SlaveMonitor Remarks e Use this function after using R_IIC_SlaveMonitor and detecting that a slave transmission is required e If a callback function was specified in the call to R_IIC_SlaveMonitor then this transfer shall be completed using interrupts and the callback function shall be called when the transfer ends If a callback function was not specified in the call to R_IIC_SlaveMonitor then this function will not return until the transfer has ended lf the master requires more data than is supplied this function shall loop back to the start of the data Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Assign 5 bytes to be read by a master on channel 0 R_IIC_SlaveSend 0 data_array 5 R01US0059EG0111 Rev 1 11 ztEN ESAS Page 276 of 429 Aug 01 2014 RX220 Group 4 Library Reference 9 Synopsis Prototype Description Return value Category Reference Remarks Program example R_IIC_Control l2C channel control bool R_IIC_Conitro
460. ti Processor mode R01US0059EG0111 Rev 1 11 Page 380 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 18 7 SCI Transmission in Asynchronous Multi Processor mode This shows the setting of SCI channel 9 and the Multi Processor mode transmission of data using interrupts and polling PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h void SCItx void uint8_t send_data0 Welcome to the Renesas RX220 n r uint8_t send_data testing ASYNC MP mode bool tx_end volatile bool g_SwitchlPressed static void SWl_handler void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Pleas refer to 5 1 Clock Generation Circuit Set Channel 9 pin options R_SCI_Set 9 PDL_SCI_PIN_SCI9_RXD9_PB6 PDL_SCI_PIN_SCI9_TXD9_PB7 Configure the R5232 port specify Async MP mode R_SCI_Create 9 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 9600 15 es TE a Async MP mode data Transmission by CPU ISR 7 Ej NOTE The receiving side must be ready before this ID is transmitted Send Target Station ID 0x0A by internal polling R_SCI_Send 9 0x0A00 PDL_SCI_MP_ID_CYCLI PDL_NO_PTR 0 PDL_NO_FUNC Fi tx_end false Send data to Target
461. tion call R CGC_Set for each clock that will be measured or used as a reference e lf both edges are selected the clock duty cycle is assumed to be 50 e f a frequency error callback function is specified then it must clear the error flag using R_CAC_ Control to prevent continuous interrupts callbacks e Ifa measurement complete callback function is specified then it must clear the measurement flag e ifan using R_CAC_Control to prevent continuous interrupts callbacks overflow callback function is specified then it must clear the overflow flag using R_CAC_Control to prevent continuous interrupts callbacks RPDI L definitions include r_pdl_cac h RPDI L device specific definitions include r_pdl_definitions h Callback functions void CAC_frequency_error void void CAC_measurement_complete void void CAC_overflow void void func void R_CAC_Create Rev 1 11 Use the main clock to check the LOCO accuracy PDL_CAC_REFERENCE_MAIN PDL_CAC_REFERENCE_RISING PDL_CAC_REFERENCE_DIV_8192 PDL_CAC_MEASURE_LOCO PDL_CAC_MEASURE_DIV_1 PDL_CAC_LIMIT_TOLERANCE PDL_NO_DATA PDL_NO_DATA 10 10 CAC_frequency_error 15 CAC_measurement_complete 6 CAC_overflow 10 RENES S Page 104 of 429 RX220 Group 4 Library Reference 2 Synopsis
462. tion prototypes static void SWl_handler void static void SW2_handler void static void SW3_handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Select the pins for SW1 SW2 and SW3 R_INTC_SetExtInterrupt PDL_INTC_IRQ1_P31 PDL_INTC_IRQ3_P33 PDL_INTC_IRO4 P34 Configure the SW1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ1 PDL_INTC_FALLING SWl_handler 7 Configure the SW2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ3 PDL_INTC_FILTER_DIV_32 PDL_INTC_FALLING SW2_handler 7 Configure the SW3 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ4 PDL_INTC_LOW SW3_handler 7 while 1 static void SW1l_handler void uint8_t irq status 0u R_INTC_GetExtInterruptStatus PDL_INTC_IRQI1 amp irg_status R01US0059EG0111 Rev 1 11 Page 319 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Falling edge detected if irg_status amp 0x0C 0x04 Disable and invert th dge interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRQI1 PDL_INTC_RISING PDL_INTC_DISABLE else if irq status amp 0x0C 0x08 Disable and invert th dge interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 L_INTC_FALLING PDL_INTC_DISABLI Figure
463. tion used to change to read from that memory location in the EEPROM Slave address Memory address Slave address PR A Pen Figure 46 The bus activity showing the Repeated Start condition when switching to the Read process Send 1 byte to the EEPROM to update the EEPROM sub address bits and do not stop R_IIC_MasterSend 0 f PDL_IIC_STOP_DISABLE EEPROM_ADDRESS eprom_data_array_l e 1 PDL_NO_FUNC 0 Read data from the EEPROM A repeated start will occur R_IIC_MasterReceive 0 r DL_NO_DATA EPROM_ADDRESS ta_storage L_NO_FUNC Figure 47 Set the EEPROM sub address and then read 2 bytes R01US0059EG0111 Rev 1 11 Page 393 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 19 2 Master mode with DMAC In the following example data is written to an EEPROM in two bursts DMAC channel 3 is used to handle the data transfer The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer PDL functions include r_pdl_cgc h include r_pdl_iic h include r_pdl_cmt h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void void iic_rx_dmac_end_handler void define EEPRO
464. tions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set all reserved I O port pins to the recommended state R_IO_PORT_NotAvailable RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 87 of 429 RX220 Group 4 Library Reference 4 2 4 Multifunction Pin Controller The peripheral functions can be assigned to different pins controlled by the Multifunction Pin Controller The definitions available to the MPC functions are listed below MPC register definitions PDL_MPC_REG_P07PFS PDL_MPC_REG_PBOPFS PDL_MPC_REG_P12PFS PDL_MPC_REG_PB1PFS PDL_MPC_REG_P13PFS PDL_MPC_REG_PB2PFS PDL_MPC_REG_P14PFS PDL_MPC_REG_PB3PFS PDL_MPC_REG_P15PFS PDL_MPC_REG_PB4PFS PDL_MPC_REG_P16PFS PDL_MPC_REG_PB5PFS PDL_MPC_REG_P17PFS PDL_MPC_REG_PB6PFS PDL_MPC_REG_P20PFS PDL_MPC_REG_PB7PFS PDL_MPC_REG_P21PFS PDL_MPC_REG_PCOPFS PDL_MPC_REG_P22PFS PDL_MPC_REG_PC1PFS PDL_MPC_REG_P23PFS PDL_MPC_REG_PC2PFS PDL_MPC_REG_P24PFS PDL_MPC_REG_P25PFS PDL_MPC_REG_PC3PFS PDL_MPC_REG_PC4PFS PDL_MPC_REG_P26PFS PDL_MPC_REG_PC5PFS PDL_MPC_REG_P27PFS PDL_MPC_REG_PC6PFS PDL_MPC_REG_P30PFS PDL_MPC_REG_PC7PFS PDL_MPC_REG_P31PFS PDL_MPC_REG_P32PFS PDL_MPC_REG_PDOPFS PDL_MPC_REG_PD1PFS PDL_MPC_REG_P33PFS PDL_MPC_REG_PD2PFS PDL_MPC_REG_
465. tions The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SCI_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_SCI_DTC_TRIGGER_ENABLE received Continuous receive mode valid only in asychronuous mode PDL_SCI_RX_CONTINUOUS DISABLE or Disable or enable continuous receive when PDL_SCI_RX_CONTINUOUS_ENABLE an interrupt is used as the receive method e ID reception control valid only in Multi processor mode Use the upper byte as the station ID ERE SCL es ca The valid ID range is 0 to 255 data3 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data or for ID cycle in Multi processor mode data4 The number of bytes that must be received before the function completes or the callback function is called Specify 0 for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Transter Parameter method Polling PDL_NO_FUNC This function will continue until the required number of bytes has been recei
466. tivation trigger or pass it on to the CPU e DTC trigger control PDL_DMAC_DTC_TRIGGER_DISABLE or PDL_DMAC_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when an event specified in the Interrupt generation options occurs data3 Select one activation source for channel DMAn e Trigger selection Name Trigger cause PDL_DMAC_TRIGGER SW or By software PDL_DMAC_TRIGGER_CMT0 or PDL_DMAC_TRIGGER_CMT1 or PDL_DMAC_TRIGGER_CMT2 or PDL_DMAC_TRIGGER CMT or Compare match on channel CMTn n 0 to 3 PDL_DMAC_ TRIGGER SPIO RX or Receive buffer full on RSPI channel 0 PDL_DMAC_TRIGGER_SPI0_TX or Transmit buffer empty on RSPI channel 0 PDL_DMAC_TRIGGER_IRQO or PDL_DMAC_TRIGGER_IRQ1 or PDL_DMAC_TRIGGER_IRQ2 or PDL_DMAC_TRIGGER_IRQ3 or Valid edge detected on pin IRQn n 0 to 3 PDL_DMAC_TRIGGER_ADC12 or Conversion completed on the 12 bit ADC unit PDL_DMAC_TRIGGER_ADC12_GBADI or Conversion completed on group B of the 12 bit ADC unit PDL_DMAC_TRIGGER_ELSR18l or Event link interrupt PDL_DMAC_TRIGGER MTUO or PDL_DMAC_ TRIGGER MTU1 or PDL_DMAC_TRIGGER_MTU2 or PDL_DMAC_ TRIGGER MTU or PDL_DMAC_ TRIGGER MTU4 or Input capture or compare match on MTU channel n n 0 to 4 PDL_DMAC TRIGGER SCI1_RX or PDL_DMAC_TRIGGER_SCI5_RX or
467. to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety
468. totype bool R_MCU_GetStatus uint16_t data1 The location where the mode status flags shall be stored uinti6_t data2 The location where the reset status flags shall be stored uint32_t data3 The storage location for the Option Function Select Register 0 uint32_t data4 The storage location for the Option Function Select Register 1 J Description Read the status registers for the MCU data1 The status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required b15 b14 b13 b12 b9 b8 User boot mode 0 0 Other 0 1 1 Selected b7 b5 b4 b1 bO Endian mode in level at release from reset 000b Big 0 0 Low 111b Little 1 High data2 The reset status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required b15 b9 b8 Start type 0 0 Cold 1 Warm b7 b6 b5 b4 b3 b2 b1 bO Reset detection flags 0 Software 0 IWDT voltage montor 0 Power on 0 Not detected 1 detected data3 Where the OFSO register contents shall be stored Please refer to the MCU hardware manual for the format Specify PDL_NO_PTR if they are not required data4 Where the OFS1 register contents shall be stored Please refer to the MCU hardware manual for the format Specify PDL_NO_PTR if they are not required Return value True Category MCU registers
469. true Is the master starting a read Check this by seeing if in transmit mode else if 0 status_flags amp BIT_6 Send data to master based on current address R_IIC_SlaveSend SLAVE_CHANNEL amp data_storage data_storage_index uintl6_t STORAGE_SIZE data_storage_index Don t start monitoring again until the R_IIC_SlaveSend completes bStartMonitor false if true bStartMonitor Continue monitoring R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_NO_DATA Rx_Buffer RX_BUFFER_SIZE slave_callback 7 The master has sent us data now in the Rx_Buffer store it in the data_storage array static void StoreData uintl6_t count uintl6_t index 0 Update data_storage_index data_storage_index Rx_Buffer index count index R01US0059EG0111 Rev 1 11 Page 404 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples Store any data while count 0 data_storage data_storage_index Rx_Buffer index count index data_storage_indext if data_storage_index STORAGE_ Wrap around data_storage_index Figure 50 Virtual IIC Slave memory R01US0059EG0111 Rev 1 11 Page 405 of 429 Aug 01 2014 RENESAS RX220 Group 5 Usage Examples 5 20 Serial Peripheral Interface 5 20 1 Synchronous transfer with 32 bit data This is an example of Serial Peri
470. ttings are shown in bold 4 Library Reference Output control for pin TMOy y 0 or 2 for n 0 or 1 PDL_TMR_OUTPUT_IGNORE_CM_A or PDL_TMR_OUTPUT_LOW_CM Aor PDL_TMR_OUTPUT_HIGH_CM_Aor PDL_TMR_OUTPUT_INV_CM_A No change if a compare match A occurs 0 is output if a compare match A occurs 1 is output if a compare match A occurs The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or PDL_TMR_OUTPUT_LOW_CM B or PDL TMR_OUTPUT_HIGH_CM B or PDL TMR _OUTPUT_INV_CM _B No change if a compare match B occurs 0 is output if a compare match B occurs 1 is output if a compare match B occurs The output toggles if a compare match B occurs data4 The 16 bit counter value data5 The 16 bit compare match A value data6 The 16 bit compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for all parameters func1 func2 and funcs True if all parameters are valid and exclusive otherwise false 2tENESAS RX220 Group Program example RO1US0059EG011
471. uation test for the given product Table of Contents IMthOGUCHION 2 028 A cvien etal ee eth ad See ta ee bad ed E E TOT 1 1 1 Tool chain requirements cece cceeceeecceeeeecceeeeeeeceeeenseceeeeseceeeenaecessnaeceeeenaeceeesnaeceeeeneeaeeseneeaeeeeneneeeeenanes 2 1 2 Compiler options when you use this product ceeeeeeneeceeeee cee eeeeaeeeeeeeeeaeeeeaaeeeeaeeseaeeesaeeseaeseeeeesaas 2 1 3 Using the library within your project cecceeeeeceeeeeeeeeeeeeee eae eeeeaeeeeaeeeeeeeeseaeseaaeedeaeeseeeesaeeeeaaeseeeeesaas 2 1 3 1 Via the PDG graphical utility sisie tasar ee eeeeeeee eens ee eeee este ae eeeeeeseeeeeseaeeeeeaeseeeeeseeeesaeeseaeeseeeees 2 1 3 2 Using RADE standalone ccsscceccs ace zectastocetacackcceueseccanesantgenhiaecesdestudccvteatcecdvsatt cenbastcectesdidcaetedecectesbs 2 1 Wnzipsthe RPD MeS riaa aat aa neers idan eed nats nasa ida Taaa ad MaRi 2 2 Copy the files into your project AF Ca eeececeeceeneeceeeeeeeeeeeaaeeeeeeeeeeeeeeaaeeeeaaeseaeeseeeeescaeeesaeeseneeseaees 3 3 Include the NOW directory oa eeececeeeecceeeeeeeeeeeeeeeeeeeaeeeeeeaeeeceeseneeseeeneeseeneneeseeseneeeeenenseseeneeseeeenenes 5 A Add the RPDE library fle sasescescentes sectas cvsaaceaasictus EAr ATN EEEE EON E VAR AF NEENA TATANA E OEKE TANER AEE AS S 6 5 Include the new source files oneesneesneeseeeseesnnesn nesr nesrnssrnsttnnnnnstnnstnnstnnstnnstnnsnennnensnennnnnnnnnnnnnnt 7 6 Peripherals
472. uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location uint16_t data6 A pointer to the data storage location uint16_t data7 A pointer to the data storage location uint16_t data8 A pointer to the data storage location uint16_t data9 A pointer to the data storage location Description 1 2 Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 5 data2 The status flags shall be stored in the format below The input capture compare match flags will be set to1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read Forn 0 b7 b6 b5 b4 b3 b2 bi bO Detection Count Overflow Input capture compare match direction 0 down V F E D C B A 1 up Forn 10r2 b7 b6 b5 b3 b2 bi bO Detection Count Underflow Overflow Input capture compare match _ direction 0 down U V 0 B A 1 up Forn 3 b7 b6 b5 b4 b3 b2 b1 bO i Detection Count Overflow Input capture compare match direction 0 down 0 V 0 D C B A 1 up Forn 4 b7 b6 b5 b4 b3 b2 b1 bO acon a cou underflow Input capture compare match direction 0 down 0 V 0 D C B A 1 up Forn 5 b7 b3 b2 b1 bO 7 Detection Input capture compare match 0 W V U R01US0059EG0111 Rev 1 11 REN ESAS Page 173 of 429 Aug 01 2014 RX220 Group Description 2
473. uintl6_t status2 Read the flags R_BSC_GetStatus amp statusl status2 i Rev 1 11 REN ESAS Page 121 of 429 RX220 Group 4 2 11 1 DMA Controller R_DMAC_Create Synopsis Configure the DMA controller Prototype bool R_DMAC_Create uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 Trigger selection void data4 Source start address void data5 Destination start address uint16_t data6 Transfer count uint16_t data7 Repeat or Block size int32_t data8 Address offset uint32_t data9 Source address extended repeat area uint32_t data10 Destination address extended repeat area void func Callback function uint8_t data11 Interrupt priority level Description 1 3 Set up a DMA channel R01US0059EG0111 Aug 01 2014 data1 The channel number n where n 0 to 3 data2 Configure the operation of channel DMAn If multiple selections are required use to separate each selection The default settings are shown in bold e Transfer mode selection PDL_DMAC_NORMAL or Normal or PDL_DMAC_REPEAT or Repeat or PDL_DMAC_BLOCK Block mode 4 Library Reference PDL_DMAC_SOURCE or PDL_DMAC_DESTINATION area This selection is optional If Repeat or Block mode is selected the source or destination side can be selected as the Repeat or Block e Address di
474. up 1 Introduction 5 Include the new source files 3 Use the key sequence Alt P A to open the Add files to project lt your project gt window Double click on the RPDL folder From the Files of type drop down list select C source file C Use the key sequence Cirl A to select all of the files as shown below Add files to project rpdl_lib_test Look in RPDL e cf Interrupt_A4DC_12 c Interrupt_DOC c E Interrupt_POE c Interrupt_BSC c Interrupt_ELC c Interrupt_RTC c Interrupt _CAC c E Interrupt_IIC c Interrupt _SCI c Interrupt _CMT c E Interrupt _INTC c Interrupt _SPI c Interrupt _CPA_LYD c Interrupt_MTU2 c Interrupt_TMR c B Interrupt_DMAC c Interrupt_not_RPDL c File name Interrupt ADC_12 c Interrupt_BSC c Intern Add Files of type Ic source file C v Cancel V Relative Path Hide Project Files Click on Add Click on OK to return to the main HEW window 6 Peripherals that are not required If a peripheral module is not required the interrupt handler file does not need to be included If the unused interrupts still require entries in the interrupt vector table edit the file Interrupt_not_RPDL c to uncomment the define for the unused peripherals For example define RPDL_ADC_12_not_used Becomes define RPDL_ADC_12_not_used The file Interrupt_INTC c must be included 7 Peripherals that are not supported by RPDL The file Interrupt_no
475. upt can be processed until the callback function has completed Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h Bus error handler void BusErrorFunc void void func void Enable illegal address detection and register a callback R_BSC_Create PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE BusErrorFunc 5 R01US0059EG0111 Rev 1 11 RX220 Group 4 Library Reference 3 R_BSC Conirol Synopsis Modify the Bus Controller operation Prototype bool R_BSC_Control uint8_t data Control options Description Control the BSC operation data Control the BSC operation e Error clearing PDL_BSC_ERROR_CLEAR Clear the bus error status registers e Disable bus error interrupt request PDL_BSC_DISABLE_BUSERR_IRQ Disable bus error interrupt requests Return value True Category Bus Controller Reference R_BSC_Create Remarks e This function can be called from the error handling function assigned in R_BSC_ Create e This function will clear the Interrupt Status Flag indirectly Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Clear the bus error signals R_BSC Control PDL_BS
476. urce that will be used New Call this function once to set the clock frequency for each clock source whether it is used as system clock or RTC count source gt Add remark a Because this can not be done if ROM Flash Program Erase mode is set or if a operating power mode transition is in progress this function will return false if this is detected b When RTC is not to be used call R CGC_Control with option PDL_CGC_RTC_NOT_USE after calling this function to configure the RTC count source 2tEN ESAS Revision History 1 RX220 Group Revision History Description c Make sure PCLKB clock frequency 2 RTC count source clock frequency d Sub clock oscillator is not available for 48 pin package Revise the Program example R_CGC_Control delete the options a High speed on chip oscillator frequency control b Main clock oscillator drive type 1 control c d R_CGC_Control add the option RTC initialization control R_CGC_Control Revise remarks Main clock oscillator drive type 2 control Sub clock oscillator drive control gt Delete remark If the sub clock is selected the Start type status flag will be set to warm see R_MCU_GetStatus gt Change description Old Use R_CGC_Set to configure a clock source before selecting it New Use R_CGC_Set to configure a clock source before calling this function gt Add remark a This function can not be used if ROM Flash Progr
477. urn value True if all parameters are valid and exclusive otherwise false Category LPC References R_LPC_Control R_CGC_Control R_CGC_Set Remarks e When operating power control mode switching is in progress do not call this function e When the ROM is in program or erase mode do not call this function e During the period from the time of WAIT instruction issuance for a sleep mode transition to return from sleep mode to normal operation do not call this function e Use R_CGC_Control to stop and start the clocks as required e When switching from normal power consumption mode to low power consumption mode call R_CGC_Set to change the clock settings before calling this function e When PDL_LPC_SLEEP_RETURN_SWITCH_HOCO is selected the frequencies of the internal clocks ICLK PCLKD PCLKB and FCLk must be no more than the selected clock source frequency 2 before a transition is made to sleep mode e The sleep mode return clock source switching function and clock source switching function by the ELC cannot be used at the same time e When HOCO is operating low speed operating mode 2 cannot be selected e When HOCO frequency is 32 36 864 or 40 MHz minimum waiting time is 180 cycles When the HOCO frequency is 50 MHz the minimum waiting time is 200 cycles e If PDL_LPC_SLEEP_RETURN_SWITCH_HOCO or PDL_LPC_SLEEP_RETURN_SWITCH_MAIN is selected when the CPU is restored from the sleep mode middle speed operating mode A will be automatical
478. ve error occurs Specify PDL_NO_FUNC to ignore errors In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_SCl_Control R_SCl_GetStatus The maximum number of characters to be received or transmitted is 65535 e Wait until a transmission on the same channel is complete before calling this function e If no error callback function func3 is specified the error flags are cleared automatically to allow the reception process to complete e Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed e In SPI master mode the slave s SS pin must be asserted before calling this function A general I O pin can be used for this see the I O Port API e If using the DMAC or DTC this module does not know when the transfer has ended Therefore when the transfer has completed the user must call the R_SCI_ Control function with options PDL_SCI_STOP_TX PDL_SCI_STOP_RX to manually disable the transmission reception as appropriate e If a callback function is specified and the interrupt priority level is zero this function will return false e If using this function to perform a full duplex transfer then the transfer mode for transmit and receive can be se
479. ved The function to be called when the number of received bytes reaches the threshold Interrupts number DMAC Either the function to be called when each byte is received or PDL_NO_FUNC if the callback function specified in R_DMAC_ Create will be used DTC The function to be called at the interval specified in R_DTC_Create func2 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors True if all parameters are valid and the operation completed false if a parameter was out of range RO1US0059EG0111 Aug 01 2014 Rev 1 11 REN ESAS Page 248 of 429 RX220 Group Category Reference Remarks RO1US0059EG0111 Aug 01 2014 4 Library Reference SCI R_SCI_Control R_SCl_GetStatus The maximum number of characters to be received is 65535 Wait until a transmission on the same channel is complete before calling this function If callback function func1 is specified reception interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the RXI flag will be used to manage the data reception If the SCI channel s control registers are directly modified by the user this function may lock up If no error callback function func2 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This means that no other
480. vice Prototype bool R_IIC_MasterSend uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_t data5 Data count void func Callback function uint8_t data6 Interrupt priority level Description 1 2 Transmit data on the specified channel data1 Select channel IICn where n 0 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Start Repeated Start condition control PDL_IIC_START_ENABLE or Choose whether or not to issue a Start or Repeated Start PDL_IIC_START_ DISABLE condition at the beginning of the transfer e Slave address size override Specify this option if 10 bit address mode is to be PDL_IIC_10_ BIT SLAVE_ADDRESS used instead of 7 bit mode when the slave address is lt FFh e Stop condition control PDL_IIC_STOP_ENABLE or Choose whether or not to issue a Stop condition at the end PDL_IIC_STOP_DISABLE of the transfer e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE transmitted data3 The address of the slave device Ignored if the Start condition is disabled data4 The start address of the data to be sent If the DMAC or DTC shall
481. vision PDL_SPI_DIV_1 or PDL_SPI_DIV_2or PDL_SPI_DIV_4or PDL _ SPI DIV 8 Use the bit rate specified for R_SPI_Create 1 2 4 or 8 Ignored in Slave mode e SSL assertion PDL_SPI_ASSERT_SSLO or PDL_SPI_LASSERT_SSL1 or PDL_SPI_ASSERT_SSL2 or PDL_SPI_LASSERT_SSL3 The SSL pin to be asserted during the frame transfer Ignored in Slave mode e SSL negation PDL_SPI_SSL_NEGATE or PDL_SPI_SSL_KEEP Negate or retain the SSL signal after the frame transfer Ignored in Slave mode Frame data length PDL_SPI_LENGTH_8 or PDL_SPI_LENGTH_9 or PDL_SPI_LENGTH_10 or PDL_SPI_LENGTH_11 or PDL_SPI_LENGTH_12 or PDL_SPI_LENGTH_13 or PDL_SPI_LENGTH_14 or PDL_SPI_LENGTH_15 or PDL_SPI_LENGTH_16 or PDL_SPI_LENGTH_20 or PDL_SPI_LENGTH_24 or PDL_SPI_LENGTH_32 The number of bits in the frame transfer If a buffer size of 64 bits was selected when R_SPI_Create was called the number of bits must not exceed 16 Data transfer format PDL_SPI_MSB_FIRST or PDL_SPI_LSB_FIRST Select least or most significant bit first 2tENESAS Page 285 of 429 RX220 Group 4 Library Reference Description 2 2 data4 Extended timing control If multiple selections are required use to separate each selection The default settings are shown in bold For Slave mode select PDL_NO_DATA e Extended timing selection PDL_SPI_CLOCK DELAY MINIMUM or Select the minimum or extende
482. void register access conflicts or invalid calls to the callback function use this method when changing any value e If the CMCNT register value is changed to the same value as the CMCOR register the CMCNT register will be set to 0 RO1US0059EG0111 Aug 01 2014 Rev 1 11 RENESAS Page 212 of 429 RX220 Group 4 Library Reference Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Change channel 2 to ims period R_CMT_Controli 2 PDL_CMT_STOP PDL_CMT_PERIOD PDL_CMT_START 1E 3 R01US0059EG0111 Rev 1 11 REN ESAS Page 213 of 429 Aug 01 2014 RX220 Group 4 Library Reference 5 Synopsis Prototype Description Return value Category Reference Remarks Program example R_CMT_Read Read CMT channel status and registers bool R_CMT_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Read and store the counter value and status flag data1 The channel number n where n 0 1 2 or 3 data2 The compare match status flag shall be stored in the following format Specify PDL_NO_PTR if the flag is not to be read b7 b1 bO 0 0 Idle 1 Compare match condition detected
483. xclusive OR PDL_IO_PORT_XOR data3 The value to be used for the modification e Fora port 0x00 OxFF e Forapin 0or1 Return value True if the parameters are valid otherwise false Category I O port References None Remarks e If an invalid port or pin is specified the operation of the function cannot be guaranteed Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Invert port pin P05 R_IO_PORT_Modify PDL_IO_PORT_0_5 PDL_IO_PORT_XOR als And the value port 5 with 0x55 R_IO_PORT_Modify PDL_IO_PORT_5 PDL _IO_PORT_AND 0x55 R01US0059EG0111 Rev 1 11 Page 85 of 429 Aug 01 2014 RENESAS RX220 Group 4 Library Reference 8 Synopsis Prototype Description Return value Category References Remarks Program example R_lIO_PORT_Wait Wait for a match on an I O port bool R_IO_PORT_Wait uint16_tdata1 Output port or port pin selection uint8_t data2 Comparison value Loop until an I O port or I O port pin matches the comparison value data1 Use either one of the following definition values from 4 2 3 e One port definition or e One port pin definition data2 The value to be compared with
484. y Reference R_lIO_PORT_ModifyControl Modify an I O port s control registers bool R_IO_PORT_ModifyConirol uint16_tdata1 Port or port pin selection uint8_tdata2 Control register and logical operation selection uint16_tdata3 Modification value Modifying the operation of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be modified and the logical operation using to separate the selections e The control register to be modified PDL_IO_PORT_DIRECTION or Data direction PDL_lIO_PORT_MODE or General or Peripheral I O mode control PDL_IO_PORT_TYPE or Open drain control PDL_IO_PORT_PULL_UP or Pull up control Drive capacity control POLIO PORT Dae Valid for ports 1 B and C e The logical operation to be applied to the control register PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_ PORT_XOR data3 The value to be used for the modification using one of the formats below Pin not PE1 open drain control b15 b1 bO Do not care Oor1 Pin PE1 open drain control b15 b2 b1 b0 Do not care 0to3 Port not open drain control b15 b8 b7 b0 Do not care Register Port open drain control b15 b8 b7 b0

RX220 Group Renesas Peripheral Driver Library User`s Manual

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