Using iMPACT with FPGA Modules
Contents
1. 21 In the Add Device File window click on the Add File button and select the top bit bit stream that will have been generated last time you ran the bit stream generation process When this process has run and you are asked if you would like to add another bit stream select No Next click on the Finish button and the MCS files will be created Additional CFI files will be created if you selected Xilinx Serial PROM with Design Revisioning Enabled earlier on Add Device File xi Data Stream 0 Starting Address Mas 8 Hex Digits fo How start adding device file s Add File Il ISE 5 x For this example we will assume that we want to program the Example1 bit stream into the PROM of the FPGA module 1 Start the Project Navigator 2 Select File gt Open Project To load the Examplel project go to the directory dir example1 ISE where dir is the local directory you copied the FPGA examples to and open the appropriate project file for the board type you are using 3 Check that CCLK has been selected for the start up clock this can be found in the Startup options tab of the Generate Programming File Process Properties window With this done you can then generate a rbt file by Generate Programming File gt Run 4 The next step is to start iMPACT which will be used to create the PROM file in the correct format This is done by double clicking on Genera2. Prepare PROM Files a B want to target a ilins PROM C Generic Parallel FROM PROM File Format f MCS TEK UFP C format C Exo C HEX C BN ISC Swap Bits Checksum Fill Value 2 Hex Digit FF PROM File Name Jexamplet Location asioi E xample 41S E Browse Back Cancel Help 9 In the next window for a xcf08p or xcfl6p PROM device select Enable Revisioning and add the PROM device on your module e g xcfl6p for an IO5 module Selecting Enable Revisioning will prompt iMPACT to also generate a CFI file For a xc18v04 PROM device select Auto Select PROM instead After you made your choice click Next Specify Xilinx PROM Device o x Auto Select PROM iW Enable Revisioning for xcfO8p or xctd Bp part Number of Revisions 1 F Enable Compression Select a PROM xofp kcr Ep Add Position Part Hame T cH bp Delete All Cancel Help Specify Xilinx PROM Device ge M Auto Select PROM lt for xc1 04 part Enable Reyisioning Humber of Revisions Enable Compression Select a PAO ct rcr Ep Add Position Part Hame Delete All Back Cancel Help 10 Click Next again in the following window File Generation Summary xi Tou have entered following information PROF Type Revision File Format mes Fill al
3. Properties Processes for Source bop rtl 0 Add Existing Source fF Create New Source ar Design Entry Utilities E User Constraints 4 03 Spnthesize X57 Hia Y Implement Design J E V Generate Programming File Programming File Generation Report m Generate PR M ACE or JTAG File m Configure Device IMPACT Bt Process View 16 If iMPACT is started up separately it will first ask what you want to do If iMPACT is started from within Project Navigator as described in step 4 above you will not see this window as you have already selected you choice by selecting Generate PROM ACE or JTAG File So if you started iMPACT separately select Prepare Configuration Files and click Next Operation Mode Selection what do vou want to do first Configure Devices Load Configuration File cdf pdr 17 The next window asks want you want to create Select PROM file and click Next Prepare Configuration Files want to create a System ACE file Boundary Scan file 18 In the next window select MCS for the PROM file format enter the name for the PROM file and check that the location is correct With ISE version 6 1 you might see that PROM File Name actually holds the location in that case move the PROM File Name contents to Location We used example for the file name For a xcf08p PROM device select Xilinx
4. 10 In the Add Device File window click on the Add File button and select the top bit bit stream that will have been generated last time you ran the bit stream generation process When this process has run and you are asked if you would like to add another bit stream select No Next click on the Finish button and the MCS file will be created Add Device File o abe a Data Stream i Starting Address Mas 8 Hex digit fo Mow start adding device file s Add File 13 ISE 4 2 For this example we will assume that we want to program the Example1 bit stream into the PROM of the FPGA module L pA Start the Project Navigator Select File gt Open Project To load the Examplel project go to the directory dir example1 ISE where dir is the local directory you copied the FPGA examples to and open the appropriate project file for the board type you are using Check that CCLK has been selected for the Start Up Clock this can be found in the Startup options tab of the Generate Programming File Process Properties window With this done you can then generate a rbt file by Generate Programming File gt Run The next thing is to start the PROM file formatter In ISE 4 2 the PROM file formatter starts correctly it creates a new pdr file for you if none was present yet New pdr files still need to be saved thus answer yes if asked if you want to sa
5. HERON FPGATI to 6 and HERON IO1 to 4 use xc18v04 7 PROM devices and HERON FPGA7 onwards and HERON IO5 onwards used xcf08p devices But this may well change in future so please make sure what PROM part is used on your HERON module Generating a PROM programming file The Flash Proms on HERON FPGA and HERON IO modules are programmed via the JTAG chain using a Xilinx Parallel Cable version II or IV but if you have an ES xcf08p part you can only use IV As part of your Xilinx tools there will be a utility called iMPACT that is used to program a device The iMPACT utility uses MCS files extension mcs and in some case CFI files extension cf1 Xilinx tools before 6 0 will only create MCS files Xilinx tools version 6 0 and later can optionally also create CFI files HERON modules with a xcl18v04 PROM part only use a MCS file HERON modules with a xcf08p PROM part also need a CFI file to have the PROM device programmed These files are generated by the Xilinx PROM File Formatter after the rbt file has been generated The sequence to generate the files is slightly different between ISE 6 x ISE 5 x ISE 4 2 and ISE 4 1 The following sections discuss how to generate the necessary files for each of the ISE design tools ISE 7 x For this example we will assume that we want to program the Examplel bit stream into the PROM of the FPGA module 1 Start Project Navigator 2 Selec
6. TOQ TOG Picture 1 On the left side you can see a xefO8p PROM part detected example FPGAS module On the right hand side you can see a xc18v04 PROM part detected example FPGA3 module If you have a xcf08p part verify whether you have an ES Engineering Sample If you find that ES is printed under or after the part name on the PROM device you have an Engineering Sample When using IMPACT in the bottom text window scroll up until you find Manufacturer s ID Xilinx xcf08p there s a version number listed here If it s 0 you have an Engineering Sample PROGRESS START Starting Operation Identifying cham contents T Wlarnitacturer s ID Xilmx xcilep Version 0 INFOuMIPACT LTT Reading Di olredxcfpidatalecilep bac INFOahvIPACT S01 1 Added Device xcilep successfully For Help press F1 Configuration Mode Boundary Scan Picture 2 An Engineering Sample ES xcf0Sp PROM part If you have a xcf08p Engineering Sample you must use Xilinx Parallel Cable IV ES parts will not work with Xilinx Parallel Cable III Also verify that your cable is set to run at 5 Mhz You can verify these settings at the status line towards the bottom of the IMPACT window Bal For Help press Fl Configuration Mode Boundary Scan Parallel I v Ipti 5 MHz vt Picture 3 WMPACT has detected a Xilinx Parallel IV cable running at 5 Mhz using parallel port 1 At the moment of writing
7. bit stream This document discusses the steps involved in configuring an application FPGA and in generating the correct MCS file and loading the contents of that file into the Flash PROM on the module you are using History Rev 1 0 First written Rev 1 1 Updated for ISE 6 x and new xcf08p PROM part Rev 1 2 Updated for ISE 7 x AUNT ENGINEERING is a trading style of HUNT ENGINEERING U K Ltd Co Reg No 3333633 Directors P Warnes amp N J Warnes Reg d office 34 amp 38 North St Bridgwater Somerset TA6 3YD VAT Reg d No GB 515 8449 31 Determine PROM part HUNT ENGINEERING HERON FPGA and HERON IO modules use several different PROM parts At the time of writing two different parts are used xcl8v04 and xcf08p The programming sequence is slightly different between these Therefore as a first step we must determine what PROM part is used on your module You can look on top of the PROM device on your HERON FPGA or HERON IO modules and verify what the PROM part is the user manual for your module will show where you can find its PROM part Alternatively you can start up IMPACT part of the Xilinx tools installation Select the default choices Configure Devices Boundary Scan Mode and Automatically connect to cable and identify Boundary Scan chain The JTAG chain will be shown together with all devices that were detected on the chain The part numbers are written below the devices TDI TDI
8. Serial PROM with Design Revisioning Enabled For a xc18v04 PROM device select Xilinx Serial PROM instead Selecting Xilinx Serial PROM with Design Revisioning Enabled will prompt iMPACT to also generate a CFI file After you made your choice click Next Prepare PROM Files E x want to target a Milne Serial PROM Parallel PROM Compress Data FROM File Format f MCS of TEK UFP C format C Exo C HEX C BN ISC Swap Bits Memory Fill Value 2 Hex Digit FF PROM File Marne Jexamplet Location Jd Mipgaav Vexamplel ise Browse lt Back Cancel Help Prepare PROM Files E x want to target a iling Serial PROM lt lt tor x1 8v04 part Parallel PROM C ilins PROM with Design Revisioning Enabled Compress Data PROM File Format f MCS TEK UFP T format C EXO C HEX C BN ISC Swap Bits Memory FillValue 2 Hex Digit FF PROM File Marne Jexamplet Location Jd Mtpgaav Vexamplel ises Browse lt Back Cancel Help 19 In the next window tick Auto Select PROM and click Next 10 Specify Xilinx PROM Device eS xi Select a BRTH fact ct 718d Add Position Part Hame Number of Revisions T Delete ll lt Back Cancel Help 20 Click Next again in the following window Click Nest to add device file lt Back Cancel Help
9. to boot from PROM when the board or PC is powered on Power up the PC if using a carrier board like HEPC8 or HEPC9 or the board if using a HEBASE 1 or later board In the case of example1 you should see LED 4 flashing For your own application it may be useful to write to an LED as well so that you can verify your application was loaded properly and has started Better use the clock to generate a flashing LED so you can be sure the clock is up and working 21 14 TO DOWNLOAD DIRECT TO THE FPGA Select the FPGA device on the JTAG chain then right click on the device click on Assign Configuration File then select the bit file untitled Configuration Mode iMPACT EE loj x File Edit View Mode Operations Output Help Oa telga Hoane Boundary Scan Slave Serial SelectMAP Desktop Configuration TDI Get Device ID Get Device Signature Usercode pean ID ODE Looping TDC Assign Mew Configuration File 15 Right Click again on the selected device and this time select Program from the menu this will bring up the Program Options window Make sure that Verify is not ticked otherwise iMPACT will look for an msk file and we haven t created one Then select OK and this will program the FPGA with the bit file Program Options E x P Erase Before Programming Functional Test Verify M On jhe Fly Program Bead Protect Write Protect PROM Virkex l S
10. Chestnut Court Burton Row treme 2 S 2 Brent Knoll Somerset TA9 4BP UK from 2 Tel 44 0 1278 760188 HUNT ENGINEERING Yona of Fax 44 0 1278 760199 Ti Third Party it w a Email sales hunteng co uk _y ki www hunteng co uk S www hunt dsp com TEXAS INSTRUMENTS Using 1MPACT with FPGA Modules v 1 2 J Thie 19 12 05 The HERON FPGA and HERON IO families are ranges of HERON modules with FPGAs often combined with some interface capability Many of the HERON FPGA and HERON IO modules provide a connection for the Xilinx download tool iMPACT along with a FLASH PROM that can be programmed with a bit stream For HERON FPGA and HERON IO modules that provide a JTAG connector and a PROM by using iMPACT it is possible to directly configure the FPGA on the module or download a bit stream to the PROM When the PROM has been written with a bit stream this enables the FPGA module to automatically configure the FPGA from the PROM as soon as power is applied to the module allowing the module to perform as part of an embedded system The application FPGA and FLASH PROMs can be programmed and reprogrammed via the JTAG chain using Xilinx cables such as the Parallel 3 or Parallel 4 cables The application FPGA if connected on your module can be programmed directly from the design bit stream file bit file while the PROMs must be programmed with the contents of a MCS file generated in your design tools from the previously created
11. I sctOSp File 7 T G PROGRESS EMD End Operation Elapsed time 4 sec a Configuration Mode Boundary Scan Parallel W 2 For Help press Fl 7 TO DOWNLOAD TO A PROM Select the PROM click on it and it should become green then right click on the same device and a menu should pop up select Assign Configuration File select the mcs file S untitled Configuration Mode iMPACT E Joj x Fie Edit View Mode Operations Gutput Help D S amp eee Haane Boundary Scan Slave Serial SelectMAP Desktop Configuration Basen Blank Check Readback et Device ID TDO ae Device Checksum Get Device Signature Usercode IDC ODE Looping TDI PROGRESS_EHD End Operation Assign Mew Configuration File Elapsed time 4 sec Device 2 selected Device 2 selected Configuration Mode Boundary Scan Parallel Ii 2 For Help press Fl 19 8 Right Click again on the selected device and this time select Program from the menu untitled Configuration Mode iMPACT E 5 x File Edit View Mode Operations Output Help D teg ann HEaog e Boundary Scan Slave Serial SelectMaP Desktop Configuration TDI Program pan verify sanali check oe Readback met Device ID Get Device Checksum Get Device Signature Usercode INFOauvIPACT 1 55 Loading CFI file D fp Device 2 selec
12. ary Scan Slave Serial Select Map xc l vO4 top mecs 1 Loading file C fpga3v1 Example USE top mes done Device 1 selected For Help press F1 Parallel Iptl 23 10 11 TO DOWNLOAD TO A PROM Select the PROM click on it and it should become green then right click on the same device and a menu should pop up select Assign Configuration File select the mcs file Right Click again on the selected device and this time select Program from the menu this will bring up the Program Options window ensure that Parallel Mode has been selected Selecting OK will program the selected PROM with the mes file Program Options El Ea W Erase Before Programming P Eunetional test Verify T Bead Protect PROM Gal Aan O Skip user array Virtew Load Fpga M Secure Made Program fev W Parallel Mode Use D4 for CE T PROM Usercode 8 Hex Chars PEIFFER D PLA UES Enterupto 0 characters Cancel Help If the programming was successful you ll see a message Programming Succeeded This message is only displayed for a few seconds In the command window as well upon success you ll see Programming succeeded successfully TO DOWNLOAD DIRECT TO THE FPGA Select the Virtex H on the JTAG chain then right click on the same device and a menu should pop up select Assign Configuration File select the bit file Right Click again on the selected device and
13. e by double clicking on Generate PROM ACE or JTAG File Processes for Source top rtl Add Existing Source Create New Source Design Entry Utilities User Constraints Swnithesize 5 7 Implement Design Generate Programming File Programming File Generation Report OO Jao Es ST Si Si Generate PROM ACE or JTAG File L Configure Device IMPACT Bf Process View 5 IfiMPACT is started up separately it will first ask what you want to do If iMPACT is started from within Project Navigator as described in step 4 above you will not see this window as you have already selected you choice by selecting Generate PROM ACE or JTAG File So if you started iMPACT separately first select create a new project ipf IMPACT Project I want Eo load most recent project deFfautt ipf Browse Load most recent project file when iMPACT starts Greate a new project pf default ip Browse Cancel What do you want ta do first b ee Devices Back Cancel Help 7 The next window asks want you want to create Select PROM file and click Next Prepare Configuration Files want to create a i es ACE File r B eis can File lt Back Cancel Help 8 In the next window select MCS for the PROM file format enter the name for the PROM file and check that the location is correct We used example1 for the file name
14. ecure Mode Load FPGA Parallel Mode Use Dal for GF Program Key PROM CoolRunner Usercode 6 Hex Digits FFFFFFFF P PLS UES Enterupto 13 characters Cancel Help 16 In the case of examplel you should see LED 4 flashing For your own application it may be useful to write to an LED as well so that you can verify your application was loaded properly and has started Better use the clock to generate a flashing LED so you can be sure the clock is up and working 22 ISE 5 x and earlier 1 Start gt Programs gt Xilinx ISE 5 gt Accessories gt iMPACT 2 Next iMPACT will ask you some questions Take the defaults Configure Devices Boundary Scan Mode and Automatically connect to cable and identify boundary scan chain Operation Mode Selection Configure Devices What do you want to do first want to configure device via Configure Devices Boundary Scan Mode C Prepare Configuration Files C Slave Serial Mode Load Configuration File cdf pdr Select Map Mode C Desktop Configuration Mode Boundary Scan Mode Selection C Enter a Boundary Scan Chain 3 iMPACT will display the devices it has found on the JTAG chain which will be the PROM identified by its part number and for some module types the chain will include the FPGA I Untitled iMPACT Ee x File Edit Operations Output View Help D g H amp amp Se 36 ir 35 CE E a Bound
15. ming is successful With the xc18v04 PROM device this will bring up the Program Options window In this window ensure that Parallel Mode has been selected Selecting OK will program the selected PROM with the mcs cfi file Program Options 2 x M Erase Before Programming Functional Test Iw Verify M On The Fly Program Read Protect Write Protect PAOM T Load FPGA M Parallel Mode Use bal for GF Virbes I Secure Mode Program key PROM CoolRunner Il Usercode 8 Hex Digits FFFFFFFF P PLS UES Enterupts 13 characters Cancel Help If the programming was successful you ll see a message Programming Succeeded This message is only displayed for a few seconds In the command window as well upon success youll see Programming succeeded successfully In case the programming failed often the reason is that the PROM hasn t been erased Right click again on the PROM device and this time select Erase When that is done try to program the PROM device again To test the PROM programming power down the PC if using a carrier board like HEPC8 or HEPC9 or the board if using a HEBASE1 or later board Every HERON FPGA or HERON IO module that has a PROM fitted has a jumper that selects whether to boot from PROM or not In most cases this jumper is labelled BFPROM on the PCB of the module Make sure that the BFPROM jumper is fitted to select
16. mple1 ISE where dir is the local directory you copied the FPGA examples to and open the appropriate project file for the board type you are using 3 Check that CCLK has been selected for the Start Up Clock then generate a rbt file by Generate Programming File gt Run 4 The next thing would be to run the PROM file formatter However if there s no pdr file in your project yet you cannot start the PROM file formatter from within ISE 4 x What you can do is create an empty pdr file save it then go back to ISE4 x File Edt View Help Design Entry Utilities te Synthesize l Se ae Jelade He p iga Implement Design Cig Generate Programming File a Programming File Generation Report Generate PAROM File Configure Device IMPACT aE 5 Start gt Programs Xilinx ISE 4 x gt Accessories gt PROM File Formatter 6 Immediately do a File gt Save Description Save the pdr file in your project directory For example1 that would be dir example1 ISE use as name top pdr 7 Exit the PROM file formatter 8 Now you will be able to start the PROM file formatter from within ISE 4 x Double click on Generate PROM File The PROM file formatter should start but now with a proper filename under Data Stream 1 Make sure that the file selected is the proper file For example1 this is dir example1 ISE top bit 16 9 Make sure that File gt PROM Pro
17. on the Program Options the Load FPGA box is ticked then when the configuration has been downloaded to the PROM the FPGA is automatically and immediately configured Also note with the HERON FPGAS3 it is not possible to use Chip scope ISE 6 x and 7 x 1 Start gt Programs gt Xilinx ISE 6 gt Accessories gt iMPACT 2 In ISE 7 x you will be asked whether to open a recent project For this example select create a new project ipf 2 3 At the next window select the default Configure Devices Operation Mode Selection E x What do you want to do first Prepare Configuration Files Load Configuration File cdf pdr 4 Then select the default Boundary Scan Mode Configure Devices E x want to configure device via Slave Serial Mode C SelectMAP Mode C Desktop Configuration Mode 5 Again select the default Automatically connect to cable and identify boundary scan chain Boundary Scan Mode Selection e x Enter a Boundary Scan Chain 18 6 iMPACT will display the devices it has found on the JTAG chain which will be the PROM identified by its part number and for some module types the chain will include the FPGA S untitled Configuration Mode iMPACT E loj x File Edit View Mode Operations Gutput Help es es Se eee SS i Boundary Scan Slave Serial SelectMAP Desktop Configuration Fight click device to select operations TD
18. perties are set to MCS 806 and Serial Serial should be selected despite the fact that the hardware is parallel to work around the bug in the Xilinx software the software also then gives the PROM device in terms of the Xilinx PROM part number For example for the HERON FPGA3 the PROM type is an XC18V04 so ensure this is selected for the PROM device Select ORK to continue PROM Properties Format l Data Streams Files PROM File Format MCS 86 Save 4s Defaults Type PROM Device size in Bits f Serial Byte vide PROM File Single PROM Split PROM E Automatic Selection 10 From the PROM File Formatter window use File gt Create PROM to create the mcs files Quit the PROM File Formatter You can verify the PROM File Formatter step by checking that your project directory now has a mcs file In the case of example1 this would be dir example1 ISE top mcs 17 Downloading Bit streams via JTAG Once the mcs bit and optional cfi files have been generated they can be downloaded to the PROMs or directly to the FPGA using the Xilinx IMPACT software We recommend starting iMPACT as a stand alone tool Please note for some module types such as the HERON FPGAG3 the user FPGA is not in the JTAG chain and therefore cannot be directly configured In the case of modules like the HERON FPGAS you can still effectively download your design to the FPGA via JTAG for debug purposes If
19. t File gt Open Project To load the Examplel project go to the directory dir example1 ISE where dr is the local directory you copied the FPGA examples to and open the appropriate project file for the board type you are using 3 Check that CCLK has been selected for the start up clock this can be found in the Startup options tab of the Generate Programming File Process Properties window Sources in Froject F config SercAUser Apl vhd a top rtl 4 Commons TOF vhd ei esibench bench Vore 7B Es vhd u Ex Foga uct B he_rd_bf rtl Commons 2 AO_EF B he_rvclk rtl Commons HE _A CLI 2 M he_sdrarnrtl 4 CormmoansHE_ SORA a he_ad_cntr rtl Commons HE_ V he_userrtl Commons HE_USER w h O E Module ta Snapshot Ii Library Processes for Source bop rtl Synthesize XST View Sunthesis Report my Yiew RTL Schematic lt 3 Check Syntax He Design Programmi PL m Generate F Perun Configure Rerun All Be Process View With this done you can then generate a rbt file by Generate Programming File gt Run When you generate the rbt bitstream make sure that in the Sources in Project window the top rtl Common TOP vhd line is highlighted Properties 4 The next step is to start iMPACT which will be used to create the PROM file in the correct format This is don
20. t go to the directory dir example1 ISE where dir is the local directory you copied the FPGA examples to and open the appropriate project file for the board type you are using 14 Check that CCLK has been selected for the start up clock this can be found in the Startup options tab of the Generate Programming File Process Properties window Sources in Project iF contig 4are 5User Ap vhd a top rtl 4 Commons TOP vhd iad testbench bench 5re 7 BEX vhd m Es1_Fpgarw uct v e he_rd_6f rtl 5 S Common AD BF he_rwelk rtl 4 Commons HE _A CLI B he sdram rtl Commons HE_SDARA B he_ad_cntr rtl Commons HE_ a he _user rtl 4 SCornmon HE USER y O E Module ta Snapshot Ii Library Processes for Source bop rtl Spnthesize XST View Sunthesis Report mg Yiew RTL Schematic lt 3 Check Syntax x3 Implement Design e Generate Frogrargagis Frogrammii rU m Generate F Perun Configure Rerun All Be Process View With this done you can then generate a rbt file by Generate Programming File gt Run When you generate the rbt bitstream make sure that in the Sources in Project window the top rtl Common TOP vhd line is highlighted 15 The next step is to start iMPACT which will be used to create the PROM file in the correct format This is done by double clicking on Generate PROM ACE or JTAG File
21. te PROM ACE or JTAG File E Design Entry Utilities cere User Constraints Wo Synthesize J implement Design k Generate Programming File bocce af Programming File Generation Report Generate PROM ACE or JTAG File on C Configure Device IMPACT ma ma aoa ey for Current Source al Process Tiem 5 When iMPACT first starts it will ask what you want to do Select Prepare Configuration Files and click Next Operation Mode Selection e x What do you want to do first i R Devices m Load Configuration File cdf pdr 6 The next window asks want you want to create Select PROM file and click Next Prepare Configuration Files d X want to create 2 f cas ACE File b anae can File 12 7 In the next window select Xilinx Serial PROM MCS for the file format enter the name for the PROM file and check that the location is correct Then click Next Prepare PROM Files want to target a ilins Serial PROM C Parallel PROM PROM File Format f MECS TEK f EXO HES e Swap bits Memory fill value 2 Hes digit FF PROM file name Example1 Location C MpgaMpgaav1 Examplel SEY Browse 8 Inthe next window tick Auto select PROM and click Next 9 Click Next again in the following window File Generation Summary Click Nest to add device file e Cancel Help f Z
22. ted l 4 ae e e e Get Device Customer Code IDC ODE Looping Assign New Configuration File For Help press Fl Configuration Mode Boundary Scan Parallel TY With the xcf08p and xcfl6p PROM devices this will bring up the Advanced PROM Programming Options window In this window ensure that Parallel Mode has been selected Selecting OK will program the selected PROM with the mcs and cfi file Advanced PROM Programming Options x Design Revision and Customer Code Select Design Revizion and Enter Customer Code Max 64 Hes Digita Design Read Write Erase Wernfp Free Running Customer Revision Protect Protect Clock Code M Reg Re O we O ER PF vA M FRC PO Revd Mone Cwe ern va rac fo C Rez AP TP we eR ve 9 FRC Po Rev Tone TC we Cen va rac Default Revision T O Configuration Parallel Mode During Configuration Usercode PROM is Slave clocked externally PROM is Configuration Master select clock source f External Clock rtermal Glock Clock Frequency Enter Hex Digits Usercode FFFFFFFF l Load FPGA Cancel Hee fao MHz 20 10 11 L E With ISE 7 x you must also tick Rev 0 with ISE 6 x there s no need to tick Rev 0 You may also want to tick the Erase and or Verify boxes Note that you may have to erase the PROM device before a successful PROM program
23. this time select Program from the menu this will bring up the Program Options window Selecting OK and this will program the FPGA with the bit file In the case of example1 you should see LED 4 flashing For your own application it may be useful to write to an LED as well so that you can verify your application was loaded properly and has started Better use the clock to generate a flashing LED so you can be sure the clock is up and working If files have been downloaded to the PROMs power down the PC if using a carrier board like HEPC8 or HEPC9 or the board if using a HEBASE1 or later board Make sure that the BFPROM jumper is fitted Power up the PC if using a carrier board like HEPC8 or HEPC9 or the board if using a HEBASE 1 or later board In the case of examplel you should see LED 4 flashing For your own application it may be useful to write to an LED as well so that you can verify your application was loaded properly and has started Better use the clock to generate a flashing LED so you can be sure the clock is up and working 24
24. ue Fir PROM Filename example Humber of PROP s m Click Nest to add device file lt Back Cancel Help 11 In the Add Device File window click on the Add File button and select the top bit bit stream that will have been generated last time you ran the bit stream generation process When this process has run and you are asked if you would like to add another bit stream select No Next click on the Finish button and the MCS files will be created Additional CFI files will be created if you selected the Enable Revisioning option earlier on Add Device File Revision j Starting Address Max o Hes Digits fo Mow start adding device file s Add File Cancel Help ae File name ftop bit My Network F Files of type fan Design Files Cancel After selecting top bit click No when asked if you want to add another design file 2 would you like to add another design file to Revision O Revision 0 Starting Address Max 8 Hex Digits fo How start adding device file s Add File Click Finish to start generating file Click Cancel to go to user screen Cancel Help ISE 6 x For this example we will assume that we want to program the Examplel bit stream into the PROM of the FPGA module 12 Start Project Navigator 13 Select File gt Open Project To load the Examplel projec
25. ve the file Save into the default offered by ISE which should be your project directory Double click on Generate PROM File The PROM file formatter should start with a proper filename under Data Stream 1 Make sure that the file selected is the proper file For example1 this is dir example1 ISE top bit File Edt View Help SOL An ag Salma ele a Ele PROM a ae a al HA aes wht Toba B oo ad mE Make sure that File gt PROM Properties are set to MCS 806 and Serial Serial should be selected despite the fact that the hardware is parallel to work around the bug in the Xilinx software the software also then gives the PROM device in terms of the Xilinx PROM part number For example for the HERON FPGA3 the PROM type is an XC18V04 so ensure this is selected for the PROM Device Select OR to continue 14 Pranertics Use File gt Create PROM to create a mcs file If the tools asks you to save the pdr file do so Quit the PROM File Formatter You can verify the PROM File Formatter step by checking that yout project directory now has a mcs file In the case of examplel this would be dir example1 ISE top mcs 15 ISE 4 1 For this example we will assume that we want to program the Example1 bit stream into the PROM of the FPGA module 1 Start Project Navigator 2 Select File gt Open Project To load the Examplel project go to the directory dir exa
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