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PCI8305 User`s Manual

1. only converting the data when the trigger signal is in the low level A D Start ref Digital Trigger Signal pererezzzsssesesessnsesesenti Seong The high level before i a peewee Ed the A D started is JIS Pause Figure 5 2 4 High Level Trigger BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 3 PCI8305 Data Acquisition V6 006 When ADPara TriggerDir PCI8305 TRIGDIR POSITIVE it means the trigger level is high When DTR trigger signal is in high level A D 1s in the conversion process once the trigger signal is in the low level A D conversion will automatically stop when the trigger signal is in the high level again A D will re access to the conversion process that is only converting the data when the trigger signal 1s in the high level When ADPara TriggerDir PCI8305 TRIGDIR POSIT NEGAT it means the trigger level is low or high The effect is the same as the internal software trigger BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 4 PCI8305 Data Acquisition V6 006 Chapter 6 Methods of using A D Internal and External Clock Function 6 1 Internal Clock Function of A D Internal Clock Function refers to the use of on board clock oscillator and the clock signals which are produced by the user specified frequency to trigger the A D conversion regularly To use the clock function the hardware parameters ADPara ClockSource PCI8305 C
2. If change the initial count when counting it will be effective next time When GATE 0 the count is prohibited when GATE 1 the count is permitted Time diagram is shown in figure 4 Mode 3 Figure 4 Mode 4 Software triggered strobe Under this mode the counter is given the initial count value N and begins to count the output OUT becomes high level When the count value becomes 0 it immediately outputs a negative pulse which is equal to the width of one clock cycle If given a new count value when counting it will be effective immediately GATE 1 enables counting GATE 0 BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 11 PCI8305 Data Acquisition V6 006 disables counting GATE has no effect on OUT Time diagram is shown in figure 5 Mode 4 Figure 5 Mode 5 Hardware triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it 1s called hardware trigger the output OUT has remained high level When the count value becomes 0 it outputs a negative pulse which is equal to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter starts to count from the initial count value again in the count period the output has remained high level When the count reduction of the counter has not yet reached zero but it is given a new value NI Only when it is the rising edge of GATE the counter starts to count
3. from N1 Time diagram is shown in figure 6 Mode 5 GATE our aay LO GATE fl B lI rei OUT n 4 li Figure 6 BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 12 PCI8305 Data Acquisition V6 006 Chapter8 Notes Calibration and Warranty Policy 8 1 Notes In our products packing user can find a user manual a PCI8305 module and a quality guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using PCI8305 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of PCI8305 module 8 2 Analog Signal Input Calibration Every device has to be calibrated before sending from the factory It is necessary to calibrate the module again if users want to after using for a period of time or changing the input range PC18305 default input range 10V in the manual we introduce how to calibrate PCI8305 in 10V calibrations of other input ranges are similar Prepare a digital voltage instrument which the resolution is more than 5 5 bit install the PCI8305 module and then power on warm up for fifteen minutes 1 Zero adjustment Select AIO for example connect a DC voltage source with value equal to OV to AIO Adjust RPI until the a
4. gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s guarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments i e high temperatures high humidity or volatile chemicals VV VV Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company website BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 14 PCI8305 Data Acquisition V6 006 Products Rapid Installation and Self check Rapid Installation P
5. level After a CLK cycle OUT resumes high level and the counter automatically load the initial value N and begin to count from N 1 Thus the output will continue to output a negative pulse its width is equal to one clock cycle the clock number between the two negative pulses is equal to the initial value that is given to the counter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT If change the initial count when counting it will be effective next time Time diagram is shown in figure 3 Mode 2 OUT GATE H GATE FI 0 0 3 2 1i 0 3 3 2 1 B QUT n 4 L I L Figure 3 Mode 3 Square wave mode Similar to Mode 2 the counter is given the initial count value N and begins to count from N 1 When the signal of GATE is high level it starts to count timer counter begins to count by subtracting 1 each time more than half the initial count value The output OUT has remained high level when the count value is more than half of the initial count value but the output OUT becomes low level when the count value is less than half of the initial value If the initial count value N is an even number the output is 1 1 square wave if the initial count value N is an odd number the output OUT has remained high level during the previous n 1 2 count period but the output OUT becomes low level during the post n 1 2 count period that is the high level has one clock cycle more than the low level
6. 6 NC n 37 DGND DGND 47 n n 5 CLKXM 26 GATEI DGND 46 n A 4 CLKO 25 GATEO DTR 45 a a 3 CLKI n 24 CLK2 CLKOUT 44 n 0 2 GATE2 a 23 OUTO CLKIN 43 n l OUT2 DD OUTI Pin definition about CNI PCI8305 Data Acquisition V6 006 AIO AI15 Analog input reference ground is AGND AO0 AO3 Analog output reference ground is AGND AGND GND Analog ground This AGND pin should be connected to the system s AGND plane DGND GND Digital ground This DGND pin should be connected to the system s DGND plane CLKIN External clock input CLKOUT Internal clock output DTR Digital trigger input CLKXM On board clock oscillator pulse output can provide clock source signal for CLKO CLK2 CLKO CLK2 Counter 0 3 clock input GATE0O GATE2 Counter 0 3 gate OUTO OUT2 Counter 0 3output 5V 5V power supply output NC Not connected PCI8305 Data Acquisition V6 006 Chapter 4 Connection Wavs for Each Signal 4 1 Analog signal single ended input connection Single ended mode can achieve a signal input bv one channel and several signals use the common reference ground This mode is widelv applied in occasions of the small interference and relativelv manv channels AIO analog signal All ja e e Mal device m 1 device EA ach device ae Figure 4 1 single ended input connection 4 2 Analog differential inputs Double ended input mode which was also called differentia
7. Explorer open CD ROM drive run Others SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation
8. LOCKSRC IN should be installed in the software The frequency of the clock in the software depends on the hardware parameters ADPara Frequency For example if Frequency 100000 that means A D work frequency is 100000Hz that is 100 KHz 10us point 6 2 External Clock Function of A D External Clock Function refers to the use of the outside clock signals to trigger the A D conversion regularly The clock signals are provide by the CLKIN pin of the CNI connector The outside clock can be provided by PCI8305 clock output CLKOUT of CN1 as well as other equipments for example clock frequency generators To use the external clock function the hardware parameters ADPara ClockSource PCI8305 CLOCKSRC OUT should be installed in the software The clock frequency depends on the frequency of the external clock and the clock frequency on board that is the frequency depends on the hardware parameters ADPara Frequency only functions in the packet acquisition mode and its sampling frequency of the A D 1s fully controlled by the external clock frequency 6 3 Methods of Using A D Continuum and Grouping Sampling Function 6 3 1 A D Continuum Sampling Function The continuous acquisition function means the sampling periods for every two data points are completely equal in the sampling process of A D that is completely uniform speed acquisition without any pause so we call that continuous acquisition To use the continuous acquisition function th
9. PCI8305 User s Manual a Beijing ART Technology Development Co Ltd PCI8305 Data Acquisition V6 006 Contents CONT siccsesanshcnssaaat E E E E E E sesncesaiavonsasceracesesoceeesasareek 2 CCT OVOP a ETI EEA E A N A AE NE AOI NET A A E ne 3 Chapter 2 Components Layout Diagram and a Brief Description ss sssessssnnnnznnnnnnnznnnnzznnenznzznnizzzzntenzzznzzzzzznrnnnznnnnzznna 5 2 1 The Main Component Layout Diagram l ni a rE N A E R AN EA N AN EA N AN aa 5 2 2 The Function Description for the Main Component cccccssssssssssseessesesssssesssesssesssssseaesssessssssaeaasseaasaeaaaaaaaaas 5 22 Signal Input and Outp t CO e CIOS scssi ceruen ironie rahe Eenok ikeen EEEo thar inienn VEERO uhr S EENES 5 2 22 E E L L a 5 22 Oe SUAS IG A aa 5 2 20 Pivsieni IDO DIP WAC tuna 6 Ciprer 1 A 1 OCC OTS sie Ke A 7 3 1 The Definition of Signal Input and Output Connectors se eeeeeennnnnnnnnnnznnzzzzzzznznanzznzznznnnnnnananannzzanznnnzznznnznnnnnza 7 Chapter 4 Connection Ways for Each Signal nanna aa AAAEAAAAA KEEA EEA EA AAEEE NEED MM MEKKNNNMEKEEEEEEEZZZZZZZZ NEM EEEEEEETA 9 4 1 Analog signal single ended input CONNECTION ccccceseeeeeeseeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 9 ON aye E VON ey etil e 9 4 3 Ana OO OC OCS MO ta a A A EA A OA OA A AOA OA AA 10 4 4 Clock input output and trigger input CONNECTION ccc cceeeeeseseseseesee
10. alize the synchronization for the PC8305 the first method is using the cascade master slave card the second one is using the common external trigger and the last one is using the common external clock 10 PCI8305 Data Acquisition V6 006 When using master slave cascade card programs the master card generally uses the internal clock source model while the slave card uses the external clock source mode After the master card and the slave card are initialized according to the corresponding clock source mode At first start all the slave cards as the main card has not been activated and there is no output clock signal so the slave card enters the wait state until the main card was activated At this moment the multi card synchronization has been realized When you need to sample more than channels of a card you could consider using the multi card cascaded model to expand the number of channels lt Q Master Card CLKOUT jid e CLKIN gt Slave Card 1 Y G gt Slave Card 2 i When using the common external trigger please make sure all parameters of different PCI8305 are the same At first configure hardware parameters and use digital signal triggering DTR then connect the sampled signal input triggering signal from DTR pin then click Start button at this time PCI8305 does not sample any signal but waits for external trigger signal When each module is waiting for external trigge
11. ata Acquisition V6 006 Trigger Type edge trigger and level trigger Trigger Dir negative positive either positive or negative trigger Trigger Source DTR DTR range TTL A D Conversion Time lt 1 6uS Programmable amplifier AD8251 default AD8250 AD8253 Programmable Gain 1 2 4 8 AD8251 default or 1 2 5 10 AD8250 or 1 10 100 1000 AD8253 Analog Input Impedance 10MQ Amplifier Set up Time 785nS 0 001 max Non linear error 3LSB Maximum System Measurement Accuracy 0 1 Operating Temperature Range 0 C 50 C VV VV VV VV VC V Storage Temperature Range 20 C 70 C Analog Output Output Range O 5V 0 10V 0 10 8V 10V 10 8V 12 bit resolution Set up Time 10uS 0 01 Output Channels 4 Non linear error 1LSB Max Output error full scale 1LSB Timer Counter Counter Channel No 3 independent counter VV VV V WV Counter Mode subtract count Counter Resolution 32 bit Count Mode six count modes software configurable VV VV V electrical standard TTL compatible Other features gt Board Clock Oscillation 40MHz gt Board Dimensions 144mm L x 98mm W x 17mm H 4 PCI8305 Data Acquisition V6 006 Chapter 2 Components Layout Diagram and a Brief Description 2 1 The Main Component Layout Diagram et ee 14 j oe fur k U H B 4 ta OOL SLOSHS a p Si Aa ge J r 5 a d i if A tm al AG hs l i ML zig ow i mn a A r a TT hs ULL a JUM b a
12. ctual input value 0 000V 2 Full scale adjustment Select AIO for example connect a DC voltage source with value equal to 9997 55mV to AIQ Adjust RP2 until the actual input value 9997 55mV 3 Repeat steps above until meet the requirement 8 3 Analog Signal Output Calibration In the manual we introduce how to calibrate PCI8305 in 10V input range calibrations of other input ranges are similar 1 Zero adjustment Select AOO for example set its output value to OV Adjust RP4 until the actual output value 0 000V RP7 RP3 RP8 correspond to AOI AO2 AO3 2 Full scale adjustment Select AOO for example set its output value to 9995 11mV Adjust RP6 until the actual output value 9995 11mV RP9 RP5 RP10 correspond to AO1 AO2 AO3 3 Repeat steps above until meet the requirement 8 4 DA use In demonstration program the continuous output interval of waveform output can not be carried out the main objective is to test the strength of DA output PCI8305 Data Acquisition V6 006 8 5 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty
13. e first falling edge after the the A D started is i A D started is valid invali d H qeesetorereeeeeeeeseeeseeesneeseeeereeeresereneee i 3 ETT TPePPTTTeLTTTTE TILE TT TITeTTTTTererererrreee kell ee ee eee eee i The first working Figure 5 2 1 Falling edge Trigger When ADPara TriggerDir PCI8305 TRIGDIR POSITIVE choose the trigger mode as rising edge trigger That is when the DTR trigger signal is on the rising edge A D will immediately access to the conversion process and its follow up changes have no effect on A D acquisition When ADPara TriggerDir PCI8305 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger That is when the DTR trigger signal is on the rising or falling edge A D will immediately access to the conversion process and its follow up changes have no effect on A D acquisition This function can be used in the case that the acquisition will occur if the exoteric signal changes 2 Level trigger function Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger A D conversion When ADPara TriggerDir PCI8305 TRIGDIR NEGATIVE it means the trigger level is low When DTR trigger signal is in low level A D is in the conversion process once the trigger signal is in the high level A D conversion will automatically stop when the trigger signal is in the low level again A D will re access to the conversion process that is
14. e hardware parameters ADPara ADMode PCI8305 _ ADMODE SEQUENCE should be installed in the software For example in the internal clock mode hardware parameters ADPara Frequency 100000 100KHz should be installed and 10 microseconds after the A D converts the first data point the second data point conversion starts and then 10 microseconds later the third data point begins to convert and so on 6 3 2 A D Grouping Sampling Function Grouping acquisition pseudo synchronous acquisition function refers to the sampling clock frequency conversion among the channels of the group in the AD sampling process and also a certain waiting time exists between every two BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 5 PCI8305 Data Acquisition V6 006 groups this period of time is known as the Group Interval Loops of group refer to numbers of the cycle acquisition for each channel in the same group In the internal clock mode and the fixed frequency external clock mode the time between the groups is known as group cycle The conversion process of this acquisition mode as follows a short time stop after the channels conversion in the group that is Group Interval and then converting the next group followed by repeated operations in order so we call it grouping acquisition The purpose of the application of the grouping acquisition is that at a relatively slow frequency to ensure that all of the time difference betwee
15. equirement is the external clock cycle gt the internal clock sampling period x the total number of sampling channelsx Loops of group AD chip conversion time otherwise the external clock appearing in the group conversion time will be ignored Under the fixed frequency external clock mode for example when sampling data of two channel 0 1 then channel 0 and channel consist of a group Sampling frequency Frequency 100000Hz the cycle is 10us Loops of group is 2 then the acquisition process 1s to collect the first set of data including two data of channel 0 and two data of channel 1 the order of conversion 0 1 0 1 We need 10us to sample the four data and 40us to convert of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the next edge of the external clock triggers AD to do the next acquisition and the conversion is going on in this way as the diagram following shows Start Enabled External Clock ee Convert Pulse The external clock before the start pulse is ignored Figure 6 3 Grouping sampling under the fixed frequency external clock mode Notes a internal clock sample cycle b AD chips conversion time d group cycle external clock cycle Under an unfixed frequency external clock mode for example the grouping sampling principle is the same as that of the fixed frequency external clock mode Under this mode u
16. ia a war PITODLSAK H Fuu iian ENR ww iz Ee Aa l TE tote m oti head e w Mess ma pe fee me gt f pares A mW h P MTA pree nos epo ia FECE or are UU f era het ste Fi xa ifa Bost dua 71 Mela o f w PCI8305 4 i Qm GIB sam 88 Sa veo he max tl wa is ae AA wT 34 lia ame Se el 2 2 The Function Description for the Main Component 2 2 1 Signal Input and Output Connectors CNI Signal input and output connectors 2 2 2 Potentiometer RPI Analog input zero point adjustment potentiometer RP2 Analog input full scale adjustment potentiometer RP4 RP7 RP3 RP8 AOO AOQO3 zero point adjustment potentiometer RP6 RP9 RP5 RP10 AOO AO3 full scale adjustment potentiometer 2 2 3 Status Indicator EF FIFO non emptv status indicator HF FIFO half full status indicator FF FIFO overflow status indicator PCI8305 Data Acquisition V6 006 2 2 4 Physical ID of DIP Switch DIDI Set physical ID number When the PC is installed more than one PCI8305 you can use the DIP switch to set a physical ID number for each board which makes it very convenient for users to distinguish and visit each board in the progress of the hardware configuration and software programming The following 4 bit numbers are expressed by the binary system When DIP switch points to ON that means 1 and when it points to the other side that means 0 As they are shown in the following diagrams ID3
17. ip AD will automatically cut off to enter into the waiting state until the 50us group interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows Start Enabled ae ee ae Convert Pulse al lal lal ial fa wee ee Figure 6 1 Grouping Sampling which grouping cycle No is 1 under the Internal Clock Mode Note a internal clock sample cycle b AD chips conversion time c Group Interval d group cycle Change the loops of group into 2 then the acquisition process is to collect the first set of data including two data of channel 0 and two data of channel 1 the conversion order is 0 1 0 1 We need 10us to sample each of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the 50us Group Interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows Start Enabled me Convett Pulse oe ee al ibic ia d Figure 6 2 Grouping Sampling which grouping cycle No is 2 under the Internal Clock Mode Notes a internal clock sample cycle b AD chips conversion time c Group Interval d group cycle PCI8305 Data Acquisition V6 006 Under the external clock mode the r
18. is the high bit IDO is the low bit and the black part in the diagram represents the location of the switch Test softwares of the company often use the logic ID management equipments and at this moment the physical ID DIP switch is invalid If you want to use more than one kind of the equipments in one and the same system at the same time please use the physical ID as much as possible ID3 ID2 IDI IDO ON MI GIDI l 2 3 4 The above chart shows 1111 so it means that the physical ID is 15 ON ID3 ID2 IDI IDO ON a INI SIDI l 2 3 4 The above chart shows 0111 so it means that the physical ID is 7 ID3 ID2 IDI IDO ON l 2 3 4 The above chart shows 0101 so it means that the physical ID is 5 ON OFF 0 OFF OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF oN oN oN oN oN ON oN oN PCI8305 Data Acquisition V6 006 Chapter 3 Signal Connectors 3 1 The Definition of Signal Input and Output Connectors 62 core plug on the CNI pin definition a 21 AIO n 42 All AID 62 A A 20 AJ3 5 41 Al4 AIS 61 A a 19 AI6 a 40 AI7 AIS 60 m A 18 AIQ 5 39 AI10 AIII 59 a a 17 AI12 6 38 AI13 All4 58 A A 16 All5 5 37 NC NC 57 5 15 NC 36 NC NC 56 A A 14 NC 35 NC NC 55 0 n 13 NC 5 34 NC NC 54 0 e 12 NC A 33 NC NC 93 A 0 11 NC n 32 NC AGND 52 n n 10 AGND A 31 AOO AOI 51 n n 9 AO2 5 30 AO3 NC 50 a A 8 NC A 29 NC AGND 49 a n 7 NC 28 NC 5V 48 a n
19. l input mode uses positive and negative channels to input a signal This mode is mostly used when biggish interference happens and the channel numbers are few SE DI mode can be set by the software please refer to PCI8305 software manual According to the diagram below PCI8305 board can be connected as analog voltage double ended input mode which can effectively suppress common mode interference signal to improve the accuracy of acquisition Positive side of the 8 channel analog input signal is connected to AIO AI7 the negative side of the analog input signal is connected to AI8 AI15 equipments in industrial sites share the AGND with PCI8305 board age AIO analog signal nO device AI8 G e All AN nO device AIQ G o PTY e e e AI7 AIS OY device dozens of KQ to hundreds of KQ AGND Te d Figure 4 2 double ended input connection PCI8305 Data Acquisition V6 006 4 3 Analog output connection AOO analog signal oF g Sig AOI ej CY e TA Pe device p device man AGND J Figure 4 3 analog signal output connection 4 4 Clock input output and trigger input connection III CLKOUT aml lg CLKIN A An p DTR DGND e 4 5 Timer counter connection TAGE ee Lj CLK A Gun OUT d DGND See 4 6 Methods of Realizing the Multi card Synchronization Three methods can re
20. mber of sample channels x Loops of group AD chips conversion time Group Interval External signal cycle cycle signal points Loops of group x Group Cycle External signal frequency 1 external signal cycle Under the external clock mode a fixed frequency external clock Group Cycle external clock cycle External signal cycle cycle signal points Loops of group x Group Cycle External signal frequency 1 external signal cycle Formula Notes The internal sampling clock cycle 1 AD Para Frequency The total number of sampling channels AD Para Last Channel AD Para First Channel 1 Loops of group ADPara LoopsOfGroup AD Chips conversion time see AD Analog Input Function parameter Group Interval AD Para Group Interval Signal Cycle Points with the display of the waveform signal in test procedures we can use the mouse to measure the signal cycle points BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 6 PCI8305 Data Acquisition V6 006 Under the internal clock mode for example sample two channel 0 1 and then 0 and 1 become a group Sampling frequency Frequency 100000Hz cycle is 10us Loops of group is 1 Group Interval 50us then the acquisition process is to collect a set of data first including a data of channel 0 and a data of channel 1 We need 10us to sample the two data 20us to convert the data from the two channels After the conversion time of an AD ch
21. n channels to become smaller in order to make the phase difference become smaller thus to ensure the synchronization of the channels so we also say it is the pseudo synchronous acquisition function In a group the higher the sampling frequency is the longer Group Interval is and the better the relative synchronization signal is The sampling frequency in a group depends on ADPara Frequency Loops of group depends on ADPara LoopsOfGroup the Group Interval depend on ADPara Group Interval Based on the grouping function it can be divided into the internal clock mode and the external clock mode Under the internal clock mode the group cycle is decided by the internal clock sampling period the total number of sampling channels Loops of group and Group Interval together In each cycle of a group AD only collects a set of data Under the external clock mode external clock cycle internal clock sampling cycle x the total number of sampling channels x Loops of group AD chip conversion time AD data acquisition is controlled and triggered by external clock The external clock mode is divided into fixed frequency external clock mode and unfixed frequency external clock mode Under the fixed frequency external clock mode the group cycle is the sampling period of the external clock The formula for calculating the external signal frequency is as follows Under the internal clock mode Group Cycle the internal clock sampling period x the total nu
22. r signal use the common external trigger signal to startup modules at last we can realize synchronization data acquisition in this way See the following figure PCI 8305 External Trigger Signal DTR Dik gt PCI 8305 ME Ma Y pre e Pci 8305 Note when using the DTR select the internal clock mode When using the common external clock trigger please make sure all parameters of different PCI8305 are the same At first configure hardware parameters and use external clock then connect the sampled signal then click Start button at this time PCI8305 does not sample any signal but wait for external clock signal When each module is waiting for external clock signal use the common external clock signal to startup modules at last we realize synchronization data acquisition in this way See the following figure Exiemal clodk signal j xternal cloc signa CLKIN gt PCI 8305 aS b PCI 8305 A y gt PCI 8305 PCI8305 Data Acquisition V6 006 Chapter 5 The Instruction of the A D Trigger Function 5 1 A D Internal Trigger Mode When A D is in the initialization if the A D hardware parameter ADPara TriggerMode PCI8305_ TRIGMODE SOFT we can achieve the internal trigger acquisition In this function when calling the StartDeviceProAD function it will generate A D start pulse A D immediately access to the conversion process and not wait fo
23. r the conditions of any other external hardware It also can be interpreted as the software trigger As for the specific process please see the figure below the cycle of the A D work pulse is decided by the sampling frequency The first working pulse after the A D start pulse Figure 5 1 Internal Trigger Mode 5 2 A D External Trigger Mode When A D is in the initialization if the A D hardware parameter ADPara TriggerMode PCI8305_ TRIGMODE POST we can achieve the external trigger acquisition In this function when calling the StartDeviceProAD function A D will not immediately access to the conversion process but wait for the external trigger source signals accord with the condition then start converting the data It also can be interpreted as the hardware trigger Trigger source is DTR Digital Trigger Source 1 Edge trigger function Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal to trigger A D conversion When ADPara TriggerDir PCI8305_ TRIGDIR NEGATIVE choose the trigger mode as the falling edge trigger That is when the DTR trigger signal is on the falling edge A D will immediately access to the conversion process and its follow up changes have no effect on A D acquisition PCI8305 Data Acquisition V6 006 A D Start Pulse Digital Trigger Signal f PO FFNME Ca a The falling edge before The waiting time gt Th
24. roduct driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin definition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource
25. sers can control any channel and any number of data Users will connect the control signals with the clock input of the card CLKIN set the sampling channels and Loops of group When there are external clock signals it will sample the data which is set by users Because the external clock frequency is not fixed the size of external clock cycle is inconsistent but to meet the external clock cycle gt the internal clock sampling period x the total number of sampling channels x Loops of group AD chip conversion time otherwise the external clock edge appearing in the group conversion time will be ignored PCI8305 Data Acquisition V6 006 Start Enabled External Clock a ee ee Convert Pulse Figure 6 4 Grouping sampling under the not fixed frequency external clock mode Note a internal clock sample cycle b AD chips conversion time PCI8305 Data Acquisition V6 006 Chapter7 Subtractive Counter Mode 0 Interrupt on terminal count Under this mode when given the initial value if GATE is high level the counter immediately begins to count by subtracting 1 each time the counter output OUT turns into low level when the count ends and the count value becomes 0 the counter output OUT becomes and keeps high level until given the initial value or reset If a counter which is counting is given a new value the counter will begin to count from the new value by subtracting 1 each time GATE can be used
26. seseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 10 AD Timer coli et COnNECHO sssi EEE ASAA AARAA 10 4 6 Methods of Realizing the Multi card Synchronization ccccccccceeeeeeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 10 Chapter 5 The Instruction of the A D Trigger FUnctiOn ccccccccccccccsseeessccccceeennsseseeeceeeeaaeseeeeeceeeeaaaaeseeeceeeeaaaaeeeeeeeeeesaaaaeeeess 2 mB Das iaa MOQLI aa 2 ILA 0 Bxiemal lipoer ModE e eee nee nen enon NEEE ae on ee a en ee eee ee ee ee eee 2 Chapter 6 Methods of using A D Internal and External Clock Function sssseeeeennnzzennnnnnzznnnnzzzznntenznznnzzzzstrnnzzznnzzzana 5 oa Bal oj lock Funciono r A D eeninsun ee nee enn ee ee re ee eee eee 5 62 Extemial Clock Fufi tion of A D sse1cc2ccetceazcdedsndtadedccataetontbensbonshnieZoaseansdendintedouoiatsdecdiptetouoiatebeasieasdocoiatePessieieteateeeeess 5 6 3 Methods of Using A D Continuum and Grouping Sampling FUNCTION ccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeess 5 6 3 1 A D Continuum Sampling Function ssssssesennenzzonsnenzznnzrenzzenenenerererenerererinererirererererinerikirenerenerenerenenemezAzA Etna 5 6 3 2 A D Grouping Sampling FUNCTION 2 0 0 0 nn 5 Cnapier SUDUGCTIVC L Onor ed sesnsseasecerunatncedchadeiedeadestuasesswulnvanaseetechdd es TERETERE EN E EERE ON TE A Ei 10 Chapters Notes Calibration and Warranty POLICY 0000000000nnnnnnnnnnnnnnnnnnsssssssssssseeerrrennsssssssssssesetrrrrer
27. ssssssssssssseeeerreesesessse 13 e NO aa E E E E AE E E A E 13 8 2 Analog Signal Input Calibration ie 13 8 3 Analog Signal Output Calibration seen nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnannnnnnnAnAANAZAANAMZAMNAZNAZANZZAZZNNZZZAZAZZZAZZZZAZAAZA 13 A E E E e 13 By VV MI LIM OC AEE A E EIO IE A A AN I A I E A E E E E 14 Products Rapid Installation and Self check cccccccecseessssesseessssesssssesssesssssssssseseeessesscsessesssssssssasessssaasseeaaaassaeasaaaaaaaaaas 15 Koodo aa a A E A eee ee 15 Royo 10 ka E A eee qa 15 D ee Wrone K aa a E eta 15 PCI8305 Data Acquisition V6 006 Chapter I Overview In the fields of Real time Signal Processing Digital Image Processing and others high speed and high precision data acquisition modules are demanded ART PCI8305 data acquisition module which brings in advantages of similar products that produced in china and other countries 1s convenient for use high cost and stable performance ART PCI8305 is a data acquisition module based on PCI bus It can be directly inserted into IBM PC AT or a computer which is compatible with PCI8305 to constitute the laboratory product quality testing center and systems for different areas of data acquisition waveform analysis and processing It may also constitute the monitoring system for industrial production process Software Analysis Software ART PCI8305 module is well suited for precision data acquisition analysis applica
28. tions which you can specifically address with the ART Data Acquisition Measurement Suite The suite has two components digital and graphics mode analysis functions for voltage any signal can be transformed into the voltage signal frequency response and other analysis Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local dealer or sales gt PCI8305 Data Acquisition Board gt ART Disk 1 user s manual pdf 2 drive 3 catalog gt Warranty Card FEATURES Analog Input Input Range 10V 5V 42 5 0 10V 13 bit resolution the 13 th bit is sign bit Sampling Rate 180KS s Input Channels 16SE 8DI Isolated voltage 2500Vrms 1 min Data Read Mode software inquire non empty and half full mode FIFO Size 16K word Memory Sign non empty half full full overflow Sample mode continuous sample and group sample Group Interval software configurable minimum value is sampling period maximum value is 419430uS Clock Source internal clock and external clock VV VV VV VV VV V WV Trigger Mode software trigger and hardware trigger external trigger BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 3 PCI8305 D
29. to control the count GATE 1 enables counting GATE 0 disables counting OUT signal changes high from low can be used as interrupt request Time diagram is shown in Figure 1 Mode 0 Gime ot ee ed ee Le LI H LL our GATE H 2 WH nipo fFF l CS ILU 4 2 tid OUT Figure 1 Mode 1 Hardware retriggerable one shot The mode can work under the role of GATE After given the initial count value N OUT becomes high level the counter begins to count until the appearance of the rising edge of GATE at this moment OUT turns into low level when the count ends and the count value becomes 0 OUT becomes high level that is the output one shot pulse width is determined by the initial count value N If the current operation does not end and another rising edge of GATE appears then the current count stops the counter begins to count from N once again and then the output one shot pulse will be widened When the count reduction of the counter has not yet reached zero but it is given a new value NI Only when it is the rising edge of GATE the counter starts to count from N1 Time diagram is shown in Figure 2 Mode 1 Figure 2 Mode 2 Rate Generator BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 10 PCI8305 Data Acquisition V6 006 Under this mode the counter is given the initial count value N and begins to count from N 1 OUT becomes high level When the count value becomes 0 OUT turns into low

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