(Pico), European Release
Contents
1. Status Class Background and Handling meaning request was finished regularly PFDL_OK normal reason no problems during execution remedy nothing meann at least one bit within the specified 9 area could not be verified margin for internal verification is PFDL_ERR MARGIN normal reason below the value required for full data retention no general remedy the requester remedy has to decide how to react based on application meaning request is being processed PFDL_BUSY normal reason request has been accepted call PFDL_Handler until status remedy changes R01US0055ED0112 Rev 1 12 ENESAS User Manual 43 3 7 3 PFDL_CMD_BLANKCHECK_BYTES The blank check command is used to check if all cells in the specified target flash area are erased e g before writing data into it The user can use the blank check command freely as it is a non destructive flash access The blank check command is initiated by PFDL_Execute and is executed by the sequencer After that PFDL_Handler shall be called to complete the command and check the PFDL status Status returned by PFDL_Execute Status Class Background and Handling meaning request is being processed PFDL_BUSY normal reason request has been accepted remedy call PFDL_Handler until status changes Status returned by PFDL_Handler Status Class Background and Handling meaning request was finished r2. FAL Flash Access Library Flash access layer FCL Code Flash Library Code Flash access layer RO1US0055ED0112 Rev 1 12 ENESAS User Manual Abbreviation FDL Full Form Data Flash Library Data Flash access layer Firmware is a piece of software that is located in a Firmware hidden area of the device handling the interfacing to the flash Electrically erasable and programmable nonvolatile Flash memory The difference to ROM is that this type of memory can be re programmed several times A flash block is the smallest erasable unit of the flash Flash Block memory Elash Macro A certain number of Flash blocks is grouped together in a Flash macro FW Firmware ID Identifier of a Data Set instance in the Renesas EEPROM Emulation Non volatile memory All memories that hold the value NVM even when the power is cut off E g Flash memory EEPROM MRAM PFDL Pico FDL Random access memory volatile memory with RAM random access REE Renesas Electronics Europe GmbH REL Renesas Electronics Japan REN Renesas Electronics Corporation ROM Read only memory nonvolatile memory The content of that memory can not be changed Segment Section Segment of Flash is a part of the flash that might consist of several blocks Important is that this segment can be protected against manipulation Self Programming Capability to reprogram the embedded flash without extern
3. Normal completion Y lt 5 gt PFDL_Execute IVERIFY command A Busy R gt y lt 8 gt PFDL_Handler Busy Y e See Error Status check SE Normal completion y lt 6 gt PFDL_Execute READ command 4 Y lt 7 gt PFDL_Close ra S End of Data Flash control y Exemplary flow of Data Flash operation using the PFDL RO1US0055ED0112 Rev 1 12 User Manual ENESAS 12 Note 1 Please note that the presented flow is only an example It is not mandatory to perform a blankcheck before an erase if you are sure that you want to erase the block in any case The erase command performs an automatic blankcheck Please see Section 3 7 5 for details For a regular write however please follow the suggested sequence of blankcheck write iverify in order to ensure full data retention A detailed description of all PFDL API functions can be found in Section 3 6 while all commands that can be triggered via PFDL_Execute are explained in Section 3 7 RO1US0055ED01 12 Rev 1 12 ENESAS User Manual 13 Chapter 2 Programming Environment This chapter describes the hardware environment and software environment required to rewrite the data flash memory using the Data Flash Library Type 04 PFDL 2 1 Hardware Environment The PFDL for the RL78 microcontroller uses the sequencer to cont
4. Return value Registers Type Description CA78KOR IAR GNU CC RL Status of operation can be PFDL_BUSY R8 A PFDL_OK PFDL_IDLE Peas e A X bank 1 PFDL_ERR_MARGIN PFDL_ERR_WRITE or PFDL_ERR_ERASE RO1US0055ED0112 Rev 1 12 ENESAS 38 User Manual Destructed registers Tool chain Destructed registers CA78KOR none IAR none GNU none CC RL C Precondition Before the execution of this function the PFDL_Open function must be Description R01US0055ED0112 Rev 1 12 User Manual completed normally Checks the control state of the command specified in the PFDL_Execute function executed beforehand and performs required settings for continuous execution While the status is PFDL_BUSY the running command is not finished yet and new commands may not be issued PFDL_OK indicates the successful completion of a command The possible error codes depend on the type of the triggered command Please refer to the individual command descriptions in Section 3 7 Description of Data Flash Library Commands ENESAS 39 3 6 5 PFDL_GetVersionString Outline Acquisition of the version information of the PFDL Interface C interface for CA78KOR compiler _ far pidl u08 far PFDL GelVersionstring void C interface for IAR compiler _ far func pfdl u08 far PFDL GetVersionString void C interface for GNU compiler pral u08 _ far PFDL GetVersionSt
5. Furthermore all running commands have to be finished before calling PFDL_Close R01US0055ED0112 Rev 1 12 ENESAS 32 User Manual Description The function PFDL_Close ends the operation of the Data Flash Library and disables the data flash memory Please call PFDL_Close whenever you want to e execute the Flash Self programming Library e run an EEPROM Emulation Library e use a Data Flash Library other than Type 04 or e utilize a STOP or HALT command Please note that the execution of PFDL_Close has to be completed before any of these listed actions can be taken RO1US0055ED01 12 Rev 1 12 ENESAS User Manual 33 3 6 3 PFDL_Execute Outline Executes control commands on the data flash memory Interface C interface for CA78KOR compiler pfdl status t _ far PFDL Execute _ near pfdl request Ei Rest pstry C interface for IAR compiler _ far fune pidl status E PFDL Ex ecut l near pidi request t _ negr request pstr 7 C interface for GNU compiler PECL status E PFDL Execute pidl request t request pstr _ attribute section PFDL COD 7 C interface for CC RL compiler pfdl _ status t _ far PFDL Execute __near pfdl request_t request pstr ASM function label for CA78KOR IAR GNU and CC RL assembler PFDL Execute Arguments Parameters Registers Argument Type Description CA78KOR IAR GNU CC RL Address of the pfdl_reques structure
6. Note Caution Numeric notation Numeric prefixes Register contents Diagrams User Manual Preface This manual is intended for users who want to understand the functions of the concerned libraries This manual presents the software manual for the concerned libraries This document describes the following sections e Architecture e Implementation and Usage e API Additional remark or tip Item deserving extra attention Binary XXXX or xxxB Decimal XXXX Hexadecimal XxxxH or Ox XXxx representing powers of 2 address space memory capacity K kilo 210 1024 M mega 220 10242 1 048 576 G giga 230 10243 1 073 741 824 X x don t care Block diagrams do not necessarily show the exact software flow but the functional structure Timing diagrams are for functional explanation purposes only without any relevance to the real hardware implementation How to Use This Manual 1 Purpose and Target Readers This manual is designed to provide the user with an understanding of the library itself and the functionality provided by the library It is intended for users designing applications using libraries provided by Renesas A basic knowledge of software systems as well as Renesas microcontrollers is necessary in order to use this manual The manual comprises an overview of the library its functionality and its structure how to use it and restrictions in using the library Particular attention should be pa
7. PFDL_Execute PFDL_Handler status return State transition diagram of Data Flash Library Type 04 To operate the data flash memory by using the PFDL the provided functions need to be executed sequentially Thereby the library state can be controlled A detailed description of each state is given below 1 uninitialized closed State at Power ON and Reset In this state the Pico FDL is disabled Please drive the library to this state via PFDL_Close whenever you want to e execute the Flash Self programming Library e run an EEPROM Emulation Library e use a Data Flash Library other than Type 04 PFDL or e utilize a STOP or HALT command Please note that the execution of PFDL_Close has to be completed before any of these listed actions can be taken e aa a ee User Manual RENESAS 2 opened State in which the PFDL_Open function has been executed from the uninitialized closed state and the Data Flash Library is operational 3 busy read State in which the specified processing is being executed directly by the library The control does not return to the user program until the processing is completed Please note that the transition to this state is only triggered by the read command in the PFDL 4 sequencer busy State in which the specified processing is being executed with the sequencer The PFDL_Execute function is used to trigger various commands to be executed on the data flash memory and returns to the user progr
8. express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 3 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part 4 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 5 When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations 6 Renesas Electronics has used reasonable care in
9. Definition Return Description value PFDL_OK 0x00 Normal completion PFDL_ERR_ PROTECTION 0x10 Reserved for future usage PFDL_ERR_ERASE Ox1A Erasure error e Erasure of the target area failed RO1US0055ED0112 Rev 1 12 ENESAS 26 User Manual Definition Return Description value PFDL_ERR_MARGIN 0x1B Blank check error or Internal verification error e The target area is not in the blank state e An error occurred during internal verification processing of the target area PFDL_ERR_WRITE 0x1C Writing error e Writing to the target area failed PFDL_IDLE 0x30 Idle state e No command is executed in the PFDL_Execute function PFDL_ BUSY OxFF Execution start of the PFDL_Execute function command or in execution e The command specified in the PFDL_Execute function is in execution Other than above Other Other error than e Anabnormal return value Check above the specified command or resource allocation again Table 3 7 List of structures Structure Member Description pfdl_request_t pfdl_ut6 index_u16 Target area e Erasure block number e Other start address of the target area pfdl_u08 data_pu08 near Pointer to the data buffer for acquisition of data to be written or read Only used for read write commands pfdl_ut6 bytecount_u16 Number of bytes to be transferred starting from the start byte specified in index_u16 The byte count range is from 1
10. Emulation Library or Data Flash Library other than Type 04 during the execution of the PFDL When using the Flash Self programming Library EEPROM Emulation Library or Data Flash Library other than Type 04 be sure to execute PFDL_Close to close the PFDL Do not execute the STOP command mode or HALT command mode during the execution of the PFDL If the STOP command or HALT command needs to be executed be sure to execute the PFDL_Close function to close the PFDL The watchdog timer does not stop during the execution of the PFDL Do not allocate any PFDL function argument data buffer or stack used by the Data Flash Library to an address over OXFFE20 or in the prohibited RAM area if existent for your target device When using the data transfer controller DTC during the execution of the PFDL do not allocate the RAM area used by the DTC to an address over OxFFE20 or in the prohibited RAM area if existent for your target device Do not use the RAM area including the prohibited RAM area used by the PFDL until the library is closed Do not execute a Data Flash Library function within interrupt processing because the PFDL does not support multiple executions of a Data Flash Library function When executing the PFDL within an operating system do not execute a Data Flash Library function from multiple tasks because the PFDL does not support multiple executions of a Data Flash Library function Before initiating any operation with t
11. RO1US0055ED0112 Rev 1 12 ENESAS 30 User Manual Note 1 Note 2 Note 3 Note 4 For the prohibited RAM area refer to the document User s Manual Hardware of your target RL78 microcontroller For details of the voltage mode refer to the user s manual of the target RL78 microcontroller It is a required parameter for timing calculation in the Flash Self programming Library This setting does not change the operating frequency of the RL78 microcontroller For the range of the maximum operating frequency refer to the document User s Manual Hardware of your target RL78 microcontroller RO1US0055ED01 12 Rev 1 12 ENESAS User Manual 31 3 6 2 PFDL_Close Outline Ends the operation of the Data Flash Library and drives it into closed state Interface C interface for CA78KOR compiler void far PFDL Close void C interface for IAR compiler _ far fune void PFDL Clos void C interface for GNU compiler void PFDL Closefvoid attribute section PFDL COD 7 C interface for CC RL compiler vid far PFOL Clos void 5 ASM function label for CA78KOR IAR GNU and CC RL assembler PFDL Close Arguments no parameters no return value Destructed registers Tool chain Destructed registers CA78KOR none IAR none GNU none CC RL C Preconditions Before the execution of this function the PFDL_Open function must have been completed normally
12. Registers Type Description CA78KOR IAR GNU CC RL R8 Status of operation can pfdl_status_t G A X bank 1 A be PFDL_BUSY or PFDL_OK RO1US0055ED0112 Rev 1 12 ENESAS 35 User Manual Destructed registers Tool chain Destructed registers CA78KOR AX IAR X GNU none CC RL X BC DE HL Preconditions Before the execution of this function the PFDL_Open function must be Description Table 3 8 completed normally Furthermore a running command must be finished via PFDL_Handler before it is allowed to call PFDL_Execute again Although it depends on the command which members of the request structure are necessary for the execution see Table 3 8 all members of the request variable must be initialized If there are any unused members in the request variable the user has to set arbitrary values to these members The PFDL_Execute function triggers the execution of the specified command on the data flash memory The available commands are listed in Table 3 8 Please note that except the read command all commands are propagated to the sequencer and executed in the background The final status of the execution needs to be checked via FDL_Handler A more detailed description of each command can be found in Section 3 7 Description of Data Flash Library Commands List of Execution Commands pfdl_command_t Command Value Description Reads the specified number of bytes from the specifie
13. and file structure updated regarding the CC RL Compiler 3 all Adding description of CC RL API 2 3 21 22 Caution chapter extended all all Renesas REN Compiler renamed to CA78KOR 3 5 3 6 3 all Byte count range specification added RO1US0055ED01 12 Rev 1 12 User Manual ENESAS 49 Data Flash Access Library ENESAS Renesas Electronics Corporation R01US0055ED0112
14. contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics RO1US0055ED0112 Rev 1 12 ENESAS User Manual Regional Information Some information contained in this document may vary from country to country Before using any Renesas Electronics product in your application please contact the Renesas Electronics office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country Visit http www renesas com to get in contact with your regional representatives and distributors RO1US0055ED0112 Rev 1 12 User Manual RENESAS Readers Purpose Organization
15. definition Compiler pfdl inc PFDL interface definition Assembler pfdl lib Pre compiled library lt root gt smp pfdl_sample_linker_file sub Sample linker file ENESAS 18 2 2 2 Prohibited RAM Area The PFDL may use a fraction of the user RAM as working area referred as prohibited RAM area The size and position of this area is strictly device dependent many devices do not even have this area and vary between the different RL78 products For details please refer to the document User s Manual Hardware of your RL78 product If a prohibited RAM area is specified for the utilized device it is not allowed to access this area while the PFDL is active Whenever PFDL functions are called the data in the prohibited area may be rewritten 2 2 3 Register Bank Remark The CA78KOR IAR and CC RL releases of the PFDL use the registers of the currently selected register bank No implicit register bank switch is performed by the library For the GNU release of the PFDL it is mandatory that register bank 0 is active on function entry No implicit register bank switch is performed by the library Return values are placed in register bank 1 For details on GNU calling conventions please refer to the GNU documentation for RL78 devices A detailed description of the registers used for parameter passing and return values can be found in Section 3 6 Description of Data Flash Library Functions 2 2 4 Stack and Data
16. of the user application while a read or write command accessing this buffer is still running User Manual 2 2 5 Data Flash Library Not all Data Flash Library functions are linked Only the really utilized Data Flash Library functions are linkeqNete e Memory allocation of the PFDL Segments are assigned to the functions and variables used in the PFDL The used areas of the PFDL can be mapped to specific locations For details refer to 3 2 Segments of Data Flash Library Functions Note For the CA78KOR and CC RL assembler linking can be reduced to a subset of the Data Flash Library functions by deleting unnecessary functions from the include file 2 2 6 Program Area This is the area in which the PFDL and the user program using the PFDL are located Utilizing the PFDL for the RL78 microcontroller the user program can be operated during rewriting of the Data Flash memory because the Data Flash memory is controlled by the sequencer in the background background operation For details refer to the sections of Chapter 3 Data Flash Library Function 2 2 7 Using the PFDL on the R5F10266 device For the R5F10266 device RAM is a scarce resource The device comes with 256 bytes RAM which cannot be used completely by the PFDL Hence special care has to be taken for a proper RAM usage by a dedicated linking method Note Due to the limited memory resource especially for the stack the usage of interrupts is prohibited for the R5F10266
17. preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 7 Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics RO1US0055ED0112 Rev 1 12 User Manual RENESAS 8 The quality grade of each Renesas Electronics product is Standard unless otherwi
18. update the library status In order to avoid unnecessary erase cycles the hardware sequencer is checking if the addressed block is already blank before starting the actual erase pulse generation After that the erase command is initiated and finally a block blank check is executed automatically This is repeated automatically as long the addressed block is not completely blank During the complete repetition process the Data Flash Library remains busy When the maximum internally specified number of erase retries is exceeded an error is returned to the requester Status returned by PFDL_Execute Status Class Background and Handling meaning request is being processed PFDL_BUSY normal reason request has been accepted remedy call PFDL_Handler until status changes Status returned by PFDL_Handler Status Class Background and Handling meaning request was finished regularly PFDL_OK normal reason no problems during execution remedy nothing at least one bit within the specified meaning block is not blank the block could not be erased for any bit in the addressed flash REDEE ERR ERAGE heavy reason block the margin for an erased cell is below the value required for full data retention remedy do not use the block anymore meaning request is being processed PFDL BUSY orma reason request has been accepted call PFDL_Handler until stat
19. 9 x BYTE_CT Write 487 folk 11 67 487 folk 11 67 212 fclk 39 17 x BYTE_CT 208 fclk 82 5 x BYTE_CT iverif 621 fcik 25 622 fclk 48 33 Y 23 fclk 3 33 x BYTE_CT 14 fclk 24 17 x BYTE_CT Read 44 fclk 44 fclk 14 fclk x BYTE_CT 14 fclk x BYTE_CT Maximum command execution times Full speed mode Wide voltage mode Command us Hs Erase 281561 fclk 264790 249000 fclk 299307 Blank check 1088 fclk 36 1084 fclk 75 6 fclk 0 31 x BYTE_CT 5 fclk 1 09 x BYTE_CT Write 585 fclk 14 585 fclk 14 714 fclk 430 x BYTE_CT 669 fclk 954 x BYTE_CT iverif 746 fclk 30 747 fclk 58 y 28 fclk 4 x BYTE_CT 17 fclk 29 x BYTE_CT Read 53 fclk 53 folk 17 fclk x BYTE_CT 17 fclk x BYTE_CT RO1US0055ED0112 Rev 1 12 User Manual ENESAS 48 Revision History Chapter Page Description All Initial document revision 1 00 Revision 1 01 2 2 17 Library stack consumption corrected 2 3 19 20 Extension of programming environment precautions Revision 1 10 All Adding description of GNU API 2 24 19 Extending usage description data buffer 2 2 7 20 Adding dedicated linking method for R5F10266 device 3 8 44 Adding maximum function execution times Revision 1 11 382 44 45 Adding typical and maximum command execution times Revision 1 12 2 2 17 Resource consumption
20. Buffer Remark The PFDL uses the sequencer to write to the code flash memory but it uses the CPU for pre setting and control Therefore the PFDL also utilizes the stack specified by the user program To allocate the stack and data buffer to the user specified address the link directive is used e Stack In addition to the stack used by the user program the stack space required for flash functions must be reserved in advance It has to be ensured that the stack is allocated so that the RAM used by the user will not be destroyed during stack processing of the PFDL The stack may not be allocated in the short address range from FFE20H to FFEFFH and also not in the prohibited RAM area if it exists in the target device For the actual stack space required for the Data Flash Library functions please refer to Table 2 1 e Data buffer The usage of the data buffer is described in following e Work area for internal processing of the PFDL e RAM area in which data is located that is to be written into the data flash e RAM area in which data is located that is to be obtained from the data flash The data buffer may not be allocated in the short address range from FFE20H to FFEFFH and also not in the prohibited RAM area if it exists in the target device Please note that the allocation and usage of the data buffer falls into the responsibility of the user Especially it has to be ensured that the data buffer is not touched by any other part
21. C Y D Dd ENESAS Data Flasn Access Library Type T04 Pico European Release 16 Bit Single chip Microcontroller RL78 Series Installer RENESAS _FDL_RL78_T04E_Vx xxx All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Technology Corp website http www renesas com Renesas Electronics RO1US0055ED01 12 Rev 1 12 www renesas com Dec 17 2014 Notice 1 All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website 2 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license
22. L_CMD_IVERIFY_BYTES command specified is called to perform internal verification of 1 to 1024 bytes for the specified address The processing cannot be executed across blocks lt 6 gt Reading 1 to 1024 bytes from the specified address PFDL_CMD_READ_BYTES command The PFDL_Execute function with the PFDL_CMD_READ_BYTES command specified is called to read 1 to 1024 bytes for the specified address All the processing of reading is executed within the PFDL_Execute function lt 7 gt Ending the PFDL operation The PFDL_Close function is called to end the operation of the PFDL lt 8 gt Status checking The PFDL_Handler function is called to perform status checking and drive a running command Status checking must be performed until the control to the data flash memory by the sequencer is finished User Manual Figure 1 2 S Begin of Data Flash control gt Y lt 1 gt PFDL_Open Y lt 2 gt PFDL_Execute BLANKCHECK command Note1 Status Busy lt 8 gt Busy Blank check error Status Normal completion Y lt 3 gt PFDL_Execute ERASE command Status Error check Normal completion lt 4 gt PFDL_Execute WRITE command Error lt 8 gt PFDL_Handler Busy LU Statue check e S Y
23. U tool chain Table 2 2 File structure for CA78KOR tool chain lt root gt release txt Library release notes lt root gt lib pfdl h PFDL interface definition Compiler pfdl_types h PFDL types definition Compiler pfdl inc PFDL interface definition Assembler pfdl lib Pre compiled library lt root gt smp pfdl_sample_linker_file dr Sample linker file ROIUSOOS5EDO112Rev 1 12 8 RENESAS 1 Table 2 3 Table 2 4 Table 2 5 RO1US0055ED01 12 Rev 1 12 File structure for IAR tool chain lt root gt release txt Library release notes lt root gt lib pfdl h PFDL interface definition Compiler pfdl_types h PFDL types definition Compiler pfdl inc PFDL interface definition Assembler pfdl r26 Pre compiled library lt root gt smp pfdl_sample_linker_file xcl Sample linker file File structure for GNU tool chain lt root gt release txt Library release notes lt root gt lib pfdl h PFDL interface definition Compiler pfdl_types h PFDL types definition Compiler pfdl_asm h PFDL interface definition Assembler pfdl a Pre compiled library lt root gt smp pfdl_sample_linker_file Id Sample linker file File structure for CC RL tool chain lt root gt release txt Library release notes lt root gt lib pfdl h PFDL interface definition Compiler pfdl_types h PFDL types
24. _WRITE_BYTES 0x04 Write command PFDL_CMD_IVERIFY_BYTES 0x06 Internal verification command RO1US0055ED0112 Rev 1 12 ENESAS 23 User Manual 3 4 Background Operation BGO The Data Flash Library functions can be divided into functions that do not use the sequencer and functions that use the sequencer For the functions that use the sequencerNte background operation BGO can be performed The following Figure 3 1 and Figure 3 2 show examples of operation of the PFDL during BGO Please note that especially for a write command it is mandatory to call the PFDL_Handler not only to check the command progress but also to drive the command Table 3 3 shows a list of the API functions with their relation to the sequencer control Note Not during the execution of the PFDL_CMD_ READ BYTES command Figure 3 1 Figure 3 2 RO1US0055ED01 12 Rev 1 12 User Manual For writing trigger processing with the PFDL_Handler is required for every byte Executing PFDL_Handler before the sequencer completes writing does not result in trigger processing End of processing User Library PFDL_Execute function executed Sequencer in operation Writing 1 byte PFDL_Execute function closed Return value PFDL_BUSY PFDL_Handler function executed PFDL_Handler function closed Writing trigger Return value PFDL_BUSY Writing of 1 byte completed PFDL_Handler function executed e Sequencer in op
25. ails The actual number of handler calls required to finish a command is not predictable as it depends on the type of command the parameters and the time interval between the calls User Manual Figure 2 2 a Crem 1 User program Pico FDL Sequencer oe d I I I PFDL_Execute i A trigger l ongoing busy l PFDL_Handler gt H trigger Segment in which the Data Flash memory GG cannot be referred to busy i l l I PFDL_Handler ei l trigger y finish raf OK Exemplary sequencer control via PFDL 2 1 1 Initialization Before accessing the Data Flash memory by using the PFDL the following settings need to be performed RO1US0055ED0112 Rev 1 User Manual Starting the high speed on chip oscillator During the usage of the PFDL keep the high speed on chip oscillator running When the oscillator is stopped start the oscillator before using the PFDL Setting the CPU operating frequency In order to perform the timing calculation used in the PFDL set the CPU operating frequency during the initialization A detailed description of the method that can be used to set the frequency can be found in Section 3 6 1 PDFL_Open Setting voltage modeN2 In order to specify the voltage mode when writing the data flash memory select one of the following modes during the initialization Full speed mode Wide voltage mode A detailed descript
26. al programming tool only via control code running on the microcontroller Sequencer Dedicated circuit controlling the flash memory integral part of RL78 device with data flash Serial programming The onboard programming mode is used to program the device with an external programmer tool SPL Flash Self programming Library All trademarks and registered trademarks are the property of their respective owners RO1US0055ED01 12 Rev 1 12 User Manual ENESAS User Manual Table of Contents Chapter 1 O PAAAA GEEEEReEEEeEEE 9 1 1 Important Terms ici iia ias 9 1 2 Basic E 10 1 2 1 Library States and Transiti0NS noonmnnnncccnnnicnnnscncrcc rr 10 1 2 2 Exemplary FIOW susi edad em 11 Chapter 2 Programming Environment cceeeeeeeeeeeeeeeeeeeeeeeees 14 2 1 Hardware Environment eweg 14 2 1 1 UE e TEE 15 KN WW E 16 2 2 Software Environment ccccceeeeeeeeeeeeeesesseeeeeeeseeeeeeesseeeeeeesseeeoeeseeeeeeeees 17 2 251 File StU CTU ss seed eege E A anaE diabeticas 17 2 2 2 TA AAA A 19 222 0 Register UE 19 2 2 4 Stack and Data Buffer cuida as 19 2 2 5 Data Flash Library ii ii 20 2 26 Program Area iii ia 20 2 2 7 Using the PFDL on the R5F10266 device cccsseseeccsseeneeeeseeeeeenseeneeenseeneesnseeneeeeseenenes 20 2 3 Cautions on the Programming Environment occccccccnnnnnnncnccnnnonennnnnnnananannns 21 Chapter 3 Data Flash Library Function o
27. am without waiting for the completion of the sequencer operation The current status of a running operation in the sequencer can be checked and driven forward with the PFDL_Hander function 1 2 2 Exemplary Flow Figure 1 2 shows an example of the data flash memory rewriting flow by using the PFDL In the following a more detailed description is given of the illustrated steps lt 1 gt Initializing the PFDL The PFDL_Open function is called to initialize the RAM used for the PFDL and to enable the library lt 2 gt Blank checking 1 to 1024 bytes for the specified address PFDL_CMD_BLANKCHECK_BYTES command The PFDL_Execute function with the PFDL_CMD_BLANKCHECK_BYTES command specified is called to perform blank checking of 1 to 1024 bytes for the specified address The processing cannot be executed across blocks lt 3 gt Erasing the specified block 1 KB PFDL_CMD_ERASE_BLOCK command The PFDL_Execute function with the PFDL_CMD_ERASE_BLOCK command specified is called to erase the specified block 1 KB lt 4 gt Writing 1 to 1024 byte data to the specified address PFDL_CMD_WRITE_BYTES command The PFDL_Execute function with the PFDL_CMD_WRITE_BYTES command specified is called to write 1 to 1024 bytes to the specified address The processing cannot be executed across blocks lt 5 gt Internal verification of 1 to 1024 bytes for the specified address PFDL_CMD_IVERIFY_BYTES command The PFDL_Execute function with the PFD
28. ase follow the suggested sequence of es blankcheck e write e iverify as exemplarily shown in Figure 1 2 in order to ensure full data retention Status returned by PFDL_Execute Status Class Background and Handling meaning request is being processed PFDL_BUSY normal reason request has been accepted remedy call PFDL_Handler until status changes Status returned by PFDL_Handler Status Class Background and Handling meaning request was finished regularly PFDL_OK normal reason no problems during execution remedy nothing at least one byte could not be meanin H written correctly for any bit of the written area the reason margin for written data is below the PFDL_ERR_WRITE heavy value required for full data retention erase the block and try to write again caution erase operates block wise ensure to safe other data stored in the block remedy meaning request is being processed PFDL_ BUSY normal reason request has been accepted call PFDL_Handler until status remedy changes R01US0055ED0112 Rev 1 12 ENESAS User Manual 3 7 5 PFDL_CMD_ERASE_BLOCK The erase command is used to erase one block of the data flash The command is initiated by PFDL_Execute and is executed by the sequencer to perform the physical erase After the erase command has been initiated PFDL_Handler shall be called to complete it and to
29. ata Flash Library functions Type of Data Flash Library Functions The PFDL provides the following flash functions as listed in Table 3 1 List of Data Flash Library functions Function name Description Initialization of the RAM used by the PFDL enabling of the PFDL_Open Data Flash clock Ending the operation of the PFD disabling of the Data PFDL_Close Flash clock Triggering and execution of commands on the Data Flash PFDL_Execute memory Checking of the current status of a running Data Flash PFDL_Handler operation and driving the command forward status check processing PFDL_GetVersionString Acquisition of the version information of the PFDL Segments of Data Flash Library Functions The Data Flash Library functions are located in the following segment e PFDL_COD Segment of the Data Flash Library functions It can be allocated to the ROM or RAM Commands All flash operations are issued in the PFDL via the PFDL_Execute function The command specified as argument of PFDL_Execute determines the type of the flash operation Table 3 2 lists all available commands For details on the execution method please refer to Section 3 6 3 List of commands specified for PFDL_Execute pfdl_command_t Definition Value Command name PFDL_CMD_READ_ BYTES 0x00 Read command PFDL_CMD_BLANKCHECK_BYTES 0x08 Blank check command PFDL_CMD_ERASE_ BLOCK 0x03 Erasure command PFDL_CMD
30. ata flash of the RL78 device is activated PFDL_Open reserves and initializes the prohibited RAM areaNote 1 used for the PFDL If a prohibited RAM areaNote 1 exists do not use it until the PFDL is closed For correct operation the voltage modeNete2 of the PFDL needs to be specified in the wide_voltage_mode_u08 structure member of the argument pfdl_descriptor_t e QOH Full speed mode e 01H Wide voltage mode Furthermore the operating frequency of the CPU needs to be set in the fx_MHz_u08 structure member of the argument pfdl_descriptor_t This parameter is used for the calculation of timing data in the PFDLNote3_ For the value of the operating frequency of the CPU fx_MHz_u08 note the following e When a frequency below 4 MHzNete 4 is used as the operating frequency of the RL78 microcontroller only integer frequencies 1 MHz 2 MHz or 3 MHz can be used Frequencies with decimal fraction e g 1 5 MHz are not supported The value of fx_MHz_u08 has to match the actual operating frequency of the device e When a frequency over 4 MHzNote 4 is used as the operating frequency of the RL78 microcontroller a frequency with decimal franction can be used However the fx_MHz_u08 parameter for PFDL_Open needs to be set to the corresponding rounded up integer in this case Example For 4 5 MHz set a value of 5 with the initialization function e The operating frequency is not the frequency of the high speed on chip oscillator
31. ata retention e Sequencer The RL78 microcontroller features a dedicated circuit for controlling the flash memory In this document this circuit is called sequencer e Background operation BGO State in which rewriting of the flash memory can be done while operating the user program by letting the sequencer control the flash memory For a more detailed description please refer to 2 1 Hardware Environment and 3 4 Background Operation BGO e Status check Using the sequencer in BGO requires to check the state of the sequencer state of control for the flash memory within the program controlling the flash memory In this document the processing to check the state of the sequencer is called status checking RO1US0055ED0112 Rev 1 12 ENESAS User Manual 1 2 Basic Workflow In order to perform rewriting of the data flash memory with the PFDL the initialization process for the library needs to be executed first Afterwards the actual accesses to the data flash can be performed by means of dedicated API functions The PFDL provides APIs for the C and assembly language of the CA78KOR IAR GNU and CC RL tool chains 1 2 1 Library States and Transitions During operation the PFDL passes through several states as illustrated in the diagram presented in Figure 1 1 Figure 1 1 __ Reset or Power ON gt PFDL_Open PFDL_Close PFDL_Execute read command only return status
32. byte to 1024 bytes Please note that the execution of the read write blankcheck internal verify command across block boundaries is not allowed This struct member is not required for the erase command pfdl_command_t command_enu Command to be executed pfdl_descriptor_t pfdl_u08 fx_MHz_u08 CPU frequency pfdl_u08 Voltage mode setting wide_voltage_mode_u08 RO1US0055ED0112 Rev 1 12 User Manual ENESAS 27 3 6 Outline Interface Arguments Precondition Description of Data Flash Library Functions The flash functions are described in the following format Describes the purpose of the function Describes the C interfaces and assembler labels required to access the function Describes the parameters return values and register usage of the function Describes the conditions that have to be fulfilled before calling the function Description Describes the function details and cautions of this function RO1US0055ED0112 Rev 1 12 ENESAS User Manual 28 3 6 1 PDFL_Open Outline Initialization of all internal data and activation of the data flash Interface C interface for CA78KOR compiler pfdl_ status t Zar PFDL Open _ near pfdl descriptor t descriptor psti C interface for IAR compiler _ far func pfidl status t PFDL Open near pidl descriptor E _ mear descriptor pstr C interface for GNU compiler ptal status t PFDL Open prdl descrip
33. d starting addressN in the data flash memory and places it in the read data input buffer The following arguments must be set for execution PFDL_CMD_READ_BYTES 0x00 Sr pial request tinda ulo Reading start addressNote2 e pfdl_request t bytecount_u16 Read size e pfdl_request t data_pu08 Address of the read data input buffer Performs blank checking from the specified beginning addressNote2 of the data flash memory for the area in the execution range The following arguments are usegNotes PFDL_CMD_BLANKCHECK_BYTES 0x08 e pfdl_request_t index_u16 Start addressNote2 e pfdl_request t bytecount_u16 Execution range from the start addressNotet Performs erasure for the block of the specified number in the data flash memory PFDL_CMD_ERASE_BLOCK 0x03 The following arguments are usegNotes e pfdl_request_t index_u16 Block number RO1US0055ED0112 Rev 1 12 ENESAS User Manual 36 Command PFDL_CMD_WRITE_BYTES Value 0x04 Description Writes the data placed in the write data input buffer to the data flash memory at the specified starting addressNote2 for the specified number of bytes The following arguments must be set for execution e pfdl_request_t index_u16 Write start addressNote2 e pfdl_request t bytecount_u16 Write sizeNote1 e pfdl_request t data_puo Address of the write data input buffer PFDL_CMD_IVERIFY_BYTES 0
34. device when the PFDL is used Table 2 6 shows the usage for the different RAM areas on the R5F10266 device when using the PFDL Table 2 6 RAM usage for R5F10266 when using PFDL Address Size ae Are eee range byte Description Usage and Limitations OxFFEOO 32 Free area Please allocate your PFDL function OxFFE1F arguments and data buffers in this area OxFFE20 130 Short address Do not allocate any PFDL function OxFFEA1 area argument data buffer or stack in this area OxFFEA2 62 Stack allocation Please allocate the stack into this area OxFFEDF area when using R5F 10266 Please ensure that the stack does not exceed this area including library and user application see also Table 2 1 OxFFEEO 32 General purpose Do not allocate any PFDL function OxFFEFF register area argument data buffer or stack in this area RO1US0055ED0112 Rev 1 12 ENESAS 20 User Manual 2 3 Cautions on the Programming Environment 10 11 12 13 14 15 Library code must be located completely in the same 64k flash page The PFDL library initialization by PFDL_Open must be performed before the execution of PFDL_Close PFDL_Execute PFDL_Handler It is not allowed to read the data flash during a command execution of the PFDL It is not possible to modify the Data Flash in parallel to a modification of the Code Flash Do not execute the Flash Self programming Library EEPROM
35. egularly PFDL_OK normal reason no problems during execution remedy nothing at least one bit within the specified meanin A 9 area is not blank for any bit of the checked area the reason margin for an erased cell is below PFDL_ERR_MARGIN light the value required for full data retention no general remedy the requester remedy has to decide how to react based on the application meaning request is being processed PFDL BUSY normal reason request has been accepted call PFDL_Handler until status deit changes RO1US0055ED0112 Rev 1 12 ENESAS User Manual 3 7 4 PFDL_CMD_WRITE_BYTES The write command is used to write a number of bytes located in the RAM into the data flash at the location specified by the virtual addresses relative address that starts from block 0 of the data flash memory as address 0 The write command is initiated by PFDL_Execute and is executed by the sequencer to perform the physical write After the write command has been initiated PFDL_Handler shall be called to complete it and to update the library status When a write command is issued the sequencer generates a write pulse In case of a fail the write pulse is repeated During write pulse repetition the library state remains busy In case the write process fails after the maximum internally specified number of retries an error is returned by a PFDL_Handler call Note For a regular write ple
36. enseeneesnseeeenenseesenes 47 RO1US0055ED0112 Rev 1 12 ENESAS Chapter 1 Overview A Data Flash Library FDL is a software library to perform operations on the data flash memory on the RL78 microcontroller The library described in this manual RL78 Data Flash Library Type 04 offers a minimal set of features and aims at very resource critical systems It is referred to as Pico FDL PDFL throughout this document Please use this Data Flash Library user s manual together with the user s manual of the target RL78 microcontroller 1 1 Important Terms The following important terms and definitions are used throughout this manual e Data Flash Library FDL Library for data flash memory operations utilizing the features provided by the RL78 microcontroller family The library cannot operate on the code flash memory e Flash Self programming Library SPL Library for code flash memory operation utilizing the features provided by the RL78 microcontroller Operations on the data flash memory cannot be performed e EEPROM Emulation Library Library that provides functions to store data in the built in flash memory in an EEPROM like fashion e Block number Number that identifies a block of the flash memory It is the unit of erasure operations in the Data Flash Library Type 04 e Internal verification Is used to check if the signal level of the flash memory cell is appropriate after writing to the flash memory in order to ensure full d
37. eration Writing 1 byte PFDL_Handler function closed Return value PFDL_BUSY Writing of 2 bytes completed PFDL_Handler function executed PFDL_Handler function closed Writing trigger Return value PFDL_BUSY Sequencer in operation Writing 1 byte Writing of all 3 bytes completed PFDL_Handler function executed PFDL_Handler function closed Return value PFDL_OK Background operation example 1 write 3 byte RENESAS a The control returns immediately so other processing can be executed The state must be checked until the completion Not during the execution of the PFDL_CMD_READ_ BYTES command End of processing User q Library PFDL_Execute function executed PFDL_Execute function closed Return value PFDL_BUSY PFDL_Handler function executed Sequencer in operation PFDL_Handler function closed Return value PFDL_BUSY PFDL_Handler function executed PFDL_Handler function closed Return value PFDL_OK Background operation example 2 erase iverify blankcheck Table 3 3 List of interrupt reception and BGO of Data Flash Library functions F Sequencer control S Function name BGO function Interrupt reception PFDL_Open No PFDL_Close PFDL_Execute Allowed YesNote PFDL_Handler PFDL_GetVersionString No Note Not during the execution of the PFDL_CMD_READ_BYTES command RO1US0055ED01 12 Rev 1 12 User Manual ENESAS 25 3 5 Lis
38. fclk 443 779 fclk 968 PFDL_GetVersionString 10 fclk 10 fclk Note The execution times listed in Table 3 9 refer to the function call only and not the total time required to complete a command The execution of erase blank check write and iverify commands is only initiated by PFDL_Execute and needs to be completed with successive calls of PFDL_Handler see also Section 3 4 3 8 2 Command Execution Times The command execution times are listed in the following tables These timings are divided into the typical timings which will appear during the normal operation Table 3 10 and the maximum timings for worst case considerations Table 3 11 All given timings are based on the assumption that the command is executed with continuous PFDL_Handler calls In case the handler is called too seldom execution time might increase RO1US0055ED01 12 Rev 1 12 RENESAS 47 User Manual at Table 3 10 Table 3 11 Please note that the command execution times may depend on e the operating mode full speed or wide voltage e the used clock frequency given as fclk in MHz and e the byte count for the triggered operation referred to as BYTE_CT Typical command execution times Full speed mode Wide voltage mode Command us us Erase 11250 fclk 5800 9925 fclk 7195 Blank check 906 fclk 30 903 fclk 62 5 5 fclk 0 26 x BYTE_CT 4 fcik 0
39. he PFDL the high speed on chip oscillator needs to be started Note the following regarding the operating frequency of the RL78 microcontroller and the operating frequency value set with the initialization function PFDL_Open e When a frequency below 4 MHzNte1 is used as the operating frequency of the RL78 microcontroller 1 MHz 2 MHz or 3 MHz can be used a frequency such as 1 5 MHz that is not an integer value cannot be used Also set an integer value such as 1 2 or 3 as the operating frequency value set with the initialization function e When a frequency over 4 MHzNote is used as the operating frequency of the RL78 microcontroller a frequency with decimal places can be used However specify a rounded up integer value as the operating frequency set with the initialization function PFDL_Open Example For 4 5 MHz set 5 with the initialization function e The operating frequency is not the frequency of the high speed on chip oscillator The PFDL does not perform error checking of the parameters set in the argument of a Data Flash Library function Therefore make sure to set a User Manual 16 17 18 19 correct value to the parameter after checking the specifications of the target RL78 microcontroller If parameter checking is required to set a correct value perform it in the user program Please initialize all function arguments including unused structure elements at least once before calling a functi
40. id to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details 2 List of Abbreviations and Acronyms Abbreviation Full Form API Application programming interface BGO Background operation Flash Area Area of Flash consists of several coherent Flash Blocks Code Flash Embedded Flash where the application code or constant data is stored Embedded Flash where mainly the data of the EEPROM Data Flash E emulation are stored Instance of data written to the Flash by the EEPROM Data Set Emulation Library EEL identified by the Data Set ID DS Data Set Dual operation is the capability to access flash memory during reprogramming another flash memory range Dual operation is available between Code Flash and Data Flash Between different Code Flash macros dual operation depends on the device implementatio Dual Operation ECC Error correction code EEL EEPROM Emulation Library EEPROM Electrically erasable programmable read only memory In distinction to a real EEPROM the EEPROM emulation uses some portion of the flash memory to emulate the EEPROM behavior To gain a similar behavior some side parameters have to be taken in account EEPROM emulation
41. ion of the method that can be used to set the voltage mode can be found in Section 3 6 1 PDFL_Open 12 15 ENESAS Note 1 The CPU operating frequency is used for the parameters of the timing calculation within the PFDL The actual frequency of the processor core is not changed Note 2 For the details of the voltage mode see the target RL78 microcontroller user s manual 2 1 2 Blocks The flash memory of the RL78 microcontroller is divided into 1 KB blocks In the Data Flash Library erasure processing is performed for the data flash memory in the units of the blocks Reading writing blank checking or internal verification are performed on byte flash memory granularity and require the specification of start addressNote and size Figure 2 3 shows an example of block positions and block numbers of the data Note The address value is used when reading writing data from to the flash memory The address is specified relative to the first element of block 0 of the data flash memory Note that the specified address is not an absolute address Figure 2 3 Special function register SFR General register Internal high speed RAM Mirror F17FFH Data flash memory 2 KB a AER Not used Special function register 2nd SFR F1000H Not used Code flash memory KA 1 KB 2 blocks 07FFH Data flash memory User program Block 1 Flash data library 00000H Absolute address 0400H Data flash me
42. ll can be requested by using the PFDL_Execute function Note All commands operate on virtual addresses relative address that starts from block 0 of the data flash memory as address 0 and block numbers 3 7 1 PFDL_CMD_READ BYTES The read command is used to read a number of bytes from data flash It is the only command that does not need the sequencer It is initiated and finished directly by PFDL_Execute Status returned by PFDL_Execute RO1US0055ED01 12 Rev 1 12 User Manual Status Class Background and Handling meaning request was finished regularly PFDL_OK normal reason no problems during command execution occurred remedy nothing ENESAS 42 3 7 2 PFDL_CMD_IVERIFY_BYTES The internal verify operation is used to check if all bits 0 s and 1 s provide full data retention Inconsistent and weak data caused by an asynchronous reset during a write command can be detected using the iverify command on that specific data range The iverify command is initiated by PFDL_Execute and is executed by the sequencer After that PFDL_Handler shall be called to complete the command and check the PFDL status Status returned by PFDL_Execute Status Class Background and Handling PFDL_BUSY normal meaning request is being processed reason request has been accepted remedy call PFDL_Handler until status changes Status returned by PFDL_Handler
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44. mory Block 0 Blocks of Data Flash Memory here RL78 G12 with 2 KB Data Flash 0000H Relative address RO1US0055ED0112 Rev 1 12 User Manual ENESAS 16 User Manual 2 2 Software Environment The PFDL is allocated together with the program in the user area occupying an area equal to the size of the library Furthermore the library itself uses the CPU the stack and a data buffer Detailed information about the required software resources is listed in Table 2 1 Table 2 1 Resource consumptionN te CA78KOR IAR GNU CC RL Max code size program area 175 bytes 180 bytes 199 bytes 168 bytes Constants program area Internal data Note2 Note2 Moie _Note2 Max stack consumption 46 bytes 46 bytes 50 bytes 40 bytes Notei All values for resource consumption are based on PFDL version V1 04 Note2 Depending on the used device the PFDL may use a fraction of the user RAM as working area Size and location of this area is strictly device dependent see Section 2 2 2 for more details 2 2 1 File Structure The actual file structure for the Data Flash Library T04 depends on the utilized tool chain and is listed separately for CA78KOR IAR GNU and CC RL in Table 2 2 Table 2 3 and Table 2 4 respectively Please note that assembler header files for GNU use the same extension bh as C header files because the C preprocessor can and should be used for assembler files in the GN
45. on Otherwise a RAM parity error may cause a reset of the device For details please refer to the document User s Manual Hardware of your RL78 product Do not write to a data flash cell that is not erased It is prohibited to rewrite a data flash cell without erasing the corresponding data flash block first The PFDL does not contain any sanity checks to prevent such a situation The user is responsible to ensure the compliance of this rule The data flash control register DFLCTL should not be operated during the execution of the PFDL In addition when the operation of the PFDL is ended the DFLCTL is set to access inhibit state by the PFDL_Close function If accessing the data flash memory is required even after the operation of the PFDL is ended verify the completion of the PFDL_Close function set the DFLCTL to the access permit state and perform the setupNote2 After the execution of PFDL_Close all requested running commands will be aborted and cannot be resumed The user has to take care that all running commands are finished before calling PFDL_Close Note 1 For the range of the operating frequency see the target RL78 microcontroller user s manual Note 2 For the method of the setup see the target RL78 microcontroller user s manual RO1US0055ED01 12 Rev 1 12 ENESAS User Manual 22 Chapter 3 3 1 Table 3 1 3 2 3 3 Table 3 2 Data Flash Library Function This chapter describes the details of the D
46. ooomonnnnnnnnnnccncnnnnncnnananannnos 23 3 1 Type of Data Flash Library Functions ccccccnnnncnnccccncncncnonnnnnnancccnnnnnonnnnnnnas 23 3 2 Segments of Data Flash Library FunctiONS ooocccccccnnnnnncnaccccnonononnnnnnanancnns 23 o E e FE 23 3 4 Background Operation BGOk ee 24 3 5 List of Data Types Return Values and Return Types ecceeeeesseees 26 3 6 Description of Data Flash Library Functions cccsssseeeeeeeeeeeeeeeeeeeeeees 28 301 PDFE Oper cn dai 29 36 2 PRD Cl ci crass nesta wis nee 32 3 6 3 REDER AEN 34 364 PER Handler sssaaa AS 38 3 6 5 PFDL_GetVersiomStritng ecccccccssscceseeeeeseeeesseceseeeseseeeeeseeessaeseseeeenseaesenesessaesnseeeeneneess 40 3 7 Description of Data Flash Library COMMANdS oooooocccccccccnnnnnnnancccnnnnnenenananas 42 3 7 1 PFDL_CMD_READ_BYTEG s ssssssssssssssssssssssssssssssseceeseoeseoeoeoeoessseseaeaeaeatesseseseess 42 3 7 2 PFDL_CMD_IVERIFY_BYTEG s sssssssssssssssssssssssscsssceeeeoeoeoeoeososseeeaeacataeatersssessess 43 3 7 3 PFDL_CMD_BLANKCHECK_BYTES ssssssssssssesesesssssssessecasasasacasasacacacacacacesesesssess 44 3 7 4 PFD CMD WRITE EECHER 45 375 PER CMD ERASE BLOCK icons is sd 46 3 8 Library TIMINGS sst aia aE aa eiea aTi 47 3 8 1 Maximum Function Execution Times 0ooooccccccnnnnnnonnccnnnnnnnnnnaocn cn nn nn cnc 47 3 8 2 Command Execution Times cccceseceeessseceenseeeeeenseneeeenseseeeenseeee
47. ring void _ attribute section PFDL COD C interface for CC RL compiler _ far pfdl u08 far PFDL GetVersionString void ASM function label for CA78KOR IAR GNU and CC RL assembler PFDL GetVersionString Arguments Parameters none Return value Registers Type Description CA78KOR IAR GNU CC RL Beginning address 24 bit of the pfdl_u08 R11 R8 area where the version far DE BC A HL BC AX A DE information of the PFDL is bank 1 stored as 0 terminated ASCII string Destructed registers none RO1US0055ED0112 Rev 1 12 ENESAS 40 User Manual are Preconditions none Description The function PFDL_GetVersionString can be used to obtain the version information of the utilized library The version string is given in the following format DRL78T04cxx xyabc where e c codes the target compiler for the used library R for CA78KOR I for IAR U for GNU and L for CC RL e xx x codes the information about the used compiler version and memory model the length can be between 4 and 5 digits depending on the compiler and release date of the library e y identifies the release type V for release E for engineering version e abc specifies the library version as Va bc RO1US0055ED01 12 Rev 1 12 ENESAS User Manual 41 3 7 Description of Data Flash Library Commands The PFDL offers a set of commands that a
48. rol the Data Flash memory As the sequencer has the direct control to the data flash memory the user program can be operated in parallel to the data flash memory control This is called BGO background operation During rewriting of the data flash memory the data flash memory is blocked for other accesses However the code flash memory can be accessed so interrupt processing the user program and the PFDL can be allocated in the ROM for operation as usual The access restrictions during data flash operations are depicted in Figure 2 1 Figure 2 1 On chip RAM Reading cannot be Data flash memory X executed during data flash memory control The user program can operate as usual with the BGO back gt ground operation during data flash memory control Code flash memory Interrupts can be used as gt usual Access restrictions during Data Flash operation Figure 2 2 shows an example of execution of the Data Flash Library function to perform rewriting of the data flash memory After an execution request has been send to the sequencer of the RL78 microcontroller via the PFDL API the control is immediately returned to the user program For the current state and result of the issued FDL command the status check function PFDL_Handler function must be called repeatedly from the user program Please note that there are commands which require a calling PFDL_Handler to drive the command execution see Section 3 4 for det
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50. specifying renuesi petr t_t near AX AK Stack AX the flash command to be executed User Manual Structures Structure Member Description Target area e Erasure block number e Other start address 2 of the target area pfdl_u16 index_u16 Pointer to the data buffer for pfdl_u08 data_pu08 acquisition of data to be written or near readNote1 pfdl_request_t Only used for read write commands Range of the command specified in bytesNote1 starting from the specified pfdl_u16 bytecount_u16 start addressNote 2 Not required for erase commands pfdl_command_t Command to be executed command_enu Note 1 Specify only for commands requiring the target parameter if not required initialize with arbitrary value The byte count range is from 1 byte to 1024 bytes Provide the data buffer size for the number of bytes of the data to be written or read Please note that the specified range may not cross block and has to be specified within one block Note 2 The specified address is the relative address that starts from block 0 of data flash memory as address 0 This is not the absolute address Figure 3 3 Absolute address Relative address F1FFFH Seen B 3 1 2 Gon Address to be specified 0000H when using the PFDL GC 1 Blocko 0 F1000H Address specification for commands executed via PFDL_Execute Return value
51. t of Data Types Return Values and Return Types The data types are listed in Table 3 4 The return types are specified in Table 3 5 while the meaning of each return value is given in Table 3 6 Table 3 4 List of data types Definition Data type Description pfdl_u08 unsigned char 1 byte 8 bit unsigned integer pfdl_u16 unsigned int 2 byte 16 bit unsigned integer pfdl_u32 unsigned long int 4 byte 32 bit unsigned integer set of 1 byte 8 bit unsigned integer pial status t enumeration ype constants see also Table 3 6 set of 1 byte 8 bit unsigned integer pfdl_command_t enumeration type constants Mote see also Table 3 2 structure to specify requests to be pfdl_request_t structure executed on the data flash Note 1 see also Table 3 7 structure to specify the configuration for pfdl_descriptor_t structure library initialization Note 2 see also Table 3 7 Note 1 A detailed description can be found in Section 3 6 3 PFDL_Execute Note 2 A detailed description can be found in Section 3 6 1 PDFL_Open Table 3 5 List of return types Return value C language Assembly language pfdl_status_t C CA78KOR _ far pfdl_u08 DE BC pfdl_status_t A IAR pfdl_u08 _ far A HL Did status R8 X on bank 1 GNU pfdl_u08 Tor R11 R8 BC AX on bank 1 Did status A CC RL ___far pfdl_u08 A DE Table 3 6 List of pfdl_status_t values
52. tor t descriptor pstr _ Sttribute seccion PFDL COD C interface for CC RL compiler pfdl status t Zar PFDL Open __near pfdl descriptor t descriptor pstre ASM function label for CA78KOR IAR GNU and CC RL assembler PFDL Open Arguments Parameters Registers Argument Type Description CA78KOR IAR GNU CC RL address of the descriptor variable pfdl_desc l ocated in the RAM descriptor Gett er AX AX stack AX defines voltage mode and CPU frequency Structures Structure Member Description pfdl_u08 fx_MHz_u08 CPU frequency pfdl_descriptor_t pfdl_u08 wide_voltage_mode_u08 Voltage mode setting RO1US0055ED0112 Rev 1 12 ENESAS 29 User Manual Return value Registers Type Description CA78KOR IAR GNU CC RL R8 Status of operation pfdl_status_t C A X bank 1 A PFDL_OK only possible value Destructed registers Tool chain Destructed registers CA78KOR AX IAR X GNU none CC RL X HL C Preconditions The following conditions need to be ensured before using PFDL_Open e The Flash Self programming Library the EEPROM Emulation Library or any Data Flash Library other than Type 04 are not running or have been closed e The high speed on chip oscillator is running Description By calling PFDL_Open the Data Flash Library is put into operational state and the d
53. us changes remedy R01US0055ED0112 Rev 1 12 User Manual RENESAS 3 8 Library Timings In the following certain timing characteristics of the Pico FDL are specified All timing specifications are based on the RL78 FDL T04 V1 04 V1 05 Please note that there might be deviations from the specified timings in case you are using other library versions 3 8 1 Maximum Function Execution Times The maximum function execution times are listed in Table 3 9 These timings can be seen as worst case durations of the specific PFDL function calls and therefore can aid the developer for time critical considerations e g when setting up the watchdog timer Please note that the function execution times may depend on e the operating mode full speed or wide voltage e the used clock frequency given as fclk in MHz and e the byte count for the triggered operation referred to as BYTE_CT Table 3 9 Maximum function execution times Full speed mode Wide voltage mode Function Command us us PFDL_Open 862 fclk 862 fclk PFDL_Execute erase Note 536 fclk 536 fclk PFDL_Execute blank check Note 484 fclk 484 fclk PFDL_Execute write Note 549 fclk 549 fclk PFDL_Execute iverify Note 502 fclk 502 fclk 53 fclk 53 fcik PEDE Execute 1690 17 fclk x BYTE_CT 17 fclk x BYTE_CT PFDL_Handler 251 fclk 14 251 folk 14 PFDL_Close 823
54. x06 Performs internal verification starting from the specified beginning addressNote2 of the data flash memory for the area in the execution range The following arguments are useqNotes e pfdl_request_t index_u16 Start addressNote2 e pfdl_request t bytecount_u16 Execution range from the start addressNotel Note 1 Cannot be specified across blocks Specify it within one block Note 2 The specified address is the relative address that starts from block 0 of the data flash memory as address 0 when writing and reading the memory Note that the specified address isn t an absolute address Note 3 All members of the request variable must be initialized Unused members in the request variable can be set to arbitrary values RO1US0055ED0112 Rev 1 12 User Manual ENESAS 37 3 6 4 PFDL_Handler Outline Checking of the current processing state of a previously issued command and driving the command forward especially in case of a write command Interface C interface for CA78KOR compiler ptal status t _ far PFDL Handler void C interface for IAR compiler _ far fune pfdl status t PFDL Handler void C interface for GNU compiler pfdl_status_t PFDL Handler void _ attributs isectaon PEDL COD C interface for CC RL compiler pfdl status t Zar PFDL Handler void ASM function label for CA78KOR IAR GNU and CC RL assembler PFDL Handler Arguments Parameters none
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