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Correction for Incorrect Description Notice RL78/I1A Descriptions in

1. Edge Timer restart request signal detector timers KBO to KB2 INTP21 P11 D 1 Do External interrupt control register INTPCTL INTP20 Edge detector External interrupt edge enable register EGP2 EGN2 Timer output forced stop request signal timers KBO to KB2 7 INTP21 vv Comparator 0 Comparator rising edge enable register CMPEGPO gt Comparator falling edge enable register CMPEGNO CEGPO CEGNO 0 CMPOoutput Edge INTCMPO lefector 1 dz Timer output forced stop request signal timers KBO to KB2 CMPOSTEN CMPOP ANI2 P22 pad CODFS1 CMPMONO Comparator 0 control register COCTL Comparator output Na monitor register CMPMON _ INTCMP1 Timer restart request signal timer KBO Timer output forced stop request signal timer KBO Edge detector Comparator 1 CMP1P ANI4 P24 8 3 3 3 WCSELO bit Selector VAY AY EYE CMP2STEN INTCMP2 parator 2 CMP2P ANIS P25 Edge Timer restart request signal detector timer KB1 WCSEL1 bit Timer o
2. Operable Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Wakeup operation is enabled switching to the SNOOZE mode Programmable gain amplifier Operable Comparator Only CMPO and CMP2 are operable when the STOP mode cancel is set CMPnSTEN 1 in the PFSELO register by the comparator interrupt detection and the noise filter is not used n 0 2 Omitted zu Page 33 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 13 Table 21 3 Operating Statuses in SNOOZE Mode Incorrect description about the comparator operation in SNOOZE mode is revised Incorrect STOP Mode Setting When Inputting CSIOO UARTO Data Reception Signal or A D Converter Timer Trigger Signal While in STOP Mode When CPU Is Operating on High speed On chip Oscillator Clock fiu System clock Clock supply to the CPU is stopped Main system clock Operation started Stopped Subsystem clock Use of the status while in the STOP mode continues fit Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Use of the status while in the STOP
3. Function Control Register 2p TKBPACTL2p 1 2 Address FO6BOH TKBPACTL20 F06B2H TKBPACTL21 After reset 0000H R W gSymbol 15 14 13 12 11 10 9 8 TKBPACTL2p TKBPAFXS2p3 TKBPAFXS2p2 TKBPAFXS2p1 TKBPAFXS2p0 amp x d uw j TKBPAFCM2p 7 6 5 4 3 2 1 0 0 ePAHzsopa TKBPAHZS2p1 TKBPAHZS2p0 TKBPAHCM2p1 TKBPAHCM2p0 TKBPAMD2p1 TKBPAMD2p0 TKBPAFXS2p3 External interruption trigger selection for forced output stop function 2 oo INTP20 can not be used as a trigger TKBPAFXS2p2 Comparator trigger selection for forced output stop function 2 o Comparator 5 can not be used as a trigger 1 Comparator 5 can be used as a trigger TKBPAFXS2p1 Comparator trigger selection for forced output stop function 2 EE Comparator 3 can not be used as a trigger TKBPAFXS2p0 Comparator trigger selection for forced output stop function 2 oo Comparator 0 can not be used as a trigger TKBPAFCM2p Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period 1 Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger R Page 13 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TK
4. Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation SroPmode sNoozEmoe mode SNOOZE mode Normal operation 4 SS01 3 lt 12 gt STO lt 1 eC SEO1 jg ee SWCO 11 EOCO il L SSECO L Clock request signal internal signal Receive data 2 SDRO1 1 Recevedta1 y data 1 poA Read e RxDO pin ST Receive data 1 X P SP ST Receive data2 X P SP Shift register 01 XX Shift operationX X M T X X Shift operation X INTSRO INTSREO L Data reception lt 7 gt Data reception TSF01 Correct Figure 15 90 Timing Chart of SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation sroPmode sNoozbEmoe mode SNOOZE mode Normal operation 4 SS01 STO1 1 SE01 SWCO EOC01 L SSECO L Clock request signal internal signal Receive data 2 SDR01 XO o o Recivedaa1 JJ data 1 97A Read RxDO pin ST Receive data 1 P sP ST Receive data2 P sP Shift mm m eisa LL TOOS T Om INTSRO INTSREO L Data reception lt 7 gt Data reception TSF01 RE Page 24 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Incorrect the timing chart of clock request signal internal signal and SDRO1 is revised Incorrect Figure 15 91 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status Normal operation
5. Real time clock RTC Operable 12 bit interval timer Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Wakeup operation is enabled switching to the SNOOZE mode Programmable gain amplifier Operable Comparator Operable Only for channels set to enable cancellation of STOP mode and when digital filter is not used Omitted R Page 32 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on High speed On chip Oscillator X1 Clock fx External Main System Clock Clock fiu fex Clock supply to the CPU is stopped System clock Main system clock Stopped Subsystem clock Status before STOP mode was set is retained fit Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Timer array unit Timer KBO to KB2 Timer KCO Real time clock RTC 12 bit interval timer Status before STOP mode was set is retained Operation disabled
6. Subsystem clock Operation continues cannot be stopped Cannot operate Cannot operate Operation continues cannot be stopped fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Code flash memory Data flash memory RAM Operation stopped Port latch Status before HALT mode was set is retained Timer array unit Timer KBO to KB2 Timer KCO Operable when the RTCLPC bit is 0 operation is disabled when the RTCLPC bit is not 0 Real time clock RTC 12 bit interval timer Operable Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Operation disabled Programmable gain amplifier Operable However this is not used since the operation has been disabled for the A D converter that is the destination for input of the PGA output signal Comparator Operable When in the low consumption RTC mode RTCLPC 1 in the OSMC register this can be used only when the STOP mode cancel is set CMPnSTEN 1 in the PESELO register by the comparator interrupt detection and the noise filter is not used n 2 0 2 Omitted zu Page 30 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A
7. Symbol PFSELO ES CMPOSTEN PNFEN ADTRG11 ADTRG10 TMRSTEN1 TMRSTENO CMP2STEN CMPOSTEN Comparator interrupt selection See CHAPTER 14 COMPARATOR PNFEN Use Do not use external interrupt INTP20 noise filter o Use noise filter Do not use noise filter ADTRG11 ADTRG10 Timer trigger selection for A D conversion foo o Timer KBO trigger source foo 1 Timer KB1 trigger source 1 Remark See Figure 14 1 Block Diagram of Comparator R Page 3 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Address FO5C6H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PFSELO CMP2STEN CMPOSTEN PNFEN ADTRG11 ADTRG10 TMRSTEN1 TMRSTENO CMP2STEN CMPOSTEN Comparator interrupt selection See CHAPTER 14 COMPARATOR PNFEN Use Do not use external interrupt INTP20 noise filter 0 Use noise filter Do not use noise filter o oo mexevmemme 700000000 5 o oresrmeresn s a meserewess TMRSTEN1 Switch of external interrupt INTP21 efe External interrupt function is selected stop mode release enabled timer restart disabled Timer restart function is selected stop mode release disabled timer restart enabled TMRSTENO Switch of external interrupt INTP20 Pete oo External interrupt function is selected stop mode release enabled timer restart disabled Timer restart function fo
8. an additional output delay time 10 to 40 ns is required until the level of the timer KB output changes Remark m 0 1 n 20 21 p 7 6 Table 14 5 Relationship of comparator 0 and 2 functions register settings and active signal width SURE register setting registers Timer restart External interrupt CMPnSTEN 1 Rising edge only To 150 ns N STOP release is Deine enabled External interrupt CMPnSTEN 0 CEGPn CEGNn To 150 ns STOP release is 2 to 3 clocks 45 disabled Forced ouputstop oMPnsten 1 Notes Torsone Todo Timer restart CMPnSTEN 0 CEGPn CEGNn To 150 ns te 3 To 150 ns 34 2 to 3 clocks 2 to 3 clocks Figure 14 19 Generation Timing of Forced Output Stop Request Signal by Comparator 0 and 2 CMPnSTEN 1 CMPNR pin Comparator respondence time to 150 ns Nete3 Forced output stop request signal Interrupt request signal Figure 14 20 Generation Timing of Timer Restart Request Signal by Comparator 0 and 2 CMPnSTEN 0 CMPnP pin Comparator respondence time y to 150 ns Note3 Comparator output signal Edge comfirming time EK 2 to 3 clocks Nee 4 5 Timer restart request signal i Interrupt request signal Notes 1 When noise filtering is set to 0 0 by using the CnDFS1 and CnDFSO bits in the comparator n control register CnCTL To change the level of the edge direction invert the comparator output signal by using the CnINV bit in the comparator n contr
9. in its inactive period TKBPAMD1p1 TKBPAMD1p0 Output status selection when executing forced output stop function Sei ieee eae ae oe a a Output fixed at low level Output fixed at low level Output fixed at high level Output fixed at high level Notes 1 When INTP20 is used as the forced output stop function 2 see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMP3 is used as the timer KB forced output stop function see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMPO or CMP2 is used as the timer KB forced output stop function set CMPnSTEN 1 For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function When timer KB is stopped TKBCEn 0 without waiting for the next counter period the forced output stop function is kept on until timer KB is restarted TKBCEn 1 Cautions 1 During timer operation setting the other bits of the TKBPACTL1p register is prohibited However the TKBPACTL1p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 12 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 4 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p Incorrect descriptions of forced output stop function control register 2p TKBPACTL2p are revised and Note is added Incorrect Figure 7 75 Format of Forced Output Stop
10. sroPmode sNoozEmode mode SNOOZE mode Normal operation 4 SS01 lt 3 gt lt 12 gt STo1 lt 1 gt st __ SWCO EOCO1 SSECO L Clock request signal internal signal Receive data 2 SDRO1 1 Receivedata X data 1 3 RxDO pin ST Receive data 1 X P sP ST Receive data 2 pP sP Shift mum register 01 X_Xshiftoperation XY XX Shift operation Y INTSRO Data reception lt 7 gt Data reception INTSREO TSF01 Correct Figure 15 91 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status Normal operation sroPmode sNoozEmode mode SNOOZE mode Normal operation 4 Clock request signal internal signal Receive data 2 SDRO1 1 Receivedaai Jk data 1 F94 Read e RxDO pin ST Receive data 1 Y P sp ST Receive data 2 P sP Shift register 01 X XswRopen X X XX Shite operation XX INTSRO Data reception lt 7 gt Data reception INTSREO TSF01 RE Page 25 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Incorrect the clock request signal internal signal timing chart is revised Incorrect Date Apr 9 2014 Figure 15 93 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode SS01 STO1 SE01 SWCO EOCO1 SSECO Clock request sig
11. timer KB forced output stop function see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMPO is used as the timer KB forced output stop function set CMPOSTEN 1 For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function When timer KB is stopped TKBCEn 0 without waiting for the next counter period the forced output stop function is kept on until timer KB is restarted TKBCEn 1 Cautions 1 During timer operation setting the other bits of the TKBPACTL2p register is prohibited However the TKBPACTL2p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 Re Page 16 of 37 s lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 5 Figure 14 Block Diagram of Comparator Incorrect names of the noise filter and the edge detection circuit in the block diagram are revised and Note is added Incorrect Peripheral function switch register 0 PFSELO IMR SIMA ogee ESL PNFEN stent STENO External interrupt INTP20 INTP21 control block Comparator rising edge enable register CMPEGPO Comparator falling edge enable register CMPEGN1 INTP20 P10 gt Noise Edge Timer restart request signal filter De 1 detector gt timers KBO to KB2 Timer output forced stop request signal timers KBO to KB2 CEGP7 CEGN7 CEGP6 CEGN6
12. 0 Remark n 0to2 p 0 1 R Page 8 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 3 Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p Incorrect descriptions of forced output stop function control register 1p TKBPACTL1p are revised and Note is added Incorrect Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 1 2 Address F0670H TD F0672H on 1 After reset 0000H R W Symbol TKBPACTL1p TKBPAFXS1p3 TKBPAFXS1p2 TKBPAFXS1p1 TKBPAFXS1p0 LT T TKBPAFCM1p pao TKBPAHZS1p1 TKBPAHZS1p0 JTKBPAHCM1p1 TKBPAHCM1p0 TKBPAMD1p1 TKBPAMD1p0 TKBPAFXS1p3 External interruption trigger selection for forced output stop function 2 oo INTP20 can not be used as a trigger 1 ivtpzocanbeusedasatigger TKBPAFXS1p2 Comparator trigger selection for forced output stop function 2 o Comparator 3 can not be used as a trigger Pt comparstorscanbeusedasatiges TKBPAFXS1p1 Comparator trigger selection for forced output stop function 2 E Comparator 2 can not be used as a trigger TKBPAFXS1p0 Comparator trigger selection for forced output stop function 2 oo Comparator 0 can not be used as a trigger 1 ComparatorOcanbeusedasatigge TKBPAFCM1p Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter peri
13. 2p 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT2p 1 is invalid Forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT2p 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTT2p 1 is written regardless of the trigger signal level Note 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT2p 1 is invalid Forced output stop function 1 is cleared at the next counter period after forced output stop function release CSP sity 1 is written when the trigger signal is in its inactive period TKBPAMD2p1 TKBPAMD2p0 Output status selection when executing forced output stop function ei quu eee as a ee a a Output fixed at low level Output fixed at low level Output fixed at high level Output fixed at high level Notes 1 When INTP20 is used as the forced output stop function 2 see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMP4 or CMP5 is used as the
14. Apr 9 2014 Correct B External maskable interrupt INTPn INTCMPm Internal bus External interrupt edge enable register ISP1 ISPO EGP EGN Nete INTPnNete Vector table INTCMPmNete address generator pin input Standby release signal Note According to setting for using of the timer KB simultaneous function the timer KB forced output stop function and timer restart function the interrupt signal pass and the interrupt generation timing and the edge enable register for INTP20 and INTP21 and INTCMPm vary For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function Interrupt request flag Interrupt enable flag In service priority flag 0 In service priority flag 1 Interrupt mask flag Priority specification flag O Priority specification flag 1 20 pin n 0 20 21 22 m 0to3 30 pin n 0 4 11 20 to 23 m O0to5 38 pin n 0 3 4 9 to 11 20 to 23 m 0to5 R Page 29 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 11 Table 21 1 Operating Statuses in HALT Mode 2 2 Incorrect description about the comparator operation in HALT mode is revised Incorrect HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock System clock When CPU Is Operating on XT1 Clock fxr When CPU Is Operating on External Subsystem Clock fexs Clock supply to the CPU is stopped Main system clock Operation disabled
15. BPACTL2p 2 2 TKBPAHZS2p2 Comparator trigger selection for forced output stop function 1 Comparator 5 can not be used as a trigger Comparator 5 can be used as a trigger TKBPAHZS2p1 Comparator trigger selection for forced output stop function 1 Comparator 4 can not be used as a trigger TKBPAHZS2p0 Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger TKBPAHCM2p1 TKBPAHCM2pO Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT2 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTT2 1 is invalid Forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT2 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT2 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger IKBPAHTT2 1 is invalid Forced output stop fu
16. BPAHZSOp1 Comparator trigger selection for forced output stop function 1 oo Comparator 1 can not be used as a trigger Comparator 1 can be used as a trigger Notes TKBPAHZSOpO Comparator trigger selection for forced output stop function 1 oo Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Nora R Page 7 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Figure 7 73 Format of Forced Output Stop Function Control Register 0p TKBPACTLOp 2 2 TKBPAHCMOp1 TKBPAHCMOpO Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTTOp 7 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTTOp 1 is invalid Forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTTOp 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTTOp 1 is written regardless of the trigger signal level Note 1 1 Forced output
17. CTLOp 1 2 Address F0630H TKBPACTLOO F0632H TKBPACTLO1 After reset 0000H R W Symbol 15 14 13 1 11 10 9 8 2 1 TKBPACTLOp TKBPAFXSOp3 TKBPAFXSOp2 TKBPAFXS0p1 TKBPAFXSOpO 0 o o TKBPAFCMOp 7 2 6 5 4 3 0 0 rePAHzsopa TKBPAHZSOp1 TKBPAHZSOpO TKBPAHCMOp1 TKBPAHCMOpO TKBPAMD0p1 TKBPAMDOpO TKBPAFXSOp3 External interruption trigger selection for forced output stop function 2 fo INTP20 can not be used as a trigger INTP20 can be used as a trigger Note o Sememerzcennetewedseamppe Comparator 2 can be used as a trigger Nowe Comparator trigger selection for forced output stop function 2 o conpartortcannatteuedas aves C O omnea o CS TKEPAFXSO0 TKBPAFXSOpO Comparator trigger selection for forced output stop function 2 1 o Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger noes 1 TKBPAFCMOp Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is A Note 4 cleared at the next counter period ae Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger Note 4 TKBPAHZSOp2 Comparator trigger selection for forced output stop function 1 oo Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger Nota TK
18. Date Apr 9 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Category Document MPU MCU No 1 00 TN RL A024A E Rev Correction for Incorrect Description Notice RL78 11A Descriptions in the Hardware User s Manual Rev 2 10 Changed Information THE Category Technical Notification Lot No RL78 I1A User s Manual Hardware Rev 2 10 RO1UHO0169EJ0210 Jul 2013 Reference Document Applicable Product RL78 11A Group R5F107xxx All lot This document describes misstatements found in the RL78 I1A hardware user s manual Rev 2 10 RO1UH0169EJ0210 Corrections Figure 7 19 Format of Peripheral Function Switch Register 0 P 303 Incorrect descriptions PFSELO revised Figure 7 73 Format of Forced Output Stop Function Control Incorrect descriptions Register Op TKBPACTLOp revised Figure 7 74 Format of Forced Output Stop Function Control Incorrect descriptions Register 1p TKBPACTL1p revised Figure 7 75 Format of Forced Output Stop Function Control Incorrect descriptions Register 2p TKBPACTL2p revised Figure 14 1 Block Diagram of Comparator Incorrect descriptions revised P 380 381 P 382 383 P 384 385 P 527 P 538 Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Incorrect descriptions revised 14 5 Caution for Using Timer
19. E Date Apr 9 2014 Correct HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock System clock When CPU Is Operating on XT1 Clock fxr When CPU Is Operating on External Subsystem Clock fexs Clock supply to the CPU is stopped Main system clock Operation disabled Subsystem clock Operation continues cannot be stopped Cannot operate Cannot operate Operation continues cannot be stopped fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Code flash memory Data flash memory RAM Operation stopped Port latch Status before HALT mode was set is retained Timer array unit Timer KBO to KB2 Timer KCO Operable when the RTCLPC bit is 0 operation is disabled when the RTCLPC bit is not 0 Real time clock RTC 12 bit interval timer Operable Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Operation disabled Programmable gain amplifier Operable However this is not used since the operation has been disabled for the A D converter that is the destination for input of the PGA output signal Comparator O
20. KB Simultaneous Operation Function Caution added Timing Chart of SNOOZE Mode Operation P 666 667 669 Incorrect descriptions revised Table 20 1 Interrupt Source List 2 3 P 898 Caution added Figure 20 1 Basic Configuration of Interrupt Function P 900 Incorrect descriptions revised Table 21 1 Operating Statuses in HALT Mode 2 2 P 931 Incorrect descriptions revised Table 21 2 Operating Statuses in STOP Mode P 936 Incorrect descriptions revised Table 21 3 Operating Statuses in SNOOZE Mode P 942 Incorrect descriptions revised 32 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics P 1100 Explanations added 33 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics c 2014 Renesas Electronics Corporation All rights reserved P 1142 RENESAS Explanations added Page 1 of 37 RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Document Improvement The above corrections will be made for the next revision of the hardware user s manual Corrections in the hardware user s manual Applicable Item Applicable Ne English RO1UH0169EJ0210 ee 4 Figure 7 19 Format of Peripheral Function Switch Register O p 303 3 PFSELO P 2 Figure 7 73 Format of Forced Output Stop Function Control p 380 381 5 Register Op TKBPACTLOp P 3 9 Figure 7 74 Format of Forced Output Stop Function Control Re
21. PMONO Comparator 0 control register COCTL Comparator output Ne monitor register CMPMON _ Digital Edge INTCMP1 detector Timer restart request signal timer KBO Timer output forced stop request signal timer KBO Comparator 1 CMP1P ANI4 P24 5 3 3 E WCSELO bit CMP2STEN INTCMP2 o parator 2 CMP2P ANIS P25 Digital Edge Timer restart request signal detector timer KB1 Selector WCSEL1 bit Timer output forced stop request signal timers KBO KB1 gt P gt parator 3 EE N man k detector Timer restart request signal LLIL timer KB2 Timer output forced stop request signal timer KB1 P gt gt Q z CMP3P ANIG P26 Selector __ Select Selector m 8 3 Digital Edge parator 4 detector INTCMP4 CMP4P ANI7 P27 I Timer output forced stop request signal timer KB2 Selector parator 5 Digital Edge detector INTCMP5 CMPS5P ANI16 RxD1 P03 Timer output forced stop request signal timer KB2 Selector CMPCOM CMP3P ete ANI18 P147 9 Vo AVnere ANIO P20 Note ICMPSELO Selector Comparator input switch CVREm bit c
22. Page 11 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 2 2 TKBPAHCM1p1 TKBPAHCM1p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT 1p 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT1p 1 is invalid Forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT1p 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTT 1p 1 is written regardless of the trigger signal level Note 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT1p 1 is invalid Forced output stop function 1 is cleared at the next counter period after forced output stop function release ALES T p 1 is written when the trigger signal is
23. al via digital edge detect circuit is selected STOP mode release is disabled Forced output stop request signal is selected STOP mode release is enabled but only when not using noise filter Can be set when operating in low power RTC mode RTCLPC 1 in the OSMC register PNFEN Use Do not use external interrupt INTP20 noise filter o Use noise filter Do not use noise filter TMRSTEN1 External interrupt INTP21 function switching External interrupt function is selected STOP mode release is enabled but cannot be used for timer restart function Timer restart function is selected STOP mode release is disabled but can be used for timer restart function TMRSTENO External interrupt INTP20 function switching External interrupt function is selected STOP mode release is enabled but cannot be used for timer restart function Timer restart function forced output stop function 2 is selected STOP mode release is disabled but can be used for timer restart function When the interrupt for CMPO and CMP2 is used adopt a function used with the interrupt input signal When the CMPO and CMP2 are used as a trigger of the timer KB forced output stop function set CMPnSTEN 1 When the CMP2 is used as a trigger of the timer restart function for timer KB set CMP2STEN 0 For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function When INTP20 and INTP21 are used as a trigger of the timer KB forced out
24. and forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT1 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTTI 1 is invalid Forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT1 1 is written when the trigger signal is in its inactive period TKBPAMD1p1 TKBPAMD1p0 Output status selection when executing forced output stop function EERE E O Pe teow a NN E e a a a 7 Cautions 1 During timer operation setting the other bits of the TKBPACTL1p register is prohibited However the TKBPACTL1p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 10 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 1 2 Address F0670H TKBPACTL10 F0672H TKBPACTL11 After reset 0000H R W Symbol 15 14 13 1 11 10 9 8 2 1 TKBPACTL1p TKBPAFXS1p3 TKBPAFXS1p2 TKBPAFXS1p1 TKBPAFXS1p0 foo o o TKBPAFCM1p 7 2 6 5 4 3 0 0 ePAHzstp2 TKBPAHZS1p1 TKBPAHZS1p0 JTKBPAHCM1p1 TKBPAHCM1p0 TKBPAMD1p1 TKBPAMD1p0 TKBPAFXS1p3 External interruption trigger selection for forced out
25. ate Apr 9 2014 Correct Peripheral function switch register 0 PFSELO mm mM AED UN PNFEN STEN1 STENO External interrupt INTP20 INTP21 control block Comparator rising edge enable register CMPEGPO Comparator falling edge enable register CMPEGN1 CEGP7 CEGN7 CEGP6 ceans INTP20 P10 I i Noise DigialEdge filter 1 detector Timer restart request signal timers KBO to KB2 i timers KBO to KB2 A T Timer output forced stop request signal D Noise INTP2UP11 filter Digital Edge Timer restart request signal e 1 detector timers KBO to KB2 Timer output forced stop request signal timers KBO to KB2 External interrupt control register INTPCTL al 1 INTP20 Edge detector enable register EGP2 EGN2 INTP21 0 L External interrupt edge XN 0 La f cosiparaior 0 Comparator rising edge enable register CMPEGPO N Comparator falling edge enable register CMPEGNO CEGPO CEGNO 0 Digital Noise CMPO output pigital Edge INTCMPO 1 detector E us Timer output forced stop request signal timers KBO to KB2 CMPOSTEN CMPOP ANI2 P22 CODFS1 CM
26. ator respondence time to 150 ns Note 1 Forced output stop request signal Edge comfirming time i 2 to 3 clocks 2 3 H n Timer restart request signal Note 5 i Interrupt request signal When noise filtering is set to 0 0 by using the CnDFS1 and CnDFSO bits in the comparator n control register CnCTL Ifa setting other than 0 0 is specified the specified noise elimination width is added For fck or fe when PLLON 1 Until the timer restart function starts operating an additional clock cycle is required after the timer restart request signal is received and an additional output delay time 10 to 40 ns is required until the level of the timer KB output changes The active level of INTP20 used for forced output stop function 2 is high An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes The timer restart function can be used for comparator 1 and 3 only An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes n 1 3to5 zu Page 23 of 37 aQENECSAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 8 Timing Chart of SNOOZE Mode Operation p 666 667 669 Incorrect the clock request signal internal signal timing is revised Incorrect Figure 15 90 Timing Chart of SNOOZE
27. e each function Function register setting registers Interrupt Forced output stop Timer restart External interrupt TMRSTENm 0 EGPn EGNn To 1 4s STOP release is enabled Forced output stop 55 to 215 ns e 55 to 215 ns Note 1 Note 2 2 to 3 clocks Note 4 Note 3 5 Timer restart TMRSTENm 1 CEGPp CEGNp 55 to 215 ns N34 55 to 215 ns N34 2 to 3 clocks 2 to 3 clocks 6 Figure 14 18 Generation Timing of Forced Output Stop Signal and Timer Restart Request Signal by INTP2m INTP2m pin I y Internal wait time 55 to 215 ns Nee 5 I Forced output stop request signal Net we Edge comfirming time 2 to 3 clocks Nete 4 6 1 r 1 Timer restart i request signal i Interrupt request signal Only INTP20 can be used as a trigger for forced output stop function 2 The active level of INTP20 used for forced output stop function 2 is high Edge selection is only applied to detection of an interrupt signal 5 to 15 ns when noise filtering on INTP20 is disabled PNFEN 1 For ferk or fet when PLLON 1 An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes R Page 21 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Notes 6 Until the timer restart function starts operating an additional clock cycle is required after the timer restart request signal is received and
28. ed but only when not using noise filter Can be set when operating in low power RTC mode RTCLPC 1 in the OSMC register CMPOSTEN Comparator 0 detection interrupt INTCMPO switching fo STOP mode clear disabled STOP mode clear enabled but only when not using noise filter Can be set when operating in low power RTC mode RTCLPC 1 in the OSMC register PNFEN Use Do not use external interrupt INTP20 noise filter Use noise filter Do not use noise filter TMRSTEN1 External interrupt INTP21 function select External interrupt function can be generated external interrupt but cannot be used for timer restart function Caution Comparator detection interrupt other than CMPO and CMP2 cannot be used to clear the STOP mode R Page 19 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Address FO5C6H After reset 00H Symbol PFSELO PERS CMPOSTEN PNFEN ADTRG11 ADTRG10 TMRSTEN1 TMRSTENO CMP2STEN Comparator 2 detection interrupt INTCMP2 switching N 1 EUM Signal via digital edge detect circuit is selected STOP mode release is disabled Forced output stop request signal is selected STOP mode release is enabled but only when not using noise filter Can be set when operating in low power RTC mode RTCLPC 1 in the OSMC register CMPOSTEN Comparator 0 detection interrupt INTCMPO switching 9 1 Sign
29. en the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTTO 1 is invalid Forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTTO 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger IKBPAHTTO 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTTO 1 is invalid Forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTTO 1 is written when the trigger signal is in its inactive period TKBPAMDOp1 TKBPAMDOpO Output status selection when executing forced output stop function Mis s s zem owed e ft riz out outputinedatigh ove v 5 owwtesaews ouput ned atiowievel Cautions 1 During timer operation setting the other bits of the TKBPACTLOp register is prohibited However the TKBPACTLOp register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 RE Page 6 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct Figure 7 73 Format of Forced Output Stop Function Control Register 0p TKBPA
30. forced output stop function 2 o Comparator 0 can not be used as a trigger 1 Comparatorocanbeusedasatigge TKBPAFCMOp Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger R Page 5 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Figure 7 73 Format of Forced Output Stop Function Control Register 0p TKBPACTLOp 2 2 TKBPAHZSOp2 Comparator trigger selection for forced output stop function 1 Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger TKBPAHZSOp1 Comparator trigger selection for forced output stop function 1 Comparator 1 can not be used as a trigger TKBPAHZSOpO Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger TKBPAHCMOp1 TKBPAHCMOpO Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTTO 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and wh
31. function 2 1 o Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger nowa 1 TKBPAFCM2p Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is Note 4 cleared at the next counter period oa Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger Mole 4 TKBPAHZS2p2 Comparator trigger selection for forced output stop function 1 oo Comparator 5 can not be used as a trigger Comparator 5 can be used as a trigger Nota TKBPAHZS2p1 Comparator trigger selection for forced output stop function 1 0 Comparator 4 can not be used as a trigger Comparator 4 can be used as a trigger How TKBPAHZS2p0 Comparator trigger selection for forced output stop function 1 oo Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Norea R Page 15 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p 2 2 TKBPAHCM2p1 TKBPAHCM2p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT
32. gister 1p TKBPACTL1p 4 Figure 7 75 Format of Forced Output Stop Function Control p 384 385 13 Register 2p TKBPACTL2p P Figure 14 1 Block Diagram of Comparator p 527 ER a nl E 0 PFSELO p EN I es Pe ee Function 8 Timing Chart of SNOOZE Mode Operation p 666 667 669 Table 20 1 Interrupt Source List 2 3 p 898 aa ist 2 3 Figure 20 1 Basic Configuration of Interrupt Function p 900 Table 21 1 Operating Statuses in HALT Mode 2 2 p 931 Table 21 2 Operating Statuses in STOP Mode p 936 Table 21 3 Operating Statuses in SNOOZE Mode p 942 44 32 7 Data Memory STOP Mode Low Supply Voltage Data p 1100 p 35 Retention Characteristics 45 33 7 Data Memory STOP Mode Low Supply Voltage Data p 1142 p 36 Retention Characteristics Incorrect Bold with underline Correct Gray hatched Issued Document History RL78 I1A Incorrect description notice issued document history Document Number TN RL A024A E Apr 9 2014 First edition issued Incorrect descriptions of No 1 to No 15 revised This notice R Page 2 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 1 Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Incorrect descriptions of the TMRSTEN1 and TMRSTENO bits of Peripheral Function Switch Register 0 PFSELO are revised and Note is added Incorrect Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Address F05C6H After reset 00H
33. mode continues Timer array unit Operation disabled Timer KBO to KB2 Timer KCO Real time clock RTC Operable 12 bit interval timer Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Operable Programmable gain amplifier Operable Comparator Operable Only for channels set to enable cancellation of STOP mode and when digital filter is not used Omitted R Page 34 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct STOP Mode Setting When Inputting CSIOO UARTO Data Reception Signal or A D Converter Timer Trigger Signal While in STOP Mode When CPU Is Operating on High speed On chip Oscillator Clock fiu System clock Clock supply to the CPU is stopped Main system clock Operation started Stopped Subsystem clock Use of the status while in the STOP mode continues fit Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Use of the status while in the STOP mode continues Timer array unit Operation disabled Timer KBO to KB2 Timer KCO Real time clock RTC Operable 12 bit in
34. nal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO TSF01 Correct CPU operation status SS01 STO1 SE01 SWCO EOCO1 SSECO Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO TSF01 lt 4 gt lt 3 gt lt 1 gt mile DIE Receive data 2 KX Reeivdaai XK data 1 Read N 4 9 ST Receive data 1 X P sP he A pem mmm ie n d LM Data reception T ST Receive data 2 P SP Data reception lt 7 gt lt 11 gt lt 8 gt Figure 15 93 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode lt 4 gt lt 3 gt L 2 ST Receive data 1 X P sP ren ANUS pem emm aen 5 6 Data reception T RENESAS Receive data 1 ST Receive data 2 P SP Receive data Read N la 9 lt 5 gt lt 6 gt Data reception lt 7 gt lt 11 gt lt 8 gt Page 26 of 37 RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 9 Table 20 1 Interrupt Source List 2 3 Note for the interrupt source list is added Incorrect Notes 1 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously Zero indicates the highest priority and 40 indicates the lowest pri
35. nction 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT2 1 is written when the trigger signal is in its inactive period TKBPAMD2p1 TKBPAMD2p0 Output status selection when executing forced output stop function I 9 5 weadd a BOMINUM T a NN E e a a a 7 Cautions 1 During timer operation setting the other bits of the TKBPACTL2p register is prohibited However the TKBPACTL2p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 14 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Correct Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p 1 2 Address FO6BOH TKBPACTL20 F06B2H TKBPACTL21 After reset 0000H R W gSymbol 15 14 13 1 11 10 9 8 2 1 TKBPACTL2p TKBPAFXS2p3 TKBPAFXS2p2 TKBPAFXS2p1 TKBPAFXS2p0 o o o TKBPAFCM2p 7 2 6 5 4 3 0 0 eeAHzsopa TKBPAHZS2p1 TKBPAHZS2p0 TKBPAHCM2p1 TKBPAHCM2p0 TKBPAMD2p1 TKBPAMD2p0 TKBPAFXS2p3 External interruption trigger selection for forced output stop function 2 oo INTP20 can not be used as a trigger INTP20 can be used as a trigger Note o Sewwmerssennetteweedseamppe Comparator trigger selection for forced output stop function 2 o conpartorcannatteuedasavage 1 omoran E OOOO enne TKBPAFXS2p0 Comparator trigger selection for forced output stop
36. nly CMPO and CMP2 are operable When in the low consumption RTC mode RTCLPC 1 in the OSMC register CMPn can be used only when the STOP mode cancel is set CMPnSTEN 1 in the PFSELO register by the comparator interrupt detection and the noise filter is not used n 0 2 Omitted zu Page 31 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 12 Table 21 2 Operating Statuses in STOP Mode Incorrect description about the comparator operation in STOP mode is revised Incorrect STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on High speed On chip Oscillator X1 Clock fx External Main System Clock Clock fiu fex System clock Clock supply to the CPU is stopped Main system clock Stopped Subsystem clock Status before STOP mode was set is retained fit Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Status before STOP mode was set is retained Timer array unit Operation disabled Timer KBO to KB2 Timer KCO
37. not retained Therefore set STOP mode before the supplied voltage is below the operation voltage range STOP mode Operation mode RAM Data retention STOP instruction execution Standby release signal interrupt request zu Page 36 of 37 aQENECSAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 15 33 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Descriptions of the data memory STOP mode low supply voltage data retention characteristics are added Incorrect D Memory STOP M Low Ta 40 to 125 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected STOP mode Operation mode Data retention mode STOP instruction execution Standby release signal interrupt request Correct 33 7 RAM Data Retention Characteristics Ta 40 to 125 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the RAM data is retained before a POR reset is effected but RAM data is not retained when a POR reset is effected Caution When CPU is operated at the voltage of out of the operation voltage range RAM data is not retained Therefore set STOP mode before the supplied voltage is below the operation vol
38. od Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger R Page 9 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 2 2 TKBPAHZS1p2 Comparator trigger selection for forced output stop function 1 Comparator 3 can not be used as a trigger Comparator 3 can be used as a trigger TKBPAHZS1p1 Comparator trigger selection for forced output stop function 1 Comparator 2 can not be used as a trigger TKBPAHZS1p0 Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger TKBPAHCM1p1 TKBPAHCM1p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT1 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTTI1 1 is invalid Forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT1 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input
39. ol register CnCTL This is the time required when noise filtering is set to 0 0 by using the CnDFS1 and CnDFSO bits in the comparator n control register CnCTL If a setting other than 0 0 is specified the specified noise elimination width is added For fci or fe when PLLON 1 RE Page 22 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 Until the timer restart function starts operating an additional clock cycle is required after the timer restart request signal is received and an additional output delay time 10 to 40 ns is required until the level of the timer KB output changes The active level of INTP20 used for forced output stop function 2 is high An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes Remark n 0 2 Table 14 6 Relationship of comparator 1 3 4 and 5 functions register settings and active signal width CEGPn CEGNn To 150 ns Net 2 to 3 clocks e 2 3 To 150 ns Note To 150 ns 25 2 to 3 clocks 3 4 CEGPn CEGNn To 150 ns Note To 150 ns Nt 2 to 3 clocks efe 3 4 2 to 3 clocks e 3 4 Figure 14 21 Generation Timing of Forced Output Stop Request Signal and Timer Restart Request Signal by External interrupt STOP release is disabled Forced output stop i Timer restart Comparator 1 3 4 and 5 CMPnP pin P ai Compar
40. ontrol register CMPSEL t t ii osez WCSEL1 woseo Window comparator function setting register CMPWDC Vss AVrerwANI1 P21 Selector il l t CMP2 CMPO CmVRS6 CmVRSS5 CmVRS4 CmVRS3 CmVRS2 CmVRS1 CVRVS1 CVRVSO CVRE2 CVRE1 CVREO STEN STEN Comparator internal reference Comparator internal reference Peripheral function voltage select register m CmRVM voltage control register CVRCTL switch register 0 PFSELO Note 20 pin products only ANI16 CMP3P P26 is selected by default for 30 and 38 pin products Caution When INTP20 INTP21 and comparator are used as the timer KB forced output stop function 2 or timer KB restart function see 14 5 Caution for Using Timer KB Simultaneous Operation Function Remark m 0to2 Re Page 18 of 37 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 6 Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Incorrect descriptions of the comparator and external interrupts are revised and Notes are added Incorrect Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Address FO5C6H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PFSELO CMP2STEN CMPOSTEN PNFEN ADTRG11 ADTRG10 TMRSTEN1 TMRSTENO CMP2STEN Comparator 2 detection interrupt INTCMP2 switching 0 STOP mode clear disabled STOP mode clear enabl
41. ority 2 Basic configuration types A to D correspond to A to D in Figure 20 1 3 INTCMP1 INTCMP3 INTCMPA and INTCMPS cannot be used to clear the STOP mode Correct Notes 1 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously Zero indicates the highest priority and 40 indicates the lowest priority 2 Basic configuration types A to D correspond to A to D in Figure 20 1 3 INTCMP1 INTCMP3 INTCMP4 and INTCMP5 cannot be used to clear the STOP mode About interrupt generation timing see 14 5 Caution for Using Timer KB Simultaneous Operation Function RE Page 27 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 10 Figure 20 1 Basic Configuration of Interrupt Function Incorrect the basic configuration of interrupt function is revised Incorrect B External maskable interrupt INTPn INTCMPm Internal bus External interrupt edge enable register EGP EGN INTPn INTCMPm pin input Standby release signal Interrupt request flag Interrupt enable flag In service priority flag 0 In service priority flag 1 Interrupt mask flag Priority specification flag 0 Priority specification flag 1 20 pin n 0 20 21 22 m 0to3 30 pin n 0 4 11 20 to 23 m O0to5 38 pin n 0 3 4 9 to 11 20 to 23 m 0 to 5 R Page 28 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date
42. put stop function 2 oo INTP20 can not be used as a trigger INTP20 can be used as a trigger Note 0 Conparstracannetteusdasangen Comparator 3 can be used as a trigger Nowe Comparator trigger selection for forced output stop function 2 0 conpartor2cannatteuedasavage 1 omanesa o TKEPAFXS 0 TKBPAFXS1p0 Comparator trigger selection for forced output stop function 2 1 o Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger nowa 1 TKBPAFCM1p Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is A Note 4 cleared at the next counter period A Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger NE 4 TKBPAHZS1p2 Comparator trigger selection for forced output stop function 1 oo Comparator 3 can not be used as a trigger Comparator 3 can be used as a trigger Nota TKBPAHZS1p1 Comparator trigger selection for forced output stop function 1 oo Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger Notes TKBPAHZS1p0 Comparator trigger selection for forced output stop function 1 a Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Norea R
43. put stop function 2 or timer restart function see 14 5 Caution for Using Timer KB Simultaneous Operation Function Caution Comparator detection interrupt other than CMPO and CMP2 cannot be used to clear the STOP mode Remark n 0 2 R Page 20 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 7 14 5 Caution for Using Timer KB Simultaneous Operation Function As respects of INTP2m and comparator Caution for Using Timer KB Simultaneous Operation Function is added Incorrect No applicable item Correct 14 5 Caution for Using Timer KB Simultaneous Operation Function In addition to their use as an external interrupt input the INTP2m pin output and the comparator output signal can be used as a trigger for functions that operate simultaneously with timer KB such as the forced output stop function and timer restart function The settings in peripheral function switch register 0 PFSELO and the edge selection registers must be specified according to the function used The width of the active signal required until each function starts operating differs When using INTP2m or the comparator output signal refer to Tables 14 4 to 14 6 to specify the necessary register settings and configure external circuits so that the required active signal width is assured Table 14 4 Relationship of INTP2m function register settings and active signal width Peripheral enable Edge setting Necessary active signal width to operat
44. rced output stop function 2 is selected stop mode release disabled timer restart enabled Note When INTP20 or INTP21 is used as a trigger of the timer KB forced output stop function 2 or timer restart function see 14 5 Caution for Using Timer KB Simultaneous Operation Function Remark See Figure 14 1 Block Diagram of Comparator R Page 4 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 2 Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp Incorrect descriptions of forced output stop function control register Op TKBPACTLOp are revised and Note is added Incorrect Figure 7 73 Format of Forced Output Stop Function Control Register 0p TKBPACTLOp 1 2 Address F0630H de UA F0632H ra After reset 0000H R W Symbol TKBPACTLOp TKBPAFXSOp3 TKBPAFXSOp2 TKBPAFXS0p1 TKBPAFXS0p0 LT T TKBPAFCMOp ES TKBPAHZSOp1 TKBPAHZSOpO TKBPAHCMOp1 TKBPAHCMOpO TKBPAMDOp1 TKBPAMDOpO TKBPAFXSOp3 External interruption trigger selection for forced output stop function 2 oo INTP20 can not be used as a trigger 1 ivtpzocanbeusedasatigger TKBPAFXS0p2 Comparator trigger selection for forced output stop function 2 o Comparator 2 can not be used as a trigger P comparstor2canbeusedasatigen TKBPAFXS0p1 Comparator trigger selection for forced output stop function 2 MX Comparator 1 can not be used as a trigger TKBPAFXSOpO Comparator trigger selection for
45. stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTTOp 1 is invalid Forced output stop function 1 is cleared at the next counter period after forced output stop function release CES RAHIMOR 1 is written when the trigger signal is in its inactive period TKBPAMDOp1 TKBPAMDOpO Output status selection when executing forced output stop function mE s ioa o owaheisbewm s ft riz out outputfinedatighiover a ee a Output fixed at low level Output fixed at low level Output fixed at high level Output fixed at high level When INTP20 is used as the forced output stop function 2 see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMPO or CMP2 is used as the timer KB forced output stop function set CMPnSTEN 1 See 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMP1 is used as the timer KB forced output stop function see 14 5 Caution for Using Timer KB Simultaneous Operation Function When timer KB is stopped TKBCEn 0 without waiting for the next counter period the forced output stop function is kept on until timer KB is restarted TKBCEn 1 Cautions 1 During timer operation setting the other bits of the TKBPACTLOp register is prohibited However the TKBPACTLOp register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to
46. tage range STOP mode Operation mode RAM Data retention STOP instruction execution Standby release signal interrupt request zu Page 37 of 37 aQENECSAS
47. terval timer Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Operable Programmable gain amplifier Operable Comparator Only CMPO and CMP2 are operable when the STOP mode cancel is set CMPnSTEN 1 in the PFSELO register by the comparator interrupt detection and the noise filter is not used n 0 2 Omitted RE Page 35 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E Date Apr 9 2014 14 32 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Descriptions of the data memory STOP mode low supply voltage data retention characteristics are added Incorrect 27 D Memory STOP M Low Ta 40 to 105 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected STOP mode Operation mode Data retention mode STOP instruction execution Standby release signal interrupt request Correct 32 7 RAM Data Retention Characteristics Ta 40 to 105 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the RAM data is retained before a POR reset is effected but RAM data is not retained when a POR reset is effected Caution When CPU is operated at the voltage of out of the operation voltage range RAM data is
48. utput forced stop request signal timers KBO KB1 Selector INTCMP3 Timer restart request signal timer KB2 Timer output forced stop request signal timer KB1 parator 3 CMP3P ANIG P26 parator 4 INTCMP4 CMP4P ANI7 P27 I Timer output forced stop request signal timer KB2 parator 5 INTCMP5 CMP5P ANH6 RxD1 P03 Timer output forced stop request signal timer KB2 CMPCOM CMP3P ets ANI18 P147 9 Vo AVrerr ANIO P20 Note ICMPSELO Comparator input switch control register CMPSEL Selector CVREm bit mas ii t ii wose WCSEL1 woseo Window comparator function setting register CMPWDC Vss AVrerwANI1 P21 Selector t l t CMP2 OMPO CmVRS6 CmVRS5 CmVRS4 CmVRS3 CmVRS2 CmVRS1 CVRVS1 CVRVSO CVRE2 CVRE1 CVREO STEN STEN Comparator internal reference Comparator internal reference Peripheral function voltage select register m CmRVM voltage control register CVRCTL switch register 0 PFSELO Note 20 pin products only ANI16 CMP3P P26 is selected by default for 30 and 38 pin products Remark m 0to2 RE Page 17 of 37 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024A E D

Correction for Incorrect Description Notice RL78/I1A Descriptions in

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