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Evaluation Module User Manual

1. P1 Pin Signal Pin Signal 1 NC 14 NC 2 PORT RESET 15 PORT IDENT 3 PORT TMS 16 NC 4 PORT TCK 17 NC 5 PORT TDI 18 GND 6 PORT TRST 19 GND 7 PORT DE 20 GND 8 PORT IDENT 21 GND 9 PORT VCC 22 GND 10 NC 23 GND 11 PORT TDO 24 GND 12 NC 25 GND 13 PORT CONNECT DSP56858EVM User Manual Rev 3 Freescale Semiconductor External Interrupts 2 9 External Interrupts Two on board push button switches are provided for external interrupt generation as shown in Figure 2 8 S1 allows the user to generate a hardware interrupt for signal line IRQA S2 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs Figure 2 8 Schematic Diagram of the User Interrupt Interface Technical Summary Rev 3 Freescale Semiconductor 2 13 2 10 Reset Logic is provided on the 56858 to generate an internal Power On RESET The 56858EVM provides reset logic to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button refer to Figure 2 9 JTAG RESET RESET MANUAL RESET TRST JTAG TAP RESET Figure 2 9 Schematic Diagram of the RESET Interface RESET PUSHBUTTON O DSP56858EVM User Manual Rev 3 2 14 Freescale Semiconductor Power Supply 2 11 Power Supply Th
2. O A0 S 24 56858EVM Schematics Rev 3 Appendix A 11 Freescale Semiconductor a a3 seiddng LL V 941614 08450 ueuBiseg 19945 LL 40 2002 OL Aepsinyl ejeg 0188 619 08 4 0609 1 087 8268 euozuy 10113 1523 0012 UOISIAIG 3 psepuels 450 jueunooq SdVO SSVdAd zis NSQ INA38S89SdSG eni DSP56858EVM User Manual Rev 3 i LNIOd 1541 INTOd LSHL INTOd LSAL 441 VAO S UN 1 1 P 841 tdl t eal 241 401070 47170 471070 259 180 089 675 EdL bd EC INIOd 1591 VAO G Ag e AS L NE E OSO IVNV VAO 8 088vVWI 02002 DSO STCvSO 02 rM J T m ane ms J m m T 879 170 979 Svo 0 272 175 075 680 859 Ag e Ag et Ag e Ag et Ag e Ag e Ag e Ag et Ag et ASCH YTYVCXO VL SVCtXVW S8T8TSA O00DVvL _ TTOHGSYIV 9IICLSD 1 9ITELS TN mo mos TM PN mu PM mu RS WB 280 9 0 geo veo 659 260 159 059 620 820 120 920
3. 97 NSQ INA38S89SdSQ 15 AYOWAW IWOHd33 WI 181295 45 pue ISOH 0152 61 089 XvJ 0605 61 087 78268 euozuy 101113 1523 0012 UOISIAIG 8 pJepuels 450 lt SOH Su IM STH 95H 994 SON 1587 MER Mol pou ES Ae e Ae e 56858EVM Schematics Rev 3 MOVH 39 ss L KK 198 9 8 lt lt ISON LVH T IS 33 OSIN 8 os 33 eau T 5 33i 2 lt lt 55 orar a a 9 v Freescale Semiconductor 40 99UU0D pue Z Z SM 1404 IOS s V eJnBi4 3 5 v LL JO 4 19945 0484 ueuDiseq 2002 01 Aepsuny ojeg y NSQ WA3 S89SdSG Jequnw 9215 jueuinooq HOLO3NNOO 222 58 1HOd IOS ll 0152 61 089 4 0609 17 087 98268 euozuy 1013 1523 0012 UOISIAIG 8 pJepuels 450 H IavSIQ cec sa AL 6vu NIGH WISgVNH CEC SH 318VN3 22 59 IV33SezEXVIN Y NIEI 44030H04 aAOLOANNOO 11030804 NIZI cec sa NISH 10088
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5. AS AS AS L AS Ag Ag e Ag e Ag e Ag e Ag e Ag e ecw Seba ana n es SSUSSdB cr sed xcu eo purus ee dub ee Aad I 8 Freescale Semiconductor Appendix A 12 Appendix B 56858EVM Bill of Material Qty Description Ref Designators Vendor Part s Integrated Circuits 1 56858 U1 Freescale DSP56858FV120 2 GS72116 U2 U3 GSI GS72116ATP 7 1 AT45DB011 U4 Atmel AT45DB011B SC 1 MAX3245 U5 Maxim MAX3245EEAI 1 CS4218 U6 Crystal Semiconductor CS4218 KQ 1 12 288MHz OSC U7 Epson SG 531P 12 288MC 1 LM4880 U8 National Semiconductor LM4880M 1 TALCX244 U9 ON Semiconductor MC74LCX244ADW 1 74AC00 U10 Fairchild 74 5 1 74AC04 U11 ON Semiconductor 74 4 1 5 0V Voltage Regulator U12 ON Semiconductor MC33269DT 5 1 3 3V Voltage Regulator U13 ON Semiconductor MC33269DT 3 3 1 1 8V Voltage Regulator U14 ON Semiconductor MC33269DT ADJ 1 NET2270 U15 NetChip NET2270 1 DS1818 U20 Dallas Semiconductor DS1818 Resistors 12 2700 R1 R5 R75 R80 R83 SMEC RC73L2A2700HMJT 5 5 1KQ R6 R10 R13 R14 R16 SMEC RC73L2A5 1KOHMJT 2 510 R7 R9 5 RC73L2A51OHMJT 56858EVM Bill of Material Rev 3 Freescale Semiconductor Appendix B 1 Qty Description Ref Designators Vend
6. 1008 12010 Josey Z Y 3 8 II Jo 219945 uBiseq 0454 2002 ot ejeq y i 921 NSQ WA38S898dSQ embed IS 508 3800 1008 42012 13S3H 0192 61 089 XV4 0605 6 087 78568 euozuy 101113 1523 0012 UOISIAIG pJepuels 450 302v 208188 g 800N y el 11 t anyo 820 uod NOLLIQSHS g LASTA 40170 15 ved MOL 894 53 YO NOLLNGHSAd OUI 198 SAR 6 lt ZHNB8Z ZI ES WX lt lt 2 vor SSVdAH 250 Not 9 O a T oi zs MO NOLLQSHS d wi lt ZIN ZHINOO v FA 01 901 168 56858EVM Schematics Rev 3 Appendix A 3 Freescale Semiconductor Aiowaw NVYS 250 159 234g 052 lt a 5 21 II JO 19045 ubiseq 0454 2002 90 1240120 ejeg T 184 NSQ WA38Ss89SdSQ 9216 AHON3N WVHS 289 189 3148 v1va pue 080 WWHDOUd 0148 819 089 4 0608 61 087 98258 euozuy peoy
7. Freescale Semiconductor 2 17 about to start The FSYNC frequency is always the system s sample rate It may be an input to the codec or it may be an output from the codec in data mode The basic codec digital connections are shown in Figure 2 12 Table 2 9 and Table 2 10 The codec s MODE is set by the three MODE selection resistors R42 R44 In the factory default setting of MODE 4 the codec is set to be the master of the ESSI bus with its data word set at 32 bits per frame i e 16 bits Left channel and 16 bits Right channel The sample rate is selected on the Sample Rate Selector switch S5 see Table 2 8 for selection options Codec control information is sent over a separate serial port using PC3 as the Control Chip Select signal CCS PE2 as the Control Data Input signal CDIN and PE3 as the Control Clock signal CCLK CODEC Enable Logic CS4218 Figure 2 12 CS4218 Stereo Audio Codec Table 2 9 ESSI Port Connector Description SDIN SDOUT SCLK FSYNC RESET JG6 Pin Controller Signal Pin Codec Signal 1 STDO 2 SDIN 3 SRDO 4 SDOUT 5 SCKO 6 SCLK 7 SC02 8 FSYNC 9 PC4 10 RESET DSP56858EVM User Manual Rev 3 2 18 Freescale Semiconductor Table 2 10 GPIO Port Connector Description JG7 Pin Controller Signal Pin Codec Signal 1 PC3 2 CCS 3 PE2 4 C
8. 195 1 noru 6 974 1noeg NICE 10088 ginoecu 110841 NIEL 810 10041 121 gt gt LNOLL NILL 00X1 usa sor aoa a a o 8 v Freescale Semiconductor DSP56858EVM User Manual Rev 3 Appendix A 6 99po2 oeJejS 9 ISS 9 V 4 H a 9 8 v J 91 401890 0480 ueufise 2002 01 Aepsin 21 19905 sea exeindod JON 310N Jequin 921 NSQ WA38689SdSQ IS Pers ON 04000 03431 119 91 ISS 00 8 09 6 Tt 0188 619 089 xv3 060 617 087 00 21 0 78298 euozuy edue 00 9T 0 0 101113 1583 0012 0 6 t 0 UOISIAIG sjonpo4d PIEPUE S 450 00 vC 0 0 1300W 00 26 0 0 SLIGZE WHLSVW 00 89 0 0 0 GHIONIHS TVINHS ZHN 54 SAN LAN 301 y 0N9 NOLDHS Teo 2002 GAOL ani 889418 21 m Ta ii B L 0 02 7 BIW 3192
9. 56858 Evaluation Module User Manual 56F850 16 bit Digital Signal Controllers DSP56858bEVMUM Rev 3 07 2005 freescale com 4 freescale semiconductor TABLE OF CONTENTS Preface vii Chapter 1 Introduction LI d dd 1 2 L2 30625 Configuration Jumpets 1 3 J3 S6555EVNI 1 4 Chapter 2 Technical Summary 41 2013 rrr 2 2 i Data vaa d ad dad dada be 2 3 22 1 rcc 2 3 2 2 2 2 4 23 oF Social EBPROM Data FLASH 2 5 24 R33 Serial RARE P RU 2 6 2 7 OPE RE d orba OR bad ire ewes 2 8 E LID 2 8 PO PEL 2 9 2 8 1 la tis o ETT 2 10 2 8 2 Parallel JTAG Interface Connector idisse gr RR REG 2 11 235 Lead ed hr ER ard oe i Ib e ER IP LES 2 13 1 GUN Ls eee 2 14 PONCE ur ne ce o dad e drach 2 15 212 2 16 223111 Analog Input Outfput 2 17 2412 2 Digtal METGE 2 17 213 Daughter Card ae S 2o qa OR E Rr dea kaskaq 2 19 2 131 Memory Daughter Card Expansion Connector 2 19 2 13 2 Periphera
10. Rev 3 Freescale Semiconductor V DSP56858EVM User Manual Rev 3 vi Freescale Semiconductor Preface This reference manual describes in detail the hardware on the 56858 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freescale 56858 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56858 hardware Appendix A 56858EVM Schematics contains the schematics of the 56858 Appendix B 56858EVM Bill of Material provides a list of the materials used on the 56858EVM board Suggested Reading More documentation on the 56858 and the 56858EVM kit may be found at URL www freescale com Preface Rev 3 Freescale Semiconductor vii Notation Conventions This manual uses the following notational conventions Term or Value Symbol Examples Exceptions Active High Signals No special symbol AO Logic One attached to the signal CLKO name Active Low Signals Noted with an WE In schematic drawings Logic Zero overbar in text and in OE Active Low Signals may be most figures noted by a backslash WE Hexadecimal Values Begin with a sym 0FFO bol 80 Decimal Values No special symbol 10 attached to the 34 number Binary Values
11. 10sse oJd 86896 4 3 Jo 19945 ubiseg 1450 190 590 e 2002 01 Aepsiny 29180 JequnN NSQ AAS8S8994S0 290021 8431 90830 pue 105592014 89898450 0152 61 089 4 0608 819 087 98288 euozuy duel 10113 1863 0012 UOISIAIG S ONPOld 15 50 N QVr00VeOW 0 2 NH gt cdi 08H 031 QVr0OVrZ9N 0 2 MOTTSA y Ur TT 8031 aun QVr00VPLOW 0 2 daa 5 d 84 1 qun QVvr0OVrZ29N 0 2 Nu y oin QVr00VeLOW 0 2 Y 91H 2031 gun 097097495 042 daa AA T Mi d 1031 vin 2105 1108 0108 159 idis 08 488898480 VSSA Vaan OLSSA 6SSA 600 8SSA 800A LSSA LOA 9SSA 900 SSSA saan SSA ESSA ZSSA ISSA 70551 9004 EISSA 29551 LOSSA 1900A 100188 4 F 100189 13844 gt 13834 SNL SNL 1881 1881 HOVH SI Bd DHBHDIOVH 391 MOL vi gd OH1H 03HH 001 Hre 001 SOH iSOH 10L lt a SQu zi 8d HMH SQH MH 118d CHH MHH zHd OGOW od0N 18d L0H 800N 90H 98d 90H 0Hd VQON vaon S8d SQH
12. Daughter Card Expansion connector J2 Table 2 12 shows the port signal to pin assignments Table 2 12 Peripheral Daughter Card Connector Description J2 Pin 2 Signal Pin 2 Signal 1 50 2 CS1 PA1 3 CLKO 4 CS2 PA2 5 TIOO PGO 6 TIO1 PG1 7 CS3 PA3 8 RSTOUT 9 TIO2 PG2 10 TIO3 PG3 11 NC 12 NC 13 GND 14 GND 15 SRDO PC1 16 SRD1 PD1 17 01 4 18 SC11 PD4 19 SCK PF2 20 SCK1 PD2 21 GND 22 GND 23 MOSI PF1 24 SC10 PD3 25 MISO PFO 26 SC12 PD5 27 GND 28 GND 29 SS PF3 30 STD1 PDO 31 00 32 MODA PHO 33 SCO2 PC5 34 MODB PH1 35 RESET 36 MODC PH2 37 GND 38 GND 39 STDO PCO 40 RXD1 PE2 41 SCKO PC2 42 TXD1 PE3 Technical Summary Rev 3 Freescale Semiconductor 2 21 Table 2 12 Peripheral Daughter Card Connector Description Continued J2 Pin Signal Pin Signal 43 IRQB 44 RXDO PEO 45 IRQA 46 TXDO PE1 47 3 3V 48 3 3V 49 GND 50 GND 51 2 14 USB A USB version 2 0 interface controller NetChip NET2270 is connected to the 56858 s external address data bus via CS3 The NET2270 is clocked with a 30 00MHz crystal This allows the NET2270 interface controller to support the USB Full Speed 12 Mb sec USB version 1 1 along with the USB High Speed 480 Mb sec USB version 2 0 bus transfer rates The NET2270 provides a USB Tranceiver Serial Interface Engine USB Protocol Controller E
13. Host Interface a communications port on Freescale s family of controllers Integrated Circuit Joint Test Action Group a bus protocol interface used for test and debug Light Emitting Diode Low Profile Quad Flat Pack package Multi Purpose Input and Output port on Freescale s family of controllers shares package pins with other peripherals on the chip and can function as a GPIO Printed Circuit Board Phase Locked Loop Random Access Memory Read Only Memory Serial Communications Interface a communications port on Freescale s family of controllers Preface Rev 3 Freescale Semiconductor ix SPI Serial Peripheral Interface a communications port on Freescale s family of controllers SRAM Static Random Access Memory SSI Synchronous Serial Interface a communications port on Freescale s family of controllers THD Total Harmonic Distortion USB Universal Serial Bus WS Wait State References The following sources were referenced to produce this manual 1 DSP56800E Reference Manual DSP56800ERM Freescale Semiconductor 2 DSP5685x 16 Bit Digital Signal Processor User s Manual DSP5685xUM Frees cale Semiconductor 3 DSP56858 16 Bit Digital Signal Processor Technical Data DSP56858 Freescale Semiconductor DSP56858EVM User Manual Rev 3 x Freescale Semiconductor Chapter 1 Introduction The 56858EVM is used to demonstrate the abilities of the 56858 and to provide a hardware tool allowing the development of ap
14. Interface DSP56858EVM User Manual Rev 3 2 4 Freescale Semiconductor 2 3 SPI Serial EEPROM Data FLASH Memory A 1M bit 3 3V SPI serial EEPROM Data FLASH Memory Atmel AT45DB011B SC is provided on the 56858EVM reference Figure 2 3 This memory connects directly to the SPI SPI Serial EEPROM Data FLASH Memory Port through a header on the 56858 It can be used to load program code and data into the 56858 s internal or external memory spaces Jumper block JG10 is provided to allow the user to disconnect the on board SPI EEPROM Data FLASH from the SPI port and allow him to connect his own SPI port peripheral The header details are shown in Table 2 1 56858 Data FLASH Enable Serial EEPROM SPI Port Connector MOSI SRFS MISO SRCK SCLK STCK SS STFS PC3 Data FLASH SDI SDO Figure 2 3 SPI EEPROM Memory Block Diagram Table 2 1 SPI Port Connector Description JG10 Pin Signal Pin Signal 1 SS PF3 2 cs 3 MISO PFO 4 SDO 5 MOSI PF1 6 SDI 7 SCK PF2 8 SCK Technical Summary Rev 3 Freescale Semiconductor 2 5 2 4 RS 232 Serial Communications The 56858EVM provides an RS 232 interface by the use of an RS 232 level converter Maxim MAX3245EEAI designated as U5 Refer to the RS 232 schematic diagram in Figure 2 4 The RS 232 level converter transitions the SCI UART s 3 3V signal levels to RS 232
15. Interface HI Host Interface Connector 4 00MHz 1 8V Power Supply Crystal ATALIEXTAL 3 3V 1 8V 3 3V amp 5 0V amp GND Figure 1 1 Block Diagram of the 56858EVM DSP56858EVM User Manual Rev 3 1 2 Freescale Semiconductor 56858EVM Configuration Jumpers 1 2 56858EVM Configuration Jumpers Ten jumper groups JG1 JG11 shown in Figure 1 2 are used to configure various features on the 56858EVM board Table 1 1 describes the default jumper group settings 2 DSPS68S8EVM RE10519B REV ss HEADPHONE __ Figure 1 2 56858EVM Jumper Reference Table 1 1 56858bEVM Default Jumper Options rom Comment 461 Enable on board Word selectable SRAM via 50 02 1 2 JG2 Enable on board Byte selectable SRAM via CS1 CS2 U3 1 2 3 4 JG3 Use on board EXTAL crystal input for oscillator 2 3 JG4 Use on board XTAL crystal input for oscillator 1 2 JG5 Enable on board Parallel JTAG Host Target Interface NC JG6 Enable ESSIO Port for CODEC data 1 2 3 4 5 6 7 8 9 10 JG7 Enable GPIO for CODEC control 1 2 3 4 5 6 JG8 Enable SCIO Port to RS 232 transceiver 1 2 3 4 JG9 Enable
16. LED2 Port D PD1 LED3 Port D PD2 LED4 Port D PD3 LED5 Port D PD4 LED6 Port D PD5 DSP56858EVM User Manual Rev 3 2 8 Freescale Semiconductor Debug Support Setting PDO PD2 or PDS to a Logic One value will turn on the associated LED INVERTING BUFFER RED LED KR YELLOW LED KR 4 GREEN LED AN RED KR YELLOW LED KR GREEN LED AN VVVVVV Figure 2 6 Schematic Diagram of the Debug LED Interface 2 8 Debug Support The 56858EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Connector Technical Summary Rev 3 Freescale Semiconductor 2 9 2 8 1 JTAG Connector The JTAG connector on the 56858EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56858 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 5 shows the pin out for this connector Table 2 5 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND
17. Y 3 a 9 8 v LL Jo 6 19945 401880 0480 euBiseq 2002 01 Aepsuny 29180 8 21 n NSQ WA38S895dSQ JequnN 9715 __ 0V38 3118834 jueunooq NET P I TND 02 GSN anro NL 40100 L al 210 ML 311070 699 010 0152 61 087 4 0608 819 087 Gees 3118833 o 78508 euozuy VAE O gens c ONE E 10113 1523 0012 TWLIDIG UOISIAIG Sjonpo4d 15 45 T m anro L anro I 30100142 40100 42 20 01 880 180 990 599 SL 301070 90 90 1 Ioane qv3a 3118833 anee o ONE e 0 2213 36136076 ZSSAY Hro A 3388 ISSAV SSAd 2088 Logan LOSSA OISSA 10100A 201881 LOISSA ESSA ZSSA OWS be ISSA UMVING TUTUP 61631 21631 11831 4344 31v 57 i3HH 103 on ova 5 Her 13834 vou oui 450 e ST 903 adi MO oo sz 91191 Gro du I IM s gt I 1n0X i 292 7 T 110412 er ZHINOO 08 ZA 391 M LY xL 7 Noro TT ane 190 ovi ov T LE 5101 v snaa eral era mo er mo t m i anoo L gt 3118834 vag 3118834 099 84 91
18. and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56858EVMUM Rev 3 07 2005
19. that all memory on the board and on the chip is available to the user Introduction Rev 3 Freescale Semiconductor 1 1 1 1 56858EVM Architecture The 56858EVM facilitates the evaluation of various features present in the 56858 part The 56858EVM can be used to develop real time software and hardware products based on the 56858 The 56858EVM provides the features necessary for a user to write and debug software demonstrate the functionality of that software and interface with the customer s application specific device s The 56858EVM is flexible enough to allow a user to fully exploit the 56858 s features to optimize the performance of his product as shown in Figure 1 1 56858 RESET SPI Data FLASH 1M bit IRQ Interface MODE US LOGIC RS 232 DSub 5 10 Interface 9 Pin cso Address Program Memory Data amp 128Kx16 bit SRAM Control CS1 CS2 Peripheral Data Memory 9 Daughter 128Kx16 bit SRAM ESSM Card Connector Memory Daughter Card 9 Connector USB USB Interface i fe 2 Stereo 16 bit Stereo Line In Codec Stereo Line Out Amp Headphone Jack JTAG JTAG EOnCE Connector GPIO e Debug LEDs DSub Parallel 25 JTAG
20. 10113 1884 0012 UOISIAIG 51 PIEPUEIS 450 ON ON IHVSIG WVNS 2N IHVSIG NVUS ON c T WUSVNH ALAE YAMOT WWAS 7 ON WUgSVNH ALAd WHdd WVAS ct HIVE Weds PE Crk WIgHVNH GHOM NVAS TO NOILdO NOILdO 318VN3 089 uadWnfr 318VN3 250 189 ib 1 4149112159 4 4149112 59 SSA 8n SSA an SSA 81 SSA 81 35 30 2 ME PL 3M 3M ym 0594 L lt 089 30 30 qu aon aan sy 91V 91 ar 9 00 siy sia 9100 SLY SLY T 100 21 via 21 vig ZE 8T piv 094 Hi e 7100 ely eld ely 100 ziy 210 ZLY AH 2100 03 LLY 1 00 ory pg 01d OLV 0 00 6v tt Xs 600 bg 80 av tar 00 20 LY 100 oy bgp 90 9v sd 900 sy fyr 54 sv soa wh 3 ra mr roa ey a JT ev q 19 21 0 za ov r H 200 IE La LV oy 00 ov En en 250 150 052 Freescale Semiconductor DSP56858EVM User Manual Rev 3 Appendix A 4 ROWN WO3d33 leues HA AL 1 145 pue 15 t V 4 Appendix A 5 JO v 1994 ubiseq 0484 ueuBiseq 2002 0 Aepsinul ejeg
21. 2 Power Connector 1 DE9S Connector P3 AMPHENOL 617 C009S AJ120 3 1 8 Stereo Jack P4 P6 Switchcraft 35RAPC4BHN2 2 51 Pin HD Connector J1 J2 BERG 91930 21151 1 7 x 2 Bergstick J3 SAMTEC TSW 107 07 S D 1 10 x 2 RT Bergstick J4 SAMTEC TSW 110 07 S D RT 1 Type B USB J5 Mill Max 897 30 004 90 000000 1 2 Pin Terminal Block TB1 On Shore Technology ED500 2DS Switches 3 SPST Pushbutton 51 53 Panasonic EVQ PADO5R 2 3 Position DIP SW S4 S5 CTS 209 3LPST Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Miscellaneous 20 2mm Shunt SH1 SH20 Samtec 2SN BK G 4 Rubber Feet RF1 RF4 3M SJ5018BLKC DSP56858EVM User Manual Rev 3 Appendix B 4 Freescale Semiconductor INDEX C Clock Source 2 7 Codec Preface ix Connectors Host Interface 2 23 D Daughter Card Connectors 2 19 Daughter Card Expansion interface 2 1 Debugging 2 8 DIP Preface ix DSP56858EVM 12 0V DC power supply 2 15 1 M bit Serial EEPROM Data FLASH 2 1 128Kx16 bit of memory 2 1 16 bit 1 8V 3 3V Digital Signal Processor 2 1 16 bit stereo codec interface 2 1 4 00MHz crystal oscillator 2 1 Codec sample rate selector 2 1 connecting to the PC 1 4 Development Card 2 1 external oscillator frequency input 2 1 FSRAM 2 1 GPIO compatible peripheral 2 2 Host Interface Connector 2 2 interconnection diagram 1 4 ISSI compatible peripheral 2 2 JTAG port interface 2 1 Memory Daughter Caard Expansion Connector 2 2 O
22. 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 DE 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG5 Reference Table 2 6 for this jumper s selection options Table 2 6 Parallel JTAG Interface Disable Jumper Selection JG5 Comment No jumpers On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface DSP56858EVM User Manual Rev 3 2 10 Freescale Semiconductor Debug Support 2 8 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P1 allows the 56858 to communicate with a Parallel Printer Port on a Windows PC reference Figure 2 7 Using this connector the user can download programs and work with the 56858 s registers Table 2 7 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG5 should be removed as shown in Table 2 6 DB 25 Connector Parallel JTAG Interface TDI IN OUT TDO OUT IN P TRST OUT TMS OUT TCK OUT RESET OUT P DE OUT JG5 Jumper Removed Enable JTAG Jumper Pin 1 2 Disable JTAG I F Figure 2 7 Block Diagram of the Parallel JTAG Interface Technical Summary Rev 3 Freescale Semiconductor 2 11 Table 2 7 Parallel JTAG Interface Connector Description
23. 81 ES 601 60 _ 1198 801 80 Sed 4 4488 101 La S seu 4088 901 90 gt 2881 501 80 POND TES 4 y 90 01 va 2 ge Wa eq wa 201 Er L SE 101 10 nasr e 1058 001 og sin DSP56858EVM User Manual Rev 3 Freescale Semiconductor Appendix A 10 seiddng 0L V 941614 n 10 0 JO 01 12945 21 401894 0450 ueuBiseg 2002 O Menuer epsinul ejeg V 69cCttoON NSQ IWA38S849SdSG JequinN 9215 54114405 H3MOd L 0152 61 089 xvJ 78268 euozuy 10113 1523 0012 UOISIAIG 83 pJepuels 450 0608 8619 087 SHOLVIOOSH s A0 S A6 T 107 AS 2 107 uPruH MOTH T OGAOL 37 L 199 ASI O 37127 990 ST LET ST tvc ST LOT N H H 2 MOTU MOTU MOTU 3noA 3114434 3114434 MOTU 961 eve 189 10692660 1 LNOA T vin a 6 6 10692660 1 t VAN LNOA LNOA NIA ein 1007 3 859 avaag x 022 8u Ager 3114434 3114434 T VA0 S G 1069cEEOW LNOA AAW 1 L00vN LOdNI 4
24. Begin with the letter b1010 p attached to the b0011 number Numbers Considered positive 5 Voltage is often shown as unless specifically 10 positive 3 3V noted as a negative value Blue Text Linkable on line refer to Chapter 7 License Bold Reference sources See paths emphasis www freescale com DSP56858EVM User Manual Rev 3 viii Freescale Semiconductor Definitions Acronyms and Abbreviations Definitions acronyms and abbreviations for terms used in this document are defined below for reference Codec DIP EEPROM EOnCE ESSI EVM GPIO HI IC JTAG LED LQFP MPIO PCB PLL ROM SCI COder DECoder a part used to convert analog signals to digital coder and digital signals to analog decoder Dual Inline Package Electrically Erasable Programmable Read Only Memory Enhanced On Chip Emulation a debug bus and port created by Freescale to enable a designer to create a low cost hardware interface for a professional quality debug environment Enhanced Synchronous Serial Interface a communications port on Freescale s family of controllers Evaluation Module a hardware platform which allows a customer to evaluate the silicon and develop his application General Purpose Input and Output port on Freescale s family of controllers does not share pin functionality with any other peripheral on the chip and can only be set as an input output or level sensitive interrupt input
25. DIN 5 PE3 6 CCLK 2 13 Daughter Card Connectors The EVM board contains two daughter card expansion connectors One connector J1 contains the controller s external memory bus signals The other connector J2 contains the controller s peripheral port signals 2 13 1 Memory Daughter Card Expansion Connector Daughter Card Connectors The controller s external memory bus signals are connected to the Memory Daughter Card Expansion connector J1 Table 2 11 shows the port signal to pin assignments Table 2 11 Memory Daughter Card Connector Description J1 Pin Signal Pin Signal 1 A10 2 11 3 A9 4 CS1 5 6 15 7 7 8 14 9 20 10 19 11 WR 12 A13 13 DO 14 A12 15 D1 16 D8 17 D2 18 D9 Technical Summary Rev 3 Freescale Semiconductor 2 19 Table 2 11 Memory Daughter Card Connector Description Continued J1 Pin Signal Pin Signal 19 GND 20 GND 21 D3 22 D10 23 D4 24 D11 25 D5 26 D12 27 D6 28 D13 29 A18 30 A17 31 D7 32 D14 33 cso 34 D15 35 AO 36 RD 37 A1 38 A6 39 A16 40 GND 41 A2 42 A5 43 A3 44 A4 45 CS3 46 CS2 47 3 3V 48 3 3V 49 GND 50 GND DSP56858EVM User Manual Rev 3 2 20 Freescale Semiconductor 2 13 2 Peripheral Daughter Card Expansion Connector Daughter Card Connectors The controller s peripheral port signals are connected to the Peripheral
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27. O T1 9 1 0uF 25V DC C3 C5 C14 C16 C18 C22 SMEC MCCE105K3NR T1 2 0 0022uF C7 C8 SMEC MCCE222K2NR T1 3 0 47 uF C9 C11 SMEC MCCE474K3NR T1 8 47uF 16V DC C12 C15 C17 C55 C57 C59 ELMA RV2 16V470M R C63 C69 25 0 1uF C13 C23 C25 C27 C29 C31 SMEC MCCE104K2NR T1 C33 C35 C37 C39 C41 C43 C44 C46 C48 C50 C52 C54 C56 C58 C67 C68 C72 18 0 01uF C26 C28 C30 C32 C34 C36 SMEC MCCE103K2NR T1 C38 C40 C42 C45 C49 C51 C60 C64 C66 C70 C71 1 470uF 16V DC C53 ELMA RV 16V471MH10R 2 15pF C61 C62 SMEC MCCE150J2NO T1 Jumpers 4 1 x 2 2mm Header JG1 JG5 JG9 JG11 SAMTEC TMM 102 02 S S 2 2 x 2 2mm Header JG2 JG8 SAMTEC TMM 102 02 S D 2 3 x 1 2mm Header JG3 JG4 SAMTEC TMM 103 02 S S 1 5 x 2 2mm Header JG6 SAMTEC TMM 105 02 S D 1 3 x 2 2mm Header JG7 SAMTEC TMM 103 02 S D 1 4 x 2 2mm Header JG10 SAMTEC TMM 104 02 S D 56858EVM Bill of Material Rev 3 Freescale Semiconductor Appendix B 3 Qty Description Ref Designators Vendor Part s Test Points 4 Black Test Point TP1 TP3 TP6 TP7 Keystone 5001 1 Red Test Point TP2 Keystone 5000 1 White Test Point TP4 Keystone 5002 1 Yellow Test Point TP5 Keystone 5004 Crystals 1 4 00MHz Crystal Y1 CTS ATSO4ASM T 1 30 00MHz Crystal Y2 Epson MA 306 30 000M C2 Connectors 1 DB25M Connector P1 AMPHENOL 617 C025P AJ121 1 2 1mm coax P2 Switchcraft RAPC 72
28. RS 232 output NC JG10 Enable SPI Port to Serial EEPROM Data FLASH 1 2 3 4 5 6 amp 7 8 JG11 Enable USB interface via CS3 1 2 Introduction Rev 3 Freescale Semiconductor 1 3 1 3 56858EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12 0V DC AC power supply or external 5 0V DC lab power supply to the 56858EVM board Parallel Extension Cable 56858EVM PC compatible Computer 2 2 Connect cable L nmHP2 to Parallel Printer port External 5 0V with 2 4mm 49 Lab receptacle P connector en Suny Figure 1 3 Connecting the 56858EVM Cables Perform the following steps to connect the 56858EVM cables 1 Connect the parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56858EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12 0V DC 1 2A switching power supply or the external 5 0V DC 1A lab power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external switching power supply into P2 shown in Figure 1 3 on the 56858EVM board Optionally attach an external 5 0V DC lab power supply via the 2 pin terminal block TB1 5 Apply power to the external power su
29. Schematic Diagram of the Power 2 15 CODEC Analog Connections ese kk 2 17 ORA IS Stereo Lora ad dI Eae oo 2 18 Diagram or the USB 2 22 List of Figures Rev 3 Freescale Semiconductor iii DSP56858bEVM User Manual Rev 3 Freescale Semiconductor 1 1 2 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 LIST OF TABLES 56858EVM Default Jumper Options 1 3 SPI Port Connector Dee dd an da d ERE abd dee od 2 5 RS 232 Serial Connector aid us dudes br A 2 6 Operatins Mode Selection uu aqu eye e aX es AE eee En 2 8 pla js RICE 2 8 s serr areri irk dob ER e D RR ole doe 2 10 Parallel JTAG Interface Disable Jumper Selection 2 10 Parallel JTAG Interface Connector Description 2 12 Codec Sample Rate caa 2 16 ESSI Port Connector Desciipton 2 18 GPIO Port Connector duae a das RR RR Kar aa 2 19 Memory Daughter Card Connector Description 2 19 Peripheral Daughter Card Connector 2 21 Host Interface Connector 2 23 List of Tables
30. ale Semiconductor 1o 9 uuoo pue 1 OVI JojeJed V 4 3 JO 4 19995 401880 0484 euDiseq 2002 01 Aepsiny 29180 8 21 92 NSQ WA38S89SdSQ IS a a t HOLOANNOD ANY 39Y4431NI LADYVL LSOH T3T VHVd L 0152 61 087 4 060S Lp 087 NEZZCNC 98268 euozuy eduaj 101113 1523 0012 1 5 UOISIAIG sjonpo4d 5 460 acum Eee 002 00994 T 1030euuo OWL isu n 2 L 20 I siu 001 aie kat xe i Is tie su LE 002 0020 10 188884 2 01648338 f uod 158177 13838 or 13538 T7 13638 T7 ars Coo Ag e AE 198117 E 30 d I eoegaequI paeog uo ANANAS wszaa 307 TE 2 ola Las 99 ee T Co m 103NNO9 1HOd o KN or 289 dad 9 uuo 18 aan 180d on 9 x 0 2 vA 90A 1804 po sar 042 otr qe 2 T 1804 d iiy WE Cr oia 1881 14047 S f PVE bg 1808 ol Ser evt bg iis X91 1804 7 Sols se avt SWI 1804 za iu G 13538 1804 5 8m 0 2 zu 2 4 0 2 IN3
31. compatible signal levels and connects to the host s serial port via connector P3 Flow control is not provided but could be implemented using uncommitted GPIO signals The pinout of connector P3 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by placing a jumper at JG9 RS 232 Level Converter Interface T1in Riout FORCEOFF Jumper Removed Enable RS 232 Jumper Pin 1 2 Disable RS 232 Figure 2 4 Schematic Diagram of the RS 232 Interface Table 2 2 RS 232 Serial Connector Description P3 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXDO 7 Jumper to 8 3 RXDO 8 Jumper to 7 4 Jumper to 1 amp 6 9 N C 5 GND DSP56858EVM User Manual Rev 3 2 6 Freescale Semiconductor Clock Source 2 5 Clock Source The 56858EVM uses a 4 00MHz crystal Y 1 connected to its external crystal inputs EXTAL and XTAL To achieve its 120MHz maximum operating frequency the 56858 uses its internal PLL to multiply the input frequency by 30 An external oscillator source can be connected to the controller by using the oscillator bypass connectors JG3 and JG4 see Figure 2 5 If the input frequency is above 4MHz then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2 The input frequency would then be injected on JG3 s pin 2 If the controller needs to be synchronized to the codec s sample frequency then the
32. controller s input frequency should be jumpered using the 12 2280MHz codec frequency If the input frequency is below 4MHz then the input frequency can be injected on JG4 s pin 2 EXTERNAL OSCILLATOR HEADERS 12 2880MHz Figure 2 5 Schematic Diagram of the Clock Interface Technical Summary Rev 3 Freescale Semiconductor 2 7 2 6 Operating Mode 56858EVM provides a boot up MODE selection switch S4 This switch is used to select the operating mode of the controller as it exits RESET Refer to the DSP56858 User s Manual for a complete description of the chip s operating modes Table 2 3 shows the two operation modes available on the 56858 Table 2 3 Operating Mode Selection Operating Mode S4 ON Comment 0 1 2 3 4 amp 5 6 Bootstrap from External byte wide memory 1 3 4 amp 5 6 Bootstrap from SPI 2 1 2 amp 5 6 Normal Expanded mode 3 5 6 Development Expanded mode 4 1 2 amp 3 4 Host Interface Port Single Strobe mode 5 3 4 Host Interface Port Dual Strobe mode 2 Debug LEDs Six on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 6 Table 2 4describes the control of each LED Table 2 4 LED Control Controlled by User LED Signal LED1 Port D PDO
33. d 1804 OWLE DSP56858EVM User Manual Rev 3 Freescale Semiconductor Appendix A 8 10 D9UUOD uoisuedx3 8 ll Jo 819945 ubiseq 0484 ueuBiseq 200201 Aepsinyy ejeq V NSQ INA38S89SdS a JequinwN 9215 SHOLO3NNOO NOISNVdXd QHVO H31HO9flVGO oy 0152 61 089 XvJ 0605 61 087 78268 euozuy 101113 1523 0012 UOISIAIG 8 pJepuels 450 GND oax 289 oaxu c vv aX Sv tud cud TS 800N Ix sia vid 1015 LN 210 28 21 010540899 edd 4 010 ANS 1498 203 1195 zaa 6a 485 ely golL 61V LNOLSH mE 21 LOIL SLY 255 192 189 189 zua LLY Sd QN9 OLV 56858EVM Schematics Rev 3 Appendix A 9 Freescale Semiconductor 19 ou02 0 2 ASN 6 V 21614
34. e main power input 12 0V DC AC to the 56858EVM is through a 2 1mm coax power jack An optional 5 0V DC power supply input is available through a 2 pin terminal block TB1 A 12 0V DC 1 2A power supply is provided with the 56858EVM however less than 500mA is required by the EVM The remaining current is available for user daughter card applications when connected to the daughter card interface The power regulation on the 56858EVM provides 5 0V DC voltage regulation for the codec s analog circuits and to the additonal voltage regulation logic on the EVM The additonal voltage regulation logic provides 1 8V DC voltage regulation for the controller s core and 3 3V DC voltage regulation for the controller s I O memory parallel JTAG interface and supporting logic refer to Figure 2 10 Power applied to the 56858EVM is indicated with a Power On LED referenced as LED7 12 0V DC 5 0V Power 5 0V DC Regulator Condition Analog 3 3V Regulator 56858EVM PARTS 1 8V Regulator Figure 2 10 Schematic Diagram of the Power Supply Technical Summary Rev 3 Freescale Semiconductor 2 15 2 12 Stereo Codec A 16 bit audio quality stereo codec Crystal Semiconductor CS4218 is connected to the 56858 s ESSI port to support audio voice and signal analysis applications The codec is clocked with a 12 288MHz oscillator Th
35. ice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages
36. is allows the codec to operate between a sample frequency of 8KHz and 48KHz The sample rate can be manually set by setting the appropriate switch positions on DIP switch S5 The sample rate selections possible using this three position dip switch are detailed in Table 2 8 The codec supports 3 3V digital levels eliminating the need for voltage level translation circuitry Additionally a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the on board codec from the ESSI port and allow him to connect his own codec to the ESSI port see Figure 2 12 The on board codec has analog signal conditioning logic allowing direct connection to its line level input and line level output signals through two 1 8 stereo jacks reference Figure 2 11 Table 2 8 Codec Sample Rate Selector SW 5 SW 5 SW 5 Position 3 Position 2 Position 3 Sample Rate MF6 MF7 MF8 ON ON ON 48 00KHz ON ON OFF 32 00KHz ON OFF ON 24 00KHz ON OFF OFF 19 20KHz OFF ON ON 16 00KHz OFF ON OFF 12 00KHz OFF OFF ON 9 60KHz OFF OFF OFF 8 00KHz DSP56858EVM User Manual Rev 3 2 16 Freescale Semiconductor Stereo Codec 2 12 1 Analog Input Output The 56858EVM uses jacks for line level stereo input line level stereo output and stereo headphone output A National Semiconductor LM4880 provides the drive required for the use of headphones This device offers a THD which is superior by a factor of tw
37. l Daughter Card Expansion 2 21 POS o a hand oa Sha ee 2 22 2 15 Host Interface Connector uds Se ooo oobi oes bee e 2 23 TD 2 23 Table of Contents Rev 3 Freescale Semiconductor i Appendix A 56858EVM Schematics Appendix B 56858EVM Bill of Material DSP56858EVM User Manual Rev 3 ii Freescale Semiconductor i i b id 2 1 23 2 3 2 4 2 5 2 6 2 8 2 9 2 10 2 11 215 2 13 LIST OF FIGURES Block Diagram of the 1 2 S6838EVM Jumper Referenc rrii oprig 1 3 Connecting the 568586EV M dura ER ERO od ie een 1 4 Schematic Diagram of the External CSO Memory Interface 2 3 Schematic Diagram of the External CS1 CS2 Memory Interface 2 4 SPI EEPROM Memory Block Diggins ua aci EROR ORCI ROI 2 5 Schematic Diagram of the 2 6 Schematic Diagram of the Clock 2 7 Schematic Diagram of the Debug LED Interface 2 9 Block Diagram of the Parallel JTAG Interface 2 11 Schematic Diagram of the User Interrupt Interface 2 13 Schematic Diagram of the RESET Interface 2 14
38. m speed of 120MHz A full description of the 56858 including functionality and user information is provided in these documents DSP56858 Technical Data DSP56858 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and available packaging DSP5685x User s Manual DSP5685xUM Provides an overview description of the controller and detailed information about the on chip components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem DSP56800E Reference Manual DSP56800ERM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set Refer to these documents for detailed information about chip functionality and operation They can be found on this URL www freescale com DSP56858EVM User Manual Rev 3 2 2 Freescale Semiconductor Program and Data Memory 2 2 Program and Data Memory The 56858EVM contains two 128Kx16 bit Fast Static RAM banks SRAM bank 0 is controlled by CSO and SRAM bank 1 is controlled by CS1 and CS2 2 2 1 SRAM Bank 0 SRAM bank 0 which is controlled by CSO uses a 128 16 01 Fast Static RAM GSI GS72116 labelled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 CSO can be configured to use this memory bank as 16 bit program memo
39. n board power regulation 2 2 Parallel JTAG Host Target Interface 2 1 power connection cable connection 1 4 real time debugging 2 8 RS 232 interface 2 1 SCI compatible peripheral 2 2 SPI compatible peripheral 2 2 test points 2 23 USB interface 2 2 E EEPROM Preface ix EOnCE Preface ix ESSI Preface ix EVM Preface ix F FSRAM 2 3 2 4 G GPIO Preface ix H HI Preface ix Host Parallel Interface Connector 2 9 Host Target Interface 2 9 IC Preface ix J JTAG Preface ix 1 1 2 1 connector 2 10 Jumper Group 101 1 3 JG10 1 3 JG11 1 3 JG2 1 3 JG3 1 3 JG4 1 3 105 1 3 JG6 1 3 JG7 1 3 108 1 3 JG9 1 3 Jumper Options 1 3 L LED Preface ix LQFP Preface ix M MPIO Preface ix Operating Mode 2 8 Index Rev 3 Freescale Semiconductor Index 1 P PCB Preface ix PLL Preface ix power supply external 1 4 R RAM Preface ix ROM Preface ix RS 232 interface 2 1 2 6 level converter 2 6 schematic diagram 2 6 RS 232 Serial Communications 2 6 S SCI Preface ix SPI Preface x SRAM Preface x external data 2 1 external program 2 1 SSI Preface x stereo 16 bit codec interface 2 1 Stereo headphone interface 2 1 T THD Preface x U USB Preface x 2 22 schematic diagram 2 22 W WS Preface x DSP56858EVM User Manual Rev 3 Index 2 Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not
40. ndpoint FIFOs Local Bus Interface and Configuration Registers Refer to the USB diagram in Figure 2 13 The USB Interface s use of CS3 can be disabled by removing the jumper at JG11 USB Interface Jumper Pin 1 2 Enable USB Jumper Removed Disable USB Figure 2 13 Diagram of the USB Interface DSP56858EVM User Manual Rev 3 2 22 Freescale Semiconductor Test Points 2 15 Host Interface Connector The 56858EVM board contains a Host Interface connector The HI connector J4 provides the signals present on the 56858 s HI port Table 2 13 shows the HI connectors signal to pin assignments Table 2 13 Host Interface Connector Description J4 Pin Signal Pin Signal 1 HDO 2 HD1 3 HD2 4 HD3 5 HD4 6 HD5 7 HD6 8 HD7 9 HAO 10 HA1 11 HA2 12 HRW 13 HDS 14 HCS 15 HREQ 16 HACK 17 3 3V 18 GND 19 3 3V 20 GND 2 16 Test Points The 56858EVM board has a total of seven test points Three digital GND test points are located in corners of the board The 5 0VA and AGND test points are located in the analog corner of the board The 1 8V and 3 3V test points are located in the power supply section of the board Technical Summary Rev 3 Freescale Semiconductor 2 23 DSP56858EVM User Manual Rev 3 2 24 Freescale Semiconductor Appendix A 56858EVM Schematics 56858EVM Schematics Rev 3 Freescale Semiconductor Appendix A 1 sq31 pue
41. o to the CS4218 s on chip headphone drive circuitry The basic Analog codec connections are shown in Figure 2 11 CS4218 RIN1 LOUTL Line Level Line Level Input LIN1 LOUTR Output LM4880 Headphone Output Figure 2 11 CODEC Analog Connections 2 12 2 Digital Interface The serial interface of the codec transfers digital audio data and control data into and out of the device The ESSI port consists of independent transmitter and receiver sections and is used for serial communication with the codec On the controller side the Serial Transmit Data pin STDO is an output when data is being transmitted to the codec The Serial Receive Data pin SRDO is an input when data is being received from the codec These two pins are connected to the codec s Serial Data Input SDIN and Serial Data Output SDOUT pins The controller s Transmit Serial Clock pin SCKO provides the serial bit rate clock for the ESSI interface It is connected to the CODEC s Serial Port Clock pin SCLK Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK The controller s GPIO PORT C Bit 4 pin PC4 is programmed to control the codec s Active Low Reset signal RESET The Serial Transmit Frame Sync pin 5 02 is programmed to control the codec s Frame Sync signal FSYNC This signal is sampled by SCLK with a rising edge indicating a new frame is Technical Summary Rev 3
42. or Part s Resistors Continued 1 10M Q R8 SMEC RC73L2A10MOHMJT 4 47K Q R11 R12 R15 R88 SMEC RC73L2A47KOHMJT 4 5 62K Q 1 R19 R20 R23 R25 SMEC RC73L2A5 62KOHMFT 29 10K R21 R22 R24 R26 R29 R31 SMEC RC73L2A10KOHMJT R34 R36 R38 R53 R60 R64 R67 R71 R73 R90 R92 2 39 2K Q 1 R27 R28 SMEC RC73L2A39 2KOHMFT 13 1KQ R32 R33 R45 R52 R61 R63 SMEC RC73L2A1KOHMJT 4 20 0K Q 1 R37 R39 R41 SMEC RC73L2A20 0KOHMFT 2 00 R42 R43 SMEC RC73JP2A 0 00 R44 SMEC RC73JP2A 0 10K R68 SMEC RC73L2A10KOHMJT 3 470 R69 R70 R74 SMEC RC73L2A470KOHMJT 1 243 1 R81 5 RC73L2A2430HMFT 1 1070 1 R82 SMEC RC73L2A107OHMFT 2 35 7 O 1 R84 R85 SMEC RC73L2A35 70HMFT 1 1 5K O R86 SMEC RC73L2A1 5KOHMJT 1 1M O R87 SMEC RC73L2A1MOHMJT 1 9 09K Q 1 R89 SMEC RC73L2A9 09KOHMFT Inductors 4 1 0mH FERRITE BEAD L1 L4 Panasonic EXC ELSA35V 5 FERRITE BEAD L5 L9 TOKO FLSM2520 1ROJ LEDs 2 Red LED LED1 LED4 Hewlett Packard HSMS C650 2 Yellow LED LED2 LED5 Hewlett Packard HSMY C650 3 Green LED LED3 LED6 LED7 Hewlett Packard HSMG C650 DSP56858EVM User Manual Rev 3 Appendix B 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Diodes 1 S2B FM401 D1 Vishay DL4001DICT 1 50V 1A BRIDGE RECT D2 DIODES DF02S Capacitors 2 0 33uF C1 C6 SMEC MCCE334K3NR T1 2 470pF C2 C4 SMEC MCCE471J2N
43. plications that use the 56858 The 56858EVM is an evaluation module board that includes a 56858 part 16 bit stereo codec USB 1 1 2 0 interface external memory and a daughter card expansion interface The daughter card expansion connectors are for signal monitoring and user feature expandability The 56858EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800E architecture The tools and examples provided with the 56858EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG Enhanced OnCE EOnCE port The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory and peripherals through the EOnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the controller s peripherals The EOnCE port s unobtrusive design means
44. pply The green Power On LED LED7 will illuminate when power is correctly applied DSP56858EVM User Manual Rev 3 1 4 Freescale Semiconductor Chapter 2 Technical Summary The 56858EVM is designed as a versatile controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging digital answering machines feature phones modems and digital cameras The power of the 16 bit 56858 controller combined with the on board 128K x 16 bit external program data static RAM SRAM 128K x 16 bit external data program SRAM RS 232 interface Stereo 16 bit codec interface USB 2 0 interface Daughter Card Expansion interface and parallel JT AG interface makes the 56858EVM ideal for developing and implementing many audio and voice algorithms as well as for learning the architecture and instruction set of the 56858 processor The main features of the 56858EVM with board and schematic reference designators include 56858 16 bit 1 8V 3 3V Digital Signal Processor operating at 120MHz 01 External fast static RAM FSRAM memory configured as 128Kx16 bit of memory U2 with one wait state at 120MHZ via CSO 128Kx16 bit of memory U3 with one wait state at 1220M Hz via CS1 CS2 M bit Serial EEPROM Data FLASH U4 4 00MHz crystal oscillator for controller frequency generation Y 1 Optional external oscillator frequency input connector
45. ry data memory or both Additionally CSO can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with wait state access while the 56858 is running at 120MHz and can be disabled by removing the jumper at JG1 GS72116 0 16 000 0015 Jumper Pin 1 2 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External CS0 Memory Interface Technical Summary Rev 3 Freescale Semiconductor 2 3 2 2 2 SRAM Bank 1 SRAM bank 1 which is controlled by CS1 and CS2 uses a 128Kx16 bit Fast Static RAM GSI GS72116 labeled U3 for external memory expansion see the FSRAM schematic diagram in Figure 2 2 Using CS1 and CS2 this memory bank can be configured as byte 8 bit or word 16 bit accessable program memory data memory or both Additionally CS1 and CS2 can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with one wait state access while the 56858 is running at 120MHz and can be disabled by removing the jumpers at JG2 GS72116 0 16 000 0015 RD OE WR WE LB CS2 HB CE Jumper Pin 1 2 Enable SRAM Low Byte Jumper Pin 3 4 Enable SRAM High Byte Figure 2 2 Schematic Diagram of the External CS1 CS2 Memory
46. s JG3 and JG4 Joint Test Action Group JTAG port interface connector for an external debug Host Target Interface J3 On board Parallel Host Target Interface with a connector for a PC printer port cable P1 RS 232 interface for easy connection to a host processor U5 and P3 16 bit stereo codec interface U6 JG6 JG7 and P5 Stereo headphone interface U8 and P6 Codec sample rate selector S5 Technical Summary Rev 3 Freescale Semiconductor 2 1 USB interface U15and J5 Peripheral Daughter Card Expansion Connector to allow the user to connect his own SCI ISSI SPI or GPIO compatible peripheral to the controller J2 Memory Daughter Card Expansion Connector to allow the user to connect his own memory or memory device to the controller J1 Host Interface Connector for high speed bus data transfer J4 On board power regulation from an external 12V DC supplied power input P2 On board power regulation from an optional 5V DC supplied power input Light Emitting Diode LED power indicator LED7 Six on board real time user debugging LEDs LED1 6 Boot MODE selector S4 Manual RESET push button S1 Manual interrupt push button for IRQA S2 Manual interrupt push button for IRQB S3 2 1 56858 The 56858EVM uses a Freescale DSP56858FV 120 part designated U1 on the board and in the schematics This part will operate at a maximu
47. t 4 F 5 ZIW 109 j vin T SW 5007 0008 910 98 GAOL z NHd dil anit 1 _ 0 02 ani NHi9NH SUME Eg TON 13534 93000 5008 9d 19 DNAST 03000 9 5 20 0498 en Xi0 03000 SS onus 10048 93000 2 0015 1 002 NIQS 23002 HOL MARC TIW A CU 1 X002 D 81280 E LAA Leu OND Ly LD gt aan YOGA 0 85 antes 1115 03909 4128 11005 93909 vetu San Andy anyo ONASS X198 03009 oso ZHNW88Z 2 29 T ER Nad 55 9NASd 23402 ano sau LZ N d E yr 49434 13538 m 1 938 ee d 7 Tr ZHW88Z ZL t T pey S99 3qons eeu 92 2agoms Sow 300MS D ZHNS8Z zi T n T W Ag et 17 S 308438 DEN E HQ To vM TN SaM ocu 201 zz qug E m LAN 010 E Ngo EAN 5 02 5 2190000 3082100 rin Que ype foams 824 Lau 89 1o can ce 22 Ws so 68000 Jon ie anl ELM pe oaas 94 110 dii 59 ino vr 1001 T MW 5 Ase A ONE 51108 INI Er Ni dii Sd 9 TION NI ONIE MOL 3d0 v td wn 22 aneco TO 9 8 v 56858EVM Schematics Rev 3 Appendix A 7 Freesc

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