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the user manual for the HPDI32A

1. Table 5 0 Cable Pin Out No No Pin 80 ol Pin 40 6 LINEVALID GPIOO 8 STATUS VALID GPIO1 9 RXREADY GPIO2 P D 3 2 60 CABLED21 5 B 66 CABLED24 68 CABLED25 69 CABLED26 p epa Pin 4 80 CABLED3I 32 CHAPTER 6 ORDERING INFORMATION 6 0 ORDERING INFORMATION Since HPDI32A is designed to fit a variety of high speed digital interface needs there are several options that must be specified when ordering the HPDI32A board Please consult our sales department with your application requirements to decide on the correct ordering options 6 0 1 BUSINTERFACE RS485 422 Interface The RS485 RS422 interface provides for synchronous bus clock speeds up to 26MHz 104 Mbytes per sec This is the standard interface option PECL Interface The PECL Pseudo ECL interface LVDS and TTL versions of the HPDI32A board are available in the HPDI32ALT version of the board Please visit our website or consult our sales department for more information 6 0 2 FIFO SIZE The HPDI32A can accept FIFOs with depths ranging from 2k words to 128k words Larger FIFO depth is important for faster interfaces to reduce the risk of software overhead Standard configuration of the HPDI32A contains 32k word deep FIFOs 6 0 3 INTERF
2. Cable Cik Four E Frame Valid Frame Valid Los Line Valid Line Invalid Count Line Valid Count Line Invalid Count Line Valid Coun Line Invalid Count Status Valid Status Valid Count Cable Data X do X o1 Y oe 03 X X os Y oe UTD TI 07 X D8 X vo Xoro WWD MTS 1 2 Figure 1 1 HPDI32A Cable Interface FIFOs The FIFOs on the PCI PMC HPDI32A are used for buffering the transmit or receive data This allows the data on cable interface to run independent of the PCI interface There are two sets of FIFOs on the board a set of four FIFOs for transmit data and a second set of four for receive data Each set consists of 32 bits of data and 4 status flags The receive FIFOs are loaded by the cable receive control logic and read by either the CPU or the DMA The transmit FIFOs are loaded by either the CPU or the DMA and read by the cable transmit control logic Four status flags accompany each set the FIFOs Empty Almost Empty Almost Full Full The Almost Empty and the Almost Full status flags can be programmed via software to assert most desired levels within the FIFOs These programmable flags can be used for DMA control throttling cable data or to indicate when a desired amount of data has been received CHAPTER 2 PROGRAMMING 2 0 2 1 2 2 INITIALIZATION Several functions on the HPDI32A board will generally be unchanged
3. 22 220 2 2 10 000000000000000005020 rennen inneren nnns 15 3 8 TX STATUS LENGTH COUNT OFFSET 0 00000016 enne enne 15 3 9 TX LINE VALID LENGTH COUNT OFFSET 0x00000020 cessere 15 310 TX INVALID LENGTH COUNT OFFSET 0 00000024 cesses enne eene enne 16 311 RX STATUS LENGTH COUNTER OFFSET 0 00000028 16 312 RX LINE LENGTH COUNTER OFFSET 0 00000026 2 24241 000000000000000000000 ener enne 16 313 INTERRUPT CONTROL REGISTER OFFSET 0 00000030 enne 16 3 14 INTERRUPT STATUS REGISTER OFFSET 0 00000034 17 3 15 TRANSMIT CLOCK DIVIDER REGISTER OFFSET 0 00000038 17 3 16 TRANSMIT FIFO SIZE OFFSET 0 00000040 22 6 00000000 enne nnne enne enne nen 17 3 17 RECEIVE FIFO SIZE OFFSET OXQ0Q0004 4 ceccccceesscecsesececseececeesececsesaaeeecseeeecseaeeecsesaeeesseeeeeneaee 17 3 18 TRANSMIT FIFO WORDS OFFSET 0 00000048 2 18 3 19 RECEIVE FIFO WORDS OFFSET 0 0000004 lt 22 2 0 02020006000000000000000000000 0000000 18 3 20 INTERRUPT EDGE LEVEL REGISTER OFFSET 0 00000050 22 0 18 3 21 INTERRUPT HI LO REGISTER OFFSET 0 00000054 esses enne enne enne 18 CHAPTER 4 PCEINTEREFA CE sic cssssccsscessvescsstsesssesssnescnseseessesesvosdtsssedecessteeonttectassesesbescssaaessstessensos cseessesestesdenesretes 19 4 0 P
4. D1 D2 D3 D4 D5 D6 D7 D8 D9 D15 10 T O Space A 1 allows the device to respond to I O space accesses Memory Space A I allows the device to respond to memory space accesses PCI Master Enable A 1 allows the device to behave as a PCI bus master Note This bit must be set for the PCI 9080 to perform DMA cycles Special Cycle Not Supported Memory Write Invalidate A 1 enables memory write invalidate VGA Palette Snoop Not Supported Parity Error Response A 0 indicates that a parity error is ignored and operation continues A I indicates that parity checking is enabled Wait Cycle Control Controls whether the device does address data stepping A 0 indicates the device never does address data stepping Note Hardcoded to 0 SERR Enable A 1 allows the device to drive the SERR line Fast Back to Back Enable Indicates what type of fast back to back transfers a Master can perform on the bus A I indicates fast back to back transfers can occur to any agent on the bus A 0 indicates fast back to back transfers can only occur to the same agent as the previous cycle Reserved 4 1 3 PCI STATUS REGISTER Offset 0x06 Reset 0x0280 D5 0 D6 D7 D8 D10 9 D11 Reserved User Definable Features Supported A 47 indicates UDF are supported Note User Definable Features are Not Implemented Fast Back to Back Capable A I
5. indicates Local initialization done PCI PERMANENT CONFIGURATION ID REGISTER PCI 0x70 Reset 0x10B59080 D15 0 D31 16 Permanent Vendor ID 0x10B5 Permanent Device ID 0x9080 PCI PERMANENT REVISION ID REGISTER PCI 0x74 D7 0 Permanent Revision ID 4 4 LOCAL DMA REGISTERS The Local DMA registers are used to setup the DMA transfers to and from the on board FIFOs Since the PCI PMC HPDI32A is half duplex data is only transferred in one direction at a time only DMA Channel 0 is used Table 4 4 DMA Registers PCI Local CFG Offset PCI Local Register Name Value after Addr Addr Writable Reset 0 80 Ox100 0x84 0x04 v DMA Channel 0 PCI Address Regier 000000000 Ox88 0x108 DMA Channel 0 Local Address Register Ox00000000 Ox8C OxIOC Y DMA Channel 0 Transfer Byte Count Register 0 00000000 0x90 0x110 0x94 0x114 0x98 0x118 DMA Channel 1 PCI Address Register Unused 0x00000000 Ox9C_ 0x11C OxAO 0x120 Channel 1 Transfer Byte Count Register Unused 0x00000000 OxA4 0x124 8 0x128 DMA Channel 1Command Status Register DMA Channel 0 Command Status Register 0x12C 0 0 0 130 lt lt lt lt lt 4 4 1 DMA CHANNEL 0 MODE REGISTER PCI 0x80 D1 0 Local Bus Width 00 8 bit DMA transfer width 01 16 bit DMA transfer width 10 11 32 bit DMA transfer width D5 2 Internal Wait States
6. indicates the adapter can accept fast back to back transactions Master Data Parity Error Detected A 1 indicates the following three conditions are met 1 PCI9080 asserted PERR itself or observed PERR asserted 2 PCI9080 was bus master for the operation in which the error occurred 3 Parity Error Response bit in the Command Register is set Writing a 1 to this bit clears the bit DEVSEL Timing Indicates timing for DEVSEL assertion A value of 01 indicates a medium decode Note Hardcode to 01 Target Abort A 1 indicates the PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit 20 D12 Received Target Abort A 1 indicates the PCI9080 has received a target abort Writing a 1 to this bit clears the bit D13 Master Abort A 1 indicates the PCI9080 has generated a master abort signal Writing a 1 to this bit clears the bit D14 Signal System Error A 47 indicates the PCI9080 has reported a system error on the SERR signal Writing a 1 to this bit clears the bit D15 Detected Parity Error A 47 indicates the PCI9080 has detected a PCI bus parity error even if parity error handling is disabled the Parity Error Response bit in the Command Register is clear One of three conditions can cause this bit to be set 1 PCI9080 detected a parity error during a PCI address phase 2 PCI9080 detected a data parity error when it was the target of a write 3 PCI908
7. An on board configuration serial EEPROM initializes many of these registers Table 4 1 PCI Configuration Registers PCI Local CFG Offset PCI Local Register Name Value after Addr Addr Writable R eset 0 00 0x00 Device ID Vendor ID 0x908010B5 0x04 0x04 Y Status Command 0x02800017 0x08 0x08 Class Code Revision ID 0x0680003 Y 0 0 0 0 Y 15 0 BIST Unused Header Type Latency Timer Cache Line Size 0x00002008 Local Y PCI Base Addr 1 for I O Mapped Local Runtime DMA 0x00000001 Registers PCIBAR1 0 10 0x10 PCI Base Addr 0 for Memory Mapped Local Runtime DMA 0x00000000 Registers PCIBARO 0x14 0x14 0x18 0x18 PCI Base Addr 2 for Local Addr Space 0 PCIBAR2 0x00000000 Ox1C Ox1C PCI Base Addr 3 for Local Addr Space 1 PCIBAR3 Unused 0 00000000 Ox2C Ox2C Local Subsystem ID Subsystem Vendor ID 0x90802400 0x30 0x30 PCI Base Address to Local Expansion ROM Unused 0x00000000 0 3 0 3 Y 7 0 Max Lat Min Gnt Interrupt Pin Interrupt Line 0x00000100 Local Note The Local Base Address for the PCI Configuration registers in Local Address Space is 0xC0000000 However there should be no need for the user to access the PCI Configuration registers through Local Address Space 4 1 1 PCI CONFIGURATION ID REGISTER 19 Offset 0x00 Reset 0x908010B5 D15 0 D31 16 Vendor ID 0x10B5 PLX Technology Device ID 0x9080 PCI9080 4 1 2 PCI COMMAND REGISTER Offset 0x04 Reset 0x0017 DO
8. D1 D2 D3 D4 D7 5 Channel 0 Enable Channel 0 Control Channel 0 Abort Clear Interrupt Channel 0 Done Reserved 4 4 7 DMA ARBITRATION REGISTER PCI Same as Mode Arbitration Register MARBR PCI 0x08 See Section 2 2 2 4 4 8 DMA THRESHOLD REGISTER PCI OxBO D3 0 D7 4 D11 8 D15 12 D19 16 D23 20 D27 24 D31 28 DMA Channel 0 PCI to Local Almost Full COPLAF DMA Channel 0 Local to PCI Almost Empty COLPAE DMA Channel 0 Local to PCI Almost Full COLPAF DMA Channel 0 PCI to Local Almost Empty COPLAE DMA Channel PCI to Local Almost Full C1PLAF Unused DMA Channel Local to PCI Almost Empty C1LPAE Unused DMA Channel PCI to Local Almost Full C1LPAF Unused DMA Channel 1 PCI to Local Almost Empty C1PLAE Unused 4 5 MESSAGING QUEUE REGISTERS Messaging queue registers are not used on the PCI PMC HPDI32A 30 CHAPTER 5 HARDWARE CONFIGURATION 5 0 HARDWARE JUMPERS J1 The EEPROM jumper header J1 is a 4x2 header which contains four mini jumpers installed PCI factory default or two jumpers installed PMC factory default These jumpers described below should remain installed for most applications To locate the hardware jumpers view the top side of the card with the cable interface connector to the right The jumper block is located about two inches to the right of the connector in the center of the card The jumpers will number top to bottom with Jumper toward the top and
9. 1 Function Discrete Output Hi D26 D18 Cable Command D2 Setup Control For D18 0 and D26 0 Function Status Valid For D18 0 and D26 1 Function Discrete Input For D18 1 and D26 0 Function Discrete Output Lo For D18 1 and D26 1 Function Discrete Output Hi D27 D19 Cable Command D3 Setup Control For D19 0 and D27 0 Function Rx Ready For D19 0 and 27 Function Discrete Input For D19 1 and D27 0 Function Discrete Output Lo For D19 1 and D27 1 Function Discrete Output Hi D28 D20 Cable Command D4 Setup Control For D20 0 and D28 0 Function Tx Data Ready For D20 0 and D28 1 Function Discrete Input For D20 1 and D28 0 Function Discrete Output Lo For D20 1 and D28 1 Function Discrete Output Hi D29 D21 Cable Command D5 Setup Control For D21 0 and D29 0 Function Tx Enabled For D21 0 and 29 1 Function Discrete Input For D21 1 and D29 0 Function Discrete Output Lo For D21 1 and D29 1 Function Discrete Output Hi D30 D22 Cable Command D6 Setup Control For D22 0 and D30 0 Function Rx Enabled For D22 0 and 030 Function Discrete Input For D22 1 and D30 0 Function Discrete Output Lo For D22 1 and 030 1 Function Discrete Output Hi 023 Reserved For
10. D29 D31 30 Local bus Latency Timer Unused Local bus Pause Timer Unused Local bus Latency Timer Enable Unused Local bus Pause Timer Enable Unused Local bus BREQ Enable Unused DMA Channel Priority 00 Rotational priority 01 Channel 2 priority 10 Channel priority 11 Reserved Local bus direct slave give up bus mode A value of 1 indicates local bus will be released when PCI9080 write FIFO empty or read FIFO full Direct slave LLOCKo Enable Unused PCI Request Mode PCI Rev 2 1 Mode PCI Read No Write Mode PCI Read with Write Flush Mode Gate the Local Bus Latency Timer with BREQ Unused PCI Read No Flush Mode Reads Device Vendor ID or SubDevice SubVendor ID Reserved BIG LITTLE ENDIAN DESCRIPTOR REGISTER PCI 0x0C Since local bus is little endian all bits should be left zero LOCAL ADDRESS SPACE 0 EXPANSION ROM BUS REGION DESCRIPTOR REGISTER PCI 0x18 Reset 0x40030143 D1 0 D5 2 D6 D7 D8 D9 D10 D14 11 D15 D17 16 D21 18 D22 D23 D24 D25 D26 D27 D28 31 Memory Space 0 Local Bus Width 11 indicates 32 bit local bus Memory Space 0 Internal Wait States A 0 indicates no wait states required Memory Space 0 Ready Input Enable A I indicates Local Ready input enabled Memory Space 0 Bterm Input Enable Unused Memory Space 0 Prefetch Disable Unused Expansion ROM Space Prefetch Disable Unused Read Prefetch Count Enable Unused Prefetch Counter Unused
11. FIFO Almost Empty D10 IRQ Source 10 Enable Tx FIFO Almost Full default rising edge Tx FIFO Almost Full D11 IRQ Source 11 Enable Tx FIFO Full default rising edge Tx FIFO Full D12 IRQ Source 12 Enable Rx FIFO Empty default falling edge Rx FIFO Not Empty D13 IRQ Source 13 Enable Rx FIFO Almost Empty default falling edge Rx FIFO Not Almost Empty 16 3 14 3 15 3 16 3 17 D14 IRQ Source 14 Enable Rx FIFO Almost Full default rising edge Rx FIFO Almost Full D15 IRQ Source 15 Enable Rx FIFO Full default rising edge Rx FIFO Full D31 16 Reserved INTERRUPT STATUS REGISTER Offset 0x00000034 The Interrupt Status Register will provide interrupt status for each of the interrupt sources If an interrupt is enabled in the Interrupt Control register the interrupt will be latched in this register until cleared via writing a 1 back to the respective bit If an interrupt is not enabled each bit will represent the current state of the interrupt although the interrupt will not be latched and will not generate a Local Interrupt request D15 0 IRQ 15 0 Status D31 16 Reserved TRANSMIT CLOCK DIVIDER REGISTER Offset 0x00000038 This register will allow the On board Transmit clock to be slowed based on the value in this register The value in this register is the clock divider value If this register contains 0 default or 1 the On board clock is used as the Transmit clock D15 0 Tx Clock Divi
12. IEEE Computer Society Copies of IEEE specifications available from Institute of Electrical and Electronics Engineers Service Center 445 Hoes Lane Piscataway NJ 08855 1331 USA http www ieee org PCI Local Bus Specification Revision 2 1 June 1 1995 Copies of PCI specifications available from PCI Special Interest Group NE 2575 Kathryn Street 17 Hillsboro OR 97124 http www pcisig com TABLE of CONTENTS CHAPTER 1 INTRODUCTION cccisescesscsssvescssossssstsessessnsesvecasseaxesosssssesedsstvessesseesessesvecesseatesetessvesessesvessessoxessesesvecaese 3 1 0 FUNC TONAT DESCRIPTION 5 555 mo meteo eene Some eom nt ORI 3 Figure 1 02 HPDIB2A Block Diagratn peers nente ere err e EO reete de cete c tege eee pied 3 1 1 OON EAEE E eer RET e ed 4 Figure 1 1 HPDIB2A Cable l terf ce ien ie cete GO E RE DOR ee ERE Enti epe rete 4 1 2 gie c M HE 4 CHAPTER 2 PROGRAMMING eos io eo eee rao euo ea cr iR e epar soseste sessao uae eara oops For en eere 5 2 0 INPTITALEUZATION nik da cused es tette eet eee rere eee et eee ee de es 5 221 5 2 2 a 5 2 3 I
13. Only A 1 will indicate the mini jumper on pins J2 1 to J2 2 is installed D17 Board Jumper 1 PCI Only A 47 will indicate the mini jumper on pins J2 3 to J2 4 is installed Note Board jumpers can be used to distinguish between two HPDI32A cards in a system D18 Transceiver Option A 0 indicates RS 485 transceivers are installed A 1 indicates PECL transceivers are installed D20 19 Reserved D21 Tx OverRun A 47 will indicate an attempt to write to the Rx FIFO when the FIFO was full has occurred Since this bit is latched it is cleared by writing a 1 back to D21 D22 Rx UnderRun A 47 will indicate an attempt to read from the Rx FIFO when the FIFO was empty has occurred Since this bit is latched it is cleared by writing a 1 back to D22 D23 Rx OverRun A 47 will indicate an attempt to write to the Rx FIFO when the FIFO was full has occurred Since this bit is latched it is cleared by writing a 1 back to D23 D24 31 Reserved Tx ALMOST FLAG REGISTER Offset 0x0000000C This register is sets the programmed values for the Tx FIFO Almost Empty and Almost Full Flags This value is programmed following a Tx FIFO Reset A Board Reset will reset this register to the default value 0 0010000 and then program this value D15 0 Almost Empty Flag Value D31 16 Almost Full Flag Value Number of available words remaining in FIFO 1 when Flag asserted Rx ALMOST FLAG REGISTER Offset 0x00000010 This
14. PECL Transceivers GPIO Control D24 D16 Cable Command DO Setup Control For D16 0 and D24 0 Function Frame Valid For D16 0 and 24 1 Function Discrete Input For D16 1 and D24 0 Function Discrete Output Lo For D16 1 and 24 1 Function Discrete Output Hi D25 D17 Cable Command D1 D2 Setup Control D25 D17 control the Cable Command D1 and Cable Command D2 direction The direction control is shared between the two signals Cable Command D1 is controlled as follows For D17 0 and D25 0 Function Line Valid For D17 0 and D25 1 Function Discrete Input For D17 1 and D25 Function Discrete Output Lo For D17 1 025 1 Function Discrete Output Hi D26 D18 Cable Command D2 Setup Control For D18 0 and D26 0 and D17 0 and D25 0 Function Status Valid For D17 0 and D25 1 Function Discrete Input For D18 1 D26 0 D17 1 Function Discrete Output Lo For D18 1 D26 1 and 17 1 Function Discrete Output Hi Note Other combinations are indeterminate and should not be used D27 D19 Cable Command D3 D4 Setup Control D27 D19 control the Cable Command D3 and Cable Command D4 direction direction control is shared between the two signals Cable Command D3 is controlled as follows For D19 0 and D27 0 Function Rx Ready For D19 0
15. a bit is setup as an input the Cable Command state may be read through the Board Status register To set a Cable Command as an interrupt source set the signal as a discrete input and setup the interrupt source via the interrupt registers The default configuration for the Cable Command bits is the factory defined cable functions The user will need to re initialize General Purpose IO setup following a board reset If a Cable Command signal is changed from its default function all on board logic associated with that function is disabled NOTE For PECL transceivers the GPIO control is slightly different than for the RS 485 board Since the PECL transceivers are controlled in pairs the direction control for the GPIO signals must be set in pairs rather than individually The PECL GPIO is detailed in section 3 2 Board Control Register 27 LOOPBACK TESTING Even though the HPDI32A interface is half duplex i e the interface signals are defined as transmit mode or receive mode the HPDI32A is capable of receiving the data as it is being transmitted This allows for single board loopback testing To prevent erroneous data from being received the transmit interface should be enabled before the receiver is enabled Then the receiver may be enabled and transmitting of data may begin More information on loopback testing may be found on the General Standards website or contact techsupport generalstandards com for further assistance CH
16. and 27 Function Discrete Input For D19 1 and D27 0 Function Discrete Output Lo For D19 1 and D27 1 Function Discrete Output Hi D28 D20 Cable Command D4 Setup Control For D20 0 and D28 0 D19 0 and D27 0 Function Tx Data Ready For D19 0 and 27 Function Discrete Input For D20 1 D28 0 D19 1 Function Discrete Output Lo For D20 1 and 028 1 and D19 1 Function Discrete Output Hi Note Other combinations are indeterminate and should not be used D29 D21 Cable Command D5 D6 Setup Control D29 D21 control the Cable Command D5 and Cable Command D6 direction The direction control is shared between the two signals For D21 0 D29 0 Function Tx Enabled For D21 0 and D29 1 Function Discrete Input For D21 1 and D29 0 Function Discrete Output Lo For D21 1 and D29 1 Function Discrete Output Hi D30 D22 Cable Command D6 Setup Control For D22 0 and D30 0 and D21 0 and D29 0 Function Rx Enabled For D22 0 and 030 1 Function Discrete Input For D22 1 and D30 0 D21 1 Function Discrete Output Lo For D22 1 and 030 1 and D21 1 Function Discrete Output Hi Note Other combinations are indeterminate and should not be used For Both RS 485 and PECL Transceivers D31 Test Mode Enable Fact
17. in a given application These include interrupt setup FIFO Almost Flag Values and General Purpose IO direction setup Therefore initializing these functions board will generally need to be done only once by the software However if a Board Reset is performed all registers will return to their default values Software must reinitialize the board following a Board Reset RESETS There are three bits in this Board Control Register that are used as resets to the local logic functions These bits perform a reset when the software writes a 17 software does not need to clear the bits following a Reset since the reset bits are self clearing Board Reset Board Control Register DO Setting this bit will reset the local logic reset clear the FIFOs and program the default Almost Flag Values and place all registers into a known state Tx FIFO Reset Board Control Register D1 Setting this bit will clear the Tx FIFOs and program the current Almost Flag Values Rx FIFO Reset Board Control Register D2 Setting this bit will clear the Rx FIFOs and program the current Almost Flag Values FIFOs The FIFOs on the PCI PMC HPDI32A are used for buffering the transmit or receive data This allows the data on cable interface to run independent of the PCI interface ensuring data will be transferred on the cable regardless of software overhead to the board assuming the average receive throughput can be maintained The board allows for differe
18. may be disabled via the Board Control Register and used as discrete IO GPIOO Command 2 Status Valid Programmable signal to allow for status words at the start of frame If Status Valid counters are used during transmit the signal will be asserted for Status Valid Count at the beginning of every frame and negated for the remainder of the frame Status Valid may be disabled via the Board Control Register and used as discrete IO GPIOI Command 3 Rx Ready Provides a method for the receiving device to pause the data transfer The receiving device drives this signal This function is enabled by Board Control Bit D9 When the HPDI32A is in receive mode this signal is negated when the Rx FIFO Almost Full flag is reached Rx Ready may be disabled via the Board Control Register and used as discrete IO GPIO2 Command 4 Tx Data Ready Provides a signal to indicate data is present in the Tx FIFO The transmitting device drives this signal Tx Data Ready may be disabled via the Board control register and used as discrete IO GPIO3 Command 5 Tx Enabled Provides a signal to indicate the HPDI32A is in transmit mode Board Control Bit D4 If enabled the HPDI32A card always drives this signal Tx Enabled may be disabled via the Board Control Register and used as discrete IO GPIO4 Command 6 Rx Enabled Provides a signal to indicate the HPDI32A is in receive mode Board Control Bit D5 If enabled the HPDI32A card always drives this si
19. reset at the start of the next frame If Cable Command D2 is set as Discrete IO instead of Status Valid this register will count the total number received words since Receive Enabled This register will reset when receive is disabled D31 0 Rx Status Length Counter RX LINE LENGTH COUNTER Offset 0x0000002C This register contains the number of Line Words clocks where the Line Valid signal was asserted during the last received frame This register is unused if Cable Command D1 is set as discrete IO instead of Line Valid D31 0 Rx Line Length Counter INTERRUPT CONTROL REGISTER Offset 0x00000030 The Interrupt Control Register enables the Local Interrupt Sources to generate a Local Interrupt request See Section 3 3 for more detailed explanation of Interrupts DO IRQ Source 0 Enable Frame Valid default rising edge Frame Start D1 IRQ Source 1 Enable Frame Valid default falling edge Frame End D2 IRQ Source 2 Enable Cable Command D1 default rising edge D3 IRQ Source 3 Enable Cable Command D2 default rising edge D4 IRQ Source 4 Enable Cable Command D3 default rising edge D5 IRQ Source 5 Enable Cable Command D4 default rising edge D6 IRQ Source 6 Enable Cable Command D5 default rising edge D7 IRQ Source 7 Enable Cable Command D6 default rising edge D8 IRQ Source 8 Enable Tx FIFO Empty default rising edge Tx FIFO Empty D9 IRQ Source 9 Enable Tx FIFO Almost Empty default rising edge Tx
20. 0 Interrupt Line Routing Value Indicates which input of the system interrupt controller s to which the interrupt line of the device is connected 4 114 PCI INTERRUPT PIN REGISTER Offset Ox3D Reset 0x01 D7 0 Interrupt Pin register Indicates which interrupt pin the device uses O1 INTA Note PCI 9080 supports only one PCI interrupt pin INTA 4 115 PCI MIN GNT REGISTER Offset Ox3E Reset 0x00 D7 0 Minimum Grant Specifies the minimum burst period the device needs assuming a clock rate of 33 MHz Value is in 250 nsec increments A 0 indicates no stringent requirement 4 1 16 PCI MAX LAT REGISTER Offset Ox3F Reset 0 00 D7 0 Maximum Latency Specifies the maximum burst period the device needs assuming a clock rate of 33 MHz Value is in 250 nsec increments A 0 indicates no stringent requirement 4 2 LOCAL CONFIGURATION REGISTERS The Local Configuration registers give information on the Local side implementation Since Local Expansion ROM Local Address Space 1 and Direct Master accesses are not implemented on the PCI PMC HPDI22A the descriptions of these registers have been omitted Most of the Local Configuration Registers are preloaded from the configuration Serial EEPROM at system reset Table 4 2 Local Configuration Registers Offset PCI Local Register Name Value after Addr Addr Writable Reset 0 00 0x80 Y 00 0x04 0x84 Y Local Base Address Remap for PCI to Local Address
21. 0 detected a data parity error when performing a master read Writing a 1 to this bit clears the bit PCI REVISION ID REGISTER Offset 0x08 D7 0 Revision ID The silicon revision of the PCI9080 PCI CLASS CODE REGISTER Offset 0x09 0B Reset 0x068000 D7 0 Register level programming interface 0x00 Queue Ports at 0x40 and 0x44 0x01 Queue Ports at 0x40 and 0x44 Int Status and Int Mask at 0x30 and 0x34 D15 8 Sub class Code 0x80 Other bridge device D23 16 Base Class Code 0x06 Bridge Device PCI CACHE LINE SIZE REGISTER Offset OxOC Reset 0x00 D7 0 System cache line size in units of 32 bit words PCI LATENCY TIMER REGISTER Offset OxOD Reset 0x00 D7 0 PCI Latency Timer Units of PCI bus clocks the amount of time the PCI9080 as a bus master can burst data on the PCI bus PCI HEADER TYPE REGISTER Offset OxOE Reset 0x00 D6 0 Configuration Layout Type 0 D7 Header Type 0 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL RUNTIME DMA REGISTERS Offset 0x010 Reset 0x00000000 0 Memory Space Indicator A 0 indicates register maps into Memory space Note Hardcoded to 0 D2 1 Location of Register 00 Locate anywhere in 32 bit memory address space Note Hardcoded to 0 D3 Prefetchable Note Hardcoded to 0 D7 4 Memory Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 Memory Base Address Memory base address for access to Local Runtime and DMA regis
22. 000000000 sete teas se 26 4 3 2 SERIAL EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER 27 4 3 3 PCI PERMANENT CONFIGURATION ID 1 0 00202000000 00100000000000000000000000 27 434 PCI PERMANENT REVISION ID REGISTER cssssccccccecsesesnscecececsensuececececeeseeaececececsesaaeceeececsesnaaeeeeecs 27 4 4 LOCAL DMA REGISTERS ecrit ce dd 28 Table 4 4 DMA Registers 0 e e ae a ae r a r a aee ae eine aes ree eraren ae ea eiae ea etea 28 4 4 1 DMA CHANNEL 0 MODE REGISTER cc s cccccecesssssscecececsensuececececseseaesecececeesesaaeseccceesesssaeeeeeeecsensaaeaeeecs 28 442 DMA CHANNEL 0 PCI ADDRESS REGISTER 29 4 4 3 DMA CHANNEL 0 LOCAL ADDRESS REGISTER ccccccssesessscecececeessnsececececeeseseaesececeesensaaeeeeeceesessaaeeeeees 29 444 DMA CHANNEL 0 TRANSFER SIZE BYTES 8 0 0 1 4 441 29 4 4 5 DMA CHANNEL 0 DESCRIPTOR POINTER REGISTER cssssssccececeesessececececeesenseaeseeececsessaaeeeeeesesensaaeeeeecs 29 4 46 DMA CHANNEL 0 COMMAND STATUS REGISTER ccscsssccccceceessssscecececeesesssaececececsesnsaeeeeceeceessaeeeeecs 29 4 4 7 DMA ARBITRATION REGISTER csssessececececeessuececececeensaececececeessaseaecececeesesuaaesececeesesaaeceeeeecsessaaeeeeecs 30 4 4 8 DMA THRESHOLD REGISTE
23. ACE CABLE General Standards Corporation can provide an interface cable for the HPDI32A board This cable is twisted pair for increased noise immunity Several standard cable lengths are offered or the cable length can be custom ordered to the user s needs Versions of the cable are available with connectors on both ends or the cable may be ordered with a single connector to allow the user to adapt the other end for a specific application Please consult factory for more information on cabling options and pricing 6 1 CUSTOM APPLICATIONS Although the HPDI32A board provides extensive flexibility to accommodate most user applications custom interfaces exist which may not exactly conform to the HPDI32A interface standard General Standards Corporation has worked with many customers to provide customized versions based on the HPDI32A board Please consult our sales department with your specifications to inquire about a custom application 33
24. APTER 3 LOCAL SPACE REGISTERS 3 0 LOCAL REGISTERS The Local Space registers control the transmission and reception of data to and from the board Table 2 13 1 Local Register Map Offset Value Address Size Access Register Name after Reset Ox00 D32 Firmware Revision Oxi4 D32 RO Features OxO00000F Rx Tx FIFOs 0928 D32 RO Rx Status Counter 7 Ox00000000 OQC D3 RO JjRxLineCoumter Ox00000000 OGC jJReevd 040 D3 RO Tx FIFOSize OxO00XXXO0 Ox4g D3 RO _ RxFIFO Size Ox000XXXO0 Oxi8 D3 RO TxFIFOWords Ox00000000 Ox4C D32 RO RxFIFOWords Ox00000000 RO read only RW read write capability RC read clear a write clears the specified bits 3 1 FIRMWARE REVISION REGISTER Offset 0x00000000 This Register is used to determine the version of firmware that is programmed into the board If the board logic is changed the value in this register is changed D7 0 D15 8 D23 16 D30 24 D31 Firmware Revision Incremented when firmware changes PCB Revision This field details the PCB version for this firmware version Sub ID This field reflects special variations of the HPDI32A board Reserved Features Register present A indicates Features Register is implemented in specific firmware version 10 3 2 BOARD CONTROL REGISTER Offset 0x00000004 The Board Control Register is used to contr
25. CLINTEREACE REGISTERS eornm ea edam n o RED RH 19 4 1 PCI CONFIGURATION REGISTERS 19 Table 4 1 PCIE Configuration Registers e hedera eed cere ene eun 19 4 1 1 PCI CONFIGURATION ID 1 2 2 2 2 2 000000000000000000000000000000000000 19 4122 PCECOMMAND REGISTER eere erento rete hie Pee oer ire Re peus 20 41 3 PCISTATUS REGISTER aisar rere eee vete ee ee EE HET SEV RR EAE Ve YE CEDE REPE CREER ORE ERR Y 20 41 4 PEVREVISION ID REGISTER eee es ee re et eo rete en ev ees 21 4 1 5 PCICEASSCODEREGISTER uerit erepto Ec reo iri bebe 21 4 1 6 PCI CACHE LINE SIZE REGISTER sssccssccscsssssscescccscecssnseucececessenseaeeesceeceensnauaesececesnennceescescesssnneessecscs 21 4 1 7 M PCILATENCY TIMER REGISTER cccsesscccececeessaececececsesssececececseseasececececeeseasaaeseeeceesensaaeceeeeecsesnaaeeeeecs 21 4 1 8 PCI HEADER TYPE REGISTER ccccessessccecececeessaececececsensaaececececeessnaeaesececseseasaaesecececseeaaeceeceseseneaaeeeeecs 21 4 1 9 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL RUNTIME DMA REGISTERS 21 4 1 10 PCI BASE ADDRESS REGISTER FOR I O ACCESS TO LOCAL RUNTIME DMA 8 8 22 4 1 11 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRE
26. Jumper 4 toward the bottom PCI Only Two general purpose jumpers are used on the PCI version only These jumpers are present on the PMC version but are not connected They may be connected on a future PMC version These jumpers may be read from the Board Status register installed 1 removed 0 If more than one HPDI32A board is installed in a system Board Jumpers 0 1 can provide an addressing method to distinguish between the cards via software Board Jumper 1 Jumper closest to top of card Board Jumper 0 Jumper 2 second from top of card PCI PMC FPGA Reload Jumper 3 third from top of card PLX Default Configuration Jumper 4 closest to bottom of card These jumpers should remain installed ALWAYS Removing either of these this jumpers will cause the board to not function correctly Therefore these jumpers should only be removed following factory consultation 5 1 CABLE INTERFACE CONNECTOR The 80 pin cable interface connector reference designator P1 on the HPDI32A board is manufactured by Robinson Nugent part number PSOE 080 P1 SR1 TG The mating part number is Robinson Nugent 5 080 5 TG 50 mil cabling is suggested for twisted pair or Robinson Nugent P25E 080S TG 25 mil cabling may be used for multi drop capability but with loss of twisted pair Table 5 0 shows the cable pinout
27. NTERRUMPTS 6 2 4 EN RE 6 ER E REPRE EE e UEM ERE DEM REED ERE 6 242 SINONSDEMAND DMA terri aeter t e i te bc E Ve Br e E de verde 6 24 32 DEMAND MODE re oreet eve dee YR ERR 7 2 4 4 DMA DATA PACKING itecto eese tere tp 7 2 9 CABLE INTERFACE 55 000000 444 nnne eaten asse eset eate nasse 7 FIGURE 2 17 CABLE INTERFACE TIMING eere et itr ente eee ee ee ee ee tre ee oer Re dead 8 2 6 GBNBRALPURPONSE I C ette erret eee b ee rei ee oe UE Ee c PEE PCR EUR 9 2 7 LOOPBACK TES PING nte ae cte t o a OPER EA os B D EE REST ate do 9 CHAPTER 3 LOCAL SPACE REGISTERS scssssisssessossnccsssnssonssessccosnssessasensecssscsnssovstsssbassecsesesesensessensosecsesensoutees 10 3 1 FIRMWARE REVISION REGISTER OFFSET 0 00000000 10 3 2 BOARD CONTROL REGISTER OFFSET 0 00000004 11 3 3 BOARD STATUS REGISTER OFFSET 0 00000008 0 13 3 4 ALMOST FLAG REGISTER OFFSET 14 3 5 Rx ALMOST FLAG REGISTER OFFSET 0 00000010 14 3 6 FEATURES REGISTER OFFSET 0x00000014 esses eene enne enn nennen nennen enne 15 3 7 TX FIFO RX FIFO OFFSET 0x00000018 2
28. PCI HPDI32A PCI HPDI32A PECL PMC HPDI32A PMC HPDI32A PECL 32 Bit High Speed Parallel Digital Interface User Manual General Standards Corporation 8302 Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail support generalstandards com PREFACE General Standards Corporation Copyright C 2006 General Standards Corporation Additional copies of this manual or other literature may be obtained from General Standards Corporation 8302A Whitesburg Dr Huntsville Alabama 35802 Tele 256 880 8787 FAX 256 880 8788 E mail support generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corporation assumes no respon
29. R 20 2 2 0000000000000000000000000000000000 30 4 5 MESSAGING QUEUE REGISTERS r E N EE N N E eren tete i 30 CHAPTER 5 HARDWARE CONFIGURATION eessesssescceesecesccssccsscesoccsoescossocesccesesssessocesocecoesccesccesecsseessessssesse 31 5 0 HARDWARE JUMPERS OG Drm nea etr a oar BORE are 31 5 1 CABEE INTERFACE CONNECT OR aod eire tane taedet N 32 Table 5 0 AO E ete RE TE EN REO A OO E 32 CHAPTER 6 ORDERING 33 6 0 ORDERINGINEORMUUTION 5 5 ettet redet c ERR TH E sack crc e cs BE 33 60 2 BUS INTERFACE troie treni tune e e a DEG eris 33 6 0 2 3BIBEOSIZE 655 E ect m 33 6 1 CUSTOM APBEIGCATIONS rette GRO DUO 33 CHAPTER 1 INTRODUCTION 1 0 FUNCTIONAL DESCRIPTION The PCI PMC HPDI32A Board is a high speed 32 bit parallel digital interface card capable of transmitting or receiving data at up to 80 Mbytes per second over a RS 485 or PECL interface On board transmit and receive FIFOs of up to 128k words deep buffer transfer data between the PCI PMC bus and the cable interface This allows the HPDI32A to maintain maximum bursts on the cable interface at least up to the depth of the FIFOs independent of the PCI bus interface The on board FIFOs can also used to buffer data between the cable interface and the PCI bus to maintain a sustained data throughput for real time applications The HPDI32A
30. Reserved Expansion ROM Space Local Bus Width Unused Expansion ROM Space Internal Wait States Unused Expansion ROM Space Ready Input Enable Unused Expansion ROM Space Bterm Input Enable Unused Memory Space 0 Burst Enable Extra Long Load from Serial Enable Expansion ROM Space Burst Enable Unused Direct Slave PCI Write Mode PCI Target Retry Delay Clocks 4 3 RUNTIME REGISTERS The Runtime registers consist of mailbox registers doorbell registers and a general purpose control register The mailbox and doorbell registers serve no purpose on the PCI PMC HPDI32A Table 4 3 Runtime Registers CFG Offset PCI Local Register Name Value after Addr Addr Writable Reset 0 40 OxCO 0x44 0 4 0x48 0 8 Ox4C OxCC 0x50 OxDO 0x54 OxD4 0x58 0xD8 0 5 OxDC 0x60 OxEO 0 64 OxE4 0x68 OxES 0 6 OxEC 0x70 OxFO 0 74 OxF4 0 78 0 0 Ox7C 0 4 4 3 1 INTERRUPT CONTROL STATUS PCI 0x68 Reset 0 00000000 DO Enable Local bus LSERR Unused D1 Enable Local bus LSERR on a PCI parity error Unused D2 Generate PCI Bus SERR D3 Mailbox Interrupt Enable Unused D7 4 Reserved D8 PCI Interrupt Enable D9 PCI Doorbell Interrupt Enable Unused D10 PCI Abort Interrupt Enable D11 PCI Local Interrupt Enable Local Interrupt must be enabled for USC FIFO interrupts D12 Retry Abort Enable Unused D13 PCI Doorbell Interrupt Status D14 PCI Abort Interrupt Status D15 PCI Local Interrupt
31. SS SPACE 0 22 4 1 12 PCI SUBSYSTEM DEVICE VENDOR ID REGISTER 22 4 1 13 PCL INTERRUPT LINE REGISTER Pe ERE EHE e e are eos 22 4 1 14 23 4 1 15 PEIMN GNT REGISTER ea 23 4 1 16 PGI MAX LAT REGISTER irrita e ete esce cet Eee eee peo HER Ven 23 4 2 LOCAL CONFIGURATION 24 Table 4 2 Local Configuration Registers cccescsssssssesesseeseesceececseesecseeseeacsecseesessesaeeseeacsesseesecsesseeseeaeeeeseesesateaeeaseaes 24 4 1 1 LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL 5 2 400 0 0000000000 24 4 2 2 MODE ARBITRATION REGISTER cccsesscecececsessaececececeessuececececseneaaeeecececeesesseaeceeeceesesaaeceeeeecseseaaeeeeecs 24 4 2 3 BIG LITTLE ENDIAN DESCRIPTOR REGISTER sc scccccceceesessececececsessssscecececeeseucaeceeeceeseaaeeeeececeessaaeaeeecs 25 424 LOCAL ADDRESS SPACE 0 EXPANSION ROM BUS REGION DESCRIPTOR REGISTER 25 4 3 RUNTIMEREGISTERS e rre tec eere eae rte Eee a E ede rs eee EUER 26 Table 4 3 Runtime Registers eese nenne eenetetnetretnetnetr 26 4 31 INTERRUPT CONTROL 5 5 22 22 22222 0000000000000000
32. Space 0 0x00000000 Unused 0 08 0x88 0x00000000 Ox0C 0 8 0x00000000 0x10 0x90 0x00000000 ROM BREQo control Unused 0x18 0x98 0 00000000 Ox9C 0x00000000 0 20 OxAO 0x00000000 0x24 4 Local Base Address for Direct Master to PCI Memory IO CFG 0 00000000 0 28 OxAS Y 0 00000000 2 OxAC Y PCI Configuration Address Register for Direct Master to PCI 0x00000000 IO CFG Unused OxFO 0x170 Y 0x00000000 OxF4 0 174 Y Local Base Address Remap for PCI to Local Address Space 1 0 00000000 OxF8 0 178 Y Local Bus Region Descriptor Space 1 for PCI to Local 0x00000000 Accesses Unused 4 1 1 LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL BUS PCI 0x00 Reset OXFFFFF000 0 Memory Space Indicator A 0 indicates register maps into Memory space D2 1 Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space D3 Prefetchable A 0 indicates reads are not prefetchable D31 4 Specifies which PCI address bits will be used to decode a PCI access to Local Address Space 0 A 1 indicates bit is included in address decode Local Address Space 0 value OXFFFFF000 maps a 4kbyte range Since entire Local Address Space be mapped into 4kb range the remap register is not used 4 2 2 MODE ARBITRATION REGISTER PCI 0x08 24 4 2 3 4 2 4 D7 0 D8 15 D16 D17 D18 D20 19 D21 D22 D23 D24 D25 D26 D27 D28
33. Status D16 Local Interrupt Output Enable D17 Local Doorbell Interrupt Enable Unused D18 Local DMA Channel 0 Interrupt Enable D19 Local DMA Channel 1 Interrupt Enable D20 Local Doorbell Interrupt Status D21 DMA Channel 0 Interrupt Status D22 DMA Channel 1 Interrupt Status D23 BIST Interrupt Status 26 4 3 2 D24 D25 D26 D27 D31 28 A 0 indicates a Direct Master was bus master during a Master or Target abort A 0 indicates that DMA CHO was bus master during a Master or Target abort A 0 indicates that DMA CHI was bus master during a Master or Target abort A 0 indicates that a Target Abort was generated by the PCI9080 after 256 consecutive Master retries to a Target PCI Mailbox 3 0 Write Status SERIAL EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER PCI 0x6C Reset 0x0x001767E D3 0 D7 4 D11 8 D15 12 D16 D17 D23 18 D24 D25 D26 D27 D28 D29 D30 D31 PCI Read Command Code for DMA PCI Write Command Code for DMA PCI Memory Read Command Code for Direct Master Unused PCI Memory Write Command Code for Direct Master Unused General Purpose Output Unused General Purpose Input Unused Reserved Serial EEPROM clock for Local or PCI bus reads or writes to Serial EEPROM Serial EEPROM chip select Write bit to serial EEPROM Read serial EEPROM data bit Serial EEPROM present Reload Configuration Registers PCI Adapter Software Reset Local Init Status A l
34. Unused D6 Ready Input Enable Note This bit should always be set to 1 Ready Input Enabled D7 Bterm Input Enable Unused Note This bit should always be set to 0 BTERM Disabled D8 Local Burst Enable Note If Burst enabled the user must ensure FIFO will not become empty read or full write during the burst access For Demand Mode DMA this means the Almost Empty Almost Full flags should be set to a value of at least 8 D9 Chaining Enable A I indicates chaining mode is enabled For chaining mode the DMA source address destination address and byte count are loaded from memory in PCI Space D10 Done Interrupt Enable A 1 enables interrupt when DMA done Note If DMA clear count mode is enabled the interrupt won t occur until the byte count is cleared D11 Local Addressing Mode 28 4 4 2 4 4 3 4 4 4 4 4 5 4 4 6 A I indicates local addresses LA 31 2 to be held constant Note This bit should always be set to 1 no address increment D12 Demand Mode Enable A 1 causes the DMA controller to operate in Demand Mode In Demand Mode the DMA controller transfers data when its DREQ input is asserted The DMA controller transfers Lwords 32bits of data This may result in multiple transfers for an 8 or 16 bit bus D13 Write and Invalidate Mode for DMA Transfers When set to 1 PCI 9080 performs Write and Invalidate cycles to the PCI bus PCI 9080 supports Write and Invalidate s
35. and possibly data storage overhead such as hard disk drive accesses Since sustained PCI data rates will be typically slower than the maximum cable interface rate DMA on the PCI bus is supported to make the PCI data transfers as fast as possible There are 3 methods the software application can move data to and from the HPDI32A board PIO mode Non Demand DMA and Demand Mode DMA The two DMA modes are only supported to the on board data FIFOs DMA accesses to local registers are not supported 2 4 MODE 2 4 2 In PIO mode the user accesses the FIFOs through is single register reads and writes to the board This is the slowest data transfer mode In PIO mode the user must check to make sure the Tx FIFO is not full prior to writing the Tx FIFOs and check to ensure the Rx FIFO contains data before reading The device driver should normally handle checking of this status prior to reading writing the FIFO See specific driver information for further details NON DEMAND DMA Non Demand DMA mode the user specifies a DMA transfer size and initiates the transfer Since there is no checking for data validity no check to determine if Tx FIFO Full or Rx FIFO empty the user must ensure the FIFOs can handle the entire transfer prior to transfer initiation If the Tx FIFO becomes full or Rx FIFO Empty during a Non Demand mode DMA transfer the extra data will be discarded and no error indication is received the DMA appears to have comple
36. bit transfers This is useful if only a 16 bit or 8 bit cable interface is used In such cases each data word uses the full 32 bit FIFO width data is not packed in FIFO but is packed for the PCI bus transfer This will increase the effective PCI data throughput 2 5 CABLE INTERFACE SIGNALS Data is transferred to and from the HPDI32A board via an 80 pin cable interface consisting of 40 differential signals 1 Clock 7 Command Control signals and 32 Data bits The seven Command Control signals provide many cable protocol options The default Cable Command signals are Command 0 Frame Valid Provides an indication that data is currently being transferred on the cable This signal is driven by the transmitter and must be asserted before data is recorded Frame Valid may be disabled via the Board Control Register and used as discrete IO although this is only useful for test purposes Command 1 Line Valid Programmable signal to allow for multiple lines or rows within a frame If Line Valid and Line Invalid counters are used during transmit the signal will be and negated for Line Invalid Count and asserted for Line Valid Count alternating for the entire frame The Line Invalid Count begins after the Status Valid Count Board Control Register Bit 6 controls the Line Valid state during the Status Word Count If Line Valid is enabled but the Line Valid counter is zero default Line Valid will be asserted for the entire Frame Line Valid
37. ch respective bit will set the interrupt source to active Hi 0 will set the interrupt source to active Lo D15 0 IRQ 15 0 Active Hi Enable D31 16 Reserved 18 4 4 0 PCI INTERFACE REGISTERS A PCI9080 I O Accelerator from PLX Technology handles the PCI Interface The PCI interface is compliant with the 5V 33MHz PCI Specification 2 1 The PCI9080 provides dual DMA controllers for fast data transfers to and from the on board FIFOs Fast DMA burst accesses provide for a maximum burst throughput of 132MB s to the PCI interface To reduce CPU overhead during DMA transfers the controller also implements Chained Scatter Gather DMA as well as Demand Mode DMA Since many features of the PCI9080 are not utilized in this design it is beyond the scope of this document to duplicate the PCI9080 User s Manual Only those features which will clarify areas specific to the PCI PMC HPDI32A are detailed here Please refer to the PCI9080 User s Manual See Related Publications for more detailed information Note that the BIOS configuration and software driver will handle most of the PCI9080 interface Unless the user is writing a device driver the details of the PCI interface Chapter 2 may be skipped 4 1 PCI CONFIGURATION REGISTERS The PCI device configuration for the PCI PMC HPDI32A is fully PCI 2 1 compliant Table 4 1 contains a list of the PCI configuration registers present in the PCI9080
38. de Value D31 16 Reserved TRANSMIT FIFO SIZE Offset 0x00000040 This register contains the Transmit FIFO depth This is the true FIFO depth regardless of the FIFO data width This value is calculated once on power up D19 0 Tx FIFO Depth D31 0 Reserved RECEIVE FIFO SIZE Offset 0x00000044 This register contains the Receive FIFO depth This is the true FIFO depth regardless of the FIFO data width This value is calculated once on power up D19 0 Rx FIFO Depth D31 0 Reserved 3 18 3 19 3 20 3 21 TRANSMIT FIFO WORDS Offset 0x00000048 This register will track the current number of words in the Transmit FIFO D19 0 Current Number of Words in Tx FIFO D31 20 Reserved RECEIVE FIFO WORDS Offset 0x0000004C This register will track the current number of words in the Receive FIFO D19 0 Current Number of Words in Rx FIFO D31 0 Reserved INTERRUPT EDGE LEVEL REGISTER Offset 0x00000050 This register along with the Interrupt Hi Lo Register defines the interrupt source as Level Hi Level Lo Rising Edge or Falling Edge triggered 1 in each respective bit will set the interrupt source to edge triggered a 40 will set the interrupt source to level triggered D15 0 IRQ 15 0 Edge Trigger Enable D31 16 Reserved INTERRUPT HI LO REGISTER Offset 0x00000054 This register along with the Interrupt Edge Level Register defines the interrupt source as Level Hi Level Lo Rising Edge or Falling Edge triggered A 17 in ea
39. errupts are latched edge triggered interrupts are more user friendly The interrupts default at reset to the most common configuration but this configuration may not suit all users For example one may wish to interrupt when the Tx FIFO is almost full to stop writing data to the FIFO while another may wish to interrupt when it is not almost full to know when to resume writing to the FIFO The HPDI32A provides the user the flexibility of interrupt configuration Interrupts are latched in the Interrupt Status Register ISR Since all interrupts are multiplexed onto a single interrupt request the ISR provides the means of determining the unique interrupt source The user should clear the interrupt by writing the specific bit back to the ISR as part of the interrupt service routine From the previous example when the interrupt has occurred bit 13 of the ISR is now a 1 indicating that a FIFO Almost Empty interrupt has occurred This bit will remain a 1 and will not allow any additional interrupts to be generated until the user clears the interrupt To re enable the FIFO Almost Empty interrupt the user must clear the interrupt by writing a 1 to bit 13 of the Interrupt Status Register DMA Although the 33MHz PMC PCI bus is capable of burst transfers up to 132Mbytes per sec actual sustained throughput on the PCI bus will be much lower This is due to many factors such as bus overhead operating system overhead application overhead
40. gnal Rx Enabled may be disabled via the Board Control Register and used as discrete IO GPIOS Data is transferred using the Cable Clock transmit data and command control signals are clocked on the rising edge of the TxCLK The transmit clock on the HPDI32A is supplied by an on board oscillator This oscillator is socketed so the user can customize the clock interface speed The board is shipped with a 20MHz oscillator standard To ensure maximum setup and hold times all receive data and Command Control signals are clocked on the falling edge of the RxClk Figure 2 1 shows the data setup and hold times Clock Hi Time Clock Low Time 19ns Min 19ns Min pi gt Cable fmax 20MHz Transmit Clock Receive Clock Cable Input Hold to to b from Cable Output Cable Input Setup Receive Clock ns Mi 2ns Min 16ns Max Cable l O X X X 3ns Min 20ns Min FIGURE 2 1 CABLE INTERFACE TIMING 2 6 GENERAL PURPOSE I O Since most users will not require all of the default Cable Command functions six of the cable command signals can be changed from their default function and used as discrete IO This allows users to control cable outputs read cable inputs or receive cable interrupts via simple software control The General Purpose IO bits are controlled from the Board Control register If a bit is set as a discrete output the Board Control register also defines the output value If
41. interface is a half duplex interface board is either transmitting or receiving data not simultaneous The HPDI32A is easily set up to transfer data by initializing few local registers Once the data link is established the data is transferred to from the user application by simply reading or writing the on board FIFOs The board has an advanced PCI interface engine which provides for increased data throughput via DMA The cable interface provides a flexible interface suited to most high speed parallel applications All data to from the board is synchronous with the transmit clock supplied by the transmitter A Frame Valid signal indicates data is present on the interface and programmable Line Valid and Status Valid signals provide additional interface capability The interface also provides for data throttling by the receiving device the receiver can holdoff data the transmitting device until ready to receive The HPDI32A interface is further programmable to allow the user to disable most of these standard interface functions and use the interface signals as discrete IO including external interrupts C a Board Control a b Board Status b Tx FIFO e e lt gt BDX gt Interrupt n PCI 9080 P n RS485 t e or e r PECL f Rx FIFO Xcvrs f a FIFO Control a Cable Commands Figure 1 0 HPDI32A Bl
42. izes of 8 or 16 Lwords The size is specified in the PCI Cache Line Size Register If a size other than 8 or 16 is specified PCI 9080 performs write transfers rather than Write and Invalidate transfers Transfers must start and end at the Cache Line Boundaries D14 DMA EOT End of Transfer Enable Unused D15 DMA Stop Data Transfer Mode A 0 sends a BLAST to terminate DMA transfer Note This bit should always be set to 0 D16 DMA Clear Count Mode Unused D17 DMA Channel 0 Interrupt Select A 1 routes the DMA Channel 0 interrupt to the PCI interrupt Note This bit should always be set to 1 D31 18 Reserved DMA CHANNEL 0 PCI ADDRESS REGISTER PCI 0x84 D31 0 PCI Address Register DMA CHANNEL 0 LOCAL ADDRESS REGISTER PCI 0x88 D31 0 Local Address Register Note Should be set to Local FIFO offset 0x18 DMA CHANNEL 0 TRANSFER SIZE BYTES REGISTER PCI 0x8C D22 0 DMA Transfer Size D31 23 Reserved DMA CHANNEL 0 DESCRIPTOR POINTER REGISTER PCI 0x90 0 Descriptor Location A I indicates PCI address space Note This bit should always be set to 1 if Chained DMA enabled D1 End of Chain D2 Interrupt after Terminal Count D3 Direction of transfer A I indicates transfers from local bus to PCI bus Read Receive FIFO A 0 indicates transfers from local bus to PCI bus Write Transmit FIFO D31 4 Next Descriptor Address DMA CHANNEL 0 COMMAND STATUS REGISTER 29 8 0
43. nt FIFO depths to be installed from 8k to 128k 32k standard This allows the user to customize the board for specific real time applications The FIFO depth must be specified when ordering consult factory for further information There are two sets of FIFOs on the board one for transmit and one for receive Each set has a width of 32 bits of data and provides four FIFO status flags These flags indicate Empty Full Almost Empty and Almost Full Two of these flags Almost Empty and Almost Full are user programmable These programmable flags are used for Demand Mode DMA see Section 3 3 or may be used for cable throttling pause transmitter when Rx FIFO Almost Full or to provide the user with a trigger at a specific FIFO level The Almost Flags of the FIFOs are programmed with the Almost Register values during a FIFO Reset See Resets Section 3 1 NOTE The Almost Empty Flag value represents the number of words from empty The Almost Full Flag value represents the number of words from Full 1 not the number of words from empty The board also provides FIFO Size registers for both transmit and receive FIFOs These registers may be useful if writing software especially drivers which needs to support multiple FIFO depth The board also tracks the number of words currently in each FIFO This count may be useful when accessing the FIFOs to prevent underruns or overflows 2 3 2 4 INTERRUPTS The HPDI32A contains many possible interrup
44. ock Diagram 1 1 CABLE INTERFACE The cable interface consists of 32 bits of data one clock and 7 bi directional signals All cable interface signals are either differential RS485 RS422 or differential PECL depending upon the version of the board The clock and 7 bi directional signals are used for controlling the data transfer and other pre defined functions Six of these signals may also be used for user IO or interrupt sources if the default function is not used Figure 1 1 shows the default HPDI32A interface control signals control signals and data synchronous to the cable interface clock supplied by the transmitting device The on board transmit clock 20MHz is standard may be up to 20MHz Frame Valid signal indicates valid data is being transferred Two optional programmable signals Line Valid and Status Valid can be used to further qualify the data The Status Valid signal is used to flag a programmable number of words at the start of the cycle as status words The Line Valid signal can be used to signify valid data within a frame If the Line Valid signal is used data is only recorded when the Line Valid signal is asserted standard cable interface also provides for a cable throttling signal to pause data transmission This signal is driven by the receiving device to indicate it is capable of receiving data Section 2 5 provides a more detailed cable interface description
45. ol miscellaneous functions on the HPDI32A These include Resets Enable data transmit receive and General Purpose IO DO D1 D2 D3 D4 D5 D6 D7 D8 D9 Board Reset Writing 717 to this bit will generate a pulse to reset the on board logic and the FIFOs This bit will clear automatically The Rx Tx FIFOs are also reset and reprogrammed with the default values following a board reset To allow FIFO programming to occur the user should wait about 10usec following Board Reset before the FIFOs are accessed Tx FIFO Reset Writing a 1 to this bit will generate a pulse that will reset the Tx FIFOs Following the Reset this bit will automatically clear itself The Tx FIFO Reset also programs the Tx Almost Empty and Almost Full flags with the values contained in the Tx Almost Programming register See Section 3 3 Rx FIFO Reset Writing a 1 to this bit will generate a pulse that will reset the Rx FIFOs Following the Reset this bit will automatically clear itself The Rx FIFO Reset also programs the Rx Almost Empty and Almost Full flags with the values contained in the Rx Almost Programming register See Section 3 4 Reserved Transmit Enable A 47 will enable data transmission from the Tx FIFOs to the Cable When Transmit is enabled the HPDI32A will drive Cable Data TxClk Frame Valid Line Valid if enabled Status Valid if enabled and Tx Empty if enabled Receive Enable A 1 will enable data recep
46. ory Test Only A 47 will disable driving Tx Enabled Cable Command D5 and Rx Enabled Cable Command D6 This will prevent contention if two HPDI32A boards are cabled together 3 3 BOARD STATUS REGISTER Offset 0x00000008 The Board Status Register is used to check the most current status of on board signals including the FIFO status flags and the Cable Command signals DO Cable Command DO D1 Cable Command D1 D2 Cable Command D2 D3 Cable Command D3 D4 Cable Command D4 D5 Cable Command D5 D6 Cable Command D6 D7 Start Transmit A I indicates data transmission is in currently in progress D8 Tx FIFO Empty Low A 0 indicates the Tx FIFO is empty Tx FIFO Empty Flag asserted D9 Tx FIFO Almost Empty Low 3 4 3 5 0 indicates the Tx FIFO is almost empty Tx FIFO Almost Empty Flag asserted D10 Tx FIFO Almost Full Low A 0 indicates the Tx FIFO is almost full Tx FIFO Almost Full Flag asserted D11 Tx FIFO Full Low A 0 indicates the Tx FIFO is full Tx FIFO Full Flag asserted D12 Rx FIFO Empty Low A 0 indicates the Rx FIFO is empty Rx FIFO Empty Flag asserted D13 Rx FIFO Almost Empty Low A 0 indicates the Rx FIFO is almost empty Rx FIFO Almost Empty Flag asserted D14 Rx FIFO Almost Full Low A 0 indicates the Rx FIFO is almost full Rx FIFO Almost Full Flag asserted D15 Rx FIFO Full Low A 0 indicates the Rx FIFO is full Rx FIFO Full Flag asserted D16 Board Jumper 0 PCI
47. register is sets the programmed values for the Rx FIFO Almost Empty and Almost Full Flags This value is programmed following an Rx FIFO Reset A Board Reset will reset this register to the default value 0x0010000F and then program this value 14 3 6 3 7 3 8 3 9 D15 0 Almost Empty Flag Value D31 16 Almost Full Flag Value Number of available words remaining in FIFO 1 when Flag asserted FEATURES REGISTER Offset 0x00000014 This Register indicates new features in each firmware version This allows a driver to maintain compatibility across firmware and board revisions while providing for new features to be added DO Tx Rx FIFO Size Registers Present D1 Tx Rx FIFO Words Registers Present D2 Level Edge Triggered Interrupts Supported D3 General Purpose IO on Cable Command D6 2 Supported D4 PLX DMA Channel 1 Supported D5 Tx Rx Underrun amp Overrun flags D31 6 Reserved TX FIFO RX FIFO Offset 0x00000018 This register provides access to the transmit and receive FIFOs Writing this register sets data for transmission while reading gets incoming stored data from the Rx FIFO The user must ensure that the Tx FIFO is not full when writing or data will be discarded The user must also ensure that the Rx FIFO is not empty when reading or data returned will be indeterminate D31 0 FIFO Data TX STATUS LENGTH COUNT Offset 0x0000001C This register holds the number of clocks the Status Valid signal will be asserted at
48. sibility for any consequences resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation RELATED PUBLICATIONS The following manuals and specifications provide the necessary information for in depth understanding of the specialized parts used on this board PLX PCI 9080 Data Book PLX Technology Inc 390 Potrero Avenue Sunnyvale CA 4085 408 774 3735 http www plxtech com EJA 422 A Electrical Characteristics of Balanced Voltage Digital Interface Circuits EIA order number EJA RS 422A EIA 485 Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems EIA order number EIA RS 485 EIA Standards and Publications can be purchased from GLOBAL ENGINEERING DOCUMENTS 15 Inverness Way East Englewood CO 80112 Phone 800 854 7179 http global ihs com IEEE P1386 Standard Mechanic for Common Mezzanine Card Family CMC IEEE P1386 1 Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC Sponsored by the Microprocessor amp Microcomputer Standards Committee MMSC of the
49. t sources The PLX 9080 PCI Interface chip has several interrupt sources DMA done is the most useful and the local HPDI32A firmware has 16 potential interrupt sources All local interrupts are passed through the PLX chip and will be requested on PCI INTA In order for this board to generate interrupts to the PCI bus they must be enabled in the PLX chip Bits 8 11 and 16 of the PLX Interrupt Control Status Register must be set to a 1 in order for the interrupts to occur The device driver typically handles enabling board interrupts so the average user should not be concerned with accessing the PLX registers The 16 local interrupt sources allow for interrupts on Frame Start Frame End six cable inputs and all FIFO flags All interrupt sources are can be individually enabled allowing the user to enable some interrupts and leave others disabled This is accomplished by writing 1 to the appropriate bits in the Interrupt Control Register ICR For example to enable the Rx FIFO Almost Empty Interrupt the software will need to write a 1 to bit 13 of the ICR This bit will should remain set until the need to disable this specific interrupt Each interrupt source is individually programmable as Rising Edge Falling Edge Level High or Level Low triggering All interrupts default to edge triggered to prevent a potential interrupt lockup seen with level interrupts the level interrupt may keep re interrupting indefinitely Since int
50. ted normally Therefore the user must use caution when using Non Demand DMA 2 4 3 DEMAND MODE DMA Demand Mode DMA is similar to Non Demand DMA except the local logic will request the transfer based on FIFO status After the user specifies a DMA transfer size and initiates the transfer the local logic will request the data transfer if the Tx FIFO is not Full transmit or the Rx FIFO is not empty Rx FIFO For transmit the logic will burst data into the FIFO until the Almost Full Flag is reached The logic will then switch into a single transfer mode until the FIFO is filled or transfer is complete When the Tx FIFO becomes full the logic will cease requesting data When data is transmitted out of the FIFO Tx FIFO no longer full the request will again be asserted to re fill the FIFO This will resume until the transfer completes When receive Demand DMA is initiated the DMA is requested whenever data is in the Rx FIFO On board logic will run in burst mode until the Rx FIFO reaches the Almost Empty level at which time the logic will switch into single word mode where single words will be transferred until the FIFO goes empty Once the Rx FIFO is empty the logic ceases to request data until more data is received The request is again asserted to empty the FIFO This will continue until the transfer completes Demand Mode DMA is the preferred DMA method 2 4 4 DMA DATA PACKING DMA also provides a means to pack 16 bit or 8 bit data into 32
51. ters Note PCIBARO is Memory Mapped Base Address of PCI9080 Registers 4 1 10 PCI BASE ADDRESS REGISTER FOR I O ACCESS TO LOCAL RUNTIME DMA REGISTERS Offset 0x14 Reset 0 00000001 DO Memory Space Indicator A 1 indicates the register maps into I O space Note Hardcoded to 1 D1 Reserved D7 2 I O Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 I O Base Address Base Address for I O access to Local Runtime and DMA Registers Note PCIBARI is I O Mapped Base Address of 9080 Registers 4 1 11 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 0 Offset 0x18 Reset 0x00000000 0 Memory Space Indicator A 0 indicates register maps into Memory space Specified in Local Address Space 0 Range Register LASORR D2 1 Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space Specified in Local Address Space 0 Range Register LASORR D3 Prefetchable A 0 indicates reads are not prefetchable Specified in Local Address Space 0 Range Register LASORR D31 4 Memory Base Address Memory base address for access to Local Address Space 0 4 1 12 PCI SUBSYSTEM DEVICE VENDOR ID REGISTER Offset 2 Reset 0 908010 5 D15 0 Subsystem Vendor ID 0x10B5 PLX Technology D31 16 Subsystem Device ID 0x2400 General Standards Corporation HPDI32A 4 1 13 PCI INTERRUPT LINE REGISTER Offset Ox3C Reset 0x00 D7
52. the start of each transmit frame This register is unused if Cable Command D2 is set as Discrete IO instead of Status Valid D31 0 Tx Status Length Count Value TX LINE VALID LENGTH COUNT Offset 0x00000020 This register is contains the number of clocks that the Line Valid signal will be asserted after the Tx Line Invalid Length Counter has expired in a frame The Line Valid signal will continue to alternate between the Tx Line Valid Length Counter and the Tx Line Invalid Length Counter until the end of the frame This register is unused if Cable Command D1 is set as discrete IO instead of Line Valid D31 0 Tx Line Valid Length Count Value 3 10 3 11 3 12 3 13 TX INVALID LENGTH COUNT Offset 0x00000024 This register is contains the number of clocks that the Line Valid signal will be negated at the beginning of each transmit frame following Status Valid count or after the Tx Line Valid Length count has expired in a frame The Line Valid signal will continue to pulse alternating between the Tx Line Valid Length Counter and the Tx Line Invalid Length Counter until the end of the frame This register is unused if Cable Command D1 is set as discrete IO instead of Line Valid D15 0 Tx Line Invalid Length Count Value D31 16 Reserved RX STATUS LENGTH COUNTER Offset 0x00000028 This register will count the number of Status Words clocks where the Status Valid signal was asserted received during the last frame This register will
53. tion into the Rx FIFOs from the Cable When Receive enabled the HPDI32A will drive Rx Ready if enabled Demand DMA Direction A I will set the demand mode DMA direction to transmit This bit is not used in half duplex operation but is added for future full duplex operation Line Valid Hi On Status Valid Hi A 1 will assert the Line Valid signal while Status Valid is asserted This bit is unused if Line Valid is not used or Status Valid counter is not used Start Transmit A I will start data transmission from the Tx FIFO to the cable This bit will automatically reset when the Tx FIFO is empty no data to transmit Cable Throttle Enable A 47 will allow Rx Ready input Tx Cable Command D3 to control the data transmission If enabled and transmit enabled data will be transferred from the Tx FIFO to the cable as long as Rx Ready is asserted D15 D10 Reserved For RS 485 Transceivers GPIO Control D24 D16 Cable Command DO Setup Control For D16 0 and D24 0 Function Frame Valid For D16 0 and 24 1 Function Discrete Input For D16 1 and D24 0 Function Discrete Output Lo For D16 1 and 24 1 Function Discrete Output Hi D25 D17 Cable Command D1 Setup Control For D17 0 and D25 0 Function Line Valid For D17 0 and 25 1 Function Discrete Input For D17 1 and D25 Function Discrete Output Lo For D17 1 and D25

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