FLT V4 User Manual
Contents
1. Filter I out The second trigger condition occurs when sloping curve of Filter_II crosses zero The gradient at zero point determines the most precise time point as given be clock of 20Mhz This allows a time stamp resolution of 2 25 ns The time precision bit marks the appropriate half 0 left half 1 right half ILI Filter II out Zero crossing FilterA Out FilterB Pole Zero Correction without pole zero correction 240 220 1 T bel Lo m FilterazA cut FilterE settings Format bits 27 24 of RunControlRegister settings 15 14 13 12 11 10 co gt OC attenuation 0 695 0 719 0 734 0 758 0 773 0 797 0 813 0 836 02. Energy Mode 582 overwrite 0 Histogram Mode 2 overwrite _ no Runmode 7 19 16 0 3 FLT EventFifo length ControlReg 25 0 512 1 44 FLT EventFifo behave ControlReg 24 O overwrite 1 stop when full 0 NEW Fast Events Readout for Energy Mode Event information should be sent from FLT to SLT field bit length description Trigger bit Channels E Chamel amp 5 __ TimeStampsecondslb TimeStamp subseconds 251 6 0 Energy 0 20 01002 Energy diff l12 202 Flatlngh o 02 FLT gt SLT transmission format PixLink 1OMHz clock 23 bit payload Start bit Parity one event transmission next event Pe 7 22 2120119 1817 16 15 1141312 1110 09 0810706 05 04 03 02 01 00 N mulip channel 0 0 toplengh word3 Energy 20bi seconds I2bi TS subseconds 25bit Time correction on SLT if FLT TS subseconds gt SLT subseconds TS seconds SLT seconds I else TS seconds SLT seconds FLT Block Diagram trigger chl 24 trigger ch24 gt es FLT Timer Event information stored on SLT bit length FLT TimeStamp seconds msb time correction TimeStamp seconds 156 2 time correction FIFO depth 1K pixLink ME 711
3. 7 211 sla 11 Sslotid channel 2 DS 2 A ades MA 1 20 31 0 23 31 Seat ME RR RR PCI Address Format 21212121111 111 11 1 0 00000 312109876 5 4 7 54 1312 I 1 20 31 0 2333 see SLT specification unused 7 for future DS Destination Select 00 CFPGA Registers global Registers analog settings etc 01 CFPGA Memory TestPattern HitRate SODIMM 10 Periph Registers Thresh Settings ADC SPI settings Statistics etc 11 Periph Memory QDR iRAM lower address 10 bit 00 Channel address 0 23 select channel 31 all channels Example long get_address long slot long base_addr return slot lt lt 19 base long get_address long slot long channel long base_addr return slot lt lt 19 channel lt lt 14 base_addr 18 FLT Address see FLT MemoryMap pdf 19 Clock Distribution Synchronization Schema All the clocks in subrack are synchronized with a global system clock of 20MHz to allow all the synchronous communications between several boards The SLT module receives the external 10MHz clock from a GPS unit and produces a zero phase delayed 20MHz system clock This is distributed to several FLT boards clock fanout chips and aligned clock lines on the backplane The resulting delay of 3 5 nsec is compensated by internal PLLs in the FLTs
4. GPS IPPS SecStrb Pixel Trigger PixTr extend NUR Pixel Trigger Timing 20 Abbreviations FD PMT FPGA FLT AB SLT JTAG QDR fluorescence detector photomultiplier field programmable gate array first level trigger analog board second level trigger joint test action group quad data rate 21 References SLTman ADCds PEbus ABman SLT user manual ADC datasheet Specification of PE bus Analog Board manual 22 Appendix 22 02 2012 Update increase in bandwidth Using SLT as data concentrator SLT coNects all triggers energies timestamp s in an EventFIFO gt no ADC traces Assumedw dead time of 28 2 56 clock cycles gt not working for shaping times lt 2 805 SLT 2Sbits SLT Event FIFO 24bits 1001 D Ch01 T R i R gt _ T Ch02 FLT i gt 7 _ Ch24 FLTZi _ N x FLT links T aD gt pile up d E trigger info energy 222 Readout gt trigger bit 120MB s 120 IOMEvents s 1 I2bytes in energy mode Using SLT as status concentrator SLT collects status of FLT s fill pointers FLT EventFIFO Nn Status Interrupt Register SLT sends interrupt to DAQ SW after programmable limit exceeded ISR delivers status of all FLT FIFOs e g fill pointer 01 5 fill pointer 02
5. Note that the energy value in this mode corresponds to the absolute pulse amplitude with offset Paix Trigger The pair trigger based on coincidence of two channels corresponding to two ends of a fiber The is programmable in range of 200ns 200ns However the pair assignment is fix AN 24 pixel per FLT board 1 24 build 12 pairs 1 3 5 7 9 11 1315 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 Trigger Chi 4 over Trigger 1 1 Trigger N Chi Pair Trigger Chi 1 Sum and Coincidence Triggering The veto triggering schema based on coincidence of at least N channels fiber ends with an analog sum of all six inputs The sum building occurs outside the crate analog Coincidence window and are programmed in range of 0 250ns in 50ns steps and 0 to 7 respectively Note that the involved thresholds should be adopted appropriate and the numbers of involved channels 15 fixed see below FLT group 00 02 04 06 08 10 channel 12 0 16 18 20 22 01 03 channel 05 0 09 11 13 15 17 19 channel 21 0 sum channel chan 1 trigg amp Veto M A prolong Fy of bits 6 channels 0 5 thresholds coincidence 0 5 time window N fold 0 250 ns Figure 3 Sum amp Coincidence Trigger Block Diagram Further processing of
6. clear by user clear histogramming page second counter O HistMeasTime 1 number of measurement cycles first bin last bin a flag per channel Page B i 1 mode 0 continuous 1 1 1 1 1 i stop i 1 1 mode 1 stop if not cleared 14 Rate Measurement trigger rate is measured periodically for enabled channels The measurement time is programmable in range of Teount 1 2 4 8 16 32 sec The overflow of some counters will cause an interrupt flag The hit rate measurement is disabled after reset and can be started for each channel separately by setting HitRateMeasEnable register While Veto is active all hit rate counters keep unaltered PCI start address 0x00080100 31 ___ Rover HitRate Hz Table Hit Rate Memory Data Format PCI address 0x00000048 24 16 Tom Table HitRateMeasParameters 0 15 0 gt 1 sec 2 gt 2sec 3 gt 4sec 4 gt 8sec 5 gt 165 6 gt 32sec PCI address 0x00000024 Enable Bits 1 enabled 0 disabled Table HitRateMeasEnable 15 Veto Mode Channel Trigger Building The veto triggering concept makes use of short pulse shape of signals In Veto Mode the first filter stage 15 bypassed to the second stage The filter becomes a triangle function as shown below The shaping time and threshold should be set adequately
7. N 0 if L gt 256 All parameters are in units of the time atom 50ns ADCdata X X coeff_x_ 128 gt gt 7 Filter I Trigger zero cross detector Filter Filter amp Pixel Trigger Implementation An internal FIFO is used for delay element 27 The depth of FIFO is limited to 512 so maximal delay 2 shaping time gap length is 512 This means also that settings of ShapingTime 8 256 and gap non zero would excess the maximal FIFO length To avoid the overflow when ShapingTime is set to 256 the GapLength parameter will reset automatically and an warning flag at bit2 of PStatus is set PCI address 0x00000038 Bits Bit 0 Bit 1 Bit 2 Bit 3 07 04 13 08 ShapingTime 27 24 31 16 Table RunParam Register Bits Bito Bit Bit2 er LL PCI address 0x00002080 31 20 19 Threshold channel 1 Table Threshold Format An example right shows behavior of the filter parameterized with ShapingTime 4 24 16 GapLength 5 and Threshold 19200 ADC trace The measured energy is_ the 111111111111 height of trapeze triangle if 545 130 140 150 160 170 180 190 200 210 220 230 240 251 GapLength 0 delivered by first stage of the filter P threshold The first condition is met because of energy gt threshold
8. PP err run Ce leemte le B 211 PLL1 unlocked 2 unlocked QD DLL unlocked QDR RAM don t deliver the clock QE QDR II self test error flag mode mode of operation copy of Control register bits17 16 errF error invalid filter parameters hPg actual histogram Page copy of Status register bit28 hClr cleared flag copy of Status register bit29 FID number 00 A 01 B 10 C RunControl Global Settings Run Parameters address 0x000038 reserved 15 14 00 reserved 19 16 veto overlap time 0 2320 fol 000000000 31 20 reserved HistgrSettings Histogram Parameters address 0x00003C 19 00 E Min 23 20 expected offset of ADC data preserved S 30 28 reserved bit 28 Mode of histogram bit 29 CM Clear mode Energy energy value of last trigger indiv channel PCI address 0x002040 31 20 19 0 histFirstLast histogram first and last bins indiv channel PCI address 0x002044 31 16 15 LastEntry Threshold Pixel Trigger Threshold indiv channel PCI address 0x002080 31 20 19 16 17 0 Previous 12 lower bits 00 Actual Threshold ADCsettings ADC settings status info ADCsettings 0x000400 ADCsettingsB 0x010400 ADCsettingsC 0x050400 N ADC byte 17 In Crate Communication as Bus Address Format
9. on 0 off default 01 X Clock Channel DCO 1 on 0 off default Synchronously transfers data from the master shift register to the slave ADC Functions Bit 4 Child ID 6 4 identify device variants of Chip ID 011 50 MSPS 001 40 MSPS Data Channel Clock Channel FCO 1 on0 off default Bit 3 1 default off Data Channel D1 on default off Bit 2 Soft reset 1 on 0 off default Data Channel G1 on default off Data Channel C1 on default off Bit 1 LSB first 1 on0 off default chip_id Data Channel 1 default off Data Channel B1 on default off Bit 0 LSB 8 bit Chip ID Bits 7 0 AD9222 0x07 default Data Channel 1 default 0 off Data Channel A 1 default 0 off SW transfer 1 off default Internal power down mode 000 chip run default 001 full power down 010 Determines various generic modes of chip operation Turns the internal duty cycle stabilizer on and off When set the test data is placed on the output pins in place of normal data standby 011 reset clock Duty cycle stabilizer 1 on default 0 off User test mode 00 off default test_io Deserializer wid Be m m poa 1 01 single alternate 10 single on
10. filled out with start and parity bits to the central card SLT every 100 ns The start of transmission is synchronized to the internal 10MHz 1100 S Trigger 21 00 Table Pixel Trigger Link Data Fomat 5 Start Bit 517 P Parity Bit odd Several pixel triggers can be tied to a fixed value or replaced by different test pattern before sending to SLT This may be useful to mark the damaged pixels and for tests Both PixelSettings1 amp 2 registers define the state of the outgoing pixel triggers PCladdress 31 22 0x000030 LSBits 21 0 0x000034 _ XEM MSBits 21 0 Table PixelSettings1 2 Registers The state of a pixel trigger is defined as Pixel Trigger Output normal state 01 test pattern taken from TestPatternMem I 0 alwayso 11 Trigger Data Storage internal DP RAM For each trigger event following data should be stored for readout e energy interpretation of event e precise time stamp of occurrence 100 us deep corresponding ADC trace mode only else histogram The paging schema is used to handle the bursts of triggers The page lengths are 512 64 per board and 64 per channel All incoming pixel trigger are OR ed together to an overall trigger event whose occurrence causes an increment of the write pointer and storage the appropriate data into the EventFIFO consists of EventTable and PageTable see below EventFIFO is organized as FIFO depth
11. loops A write of 0x02 data bit25 1 to any gain address causes a reset of the read pointer TP_switch TP_MEM_OUT AND TestPulseEnable 0 when TestPulseEnable 0 The amplitude and shape of the pulse are given by the SLT module The output of test pattern is delayed with respect to begin of the TPulse strobe by 100ns The TP MEM can be used as well as direct test pattern for the pixel trigger if registers PixelTriggerMode PixelSettings1 PixelSettings2 are set accordingly see Pixel Trigger Unit In this case each 24bit pixel trigger word is replaced by 24 output bits of TP MEM TestPatMem Test Pattern Memory 128x32 PCI address z 0x001100 31 26 O Test pattern first MN 0 rst_ ___ 0 rep Pe Ox7F O Test pattern 128 Table Format 9 Filter Unit Two cascaded FIR shaping filters are used in the actual KATRIN design to provide the accurate amplitude Filter I and time my stamp Filter of a pulse A pixel trigger occurs when the extracted amplitude represents the energy of particle exceeds W_J Lii the threshold adjustable Both filter parameters shaping time L and gap length N are adjustable as shown below Frequency Response 1 stage Parameter Label Interpretation 2 ShapingTime L 28 L 24 38 416 532 6 gt 64 7 gt 128 82256 8 GapLength 0 7 Note
12. 0 fill pointer 08 99 fill pointer 12 485 fill pointer NNS 54 SW reads out corresponding FLTs 20 222 I 2MEvent s in energy mode Using SLT as readout master SLT analyzes FLT s fill pointers if necessary starts readout of FLTs immediate and finally handles DMA transfer Reduced TimeStamp format Split 32bit SecCounter in two one on SLT NEW Filter and Trigger Update KATRIN trapezoidal filter is revised regarding better separation of peak pile up effects as recommended by Sanshiro see his paper ADCdata X coeff x 128 gt gt 7 coeff_x 128 Filter I Energy Trigger Energy diff Filter amp Pixel Trigger Implementation Filter stagi gt stage II stage III Qut d l l T T T T 1 T rd 707 800 900 1000 1200 1300 128 s 900 1000 1101 1200 1300 1438 NN a te EOM ax SL tee LL a ingth Filter Qut FilterIII Qut l 707 800 900 1000 1100 1200 1300 14 707 800 900 1000 1100 1200 1300 1438 Filter amp Pixel Timing Diagram Trigger output consists of following data mmy ____ Modes of operation Several setting parameters control the behavior of daq and should be set in according to desired operation mode e Mode oe m Standby
13. 32 1 NE P me mode 0 LED sby LED set 1 to switch LED off stoy FLT standby mode enables the Test Pulse activities mode mode of operation 00 standby 01 Run 1 10 Run 11 11 test fBeh FIFO behaviour 0 enable overflow 1 stop when full Command FLT Command Register PCI address 0x000004 37 1171 161 87 5 4 321 0 swi 1060 rstTP reset TestPulse pointers SWR set interrupt request for test LG load gains now rPoint reset pointers rstPg reset pages swIr SW trigger Version Number FLT Version Management PCI address 0 00000 0 000010 PCI Addr 0x0000000C Project N CFPGA 0x00000010 Project N FPGAS Project N 1 for Auger HEAT Board ID unique Silicon Serial Number address 0 000014 0 000018 PCI Adar 31 24 23 16 0x00000018 31 0 0x0000001C Slot ID BoardlD 47 32 IntMask Interrupt Mask Register PCI address 0x00001C 31 24 23 Interrupt Mask IntRequest Interrupt Sources address 0x000020 31 29 28 24 23 SlotID Interrupt Sources hrMeasEnable Enable Hite Rate Measurement address 0x000024 31 22 21 0 disabled default 1 enabled PixSettings Pixel Trigger Output Settings 1 amp 2 address 0x000030 0x000034 Address 21 0 000030 0 000034 LSBits 21 0 MSBits 2 1 0 MSBit i LSBit i
14. 52 4x32bit 71 SLT Block Diagram EventFIFO status Event FIFO SMB s TS subseconds Fla 1943 FLT AU LT S Second Counter SLT Event FIFO contents see SLT description 31 w 65 9 flt Sbit 5bit Energy 20 bit TS seconds 32 bit p mult 5bit TS subseconds 25 bit Energy diff 12bit top length 951 1 Event 4 long 16 byte 1 Event 4 100 ns 2 5MEvent sec FLT gt SLT transmission 22 21 20 19 18 17 16 15 14 13 12 11 10109 08 07 0605 04 03102 01 00 N mulip channel 0 0 P ____ 2 SS Energy 20bit TS seconds 12bit TS subseconds 25bit
15. 859 0 875 0 898 0 914 0 938 0 953 0 977 1 000 coeff x 128 89 92 94 97 99 102 104 107 110 112 115 117 120 122 125 128 none default pole zero correction coeff 0 836 Filter II 10 Pixel Trigger Handling A Pixel Trigger occurs in FPGAS when filter output exceeds the threshold A trigger bit as well as energy value and two time precision bits packed to a word are sent serial each channel individually to CFPGA to store there the trigger data measure the hit rate and to send these further to the SLT via 240Mbit s serial LVDS link The transmission of a word takes 300ns so the equal dead time after a trigger 15 to respect for the very short filter lengths lt 2 When the CFPGA detects the first bit of a trigger telegram it takes the actual timer state and stores this together with received data into EventFIFO Timer Unit The timer in CFPGA consists of two counters e 32 bit second counter and 25 bit subsecond counter SLT SecStrb The second counter can be set by SW SecStrb and increments with every SecStrobe pulse subsecond counter runs with SecCount _ second i i D internal 20MHz clock and restarts after N 1 every SecStrobe pulse Therefore first rey oun second is always to waiting for synchronization after each start of run mode l Pixel Trigger Transmission to SLT The CFPGA sends a pixel trigger word
16. 9 13 Ot WI oc ea 20 14 Measure MeN 22 15 ON MT Re 26 16 KATRIN FLI Reiter OVEEVIGW 27 IF Communication DN OR ba nt 32 18 FETAddress ___________ 33 19 Clock Distribution Synchronization 34 20 UO DESY LAU OMS see UI IR IE 35 vale E 35 22 multe dad addet 36 1 Introduction 2 Trigger van g ae he en 2 odale 20 Sud Bde backplane ne 440 igne om ine camera are processed Dy ZU 3oatds tone 2oarc I bed ibed up to 20 FLTs 24 channels gain tri Param II TimeMgr gt Timer 2 HUE cuu eo Unit FELT us Figure Trigger Concept 3 Subrack Architecture SLT slot FLT 1 10 FLT 11 20 E fe AE RR L L ete 2 EA eee Figure 1 19 Subrack 4 Backplane GTLP control bus a E M LVDS bus 16 bits 4 40MHz gt 80MB s wae PTrigger bus LVDS 240 Mb s 20 2 M LVDS Multipoint LVDS GTLP Gunnin
17. FLT V4 User Manual Project KATRIN Version 3 1 Denis Tcherniakhovski 17 April 2013 Contents D JJ ttodUuCHOTEs 3 2 Teer oneei 3 3 MDC UL deste ub aad 4 5 Sic aca wees cis cori dmt ner do uuu bonae qua qb ocean 6 0 KATRIN Modes Of d n Model standard nodes hat bai d pants 7 sat ce 7 8 sContmolor Analog 10 Gain amp Offset Settings Sequence of Settings 10 MU E T S 11 MES cc 12 10 Pixel Tigger andin 14 Fimer 15 Pixel Trigger 15 11 Trigger Data Storage internal 2 2000 02 0 0 0 0 0000 00 000000 16 12 ADC Data Storage IM x 1851 19 aye ua ata 19 ADC Page Management dug cu Duda na av 1
18. Ostatus read EventTable empty TimeStamp 1 ChannelN Page k Channel j read Energy Page k Channel j read ADCtrace Energy 1 TimeStamp 1 ADC trace 1 Read corresponding ADC data If multichannel trigger select next channel 12 ADC Data Storage 1M x 18bit ADC Data Format Three 1Mx18 synchronous QDRII RAMs are used to store the ADC data of 24 channels The address space of each SRAM is partitioned into 64 pages a 2K words Normally no trigger occurred the ADC data are written into the actual page organized as a ring buffer depth 2048 The 2K data frame as shown below consists of the 100us history and may be read out as block or via single Each data word consist of 12 bit ADC data and four auxiliary flags ADC Value 0 4095 PT Pixel Trigger flag Inh global Inhibit flag readout page 5 AN Append this Page flag ADC samples NxtPage read address x AppendThisPage Inhibit flag actual page write address Pixel Trigger ADC Page Management Each channel has a simplified page management implemented as a free running trigger counter The number of the actual page 0 63 equates to the trigger count 0 63 which increments delayed after post trigger time PostTrigTime When next trigger i 1 occurs during the post trigger time of previous trigger i the page number increases immediately i 1 and flag AppendThisPage bit13 is se
19. Pixel Trigger i Output 0 normal state 1 test pattern taken from the TestPatternMem 0 always 0 1 always 1 AccessTestReg Communication Test Register address 0x000040 SecTimer second counter address 0x000044 31 0 set time to get actual time hrControl Parameters for Hit Rate Measurement address 0x000048 24 16 zero T iod for HRmeas Meas Time 0 1 sec 2 2sec 3 gt 4sec 5 gt 165 6 gt 32sec histMeasTime define histogram measurement period in sec PCI address 0x00004C histRecTime second counter in range of 0 to histMeasTime 1 PCI address 0x000050 histNofMeas number of histogram measurement cycles PCI address 0x000054 postTrigTime post trigger time in bins of 50ns PCI address 0x000058 31 post trigger time 50 5 steps Offset analog offset address 0x001000 common offset Gain adjustable gain value per channel address 0x001004 HitRate Hit Rate Memory 24x32 channel PCI address 0x001100 2 1 measured hit rate Ov overflow flag TestPattern Test Pattern Memory 128x32 address 0x001100 31 25 24 23 0 _ Test pattern rep repeat flag pStatusA pStatusB pStatusC Peripheral Status Registers address PStatusA 0x002000 PStatusB 0x00A000 PStatusC 0x02A000 3128 27 209 209 8 7 65 FID Histogram
20. ce 11 alternate once LI Reset PN short gen 1 on 0 off default oF i oe d Di 5 aj N a y m M a i Output test mode see Table 9 in the Digital Outputs and Timing section 0000 off default 0001 midscale short 0010 FS short 0011 FS short 0100 checker board output 0101 PN 23 sequence 0110 PN 9 0111 one zero word toggle 1000 user input 1001 one zero bit toggle 1010 1x sync 1011 one bit high 1100 mixed bit frequency format determined by output_mode m E ee 5 8 Control of Analog Board Gain amp Offset Settings Sequence of Settings IPE AB Several gains and common offset on the analog board are controlled by three octal 3 8 24 12bit DACs MAX5306 for gains and one 12bit MAX5530 for offset connected as a chain via SPI bus to the CFPGA Gain and Offset values may be set read as e ablock of 25 words a common offset word 24 individual gains or sequence of single access to OffsetAddr address 0x00080000 followed by a block of 24 gains addressed to GainStart address 0x00080001 or e sequence of single accesses Loading of data starts after setting of bit 8 LG in the Command register The load routine takes about 150us due to slow
21. g Transceiver Logic Plus Figure 2 Backplane Block Diagram 5 FLT Architecture The frontend module FEboard is separated two submodules Analog Board AB and digital trigger board FLT to keep digital signal lines far away from the analog circuitry The main tasks of FLT are A D conversion of 24 incoming analog channels e settings of gain individually per channel and offset common on the analog board activation of the test pulse circuits on the analog board l bael digital filtering threshold setting and eentrel for each channel pixel trigger detection measurement of trigger rate for each channel storage of ADC data into the QDRII memory ADC RAM or storage of energy histograms memory page management transmission of pixel trigger data to SLT transmission of ADC data to SLT overall FLT control rPointe 3 x 8ch ADC CFPGA 5 GE 3 x FPGAS eoe 300ns Event table Energy Ch 1 channels 2 30 Energy Ch 24 2 cud T BE Data Bus 32bit I9 0 13u0 24 x Histograms Channel 1 pages 0 63 e Trace Energy Mode Channel 24 pages 0 63 Histogramming Mode 3x QDRII RAM x 18 always running tasks Figure FLT Block Diagram 6 KATRIN Modes of Operations Three different measurement schemas are available depending on preset mode e Run Mode I standard e Run Mode II for higher trigger rates e Test Mode for hardware and soft
22. nt period the readout page can be cleared to cleanup the old data and begin the histogram ab initio The cleanup can start either automatically by hardware clear mode CM 07 or by user 1 If the readout page was not cleared by user in clear mode 1 in sufficient time the histogram unit stops when HM 1 Set the 71 and 0 causes further accumulating of histograms The age of a histogram is shown in registers HistRecTime and HistNofMeas Programmable settings E Min E Bin HistMeas Time HM CM Control bits CLR Status HistRecTime HistNofMeas FirstEntry LastEntry page not empty Fixed parameters N of bins MaxHistCount Timing Page B Page B gt i HistgrSettings 19 00 HistgrSettings 23 20 HistMeas Time 31 00 HistgrSettings 28 HistgrSettings 29 Command 7 HistRecTime HistNofMeas HistLastFirst 15 00 HistLastFirst 15 00 pStatusABC 19 12 2048 2 32 1 32bit stop clear page 1 l 1 1 1 i 1 1 1 1 1 i i 1 1 HistMeasTime seconds Page A histogram begin 0 15 gt 0 1 2 4 8 16 32K 0 2 32 1 sec histogram mode 0 continuous 1 stop if not cleared before clear mode 0 automatically 1
23. of 512 64 so only one latest item can be read by SW Event Status register shows the current number of triggers 7 write pointer and read accesses read pointer The overflow behavior of the FIFO is selected by setting of bit 24 of Control Register 1 stop when full O enable overflow The depth of EventFIFO is selectable by setting of bit ControlReg 25 T 64 0 512 EventFIFO Status Register 291825 BAD While fifo not empty is observed the program reads last entry consisting of time stamp and channel list multiple pixels can trigger simultaneously decides on the channel number and gets then under specification of channel number the corresponding page number When channel and page indexes are known appropriate energy and ADC trace data can be read ADC data mode only Event Table 512x96 11 blocks addr Channel Map Time Stamp 24bit Seconds 32bit Subseconds ADC traces block of 2048 ADC samples a 16 bit block of 2048 ADC samples a 16 bit extern QDR RAM Event Handling Procedure Observe the event status Handle event 1 Read EventTable Get the channel list a time stamp Which channel s has have triggered Select channel number Get the page number Read corresponding energy block of 2048 ADC samples a 16 bit Event loop Channel List Channels loop Channel Event 1 read PageTable read EventFIF
24. s some error cases in FLTs Four possible error flags bits 3 0 are allocated for it Level 1 interrupt SpareOut P2 D2 line is used to inform SLT about the transaction status Interrupt signals on the backplane are active low when INT IntrotSources 3 0 amp not IntrptMask 3 0 SpareOut IntrptSources 7 4 amp IntrptMask 7 4 address 0x000014 31 29 28 24 23 16 000 Intrpt Mask RO __ e R Table Interrupt Register Bit Settings Interrupt Sources ee Bit __ Action2Done Bit6 __ Actios3Done Bit7 Action4Done 16 KATRIN FLT Register Overview Status FLT Module Status Register address 0x000000 31 23 16 1598 76 54 312 110 h h pue qa ea interrupt Bsy AB AB Qe aie EE HW FW P 2 power fail 1 1 unlocked 2 2 unlocked 100 FZK HEAT UP unlock phase 10 2 01 KATRIN ABFW Firmware type of analog board ABHW Hardware type of analog board SNE error flag Bsy action busy flag EF eventFlFOstatus empty flag AE eventFlFOstatus almost empty mode512 16 mode64 lt 4 AF eventFIFOstatus almost full flag mode512 447 gt 55 FF eventFIFOstatus full flag hPg histogram page toggle bit hClr histogram cleared flag IRQ interrupt request Control FLT Module Settings address 0x000004 31 25 24 233 2019 1615 5 4
25. serial data transmission Accessory new gains are stable only after 30ms settling time caused by blocking capacitor on the DAC outputs The summary delay 30 150 ms is indicated by the busy flag bit 8 in Status register Note Avoid any accesses to the gains while first 150us PCI Addr Chan Addr base RAM 31 IS D ee 0x00080000 ml _ 0x0800 0 00080004 0x00080004 0x00080004 23 0418 GainCh24 0800 091 08000 update offset Ox8000 Lo OxFFFF update gains OxFFFF OxFFFF update gains OXFFFF ______________ IC OxFFFF update gains OxFFFF Table GainRAM Format Test Pulse Circuit The test pulses are used to test the analog channels and trigger logic The SLT module provides the pulse shape and timings the FLT switches the several channels on off depending on the test pattern stored in the internal memory The internal FIFO TP_MEM consists of 128 words of 25 bits 22 2 outputs repeat flag Each word represents the state of the 22 test pulses outputs The 50ns long strobe on the TPulse line forces the next memory word AND masked with TestPulseEnable to be put on the FPGAs output and increments the address afterwards The bit 24 repeat flag marks the end of pattern and cause the restart of read pointer This may be used to build the repeat
26. t to mark the pile up 4 T postTrigTime G 13 Histogram Unit For higher trigger rates above kHz the standard mode Run 1 is not capable handling several events The histogram mode Run 1 can be used in order to determine the energy distribution of each channel Histogramming Schema The energy range and resolution are adjustable using E Min and E Bin parameters to get a best fit to expected energy spectrum To limit the readout time two margins FirstEntry and LastEntry marking an area that contains data are calculated by hardware Every bin of the histogram contains a 32 bit counter Bo first last in range BEEN E Min E Max If e i is the measured energy of a trigger i then the appropriate bin is calculated as Min gt gt E Bin All triggers that don t match the defined range will be absorbed into the bins and respectively If no triggers are observed during the measurement period HistMeasTime page not empty flags in pStatus registers remain zero The histogram building works without dead times during readout For this reason two memory fields two pages are used per channel one working area to build the actual histogram and one containing last measurements for readout Both pages are toggled after programmable time HistMeasTime Bits 29 28 bit28 histogram mode HM and bit 29 clear mode CM determinate behaviour of the histogram unit At the end of measureme
27. veto triggers is identical to the standard mode RunControl Global Settings Run Parameters address 0x000038 StoreData store data into external RAM RunADC start ADC sampling FilterRun run the boxcar filter amp trigger units reserved 7 reserved 51110 Jresrvd 0 0 0 0 0 000 00 0000000 0 19 16 overlap vetooverlaptime0 5 0 250ns mfod n fold 0 7 23 20 31 24 reserved Veto Mode Upgrade 23 11 2012 Existing trigger algorithm 1s updated because the zero cross time point was sensitive to noise for very short pulses Now delayed ADC data stream runs through short boxcar filter to make flat top of the pulse see Ar so zero cross time point can jitter for one cycle Boxcar filter is implemented as sum of N ADC values Filter I bypassed Energy progr length BL 1 4 ADCdata Trigger zero cross detector Filter Veto Mode Filter amp Trigger Implementation 2110 2100 2090 2080 2070 2060 2050 2040 030 794 796 798 800 802 804 806 808 810 812 814 816 The length of boxcar filter 15 programmable by user range of 0 none to 3 gt RunControl register 0x000038 bits 15 14 Interrupt Logic Two level interrupt mechanism is implemented at the FLT hardware layer Level 0 interrupt transmitted via INT line signal
28. ware test Run Mode I Active tasks are e Trigger logic filter comparator per channel e Trigger data storage energy timestamp traces storage e Rate Measurement standard mode Run Mode Il Active tasks are e Trigger logic filter comparator per channel histogram mode C ara LIC gt Te 77772 CO CO a O 4 1 CY ge Q ad inte Q 4 7 O Dac C C C e Histogram Unit per channel e Hit Rate Measurement Test Mode for test of the HW FW SW routines 7 A D Conversion ADC SPI port ADC PCI address space 0x000400 0x0007FC 256 Registers Table 15 Memory Map Register Addr Hex Default Notes Comments Chip Configuration Registers The nibbles should be mirrored so that LSB or MSB first mode registers correctly regardless of shift mode Default is unique chip ID different for each device This is a read only register 02 Param Name chip_port _ config chip grade Bit 7 MSB Child ID used to differentiate graded devices Device Index and Transfer Registers Bits are set to determine which on chip device receives the next write command Bits are set to determine which on chip device receives the next write command 05 FF device u X X X X pdate device in dex 2 device in Bit 6 Bit 5 Soft reset 1
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