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DM5806/DM6806 User`s Manual - RTD Embedded Technologies, Inc.

1. What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the DM5806 the DM5806 Digital I O module 4 11 RTD Embedded Technologies Inc interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the processor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the inter rupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smalles
2. AT Bus Connector DM6806 The DM6806 is exactly the same as the DM5806 except for the addition of the AT bus connector This allows you to stack the module with CPU s that have AT bus connectors Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem DM5806 Digital I O module 1 4 RTD Embedded Technologies Inc CHAPTER 1 BOARD SETTINGS The DM5806 board has jumper and switch settings you can change if necessary for your application The board is factory configured with the most often used settings
3. Enable and disable interrupt IRQ Enable Not used generation BA 4 Interrupt Status Clear Read status of interrupt Clear interrupt BA 5 Resemed Ta Reeved ____ _ ae 8254 Timer Counter 0 Read TC0 count value Load count register BA 8 8254 Timer Counter 1 Read TC1 count value Load TC1 count register BA 9 8254 Timer Counter 2 Read TC2 count value Load TC2 count register BA 10 8254 Control Word Program control register 11 BA Address BA 0 PPI Port Digital VO Read Write Transfers the 8 bit Port A digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port A a write transfers the written data from Port A through P2 to an external device 1 PPI Port B Digital Read Write Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port B a write transfers the written data from Port B through P2 to an external device BA 2 PPI Port C Digital I O Read Write Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through P2 and P6 and into PPI Port C a write transfers the written data from Port C through P2 and P
4. INTE flip flop definition BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Note All Mask flip flops are automatically reset during mode selection and device Reset intel Operating Modes Mode 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking is required data is simply written to or read from a specified port MODE 0 BASIC INPUT 82C55A Mode 0 Basic Functional Definitions e Two 8 bit ports and two 4 bit ports port can be input or output e Outputs are latched Inputs are not latched 16 different Input Output configurations are pos sible in this Mode tir INPUT tar tral A1 tHR 231256 8 MODE 0 BASIC OUTPUT D Dy taw CS A1 AU OUTPUT twe twa 231256 9 82C55A MODE 0 Port Definition intel A B GROUP A GROUP B D4 Ds Do PORTA PORT LONEN 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 1 OUTPUT OUTPUT 1 OUTPUT 0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT 0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT 0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT 0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT 0 1 1 1 OUTPUT INPUT 7 INPUT INPUT 1 0
5. 1 x x X X No Operation 3 State 0 1 1 X X No Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82C54 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter 82C54 GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte does not disable counting OUT is set low immediately no clock pulse re quired 2 Wri
6. BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your DM5806 board It provides a complete description of the I O map and detailed description of programming operations to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal Assembly and BASIC include source code to simplify your applications programming DM5806 Digital I O module 4 1 RTD Embedded Technologies Inc DM5806 Digital I O module 4 2 RTD Embedded Technologies Inc Defining the I O Map The I O map for the DM5806 is shown in Table 4 1 below As shown the board occupies 12 consecutive I O port locations The base address designated as BA can be selected using DIP switch S1 as described in Chapter 1 Board Settings This switch can be accessed without removing the board from the connectorr The following sections describe the register contents of each address used in the I O map Table 4 1 DM5806 I O Map Address Register Description Read Function Write Function Decimal 8255 PPI Port A Read Port A digital input lines Program Port A digital output lines 0 8255 PPI Port Read Port B digital input lines Program Port B digital output lines 1 8255 PPI Port Read Port C digital input lines Port C digital output lines 2 8255 PPI Control Word Notusd PPI configuration BA 3
7. to an external device DM5806 Digital I O module 4 3 RTD Embedded Technologies Inc BA 3 8255 PPI Control Word Write Only When bit 7 of this word 18 set to 1 write programs the PPI configuration Bit 6 must always be set to 0 Mode 2 operation is not supported by the DM5806 The table below shows the control words for the 16 possible Mode 0 Port combinations E mic ET 1 M FI ode Set ag Port C Lower 1 active 0 output Mode Select 1 input 00 mode 0 01 mode 1 Port B 1 mode 2 0 output 1 input Port A 0 output Select 1 input 0 0 1 1 Upper GreupB 0 output Group A 1 input 1 2 Port Pone Port CLower Binary Decimal Hex so Ooa sz s s ss Output input pu 10001010 138 sa 98 90 NECI sa 81 82 83 88 8A 8B 91 92 93 98 99 A DM5806 Digital I O module 4 4 RTD Embedded Technologies Inc When bit 7 of this word is set to 0 a write can be used to individually program the Port C lines 07 D6 D5 D4 D3 D2 01 DO Set Reset Bit Set Reset Function Bit Bit Select 0 set bit to 0 0 active 000 PC0 1 set bit to 1 001 PC1 010 PC2 011 PC
8. 1 0 1 0 0 Data Bus Port C 1 1 1 0 0 Data Bus Control Disable Function X X X X 1 Data Bus 3 State X X 1 1 0 Data Bus 3 State PC7_4 10 13 11 13 15 I O PORT PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports and B PCo 3 14 17 16 19 PORT C PINS 0 3 Lower nibble of Port C PBo 7 18 25 20 22 I O PORT B PINS 0 7 An 8 bit data output latch buffer and 8 24 28 bit data input buffer Voc 26 29 SYSTEM POWER 5V Power Supply 07 0 27 34 30 33 I O DATA BUS Bi directional tri state data bus lines connected to 35 38 system data bus RESET 35 39 high on this input clears the control register and all ports are set to the input mode WR 36 40 WRITE CONTROL This input is low during CPU write operations PAz 4 37 40 41 44 I O PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch NC 1 12 Connect 23 34 intel 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems lts function is that of a general purpose I O component to interface peripheral equipment to the microc
9. DATA BUS ro PCa PCo WR O GROUP CONTROL 231256 3 Figure 3 82C55A Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions RESET o EXTERNAL INTERNAL lt o PORT DATA IN PIN INTERNAL DATA OUT WR EXTERNAL lt PORT B C PIN INTERNAL DATA WR 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following hardware reset Figure 4 Port A B C Bus hold Configuration intel 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while
10. GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 12 intel 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written 0 0 0 51 FF FF le FE FD CW 18 LSB 3 CW 18 LSB 3 LSB 2 0 01 10101901050 FF aaa las LT TS TR 231244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again intel After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter bei
11. as the count is loaded BA 10 8254 Timer Counter 2 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 11 8254 Control Word Write Only Accesses the 8254 control register to directly control the three timer counters BCD Binary 0 binary 1 BCD Counter Select 00 Counter 0 Counter Mode Select 01 Counter 1 000 Mode 0 event count 10 Counter2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation x10 Mode 2 rate generator 01 read load LSB only x11 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe DM5806 Digital I O module 4 6 RTD Embedded Technologies Inc Programming the DM5806 This section gives you some general information about programming and the DM5806 board and then walks you through the major DM5806 programming functions These descriptions will help you as you use the example programs included with the board All of the program descriptions in this section use decimal values unless otherwise specified The DM3806 is programmed by writing to and reading from the correct I O port locations on the board These I O ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course asse
12. programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages 05 Ds D NC Vcc WR RD INDEX r1 CORNER DOS CLK 0 D2 7 Ceo COUNTER lt GATEU Dia CLK 1 12 13 15 16 1 18 o 2 LJ T LJ LJ LJ LT E 5 COUNTER GATE 1 OUTO GATEO GND NC OUT1GATE1CLK1 5 231244 3 z RUTA PLASTIC LEADED CHIP CARRIER D t Ds I CLK 2 Ds CONTROL WORD 4 2 D REGISTER Da OUT 2 D2 Di Do GATE 0 231244 1 Mn Figure 1 82C54 Block Diagram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82C54 Pinout October 1994 Order Number 231244 006 82C54 intel Table 1 Pin Description Symbol Fin Number Type Function DIP PLCC 07 00 1 8 2 9 1 0 Data Bidirectional tri state data bus lines connected to system data bus CLK 0 9 10 Clock 0 Clock input of Counter 0 OUT 0 10 12 Output 0 Output of Counter 0 GATE 0 11 13 Gate 0 Gate input of Counter 0 GND 12 14 Ground Power supply connection OUT 1 13 16 Out 1 Output of Counter 1 GATE 1 14 17 Gat
13. you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit 0 is for IRQO bit 1 is for and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for 1801 and so on If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on
14. 9 shows a blowup of the pads for Port A To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin For example Figure 1 10 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors DM5806 Digital I O module 1 9 RTD Embedded Technologies Inc PORT A PA0 7 Fig 1 10 Adding Pull ups and Pull downs to Some Digital I O Lines DM5806 Digital I O module 1 10 RTD Embedded Technologies Inc DM5806 Digital I O module 1 11 RTD Embedded Technologies Inc CHAPTER 2 BOARD INSTALLATION The DM5806 board is easy to install in your cpuModule other PC 104 based system This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your connec tions you can turn your system on and run the 5806DIAG board diagnostics program included on your example software disk to verify that your board is working DM5806 Digital I O module 2 1 RTD Embedded Technologies Inc DM5806 Digital I O module 2 2 RTD Embedded Technologies Inc Board Installation Keep the board in its antistatic bag until you are ready to install it in your cpuModule or other PC 104 based system When removing it from the bag hold the board at the edges and do not touch the components or connectors Before
15. APPENDIX aS ce oe Steak ak ad C 1 COMPONENT DATA SHEETS C 1 LIST OF ILLUSTRATION S 3 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 10 2 1 3 1 4 1 LIST OF ILLUSTRATIONS Board Layout Showing Factory Configured Settings et 1 3 Interrupt and Interrupt Channel Jumper 1 4 Pulling Down the Interrupt Request Line Ne 1 4 Interrupt Source Select Jumper u ua ote eU Hehe 1 5 8254 Timer Counter Clock Source Jumpers 5 1 5 8254 Timer Counter Circuit Block Diagram 9 1 6 Address S Watch cree EE A teste eee reote ete dee 1 6 Port Buffer Crrcuitty o eie Un erede ridere i qr eo D ere eor tee 1 8 Adding Pull ups and Pull downs to Some Digital Lines sees 1 9 P2 and P6 Connector Pin Assignments eese eee nennen enne 2 4 DM5806 Block Diagram ene teet ete n e dp tete tie peer edet e pedes 3 3 8254 Timer Counter Circuit Block Diagram et 4 10 iii iv INTRODUCTION DM5806 Digital I O module 1 1 RTD Embedded Technologies Inc DM5806 Digital I O module 1 2 RTD Embedded Technologies Inc The DM5806 dataModule general purpose digital I O board turns your IBM PC compatible cpuModul
16. IBFg OBFg IN OUT STBg IN OUT INTRA INTRA IN OUT STBA IN OUT IBFA IN OUT IN OUT OBFA MODE 0 OR MODE 1 ONLY Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port command only the Port pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to 16 change an interrupt enable flag the Set Reset Port C Bit command must be used With Set Reset Port C Bit command any Port line programmed as an output including INTR IBF and OBP can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset Port C Bit
17. INTR E IBF l O AO oe te nig RD DATA FROM DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL DATA FROM 82 55 TO 8080 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF e MASK e STB e RD e MASK e ACK e WR 14 82C55A MODE 2 AND MODE 0 INPUT CONTROL WORD D Ds Ds D Dz D D Do DEVE MODE 2 AND MODE 1 OUTPUT INTRA EA CONTROL WORD aoe D Dg Ds D Dy D D Do PDT 88 IBFA OBF RD PC2 ACK WR INTR MODE 2 AND MODE 0 OUTPUT CONTROL WORD D Dg Dg D Dz Dz D D LO PC2o 1 0 OUTPUT WR QA MODE 2 AND MODE 1 INPUT CONTROL wORD D Ds Ds D D3 Dz D Do hnao WR a 231256 21 Figure 16 MODE 1 4 Combinations 15 82C55A Mode Definition Summary MODE 2 GROUP A ONLY MODE 0 MODE 1 IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT INTRg INTRg IN OUT
18. Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis ADDRESS BUS CONTROL BUS DATA BUS MODE 0 PB7 PBo PAPA MODE 1 B 1 0 Jeo PB PB CONTROL CONTROL OR 1 0 OR 1 0 TPA MODE 2 B A PB PB vo t PA PA CONTROL Ed 231256 5 Figure 5 Basic Mode Definitions and Bus Interface 82C55A CONTROL WORD GROUP B PORT C LOWER 1 0 OUTPUT PORT B 1 INPUT 0 OUTPUT MODE SELECTION Q MODEO 1 MODE 1 PORT C UPPER 1 0 OUTPUT 1 0 OUTPUT MODE SELECTION 00 0 01 MODE 1 1 2 MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logi
19. The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer Note that DIP switch S2 has been provided to bypass the Port C buffers and allow Mode 1 operation of the 8255 Also note that by installing resistor packs at four locations near the 8255 PPI and soldering jumpers in the desired locations in the associated pads you can configure your digital I O lines to be pulled up or pulled down This procedure is explained at the end of this chapter DM5806 Digital I O module 1 1 RTD Embedded Technologies Inc DM5806 Digital I O module 1 2 RTD Embedded Technologies Inc Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumper and switches on the DM5806 board Fig ure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of S1 the base address switch to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Switch Factory Settings Jumper Function Controlled Jumpers Installed Connects 1 of 6 interrupt sources toaninterrupt channel pulls G ground for buffer tri state buffer to ground G for connected interrupt multiple interrupt applications channels
20. be easily configured to solve a wide range of digital real world problems This high performance TTL CMOS compatible chip has 24 parallel programmable digital I O lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines Each group can be programmed for Mode 0 or Mode 1 operation Do not try to use Mode 2 operation The DM5806 does not support Mode 2 When operating in Mode 1 the on board buffers must be disabled with JP1 and JP2 This procedure is described in Chapter 1 in the S2 DIP switch discussion The DM5806 operating modes are Mode 0 Basic input output Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A or Port B in conjunction with strobes or handshaking signals Port C posseses no buffers These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C The bidirectional buffers on the 8255 s I O lines monitor the 8255 control word to automatically set their direction Hardware changes to the buffer circuitry is required only when using Mode 1 where the Port C buffers must be disabled as described in Chapter 1 DM5806 Digital I O module 3 3 RTD Embedded Technologies Inc Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to sup
21. but its contents de termine how the Counter operates 82C54 INTERNAL BUS CONTROL STATUS WORD LATCH REGISTER STATUS REGISTER controt LOGIC CLK n OUT n 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter OLM and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82654 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRM and CR for Count Register Both are normal
22. by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here not use any DOS functions outportb BaseAddress 5 0 Clear DM5806 interrupt outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port BaseAddress 5 0 Clear DM5806 interrupt Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 uses vector 9 and so on Thus if the DM5806 will be using IRQ3
23. can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the sc
24. disabled EXT external Selects the interrupt source interrupt CLKO OSC CLK1 OT0 Sets the clock sources for the CLK2DOT1 all three three 8254 timer counters TCO timer counters are cascaded 102 the base address 300 hex 768 decimal Bypasses Port C buffers for Mode 1 Open buffers not operation bypassed DM5806 Digital I O module 1 3 RTD Embedded Technologies Inc P P5 JE os cH BE EM mm mm LINH 5 ose EC EE RE S x HEHE UM GEE My de datado dule FE A IR ADDRES l IIIIIIIIIIWIIIIIOIIIITU IZ 2 le F 5 le 7 a Fig 1 1 Board Layout Showing Factory Configured Settings DM5806 Digital I O module 1 4 RTD Embedded Technologies Inc P3 Interrupt and Interrupt Channels Factory Setting G Connected Interrupt Channels Disabled This header connector shown in Figure 1 2 lets you connect an interrupt source selected on P4 to an interrupt channel IRQ2 through IRQ7 To connect the interrupt source to an interrupt channel you must install a jumper across the desired IRQ channel P7 IRQ P3 IRQ Oa N pb wn Fig 1 2 Interrupt Interrupt Channel and P7 The bottom pair of pins on P3 labeled G are provide
25. future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 82C54 gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is val
26. installing the board in your system check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response The DM5806 comes with a stackthrough P1 connector The stackthrough connector lets you stack another board on top of your DM5806 plugging it into the data bus through the pins on the non component side of the board the side which faces up when the board is installed in the system To install the board follow the procedures described in the computer manual and the steps below 1 Turn OFF the power to your system 2 Touch the metal rack to discharge any static buildup and then remove the board from its antistatic bag 3 Select the appropriate standoffs for your application to secure the board when you install it in your system two sizes are included 4 Holding the board by its edges orient it so that the P1 bus connector s pin 1 lines up with pin 1 of the expansion connector onto which you are installing the board 5 After carefully positioning the board so that the card edge connector is resting on the expansion connector gently and evenly press down on the board until it is secured on the connector NOTE Do not force the board onto the connector If the board does not slide into place remove it and try aga
27. optional pull up pull down resistors High level output voltage ps 4 2V min Low level output voltage u u u u nnne 0 45V max High level input Voltage pp 2 2V min 5 5V Low level input voltage 0 3V min 0 8V max High level output current Isource CMOS buffer 12 mA max TTL buffer 16 mA max Low level output current Isink CMOS buffer 24 mA max TTL buffer 64 mA max Input load current ie UP tridente 10 pA MES 10 pF Input capacitance G IN FH1 MHZ a 10 pF Output capacitance git tiet E eee Deseo i e e er dts 20 pF Timer GOUhlels u cun du pan ava Far Fawn a CMOS 82C54 Three 16 bit down counters 6 programmable operating modes Counter input source pp External clock 8 MHz max or on board 8 MHz clock Counter outputs Available externally used as PC interrupts Counter gate pp External gate or always enabled Current Requirements 194 mA 5 volts Connectors P2 50 pin right angle header P6 20 pin right angle header Size 3 55 L x 3 775 W x 0 6 H 90mm x 96mm x 16mm DM5806 Digital I O module A 3 RTD Embedded Technologies Inc DM5806 Digital I O module A 4 RID Embedded Tec
28. that the DM5806 cannot use Mode 2 In the example below a decimal value of 128 sets up the 8255 so that all I O lines are Mode 0 outputs 1 0 0 0 0 0 0 0 07 D6 D5 D4 D3 D2 D1 DO Digital I O Operations Once the 8255 is initialized you can use the digital I O lines to control or monitor external devices Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts All three timer counters are cascaded at the factory Figure 4 1 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map section at the beginning of this chapter One of two clock sources the on board 8 MHz crystal or an external clock routed through on board I O connector P6 can be selected as the clock input to each timer counter In addition the timer counters can be cascaded by connecting TCO s output to TC1 s clock input and TC1 s output to TC2 s clock input The diagram shows how these clock sources are connected to the timer counters An external gate source can be connected to each timer counter through P6 When a gate is disconnected an on board pull up resistor automatically pulls the gate high enabling the timer counter T
29. 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 0 1 INPUT INPUT 13 OUTPUT INPUT 1 1 1 0 INPUT INPUT 14 INPUT OUTPUT 1 1 1 1 INPUT INPUT 15 INPUT INPUT MODE 0 Configurations CONTROL WORD 0 D D Ds D D D D D 7D PA PAY PC7 PC4 PC3 Pco PB PB CONTROL WORD 2 D Dg D D D D D D PAPA PC PC PC PC P8 PB CONTROL WORD 1 D Dg D D D D D Dy 5 0 CONTROL WORD 3 D 05 Ds D D D D Do 00 5 PAPA PC PC 4 8 pe pey 231256 10 intel MODE 0 Configurations Continued 82C55A CONTROL WORD 4 D D D D D D 05 D CONTROL WORD 8 0 05 Dy D Db a PA PA 82C55A PC PC 050 D Dy 4 PC PC P8 PB CONTROL WORD 5 CONTROL WORD 49 D Dg Dg D D 82C55A CONTROL WORD 6 CONTROL WORD 10 82 55 98 PB CONTROL WORD 47 PAPA 82C55A 4 ree E CONTROL WORD 11 PB PR 231256 11 82C55A MODE 0 Configurations Continued CONTROL WORD 12 D Dg 05 D Dz D D Dg i a ray 4 PC PCo PB PBo CONTROL WORD 14 by Ds Ds D D Dy D D
30. 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Interrupt Enable Flag Position Alternate Port C Pin Signal Mode INTE B PC2 ACKg Output Mode 1 or STBg Input Mode 1 INTE A2 PC4 STBA Input Mode 1 or Mode 2 INTE 1 PC6 ACKA Output Mode 1 or Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 17 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Supply Voltage 0 510 8 0V Operating Voltage 4Vto 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Vcc 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS intel NOTICE This is a production data sheet The specifi cations are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended tended exposure beyond the Operating Conditions may affect device reliability TA 0 to 70 5V 10 GND 0V TA 40 C to 85 C for Extended Temperture Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage 0 5 0 8 V VIH Input High Voltage 2 0
31. 16 bits 0 1 Read Write least significant byte only 1 Binary Coded Decimal BCD Counter 1 0 Read Write most significant byte only 4 Decades Read Write least significant byte first then most significant byte NOTE Don t care bits X should be 0 to insure compatibility with future Intel products Figure 7 Control Word Format 82C54 Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the A4 Ao inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in intel struction sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counters pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format If Counter is programmed to read write two byte counts the followin
32. 2 Fig 1 5 8254 Timer Counter Clock Source Jumpers P5 DM5806 Digital I O module 1 6 RTD Embedded Technologies Inc ON BOARD CONNECTOR P6 OSC 8 MHz TIMER COUNTER CLK PIN 104 EXT CLK 0 0 5 V PIN 11 b EXT GATE 0 PIN 12 T C OUT O TIMER PIN 13 COUNTER CLK 1 O EXT CLK 1 O GATE PIN 140 EXT GATE 1 PIN 15 T C OUT 1 OUT COUNTER CLK I PIN 16 amp EXT CLK 2 2 GATE PIN 17 EXT GATE 2 PIN 18 T C OUT 2 l Fig 1 6 8254 Timer Counter Circuit Block Diagram S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the DM5806 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the DM5806 has an easily accessible DIP switch S1 which lets you select any one of 32 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any value shown in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 5 be
33. 3 100 PC4 101 PC5 110 PC6 111 PC7 For example 1 you want to set Port C bit to 1 you would set up the control word so that bit 7 1 0 bits 1 2 and 3 are 0 this selects PC0 and bit 0 15 1 this sets PC0 to 1 The control word 15 set up like this 0 0 0 0 1 serwo D7 D6 05 ba ba p2 Di bo written to 3 dont Set Reset Set PC0 Function Bit Bit Select 000 PC0 4 IRQ Enable Write Only Enables and disables interrupt generation Writing a 1 enables interrupt generation writing a 0 disables interrupt generation Interrupt Enable Disable 0 interrupt disabled 1 interrupt enabled 5 Interrupt Status Clear Read Write A read shows the status of the interrupt bit 0 only as defined below A write clears the interrupt data written is irrelevant Each time the interrupt status bit goes high a write should follow to clear the bit Interrupt Status 0 no interrupt 1 interrupt has occurred DM5806 Digital I O module 4 5 RTD Embedded Technologies Inc BA 6 Reserved BA 7 Reserved BA 8 8254 Timer Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded 9 8254 Timer Counter 1 Read Write A read shows the count in the counter and write loads the counter with a new value Counting begins as soon
34. Board Settings 8254 Timer Counter An 8254 programmable interval timer contains three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions The clock gate and output pins for each of the timer counters are available at P6 a 20 pin right angle connector What Comes With Your Board You receive the following items in your DM5806 package DM5806 interface board with stackthrough bus header Software and diagnostics diskette with BASIC Turbo Pascal and Turbo C source code User s manual If any item is missing or damaged please call RTD Embedded Technologies Inc Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your DM5806 package RTD Embedded Technologies Inc offers a full line of accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Accessories for the DM5806 include the TB50 terminal board and XB50 prototype terminal board for prototype development and easy signal access the DM14 extender board for testing your module in a PC compatible computer the XO50 opto 22 cable for connection to opto 22 systems and XT50 twisted pair wire flat ribbon cable assembly for external interfacing DM5806 Digital I O module 1 3 RTD Embedded Technologies Inc
35. DIAG Diagnostics Program eene nennen neret nennen tenen nenne enne 2 4 CHAPTER 3 HARDWARE DESCRIPTION 3 1 Digital I O 8255 Programmable Peripheral Interface 4 3 3 funus d PPP 3 4 Interr p S e AI e mei ee o peo eciam teu epe iun qu A ua iii 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING 4 1 Defining the Map n Eh RE be ee iia 4 3 BA 0 PPI Port A Digital I O Read Write 4 4 3 BA 1 PPI Port B Digital VO Read Write Te 4 3 BA 2 PPI Port C Digital I O Read Write eese nennen nre mentre nennen trees 4 3 3 8255 PPI Control Word Write 4 4 4 IRQ Enable Write 4 5 5 Interrupt Status Clear Read Write ps 4 5 6 Reserved 4 6 BAHT ROSE VEO m M 4 6 BA 8 8254 Timer Counter O Read Write na 4 6 9 8254 Timer Counter 1 Read Write 4 6 BA 10 8254 Timer Counter 2 Read Write a 4 6 11 8254 Control Word Write Only u W 4 6 Programming the DM5806 aaa ete oio Pea ed ede teer te
36. DIGITAL GND 20 pin on board l O connector PB7 DIGITAL GND PA0 6 DIG n GND PA1 85 88 DIGITAL GND PA2 87 88 DIGITAL GND PA3 89 80 DIG At GND PA4 DIGITAL GND DIGITAL GND 45 46 DIGITA D 47 48 DiGITA D DIGITA D 5 VOLTS Fig 2 1 P2 and P6 I O Connector Pin Assignments Connecting the Digital I O The DM5806 is designed for direct connection to industry standard opto 22 isolated I O racks and system modules Each digital I O line on P2 has a digital ground as shown in Figure 2 1 For all digital I O connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is connected to the DIGITAL GND A cable to provide direct connection to opto 22 systems the 50 is available as an accessory from RTD Connecting the Timer Counter I O External connections to the timer counters on the DM5806 can be made by connecting the high side of the external device to the appropriate signal pin on on board connector P6 and the low side to a P DIGITAL GND Connecting the External Interrupt The DM5806 can receive an externally generated interrupt signal EXTINT through I O connector P2 pin 2 and route it to an IRQ channel through on board header connectors P3 and P4 Interrupt generation is enabled through software When interrupts are enabled a rising edge on the EXTINT line will cause the selected IRQ line to go
37. DM5806 DM6806 User s Manual STIGO RTD Embedded Technologies Inc Real Time Devices Accessing the Analog World BDM 610010023 Es Rev B ISO9001 and AS9100 Certified DM5806 DM6806 User s Manual RTD Embedded Technologies INC 103 Innovation Blvd State College PA 16803 0906 Phone 1 814 234 8087 FAX 1 814 234 5218 E mail sales rtd com techsupport rtd com web site http www rtd com Revision History Rev New manual naming method Rev B Board redesign Published by RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 Copyright 1999 2002 2003 by RTD Embedded Technologies Inc rights reserved Printed in U S A The RTD Logo is a registered trademark of RTD Embedded Technologies cpuModule and utilityModule are trademarks of RTD Embedded Technologies PhoenixPICO and PheonixPICO BIOS are trademarks of Phoenix Technologies Ltd PS 2 PC XT PC AT and IBM are trademarks of International Business Machines Inc MS DOS Windows Windows 95 Windows 98 and Windows NT are trademarks of Microsoft Corp PC 104 is a registered trademark of PC 104 Consortium All other trademarks appearing in this document are the property of their respective owners Table of Contents INTRODUCTION 1 1 Digital 1 3 o ord costs saved eer d ede e eec e FO te EE E e et tte w
38. EI Tee ere ei ere edet 4 7 Clearing and Setting Port etit e OR RO GROTIUS RR CREE 4 8 Initializing the 8255 PPM eate eee tt 4 9 Digital I O Operations eee ete per t E C eap ette be et PR bita 4 9 Timer Couhtets e eere RR RI EE RAP n HE HAUS 4 9 eie asa 4 11 What Is an Interrupt y REIR ERE IO 4 11 Interrupt Request Eines 5 iet RR EE EFE TEE epp eh SE Fee Re cane 4 11 8259 Programmable Interrupt Controller pp 4 11 Interrupt Mask Register hayka PREFERRED EXE UE 4 11 End of Interrupt EOD n u L q enne neret netten ai pu aY 4 11 What Exactly Happens When an Interrupt Occurs 4 4 11 Using Interrupts in Your Programs 4 12 Writing an Interrupt Service Routine ISR et 4 12 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector pp 4 13 Restoring the Startup IMR and Interrupt Vector et 4 14 Comnion Interrupt Mistake ritieni 4 14 Example Programs er RE unun 4 14 Cand Pascal Programs ener d pU ete ear dep o EI DEREN RS 4 14 BASIC 4 14 APPENDIX wor E A 1 DM5806 DM6806 SPECIFICATION S 1 APPENDIX A MM LUE 1 CONNECTOR PIN ASSIGNMENTS pp
39. EST 0 45 150 pF 231256 29 231256 30 A C Testing Inputs Are Driven At 2 4V For A Logic 1 And 0 45V i For Logic 0 Timing Measurements Are Made At 2 0V For Vexr Is Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For A Logic 0 The Specification Includes Jig Capacitance 23 DM5806 Digital I O module C 4 RTD Embedded Technologies Inc intel 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER m Compatible with all Intel and most W Three independent 16 bit counters other microprocessors m Low Power CHMOS W High Speed Zero Wait State Icc 10 mA 8 MHz Count Operation with 8 MHz 8086 88 and frequency 5801854188 Completely TTL Compatible m Handles Inputs from DC 10 MHz for 82C54 2 alx E Counter Modes m Available in EXPRESS M Binary or BED Counting Standard Temperature Range m Status Read Back Command Extended Temperature Range m Available in 24 Pin DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator
40. Eee 1 3 What Comes With Your Board reste ede e ERR eret eene a u rep ee Food ana ER 1 3 Board Acessories aneen 1 3 AT Bus Connector DM6806 2 ee 1 4 STE NA 1 4 When You Need PPP 1 4 CHAPTER 1 BOARD SETTINGS L PA S Qu Sp a Sas kusa kaws 1 1 Factory Configured Switch and Jumper Settings 3 1 3 P3 Interrupt and Interrupt Channels Factory Setting G Connected Interrupt Channels Disabled 1 5 P4 Interrupt Source Select Factory Setting EXT essere 1 6 P5 8254 Timer Counter Clock Sources Factory Settings CLK0 OSC CLK1 OTO 2 1 1 6 51 Base Address Factory Setting 300 hex 768 decimal a 1 7 S2 Buffer Bypass Switch Factory Setting OPEN Not Bypassed pe 1 8 E External amp 5 volt Fuse z u aa eren iier Ur Ia eter t ipe tede Q Cere ete E Deeper dn 1 8 Pull up Pull down Resistors on Digital I O Lines ee 1 9 CHAPTER 2 BOARD INSTALLATION a ense ta stato sense tastes sonata stas eta sesso sense tastes sone 2 1 Board Installation iic ed eO ORE UR AR RERO US GR RR ERE RERO ERE ERRORS 2 3 External VO 2 3 Connecting the Digital 2 4 Connecting the Timer Counter 2 4 Connecting the External Intert pt 5 eee e der rr UP REIR ERREUR aaa 2 4 Running the 5806
41. F 13 231244 9 Figure 16 Mode 1 intel MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also CW 14 LSB 3 0 0 ale nl 1 CW 14 LSB 3 paje a CW 14 LSB 4 158 5 4 2 71814 231244 10 NOTE A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 82C54 Writing a new count while counting does not affect the current counting sequence lf a t
42. One 8 bit bi directional bus port Port A and 5 bit control port Port C Both inputs and outputs latched e The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus 1 0 Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit of PCg Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit of PCy 13 82C55A In e CONTROL WORD Dg Ds D Dz D 0 EDUC Do B 1 INPUT 0 OUTPUT D PORTB 1 INPUT 0 OUTPUT V GROUP 0 MODEO 1 MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 DATA FROM CPU TO 82C55A WR
43. Vcc V VoL Output Low Voltage 0 4 V 2 5 VoH Output High Voltage 3 0 V 2 5 mA Vcc 0 4 V 100 pA lit Input Leakage Current 1 pA Vin Vcc to OV Note 1 loFL Output Float Leakage Current 10 pA ViN Vcc to 0V Note 2 IDAR Darlington Drive Current 2 5 Note 4 Ports A B Rext 5000 1 7V IPHL Port Hold Low Leakage Current 50 300 pA Vour 1 0V Port A only IPHH Port Hold High Leakage Current 50 300 pA 3 0V Ports A B C IPHLO Port Hold Low Overdrive Current 350 pA 0 8V IPHHO Port Hold High Overdrive Current 350 pA 3 0V lcc Voc Supply Current 10 mA Note 3 IccsB Vcc Supply Current Standby 10 pA Voc 5 5V Vin Voc or GND Port Conditions If I P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High NOTES 1 Pins Ay CS WR RD Reset 2 Data Bus Ports B C 3 Outputs open 4 Limit output current to 4 0 mA 18 intel CAPACITANCE TA 25 GND OV 82C55A Symbol Parameter Min Max Units Test Conditions Cin Input Capacitance 10 pF Unmeasured pins C I O Capacitance 20 F returned to GND Mp lob fc 1 MHz 5 Sampled not 100 tested A C CHARACTERISTICS TA 0 to 70 C 5V 10 GND OV TA 40 to 85 for Ex
44. and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 25 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 23 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress OR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 2 and then write the re
45. ata Sheet Reprint DM5806 Digital I O module C 5 RTD Embedded Technologies Inc DM5806 Digital I O module C 6 RTD Embedded Technologies Inc DM5806 Board User Selected Settings Base I O Address
46. ators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 25 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits 0 to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the DM5806 board functions Initializing the 8255 PPI Before you can operate the DM5806 the 8255 must be initialized This step must be executed every time you start up reset or reboot your computer The 8255 is initialized by writing the appropriate control word to I O port BA 3 The contents of your control word will vary depending on how you want to configure your I O lines Use the control word description in the previous I O map section to help you program the right value Remember
47. cal MO approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 82C55A CONTROL WORD BIT SET RESET 1 SET 0 BIT SELECT 1 o BIT SET RESET FLAG 0 231256 7 Figure 7 Bit Set Reset Format intel When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C Interrupt Control Functions This function allows the Programmer to disallow or allow a specific 1 O device to interrupt the CPU with out affecting any other device in the interrupt struc ture
48. chip carrier PLCC packages POWER TM SUPPLIES 820554 ano VD gt GROUP panne npa UPPER a BI DIRECTIONAL DATA BUS 2 00 gt INTERNAL DATA BUS LA Porc KL LOwER vo PB1 PBo 82C55A 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale October 1995 Order Number 231256 004 2 A 82c55 intel Table 1 Pin Description Symbol Pin Number Type Name and Function Dip PLCC yp PA3_0 1 4 2 5 PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch RD READ CONTROL This input is low during CPU read operations CS CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise GND 7 8 System Ground A1 0 8 9 9 10 ADDRESS These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers A4 Ao RD WR CS Input Operation Read 0 0 0 1 0 Port A Data Bus 0 1 0 1 0 Port B Data Bus 1 0 0 1 0 Port C Data Bus 1 1 0 1 0 Control Word Data Bus Output Operation Write 0 0 1 0 0 Data Bus Port A 0 1 1 0 0 Data Bus Port B
49. command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current intel Reading Port C Status In Mode 0 Port C transfers data to or from the pe ripheral device When the 82C55A is programmed to function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de vice Reading the contents of Port C allows the pro grammer to test or verify the status of each pe ripheral device and change the program flow ac cordingly There is no special instruction to read the status in formation from Port C A normal read operation of Port C is executed to perform this function 82C55A INPUT CONFIGURATION 1 0 1 0 IBFA INTEA INTRA INTEg IBFg INTRB GROUP GROUP B OUTPUT CONFIGURATIONS D De Ds D4 D3 Do D D GBFA INTEA I O Vo INTRA INTEB OBFg INTRg GROUP A GROUP B Figure 17a MODE 1 Status Word Format D Dg Ds D3 Do D D GEBFA INTE1 IBFA INTE2 INTRA GROUP A GROUP B Defined By Mode
50. d so that you can install a jumper which connects a 1 kilohm pull down resistor to the output of a high impedance tri state driver which carries the interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active So whenever an interrupt request is made the tri state buffer is enabled forcing the output high and causing an interrupt You can monitor the interrupt status through bit 0 in the status word IO address location BA 5 After the interrupt has been serviced the clear command returns the IRQ line low disabling the tri state buffers and pulling the output low again Figure 1 3 shows this circuit Because the interrupt request line is driven low only by the pull down resistor you can have two or more boards which share the same IRQ channel You can tell which board issued the interrupt request by monitoring each board s IRQ status bit NOTE When you use multiple boards that share the same interrupt only one board should have the G ground jumper installed The rest should be disconnected Whenever you operate a single board the G jumper should be installed INT IRQ STATUS source CLK INTERRUPT REGISTER INTERRUPT CLR Fig 1 3 Pulling Down the Interrupt Request Line DM5806 Digital I O module 1 5 RTD Embedded Technologies Inc P4 Interrupt Source Select Factory Setting EXT This header connector shown in Figure 1 4 lets you connect one of six i
51. e other PC 104 computer into a high performance control system Ultra compact for embedded and portable applica tions the DM5806 board features 24 TTL CMOS 8255 based programmable digital I O lines Direct connection to opto 22 I O system modules Buffered outputs for high driving capability Optional pull up pull down resistors Simple I O or strobed I O operation Three 16 bit 8 MHz timer counters Software enabled interrupts IRQ2 IRQ7 IRQ10 IRQ12 IRQ14 IRQ15 Requires 5 volts only for operation BASIC Turbo Pascal and Turbo C source code diagnostics program The following paragraphs briefly describe the major function of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Digital VO The DM5806 has 24 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip The 8255 can be operated in one of two modes Mode 0 or Mode 1 To ensure high driving capacity CMOS buffers are installed Pads for installing and activating pull up or pull down resistors are included on the board Installation proce dures are given at the end of Chapter 1
52. e 1 Gate input of Counter 1 CLK 1 15 18 Clock 1 Clock input of Counter 1 GATE 2 16 19 Gate 2 Gate input of Counter 2 OUT 2 17 20 Out 2 Output of Counter 2 CLK 2 18 21 Clock 2 Clock input of Counter 2 Ao 20 19 23 22 Address Used to select one of the three Counters orthe Control Word Register for read or write operations Normally connected to the system address bus A4 Selects 0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control Word Register CS 21 24 Chip Select A low on this input enables the 82C54 to respond to RD and WR signals RD and WR are ignored otherwise RD 22 26 Read Control This input is low during CPU read operations WR 23 27 Write Control This input is low during CPU write operations Vcc 24 28 Power 5V power supply connection 1 11 15 25 Connect FUNCTIONAL DESCRIPTION General The 82C54 is a programmable interval timer counter designed for use with Intel microcomputer systems It is a general purpose multi timing element that can be treated as an array of MO ports in the system software The 82C54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures the 82C54 to match his require ments and programs one of the counters for the de sired delay After the desired delay t
53. east significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 10 intel MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires CW 12 LSB 3 EEES CW 12 LSB 3 0 0 CW 12 LSB 2 LSB 4 0 FF F
54. equest has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer is used by the keyboard IRQ3 by 2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the DM5806 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you will need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H
55. et reset of PCs INTE B Controlled by bit set reset of 2 CONTROL WORD D Ds Ds D D D D Do s 1 0 OUTPUT CONTROL WORD D Ds Ds Dy D D D Dy 23125615 Figure 10 1 Output GBF INTR OUTPUT we 231256 16 Figure 11 MODE 1 Strobed Output 12 intel Combinations of MODE 1 82C55A Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I O applications CONTROL WORD D Dg Ds D D D D Dy o Pd P657 1 0 OUTPUT WR 0 PORT A STROBED INPUT PORT B STROBED OUTPUT o CONTROL WORD D Dg 05 D Ds D D Do PCy 1 0 OUTPUT RD gt PORT A STROBED OUTPUT PORT 5 INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus I O This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group A only
56. fore setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 7 shows the DIP switch set for a base address of 300 hex 768 decimal Fig 1 7 Base Address Switch S1 DM5806 Digital I O module 1 7 RTD Embedded Technologies Inc Base Address Base Address Decimal Hex 54321 Decimal Hex 54321 656 290 11001 S2 Buffer Bypass Switch Factory Setting OPEN Not Bypassed When operating the 8255 in Mode 1 the lines of Port C function as control lines some as outputs and some as inputs When using Mode 1 the Port C buffers must be disabled and bypassed to allow the Port C lines to be individually set as inputs or outputs Figure 1 8 shows the Port C buffers and the following steps tell you how to configure the board for Mode 1 operation To remove buffering from Port C 1 Close DIP switches 1 through 8 on S2 2 Move JP1 from 2 3 to 1 2 3 Move JP2 from 2 3 to 1 2 CAUTION Remember whenever you close the switches be sure to disable the buffers by moving the jumpers F1 External 5 volt Fuse This 1 ampere fuse protects the 5 volt line available at I O connector P2 pin 49 from drawing too much current and damaging system equipment DM5806 Digital I O module 1 8 RTD Embedded Technologies Inc F
57. g edge of RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of INTE B Controlled by bit set reset of 82C55A MODE 1 PORT A CONTROL WORD D Dg 05 Ds D D Do B BORED PCe7 IBFA 1 0 OUTPUT INTRA RD 2 mo CONTROL WORD D Dg Ds D4 Ds D D Do INTR 231256 13 Figure 8 MODE 1 Input IBF INTR RD INPUT FROM PERIPHERAL tes 231256 14 Figure 9 MODE 1 Strobed Input 11 82C55A Output Control Signal Definition OBF Output Buffer Full F F The OBF output will go low to indicate that the CPU has written data out to the specified port The OBF F F will be set by the rising edge of the WR input and reset by ACK Input being low ACK Acknowledge Input low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is a one OBF is a one and INTE is It is reset by the falling edge of WR INTE Controlled by bit s
58. g precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count A1 Ao A1 Ao Control Word Counter 0 1 1 Control Word Counter 2 1 1 LSB of count Counter 0 0 0 Control Word Counter 1 1 1 MSB of count Counter 0 0 0 Control Word Counter 0 1 1 Control Word Counter 1 1 1 LSB of count Counter 2 1 0 LSB of count Counter 1 0 1 MSB of count Counter 2 1 0 MSB of count Counter 1 0 1 LSB of count Counter 1 0 1 Control Word Counter 2 1 1 MSB of count Counter 1 0 1 LSB of count Counter 2 1 0 LSB of count Counter 0 0 0 MSB of count Counter 2 1 0 MSB of count Counter 0 0 0 As Ao A1 Ao Control Word Counter 0 1 1 Control Word Counter 1 1 1 Counter Word Counter 1 1 1 Control Word Counter 0 1 1 Control Word Counter 2 1 1 LSB of count Counter 1 0 1 LSB of count Counter 2 1 0 Control Word Counter 2 1 1 LSB of count Counter 1 0 1 LSB of count Counter 0 0 0 LSB of count Counter 0 0 0 MSB of count Counter 1 0 1 MSB of count Counter 0 0 0 LSB of count Counter 2 1 0 MSB of count Counter 1 0 1 MSB of count Counter 0 0 0 MSB of count Counter 2 1 0 MSB of count Counter 2 1 0 NOTE In all four examples all counters are programmed to read write two byte counts These are
59. gnals should be synchronous This is accomplished by using a CLK input signal to the 82C54 counters which is a derivative of the sys tem clock source Another technique is to externally synchronize the WR and CLK input signals This is done by gating WR with CLK 82C54 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ao 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command CLK 0 DATA 07 06 COUNTER O BUS BUFFER E E 1 qun COUNTER LATE OUT 1 RD a W O LOGIC INTERNAL BUS x 2 CONTROL WORD T 2 REGISTER Our 2 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself
60. h counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the 82C54 count all but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits D5 through D0 contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system D Dg Ds D4 Ds 02 Dy Do NULL OUTPUT couNr Rw1 Rwo m2 M1 MO BCD D7 1 Out Pin is 1 0 Out Pin is O Ds 1 Null count 0 Count available for reading Ds Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the coun
61. he 82C54 will interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated Some of the other counter timer functions common to microcomputers which can be implemented with the 82C54 are Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller intel Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82C54 to the system bus see Figure 9 CLK 0 COUNTER GATEO l 1 FRONTER GATE 1 OUT INT RNAL BUS CLK 2 WORD REGISTER GATE 2 COUNTER 2 OUT 2 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82C54 A4 and Ag select one of the three counters or the Control Word Regis ter to be read from written into A low on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low The WR and CLK si
62. he output from each timer counter is available at P6 where it can be used for interrupt generation or for counting functions The timer counters can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode DM5806 Digital I O module 4 0 RTD Embedded Technologies Inc ON BOARD CONNECTOR P6 OSC 8 MHz TIMER COUNTER CLK PIN 104 EXT CLK 0 0 5 V PIN 11 b EXT GATE 0 PIN 12 T C OUT O TIMER PIN 13 COUNTER CLK 1 O EXT CLK 1 O GATE PIN 140 EXT GATE 1 PIN 15 T C OUT 1 OUT COUNTER CLK I PIN 16 amp EXT CLK 2 2 GATE PIN 17 EXT GATE 2 PIN 18 T C OUT 2 Fig 4 1 8254 Timer Counter Circuit Block Diagram Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high untila new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The ou
63. high and the IRQ status bit will change from 0 to 1 The pulse applied to the EXTINT pin should have a duration of at least 100 nanoseconds Running the 5806DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 5806DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device DM5806 Digital I O module 2 4 RTD Embedded Technologies Inc CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the major features of the DM5806 s 8255 based digital I O and 8254 timer counters This chapter also describes the hardware selectable interrupts DM5806 Digital I O module 3 1 RTD Embedded Technologies Inc DM5806 Digital I O module 3 2 RTD Embedded Technologies Inc The DM5806 provides buffered digital I O lines and three 16 bit timer counters as shown Figure 3 1 This chapter describes the hardware which makes up the digital I O circuitry timer counters and hardware selectable interrupts 1 0 CONNECTOR BUFFER AND INTERRUPT CONTROL EXTINT PC BUS z 8255 D PPI PULL UP DOWN mE RESISTORS 5 VOLTS CONTROL DIGITAL GROUND Fig 3 1 DM806 Block Diagram Digital 8255 Programmable Peripheral Interface The 8255 programmable peripheral interface PPI can
64. hnologies Inc APPENDIX B CONNECTOR PIN ASSIGNMENTS DM5806 Digital I O module B 1 RTD Embedded Technologies Inc DM5806 Digital I O module B 2 RTD Embedded Technologies Inc S0 Pin Connector P2 PC0 O 2 EXTINT 1 3 2 DIGITAL GND PC2 5 6 DIGITAL GND PC3 7 DIGITAL GND PC4 9 DIGITAL GND 5 41 12 DIGITAL GND PC6 9 4 DIGITAL GND PC7 5 DIGITAL GND PB0 i DIGITAL GND DIGITAL GND PB2 21 22 DIGITAL GND PB3 29 DIGITAL GND PB4 25 DIGITAL GND PB5 27 DIGITAL GND PB6 DIGITAL GND PB7 En 32 DIGITAL GND PA0 83 DIGITAL GND PA1 85 DIGITAL GND PA2 87 DIGITAL GND PA3 DIGITAL GND PA4 DIGITAL GND PA5 44 DIGITAL GND 45 DIGITAL GND PA7 4 DIGITAL GND 5 VOLTS DIGITAL GND 20 pin Connector P6 Pco 1 2 Pct Pc2 3 4 Pcs 5 6 Pcs Pc6 7 PC7 DIGITAL GND 9 10 EXT CLK 0 EXT GATE 0 1712 our o EXT CLK 1 1312 EXT GATE 1 our 1 0910 EXT CLK 2 EXT GATE 2 0909 our 2 DIGITAL GND DIGITAL GND DM5806 Digital I O module B 3 RTD Embedded Technologies Inc DM5806 Digital I O module B 4 RTD Embedded Technologies Inc APPENDIX C COMPONENT DATA SHEETS DM5806 Digital I O module 1 RTD Embedded Technologies Inc DM5806 Digital I O module C 2 RTD Embedded Technologies Inc Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint DM5806 Digital I O module C 3 RTD Embedded Technologie
65. id 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 AO A1 11 CS 0 RD 1 WR 0 D Dg Ds D4 Do Di Do 1 1 COUNT STATUS CNT 2 CNT 1 CNT O O Ds 0 Latch count of selected counter s Da 0 Latch status of selected counter s 03 1 Select counter 2 02 1 Select counter 1 D4 1 Select counter O Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for eac
66. ig 1 8 C Buffer Circuitry Pull up Pull down Resistors on Digital I O Lines The 8255 programmable peripheral interface provides 24 parallel TTL CMOS compatible digital I O lines which can be interfaced with external devices The lines are divided into four groups eight Port A lines four Port C Lower lines eight Port B lines and four Port C Upper lines You can install and connect pull up or pull down resistors for any or all of these four groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull down lines connected to relays which control turning motors on and off These motors turn on when the digital lines controlling them are high To use the pull up pull down feature you must first install 10 kilohm resistor packs in any or all of the four locations around the 8255 labeled PA PB PCL and PCH PA and PB located to the right of the 8255 take a 10 pin pack and PCL and PCH located along the top edge of the board take 6 pin packs Figure 1 9 shows these locations After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled G for ground on one end and V for Vcc on the other end The middle hole is common PA is for Port A PB for Port B PCL is for Port C Lower and PCH is for Port C Upper Figure 1
67. in Wiggling the board or exerting too much pressure can result in damage to the DM5806 or to the computer board 6 After the board is installed connect the 50 pin cable to I O connector P2 on the board and a 20 pin cable to on board connector P6 if desired When making these connections note that there is no keying to guide you in orientation Make sure that pin 1 of P2 s cable is connected to pin 1 of P2 pin 1 is marked on the board with a small square For twisted pair cables pin 1 is the dark brown wire for standard single wire cables pin lis the red wire Pin 1 on P6 is also marked on the board with a small square 7 Make sure all connections are secure External I O Connections Figure 2 1 shows the DM806 s P2 I O connector pinout and P6 on board I O connector pinout Refer to these diagrams as you make your I O connections DM5806 Digital I O module 2 3 RTD Embedded Technologies Inc GNI L GN L GN L GN P2 50 pin I O connector OO extinr PC0 PC1 PC1 GO DIGITAL GND pc2 PC2 GO DIGITAL GND DIGITAL GND PC6 PC7 PC4 DIGITAL GND Pc5 ca DIGITAL GND DIGITAL GND EXT CLK 0 PC6 3 3 DIGITAL GND EXT GATE 0 T C OUT 0 PC7 5 9 DIGITAL GND EXT CLK 1 EXT GATE 1 PBO 17 18 DIGITAL GND T C OUT 1 EXT CLK 2 di DIGITAL GND EXT GATE 2 T C OUT 2 PB2 21 G2 DIGITAL GND DIGITAL GND DIGITAL GND PB3 23 93 DIGITAL GND PB4 DIGITAL GND 27 28 DIGITAL GND 6 6
68. inues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there intel ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4V to 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS 82C54 NOTICE This is a production data sheet The specifi cations are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability TA 0 to 70 C 5V 10 GND OV 40 to 85 for Extended Temperature Symbol Parameter Min Max Units Test Conditions Input Low Voltage 0 5 0 8 V VIH Input High Voltage 2 0 Vcc 0 5 V VoL Output Low Voltage 0 4 V lo 2 5 mA VoH Output High Voltage 3 0 V 2 5 mA Vcc 0 4 V lon 100 pA lu Input Load Current 2 0 pA Vin to loFL Output Float Leakage Current 10 pA to 0 0V lcc Vcc Supply C
69. ly referred to as one unit and called just CR When a new count is written to the Counter the count is intel stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously CRM and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ao A4 connect to the Ao A4 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems O o F BUS 16 CONTROL BUS DATA BUS 8 a A C Do D7 RD wR 82C54 COUNTER COUNTER COUNTER 0 2 tS r SO OUT GATE CLK OUT GATE CLK OUT GATE CLK 231244 7 Fig
70. m the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts 11 82C54 OUT will be high for N 1 2 counts and low for N 1 2 counts CW 16 158 4 z S I uz RE SE ze uh E n Ws NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting
71. mbly language make it very easy to read write these ports The table below shows you how to read from and write to I O ports using some popular programming languages Language Turbo C Turbo Pascal Assembly Data INP Address Data inportb Address Data Port Address mov dx Address in al dx Write OUT Address Data outportb Address Data Port Address Data mov dx Address mov al Data out dx al In addition to being able to read write the I O ports on the DM5806 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB 96 amp a b c a b c a b8c a b c MOD DIV AND OR a bMODc a bDIVc a bANDc a bORc Language MOD AND OR a bMODc a b c a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the DM5806 DM5806 Digital I O module RTD Embedded Technologies Inc Clearing
72. ng loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there 0 0 0 FFI o 5 131013 LSB 3 CW 1A 158 3 158 5 nin pa 0 EE I 21 10 5 4 231244 13 Figure 20 Mode 5 82 54 Signal Low Status Or Going Rising High Modes Low 0 Disables Enables counting counting 1 1 Initiates counting 2 Resets output after next clock 2 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high 3 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high 4 Disables Enables counting counting 5 Initiates counting Figure 21 Gate Pin Operations Summary MIN MAX MOBE COUNT COUNT 0 1 0 1 1 0 2 2 0 3 2 0 4 1 0 NOTE 0 is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts 13 82C54 Operation C
73. nt value latched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched count vallue which is one least significant bit EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature Symbol Parameter 820542 Units Min Max two CLK Delay for Loading 25 25 ns twa Gate Delay for Sampling 25 25 ns 16 intel 5 82C54 WAVEFORMS WRITE Ao twa cs WR 231244 14 READ Ao cs RD DATA BUS 231244 15 RECOVERY nv RD WR 231244 16 17 82C54 CLOCK AND GATE WMODE COUNT CLK GATE OUTPUT 0 231244 17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT 24 2 0 2 0 pz TEST POINTS lt A C Testing Inputs are driven at 2 4V for a logic 1 and 0 45V for a logic 0 Timing measurements are made at 2 0V for a logic 1 0 8V for a logic 0 0 8 0 45 231244 18 REVISION SUMMARY The following list represents the key differences be tween Rev 005 and 006 of the 82C54 Data Sheet 1 References to and specifications for the 8 MHz 82C54 are removed Only the 10 MHz 82C52 2 remains in production 18 DEVICE UNDER TEST 231244 19 CL 150 pF includes jig capacitance Intel 82C54 Programmable Interval Timer D
74. nterrupt sources for interrupt genera tion These sources OTI and OT2 which are the three 8254 timer counter outputs which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI and EXT an external interrupt you can route onto the board through the P2 I O connector To connect an interrupt source place the jumper across the desired set of pins Note that only ONE interrupt source can be activated at a time oon Ug m 33300 N O O 0 P4 Fig 1 4 Interrupt Source Select Jumper P4 P5 8254 Timer Counter Clock Sources Factory Settings CLK0 OSC CLK1 OT0 CLK2 OT1 This header connector shown in Figure 1 5 lets you select the clock sources for the 8254 timer counters TC0 TC1 and TC2 The factory setting cascades all three timer counters with the clock source for TC0 being the on board 8 MHz oscillator the output of providing the clock for and the output of TC1 providing the clock for TC2 You can connect any or all of the sources to an external clock input through the P6 on board I O connector or you can set TC1 and TC2 to be clocked by the 8 MHz oscillator Figure 1 6 shows a block diagram of the timer counter circuitry to help you with these connections NOTE When installing jumpers on this header make sure that only one jumper is installed in each group of two or three CLK pins P5 g OSC d OSC EC1 OT1 OSC EC
75. o 00 06 lt CONTROL WORD 13 D Dg Ds Da Dz Dj D Dy 0 0 CONTROL WORD 15 D Dg 05 D D D D Dy PA PA PCP PCy 0 0 PB PB 231256 12 Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring I O data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals 10 Mode 1 Basic functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit port is used for control and status of the 8 bit data port intel Input Control Signal Definition STB Strobe Input low on this input loads qata into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is one IBF is a one and INTE is a one It is reset by the fallin
76. ommon to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a 14 intel high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and cont
77. omputer system bus The functional configu ration of the 82 55 is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A 82C55A Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word regis
78. only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82C54 There are three possible methods for reading the counters a simple read operation the Counter Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result intel COUNTER LATCH COMMAND The second method uses the Counter Latch Com Like a Control Word this command is written to the Control Word Register which is selected when A4 Ao 11 Also like a Control Word the SC0 SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word Ao 11 CS 0 1 WR 0 D Dg Ds D4 Dz D Dy Do SC1 sco X X X X SC1 0 specify counter to be latched SC1 SC0 Counter 0 0 0 0 1 1 1 0 2 1 1 Read Back Command 05 04 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with
79. or dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your DM5806 board can interrupt the processor when one of the six interrupt sources is enabled By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second r
80. our board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your DM5806 board Digital I O DIGITAL Simple program the shows how to read and write the digital I O lines Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer BASIC Programs These programs include both source code files and executable files so that you can run them on your DM5806 All of the executable programs are set up to look for the board at a base address BA of 300 hex 768 decimal If you change the base address of the board you must also change the BA in your programs Digital DIGITAL Simple program the shows how to read and write the digital I O lines Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer DM5806 Digital I O module 4 14 RTD Embedded Technologies Inc APPENDIX A DM5806 DM6806 SPECIFICATIONS DM5806 Digital I O module 1 RID Embedded Technologies Inc DM5806 Digital I O module A 2 RID Embedded Technologies Inc DM5806 Characteristics Typical 25 C Interface Switch selectable base address mapped Jumper selectable interrupts al sea CMOS 82C55 Opto 22 compatible NUMBER OT iui ier de eed To a 24 Logic compatibilty TTL CMOS Configurable with
81. port a wide range of timing and counting functions These timer counters can be cascaded or used individually for many applications Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT The clock sources for the timer counters can be selected using jumpers on header connector P5 see Chapter 1 The timer counters can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Interrupts The DM3806 can use any one of six signal sources to generate interrupts These sources OTI and OT2 which are the three 8254 timer counter outputs which is the INTRA signal from the 8255 PPI which is the INTRB signal from the 8255 PPI and EXT an external interrupt you can route onto the board through the P2 I O connector Chapter 1 tells you how to set the jumpers on interrupt header connectors P3 P7 and P4 and Chapter 4 provides some programming information DM5806 Digital I O module 3 4 RTD Embedded Technologies Inc CHAPTER 4
82. reen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you DM5806 Digital I O module 4 12 RTD Embedded Technologies Inc spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt bit on the DM5806 by writing any value to BA 5 Issue the EOI command to the 8259 interrupt controller
83. rigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 15 similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue fro
84. s Inc Intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most m Control Word Read Back Capability Other Microprocessors m Direct Bit Set Reset Capability m High Speed Zero Wait State 2 A DC Dri bilit I Operation with 8 MHz 8086 88 and m Capability on all I O bionda Available in 40 Pin DIP and 44 Pin PLCC m 24 Programmable 1 0 Pins bp m m Available in EXPRESS m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 0 device which is designed for use with all Intel and most other microprocessors It provides 24 O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255 5 In MODE 0 each group of 12 1 0 pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82 55 is available in 40 pin DIP and 44 pin plastic leaded
85. se width of initial Reset pulse after power on must be at least 50 uSec Subsequent Reset pu minimum The output Ports A B or C may glitch low during the reset pulse but all port pins will be held at a logic one level after the reset pulse 20 ses may be 500 ns intel gt 82C55A WAVEFORMS MODE 0 BASIC INPUT INPUT C A1 A0 0 05 231256 22 MODE 0 BASIC OUTPUT WR 575 CS A1 OUTPUT w 231256 23 21 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INTR INPUT FROM PERIPHERAL 231256 24 MODE 1 STROBED OUTPUT INTR OUTPUT twe 231256 25 22 intel 82C55A WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 TO 8255 INTR PERIPHERAL Be MEC K J e EE PERIPHERAL 8255 DATA FROM 8255 TO PERIPHERAL DATA FROM 8255 TO 8080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD is permissible INTR IBF MASK STB RD MASK ACK WR WRITE TIMING READ TIMING Ao 1 CS Ao 1 CS DATA BUS DATABUS2 22222 HIGH IMPEDANCE HIGH IMPEDANCE 231256 28 231256 27 TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 2 4 DEVICE UNDER Vea T
86. sulting value to the port In C this is programmed as v inportb port_address amp 171 outportb port address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 23 2 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v inportb port address DM5806 Digital I O module 4 8 RTD Embedded Technologies Inc amp 199 40 outportb port address v A final note Don t be intimidated by the binary oper
87. t any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Command D Dg Ds D4 D3 02 Dy Do Description Results 11110 1 Read count status Count status latched Counter 1 Counter 0 for Counter 0 1 1 1 011 Read back status of Counter 1 Status latched for Counter 1 1 1 1 0 1 0 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 1 1 0 Read back count of Counter 2 Count latched for Counter 2 1 1 01011 Read back count and status of Count latched for Counter 1 but not status Read back status of Counter 1 Command ignored status already latched for Counter 1 Figure 13 Read Back Command Example CS RD WR A4 Ao 0 1 0 0 0 Writeinto Counter 0 0 1 0 0 1 Write into Counter 1 0 1 0 1 0 Write into Counter 2 0 1 0 1 1 Write Control Word 0 0 1 0 0 Read from Counter 0 0 0 1 0 1 Read from Counter 1 0 0 1 1 0 Read from Counter 2 0 0 1 1 1 No Operation 3 State
88. t mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status of the DM5806 and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you
89. tended Temperature BUS PARAMETERS READ CYCLE Symbol Parameter 82C55A 2 Units Test Min Max Conditions tAR Address Stable Before RD J 0 ns TRA Address Hold Time After RD T 0 ns tar RD Pulse Width 150 ns tap Data Delay from RD J 120 ns tDF RD T to Data Floating 10 75 ns try Recovery Time between RD WR 200 ns WRITE CYCLE Symbol Parameter SGSRUE Units Min Max Conditions taw Address Stable Before WR 0 ns Address Hold Time After WR T 20 ns Ports amp 20 ns Port C tww WR Pulse Width 100 ns tpw Data Setup Time Before WR T 100 ns twp Data Hold Time After WR T 30 ns Ports A amp B 30 ns Port C 19 82C55A OTHER TIMINGS Symbol Parameter PROSA pale Test Min Max onditions twp WR 1 to Output 350 ns UR Peripheral Data Before RD 0 ns tun Peripheral Data After RD 0 ns tAK ACK Pulse Width 200 ns ter STB Pulse Width 100 ns tps Per Data Before STB High 20 ns tpH Per Data After STB High 50 ns tAD ACK Output 175 ns tkD ACK 1to Output Float 20 250 ns twos WR 1 to OBF 0 150 ns tAOB ACK 010 1 150 ns tsIB STB 0 to IBF 1 150 ns tRIB RD 1to 0 150 ns tRIT RD Oto INTR 0 200 ns tsIT STB 1toINTR 1 150 ns tAIT ACK 1to INTR 1 150 ns twiT WR 0to INTR 0 200 ns see note 1 tRES Reset Pulse Width 500 ns see note 2 NOTE 1 INTR T may occur as early as WR 2 Pul
90. ter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 intel THIS ACTION CAUSES A Write to the control E Null count 1 word register 1 B Write to the count Null count 1 register CR 2 C New count is loaded Null count 0 into CE CR CE 11 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 2 f the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s withou
91. ter can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 82C55A In POWER SUPPLIES vo PA PAQ GROUP A CONTROL ro PC BIDIRECTIONAL DATA BUS 8 817 INTERNAL
92. the IRQ DM5806 Digital I O module 4 13 RTD Embedded Technologies Inc Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the DM5806 and forgetting to issue the EOI command to the 8259 interrupt controller before exiting ISR Example Programs Included with the DM5806 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C Pascal Assembly and BASIC Also included is an easy to use menu driven diagnostics program 5806DIAG which is especially helpful when you are first checking out your board after installation Before using the software included with y
93. ting the second byte allows the new count to be loaded on the next CLK pulse 3 When there is a count in progress writing a new LSB before the counter has counted down to 0 and rolled over to FFFFh WILL stop the counter However if the LSB is loaded AFTER the counter has rolled over to FFFFh so that an MSB now exists in the counter then the counter WILL NOT stop This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written 82C54 If an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 LSB 4 0 FF UE CWz10 LSB 3 OUT l J 0 0 0101010 FF pp ped epe 10 LSB 3 LSB 2 2 1 E 231244 8 The Following Conventions Apply Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the l
94. tput is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again DM5806 Digital I O module 4 10 RTD Embedded Technologies Inc Jnterrupts What Is an Interrupt An interrupt 15 an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy f
95. ure 6 82C54 System Interface intel OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed 82C54 Programming the 82C54 Counters are programmed by writing a Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when A4 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The A4 Ao in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used Control Word Format CS 0 RD 1 Ay Ao 11 WR 0 D Dg 05 02 Do 1 SC0 RW1 RWO M2 M1 M0 BCD SC Select Counter M MODE SC1 SC0 M2 M1 M0 0 Select Counter 0 0 0 0 Mode 0 1 Select Counter 1 0 0 1 Mode 1 1 0 Select Counter 2 x 1 0 Mode 2 1 1 Read Back x 1 1 Mode 3 See Read Operations 1 0 Mode 4 RW Read Write 1 Modes RW1 RW0 BCD 0 0 Latch Command see Read Operations 0 Binary Counter
96. urrent 20 mA Clk Freq IccsB Vcc Supply Current Standby 10 pA CLK Freq DC CS Voc All Inputs Data Bus Voc Outputs Floating IccsB1 Voc Supply Current Standby 150 pA CLK Freq DC CS Vcc All Other Inputs Pins VGND Outputs Open Cin Input Capacitance Cio I O Capacitance Output Capacitance 10 pF fo 1MHz 20 pF Unmeasured pins 20 pF returned to GND A C CHARACTERISTICS TA 0 C to 70 C 5V 10 GND 0V TA BUS PARAMETERS Note 1 40 to 85 for Extended Temperature READ CYCLE Symbol Parameter Become Units Min Max tar Address Stable Before RD 30 ns tsn CS Stable Before RD 0 ns tRA Address Hold Time After RD T 0 ns tar RD Pulse Width 95 ns trp Data Delay from RD 85 ns tap Data Delay from Address 185 ns tor RD f to Data Floating 5 65 ns trv Command Recovery Time 165 ns NOTE 1 AC timings measured at 2 0V 0 8V 15 82C54 A C CHARACTERISTICS Continued WRITE CYCLE Symbol Parameter 82C54 2 Units Min Max tAW Address Stable Before WR 0 ns tew CS Stable Before WR 0 ns twa Address Hold Time After WR T 0 ns tww WR Pulse Width 95 ns tpw Data Setup Time Before WR T 95 ns twp Data Hold Time After WR T 0 ns Command Reco
97. very Time 165 ns CLOCK AND GATE Symbol Parameter 82054 2 Units Min Max tCLK Clock Period 100 DC ns fi High Pulse Width 300 ns tPWL Low Pulse Width 50 3 ns TR Clock Rise Time 25 ns tr Clock Fall Time 25 ns taw Gate Width High 50 ns tar Gate Width Low 50 ns tas Gate Setup Time to CLK T 40 ns Gate Time After CLK T 50 2 ns Top Output Delay from CLK J 100 ns topa Output Delay from Gate 100 ns twc CLK Delay for Loading 4 0 55 ns twa Gate Delay for Sampling 4 5 40 ns two OUT Delay from Mode Write 240 ns teL CLK Set Up for Count Latch 40 40 ns NOTES 2 In Modes 1 and 5 t rising clock edge may 3 Low going glitches riggers are sampled on each rising clock edge A second trigger within 70 ns for the 82C54 2 of the not be detected hat violate tpwH tpwL may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampled not 100 tested TA 25 C 6 If CLK present at Twc min then Count equals N 2 CLK pulses Two max equals Count N 1 CLK pulse Twc min to max count will be either N 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at Two min Counter will not be triggered at TwG max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at TcL min CLK will be reflected in count value latched at Tc max CLK will not be reflected in the cou

DM5806/DM6806 User`s Manual - RTD Embedded Technologies, Inc.

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