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Laboratory Exercise 7

1. change appropriately when a key is pressed and the FSM can wait for each key press to end before continuing The outputs produced by this second FSM can be used as part of the scheme for creating a variable time interval in your circuit Note that KEY 2 and KEY are asynchronous inputs to your circuit so be sure to synchronize them to the clock signal before using these signals as inputs to your finite state machine The ticker tape should operate as follows When the circuit is reset scrolling occurs at about one second intervals Pressing KEY repeatedly causes the scrolling speed to double to a maximum of four letters per second Pressing KEY repeatedly causes the scrolling speed to slow down to a minimum of one letter every four seconds Implement your circuit on the DE2 board and demonstrate that it works properly Copyright 2006 Altera Corporation
2. clock pulse to the circuit After the word HELLO scrolls off the left side of the displays it then starts again on the right side Design your circuit by using eight 7 bit registers connected in a queue like fashion such that the outputs of the first register feed the inputs of the second the second feeds the third and so on This type of connection between registers is often called a pipeline Each register s outputs should directly drive the seven segments of one display You are to design a finite state machine that controls the pipeline in two ways 1 For the first eight clock pulses after the system is reset the FSM inserts the correct characters H E L L 0 into the first of the 7 bit registers in the pipeline 2 After step 1 is complete the FSM configures the pipeline into a loop that connects the last register back to the first one so that the letters continue to scroll indefinitely Write Verilog code for the ticker tape circuit and create a Quartus II project for your design Use KEY o on the DE2 board to clock the FSM and pipeline registers and use SW as a synchronous active low reset input Write Verilog code in the style shown in Figure 3 for your finite state machine Compile your Verilog code download it onto the DE2 board and test the circuit Part VI For this part you are to modify your circuit from Part V so that it no longer requires manually applied clock pulses Your circuit should scroll the word HELLO suc
3. if all flip flop outputs are 0 when the FSM is in the reset state This approach is preferable because the FPGA s flip flops usually include a clear input port which can be conveniently used to realize the reset state but the flip flops often do not include a set input port Table 2 shows a modified one hot state assignment in which the reset state A uses all Os This is accom plished by inverting the state variable yo Create a modified version of your Verilog code that implements this state assignment Hint you should need to make very few changes to the logic expressions in your circuit to implement the modified codes Compile your new circuit and test it both through simulation and by downloading it onto the DE2 board State Code Name ys 7 eysyay3y2y1Yo 000000000 000000011 000000101 000001001 000010001 000100001 001000001 010000001 100000001 BOB Tas gt Table 2 Modified one hot codes for the FSM Part II For this part you are to write another style of Verilog code for the FSM in Figure 2 In this version of the code you should not manually derive the logic expressions needed for each state flip flop Instead describe the state table for the FSM by using a Verilog case statement in an always block and use another always block to instantiate the state flip flops You can use a third always block or simple assignment statements to specify the output z To implement the FSM use four state flip flops y3 yo and
4. Laboratory Exercise 7 Finite State Machines This is an exercise in using finite state machines Part I We wish to implement a finite state machine FSM that recognizes two specific sequences of applied input sym bols namely four consecutive 1s or four consecutive Os There is an input w and an output z Whenever w 1 or w 0 for four consecutive clock pulses the value of z has to be 1 otherwise z 0 Overlapping sequences are allowed so that if w 1 for five consecutive clock pulses the output z will be equal to 1 after the fourth and fifth pulses Figure 1 illustrates the required relationship between w and z Clock Figure 1 Required timing for the output z A state diagram for this FSM is shown in Figure 2 For this part you are to manually derive an FSM circuit that implements this state diagram including the logic expressions that feed each of the state flip flops To implement the FSM use nine state flip flops called yg yo and the one hot state assignment given in Table 1 State Code Name ys 7Yoysyay3y2y1Yo 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 TANMATAW gt Table 1 One hot codes for the FSM Reset Figure 2 A state diagram for the FSM Design and implement your circuit on the DE2 board as follows 1 Create a new Quartus II project for the FSM circuit Select as the target chip the Cyclone II EP2C35F672C6
5. binary codes as shown in Table 3 State Code Name Y3Y2Y1Y0 0000 0001 0010 0011 0100 0101 0110 0111 1000 HKTZMOAnmABTAW gt Table 3 Binary codes for the FSM A suggested skeleton of the Verilog code is given in Figure 3 module part2 define input and output ports define signals reg 3 0 y_Q Y_D y_Qrepresents current state Y_D represents next state parameter A 4 b0000 B 4 b0001 C 4 b0010 D 4 b0011 E 4 b0100 F 4 b0101 G 4 b0110 H 4 b0111 I 4 b1000 always w y_Q begin state_table case y_Q A if w Y_D B else Y_D F remainder of state table default Y_D 4 bxxxx endcase end state_table always posedge Clock begin state_FFs end state_FFS assignments for output z and the LEDs endmodule Figure 3 Skeleton Verilog code for the FSM Implement your circuit as follows 1 Create a new project for the FSM Select as the target chip the Cyclone II EP2C35F672C6 2 Include in the project your Verilog file that uses the style of code in Figure 3 Use the toggle switch SW 9 on the Altera DE2 board as an active low synchronous reset input for the FSM use SW as the w input and the pushbutton KEYo as the clock input which is applied manually Use the green LED LEDG g as the output z and assign the state flip flop outputs to the red LEDs LEDR3 to LEDR o Assign the pins on the FPGA to connect to the switches and
6. h that the letters move from right to left in intervals of about one second Scrolling should continue indefinitely after the word HELLO scrolls off the left side of the displays it should start again on the right side Write Verilog code for the ticker tape circuit and create a Quartus II project for your design Use the 50 MHz clock signal CLOCK_50 on the DE2 board to clock the FSM and pipeline registers and use KEY as a synchronous active low reset input Write Verilog code in the style shown in Figure 3 for your finite state machine and ensure that all flip flops in your circuit are clocked directly by the CLOCK_5O input Do not derive or use any other clock signals in your circuit Compile your Verilog code download it onto the DE2 board and test the circuit Part VII Augment your design from Part VI so that under the control of pushbuttons KEY 2 and KEY the rate at which the letters move from right to left can be changed If KEY is pressed the letters should move twice as fast If KEY2 is pressed the rate has to be reduced by a factor of 2 Note that the KEY2 and KEY switches are debounced and will produce exactly one low pulse when pressed However there is no way of knowing how long a switch may remain depressed which means that the pulse duration can be arbitrarily long A good approach for designing this circuit is to include a second FSM in your Verilog code that properly responds to the pressed keys The outputs of this FSM can
7. nswer Part IV We want to design a modulo 10 counter like circuit that behaves as follows It is reset to 0 by the Reset input It has two inputs w and wo which control its counting operation If w1wo 00 the count remains the same If wiwo 01 the count is incremented by 1 If wiw 10 the count is incremented by 2 If wiw 11 the count is decremented by 1 All changes take place on the active edge of a Clock input Use toggle switches SW 2 and SW for inputs w and wo Use toggle switch SWo as an active low synchronous reset and use the pushbutton KEY as a manual clock Display the decimal contents of the counter on the 7 segment display HEXO 1 Create a new project which will be used to implement the circuit on the DE2 board 2 Write a Verilog file that defines the circuit Use the style of code indicated in Figure 3 for your FSM 3 Include the Verilog file in your project and compile the circuit Simulate the behavior of your circuit Assign the pins on the FPGA to connect to the switches and the 7 segment display Recompile the circuit and download it into the FPGA chip NY Dn Nn A Test the functionality of your design by applying some inputs and observing the output display Part V For this part you are to design a circuit for the DE2 board that scrolls the word HELLO in ticker tape fashion on the eight 7 segment displays HEX7 0 The letters should move from right to left each time you apply a manual
8. the LEDs as indicated in the User Manual for the DE2 board 3 Before compiling your code it is necessary to explicitly tell the Synthesis tool in Quartus II that you wish to have the finite state machine implemented using the state assignment specified in your Verilog code If you do not explicitly give this setting to Quartus II the Synthesis tool will automatically use a state assignment of its own choosing and it will ignore the state codes specified in your Verilog code To make this setting choose Assignments gt Settings in Quartus II and then click on the Analysis and Synthesis item on the left side of the window As indicated in Figure 4 change the parameter State Machine Processing to the setting User Encoded 4 To examine the circuit produced by Quartus II open the RTL Viewer tool Double click on the box shown in the circuit that represents the finite state machine and determine whether the state diagram that it shows properly corresponds to the one in Figure 2 To see the state codes used for your FSM open the Compilation Report select the Analysis and Synthesis section of the report and click on State Machines 5 Simulate the behavior of your circuit 6 Once you are confident that the circuit works properly as a result of your simulation download the circuit into the FPGA chip Test the functionality of your design by applying the input sequences and observing the output LEDs Make sure that the FSM properly transitions be
9. tween states as displayed on the red LEDs and that it produces the correct output values on LEDG 9 7 In step 3 you instructed the Quartus II Synthesis tool to use the state assignment given in your Verilog code To see the result of removing this setting open again the Quartus II settings window by choosing Assignments gt Settings and click on the Analysis and Synthesis item Change the setting for State Machine Processing from User Encoded to One Hot Recompile the circuit and then open the report file select the Analysis and Synthesis section of the report and click on State Machines Compare the state codes shown to those given in Table 2 and discuss any differences that you observe Settings part2 Category General Analysis amp Synthesis Settings Files User Libraries Current Project Specify options for analysis amp synthesis These options control Quartus II Integrated Synthesis and Device do not affect VOM or EDIF netlists unless WYSIWYG primitive resynthesis is enabled Timing Requirements amp Options EDA Tool Settings Optimization Technique Auto Global Options MAX Devices Only Compilation Process Settings C Speed Vv Analysis amp Synthesis Settings ipsenced io VHDL Input Verilog HDL Input C Area Vv Default Parameters Synthesis Netlist Optimizations F Create debugging nodes for IP cores Fitter Settings Vv ceme IV Auto Open Drain Pins Assembler M Auto ROM Replacement Vv Timing Analyzer Design Assistant IV A
10. uto RAM Replacement IV Auto Shift Register Replacement SignalT ap Il Logic Analyzer Vv Power Up Don t Care Logic Analyzer Interface DSP Block Balancing Jauto o SignalProbe Settings Simulator Settings State Machine Processing User Encoded PowerPlay Power Analyzer Settings Software Build Settings Restructure Multiplexers auo o iS HardCopy Settings PowerPlay power optimization Normal compilation x HDL Message Level keve o id More Settings Description Specifies the processing style used to compile a state machine You can use your own User Encoded style or select One Hot Minimal Bits or Auto Compiler selected encoding Cancel Figure 4 Specifying the state assignment method in Quartus II Part III For this part you are to implement the sequence detector FSM by using shift registers instead of using the more formal approach described above Create Verilog code that instantiates two 4 bit shift registers one is for recog nizing a sequence of four Os and the other for four 1s Include the appropriate logic expressions in your design to produce the output z Make a Quartus II project for your design and implement the circuit on the DE2 board Use the switches and LEDs on the board in a similar way as you did for Parts I and II and observe the behavior of your shift registers and the output z Answer the following question could you use just one 4 bit shift register rather than two Explain your a
11. which is the FPGA chip on the Altera DE2 board Write a Verilog file that instantiates the nine flip flops in the circuit and which specifies the logic expressions that drive the flip flop input ports Use only simple assign statements in your Verilog code to specify the logic feeding the flip flops Note that the one hot code enables you to derive these expressions by inspection Use the toggle switch SWo on the Altera DE2 board as an active low synchronous reset input for the FSM use SW as the w input and the pushbutton KEY as the clock input which is applied manually Use the green LED LEDG as the output z and assign the state flip flop outputs to the red LEDs LEDR g to LEDRo Include the Verilog file in your project and assign the pins on the FPGA to connect to the switches and the LEDs as indicated in the User Manual for the DE2 board Compile the circuit Simulate the behavior of your circuit Once you are confident that the circuit works properly as a result of your simulation download the circuit into the FPGA chip Test the functionality of your design by applying the input sequences and observing the output LEDs Make sure that the FSM properly transitions between states as displayed on the red LEDs and that it produces the correct output values on LEDG 9 Finally consider a modification of the one hot code given in Table 1 When an FSM is going to be im plemented in an FPGA the circuit can often be simplified

Laboratory Exercise 7

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