User Manual
Contents
1. X P 44 45 JTAG S 46 DAUGHTER CARD HEADERS ueeeeeesssssssssnnnssnnnnnnnnsnsnnnnnnnnnnnsnnnnnnssnnnnnnnnsnnnnnnnnnnsssnnnnnnnnsssnnnnnnnssssnssssssnssnnnnnnsssssssssssssssnnnnnnssssssssssssssnsnnnnsssssssssssnen 47 DO 47 Da ght er Card Header 47 FPGA to Daughter Card Header IO Connections TT Tete 49 OR 54 Insertion Removal of Daughter Card aA 55 MEU 73373333 56 MECHANIC PR 244442224454 0 0 0 0 0 0 0 0 0 0 0 0 0 010042442220 57 57 58 APPENDIX A UCE ee 58 APPENDIX B USING A THIRD PARTY ARM DEBUGGER u nennen 58 List of Figures Figure 1 DNMEG ARM TILE REV2 Daughter Card EEE 1 Figure 2 DNMEG ARM STIER RE V2 Daughter Card Block etta ana 20 clave BOCE DII N u ae 23 Pique el JTAG 46 Pique ICE TE Gi O Om ee CHE 46 Figure 6 Daughter Card Header Pin Assignments List of Tables AddINOnal 4 Table 2 ans2. 8 Ta TPO ir 24 Table 4 Connections for Daughter Header COCKS ua anna tn einander 2 FAI Dealer COR EC 25 ADI AS ono RS resa ae ee de ne 35 Table 7 General Purpose u u u nan Ri 35 oe gh de M M 37 Tale Oe us C lt 1 O NE DI CAD se ae 38 Table TOS PO Wer Supply Staus an 39 PE SR COR HERE EE 39 D RAM ee 41 SCOR 43 Table 14 PS 2 ConnectionS ee ee 44 e EE NEC TE a es te a ee 44 dobles m E NS 45 Table 17 Connections between FPG A and the RS232 dd dis dite dt dE 45 Table 18 Daughter Card Header IO Connections sense 49 IDO RST 54 INTRODUCTION Chapter Introduction T his U sx Manual anompanistheDNMEG ARM TILE REV 2 D auchter Card For speaticinformation raprdingtheSpartan part please rdermethedatashet on theX ilinx website 1 Ab
3. 13 PROGRAMMING CONEIGURING THE HARDWARE 02a ex vox e aeu vox ez ex xav enc ex eae exec exces exaeescex cease 14 6 INTRODUCTION ER 14 7 CONFIGURATION 14 7 1 Conn eurin ehe 15 7 1 1 15 7 1 2 Conn sunne Me PRGA eee a un EEEE 15 7 2 Configuring 16 7 2 1 SP 17 1212 17 HARDWARE DESCRIPTION aa 19 8 OVERVIEW U en een a 19 9 XILINX SPARTAN 21 10 184217414 E B A POAN 21 10 1 SORAM EE 21 10 2 22 10 3 22 10 4 ACD AND MEME 777777777777 22 10 5 Ethernet PHY 10 100 1000base T not available with DN7020k10 or DN9000k10 ss 22 11 22 11 1 sea 22 11 2 Daughter Card 23 11 2 1 Connections between the FPGA and the Daughter Card Header Clocks ss 25 12 ARM HEADERS M 25 13 35 14 14 1 14 2 14 3 15 15 1 15 2 15 3 16 18 19 20 204 20 2 20 3 20 4 20 5 20 6 21 21 1 APPENDIX 22 23 37 37 38 POWOFSUHDDD SOLS Bi D S e dA AU UAR ARUM UM UU UAM ud 38 MEMORY 39 39 41 FLASH 43 PS 2 KEYBOAR DAND 44
4. BRU 3 2 302 x H Boundary Scan 38 SlaveSerial SelectMAP e Ba Desktop Configuration TDI E SystemACE xcf32p xc3s5000 dnmedg arm tilemmcs dnmeg_arm_tile bit TDO gt Boundary Scan 1 Loading file C dnmks dn fpgacode DNMEG ARM TILE Source build implement reference dr done INFO iMPACT 1835 Loading CFI file C dnmks dn fpgacode DNMEG ARM TILE Source build imple CFI file not found proceed with device default setting INFO iMPACT 1835 Loading CFI file C dnmks dn fpgacode DNMEG ARM TILE Source build imple CFI file not found proceed with device default setting 2 Loading file C dnmks dn fpgacode DNMEG ARM TILE Source build implement loopback dnr done INFO iMPACT 1777 Reading C Xilinx 10 1 ISE spartan3 data xc3s5000 bsd INFO iMPacT 2257 Startup Clock has been changed to JtagClk in the bitstream stored in but the original bitstream file remains unchanged INFO 1 501 Z Added Device xc3s5000 successfully ce DR Ne ON SEES SE DE TEEN SEE EN E ES BE EN STEEP awi Output A Error warina No Cable Connection No File Open 2 3 Right click on the XCF32P device and select Program Process Dialog box will indicate programming progress 4 Power cycle the DNMEG ARM TILE REV2 Daughter Card or hit Reset Button S4 and verify that the FPGA DONE blue LED D S7 is enabled indicating successful
5. 20 EN L8N L9N N 21 B1 B1 B1 B1 L11P L12P L29P L29N L13P 1 22 L1 N a EN ir 22 L12N B1 B1 B1 B1 L16P L30P L30N L17P 1 B1 B L15N L16N L17N B1 B1 B1 B1 25 L19P L20P L31P L31N L21P 1 1 26 LION 20 2 L20N L21N B1 B2 B2 B1 L24P L25P L25N L25P 1 B1 B L23N L24N L25N B2 B2 B2 B2 L2P L26P L26N L3P 2 B2 B L2N L3N B2 B2 B2 B2 L6P L27P L27N L7P 2 B2 B 2 PL 2 NO N 9 OD N O0 Co n2 co EJ C2 O To zm B2 30 3 32 LSN LEN 32 L6N N B2 B2 B2 B2 33 L9P L10P L28P L28N L11P 2 L7N E d i L1 N 34 L10N L11N B2 B2 B2 B2 L14P L29P L29N L15P 35 2 B2 a LSN 36 L14N aT 37 2 2 3 8 LUN 7 er 38 L18N 39 2 40 Lain 23 24 40 A C E F 3 A C E N UJ O LE Figure 6 Daughter Card Header Pin Assignments DNMEG ARM User Manual www dinigroup com 48 HARDWARE DESCRIPTION 20 3 FPGA to Daughter Card Header IO Connections Most connections to the Daughter Card Header come from the ARM X Header which carries the signals for the AHB bus The intention in the design was to provide direct access to the ARM Core Tile from a host board not needing to route through an intermediary FPGA While this is completely achieved the Spartan is still necessary
6. DNMEG ARM_TILE User Manual www dinigroup com 58
7. Table 8 General Purpose Headers DNMEG ARM User Manual www dinigroup com 35 HARDWARE DESCRIPTION Signal Name FPGA Pin DNMEG ARM User Manual www dinigroup com 36 HARDWARE DESCRIPTION 14 LED Indicators The DNMEG ARM TILE REV provides various LED s to indicate that status of the board 14 1 User LED s 32 green LED s are provided to the user as a design aid during debugging The LED s can be turned ON by driving the corresponding pin LOW Table 9 describes the user LED s and their associated pin assignments on the FPGA 07 Table 9 User LED s DNMEG ARM TILE User Manual www dinigroup com 37 HARDWARE DESCRIPTION 14 2 Configuration DONE LED After the FPGA has received all the configuration data successfully it releases the DONE pin which is pulled high by a pull up resistor A low to high transition on the DONE indicates configuration is complete and initialization of the device can begin DONE pin drives aNFET and tums ON the blue LED DS17 when the DONE pin goes high Table 10 describes the DONE LED and its associated pin assignment on the FPGA U21 Table 10 FPGA DONE LED Signal Name FPGA Pin LED FPGA DONE UTA 14 3 Power Supply Status LED s LED s are provided to indicate the presence of various power supplies The power monitors U15 U16 monitor the P12VD P3 3VD P3 0VD P2 5VD and P1 2VD voltage levels and signals an under voltage condition by pulling FP
8. CD ROM containing o Spartan Reference D esign Verilog DNMEG ARM TILE User Manual www dinigroup com 3 INTRODUCTION User Manual pdf format Schematic pdf format o Component D atasheets pdf format Optional items that support development efforts not provided U Xilinx ISE software and X ilinx Platform Cable USB download cable ARM debugging cable emulator JTAG 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Table 1 Additional Information Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions MEG D aughter Card header insertion and removal video Videos Dini Group The web page will contain the latest user manual application notes Web Site FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Spartan 3 User Pages from Spartan 3 User Guide which contains device specific Guide information on Xilinx device characteristics ARM Core Tile Information about the
9. 27 P1 D28 1 27 P1 D30 P1 C29 P1 F39 1 39 7 1 7 P1 F9 P1 E9 1 DC 280129 1 11 DC zBOL30N RX P1 F13 DC 2 0130 ETHB TXD3 P1 E13 DNMEG ARM User Manual www dinigroup com 53 HARDWARE DESCRIPTION 20 4 Power and Reset The 3 3V 5V and 12V power rails are supplied to the DNMEG ARM TILE REV2 Daughter Card Headers from the host D ini Card e g DN9000K 10 Each pin on the MEG Array connector is rated to tolerate 1A of current without thermal overload Each power rail supplied from the D aughter Card Header is fused to prevent damage from overload The preferred power source is the ATX connector J5 and not the power pins on the MEG Array The DC RST signal is pulled up on the DNMEG ARM TILE REV2 D aughter Card The signal is also routed to the FPGA U7 and can be used as a reset to the logic refer to T able 20 Table 20 Daughter Card Reset Signal RST Signal N ame FPGA DC RSI N U7 V2 DNMEG ARM TILE User Manual www dinigroup com 54 HARDWARE DESCRIPTION 20 5 Insertion Removal of Daughter Card Due to the high density MEG Array connectors the pins on the plug and receptacle of the MEG Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the ME G A r
10. L X 1 X X_helkin_up x X Y Y CLK_FPGA_DC_P CLK_FPGA_DC_N hz 100M Divide in FPGA to requency T 70 Q D TI LK FPGA OSC LK FPGA OSC P C C 100 Mhz Oscillator CLK Resistor links ER connect either v buffer default or header clocks CLK FPGA FBOU Fanout Buffer Figure 3 Clocking Block Diagram T he clocking structures for DNMEG ARM TILE REV2 include the following features 100 MHz Oscillator X 1 LVDS Fanout Buffer U6 for system synchronous operation between host board and DNMEG ARM TILE REV2 Support for both delay matched and retimed clocks to from the ARM Core Tile ARM Core Tile G lobal Clock support Ability to clock AHB standalone from DNMEG ARM TILE REV2 w host board attached or from host board DNMEG ARM User Manual www dinigroup com 23 HARDWARE DESCRIPTION The connections between the FPGA and various clocking resources are documented in Table 4 Table 4 FPGA Clocking Signal Name FPGA Pin CLK FPGA OSC P U7 AH15 100 MHz from the Oscillator CLK FPGA OSC N U7 AJ15 100 MHz from the Oscillator Output to clock buffer for CLK FPGA FBOUT U7 AF15 system synchronous operation Input from system synchronous CLK FPGA FBIN P U7 B16 clock buffer Input from system synchronous CLK FPGA FBIN N U7 C16 clock buffer Output to ARM for use as AHB
11. ug og o E 0 mmmn 50 He ou E 40 lt E FL 30 F z DIKDA Pe 25 10 ee x i T lt al EE ec Oe xe X Um e g DNMEG ARM TILE User Manual www dinigroup com 57 APPENDIX Chapter Appendix 22 Appendix A UCF File See the CUSTOMER CD for the Xilinx Universal Constraint File UCF file 23 Appendix B Using a Third Party ARM Debugger ARM debuggers are extremely useful for the development of ARM applications and the DNMEG ARM TILE REV2 supports a wide range of third party debuggers through the DEBUG JTAG interface see section 19 To successfully use such a debugger the DEBUG path must be present and enabled Make sure the following signals are configured correctly T XHEADER XHEADER DBGEN 24 HIGH Enable debugging on ARM Chip Enable debugging on ARM Chip ARM Chip ZHEADER EN LN LA Disable CONFIG JT AG path Enable DEBUG JTAG path ZHEADER RTCKEN N U7 LOW Enable RTCK on DEBUG interface Also consider the speed of the JTAG clock Please consult the documentation for your ARM Test Chip and your debugger interface for specific timings and compatibility as a rule of thumb lower JTAG clock speeds are preferred for best compatibility Testing has shown the DEBUG interface to run reliably at 3MHz
12. GPIO are also connected to the FPGA and HDRY Additional memory expansion via PISMO is enabled to the CoreTile via HDRZ The Spartan 3 FPGA also connects to all signals on this header The DNMEG ARM TILE REV2 provides the proper connector for the variety of ARM in circuit emulators ICE and debug equipment via ARM ICE debug port 9 Xilinx Spartan 3 FPGA On the DNMEG ARM TILE REV2 the AHB bus from the ARM processor is connected to a Xilinx Spartan 3 FPGA The standard stuffing options is the 3S5000 4 All resources of this Xilinx FPGA are available to the user application This is a fairly large FPGA containing 66 560 FF LUT pairs and 240kbytes of block RAM By a conservative measure this FPGA alone can prototype 560k ASIC gates excluding memory and multipliers This ASIC gate number can be increased in the short term to as much as 50M ASIC gates via a DN7020k10 When Altera releases the Stratix 4 family this number will increase to gt 100M gates 10 Penpherals The intention of the DNMEG ARM TILE REV2 is to provide AHB interfaces to useful peripherals common to most designs Verilog source is provided for each of the interfaces and allows the interface to be mapped into ARM address space for use by the processor on the Core Tile 10 1 SDRAM PC100 PC 133 Two Micron synchronous D RAMS MT48LC16M 16A 2 are connected to the FPGA in a 16M x 32 configuration These SDRAMS are PC100 PC133 compliant DNMEG ARM TILE User Manual ww
13. JTAG FPGA 4 L Fr 1 FPGA Figure 2 DNMEG ARM TILE REV2 Daughter Card Block Diagram ARM supplies a circuit board with a processor test chip that has an ARM9 or ARM11 within ARM calls this product a RealView Coretile The DNMEG ARM TILE REV 2 is an intermediate host for a CoreTile adding the features and interfaces needed to make the ARM processor on the CoreTile useful for prototyping The combination of the DNMEG ARM TILE REV 2 with the CoreTile is mounted on DNMEG ARM User Manual www dinigroup com 20 HARDWARE DESCRIPTION an ASIC FPGA board from The DINI Group enabling full speed system prototyping and debug of high gate count ARM based systems With a separate power supply the DNMEG ARM TILE REV2 CoreTile combo can be used stand alone The CoreTile for 926 5 for example contains an ARM926EJ S processor inside a test chip The ARM9 processor s configuration signals and a multiplexed AHB bus are connected to the board s headers HD RX This CoreTile is mounted onto the DNMEG ARM TILE REV2 which is in tum mounted onto any of the ASIC prototyping boards available from theDINI Group The AHB bus from HD RX is connected to the Spartan 3 FPGA and the 400 pin Array expansion header Memory expansion via PISMO is enabled to the CoreTile via HD RY The Spartan 3 FPGA connects to most signals on this connector User controllable LEDs 32 in total and 20 general purpose I Os
14. both the Core Tile and the DNMEG ARM TILE REV2 please read the section on Core Tile preparation before mating the cards Daughter Card Test Headers Over Voltage The 400 pin daughter card test headers are NOT 5V tolerant Take care when handling the board to avoid touching the components and daughter card connections due to ESD ESD Waming The board is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 cfm DNMEG ARM TILE User Manual www dinigroup com 6 GETTING STARTED Operating Temperature Avoid touching the PTH012050WAZ power supply modules PSU1 PSU2 PSU3 505 PSU6 as they operate at high temperatures and may cause skin burns 2 Preparing the ARM Core Tile 2 1 Why is this Necessary The ARM core tile has many different stuffing options and must be customized to fit a specific application Our primary concem is the power connections that are by default installed on the tile R25 and R182 connect PVD DIO AHB signal voltage on the Core Tile to 3 3V we want to use our selectable on board voltage of 2 5V or 3 0V to comply with the electrical limits of modem FPGAs R24 and R183 connect PCCOY expandable memory voltag
15. text in the command window should move to the buffer window as the text scrolls past the top line in the command window However the text may appear in the buffer window with missing characters or extra characters See Microsoft Help and Support article ID 274261 5 3 Running the Reference Design Once the board powers on it will load the bitfile stored in the Xilinx PRO M and come out of reset The attached ARM Core Tile will begin to execute the code stored in the FLASH ontheDNMEG ARM TILE REV2 When shipped the code in the FLASH will toggle the LEDs on the DNMEG ARM TILE REV2 If desired AHB transactions can be initiated over RS232 by sending command files See the reference design READ ME for further details In order to execute code from the FLASH some configuration signals must be set in a certain way described as follows DNMEG ARM TILE User Manual www dinigroup com 12 GETTING STARTED Table 3 Reference Design Configuration Signals SignalName Pm Switch State Signal State XHEADER BIGENDIN HIGH XHEADER INITRAM XHEADER VINITHI 5 4 Running the Loopback Design Power Up the DNMEG ARM TILE REV2 Daughter Card and program the Spartan FPGA with the loopback bitfile See the section on programming the Spartan FPGA for further detail Open a Hyperterminal Window and view the output of the design The loopback design will run read write tests on SRAM DRAM AHB headers and Meg Array headers It will also echo RS23
16. to drive some setup signals for correct ARM execution The Ethemet connection on theDNMEG ARM TILE REV2 is only available if the host board is connected these signals are routed directly to the Meg Array connector Table 19 Daughter Card Header IO Connections Daughter Card DC SIGNAL SIGNAL Receptacle DNMEG ARM User Manual www dinigroup com 49 HARDWARE DESCRIPTION Daughter Card DC SIGNAL SIGNAL Receptacle DNMEG ARM User Manual www dinigroup com 50 HARDWARE DESCRIPTION Daughter Card DC SIGNAL SIGNAL Receptacle DNMEG ARM User Manual www dinigroup com 51 HARDWARE DESCRIPTION Daughter Card DC SIGNAL SIGNAL Receptacle DNMEG ARM User Manual www dinigroup com 52 HARDWARE DESCRIPTION Daughter Card DC SIGNAL SIGNAL Receptacle DC xBOLSN VREF P1 B6 DC xBOL5P HOST SPARTAN 1 28 PLAS DC xBOL6N HOST SPARTAN P1 D6 DC xBOL6P DC xBOL7N DC xBOL7P DC xBOL8N VREF DC DC xBOL9N VREF DC xBOLOP DC 1111 VREF DC xB1L11P DC 15 CC DC xB1LI5P CC DC xBlL16N DC xB1L16P DC xB1LI9N CC DC xB1LI9P CC DC xB1L20N DC xB1L20P DC xB1L23N DC xB1L23P DC xB1L24N DC xB1L24P DC xB2L2N DC xB2L2P DC xzrB2L31N DC xzrB2L31P DC zBOL27N DC zB0L27P DC zBOL28N DC zBOL28P DC zBOL29N 1 1 06 1 5 P1J6 PLKS 1 8 PLAT 1 822 1 21 1 824 1 23 1 024 P1 C23 P1 B26 1 25 P1 D26 1 25 1 828 1
17. 0000000000 0 0 000 00 0 0 etas 1 2 3 PACKAGE CONTENT S hihi NETTE 3 4 INSPECT THE BOARD 4 5 ADDITIONAL INFORMATION cccscccccccccccesssssssssscceececccceeeesesssssseeeeeccceceeeesssnsnsaeeeeececceeesessessaeeeeeeeceeesessessssseeeeeececeeeseeesaaaeeeeseceeceeeeeeeeaaaeeeeeeeeeeeeeses 4 GEEIINGS EEE 6 1 BEFORE er a Eee EEE 6 1 1 ON ON CII 6 1 2 Warin cn A 2 PREPARING THE ARM CORE 7 2 4 Why is this Necessary n n nan r 7 2 2 ET ORE SUSE cu EMI 7 3 PREPARING THE DINMEG ARM EIBE QRSE V2 AIIAN 8 3 1 8 4 MATING THE DNMEG ARM TILE REV2 WITH THE ARM CORE 9 4 1 audi 9 4 2 Fres S DOWN 2 10 5 USING THE REFERENCE DESIGN 10 5 1 Initial Setup before Applying 10 5 2 GOM Setup usine Hyperterminal 11 5 3 k na me BY OIE TT 12 5 4 qhe TICS ON ARENA E 13 2 3 ROSOHTITO a o DO
18. 2 input and PS 2 Mouse input to the RS232 terminal and detect when an ARM Core Tile is attached Because loopback cables are not provided for the AHB headers and Meg Array header errors for these tests will occur This is a diagnostic test only for testing interfaces to the DNMEG ARM TILE REV2 peripherals 5 5 Resetting a Design Once a design is loaded there are several ways to reset the design If running standalone mode reloading the design with iMPACT is an easy way to do so The reset button S4 is a hard reset and will cause the FPGA to reload from the PROM If running attached to a host board the reset sent across the MEG Array connector be used as a soft reset meaning that it will reset the logic of the FPGA without reconfiguring it DNMEG ARM User Manual www dinigroup com 13 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configunng the Hardware T his chapter details the programming and configuration instructions for the DNMEG ARM TILE REV 2 D aughter C ard 6 Introduction Spartan 3 devices are configured by loading application specific configuration data the bitstream into intemal memory Because Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up T he bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration m
19. ARM Core Tile found here D atasheet http www arm com miscPD Fs 7843 pdf AMBA AHB A description of the signals on the AHB bus found here Specification http www arm com products solutions AMBA Spec html DNMEG ARM User Manual www dinigroup com 4 INTRODUCTION Description URL E Mail Y ou may direct questions and feedback to the Dini Group using this email address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 10 00am to 5 00pm Pacific Time The download section of the web page may contain a document called DNMEG ARM TILE REV2 Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the Users Manual DNMEG ARM User Manual www dinigroup com 5 GETTING STARTED Chapter Getting Started Congratulations on your purchase of the DNMEG ARM TILE REV 2 Daughter Card The remainder of this chapter describes how to start using the board 1 Before You Begin 1 1 Configuring the Programmable Components The DNMEG ARM TILE REV2 Daughter Card has been factory tested and pre programmed to ensure correct operation The user does not need to alter any jumpers or program anything to see the board work 1 2 Warnings Connecting to the ARM Core Tile There are many different build options for the Core Tile some of which involve resistor links between voltage sources In order to prevent electrical damage to
20. GA PROG N DNMEG ARM User Manual www dinigroup com 38 HARDWARE DESCRIPTION signal low The status of this signal is indicated by D 519 Table 11 describes the power supply status LED s and their associated voltage source Table 11 Power Supply Status LED s SignalName Some P12VD 15 1 P5VD P33VD PSU56 P25VD PSU26 PVDDIO 142 PSU1 6 or PSU3 6 FPGA_PROG_N U154 U164 D 519 15 Memory 15 1 SRAM The 32 bit wide SRAM has the following connections to the Spartan FPGA The SRAM shares its address and data bus with the FLASH this requires that transactions to the SRAM and FLASH be mutually exclusive Some address bits may not be used on the SRAM check stuffing options for actual address width Signal descriptions and functionality can be found in the datasheet distributed with this document Table 12 SRAM Connections DNMEG ARM User Manual www dinigroup com 39 HARDWARE DESCRIPTION DNMEG ARM User Manual www dinigroup com 40 HARDWARE DESCRIPTION 15 2 DRAM TheDNMEG ARM TILE REV2 uses two 16 bit wide DRAM chips in parallel to create a 32 bit wide D RAM interface The connections to the D RAM are listed below Some address bits may not be used on the D RAM check stuffing options for actual address width Signal descriptions and functionality can be found in the datasheet distributed with this document Table 13 DRAM Connections DNMEG ARM User Manual www din
21. NMEG ARM TILE REV 2 peripherals excluding AHB communication Extra test cables are required and not included to test AHB and Meg Array headers 5 1 Initial Setup before Applying Power Attach the ATX Power Supply to the power header 5 on the DNMEG ARM TILE REV2 Daughter Card Connect the Xilinx Platform Cable USB from the Test PC to the JTAG header J16 Connect the serial cable from the Test PC to the RS232 header J26 Ensure that pin 1 location of the cable aligns with pin 1 location on the PCB DNMEG ARM_TILE User Manual www dinigroup com 10 XILINX Platform Cable USB Model DLC9G Power 5V 0 07 Serial UHG 19298 Made in USA x 183831 fair i 11 1 gure com ITT TT TU U 2 E B B a a 4 GETTING STARTED rou TILE REV2 Daughter Card Conf www d Connect the RS232 Serial cable to a COM port on the host computer and the RS232 on the DNMEG ARM 5 2 Serial COM Setup using Hyperterminal Hyperterminal to the following settings DNMEG ARM User Manual header 26 GETTING STARTED Fort Settings Bits per second 19200 Data bits E Parity None Stop bits 1 Flow control RTE Restore Defaults cad Warning The text in the buffer window the window above the command window may appear to be corrupted The
22. THE DINIGROUP LOGIC Emulation Source User Manual DNMEG ARM TILE REV2 LOGIC EMULATION SOURCE DNMEG ARM TILE REV2 User Manual Veersion 2 0 Date of Print April 23 2010 a The Dini Group 7469 Draper Avenue La Jolla CA 92037 Phone 858 454 3419 Fax 858 454 1279 support dinigroup com Www dinigroup com Copyright N otice and Proprietary Information Copyright 2010 The Dini Group All rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of The Dini Group Right to Copy Documentation The Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer The Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However The Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents INTRODUCTION eer C C C 1 1 ABOUT THE ENMEC ARNE TIEE DAUGHTER CARD 1 2 DNMEG_ARM_TILE REV2 DAUGHTER CARD FEATURES 01 2 200 0404 0000000
23. XHEADER HWRITE U7 W5 XHEADER IRQ N U7 W8 XHEADER PLLLOCK U7Y1 XHEADER REFCLK UP U7 L4 XHEADER RESET N U7 Y2 XHEADER PLLFBDIVO U7 B27 XHEADER PLLFBDIVI U7 A27 XHEADER PLLFBDIV2 U7 C27 XHEADER PLLFBDIV3 U7 D 26 XHEADER PLLFBDIVA U7 B26 DNMEG ARM User Manual www dinigroup com 28 HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 29 HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 30 HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 3l HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 32 HARDWARE DESCRIPTION Signal Name DNMEG ARM User Manual www dinigroup com 33 HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 34 HARDWARE DESCRIPTION Signal Name FPGA Pin ZHEADER SYSRST N U7 E25 In addition several static signals are attached to DIP Switches 51 and 52 When the switches are in the OFF position the signals will be HIGH Tuming the switches ON results in making the signals LOW Table 7 Signals 51 and 52 Signal Name XHEADER BIGENDIN 13 General Purpose Headers The FPGA LED and FPGA GPIO busses serve as general purpose communication the FPGA LED bus having the added bonus of being connected to LEDs These busses are connected to the Spartan FPGA the ARM Z Header and surface mount headers for extemal interfacing
24. XHEADER REFCLK UP U7 L4 helk input on selected Core Tiles Output to ARM for use as AHB XHEADER HCLKIN UP U7 L3 helk input on selected Core Tiles XHEADER HCLK DN U7 A15 Input for clocking AHB interface Output to ARM for use as AHB ZHEADER CLK GLOBAL U7 B15 hclk input on selected Core Tiles Retimed clock see ARM Core ZHEADER CLK POS DN IN U7 AK16 Tile documentation Retimed clock see ARM Core ZHEADER CLK NEG DN IN U7 AJ16 Tile documentation Retimed clock see ARM Core ZHEADER CLK POS UP OUT U7J22 Tile documentation Retimed clock see ARM Core ZHEADER CLK NEG UP OUT U7 H22 Tile documentation D elay matched clock see ARM ZHEADER CLK OUT PLUSI U7 F22 Core Tile documentation D elay matched clock see ARM ZHEADER CLK OUT PLUS U7 E22 Core Tile documentation D elay matched clock see ARM ZHEADER CLK IN PLUSI U7 B16 Core Tile documentation D elay matched clock see ARM ZHEADER CLK IN PLUS U7 C16 Core Tile documentation DNMEG ARM User Manual www dinigroup com 24 HARDWARE DESCRIPTION 11 2 Daughter Card Clocks The 400 pin MEG Array connector on the bottom of the PCBA is used to interface to the D ini Group products e g DN7002k10MEG 11 2 1 Connections between the FPGA and the Daughter Card Header Clocks The connections between the FPGA and the D aughter Card Header Clocks are shown in Table 5 Table 5 Connections for D aughter Card Header Clocks Signal Name XHEADER HCLK DN 25V P1E1 nput for clocki
25. ading file C dnmks dn fpgacode DNMEG ARM TILE Source build implement reference dra done INFO iMPACT 1835 Loading CFI file C dnmks dn fpgacode DNMEG ARM TILE Source build imple CFI file not found proceed with device default setting INFO iMPACT 1835 Loading CFI file C dnmks dn fpgacode DNMEG ARM TILE Source build imple CFI file not found proceed with device default setting 2 Loading file C dnmks dn fpgacode DNMEG ARM TILE Source build implement loopback dnr done INFO iMPACT 1777 Reading C Xilinx 10 1 ISE spartan3 data xc3s5000 bsd INFO iMPACT Z257 Startup Clock has been changed to JtagClk in the bitstream stored in but the original bitstream file remains unchanged INFO 1 501 2 Added Device xc3s5000 successfully Im Output A Error Warning No Cable Connection No File Open 2 3 Right click on the FPGA and select the Program option A Progress Dialog box will appear indicating programming progress 4 The activation of the CFG DONE blue LED 057 indicates that the FPGA configured successfully 7 2 Configuring the FPGA using Xilinx PROM The Master Serial mode is designed so that the FPGA can be configured from a Xilinx Flash PROM The DNMEG ARM TILE REV2 Daughter Card is populated with an X CF32P 32Mbit Flash PROM DNMEG ARM User Manual www dinigroup com 16 PROGRAMMING CONFIGURING THE HARDWARE 7 2 1 Setup Before configuring t
26. are routed as differential 50 O hm transmission lines No length matching is done on the PCB for Daughter Card signals except within a differential pair because the Virtex 5 is capable of variable delay input using the built in Input Output Delay Element IODELAY capabilities Other connections on the daughter card connector system include three dedicated differential clock connections for inputting global clocks from an extemal source power connections bank Veco power and a reset signal 20 1 Daughter Card clocking Refer to the Clocking Chapter in this User Manual 20 2 Daughter Card Header Pin Assignments The pin assignments of the DNMEG ARM TILE REV2 Daughter Card Headers were designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 5 LVDS standards The D aughter Card Header is divided into three banks refer to the following figure DNMEG ARM TILE User Manual www dinigroup com 47 HARDWARE DESCRIPTION gt UJ 3 3V BO BO BO BO BO BO B B BO BO BO 3 3V ow zo Ed L6N L8N L5N BO BO BO BO BO L9P L10P L27P L27N L12P N BO B L10N L12 BO BO BO L14P L28P L28N LIAN LISN 10 11 gt Bo 11 12 so Bo 12 13 14 9 Bo 14 15 15 16 5 f 16 55 ON OOF ON OOF ND oO am gt 9 L26N BEN 17 x AH KE N L4N Si 19 LION 20 1 8 L3N co Ed EE Ed
27. configuration of the FPGA DNMEG ARM User Manual www dinigroup com 18 HARDWARE DESCRIPTION CI Hardware Description T his chapter dembethelundional blocks of the desion and focuses on the Hardware 8 Overview The DNMEG ARM TILE REV2 Daughter Card provides for a comprehensive collection of peripherals to use in creating a system around the Xilinx Spartan 3 FPGA A high level block diagram of the DNMEG ARM TILE REV2 Daughter Card is shown in Figure 2 followed by a brief description of each section DNMEG ARM_TILE www dinigroup com 19 HARDWARE DESCRIPTION Block Diagram 7 Config RS232 Expansion JTAG gt HDRY Y Memory 103 0 4 Cntl 7 PISMO 32 v1 FPGA_LED Yo 20 32 64 MBIT Y 169 150 PFOA GER 49BV320D 2M x 16 CPLD Xilinx XC9572 pts power clocks n NS Spartan 3 board ID etc SSR ARM7 ARM9 ARM 11 HDRX Clocks Misc control HADDRI31 0 32 CD Audio ARM HWDATA 31 0 1 0 Test Line Out Chip genom amp gt phone eus convo 29 3 FA l 31 Mouse a 3 gr ARM Coretile i 3 Keyboard DN9000 amp DN7000 Series ASIC Prototyping Boards to 50M gates E ur 10 100 1000 base T Fig SET Sp Ethernet Tagen LPSC unt ir i
28. create a new default project Select Configure devices using Boundary Scan JT AG from the IMPACT welcome menu IMPACT Welcome to IMPACT Please select action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identity Boundary S can chain O Prepare a PROM File Prepare a System ACE File Prepare Boundary Scan File Configure devices using Slave Serial mode Cancel DNMEG_ARM_TILE User Manual www dinigroup com 15 PROGRAMMING CONFIGURING THE HARDWARE 2 IMPACT will identify the PRO M XCF32P and the FPGA X C3S5000 in the JTAG chain A pop up window will display Assign N ew Configuration File Click Bypass and specify the location for the FPGA bit file Select D evice 2 in the Device Programming Properties window and click to continue 5 iMPACT C default ipf Boundary Scan D x L File Edit View Operations Output Debug Window Help Xoxe xu 22 302 x 2 Scan 9 38 SelectMAP Desktop Configuration 22 SPI Configuration B B SystemACE i xcf32p 385000 B PROM File Formatter file dnmeg_arm_tile bit Available Operations are ep Program Get Device ID b Get Device Signature Usercode Check Ideode perations 4 Boundary Scan 1 Lo
29. e to 3 3V we want to select from a variety of voltage ranges on the DNMEG ARM TILE REV2 for compliance with a wider range of memory modules 2 2 Removing Resistors R25 R182 R24 and R183 need to be removed from the ARM Core Tile Locations of these resistors are indicated below 5 8 a i mr fad 8 08 5 gt 24170901909 5 m A La 4 r jo ewm mem SF end 1 So wh m I r z P DNMEG ARM User Manual www dinigroup com 7 GETTING STARTED 3 Preparing the DNMEG ARM TILE REV2 3 1 Power Options umper Settings The preferred method for powering the DNMEG ARM TILE REV2 is through the ATX power connector J5 Jumper settings are available to power board using a host board s supply through the Meg Array connector Jumpers are also available to change the voltage for the AHB and Memory Expansion signals to the Core Tile Jumpers will installed at the factory before shipping only change these settings if necessary Table 2 Jumper Settings Install Jumper on pins 2 3 to use 5V power from the connector Install on pins 1 2 to use 5V power from the Meg Install Jumper on pins 2 3 to use 12V power from the ATX connector Install on pins 1 2 to use 12V power from the Meg Leave all jumpers uninstalled for 1 2V Memory Expansion Install jumper on pins 2 4 for 1 5V Install ju
30. he FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the Power header J31 on the DNMEG ARM TILE REV2 Daughter Card 2 Connect the Xilinx Platform Cable USB to the JTAG header 2 3 Power up the board by tuming ON the ATX power supply and verify that the Power LED s D S2 D 56 are ON indicating adequate power supply 7 2 2 Configuring the FPGA To configure the Xilinx Flash PRO M perform the following steps 1 OpeniMPACT and create a new default project Select Configure devices using Boundary Scan JTAG from the IMPACT welcome menu IMPACT Welcome to IMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Eoundary 5 can chain C5 Prepare a PROM File C3 Prepare a System ACE File Prepare a Boundary Scan File Configure devices using Slave Serial mode 2 IMPACT will identify the XCF32P and the FPGA X C3S5000 in the JTAG chain A pop up window will display Assign N ew Configuration File Specify the PRO M file location DNMEG ARM User Manual www dinigroup com 17 PROGRAMMING CONFIGURING THE HARDWARE Select Bypass forthe FPGA and click O K in the D evice Programming Properties window to continue 8 iMPACT C default ipf Boundary Scan i nmi x File Edit View Operations Output Debug Window Help 5 x
31. igroup com 41 HARDWARE DESCRIPTION DNMEG ARM User Manual www dinigroup com 42 HARDWARE DESCRIPTION Signal Name FPGA Pin DRAM WE N U7 AB19 15 3 FLASH The FLASH w 16 bit wide data has the following connections to the Spartan FPGA The FLASH can be given a 32 bit wide interface in RTL requiring multiple reads writes per transaction The FLASH shares its address and data bus with the SRAM this requires that transactions to the SRAM and FLASH be mutually exclusive Some address bits may not be used on the FLASH check stuffing options for actual address width Signal descriptions and functionality can be found in the datasheet distributed with this document Table 14 FLASH Connections Signal N ame FPGA Pin DNMEG ARM TILE User Manual www dinigroup com 43 HARDWARE DESCRIPTION 16 PS 2 Keyboard and Mouse The PS 2 interface consists of a bidirectional clock and a single bidirectional data signal Please see the Schematic Errata for the actual circuit used in production The signal connections are listed below Table 15 PY 2 Connections Signal Name FPGA Pin KEYBOARD CK U7 AG 24 KEYBOARD TX 07 24 MOUSE U7 AA16 MOUSE TX U7 AA18 17AC97 The on board AC97 SoundMAX Codec has two 3 5mm audio jacks 729 and J30 for input output to the chip There are also multiple testpoints that can be connected manually by the user to an external source for inputs outputs to the chip other than those
32. mper on pins 3 4 for 1 8V Install jumper on pins 4 6 for 2 5V Install jumpers on pins 4 6 7 8 for 3 3V DNMEG ARM TILE User Manual www dinigroup com 8 GETTING STARTED 211 4 Mating the DNMEG ARM TILE REV2 with the ARM Core Tile 4 1 Aligning the Headers Begin by resting the far edge of the two horizontal headers on the ARM Core Tile on headers J7 and 14 DNMEG ARM TILE REV2 d i mpm While keeping the far edge aligned allow the ARM Core Tile to lay flat on top of the DNMEG ARM TILE REV2 The headers should be aligned DNMEG ARM TILE User Manual www dinigroup com 9 GETTING STARTED Pass De 1 gt LY d 4 X IT 1 4 4 D p mar u z Bh gt WE pA sa a vd SE as 4 7 a n 3333 9 i E sv q po w pr s w 2N oh tek 4 4 2 Press Down Firmly Press down firmly on each of the three ARM headers Especially when dealing with new ARM Core Tiles these connectors can be stiff Firmly pressing each segment of each header is recommended 5 Using the Reference Design The D ini Group provides reference designs for the DNMEG ARM TILE REV2 to help the user get started with building applications Reference Loaded onto the board before shipped allows for AHB communication Loopback Allows for testing of D
33. ng AHB interface Output to ARM for use as AHB XHEADER REFCLK UP 25V P1 F1 helk input on selected Core Tiles CLK ETHB RX 25V PLE3 Ethernet clock for receive data Output to ARM for use as AHB ZHEADER CLK GLOBAL P1 F3 helk input on selected Core Tiles Input from system synchronous CLK FPGA DC P PLES clock buffer Input from system synchronous CLK FPGA DC N P1 F5 clock buffer Output to ARM for use as AHB XHEADER HCLKIN UP helk input on selected Core Tiles CLK ETHB TX P1 A37 Ethernet clock for transmit data CLK125 ETHB P1 K37 125 MHz Ethernet reference clock 12 ARM Headers The ARM header 7 J9 J14 connections were designed to be fully compliant with the CT926EJ S featuring an ARM processor For full descriptions of the function of these signals please consult the ARM Core Tile documentation Table 6 ARM Header Connections DNMEG ARM User Manual www dinigroup com 25 HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 26 HARDWARE DESCRIPTION Signal Name DNMEG ARM TILE User Manual www dinigroup com 27 HARDWARE DESCRIPTION Signal Name FPGA Pin XHEADER HRDATAT17 U7 P10 I XHEADER HRDATA18 U7NI XHEADER HRDATA19 U7 N2 XHEADER HRDATA2 U7 R1 XHEADER HRDATA20 U7 N9 XHEADER HRDATA28 U7 M6 XHEADER HRDATA7 U7 R6 XHEADER HRESP2 U7W1 CUITS XHEADER HSIZEO 07 15 XHEADER HSIZE1 U7 T10 XHEADER HSIZE2 U7T9 XHEADER HTRANSO U7T3 XHEADER HTRANSI U7 T6
34. odes the following configuration options are supported on this board JTAG Boundary Scan Master Serial from on board X ilinx PROM 7 Configuration Options This section lists detailed instructions for programming the Xilinx Virtex 5 FPGA using IMPACT Version 10 1 tools Before configuring the FPGA ensure that the Xilinx software and the Xilinx Platform Cable USB driver software are installed on the host computer Note This User Manual will not be updated for every revision of the Xilinx ISE tools so please be aware of minor differences DNMEG ARM User Manual www dinigroup com 14 PROGRAMMING CONFIGURING THE HARDWARE 7 1 Configuring the FPGA using The JTAG Boundary Scan configuration interface is always available regardless of the Mode pin settings The JTAG Boundary Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces 7 1 1 Setup Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the Power header 15 on the DNMEG ARM TILE REV2 D aughter Card 2 Connect the Xilinx Platform Cable USB to the FPGA JTAG header 16 3 Power up the board by turning ON the ATX power supply and verify that the Power LED s D S2 D 56 are ON indicating adequate power supply 7 1 2 Configuring the FPGA To configure the X ilinx FPGA perform the following steps 1 Open iMPACT and
35. onnections the Xilinx JTAG Header 16 allows for programming the Spartan 3 FPGA and the Xilinx PROM on the DNMEG ARM TILE REV2 Figure 4 Xilinx TAG Connector P2 5VD C142 P2 5VD FPGA JTAG Cable IV JTAG TMS 6 TDO JTAG TDI 87832 1420 2 J10 is the JTAG connector on the board for connecting an ARM debugger emulator to the ARM Core Tile Note for J10 to be active the signal ZHEADER EN N attached to the Spartan FPGA must be held HIGH Figure 5 Multi ICE JTAG Connector Silkscreen ICE DEBUG JTAG P3 3VD JTAG_DEBUG_SRSTN R150 1K 11 JTAG_DEBUG_RTCK 9 JTAG DEBUG TCK R156 For connector spec see multi ice user guide F 1 The final two JTAG connectors 12 and 13 are for reconfiguring devices on the ARM Core Tile Both Xilinx and Multi ICE style connectors are provided for this function since there are both Xilinx and non Xilinx parts in the JTAG chain on the Arm Core Tile Note for J12 and J13 to be active the signal ZHEADER CFG EN N attached to the Spartan FPGA must be held LOW DNMEG ARM TILE User Manual www dinigroup com 46 HARDWARE DESCRIPTION More detail about the JTAG chains on the ARM Core Tile can be found in the documentation provided with the Core T ile 20 Daughter Card Headers The DNMEG ARM TILE REV2 has one 400 pin MEG Array daughter card header Pl All signals on the DNMEG ARM TILE REV2 Daughter Card Headers
36. out the DNMEG ARM TILE Daughter Card TheDNMEG ARM TILE REV2 D aughter Card provides a development platform for designing and verifying applications targeted for use with an ARM processor This board provides designers access to commonly used peripherals and full utility of the ARM processor on a connected Core Tile The DNMEG ARM TILE 2 D aughter Card can operate in standalone mode or in conjunction with one oftheDini products that houses a 400 pin MEG Array D aughter card header e g D N 7020k10 Figure 1 DNMEG ARM TILE REV2 Daughter Card DNMEG ARM TILE User Manual www dinigroup com 1 INTRODUCTION 2 DNMEG ARM TILE REV2 Daughter Card Features DNMEG ARM TILE REV2 D aughter Card features the following AHB Interface TheAHB interface from the ARM Core Tile is connected both to the on board Spartan FPGA and to the MEG Array connector This allows for standalone usage base board only usage or combination of base board and on board FPGA usage Sample RTL code is provided to give each peripheral on the DNMEG ARM TILE REV2 an AHB interface making the peripherals easily accessible from the ARM processor Microprocessor Peripherals Xilinx Spartan 3 FPGA 355000 5 SDRAM PC100 PC133 16M x 32 o SSRAM 512K x 36 FLASH 2M x 16 o AC97 Audio Keyboard Mouse RS232 Ethemet PHY not available with DN 7020k10 or D N9000k10 Flexible Clock Resources o AHB clock can be generated using S
37. partan and on board 100 MHz clock or from base board This allows for AHB frequencies from 1 100 MHz o Can use HCLK Global Clock retimed or delay matched clocks for clocking Core Tile FPGA Configuration DNMEG ARM TILE User Manual www dinigroup com 2 INTRODUCTION On board Xilnx PROM for automatic configuration o JTAG for configuration of Xilinx Spartan and PROM Xilinx JTAG cable provided ARM Configuration o Through a combination of switches and FPGA signals all init and run time configuration signals for the ARM processor can be programmed o JTAG interface to the ARM Core Tile is provided allowing third party debuggers emulators to communicate with the ARM processor User LED s x32 General Purpose I O headers Onboard distributed Power Supplies MEG Array 400 pin interface to D inigroup base boards Full support for embedded Logic Analyzers o ChipScope Pro Analyzer RS232 Port 10 pin Header MicroBlaze Applications Stand Alone operation requires an external 12V 5V ATX power supply 3 Package Contents Before using the kit or installing the software be sure to check the contents of the kit and inspect the board to verity that you received all of the items If any of these items are missing contact The D ini Group before you proceed The DNMEG ARM TILE REV2 D aughter Card kit includes the following RS232 IDC Header to Female D B9 Cable Assembly RS232 Serial Cable Assembly 6ft F D B9
38. provided Please consult the AC97 specification for a complete description of the functionality of the codec Table 16 AC97 Connections Signal Name DNMEG ARM User Manual www dinigroup com 44 HARDWARE DESCRIPTION Signal Name AUDIO BIT U7 A E22 AUDIO RESET U7 AK28 AUDIO SDATA IN U7 AF10 J30 2 J29 2 In addition several static signals are attached to DIP Switch S3 When the switches are in the OFF position the signals will be HIGH Turning the switches ON results in making the signals LOW Table 17 Signals on S3 Signal Name AUDIO MODE AUDIO 50 AUDIO 51 AUDIO EAPD 18 RS232 Port An RS232 serial port is provided for low speed communication with the application on the FPGA The RS 232 standard specifies output voltage levels between 5V to 15V for logical 1 and 5V to 15V for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet The connections between the FPGA and the RS232 Port are shown below Table 18 Connections between FPGA and the RS232 Port Signal N ame FPGA Pin FPGA RXD U7 K17 FPGA TXD 07 18 85232 EN N U7A18 DNMEG ARM TILE User Manual www dinigroup com 45 HARDWARE DESCRIPTION 19 There several JTAG connections on the DNMEG ARM TILE REV2 The first of these c
39. ray headers line up BEFORE applying pressure to mate the connectors DNMEG ARM TILE User Manual www dinigroup com 55 HARDWARE DESCRIPTION 20 6 MEG Array Specifications Manufacturer Part Number RoHS Lead Free Compatible Total Number Of Positions Contact Area Plating Mating Force Unmating Force Insulation Resistance Withstanding Voltage Current Rating Contact Resistance Temperature Range Trademark Approvals and Certification Product Specification Pick up Cap Housing Material Contact Material D urability Mating Cycles FCI 743 101LF Bottom Receptacle P2 84520 102LF Top Plug P1 yes 400 0 76 um 30 uin gold over 0 76 um 30 uin nickel 30 grams per contact average 20 grams per contact average 1000 M ohms 200 VAC 0 45 amps 20 to 25 m ohms max initial 10 m ohms max increase after testing 40 C to 85 C MEG Array UL and CSA approved G Se 12 100 from FCI website yes LCP Copper Alloy 50 DNMEG ARM User Manual www dinigroup com 56 HARDWARE DESCRIPTION 21 Mechanical 21 1 Dimensions TheDNMEG ARM TILE REV2 D aughter Card measures 133mm x 196 75mm 9 200 196 75 190 I 1 I T Er 180 170 160 150 f 140 135 5 Hg 02975 120 ld e mi 10 UU de tay It 90 iU HK H E i H 80 1338 EN tH To 70
40. w dinigroup com 21 HARDWARE DESCRIPTION 10 2 SSRAM A single Cypress pipelined SSRAM is connected to the FPGA in a 512k x 36 configuration 10 3 FLASH A single 32 megabit FLASH memory from Atmel is connected to the FPGA in a 2M x 16 configuration Non volatile memory and ARM instructions can be stored in the FLASH and read out by the ARM processor 10 4 AC97 Audio An Analog Devices AD 1881A is connected to the FPGA A CD Audio Line Out and Headphone IN connector is provided The AD 1881A meets the A udio Codec 97 2 0 and 2 1 Extensions In addition the AD 1881A SoundMAX Codec is designed to meet all requirements of the A udio Codec 97 Component Spedfication Revision 1 03 The AD1881A also includes some other Codec enhanced features such as the built in PHAT Stereo 3D enhancement 10 5 Ethemet PHY 10 100 1000base T not available with DN7020k10 or DN9000k10 With an appropriate MAC a Vitesse VSC8601 Ethemet PHY provides 10 100 1000base T Ethernet 11 Clock Generation 11 1 Clock Methodology The DNMEG ARM TILE REV 2 has a flexible and configurable clocking scheme Figure 3 is a block diagram showing the clocking resources and connections DNMEG ARM User Manual www dinigroup com 22 HARDWARE DESCRIPTION 218846 I Qg 2155240 gt lt O O xx OO O OO N o o 2 3 JE 2 m m L 400 Pin Meg Array lt D G
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