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S1D13504 TECHNICAL MANUAL

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3. TX3912 S1D13504 A 12 0 AB 12 0 ENDIAN V gt AB 20 13 D 31 24 4 DB 7 0 D 23 16 4 gt DB 15 8 System RESET gt RESET VDD pull up CARDxWAIT 4 L WAIT DCLKOUT EAS M R 9 Clock divider gt IT8368E OKs Oscillator gt BUSCLK LHA 20 13 See text gt CLKI LHA23 IO Vpp BS IT8368E LHA23 MFIO10 gt WE1 LHA22 MFIO9 e WEO LHA21 MFIO8 gt RDI LHA20 MFIO7 gt RDO LHA19 MFIO6 f m r CSH Chip Select Logic Notes The Chip Select Logic shown above is necessary to guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that amy reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 5 2 SID13504 to TX3912 Connection using Two IT8368E Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Toshiba MIPS TX3912 Processor 1D13504 Issue Date 01 10 26 X19A G 012 05 Page 18 Epson Research and Development Vancouver Design Center The Generic MPU host interface control signals of the S1D13504 are as
4. Symbol Parameter Rating Units Core Vpp Supply Voltage Vss 0 3 to 4 6 V IO Vpp Supply Voltage Vss 0 3 to 6 0 V VIN Input Voltage Vss 0 3 to IO Vpp 0 5 V VouT Output Voltage Vss 0 3 to lO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C TsoL Solder Temperature Time 260 for 10 sec max at lead C Table 6 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Core Vpp Supply Voltage Vsg 0 V 2 7 3 0 3 3 3 6 V IO Vpp Supply Voltage Vss 0V 2 7 3 0 3 3 5 0 5 5 V ViN Input Voltage Vss IO Vop V Topr Operating Temperature 40 25 85 C Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units Low Level Input Voltage IO Vpp 3 0 0 8 V Vi CMOS inputs 3 3 0 8 V 5 0 1 0 V High Level Input Voltage IO Vbpp 3 0 1 9 V VIH CMOS inputs 3 3 2 0 V 5 0 3 5 V Positive Going Threshold IO Vpp 3 0 1 0 2 3 V Vr CMOS Schmitt inputs 3 3 1 1 2 4 V 5 0 2 0 4 0 V Negative Going Threshold IO Vpp 3 0 0 5 1 7 V Vr CMOS Schmitt inputs 3 3 0 6 1 8 V 5 0 0 8 3 1 V Vop Max liz Input Leakage Current Vin IO Vop 1 1 uA Vit Vss Cin Input Pin Capacitance 10 pF Vin Vpp 3 0 60 120 300 kQ HRpp Pull down Resistance 3 3 50 100 300 kQ 5 0 50 100 300 kQ S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Resea
5. Epson Research and Development Page 67 Vancouver Design Center tl t2 Sync Timing FPFRAME Ba t4 FPLINE t5 gt MOD Data Timing FPLINE t8 t12 FPSHIFT UD 3 0 2 LD 3 0 Figure 7 22 Single Monochrome 8 Bit Panel A C Timing Table 7 20 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPLINE falling edge to FPSHIFT falling edge t14 4 Ts t8 FPSHIFT period 8 Ts t9 FPSHIFT falling edge to FPLINE falling edge note 6 t10 FPLINE falling edge to FPSHIFT rising edge 18 Ts t11 FPSHIFT pulse width high 4 Ts t12 FPSHIFT pulse width low 4 Ts t13 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 4 Ts t14 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 4 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 timin min 9TS 3 4min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG 04h bits 6 0 1 8 1 Ts 5 t6min REG O5h bits 4 0 1 8 23 Ts 6 t9min REG O5h bits 4 0 1 8 14 Ts Hardware Functional Specification Issue Date
6. VDP VNDP i e FPFRAME me Ll FPLINE Jl l j l j IL j j nl j j UD 3 0 LD 3 0 __ LINE1 X LINE2 X LINES X LINE4 4 XLINE479XLINE480 LINE X LINE2 X _ FPLINE HDP HNDP lt 4 de gt FPSHIFT an al FPSHIFT2 sa it PO i UD3 Las R1 Y 1 G1 Y 166 X 1 86 X1 B11 X 1 R124 R636 UD2 1 81 X 1 R2 X 1 87 X 1 67 X1 G12X 1 B12 4 1 B636 UD1 pe A 1 2 X 1 82 X 1 87 X 1 R8 X1 R13X 1 13 G637 K X UDO a R3 X_1 63 X_1 68X_1 88 X 1 BI3X 1 R14 R638 LD3 _ 1 83 X 1 R4 X 1 Ro X 1 69 X1 G14X 18144 B638 LD2 e G4 Y 184 Y 189 PRIORI G639 AE LD1 T R5 X 1 45 X 1 G10X 1 B10X1 B15 X 1 R16 R640 X LDO 7 1 85 X 1 R6 X 1 R11X 1 G11X1 G16X 1B16 B640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 25 Single Color 8 Bit Panel Timing Format 1 VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson
7. 1D13504 X19A G 014 01 1 T 1 1 y 1 T 1 1 5 E sag z002 pe Bquades esn og on a na saquny juewnoog azs otadtor3031g diyo VO 1P088 sng 104 D0080 NSS uy uauidojened 3 yoseasety uosda insano ae 2 920 qua otuezao ub MHELESN 00 Go paaetndod 30N zzu 2d voseLann so ATT Hey 40d 9008 aom el zn weI MAGOT oz E ozy VS 06H YN LAOL vesLiZ4 el a o ay drug oquexa N vzo vO nao Le Mik 220 y Ha rav o t so wale 208 TH ezo St da O6ELANN Ww 0 ar gt 1A TO1109 18 ZA BSOPS XVIN ang ee 28 TSSOELON zo an ae re TS Sau or drug oquexa LAES n0t o la Y H 3 ae E t A Er 7 ano Hono z mA ME ue iva ravi EMIOOT I06ELAWN a Ton adh eLo 10 AZL yr T 3007 Le bevel Ci ppt Hn om INV ddd 8197 n N INNA 104002 rt nsz anor L4IHSda WAS see Te ME Ty z 100 ven vve rr eve Shivads ave Lo PhivGds ive Le ELIVdda ww LE ZhivGds evi ELIVOda a 2 Olives wi Le 61VQ
8. g Z E 5 y E z T p z EZE Z661 6 TOQUES FepsonL seg a a or nay Jequiny uuo az uny weunooa_ eas saod ano PIROg uojenjeag O t 9H SNG VSI D008POSELNSS 30 0 IDA ONI LN3WNdO13A3G ANY HOV3S3U NOSd3 nai o n Ags Of AEE a SzISTHL oS vsn y s Lo 201RII9SO_ZUNO OF s9 ONO ino srsonan lt A z SJ z 7 z C gt m DO yr 208 N H ia ca yor or 9A alec ano a Ny 13sau oay n Hsausau 10u nN aHas 0 nfs zw 5 nm n LS aw ozv n Le ava HUM S 89 y E sasaa lt T eros leew Y30OV3H L tar aono a S os 31s91 eizvadn S SSA 30 L EA Sen z 40 40 LO ZE ssa N Xx 9 zo 19 zz oN ES al 20 on PS oono Zt 99n EJ iTA WE sam g craw r 29 SVV Ie vor raw or Od BON g svon sia MS 100 sv svu TON 6e CIN 8E red 10a ONIL vw 9 S SOW HON 9 oroa ON OLY own Z y raw TON se 600 eyruey ow 8 E caw SQW 209 sviusy 5 z Zan TON et 00 y LE TOW zan ot_ 50 SOW 6 o 5 1S ec soa sv st lca gt vst a a a 2 wer a a as ea 20 ev su 84 ag 94 su ve eu za EJ y a wy or oa Ww v 0d z wa w zn s olww pas gt olaw E 7 E z E E z 7 Figure 2 SID13504B00C Schematic Diagram 2 of 6 1D13504 X19A G 004 06 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 yo E Tus z Z661 0e equae Repson aed a aas preog uoenena 01 A84 SNg YSI B008
9. y d SE Memory Clock 4 t2 gt t3 t4 t5 t6 t8 t9 4 pit _ gt _ gt e MA R l C1 C2 C3 C4 t7 RAS gt CAS t10 t11 rit t12 t13 t15 gt gt t14 gt MD Read d1 d2 d3 d4 Figure 7 12 FPM DRAM Read Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 55 Vancouver Design Center Table 7 12 FPM DRAM Read Timing Symbol Parameter Min Typ Max Units t1 Memory clock 40 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t2 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns Row address setup time REG 22h bits 3 2 00 2t1 ns t3 Row address setup time REG 22h bits 3 2 01 1 45 t1 ns Row address setup time REG 22h bits 3 2 10 111 ns i Row address hold time REG 22h bits 3 2 00 or 10 t1 1 ns Row address hold time REG 22h bits 3 2 01 0 45 t1 1 ns t5 Column address set up time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 CAS pulse width 0 45 t1 0 55t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 0 45 t1 ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t10 RAS precharge time REG 22h bits 3 2 01 1 4511 1 ns RAS p
10. 256 Color Data Format Red Look Up Table 7 6 5 4 3 2 1 0 Bank 0 R2 R1 RO G2 G1 G0 B1 BO o 2 a 0 Selected Bank 5 000 6 001 7 Bank 010 A 4 bit Red data output Bank 1 8 an pak 100 Logic 9 ogic 110 A 111 B 1 C D E F Bank Select bit fi REG 27h bit 4 3 bit pixel data Green Look Up Table Bank 0 0 1 2 3 0 Selected Bank 5 000 6 001 7 Bank 010 Entry 4 bit Green data output Bank 1 Select 100 Select gt 8 Logi 101 Logic 9 ogic 110 A 111 B 1 C D E F Bank Select bit 1 REG 27h bit 0 3 bit pixel data Blue Look Up Table Bank 0 9 2 00 3 Bank 1 E ot Selected Bank S Bank 4 bit Blue data output X Bank 2 Select a Logic A 10 B Bank 3 5 E 11 F Bank Select bits 1 0 t 2 bit pixel data REG 27h bits 3 2 Figure 12 7 8 Bit Per Pixel 256 Level Color Mode Look Up Table Architecture 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 127 Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13504 to accommodate the important need for power reduction in the hand held devices market These modes are hardware suspend and software suspend 13 1 Hardware Suspend Register read write disallowed Memory read write disallowed LCD outputs are forced low see Note 1 of Section 13 4 Pin States in Power Save Modes on page 128 LCDPWR forced to Off state CRT outputs ar
11. 4 bit Blue data output 1D13504 X19A A 002 19 Figure 12 5 2 Bit Per Pixel 4 Level Color Mode Look Up Table Architecture Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 125 Vancouver Design Center 4 Bit Per Pixel Color Mode Red Look Up Table TMDOWPOBNOOARWHY O 4 bit pixel data Entry Select Logic Green Look Up Table TMMDOWPOONAMTMAWHY O Entry 4 bit Red data output 4 bit Green data output Select Logic Blue Look Up Table TMMUDOWPOODNOUNAWNH O Entry Select Logic 4 bit Blue data output Figure 12 6 4 Bit Per Pixel 16 Level Color Mode Look Up Table Architecture Hardware Functional Specification Issue Date 01 11 06 1D13504 X19A A 002 19 Page 126 8 Bit Per Pixel Color Mode Epson Research and Development Vancouver Design Center
12. e 34 Identifying the S1D13504 o a 38 Hardware Abstraction Layer HAL lt lt 39 Sl gt TIMtrOdUCHION e rr YA E AS ls eR a er Bee Bs Bowl aa e we a oI 8 2 APIforidsO4HAL 0222400 a ee a a a ABD S21 ninalization A Bea E OR Ee A A as 39 8 22 Screen Manipulation seire a a ok ee ee ee e eo ew le ea 41 82 3 Color Manipulation i seee ac a REO A Se eo Re ge a a 47 824 gt Drawint a a eee Bae SE Ew Pe oe whi AR BGS 50 8 25 RegisterManipulation ses 04 cae be ee Rd ae E a we be ee ROS 52 2 6 Miscellaneous Bees BA Pow e ee hee ae we ee Bw Bae he BS 32 9 Sample Code timida a A A a eae ie See A a 54 9 11 Introductions e e e eee y p Be a BR e Re el ew awe A 9 1 1 Sample code using 13504HAL API 2 0 2 0 2 02 00 0000 00000 54 9 1 2 Sample code without using 13504HAL API o o 55 Appendix A Supported Panel Values 2 4 61 S1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 5 Vancouver Design Center List Of Tables Table 2 1 Initializing the S1D13504 Registers e 10 Table 3 1 Pixel Storage for 1 bpp 2 Colors Gray Shades in One Byte of Display Buffer 12 Table 3 2 Pixel Storage for 2 bpp 4 Colors Gray Shades in One Byte of Display Buffer 12 Table 3 3 Pixel S
13. 1D13504 PR31500 PR31700 IO Vop ut BS A 12 0 gt AB 12 0 ENDIAN Latch gt AB 20 13 ALE 5 atc D 31 24 gt DB 7 0 D 23 16 4 gt DB 15 8 System RESET gt RESET VoD pull up CARDXWAIT e b WAIT DCLKOUT A23 gt M R See text CLKI IT8368E o Clock divider 0F Oscillator _ BUSCLK LHA23 MFIO10 gt WE1 LHA22 MFIO9 gt WEO LHA21 MFIO8 RD1 LHA20 MFIO7 gt RDO LHA19 MFIO6 Chip Select ogy Notes The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 5 1 SID13504 to PR31500 PR31700 Connection using One ITS368E Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13504 Issue Date 01 10 26 X19A G 005 09 Page 16 1D13504 X19A G 005 09 Epson Research and Development Vancouver Design Center The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock This
14. ak Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to IO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 S1D13504 X19A G 010 06 Page 14 Epson Research and Development Vancouver Design Center 3 2 Generic MPU Host Bus Interface Signals 1D13504 X19A G 010 06 The interface requires the following signals BUSCLK is a clock input which is required by the 1D13504 host bus interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset M R memory register may be considered an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the 1D13504 is accessed by the host CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 RD RDO and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 WAIT is a signa
15. 128 SPTO 1 2 max Figure 14 2 Mechanical Drawing TQFP15 128 S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 131 Vancouver Design Center 14 3 QFP20 144 S1D13504F02A QFP20 144 pin Unit mm 29 0 4 r 20 0 1 108 73 A A 72 INDEX 37 TTT TT FO i 0 1 36 0 5 0 2 0 05 E TT he y Figure 14 3 Mechanical Drawing OFP20 144 Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 132 Epson Research and Development Vancouver Design Center 15 References 1D13504 X19A A 002 19 The following documents contain additional information related to the S1D13504 Document numbers are listed in parenthesis after the document name All documents can be found at the Epson Research and Development Website at www erd epson com e S1D13504 Product Brief X19A C 002 xx e S1D13504 Windows CE v2 x Display Drivers X19A E 001 xx e S1D13504 Wind River WindML v2 0 Display Drivers X19A E 002 xx e S1D13504 Wind River UGL v1 2 Display Drivers X19A E 003 xx S1D13504 Programming Notes And Examples X19A G 002 xx S5U13504B00C Evaluation Board User Manual X19A G 004 xx Interfacing to the Philips MIPS PR31500 PR31700 Microprocessor X19A G 005 xx S1D13504 Power Consumption X19A G 006 xx
16. HRTC FPLINE Start Position Register REG 06h RW HRTC HRTC HRTC HRTC HRTC n a n a n a FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start Position Bit 4 Position Bit3 Position Bit 2 Position Bit 1 Position Bit O bits 4 0 HRTC FPLINE Start Position Bits 4 0 For CRTs and TFTs these bits specify the delay from the start of the horizontal non display period to the leading edge of the HRTC pulse and FPLINE pulse respectively Contents of this Register HRTC FPLINE Start Position 8 1 The maximum HRTC start delay is 256 pixels Note This register must be programmed such that REG 05h 1 gt REG 06h 1 REG 07h bits 3 0 1 S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 93 Vancouver Design Center HRTC FPLINE Pulse Width Register REG 07h RW HRTC FPLINE HRTC HRTC HRTC HRTC Polarity Polarity n a n a FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse Select Select Width Bit 3 Width Bit 2 Width Bit 1 Width Bit 0 bit 7 HRTC Polarity Select For CRTs this bit selects the polarity of the HRTC When this bit 1 the HRTC pulse is active high When this bit 0 the HRTC pulse is active low bit 6 FPLINE Polarity Select This bit selects the polarity of the FPLINE for TFT and passive LCD When this bit 1 the FPLINE pulse is active high for TFT and act
17. Current Frame Rate 75 Hz Figure 8 13504CFG Panel Setup 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Epson Research and Development Vancouver Design Center Page 18 Edit Panel Setup When a selection is highlighted in the Panel Setup window and Edit is clicked the Edit Panel Setup window is displayed The Edit Panel Setup window lists parameters which can be edited as shown below in Figure 9 13504CFG Edit Panel Setup In this example window X Resolution 320 pixels is highlighted STN 4 BIT MONO SINGLE 326x246 for Device 2 Resolution Y Resolution Data Width Panel Format Color Mono Dual Single TFT STN Modulation Rate Horiz Non Disp lt TFT gt Vert Non Disp lt TFT gt HRTC Start Pos lt TFT gt URTC Start Pos lt TFT gt 326 pixels 246 linets gt i bits MONO SINGLE STN 5 Cancel 32 pixels 1 linets gt 8 pixels 1 linets gt ACTIVE HIGH ACTIVE HIGH 8 pixels FPLINE Polarity FPFRAME Polarity HRTC Pulse Width lt TFT gt Current Frame Rate 75 Hz Figure 9 13504CFG Edit Panel Setup Panel Parameter Edit When a selection is highlighted for editing in the Edit Panel Setup window and Edit is clicked the Panel Parameter Edit window displays for parameter editing See figure 10 13504CFG Panel Parameter Edit below In this example window X Resolution 320 pixels can be edited Cancel X Resolut
18. 0 14 3 2 6 Memory Organization for 16 Bit per pixel 65536 Colors o o 14 3 3 Look Up Table LUT LA a ehh etl ak ote ee 15 3 3 1 Look Up Table Registers coo Dw ba Se ee EA ee ne ee ee 8 15 3 3 2 Look Up Table Organization 0 000000000000 000 2 17 4 Advanced Techniques 202 eee eee ee 23 4 1 Virtual Display 23 AT RESISTE 24 41 2 Examples 0 a a a Bes gy eh he ee ae 24 4 2 Panning and Scrolling 25 42 00 Registers sages ha eA RAS Dh Bei a A be EAS a 26 ADD EXAMP ES id ek ye he Ed e e aw ha he ee ee eels 27 43 Split Screen 28 A321 E of pene B dete ee ded ae ele PE Se aed a Ge ee be He a E AY 28 4 3 2 Examples nicha e ON 63 Ga ele a 29 5 LCD Power Sequencing and Power Save Modes 200022 e tees 30 5 1 Introduction to LCD Power Sequencing 30 5 2 Introduction to Power Save Modes 30 5 3 Registers og 30 5 4 Suspend Sequencing 31 Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 4 Epson Research and Development Vancouver Design Center 5 4 1 Suspend Enable Sequence 0 000 000 0000 00 0000 31 5 4 2 Suspend Disable Sequence 2 2 e 32 5 5 LCD Enable Disable Sequencing Reg OD bit0 2 2 82 6 CRT Considerations ee 33 6 Introduction s s gfe See a ek a Abe e Ala Bob amp 2 A eed Hoge 33 GA CREO ac tec bay a a Sie ees Re ea Eb by eA 33 6 1 2 Simultaneous Display
19. TBcLK er La La Ml da rr a t1 t2 t1 t2 PA 5 o A 20 0 M RH Valid t1 t2 t1 t2 a l CS Y gt 148 HE y 4 e RDOH AD14_ gt o WEO WE1 t4 t5 t6 Hi Z Hi Z WAIT t7 t8 e gt i Hi Z nee Valid D 15 0 write t9 t10 t11 F ha Hi Z Hi Z D 15 0 read bau Figure 7 4 Generic MPU Interface Synchronous Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 43 Vancouver Design Center Table 7 4 Generic MPU Interface Synchronous Timing Symbol Parameter Min Max Units TBCLK Bus clock period 25 ns t1 A 20 0 M R CS RDO RD1 WE0 WE1 hold time 1 ns t2 A 20 0 M R CS RDO RD1 WE0 WE1 setup time 5 ns t3 RDO RD1 WE0 WE1 high to A 20 0 M R invalid and CS high 0 ns t4 RDO RD1 WE0 WE1 low and CS low to WAIT driven low 1 7 ns t5 BCLK to WAIT high 0 15 ns t6 RDO RD1 WE0 WE1 high to WAIT high impedance 1 6 ns t7 D 15 0 valid to second BCLK where RDO RD1 WE0 WE1 low and CS 5 He low write cycle t8 D 15 0 hold from WEO WE1 high write cycle 0 ns t9 RDO RD1 low to D 15 0 driven read cycle 3 15 ns t10 D 15 0 valid to WAIT high read cycle 0 t11 RDO RD1 high to D 15 0 high impedance read cycle 2 10 1 Ifthe S1D13504 host interface is disabled the timing
20. e 34 Table 6 3 8 bpp Recommended RAMDAC palette data for Simultaneous Display 35 Table 6 4 Related register data for Simultaneous Display o a 37 Table 9 1 Passive Single Panel ae a epee a dd it a a 61 Table 9 2 Passive Dual Panel vue ar a oles BGs Ca eee OR Ee ee a we REA SS A 61 Fable 9 33 SUFT Panel 2 ar AAA REG KA AA E 62 List of Figures Figure 4 1 Viewport Inside a Virtual Display e 23 Figure 4 2 320x240 Single Panel For Split Screen o ee eee 28 Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This guide describes how to program the S1D13504 Color Graphics LCD CRT Controller The guide presents the basic concepts of the LCD CRT controller and provides methods to directly program the registers It explains some of the advanced techniques used and the special features of the S1D13504 The guide also introduces the hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13504 Most S1D1350x S1D1370x and S1D1380x products support the HAL allowing OEMs to switch chips with relative ease Programming Notes and Examples 1D13504 Issue Da
21. FPM EDO DRAM Figure 3 3 Typical System Diagram MC68K Bus 2 256Kx16 FPM EDO DRAM 32 Bit MC68030 GENERIC BUS A21 CSn A 20 0 D 15 0 WEO WE1 RDO RD1 WAIT BCLK RESET Power Management Oscillator 4 vVvvvyv Vv M R CS AB 20 0 DB 15 0 WEO WE1 RD RD WR WAIT BUSCLK RESET SUSPEND kJ CLKI 1D13504 FPDAT 15 8 FPDAT 7 0 FPSHIFT FPFRAME FPLINE DRDY LCDPWR gt UD 7 0 LD 7 0 FPsHIFT 4 8 16 bit LCD FPFRAME Display FPLINE MOD A 11 0 q MAJ1 1 0 D 15 0 kg MD 15 0 WE d we RAS _ RASH LCAS LCAS UCAS UCAS x16 DO DRAM re m FPM A Figure 3 4 Typical System Diagram Generic Bus 1Mx16 FPM EDO DRAM Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 16 Epson Research and Development Vancouver Design Center 4 Block Description 4 1 Functional Block Diagram 16 bit FPM EDO DRAM Memory Power Save Register Controller Clocks CPU LCD 5 R W gt LCD Host Display I F DAC CPU MPU 4 gt F
22. Note seSetInit must first be called before calling seSplitInit This is because the VNDP is used for timing and this would not be possible if the registers were not first initialized int seSplitScreen int device BYTE WhichScreen int VisibleScanlines Description Changes the relevant registers for moving the split screen up or down Parameter device registered device ID WhichScreen Use one of the following definitions SCREEN or SCREEN2 SCREEN is the top screen VisibleScanlines number of lines to show for the selected screen Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_HAL_BAD_ARG argument VisibleScanlines is negative or is greater than vertical panel size Note seSplitInitQ must have been called once before calling seSplitScreen Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Vancouver Design Center Page 45 int seVirtinit int device int xVirt long yVirt Description Parameter Return Value Note Creates a virtual display with the given horizontal size and determines the maximum number of available lines device registered device ID xVirt horizontal size of virtual display in pixels Must be greater or equal to physical size of display yVirt seVirtInit calculates the maximum number of lines available for virtual display and returns value in yVirt ERR_OK operat
23. See Host Bus Selection table below MD4 Little Endian See Host Bus Selection table below Wait signal is active low MD9 ee required settings for MCF5307 interface Table 4 2 S1D13504 Host Bus Selection 1 Xx MD3 MD2 MD1 Host Bus Interface 0 0 0 SH 3 bus interface 0 0 1 MC68K bus 1 interface e g MC68000 0 1 0 x Reserved MC68K bus 2 interface e g MC68030 L required settings for MCF5307 interface 1D13504 X19A G 011 07 Interfacing to the Motorola MCF5307 Coldfire Microprocessor Issue Date 01 02 02 Epson Research and Development Page 15 Vancouver Design Center 4 3 Memory Register Mapping The S1D13504 is a memory mapped device requiring a 2M byte address space for the display buffer and a few more locations for the internal registers Chip selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes however these chip selects would normally be needed to control system RAM and ROM Two of the IO chip selects CS2 through CS7 are required to address the entire address space of the S1D13504 since these chip selects have a fixed 2M byte block size 4 4 MCF5307 Chip Select Configuration In the example interface chip selects 4 and 5 are used to control the S1D13504 CS4 selects a 2M byte address space for the S1D13504 control registers while CS5 selects the 2M byte display buffer The CSB
24. 3 Copy the console driver files to the build directory Copy the files tmp s1d13xxxfb c and tmp s1d13504 h to the directory usr src linux drivers video Copy the remaining source files tmp Config in tmp fbmem c Itmp fbcon cfb4 c and tmp Makefile into the directory usr src linux drivers video replacing the files of the same name Linux Console Driver Issue Date 01 11 19 Epson Research and Development Page 5 Vancouver Design Center If your kernel version is not 2 2 17 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names 4 Modify s1d13504 h The file s1d13504 h contains the register values required to set the screen resolution color depth bpp display type display rotation etc Before building the console driver refer to the descriptions in the file s1d13504 h for the default settings of the console driver If the default does not match the configura tion you are building for then s1d13504 h will have to be regenerated with the correct information Use the program 13504DCFG to generate the required header file For information on how to use 13504DCEG refer to the 13504DCFG Driver Configuration Program User Manual document number X19A B 008 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header Fi
25. Epson Research and Development Page 25 Vancouver Design Center Lookup Table LUT LUT Setup When Lookup Table is selected from the Device menu the LUT Setup dialog box is displayed To select a LUT assignment highlight it in the example window below LUT Internal 4 Color is highlighted and click OK If the highlighted LUT assignment needs changes click Edit and see the next section Edit LUT Setup Whenever a LUT assignment is edited or selected in the LUT Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configuration In addition to OK Cancel and Edit commands a Help command is listed in the LUT setup windows In this version of 13504CFG the Help files are unavailable LUT Assignment for Device LUT INTERNAL 4 COLOR LUT INTERNAL 16 COLOR LUT INTERNAL 256 COLOR LUT INTERNAL 2 MONO LUT INTERNAL 4 MONO LUT INTERNAL 16 MONO LUT EXTERNAL DAC 256 DISABLE LUT USE 15 BPP DISABLE LUT USE 16 BPP CURRENT CONFIGURATION E HH Cancel Figure 20 13504CFG LUT Setup 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 26 1D13504 X19A B 001 04 Edit LUT Setup LUT 2 BPP COLOR for Device Per Pixel 2 Select LUT or DAC INTERNAL LUT Epson Research and Development Vancouver Design Center Edit LUT Setup When a selection is highlighted in the LUT Setup window and Edit is clicke
26. In all supported Power Save Modes the LCD Enable bit and associated functionality is automati cally controlled by the internal Power Save circuitry See above for Power Save sequences LCD Enable Disable using Manual Control It may become necessary to enable disable the LCD when switching back and forth to and from the CRT In this case care must be taken when disabling the LCD with respect to the external Power Supply used to provide the LCD Drive voltage The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage Enable Setting REG OD bit 0 1 immediately enables the LCD interface signals Note FPLINE FPSHIFT2 DRY signals are always toggling regardless of the state of this bit and are only shut down completely during Power Save Modes The LCDPWR pin will go to its active state immedi ately after the LCD Enable bit is set Disable Setting REG OD bit 0 0 LCDPWR will go to its inactive state within one vertical frame while maintaining the LCD interface signals for 128 Vertical Frames with the exception of FPFRAME which goes inactive at the same time as LCDPWR If 128 frames is not enough time to allow the LCD Drive power supply to decay to OV LCDPWR can be controlled manually using REG 1A bit 3 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 33 Vancouver Design Center 6 CRT Considerations 6 1 Introdu
27. 01 11 06 S1D13504 X19A A 002 19 Page 68 Epson Research and Development Vancouver Design Center 7 4 5 Single Color 4 Bit Panel Timing VDP VNDP FPFRAME FPLINE J l l l acl l fl l fl l fl MOD me X UDJ3 0 LINE1 X LINE2 LINES X LINE4 4 XLINE479 LINE480 LINE1 Y LINE2 FPLINE l MOD E HDP HNDP FPSHIFT ri gt pail hf LJ LJ LJ LI LJ Es UD3 o 1 R1 Y 1 G2Y 1 B3 Y r XO B319 UD2 e 1 61 X 1 82 Y 1 Ra a X ERA UD1 a3 1 81 _1 R3 _1 G4 y M G320 Y UDO 7 1 R2X 1 G3 _ 1 B4 Y X X1 B320 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 23 Single Color 4 Bit Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 69 Vancouver Design Center tt t2 Sync Timing 4 FPFRAME BL t4 FPLINE l t5 MOD Y Data Timing FPLINE t6 t7 t8 t9 t10 t11 t12 lt
28. 1 in this bit drives GPIO4 to high and a 0 in this bit drives GPIO4 to low When GPIO4 is configured as an input a read from this bit returns the status of GPIO4 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO4 other wise the DACRD pin is controlled automatically and this bit will have no effect on hardware GPIO3 Pin IO Status When GPIO3 is configured as an output a 1 in this bit drives GPIO3 to high and a 0 in this bit drives GPIO3 to low When GPIO3 is configured as an input a read from this bit returns the status of GPIO3 Note the MD 7 6 pins must be properly configured at the rising edge of RESET to enable GPIO3 otherwise the MA9 pin is controlled automatically and this bit will have no effect on hardware GPIO2 Pin IO Status When GPIO2 is configured as an output a 1 in this bit drives GPIO2 to high and a 0 in this bit drives GPIO2 to low When GPIO2 is configured as an input a read from this bit returns the status of GPIO2 Note the MD 7 6 pins must be properly configured at the rising edge of RESET to enable GPIO2 otherwise the MA11 pin is controlled automatically and this bit will have no effect on hardware GPIO1 Pin IO Status When GPIO1 is configured as an output a 1 in this bit drives GPIO1 to high and a 0 in this bit drives GPIO1 to low When GPIO1 is configured as an input a read from this bit returns the status of GPIO1 Note the MD 7 6 pins m
29. 15 0E 00 1B 2A 2E 09 1B 2A 4E 12 1B 2A 6E 1B 1B 2A OF 00 1B 3F 2F 09 1B 3F 4F 12 1B 3F 6F 1B 1B 3F 10 00 24 00 30 09 24 00 50 12 24 00 70 1B 24 00 11 00 24 15 31 09 24 15 51 12 24 15 71 1B 24 15 12 00 24 2A 32 09 24 2A 52 12 24 2A 72 1B 24 2A 13 00 24 3F 33 09 24 3F 53 12 24 3F 73 1B 24 3F 14 00 2D 00 34 09 2D 00 54 12 2D 00 74 1B 2D 00 15 00 2D 15 35 09 2D 15 55 12 2D 15 75 1B 2D 15 16 00 2D 2A 36 09 2D 2A 56 12 2D 2A 76 1B 2D 2A 17 00 2D 3F 37 09 2D 3F 57 12 2D 3F 77 1B 2D 3F 18 00 36 00 38 09 36 00 58 12 36 00 78 1B 36 00 19 00 36 15 39 09 36 15 59 12 36 15 79 1B 36 15 1A 00 36 2A 3A 09 36 2A 5A 12 36 2A 7A 1B 36 2A 1B 00 36 3F 3B 09 36 3F 5B 12 36 3F 7B 1B 36 3F 1C 00 3F 00 3C 09 3F 00 5C 12 3F 00 7C 1B 3F 00 1D 00 3F 15 3D 09 3F 15 5D 12 3F 15 7D 1B 3F 15 1E 00 3F 2A 3E 09 3F 2A 5E 12 3F 2A 7E 1B 3F 2A 1F 00 3F 3F 3F 09 3F 3F 5F 12 3F 3F 7F 1B 3F 3F Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 36 Epson Research and Development Vancouver Design Center Address R G B Address R G B Address R G
30. Build for CEPC X86 on Windows CE Platform Builder 3 00 using the GUI Interface S1D13504 X19A E 006 01 1 Install Microsoft Windows 2000 Professional or Windows NT Workstation version 4 0 with Service Pack 5 or later Install Windows CE Platform Builder 3 00 Start Platform Builder by double clicking on the Microsoft Windows CE Platform Builder icon Create a new project a Select File New b In the dialog box select the Platforms tab c Inthe platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform and set the Processors to Win32 WCE x86 d Click the OK button e In the dialog box WCE Platform Step 1 of 2 select CEPC f Click the Next button g Inthe dialog box WCE Platform Step 2 of 2 select Minimal OS Minkern h Click the Finish button jmi o In the dialog box New Platform Information click the OK button Set the active configuration to Win32 WCE x86 Release a From the Build menu select Set Active Configuration b Select MYPLATFORM Win32 WCE x86 Release c Click the OK button Add the environment variable CEPC_DDI_S1D13X0X a From the Platform menu select Settings b Select the Environment tab c Inthe Variable box type CEPC_DDI_S1D13X0X Windows CE 3 x Display Drivers Issue Date 01 05 08 Epson Research and Develop
31. Page 4 1 1 Conditions Epson Research and Development Vancouver Design Center The Table 1 1 S1D13504 Total Power Consumption below gives an example of a particular environment and its effects on power consumption Table 1 1 S1D13504 Total Power Consumption Test Condition a dea Total Power Consumption Core Vpp 3 3V IO Vpp 5 0V y Power Save Mode ISA Bus 8MHz sorora Active Software Hardware Input Clock 6MHz Black and White 38 7mW 1 LCD Panel Connected 320x240 Monochrome 4 Grays 43 9mW 20mw 7 59uW 16 Grays 46 8mW Input Clock 6MHz 4 Colors 44 4mW 2 LCD Panel Connected 320x240 Color 16 Colors 49 7mW 20mw 7 59uW 256 Colors 51 2mW Input Clock 25MHz i 3 LCD Panel Connected 640x480 Monochrome P ack and White oom 24mw 7 59uW 16 Grays 124 6mW Input Clock 25MHz 16 Colors 145 6mW 4 LCD Panel Connected 640x480 Color 256 Colors 150 6mW 24mw 7 59uW 64K Colors 150 0mW Note 1 Conditions for Software SUSPEND e CPU interface active signals toggling e CLKI active 6MHz e Self Refresh DRAM 2 Conditions for Hardware SUSPEND e CPU interface inactive high impedance e CLKI stopped e Self Refresh DRAM 2 Summary The system design variables in Section 1 S1D13504 Power Consumption and in Table 1 1 S1D13504 Total Power Consumption show that S1D13504 power consumption depends on the specific implementation Active Mode power con
32. REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debug ging 3 1 Generic MPU Host Bus Interface Pin Mapping 1D13504 X19A G 009 05 The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping Eee iss Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to lO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the PC Card Bus Issue Date 01 02 02 Epson Research and Development Page 11 Vancouver Design Center 3 2 Generic MPU Host Bus Interface Signals The Generic MPU host bus interface requires the following signals BUSCLK is a clock input which is required by the S1D13504 host bus interface It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset M R memory reg
33. This document is updated as appropriate Please check for the latest revision of this document before beginning any development The latest revision can be downloaded at www erd epson com We appreciate your comments on our documentation Please contact us via email at documentation erd epson com S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual 1D13504 Issue Date 2002 12 02 X19A G 014 01 Page 8 2 Features 1D13504 X19A G 014 01 Epson Research and Development Vancouver Design Center The S5U13504B00C features the following S1D13504 Color LCD controller chip PCI bus operation using on board PCI bridge Headers for connecting to a 3 3V host bus interface 5V host bus interface also possible with modifications to the board 1Mx16 EDO DRAM Configuration options Headers for S1D13504 current consumption measurements Adjustable positive LCD bias power supplies from 24V to 40V Adjustable negative LCD bias power supplies from 23V to 14V 4 8 bit 3 3V or 5V monochrome passive LCD panel support 4 8 16 bit 3 3V or 5V color passive LCD panel support 9 12 18 bit 3 3V or 5V TFT D TFD LCD panel support Software initiated Power Save Mode S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 Epson Research and Development Page 9 Vancouver Design Center 3 Installation and Configuration The S5U13504B00C is designed to support as many platforms as possible The S53U13504B00C inc
34. image in the display buffer Note that this is a word address An entry of 0000h into these registers represents the first word of display memory an entry of 0001h represents the second word of display memory and so on See Section 10 Display Configuration on page 115 for details Screen 2 Display Start Address Register 0 RW REG 13h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Screen 2 Display Start Address Register 1 REG 14h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Screen 2 Display Start Address Register 2 REG 15h RW a ia Ala n Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16 REG 13h bits 7 0 REG 14h bits 7 0 REG I5h bits 3 0 Screen 2 Start Address Bits 19 0 This register forms the 20 bit address for the starting word of the screen 2 image in the display buffer Note that this is a word address An entry of 0000h into these registers represents the first word of display memory an entry of 0001h represents the second word of display memory and so on See Section 10 Display Configuration on page 115 f
35. ltem Qty board Designation Part Value Description 30 4 U2 UPD4218S165LE 50 NEC 1Mx16 EDO Self Refresh DRAM SOJ package 31 1 U3 TIBPAL22V10 15BCNT Texas Instrument PAL 24 pin DIP package socketed 32 1 U4 Osc 14 Fox 40 0MHz Oscillator or equiv 14 pin DIP socketed 33 1 U5 7418125 14 pin SO 14 package 34 4 U6 BT481A BrookTree RAMDAC PLCC package 44 pin PLCC SMT part 35 1 U7 RD 0412 XENTECK Positive Power Supply 36 1 U8 EPNOO1 XENTECK Negative Power Supply 37 4 U9 LP2960AIN 3 3 National 3 3V Fixed Voltage Regulator N16G 16 PIN DIP package S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 S1D13504 X19A G 004 06 Vancouver Design Center Epson Research and Development Page 20 8 Schematic Diagrams z z E p r ES Ze Ge TOQUES TEPION g x or a nou Jequny wewnsog ezs wig oe as pleog uopenjeng 0 1 A94 Sg YSI OooaPasELNSs a EN o ONI ININ d073A30 ONY HOHYIS3Y NOSd3 arde EN A 9 SSA y ssa St neo age ssa 0b ssa ssa 2 ssa HE ssa ssa HS isuova soido isuova ssa E osuova aot soidorosuova q umova a soldomunova gant auova S sorgo tarova aanoi S INS aanoi E OLA aooi o anoi En Pr ont zor ynoova MODA
36. operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seSetLutEntry int device BYTE index BYTE pEntry Description Writes one LUT entry Parameter device registered device ID index index to LUT entry 0 to 15 pEntry pointer to an array of BYTE entry 3 entry x 0 RED component entry x 1 GREEN component entry x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGet15Bppinfo int device unsigned RedMask unsigned GreenMask unsigned BlueMask Description Determines the bit fields for the red green and blue components of a 15 bpp stored ina WORD Parameter device registered device ID RedMask all bits set to 1 are used by the red component GreenMask all bits set to 1 are used by the green component BlueMask all bits set to 1 are used by the blue component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 50 Epson Research and Development Vancouver Design Center 8 2 4 Drawing int seDrawLine int device int x1 int y1 int x2 int y2 DWORD color Description Draws a line on the display Parameter device registered device ID x1 y1 top left corner of line x2 y2 bottom right corner of line see note
37. tmp and the files Makefile s1d13xxxfb c s1d13504 h should be located in a sub directory called epson within the temporary directory tmp epson 3 Copy the console driver files to the build directory Make the directory usr src linux drivers video epson Copy the files tmp epson s 1d13xxxfb c tmp epson s1d13504 h tmp epson Makefile to the directory usr src linux drivers video epson 1D13504 X19A E 004 01 Page 8 1D13504 X19A E 004 01 Epson Research and Development Vancouver Design Center Copy the remaining source files tmp Config in tmp fbmem c tmp fbcon cfb4 c tmp Makefile into the directory usr src linux drivers video replacing the files of the same name If your kernel version is not 2 4 5 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names Modify s1d13504 h The file s1d13504 h contains the register values required to set the screen resolution color depth bpp display type display rotation etc Before building the console driver refer to the descriptions in the file s1d13504 h for the default settings of the console driver If the default does not match the configura tion you are building for then s1d13504 h will have to be regenerated with the correct information Use the program 13504DCFG to generate the required header file For information on how t
38. 1 For split screen on a dual panel Split screen vertical size in number of lines ContentsOfThisRegister 1 if ContentsOfThisRegister lt OOEFh Note or Split screen vertical size in number of lines ContentsOfThisRegister 2 if ContentsOfThisRegister gt OOEFh For further details see Section 10 2 Image Manipulation on page 117 and the 1D13504 Pro gramming Notes and Examples document number X19A G 002 xx Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 99 Vancouver Design Center Screen 1 Display Start Address Register 0 REG 1 0h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Screen 1 Display Start Address Register 1 REG 1 1h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Screen 1 Display Start Address Register 2 REG 12h RW Wa na ia na Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16 REG 10h bits 7 0 REG I 1h bits 7 0 REG 12h bits 3 0 Screen 1 Start Address Bits 19 0 This register forms the 20 bit address for the starting word of the screen
39. 3 3 C20 C21 C30 0 1uF 0 1uF 1206 package 4 3 C23 C25 10uF 63V Electrolytic Radial LXF63VB10RM5X11LL 5 3 C22 C26 C27 56uF 35V LXF35VB56RM6X11LL 6 1 C29 33uF 33uF 10V Tantalum D Size TO 92 PTH Zener Diode 0 1 spc 7 1 A Ae AURA 3 pin TO 92 package 8 6 D1 D6 1N4148 Signal Diode PTH 9 3 JP1 JP3 1 x 3 Male Header PTH include 2 pin jumper shunt 10 2 H1 H2 CON34A Male Header 0 1 2x 17 Male Header 11 1 J5 PS 2 CONNECTOR Assman A HDF 15 A KG T or equivalent 12 1 J6 CON40A Shrouded Header 40 pin Dual row center key PTH 13 8 L1 L5 L7 L9 Ferrite Bead Fair rite 2743001111 PTH 14 1 L6 1uH Dale Inductor IM 4 1 0uH PTH 15 1 Q1 2N3906 PNP Signal Transistor TO 92 PTH 16 1 Q2 2N3903 NPN Signal Transistor TO 92 PTH 17 9 i me 6 R18 Nok 10K Ohm 1206 5 18 1 R27 182 182 Ohm PTH 1 19 3 R26 R33 R34 1K 1K Ohm 1206 5 R17 R20 R22 20 6 R28 R29 39 39 Ohm 1206 5 21 3 R23 R25 150 150 Ohm 1206 5 22 8 R2 R9 15K 15K Ohm 1206 5 23 3 R1 R35 R36 100K 100K Ohm 1206 5 100K Ohm Trim POT 24 1 RS 100 Spectrol 63S104T607 or equivalent 25 1 R30 470K 470K Ohm 1206 5 200K Ohm Trim POT 26 1 ne 200K Spectrol 635204T607 or equivalent 27 1 R32 14K 14K Ohm 1206 1 28 1 S1 SW DIP 5 Switch DIP 5 position 29 1 U1 S1D13504F00A QFP15 128 128 pin 1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Vancouver Design Center Page 19
40. 4 pp MHz s Panel CRT e Single Panel 2 1 2 4 8 32 80 60 800x600 CRT 16 56 78 60 e Dual Monochrome Color Panel 12 with Half Frame Buffer Disabled 640x480 ven ae 88 Simultaneous CRT Single Panel 16 56 119 85 e Si 1 2 4 8 32 247 50ns Simultaneous CRT Dual 640x240 40 EDO DRAM Monochrome Color Panel with Half 16 56 242 Frame Buffer Disabled 1 2 4 8 32 243 MClk 40MHz 480x320 16 56 232 Nac 4 Nap 1 5 aaa 1 2 4 8 32 471 x Neo 2 16 56 441 Dual Color with Half Frame Buffer 800x6003 1 2 4 8 20 32 80 X y ae ith Half Frame Buff ice ce Dual Mono with Half Frame Buffer Enabled 640x480 1 2 4 8 20 32 123 16 13 3 32 82 Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 120 Epson Research and Development Vancouver Design Center Table 11 3 Example Frame Rates Color Maximum Minimum Maximum Frame 1 DRAM Type Display Resolution Depth mixe Panel Rate Hai Speed Grade bpp Clock HNDP T 4 pp MHz s Panel CRT e Single Panel 2 1 2 4 8 32 66 55 800x600 e CRT 16 56 65 55 e Dual Mono Color Panel with Half Frame Buffer Disabled 640x480 vere En 191 18 e Simultaneous CRT Single Panel 16 56 98 78 e Si 1 2 4 8 32 203 60ns ll bs CRT Dual 640x240 33 EDO DRAM ono Color Panel with Half Fra
41. 6400 0000h 64M byte Card 2 Memory When the PR31500 PR31700 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CARD2IOEN are ignored and the attribute IO space of the PR31500 PR31700 is divided into Attribute IO and S1D13504 access Table 5 2 PR31500 PR31700 to PC Card Slots Address Remapping using the IT8368E provides all the details of the Attribute IO address re allocation by the IT8368E Table 5 2 PR31500 PR31700 to PC Card Slots Address Remapping using the IT8368E IT8368E Uses PC Card Slot Philips Address Size Function 0800 0000h 16M byte Card 1 IO S1D13504 registers 0900 0000h 8M byte aliased 131 072 times at 64 byte intervals 1 S1D13504 display buffer 0980 0000h 8M byte aliased 4 times at 2Mb intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 lO S1D13504 registers 0D00 0000h 8M byte l aliased 131 072 times at 64 byte intervals 2 1D13504 display buffer 0D80 0000h 8M byte aliased 4 times at 2Mb intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory Interfacing to the Philips MIPS PR31500 PR31 700 Processor 1D13504 Issue Date 01 10 26 X19A G 005 09 Page 20 5 5 S1D13504 Configuration Epson Research and Development Vancouver Design Center The S1D13504 latches MD15 through MDO to allow selection of the bus mode and other
42. 77 Specification 1D13504 X19A A 002 19 Page 10 Epson Research and Development Vancouver Design Center Figure 7 33 Dual Color 8 Bit Panel Timing 78 Figure 7 34 Dual Color 8 Bit Panel A C Timing 79 Figure 7 35 Dual Color 16 Bit Panel Timing 0 0 000 000 0000 80 Figure 7 36 Dual Color 16 Bit Panel A C Timing 81 Figure 7 37 16 Bit TFT Panel Timing 82 Figure 7 38 TFT A C Timing 0 000 002 0000 000000002000 00 008 83 Figure 72397 CRT Timing aca rs e ee eb ya IAS ene ek 85 Figure 7 40 CRTA C Timing 3 Pe el hee ge Ge wh a RA A eae ora 86 Figure 7 41 Generic Bus RAMDAC Read Write Timing e 88 Figure 9 1 Display Buffer Addressing 0 2000000000000 000000 113 Figure 10 1 1 2 4 8 Bit Per Pixel Format Memory Organization 00 115 Figure 10 2 15 16 Bit Per Pixel Format Memory Organization 000 116 Figure 10 3 Image Manipulation 2 2 2 0 2000000000022 22 eee ee 117 Figure 12 1 1 Bit Per Pixel 2 Level Gray Shade Mode Look Up Table Architecture 121 Figure 12 2 2 Bit Per Pixel 4 Level Gray Shade Mode Look Up Table Architecture 122 Figure 12 3 4 Bit Per Pixel 16 Level Gray Shade Mode Look Up Table Architecture 122 Figure 12 4 1 Bit Per Pixel 2 Level Color Look Up Table Architecture 123 Figure 12 5 2 Bit Per Pixel 4 Level Color Mode Loo
43. AB 20 1 FPDAT 15 8 p UD 7 0 D 15 0 gt DB 15 0 i oo FPDAT 7 0 _ L 7 0 FPSHIFT p Fpsuirt 4 8 16 bit LDS P ABOH S1 D1 3504 LOD uDS pl wets FPFRAME FPFRAME Display ASE pesi FPLINE FPLINE R W P RD WR e Ki DTACK ie WAIT LCDPWR BCLK gt BUSCLK RESET P RESET A 11 0 47 MA 11 0 D 15 0 gp MD 15 0 WE d we RAS kg RAS LCAS LCAS UCAS UCAS x D U lt zL m D 0 3 gt lt Figure 3 2 Typical System Diagram MC68K Bus 1 1Mx16 FPM EDO DRAM 16 Bit MC68000 S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Page 15 MC68030 BUS A 81 21 FCO FC1 A 20 0 D 31 16 DS AS R Wit SIZ1 SIZO DSACK1 BCLK RESET Power Oscillator Management a Y P Decoder O p M R z a W a 2 L p Decoder 0 CS a PAB L200 FPDAT 15 8 p DB 15 0 4 DB 15 0 FPDAT 7 0 FPSHIFT gt gt WEIR gt Bst S1D13504 FPFRAME gt Pi RD WR ADE FPLINE Pp DRY P WEO 4 WAIT LCDPWR 2 gt BUSCLK A a 3 3 P RESET 3 2 9 UDI7 0 LD 7 0 FesHirT 4 8 16 bit LCD FPFRAME Display FPLINE MOD JT 2 it UCAS UCAS lt X 256Kx16
44. About 13504DCFG Selecting the About 13504DCFG option from the Help menu displays the about dialog box for 13504DCFG The about dialog box contains version information and the copyright notice for 13504DCFG S1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Epson Research and Development Page 23 Vancouver Design Center Comments It is possible to override recommended register settings and select incorrect timings using 13504DCFG Seiko Epson does not assume liability for any damage done to the display device as a result of configuration errors On any tab particular options may be grayed out if selecting them would violate the operational specification of the 1D13504 i e Selecting extremely low CLKI frequen cies on the Clocks tab may result in no possible CRT options Selecting TFT or STN on the Panel tab enables disables options specific to the panel type The file panels def is a text file containing operational specifications for several supported and tested panels This file can be edited with any text editor 13504DCFG allows manually altering register values The manual changes may violate memory and LCD timings as specified in the 1D 3504 Hardware Functional Specifi cation document number X19A B 001 xx If this is done unpredictable results may occur Epson Research and Development Inc does not assume liability for any damage done to the display device as a result of conf
45. Click on OK to regenerate project file dependencies for All Project files Right click on Sbpp files and select ReBuild All vxWorks to build VxWorks 9 Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13504 8bpp default vx Works or x 13504 16bpp default vx Works to the bootable disk created in step 4 10 Start the VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO auto matically Wind River UGL v1 2 Display Drivers 1D13504 Issue Date 01 02 01 X19A E 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Wind River UGL v1 2 Display Drivers X19A E 003 02 Issue Date 01 02 01 EPSON 1D13504 Color Graphics LCD CRT Controller Linux Console Driver Document Number X19A E 004 01 Copyright 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered
46. Example Timing for 640x480 panel VDP Vertical Display Period VNDP Vertical Non Display Period HDP Horizontal Display Period HNDP Horizontal Non Display Period 1D13504 X19A A 002 19 Figure 7 37 16 Bit TFT Panel Timing REG O9h bits 1 0 REG O8h bits 7 0 1 REG OAh bits 5 0 1 REG 04h bits 6 0 1 8Ts REG O5h bits 4 0 1 8Ts HNDP HNDP gt Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Page 83 t8 FPFRAME FPLINE gt 112 t6 FPLINE DRDY t7 t17 t15 t11 t16 FPSHIFT R 5 1 G 5 0 640 B 5 1 Note DRDY is used to indicate the first pixel Hardware Functional Specification Issue Date 01 11 06 Figure 7 38 TFT A C Timing S1D13504 X19A A 002 19 Page 84 Epson Research and Development Vancouver Design Center Table 7 28 TFT A C Timing Symbol Parameter Min Typ Max Units t1 FPSHIFT period 1 Ts note 1 t2 FPSHIFT pulse width high 0 45 Ts t3 FPSHIFT pulse width low 0 45 Ts t4 data setup to FPSHIFT falling edge 0 45 Ts t5 data hold from FPSHIFT falling edge 0 45 Ts t6 FPLINE cycle time note 2 t7 FPLINE pulse width low note 3 t8 FPFRAME cycle time note 4 t9 FPFRAME pulse widt
47. LUT Address Bits 3 0 These 4 bits provide a pointer into the 16 position Look Up Table currently selected for CPU read write access The Look Up Table configuration e g 1 2 4 banks does not affect the read write access from the CPU as all 16 positions can be accessed sequentially Look Up Table Data Register REG 26h RW a aa na Ha LUT Data LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 Bit 0 bits 3 0 LUT Data Bits 3 0 These 4 bits are the gray shade color values used for display data output They are programmed into the 4 bit Look Up Table positions pointed to by LUT Address bits 3 0 and RGB Index bits 1 0 if in color display modes For example in a 16 level gray shade display mode a data value of 0001b 4 bits per pixel will point to Look Up Table position one and display the 4 bit gray shade corresponding to the value programmed into that location 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 111 Vancouver Design Center Look Up Table Bank Select Register REG 27h RW TA Ala Red Bank Red Bank Blue Bank Blue Bank Green Bank Green Bank Select Bit 1 Select BitO Select Bit 1 Select BitO Select Bit 1 Select Bit 0 bit 5 4 Red Bank Select Bits 1 0 In 2 bpp mode the 16 position Red LUT is arranged into four 4 position banks These two bits control which bank is currently select
48. MD4 Little Endian Big Endian MD5 WAIT is active high 1 insert wait state WAIT is active low 0 insert wait state Memory Address GPIO configuration 00 symmetrical 256Kx16 DRAM MAJ 8 0 DRAM address MA 11 9 GPIO 2 1 and GPIO3 MD 7 6 01 symmetrical 1Mx16 DRAM MA 9 0 DRAM address MA 11 10 GPIO 2 1 10 asymmetrical 256Kx16 DRAM MA 9 0 DRAM address MA 11 10 GPIO 2 1 11 asymmetrical 1Mx16 DRAM MA 11 0 DRAM address Configure DACRD BLANK DACPO DACWR Configure DACRD BLANK DACPO DACWR MD8 DACRSO DACRS1 HRTC VRTC as General DACRSO DACRS1 HRTC VRTC as DAC and CRT Purpose IO GPIO 11 4 outputs MD9 SUSPEND pin configured as GPO output SUSPEND pin configured as SUSPEND input MD10 Active low LCDPWR or GPO polarities Active high LCDPWR or GPO polarities MD 15 11 Not used S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 31 Vancouver Design Center 5 6 Multiple Function Pin Mapping Table 5 9 Host Bus Interface Pin Mapping tae SH 3 MC68K Bus 1 MC68K Bus 2 Generic MPU AB 20 1 A 20 1 A 20 1 A 20 1 A 20 1 ABO AO LDS AO AO DB 15 0 D 15 0 D 15 0 D 31 16 D 15 0 WE1 WE1 UDS DS WE1 M R External Decode External Decode External Decode External Decode CS CSn External Decode External Decode External Decode BUSCLK CKIO CLK CLK BCLK BS BS
49. OxFF pr TITIL IATA ey pRegs 0x0F 0x03 0000 0011 Registers 10 12 Screen 1 Display Start Address start at the EA first byte in display memory xf pRegs 0x10 0x00 0000 0000 pRegs 0x11 0x00 0000 0000 pRegs 0x12 0x00 0000 0000 Register 13 15 Screen 2 Display Start Address not applicable ER unless setting up for split screen operation Ey pRegs 0x13 0x00 0000 0000 pRegs 0x14 0x00 0000 0000 pRegs 0x15 0x00 0000 0000 S1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 59 Vancouver Design Center Register 16 17 Memory Address Offset this address represents the E starting WORD At 8BPP our 320 pixel width is 160 EX WORDS 7 pRegs 0x16 OxA0 1010 0000 pRegs 0x17 0x00 0000 0000 x Register 18 Pixel Panning tl pRegs 0x18 0x00 0000 0000 Register 19 Clock Configuration In this case we must divide R MCLK by 4 to arrive at the best frequency to set EA our desired panel frame rate a pRegs 0x19 0x03 0000 0011 Register 1A Power Save Configuration enable LCD power CBR refresh es not suspended Er pRegs 0x1A 0x00 0000 0000 Register 1C 1D MD Configuration Readback don t write anything to KR t
50. Page 12 Epson Research and Development Vancouver Design Center The host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock This gives the system designer full flexibility in choosing the appropriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 4 2 Memory Mapping and Aliasing S1D13504 X19A G 012 05 The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers This is divided into two address ranges by connecting A23 demultiplexed from the TX3912 to the M R input of the S1D13504 Using A23 makes this implemen tation software compatible with the two implementations that use the ITE IT8368E see Section 5 System Design Using the IT8368E PC Card Buffer on page 14 All other addresses are ignored The S1D13504 address ranges as seen by the TX3912 on the PC Card slot 1 memory space are as follows e 6400 0000h S1D13504 registers aliased 131 072 times at 64 byte intervals over 8M bytes e 6480 0000h S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M bytes e 6500 0000h S1D13504 registers and display bu
51. Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SPLT Display Utility X19A B 003 05 Issue Date 01 01 30 EPSON 1D13504 Color Graphics LCD CRT Controller 13504VIRT Display Utility Document Number X19A B 004 05 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504VIRT Display Utility X19A B 004 05 Issue Date 01 01 30 Epson Research and Development Page 3 Vancouver Design Center 13504VIRT 13504VIRT shows the virtual display capability of the 1D13504 A virtual display is where the image to be displayed is larger than the physical display device CRT or LCD and can be viewed by panning and scrolling 13504 VIRT allows the display device to be used as a window to
52. Please contact us via email at techpubs Oerd epson com Interfacing to the PC Card Bus 1D13504 Issue Date 01 02 02 X19A G 009 05 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most micro processors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topic
53. REG O5h bits 4 0 1 8Ts 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 73 Vancouver Design Center Sync Timing l 4 t FPFRAME l gt t4 4 8 gt FPLINE t5 MOD Data Timing FPLINE t6 t8 t9 t7 t14 t11 tio gt FPSHIFT t12 t13 UD 3 0 T LD 3 0 Figure 7 28 Single Color 8 Bit Panel A C Timing Format 2 Table 7 23 Single Color 8 Bit Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 2 t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 UDI3 0 LD 3 0 setup to FPSHIFT falling edge 1 Ts t13 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge 18 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 timin t8min 9Ts 3 t3min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 33
54. Restore the Horizontal and Vertical resolution registers to their original values 5 Disable Software Suspend 6 Enable the Display FIFO Shortening the 128 Frame Delay using Hardware SUSPEND Due to the fact that the registers can not be programmed in Hardware Suspend Mode the following routine must be followed to shorten the delay 1 Disable the Display FIFO blank the screen 2 Change the Horizontal and Vertical resolutions to the minimum values as allowed by the registers Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 32 Epson Research and Development Vancouver Design Center 3 Enable Hardware Suspend this same 128 frame delay still applies however the actual frame period is now greatly reduced 4 Disable Hardware Suspend 5 Restore the Horzontal and Vertical resolution registers to their original values 6 Enable the Display FIFO 5 4 2 Suspend Disable Sequence Disable Suspend either REG 1A bit 0 0 or SUSPEND pin inactive LCDPWR and FPFRAME will start within 1 frame while the remaining LCD interface signals will start immedi ately 5 5 LCD Enable Disable Sequencing Reg 0D bit 0 In an LCD only product the LCD Enable bit should only be disabled automatically by using a Power Save Mode In a product having both a CRT and LCD this bit will need to be controlled manually examples for both situations are given below LCD Enable Disable using Power Save Modes
55. S1D13504 X19A A 002 19 Page 38 7 1 2 MC68K Bus 1 Interface Timing e g MC68000 Epson Research and Development Vancouver Design Center CLK i A 20 1 J TE M R CS AS UDS LDS R W DTACK D 15 0 write t11 t12 t13 t14 t15 D 15 0 read 1D13504 X19A A 002 19 Figure 7 2 MC68K Bus I Interface Timing Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Table 7 2 MC68K Bus 1 Interface Timing Page 39 Symbol Parameter Min Max Units t1 Clock period 30 ns t2 Clock pulse width high 5 ns t3 Clock pulse width low 5 ns t4 A 20 1 M R setup to first CLK where CS 0 AS 0 and 4 ns either UDS 0 or LDS 0 t5 A 20 1 M R hold from AS 0 ns t6 CSH hold from ASH 0 ns t7 R W setup to before to either UDS 0 or LDS 0 5 ns t8 R W hold from ASH 0 ns 19 AS 0 and CS 0 to DTACK driven high 1 ns t10 ASK high to DTACK high impedance 1 5 ns t11 D 15 0 valid to second CLK where CS 0 AS 0 and either 0 ne UDS 0 or LDS 0 write cycle t12 D 15 0 hold from falling edge of DTACK write cycle 0 ns t132 Falling edge of UDS 0 or LDS 0 to D 15 0 driven read 3 ne cycle t14 D 15 0 valid to DTACK
56. SNId Ol 9 y4 11038 8Xld 48d Slg JO 18qUNN a Aeidsiq Snosueiinus anv ARY ae ae yaLSI93y 300W Avidsiq yao Su Ze ZH 8 9607 OLL Byuod Ol Byuoo Ol Byuoo ol 6yuoo Ol Byuoo ol Byuoo Ol Byuoo Ol Syuoo Ol Ma Bienen ee uld OOIJD Uld LOldD Uld ZOldD Uld OIdD UldvOIdD Uld GOldD Uld 9Oldd Uid LOldD sug ZH 9L eos LOL MY 0 H3LSID3Y NOILVHNDISNOD SNid Ol 1V43N39 y311938 018 Lug zug eu ej eu Kurejod AeJod sw g ZHJ 20 00 1 038 UYIPIM SSINA SWWH4dS OLYA 3 NVdux3d3 OLA su y ZH 99 zis LLO snes snjels Snes snjels snes seis snes snjels MY 83151938 HLGIM 3S1Nd SAWVH4d4 OLYA 490 934 saw San oran HAN Zaw clan YaN SLAN sw Z 3 HY 084 952 010 oy U31SIDIH A9VEAVIH NOLLVSNDIINOY GW Ya 1038 018 hig zug ena yua Sue su ZH 093 8zi 400 i 9 j i eju eju 1 994 uonisod UBIS AWVHsds OLYA su Gt z snel snye sne Sne sme snye snel sme so HA 029 9 000 1e1S oan sneis LAW snis zan smes ean saas pan sneis san sneis ea p s Zan ma A AN SOJI D 9GZ QWIL 19 o z sua Oy 0 HaLSIDaY MOVEGVAY NOLLVENDIINOY GW Y 1 038 useyey NYHA ZHINEE 104 ole Useyey JUNouIY PING DATO ayey yseyoy 018 Lua eid erg vig Sua eju Oy snes ajqesi aiqesi a A ei ley yselJey Vd na eju eju eu eu eju eju AERE 1 938 JONA Ponad Aejdsig uoN IUA daNA pasn uSAID ssaippe 134S 0 1 19yDly ay pue snq Eep dO awed JeH 1SOH ay o 4 q YBIy ay 0 pajoauuoo aq pinoys OYGWVH 84 UeIpUZ Big Buisn uayM pasn uaniB ssaippe 1e siBal Ma
57. Width dword 280 Height dword 1E0 Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 Windows CE 3 x Display Drivers Issue Date 01 05 08 Epson Research and Development Page 9 Vancouver Design Center 10 Delete all the files in the x wince300 release directory and delete the file x wince300 platform cepc bif 11 Type BLDDEMO lt ENTER gt at the command prompt to generate a Windows CE image file The file generated will be x wince300 release nk bin Windows CE 3 x Display Drivers 1D13504 Issue Date 01 05 08 X19A E 006 01 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK BIN file is built the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC after booting from a floppy drive a Create a bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain only the following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to ca f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE
58. and active TFT panel types Several options may change or become unavailable when the STN TFT setting is switched Therefore confirm all settings on this tab after the Panel Type is changed 13504DCFG Driver Configuration Program S1D13504 Issue Date 01 10 26 X19A B 008 03 Page 16 Format 2 Panel Data Width Mono Color Single Dual Half Frame Buffer Enable FPLINE Polarity FPFRAME Polarity Panel Dimensions 1D13504 X19A B 008 03 Epson Research and Development Vancouver Design Center Selects the data format for color STN panel Data Format 2 This option is only available for configuring 8 bit color STN panels See the 1D13504 Hardware Functional Specification document number X19A B 001 xx for description of Data Format 1 Data Format 2 Most panels use Data Format 2 Selects the panel data width Panel data width is the number of bits of data transferred to the LCD panel on each clock cycle and shouldn t be confused with color depth which determines the number of displayed colors When the panel type is STN the available options are 4 bit 8 bit and 16 bit When the panel type is TFT the available options are 9 bit 12 bit and 18 bit Selects between a monochrome or color panel Selects between a single or dual panel When the panel type is TFT Single is automatically selected and the Dual option is grayed out The Half Frame Buffer is used with dual STN panels to improve i
59. at maximum MCLK frequencies Table 8 14 Optimal Ngc Npp and Nrcp Values at Maximum MCLK Frequency Page 109 DRAM Type DRAM Speed Tm Nec Npp Nercp ns ns MCLK MCLK MCLK 50 25 4 1 5 2 EDO 60 30 4 1 5 2 70 33 5 2 2 60 40 4 1 5 2 PRN 70 50 3 1 5 1 bit 0 Reserved Must be set to 0 Performance Enhancement Register 1 REG 23h Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO manne n a n a Threshold Threshold Threshold Threshold Threshold Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 7 Display FIFO Disable When this bit 1 the display FIFO is disabled and all data outputs are forced to zero i e the screen is blanked This allows the S1D13504 to be dedicated to service CPU to memory accesses When this bit 0 the display FIFO is enabled bits 4 0 Display FIFO Threshold Bits 4 0 Hardware Functional Specification These bits should be set to a value of 10h upon initialization as this provides the best overall perfor mance for all display modes Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 110 Epson Research and Development Vancouver Design Center 8 2 8 Look Up Table Registers The S1D13504 has three internal 16 position 4 bit wide Look Up Tables The 4 bit value programmed into each table position determines the color weighting of display data the output gray shade is derived from the Green Look U
60. ee 102 8 2 8 Look Up Table Registers 00000000000 000 110 1D13504 X19A A 002 19 Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 5 Vancouver Design Center 8 2 9 External RAMDAC Control Registers o e e 111 9 Display Butte iio A A A ee ee ie Oe AS 113 O TmagerB lltrs E los ee e a a or A 92 HalfiFrame B lter du gee ai doia ta See da eed di at a it L A 10 Display Configuration E E a E a o a e a 115 10 1 Display Mode Data Format a a aaa DS 10 2 Image Manipulation 2 aaa 117 AT CIOCKING hein ch eek aio ah get la Mie ccs Geant A tidal ate Aan da Aa eae Bs eae tt da cee Se EE 118 11 1 Maximum MCLK PCLK Ratios a a 2 ee 118 11 2 Frame Rate Calculation 2 2 ee 119 12 Look Up Table Architecture mm a 121 12 1 Gray Shade Display Modes 2 ee 121 122 Color Display Modes rica a ta o ei 28 13 Power Save Modes oo o 1 4 4 0 2 4 4 4 127 13 1 Hardwate Suspend mocs aian Asa he a A a ee a a ke ee oe AT 13 2 Software Suspend cs oa 7S Ae Sashes OBO He BI AR OE a ee ee oe ee LF 13 3 Power Save Mode Function Summary 2 2 128 13 4 Pin States in Power Save Modes 2 ee 128 14 Mechanical Data Asi ccs we ir A AA A a A ee 129 14 1 QFP15 128 S1DISSO4RODA oo rc gs aoe ek a
61. high to WAIT high impedance 1 ns t6 WEO WE1 low to D 15 0 valid write cycle 20 ns t7 D 15 0 hold from WEO WE1 high write cycle 0 ns t8 RDO RD1 low to D 15 0 driven read cycle 3 15 ns t9 D 15 0 valid to WAIT high read cycle 0 t10 RDO RD1 high to D 15 0 high impedance read cycle 2 10 1 If the S1D13504 host interface is disabled the timing for WAIT driven low is relative to the falling edge of CS or the first positive edge of BCLK after A 20 0 and M R become valid whichever occurs later 2 If the S1D13504 host interface is disabled the timing for D 15 0 driven is relative to the fall ing edge of RDO RD 1 or the first positive edge of BCLK after A 20 0 and M R become valid whichever occurs later Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 46 Epson Research and Development Vancouver Design Center 7 2 Clock Input Requirements Clock Input Waveform PWH gt tpwL Vi VIL lt Terki gt Figure 7 6 Clock Input Requirements Table 7 6 Clock Input Requirements Symbol Parameter Min Typ Max Units Toki Input Clock Period CLKI 12 5 ns TrcLk Pixel Clock Period PCLK not shown 25 ns TmucLk Memory Clock Period MCLK not shown 25 ns town Input Clock Pulse Width High CLKI 45 55 Tek tow Input Clock Pulse Width Low CLKI 45 55 Tek Note When CLKI is m
62. in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected The physical address of the start of display buffer decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected Selects the Host CPU Data Bus width 13504DCFG Driver Configuration Program Issue Date 01 10 26 Epson Research and Development Page 9 Vancouver Design Center Preferences Tab 51D13504 Configuration Utility Build 3 The Preference tab contains settings pertaining to the initial display state During runtime the display surface or color depth may be changed by software Initial Display Sets which display device is used for the initial display Selections made on the CRT and Panel tabs may cause selections on this tab to be grayed out The selections None and Panel are always available Panel Color Depth Sets the initial color depth on the LCD panel 13504DCFG Driver Configuration Program S1D13504 Issue Date 01 10 26 X19A B 008 03 Page 10 Memory Tab Epson Research and Development Vancouver Design Center 51D13504 Configuration Utility Build 3 1 MCLK R W Delay Suspend Mode The Memory tab contains settings that control the configuration of the DRAM used for the The memory type and access time determines the optimal memory clock Access Tim
63. o 0 00000 00 00000002 97 Table 8 8 Pixel Panning Selecti0n ee 100 Table 8 9 PCLK Divide Selection 2 000 002 0000 0020000020004 101 Table 8 10 Suspend Refresh Selection e 101 Table 8 11 Minimum Memory Timing Selection 0 2 2 2 00002000 107 Table 8 12 RAS to CAS Delay Timing Select o o e 108 Table 8 13 RAS Precharge Timing Select e 108 Table 8 14 Optimal NRC NRP and NRCD Values at Maximum MCLK Frequency 109 Table 8 15 RGB Index Selection 0 2000000000000 000000000000 110 Fable 9 1 S1D13504 Addressing ebay E 113 Table 11 1 Maximum PCLK Frequency with EDO DRAM 0 00 0 118 Table 11 2 Maximum PCLK Frequency with FPM DRAM 2 2 2 000 118 Table 11 3 Example FrameRates ee 119 Table 12 1 Look Up Table Configurations 20 000000000000 00000 4 121 Table 13 1 Power Save Mode Function Summary 0 2 00 00000200000 128 Table 13 2 Pin States in Power Save Modes 2 20 0 000000 000002 eee eee 128 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 4 1 Figure 5 1 Figure 5 2 Figure 5 3 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7
64. pulse width 0 45 t1 0 55t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 1t1 ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t10 RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge time REG 22h bits 3 2 10 1t1 1 ns REQ 22h bit 4 0 and bits 3 2 00 or 10 gi el t11 RAS to CASH delay time 1 2 141 h REG 22h bit 4 1 and bits 3 2 00 or 10 RAS to CAS delay time REG 22h bits 3 2 01 1 45t1 2 1 55 t1 ns Access time from RAS 34 11 ite REG 22h bit 4 O and bits 3 2 00 or 10 t12 Access time from RAS l 24 11 ng REG 22h bit 4 1 and bits 3 2 00 or 10 Access time from RAS REG 22h bits 3 2 01 2 45 t1 12 ns t13 Access time from CAS tl 10 ns t14 Access time from CASH precharge column address 1 45 t1 6 ns t15 Read Data hold after CASH low ns t16 Read Data turn off delay from RAS ns Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 48 Epson Research and Development Vancouver Design Center 7 3 2 EDO DRAM Write Timing tl A Memory Clock t2 4 gt 13 t4 t5 t6 t8 t9 Pe gt o MA R C1 C2 C3 Xx C4 X re t7 RAS an eee CAS WE t12 t13 A t10 ble tii t14 t15 a y MD Write d X a d3 d4 Figure 7 8 EDO DRAM Write Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issu
65. t2 Clock pulse width high 5 ns t3 Clock pulse width low 5 ns t4 A 20 0 SIZ 1 0 M R setup to first CLK where CS 0 AS 4 a 0 and either UDS 0 or LDS 0 t5 A 20 0 SIZ 1 0 M R hold from AS 0 ns t6 CS hold from AS 0 ns t7 R W setup to DS 5 ns t8 R W hold from ASH 0 ns 19 AS 0 and CS 0 to DSACK1 driven high 1 ns t10 AS high to DSACK1 high impedance 1 5 ns 11 D 31 16 valid to second CLK where CS 0 ASH 0 and 0 ne either UDS 0 or LDS 0 write cycle t12 D 31 16 hold from falling edge of DSACK1 write cycle 0 ns t132 Falling edge of UDS 0 or LDS 0 to D 31 16 driven read 3 ne cycle t14 D 31 16 valid to DSACK1 falling edge read cycle 0 ns t15 UDS and LDS high to D 31 16 invalid high impedance read 2 11 ha cycle t16 AS high setup to CLK 3 ns 1 Ifthe S1D13504 host interface is disabled the timing for DS ACK 1 driven high is relative to the falling edge of AS or the first positive edge of CLK after A 20 0 and M R become valid whichever occurs later 2 Ifthe S1D13504 host interface is disabled the timing for D 15 0 driven is relative to the fall ing edge of UDS LDS or the first positive edge of CLK after A 20 1 and M R becomes valid whichever occurs later Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 42 Epson Research and Development Vancouver Design Center 7 1 4 Generic MPU Interface Synchronous Timing
66. to enable GPIO7 otherwise the DACWR pin is controlled automatically and this bit will have no effect on hard ware GPIO6 Pin IO Configuration When this bit 1 GPIO6 is configured as an output When this bit 0 default GPIO6 is config ured as an input Note the MD8 pin must be high at the rising edge of RESET to enable GPIO6 otherwise the DACPO pin is controlled automatically and this bit will have no effect on hardware GPIOS Pin IO Configuration When this bit 1 GPIOS is configured as an output When this bit 0 default GPIOS is config ured as an input Note the MD8 pin must be high at the rising edge of RESET to enable GPIOS otherwise the BLANK pin is controlled automatically and this bit will have no effect on hardware GPIO4 Pin IO Configuration When this bit 1 GPIO4 is configured as an output When this bit 0 default GPIO4 is config ured as an input Note the MD8 pin must be high at the rising edge of RESET to enable GPIO4 otherwise the DACRD pin is controlled automatically and this bit will have no effect on hardware GPIO3 Pin IO Configuration When this bit 1 GPIO3 is configured as an output When this bit 0 default GPIO3 is config ured as an input Note the MD 7 6 pins must be properly configured at the rising edge of RESET to enable GPIO3 otherwise the MA9 pin is controlled automatically and this bit will have no effect on hardware GPIO2 Pin IO Configuration When this bit 1 GPIO2
67. 0 45t1 2 ns Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Epson Research and Development Vancouver Design Center Page 50 7 3 3 EDO DRAM Read Write Timing Memory Clock t8 t10 tI lt di d2 MD Read d3 MD Write Figure 7 9 EDO DRAM Read Write Timing Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Epson Research and Development Vancouver Design Center Table 7 9 EDO DRAM Read Write Timing Page 51 Symbol Parameter Min Typ Max Units t1 Memory clock period 25 ns Random read or write cycle time REG 22h bits 6 5 00 5 tl ns t2 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns Row address setup time REG 22h bits 3 2 00 2 45 t1 ns t3 Row address setup time REG 22h bits 3 2 01 2 ti ns Row address setup time REG 22h bits 3 2 10 1 45 t1 ns i Row address hold time REG 22h bits 3 2 00 or 10 0 45t1 1 ns Row address hold time REG 22h bits 3 2 01 t1 1 ns t5 Column address setup time 0 45 t1 1 ns t6 Column address hold time 0 45t1 1 ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t7 RAS precharge time REG 22h bits 3 2 01 1 4511 1 ns RAS precharg
68. 0 Bit 3 Bit 2 Bit 1 Bit O REG 26h Look Up Table Data Register Read Write n la na Wa LUT Data LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 Bit O REG 27h Look Up Table Bank Register Read Write na na Red Bank Red Bank Blue Bank Blue Bank Green Bank Green Bank Select Bit 1 Select Bit 0 Select Bit 1 Select Bit 0 Select Bit 1 Select Bit 0 Programming Notes and Examples Issue Date 01 02 01 The S1D13504 LUT Registers are located at offsets 24h 26h and 27h They consist of a LUT address register data register and bank register Refer to the S1D13504 Hardware Functional Speci fication document number X19A A 002 xx for more details RGB Index Selects which LUT to program If set for Auto increment it will start at the Red LUT of the Index selected Then with consecutive writes reads it will increment to Green then Blue of the same index it will then increment the index and start at the Red LUT again Auto increment algorithm 1 Set RGB Index to 0 for Auto increment set LUT address to 0 i e REG 24h 00h 2 While count lt or to 16 3 write data byte to REG 26h R G or B Index select algorithm 1 Set RGB Index to R 01b G 10b or B 11b set LUT address to 0 e g REG 24h 10h 2 While count lt or 16 write data byte to REG 26h increment LUT address LUT Address Selects start index of the LUT in which to read data from or write data to Bank select has no effect on the CPU rea
69. 0001 1011 set vertical non display period REG OBh 0000 1001 0000 0000 0000 0000 0000 0000 set VSYNC start position REG 0Ch 0000 0001 0000 0010 1000 0001 1000 0011 set VSYNC polarity and pulse width REG ODh 0000 1110 0000 1110 0000 1110 0000 1110 set 8 bpp and CRT enable REG 19h 0000 0000 0000 0000 0000 0000 0000 0000 set MCLK and PCLK divide REG 2Ch 0000 0000 0000 0000 0000 0000 0000 0000 set write mode address to 0 REG 2Eh load RAMDAC palette data 6 1 2 Simultaneous Display For Simultaneous Display only 4 8 bit single passive LCD panels and 9 bit active matrix TFT panels can be used Simultaneous Display requires that the panel timing be taken from the CRT timing registers and thereby limits the number of useful modes supported The configuration of both CRT and panel must not violate the limitations as described in Frame Rate Calculation Chapter 11 of the S1D13504 Hardware Functional Specification For example on a 640x480 single panel the maximum values of both the panel pixel clock and CRT frame rate are 40 MHz and 85 Hz respectively When pixel depth is less than 8 bpp the RAMDAC is programmed with the same values as the Look Up Table The S1D13504 does not support Simulta neous Display in a color depth greater than 8 bpp When color depth is 8 bpp the RAMDAC should be programmed to mimic the recommended values in the Look Up Table as described in Section 3 3 2 The recommendation is that the intensities
70. 01 04 17 X00A E 003 04 Page 6 Windows 95 OSR2 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Windows will detect the card as a new PCI Device and launch the UPDATE DEVICE DRIVER wizard If The Driver is on Floppy Disk 3 4 5 6 Place the disk into drive A and click NEXT Windows will find the EPSON PCI Bridge Card Click FINISH to install the driver Windows will ask you to restart the system If The Driver is not on Floppy Disk 3 4 10 11 12 13 14 15 16 17 Click NEXT Windows will search the floppy drive and fail Windows will attempt to load the new hardware as a Standard VGA Card Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE Select NO for Windows to DETECT NEW HARDWARE Click NEXT Select OTHER DEVICES from HARDWARE TYPE and Click NEXT Click HAVE DISK Specify the location of the driver and click OK Click OK EPSON PCI Bridge Card will appear in the list Click NEXT Windows will install the driver Click FINISH Windows will ask you to restart the system Windows will re detect the card and ask you to restart the system S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Card
71. 02 02 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introduction se ra ras Gy Blais A AAA A Re ee A ee Be 7 2 Interfacing tothe PC CardBus 002 2c eee ee ee 8 2 1 ThePCCardSystemBus 2 2 2 2 8 ZL PC Card OVenviews suis ak a a a ook oe e Fae aed aden Loa ya 8 2 1 2 Memory Access Cycles o o ee 8 3 S1D13504 Host Bus Interface lt o o te 10 3 1 Generic MPU Host Bus Interface Pin Mapping 2 2 2 2 2 10 3 2 Generic MPU Host Bus Interface Signals Td 4 PC Card to S1D13504 Interface o 12 4 1 Hardware Description a 1 4 22 S1D13504 Hardware Configuration a a ee ee ee ee 18 4 32 PAI Equations o s i me eR we Soe Ae a ee Gee A 4 4 Register Memory Mapping 2 2 14 SoftWare te o haat at ere SA a ws ARS ela OS A A es 15 Referentes pre ee ARAS ae a A A O A a ee 16 6 1 Documents a 16 6 2 Document Sources 1 2 1 eee eee 16 7 Technical Support 2 4642 s4 2h ce eae ee AA eee 17 7 1 EPSON LCD CRT Controllers S1D13504 2 2 2 ee 17 R2 PC Card Standard y lt s s oe Go dh ae can ye an e ee ap a Wee a ee Sa Be ae LT Interfacing to the PC Card Bus 1D13504 Issue Date 01 02 02 X19A G 009 05 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the
72. 1 ns 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 61 Vancouver Design Center 7 3 10 FPM DRAM Self Refresh Timing Stopped for Restarted for tl suspend mode active mode gt Memory i Clock t5 gt t2 RAS CAS t3 t4 gt Figure 7 16 FPM DRAM CBR Self Refresh Timing Table 7 16 FPM DRAM CBR Self Refresh Timing Symbol Parameter Min Typ Max Units t1 Memory clock 40 ns 2 RAS to CAS precharge time REG 22h bits 3 2 00 2t1 ns RAS to CASH precharge time REG 22h bits 3 2 01 or 10 1t1 ns iS CAS precharge time REG 22h bits 3 2 00 2t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 1t1 ns t4 CAS setup time CAS before RAS refresh 0 45 t1 2 ns 5 RAS precharge time REG 22h bits 3 2 00 2 45 t1 1 ns RAS precharge time REG 22h bits 3 2 01 or 10 1 45t1 1 ns Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 62 7 4 Display Interface 7 4 1 Power On Reset Timing Epson Research and Development Vancouver Design Center TRESET t _ gt RESET LCD ENABLE REG ODh bit 0 LCDPWR Inactive Active FPFRAME Active FPLINE FPSHIFT Active FPDAT 15 0 DRDY t1 t2 Figure 7 17 LCD Panel Power On Rese
73. 13 2 Pin States in Power Save Modes Pin State Pins Normal Software Hardware Active Suspend Suspend LCD outputs Active Forced Low 1 Forced Low 1 LCDPWR On Off Off DRAM outputs Active Refresh Only 2 Refresh Only 2 CRT DAC outputs Active Disabled 3 Disabled 3 Host Interface outputs Active Active 4 Disabled Note 1 FPFRAME and FPLINE are forced to their inactive states as defined by REG OCh bit 6 and REG 07h bit 6 respectively 2 Selectable may be CBR refresh self refresh or no refresh at all 3 DACWR DACRD DACRSO DACRS1 are active but DACCLK is disabled 4 Active for non DAC register access only 1D13504 X19A A 002 19 Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 129 Vancouver Design Center 14 Mechanical Data 14 1 QFP15 128 S1D13504F00A QFP15 128 pin Unit mm 16 0 0 4 14 0 0 1 96 65 MER 64 14 0 0 1 16 0 0 4 33 e y a c los hoso 0 4 0 16 0 1 0 125 0 1 1 42401 gt l 0 5 0 1 TU isin 1 0 7 Figure 14 1 Mechanical Drawing QFP15 128 Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 130 Epson Research and Development Vancouver Design Center 14 2 TQFP15 128 S1D13504F01A TQFP15 128 pin Unit mm h 467 4 a 44 1 ONAA AAMA ati
74. 3 OS 5g Elz eo 8 wjo lo a si s al oe 35 os 3 z gu 3 385 A 4 82 r 2 E za a 3 ga 383 E 9 sk ax 2E 2R es wi g T le ray inon anoa T z E2 2s on bg ON 3 52 3 28 ON e lo ano ON E ano ON Z H ONO z z le ano 4 ano 2 48 la 2e z E ano lt a PEF z BE g zee ano ND S rav LAOA of efjo jojo g g 39 y 31034 E NCoa E 3 nroa o 58 roa 33 ae a lt Q 8 S Hoss Ho nx H vee P ee 33v 12V vec GND S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 Figure 6 SID13504B00C Schematic Diagram 6 of 6 S1D13504 X19A G 004 06 Page 26 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 EPSON S1D13504 Color LCD Controller S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Document Number X19A G 01 4 01 Copyright O 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Tech
75. 36 36 2A FA 3F 36 2A 9B 24 36 3F BB 2D 36 3F DB 36 36 3F FB 3F 36 3F 9C 24 3F 00 BC 2D 3F 00 DC 36 3F 00 FC 3F 3F 00 9D 24 3F 15 BD 2D 3F 15 DD 36 3F 15 FD 3F 3F 15 9E 24 3F 2A BE 2D 3F 2A DE 36 3F 2A FE 3F 3F 2A 9F 24 3F 3F BF 2D 3F 3F DF 36 3F 3F FF 3F 3F 3F S1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date 01 02 01 Table 6 4 Related register data for Simultaneous Display 640X480 75Hz 640X480 60Hz Register PCLK 40 0MHz PCLK 40 0MHz Notes REG 04h 0100 1111 0100 1111 set horizontal display width REG 05h 0001 1101 0001 0011 set horizontal non display period REG 06h 0000 0011 0000 0001 set HSYNC start position REG 07h 0000 0111 0000 1011 set HSYNC polarity and pulse width REG 08h 1000 1111 1101 1111 set vertical display height bits 7 0 REG 09h 0000 0001 0000 0001 set vertical display height bits 9 8 REG OAh 0010 1100 0010 1100 set vertical non display period REG OBh 0000 0000 0000 1001 set VSYNC start position REG OCh 1000 0010 0000 0001 set VSYNC polarity and pulse width REG ODHh 0000 1111 0000 1111 set 8 bpp and CRT enable REG 19h 0000 0000 0000 0000 set MCLK and PCLK divide REG 24h 0000 0000 0000 0000 set look up table address to 0 REG 26h load look up table REG 2
76. 4 gt FPSHIFT t13 t14 UD 3 0 Je Figure 7 24 Single Color 4 Bit Panel A C Timing Table 7 21 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPLINE falling edge to FPSHIFT falling edge t14 0 5 Ts t8 FPSHIFT period 1 Ts t9 FPSHIFT falling edge to FPLINE falling edge note 6 t10 FPLINE falling edge to FPSHIFT rising edge 19 Ts t11 FPSHIFT pulse width high 0 45 Ts t12 FPSHIFT pulse width low 0 45 Ts t13 UDI3 0 setup to FPSHIFT falling edge 0 45 Ts t14 UD 3 0 hold from FPSHIFT falling edge 0 45 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 timin t4min 9Ts 3 t4min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG O4h bits 6 0 1 8 1 Ts 5 min REG O5h bits 4 0 1 8 26 Ts 6 min REG O5h bits 4 0 1 8 17 Ts Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 70 Epson Research and Development Vancouver Design Center 7 4 6 Single Color 8 Bit Panel Timing Format 1
77. 5 1 Pinout Diagram for S1D13504F00A Epson Research and Development Vancouver Design Center s 05 4 oa 2 91 so sos a7 as as aa as faz a fso zo ze 77 ze 75 74 737271 70 5060 67 so os Y UYUVVVUVVUUO S gt SFSOvTvuwavsyevw wpitdgzgaowvwzyFodus 0 UUUUOUUOUOOD0O0O O gt O y ToU UOU GODT O 0 y UucmnonoOaozoSCc SSESESESESSE 0230833333333 LEDZBD aOR 22222200 FFP JoaronNn o FT EME aR OM 0 E D m 64 2 corevop MD1 BESA DACPO MD13 63 _ 2 2 pacwre Mps Ea 100 DACRSO MD12 ran 101 pacas MDS HE 102 unete MD11 H 103 vere Mp4 Pa 104 Z VSS MD10 Fo 108 ca MD5 106 SUSPEND MD9 PE 107 TESTEN MD6 Fo 108 53 BUSCLK MD8 109 52 vss MD7 H 110 51 2 lOVDD vss 2 aB20 LCAs F 112 apis ucas 49_ 113 48 Erbe S1D13504F00A aea AB17 RAS U5 apie lovop S 116 45 2 AB15 mag 7 Bra matt A4 118 1513 mas HB 119 42 AB12 Mato 12 AB11 maz PH FA AB10 mao O AB9 mas 139 _ 291 ape mar 38 124 AB7 mas L97 1251 ape Maz 36_ 126 aps Mas 127 34 apa MA3 128 ngs COREVDD 93 _ 37 lt 2mos gt 5 gt gt ro mon MSs 88888 8990000909096 Ny 23 Qg E a Ee Fe SOF OGFaRantrti soBBSBASRRSREZSDGBD f E E p E E E E o ho 12 hra hrali re iz fis 1920 21 2 al 4 52027 el o sofa1 a2 Figure 5 1 Pinout Diagram of FOOA Package type 128 pin surface mount QFP15 S1D13504 Hardware Functional Specific
78. 5 11 LCD CRT RAMDAC Interface Pin Mapping e 33 Table 6 1 Absolute Maximum Ratings 34 Table 6 2 Recommended Operating Conditions 002000000 34 Table 6 3 Input Specifications ma sta o e a ae a Ut ee O 34 Table 6 4 Output Specifications ee ee 35 Table 7 1 SH 3 Interface Timing lt scorre sara goe ee a a BA ROA 37 Table 7 2 MC68K Bus 1 Interface Timing 39 Table 7 3 MC68K Bus 2 Interface Timing 41 Table 7 4 Generic MPU Interface Synchronous Timing e 43 Table 7 5 Generic MPU Interface Asynchronous Timing e 45 Table 7 6 Clock Input Requirements 46 Table 7 7 EDODRAMRead Timing 47 Table 7 8 EDO DRAM Write Timing 49 Table 7 9 EDO DRAM Read Write Timing 51 Table 7 10 EDO DRAM CAS Before RAS Refresh Timing 52 Table 7 11 EDO DRAM Self Refresh Timing 0 0 000 000 0000 000000 53 Table 7 12 FPM DRAM Read Timing 55 Table 7 13 FPM DRAM Write Timing 0 0000000000000 000000 57 Table 7 14 FPM DRAM Read Write Timing 59 Table 7 15 FPM DRAM CAS Before RAS Refresh Timing o 60 Table 7 16 FPM DRAM CBR Self Refresh Timing e 61 Table 7 17 LCD Panel Power On Reset Timing 62 Table 7 18 LCD Panel Suspend Timing 0 00 0 00 00000020000 63 Table 7 19 Single Monochrome 4 Bit Panel A C Timing e 65 Tabl
79. 65536 Colors in Two Bytes of Display Buffer Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Red Bit 4 Red Bit 3 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit5 Green Bit4 Green Bit3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 4 Blue Bit 3 Blue Bit 2 Blue Bit 1 Blue Bit 0 As shown above the 65536 color pixel is divided into three parts five bits for red six bits for green and five bits for blue The output bypasses the LUT and goes directly into the Frame Rate Modulator Although 16 bit per pixel only make sense for a color panel this memory model can be set on a monochrome panel however only 16 shades of gray will be visible 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Vancouver Design Center Page 15 3 3 Look Up Table LUT This section provides a description of the LUT registers followed by a description of the color and gray shade LUTs and a discussion of the banks available in the 2 and 8 bit per pixel bpp modes The 1D13504 LUT is only used for the panel interface The optional RAMDAC is used to determine the colors for the CRT See Section 6 CRT Considerations on page 33 3 3 1 Look Up Table Registers REG 24h Look Up Table Address Register Read Write a Aa RGB Index RGB Index LUT Address LUT Address LUT Address LUT Address Bit 1 Bit
80. 7 0 LINE480 hth LINE1 X LINE480 oe se HRTC js HNDP HDP HNDP gt lt rie DACCLK LJ oe add AA BLANK a DACD 7 0 s ssS CD CL Figure 7 39 CRT Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP HNDP gt REG O5h bits 4 0 1 8Ts Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 86 Epson Research and Development Vancouver Design Center t9 VRTC g HRTC ng Ao ds 4 w HRTC j mb No gt gt t7 lt BLANK a t14 gt tl og tt t13 t16 DACCLK t4 t5 DACD 7 0 T 2 x 639 640 i Figure 7 40 CRT A C Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 87 Vancouver Design Center Table 7 29 CRT A C Timing Symbol Parameter Min Typ Max Units t1 DACCLK period 1 Ts note 1 t2 DACCLK pulse width high 0 45 Ts t3 DACCLK pulse width low 0 45 Ts t4 data setup to DACCLK rising edge 0 45 Ts t5 data hold from DACCLK rising edge 0 45 Ts t6 HRTC cycle time note 2 t7 HRTC pulse width shown active low note
81. A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address However when using the S1D13504 five MFIO pins are utilized for S1D13504 control signals and cannot provide latched addresses In this case an external latch must be used to provide the high order address bits For a solution that does not require a latch refer to Section 5 2 Hardware Description Using Two IT8368E s Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center Page 15 Functional Specification document number X19A A 002 xx or during debug states Notes The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface Asynchronous Timing for details refer to the S1D13504 Hardware 1D13504 TX3912 IO Voo BS A 12 0 gt AB 12 0 ENDIAN E Latch o gt AB 20 13 ALE y D 31 24 le gt DB 7 0 D 23 16 4 gt DB 15 8 System RESET gt RESET Vop pull up CARDxWAIT le WAIT DCLKOUT A23 gt M R See text gt CLKI IT8368E La Clock divider __ 0r c Oscillator BUSCLK LHA23 MFIO10 gt WE1 LHA22 MFIO9 gt WEO LHA21 MFIO8 RD1 LHA20 MFIO7 gt RDO LHA19 MFIO6 Chip Select CSH Logic When
82. AS AS Connect to lO Vpp RD WR RD WR R W R W RD1 RD RD Connect to IO Vpp SIZ1 RDO WE0 WE0 Connect to lO Vpp SIZO WEO WAIT WAIT DTACK DSACK1 WAIT RESET RESET RESET RESET RESET Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Epson Research and Development Page 32 Vancouver Design Center Table 5 10 Memory Interface Pin Mapping FPM EDO DRAM ee Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE MD 15 0 DQ 15 0 MA 8 0 A 8 0 MA9 GPIO3 AQ MA10 GPIO1 A10 MA11 GPIO2 A11 UCAS UCAS UWE UCAS UWE UCAS UWE UCAS UWE LCAS LCAS CAS LCAS CAS LCAS CAS LCAS CAS WE WE LWE WE LWE WE LWE WE LWE RAS RAS Note 1 All GPIO pins default to input on reset and unless programmed otherwise should be connected to either Vss or IO Vpp if not used 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 33 Vancouver Design Center Table 5 11 LCD CRT RAMDAC Interface Pin Mapping pea el Fassive Color Passive Panel S1 D13504 Single Single Color TFT Panel CRT Pin Names Single Dual Single Dual Format 1
83. Access not allowed 8 MCLK t7 First CLKI after SUSPEND inactive to Memory Access allowed 0 MCLK Note 1 t3 t5 and t7 are measured from the first CLKI after SUSPEND inactive 2 CLKI may be active throughout SUSPEND active 3 Where MCLK is the period of the memory clock Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 64 7 4 3 Single Monochrome 4 Bit Panel Timing Epson Research and Development Vancouver Design Center VDP VNDP X FPFRAME FPLINE f f f L l fl fl l fl MOD X E UD 3 0 UD 3 0 LINE1 X LINE2 X LINES X LINE4 LINE239XLINE240 LINE1 X LINE2 FPLINE MOD x mn HDP HNDP 4 gt k gt FPSHIFT UD3 11 X 15 X X X BA Y UD2 ER O X X X AE X UD1 13 X 17 Xo ate X Y 1319 Y UDO 14 Y 18 X y Yra X X 1 320 Y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 7 19 Single Monochrome 4 Bit Panel Timing VDP Vertical Display Period VNDP Vertical Non Display Period HDP Horizontal Display Period HNDP Horizontal Non Display Period S1D13504 X19A A 002 19 REG O9h bits 1 0 REG O8h bits 7 0 1 REG OAh bits 5 0 1 REG 04h bits 6 0 1 8Ts REG O5h bits 4 0 1 8Ts Hardware Functional Spe
84. Aras en bits 3 2 00 or 10 epee ee ng RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 01 1t1 2 111 ns RAS to CAS delay time REG 22h bit 4 0 and bits 3 2 01 2t1 2 2t1 ns t9 Read Data turn off delay from CAS 2 ns t10 Write Data enable delay from WE 0 45 t1 ns Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 60 7 3 9 FPM DRAM CAS Before RAS Refresh Timing Epson Research and Development Vancouver Design Center tl Memory Clock t2 t3 qu gt RAS COO CAS a t4 5 4 t6 gt Figure 7 15 FPM DRAM CAS Before RAS Refresh Timing Table 7 15 FPM DRAM CAS Before RAS Refresh Timing Symbol Parameter Min Typ Max Units ti Memory clock 40 ns 2 RAS to CAS precharge time REG 22h bits 3 2 00 2 tl ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 11 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t3 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3ti ns CAS precharge time REG 22h bits 3 2 00 2t1 ns CASH precharge time REG 22h bits 3 2 01 or 10 1t1 ns t5 CAS setup time CAS before RAS refresh 0 45t1 2 ns E RAS precharge time REG 22h bits 3 2 00 2 45t1 1 ns RAS precharge time REG 22h bits 3 2 01 or 10 1 45 11
85. B 005 05 Issue Date 01 02 01 Epson Research and Development Page 3 Vancouver Design Center 13504PLAY 13504PLAY allows the user to read write to all S1D13504 registers look up tables and display memory 13504PLAY is similar to the DOS DEBUG program commands are received from the standard input device and output is sent to the standard output device console for Intel terminal for embedded platforms This utility requires the target platform to support standard IO stdio 13504PLAY commands can be entered interactively using a keyboard monitor or they can be executed from a script file Scripting is a powerful feature which allows command sequences to be used repeatedly without re entry The 13504PLAY display utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13504CFG EXE which can be used to configure 13504PLAY This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet
86. Center S1D13XXX 32 Bit Windows Device Driver Installation Guide This manual describes the installation of the Windows 9x ME NT 4 0 2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards The file SID13XXX VXD is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x ME The file SID13XXX SYS is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows NT 4 0 2000 The file S1ID13XXX INF is the install script For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Video Controller S1D13xxx Display Type N A BIOS N A DOS Program No Dos Version N A Windows Program Yes Windows 9x ME NT 4 0 2000 device driver Windows DOS Box N A Windows Full Screen N A 0S 2 N A Installation Windows NT Version 4 0 All evaluation boards require the driver to be installed as follows 1 2 Install the evaluation board in the computer and boot the computer Copy the files SID13XXX INF and S1D13XXX SYS to a directory on a local hard drive Right click your mouse on the file S1D13XXX INF and select INSTALL from the menu Windows will install the device driver and ask you to restart S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue D
87. Design Center 5 4 Pin Description CS COx TSx TSxD CNx Input Output Bi Directional Input Output Power pin CMOS level input Page 21 CMOS level input with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively CMOS level Schmitt input CMOS output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA Tri state CMOS output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA Tri state CMOS output driver with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA CMOS low noise output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA 5 4 1 Host Interface Table 5 1 Host Interface Pin Descriptions Pin Name Pin Type FOOA rora POLA Driver Reset 0 Value Description ABO CS Hi Z This pin has multiple functions e For SH 3 mode this pin inputs system address bit O AO e For MC68K Bus 1 this pin inputs the lower data strobe LDS e For MC68K Bus 2 this pin inputs system address bit 0 AO e For Generic Bus this pin inputs system address bit 0 AO See Table 5 9 Host Bus Interface Pin Mapping on page 31 for summary AB 20 1 I 111 128 125 142 1 2 3 4 O Hi Z System address bus bits 20 1 DB 15 0 10 16 31 18 33 C TS2 System data bus Unused data pins should be connecte
88. Format 2 4 bit 8 bit 8 bit 4 bit 8 bit 8 bit 8 bit 16 bit 9 bit 12 bit 18 bit FPFRAME FPFRAME Note FPLINE FPLINE Note FPSHIFT FPSHIFT Note DRDY MOD FPSHIFT2 MOD DRDY Note FPDATO DO LDO DO DO LDO LDO R2 R3 R5 Note FPDAT1 D1 LD1 D1 D1 LD1 LD1 R1 R2 R4 Note FPDAT2 D2 LD2 D2 D2 LD2 LD2 RO R1 R3 Note FPDAT3 D3 LD3 D3 D3 LD3 LD3 G2 G3 G5 Note FPDAT4 DO D4 UDO DO D4 D4 UDO UDO G1 G2 G4 Note FPDAT5 D1 D5 UD1 D1 D5 D5 UD1 UD1 GO G1 G3 Note FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 UD2 B2 B3 B5 Note FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 UD3 B1 B2 B4 Note FPDAT8 LD4 BO B1 B3 Note FPDAT9 LD5 RO R2 DACP7 FPDAT10 LD6 R1 DACP6 FPDAT11 LD7 GO G2 DACP5 FPDAT12 UD4 G1 DACP4 FPDAT13 UD5 GO DACP3 FPDAT14 UD6 BO B2 DACP2 FPDAT15 UD7 B1 DACP1 DACRD GPIO4 DACRD BLANK GPIO5 BLANK DACPO GPIO6 DACPO DACWR GPIO73 DACWR DACRSO GPIO83 DACRSO DACRS1 GPIO9 DACRS1 HRTC GP1010 HRTC VRTC GPIO113 VRTC DACCLK DACCLK Note RO and BO are not used If no LCD is active these pins are driven low All GPIO pins default to input on reset and unless programmed otherwise should be connected to either Vss or IO Vpp if not used Hardware Functional Specification Issue Date 01 11 06 Although 18 bit TFT panels are supported only 16 data bits 64K colors are available S1D13504 X19A A 002 19 Page 34 6 D C Characteristics Table 6 1 Absolute Maximum Ratings Epson Research and Development Vancouver Design Center
89. G4 X 1 85 X 1 R7 Y 1 68 a Y 1 G640 X UDO a 1 R2 X 1 63 X 1 84 X 1 R6 YX 1 G7 Y 1 B8 i Y Y1 8640 X LD3 o J241 R1X241 G2X241 B3X241 R5 241 G6 241 B7 A Y gate X LD2 a 241 61X241 82 241 R4X241 G5 241 B5X241 R8L Y ETA i Y LD1 an 241 81 241 R9X241 G4 241 85 241 R7 24108 Y Y ER 4 Y LDO RoN 241 R2X241 G3X241 B4X241 R6X241 G7X241 B8 X Y ERA X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 33 Dual Color 8 Bit Panel Timing VDP Vertical Display Period REG O9h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 79 Vancouver Design Center Sync Timing UE FPFRAME 14 3 FPLINE 5 MOD Data Timing FPLINE t9 tt t10 FPSHIFT UD 3 0 1 2 LD 3 0 X Figure 7 34 Dual Color 8 Bit Panel A C Timing Table 7 26 Dual Color 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9
90. GO UD5 DACP3 FPDAT14 29 BO B2 UD6 DACP2 FPDAT15 31 B1 UD7 DACP1 FPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT DRDY 35 FPSHIFT2 FPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPFRAME 39 FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME DACPO DACPO DACRD DACRD DACWR DACWR DACRS1 DACRS1 DACRSO DACRSO HRTC HRTC VRTC VRTC BLANK BLANK DACCLK PCLK GND eva GND GND GND GND GND GND GND GND GND N C 28 VLCD 30 VLCD VLCD VCC 32 5V 5V 5V 5V 5V 5V 5V 5V 12V 34 12V 12V 12V 12V 12V 12V 12V 12V VDDH 36 VDDH VDDH VDDH DRDY 38 DRDY DRDY DRDY MOD FPSHIFT2 MOD MOD MOD LCDPWR 40 LCD LCD LCD LCD LCD LCD LCD LCD LCD PWR PWR PWR PWR PWR PWR PWR PWR PWR S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13504 Issue Date 01 02 02 X19A G 004 06 Page 10 4 CPU BUS Interface Connector Pinouts 1D13504 X19A G 004 06 Table 4 1 CPU BUS Connector H1 Pinout Epson Research and Development Vancouver Design Center Conner Comments Pin No 1 Connected to DBO of the S1D13504 2 Connected to DB1 of the S1D13504 3 Connected to DB2 of the S1D13504 4 Connected to DB3 of the S1D13504 5 Ground 6 Ground 7 Connected to DB4 of the S1D13504 8 Connected to DB5 of the S1D13504 9 Connected to DB6 of the S1D13504 10 Connected to DB
91. Interfacing to the NEC VR4102 Microprocessors X19A G 007 xx Interfacing to the ODO Display Card Interface X19A G 008 xx Interfacing to the PC Card Bus X19A G 009 xx Interfacing to the Motorola MPC821 Microprocessor X19A G 010 xx Interfacing to the Motorola MCF5307 Coldfire Microprocessors X19A G 011 xx Interfacing to the Toshiba TX3912 Microprocessor X19A G 012 xx Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 xx 1D13504 Register Summary X19A Q 001 xx Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center 16 Sales and Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Hardware Functional Specification Issue Date 01 11 06 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de Page 133 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking E
92. Issue Date 01 10 26 X19A G 013 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68328 2 1 The 68328 System Bus The 68328 is an integrated controller for handheld products based upon the MC68EC000 microprocessor core It implements a 16 bit data bus and a 32 bit address bus The bus interface consists of all the standard MC68000 bus interface signals plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices The 68000 bus control signals are well documented in Motorola s user manuals and will not be described here see reference 1 for details A brief summary of the new signals appears below e Output Enable OE is asserted when a read cycle is in process it is intended to connect to the output enable control of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus they may be directly connected to the write enable inputs of a typical memory device The S1D13504 implements the MC68000 bus interface using its MC68000 Bus 1 mode so this mode may be used to connect the 68328 directly to the S1D13504 with no glue logic However several of the 68000 bus control signals are multiplexed with I O and interrupt signals on the 68328 and in many applications it may be desirable to make these pins avail
93. Notes and Examples Issue Date 01 02 01 Epson Research and Development Vancouver Design Center 3 2 3 Memory Organization for Four Bit per pixel 16 Colors Gray Shades Table 3 3 Pixel Storage for 4 bpp 16 Colors Gray Shades in One Byte of Display Buffer Two pixels are grouped into one byte of display buffer as shown below Page 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bit 3 Pixel 0 Bit 2 Pixel 0 Bit 1 Pixel 0 Bit 0 Pixel 1 Bit 3 Pixel 1 Bit 2 Pixel 1 Bit 1 Pixel 1 Bit O Four bit per pixel provides sixteen shades of gray by indexing into positions O through F of the Green LUT and 16 levels of color by indexing into positions 0 through F of the Red Green Blue LUTs 3 2 4 Memory Organization for Eight Bit per pixel 256 Colors One pixel is stored in one byte of display buffer as shown below Table 3 4 Pixel Storage for 8 bpp 256 Colors in One Byte of Display Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 1 Blue Bit 0 As shown above the 256 color pixel is divided into three parts three bits for red three bits for green and two bits for blue The red bits represent an index into the red LUT the green bits represent an index into the green LUT and the blue b
94. PC Card Bus X19A G 009 05 Issue Date 01 02 02 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Options 2 o o e e 13 Table 4 2 Host Bus Interface Selection 2 2 ee a 13 List of Figures Frgure 2 1 PCCard ReadiCycles iaa a a a da ie dd ee ed 9 Figure 2 2 PC Card Write Cycle oo o 25 e400 be hee de a e a 9 Figure 4 1 Typical Implementation of PC Card to S1D13504 Interface 12 Interfacing to the PC Card Bus 1D13504 Issue Date 01 02 02 X19A G 009 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD CRT Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation
95. Parameter Min Typ Max Units t1 Memory clock 40 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t2 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns Row address setup time REG 22h bits 3 2 00 2t1 ns t3 Row address setup time REG 22h bits 3 2 01 1 45 t1 ns Row address setup time REG 22h bits 3 2 10 111 ns i Row address hold time REG 22h bits 3 2 00 or 10 ti 1 ns Row address hold time REG 22h bits 3 2 01 0 45t1 1 ns t5 Column address set up time 0 45t1 1 ns t6 Column address hold time 0 45t1 1 ns t7 CAS pulse width 0 45 t1 0 55t1 1 ns t8 CAS precharge time 0 45t1 1 0 55 t1 ns t9 RAS hold time 0 45 t1 ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t10 RAS precharge time REG 22h bits 3 2 01 1 4511 1 ns RAS precharge time REG 22h bits 3 2 10 1t1 1 ns RECs ey bits 3 2 00 or 10 anne Loe nS t11 E ao bits 3 2 00 or 10 aaa se 2Sa ns RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 01 1t1 2 1t1 ns RAS to CAS delay time REG 22h bit 4 0 and bits 3 2 01 2t1 2 2t1 ns t12 Write command setup time 0 45 t1 1 ns t13 Write command hold time 0 45 t1 ns t14 Write Data setup time 0 45 t1 3 ns t15 Write Data hold time 0 45t1 2 ns Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 58 Epson Research and Development Vancouv
96. Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the NEC VR4102 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 007 08 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 2 1 The NEC VR4102 System Bus 2 1 1 Overview 1D13504 X19A G 007 08 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 offers a highly integrated solution for portable systems This section provides an overview of the operation of the CPU bus in order to establish interface requirements The NEC VR4102 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU using its internal SysAD bus The BCU in turn communicates with external devices using its ADD and DAT buses which can be dynamically sized to 16 or 32 bit operation The NEC VR4102 has direct support for an external LCD controller Specific control signals are assigned for an external LCD cont
97. Power On Reset Options S1D13504 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 MDO 8 bit host bus interface MD1 MD2 For host bus interface selection see Table 4 2 Host Bus Interface Selection MD3 MD4 Little Endian MD5 Wait signal is active low MD9 Reserved D configuration for MPC821 interface Table 4 2 Host Bus Interface Selection MD3 MD2 MD1 Host Bus Interface 0 0 SH 3 bus interface 0 1 MC68K bus 1 interface e g MC68000 0 1 0 MC68K bus 2 interface e g MC68030 1 xX X Reserved L configuration for MPC821 interface 1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Page 19 Vancouver Design Center 4 4 Register Memory Mapping The S1D13504 is a memory mapped device The DRAM on the MPC821 ADS board extends from address Oh through 3F FFFFh so the S1D13504 must be addressed starting at 40 0000h A total of 4M bytes of address space is used where the lower 2M bytes from 40 0000h through 5F FFFFh is reserved for the S1D13504 on chip registers and the upper 2M bytes from 60 0000h through 7F FFFFh is used for the 1D13504 display buffer 4 5 MPC821 Chip Select Configuration Chip select 4 is used to control the S1D13504 The following options are selected in the base address register BR4 e BA 0 16 0000 0000 0
98. RESET Note When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MPC821 to SID13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 16 4 2 Hardware Connections 1D13504 X19A G 010 06 Epson Research and Development Vancouver Design Center The following table details the connections between the pins and signals of the MPC821 and the S1D13504 Table 4 1 List of Connections from MPC821ADS to S1D13504 MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13504 Signal Name Vcc P6 A1 P6 B1 Vcc A10 P6 C23 M R A11 P6 A22 AB20 A12 P6 B22 AB19 A13 P6 C21 AB18 A14 P6 C20 AB17 A15 P6 D20 AB16 A16 P6 B24 AB15 A17 P6 C24 AB14 A18 P6 D23 AB13 A19 P6 D22 AB12 A20 P6 D19 AB11 A21 P6 A19 AB10 A22 P6 D28 AB9 A23 P6 A28 AB8 A24 P6 C27 AB7 A25 P6 A26 AB6 A26 P6 C26 AB5 A27 P6 A25 AB4 A28 P6 D26 AB3 A29 P6 B25 AB2 A30 P6 B19 AB1 A31 P6 D17 ABO DO P12 A9 DB15 D1 P12 C9 DB14 D2 P12 D9 DB13 D3 P12 A8 DB12 D4 P12 B8 DB11 D5 P12 D8 DB10 D6 P12 B7 DB9 D7 P12 C7 D
99. Research and Development Vancouver Design Center Table 6 1 Parts List Item Qty Reference Part Description peanut claret Pare Mo t Assembly Instructions 27 2 R22 R19 R0805 100K generic 28 1 R20 R0805 1 2M generic 29 1 R21 R0805 22K generic 30 3 R24 R25 R30 R0805 1K 5 generic 31 1 S1 DIPSW5 S1D13504 Config Grayhill 76SB05S 32 1 U1 TQFP128 13504F0A Epson SED1354F0A 33 1 U2 DIP14 Machined socket 14 pin 34 1 U2 DIP 14 40MHz Epson SG8002DB 40MHz 35 1 U3 DIP14 Machined socket 14 pin 36 1 U3 DIP 14 25MHz Epson SG8002DB 25MHz 37 1 U4 DDPAK 2 LT1117CM 3 3 Linear Technologies LT1117CM 3 3 Micron MT4LC1M16E5DJS 5 or ISSI 38 1 U5 SOJ42 DRAM 1Mx16 SOJ 18411v16100 39 1 U6 SC70 5 INVERTER SINGLE NC7S04 Fairchild Semiconductor NC7S04P5 40 3 U7 U8 U9 SO20W 74AHC244 TI 74AHC244 Maxim Integrated Products 41 1 U10 SO16N MAX754CSE MAX754CSE Maxim Integrated Products 42 1 U11 SO8N MAX749CSA MAX749CSA 43 1 U12 TQFP144 EPF6016TC144 2 Altera EPF6016TC144 2 44 1 U13 DIP8 Machined socket 8 pin 45 4 U13 DIP8 EPC1441PC8 Altera EPC1441PC8 programmed socketed S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Page 25 I I 1 1 y i I 1 T 18915 Z00e Th TOQUIANESS TepsoupeMm ed 8 Jequiny weuinooq ez duo VOX 088 1 sng 104 o0osrose inss ou uewidojonag Y yoseesoy uosda T 0 nO WANS is anto vosvoser oto e i peer A anon NIA Aa
100. Research and Development Page 71 Vancouver Design Center tt Sync Timing 2 FPFRAME 13 EA gt FPLINE Data Timing FPLINE lt tba t6 t7 t8a RPL t10 tt FPSHIFT t8b gt FPSHIFT2 t2 13 gt UD 3 0 l z LD 3 0 Figure 7 26 Single Color 8 Bit Panel A C Timing Format 1 Table 7 22 Single Color 8 Bit Panel A C Timing Format 1 Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5a FPSHIFT2 falling edge to FPLINE rising edge note 4 t5b FPSHIFT falling edge to FPLINE rising edge note 5 t6 FPLINE falling edge to FPSHIFT2 rising FPSHIFT falling edge t14 2 Ts t7 FPSHIFT2 FPSHIFT period 4 Ts t8a FPSHIFT falling edge to FPLINE falling edge note 6 t8b FPSHIFT2 falling edge to FPLINE falling edge note 7 t9 FPLINE falling edge to FPSHIFT rising edge 18 Ts t10 FPSHIFT2 FPSHIFT pulse width high 2 Ts t11 FPSHIFT2 FPSHIFT pulse width low 2 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT2 rising FPSHIFT falling edge 1 Ts t13 UD 3 0 LD 3 0 hold from FPSHIFT2 rising FPSHIFT falling edge 1 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 timin t4min 9Ts 3 t4min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 t5min REG 05h bits 4 0 1 8 27 T11 Ts 5 t5min REG 05h bi
101. Shade Since the Look Up Table is bypassed in this mode the LUT programming is unimportant The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data Resulting in a maximum of 24 16 colors 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 23 Vancouver Design Center 4 Advanced Techniques This section presents information on the following e virtual display e panning and scrolling e split screen display 4 1 Virtual Display A virtual display is when the image to be displayed is larger than the physical display device in either the horizontal dimension the vertical dimension or both To view the image the physical display is used as a window or viewport into the display buffer allowing the user to see a portion of the entire image This viewport can be panned and scrolled enabling the user to view the entire image The size of the virtual display is limited by the amount of available display buffer In the case of an S1D13504 with 2M byte of display buffer the maximum virtual width ranges from 16 368 pixels in 1 bpp mode to 1023 pixels in 16 bpp mode The maximum vertical size at the horizontal maximum 1s 1025 lines By trading off horizontal size a greater vertical size can be achieved Seldom are the maximum sizes required Figure 4 1 Viewport Inside a Virtual Display depicts a more typical use of a
102. Specification Issue Date 01 11 06 Epson Research and Development Page 115 Vancouver Design Center 10 Display Configuration 10 1 Display Mode Data Format 1 bpp bit 7 bit 0 PoP P2 P3P4P5 Pe Pz Panel Display Host Address Display Buffer 2 bpp bit 7 bit 0 PoP P2 P3P4PsP6P7 Panel Display Host Address Display Buffer Po P4 P2 P3P4P5P6 P7 Ph An Br Ch Dn Panel Display Host Address Display Buffer 8 bpp 3 3 2 RGB PoP1 P2 P3P4P5 P6 P7 Go G4 Ph R 2 Gn 20 B Go Panel Display Host Address Display Buffer Figure 10 1 1 2 4 8 Bit Per Pixel Format Memory Organization Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 116 Epson Research and Development Vancouver Design Center 15 bpp PoP1P2P3P4P5PgP 5 5 5 RGB 415617 bit 7 bit O Ph Sa R Gn 401 B Passive Pa Ratt Gn 41 B 1 Panel Display Host Address Display Buffer PoP1P2P3P4P5P6P7 Pp Rn4 Gp 9 Bp 9 Passive Ph 2 BAH Gn 52 By Panel Display Display Buffer Host Address Figure 10 2 15 16 Bit Per Pixel Format Memory Organization Note 1 The Host to Display mapping described here assumes that a Little Endian interface is being used 2 For 8 15 16 bit
103. Ts 4 t5min REG 04h bits 6 0 1 8 1 Ts 5 min REG 05h bits 4 0 1 8 26 Ts 6 t min REG 05h bits 4 0 1 8 17 Ts Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 74 Epson Research and Development Vancouver Design Center 7 4 8 Single Color 16 Bit Panel Timing le VDP da VNDP gt FPFRAME sas FPLINE l l j fl ias l l f l f MOD o X UD 7 0 LD 7 0 A LINEA X LINE2 X LINES X LINE4 X XLINE479X LINE480 LINE1 X LINE2 X FPLINE MOD y HDP ple NOP y iii 7 iS ne ea i UD7 _ 1 R1 X 1 G6 X1 B11 X X Y X1 G635 f X UD6 o 1 81 X 187 X1 G12X X 1 G636 X UD5 ox 162 X 1 B7 X 1 R13 Y SA Y1 R637 Y UD4 E 1 R3 Y 1 68 Y1 B13 Y Y EEA EN ON UD3 we 1 83 X 1 9 X 1 G14X x 1 G638 X X UD2 o A 1 64 X 1 B9 X 1 R15 X A1 R639 A X UD1 5 1 R5 1 10 1 B15 X O Y Y 1 8639 C Yy UDO A 1 B5 X 1 R11X 1 G16 X x X1 G640 LD7 ae 1 G1 Y 1 B6 Y 1 R12Y Y Vo VERIA CY LD6 o R2 YX 1 67 X 1 B12X Y gt 1 8638 y LD5 o B2 Y 1 R8 Y 1 G13 Yi G637 y LD4 A163 Y 1 B8 Y 1 R14 Y I Y 1 R638 x X LD3 me A 1 R4 X 1 69 X 1 814X Y Y 8638 A LD2 K 1 B4 YX 1 R10X 1 G15 x Y E x Y 1 G6
104. Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 1 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width low 0 45 Ts t11 FPSHIFT pulse width high 0 45 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 0 45 Ts t13 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 0 45 Ts t14 FPLINE falling edge to FPSHIFT rising edge 11 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 tlmin 13min 9Ts 3 t3min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG 04h bits 6 0 1 8 1 Ts 5 min REG O5h bits 4 0 1 8 18 Ts 6 min REG 05h bits 4 0 1 8 9 Ts Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 80 Epson Research and Development Vancouver Design Center 7 4 11 Dual Color 16 Bit Panel Timing lq VDP sie VNDP gt FPFRAME me FPLINE __ j j LN l j l j MOD X de X UD 7 0 LD 7 0 LINE 1 241 LINE 2 242 X LINE 3 243 X LINE 4 244 Kline 299 479XLINE 240 480 X LINE 1 241 Y LINE 2 242 FPLINE il MOD y HDP pig HNOP y FPSHIFT
105. Vancouver Design Center Occasionally the need arises to display two distinct images on the display For example we may want to write a game where the main play area will be rapidly updated and we want an unchanging status display at the bottom of the screen The Split Screen feature of the S1D13504 allows a programmer to set up a display for such an appli cation The figure below illustrates setting up a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239 Although this example picks specific values image 1 and image 2 can be shown as varying portions of the screen Scan Line 0 vs Image 1 Scan Line 99 Scan Line 100 Image 2 Scan Line 239 Figure 4 2 320x240 Single Panel For Split Screen The other registers required for split screen operations 10h through 12h Screen 1 Display Start Address and 18h Pixel Panning Register are described in section 4 2 1 on page 26 REG 0E Screen 1 Line Compare Register 0 Line Compare Bit 7 Line Compare Bit 6 Line Compare Bit 5 Line Compare Bit 4 Line Compare Bit 3 Line Compare Bit 2 Line Compare Bit 1 Line Compare Bit 0 REG OF Screen 1 Line Compare Register 1 Line Compare Line Compare n a n a n a n a n a n a Bit 9 Bit 8 These two registers form a value known as the line compare When the line compare va
106. Windows CE Display Driver Issues Description of Windows CE Display Driver Issues The following are some issues to consider when configuring the display driver to work with Windows CE 1 When Windows CE enters the Suspend state power off the LCD controller and dis play memory may lose power depending on how the system is designed If display memory loses power all images stored in display memory are lost If power off power on features are required the OEM has several options e If display memory power is turned off add code to the display driver to save any images in display memory to system memory before power off and add code to restore these images after power on e Ifdisplay memory power is turned off instruct Windows CE to redraw all images upon power on Unfortunately it is not possible to instruct Windows CE to redraw any off screen images such as icons slider bars etc so in this case the OEM must also configure the display driver to never use off screen memory e Ensure that display memory never loses power Windows CE 3 x Display Drivers 1D13504 Issue Date 01 05 08 X19A E 006 01 Page 14 1D13504 X19A E 006 01 Epson Research and Development Vancouver Design Center Using off screen display memory significantly improves display performance For ex ample slider bars appear more smooth when using off screen memory To enable or disable the use of off screen memory edit the file x wince300 plat
107. Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 5 Vancouver Design Center Windows 98 ME All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Windows will detect the new hardware as a new PCI Device and bring up the ADD NEW HARDWARE dialog box 3 Click NEXT 4 Windows will look for the driver When Windows does not find the driver it will al low you to specify the location of it Type the driver location or select BROWSE to find it 5 Click NEXT 6 Windows will open the installation file and show the option EPSON PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Goto the CONTROL PANEL and double click on ADD NEW HARDWARE to launch the ADD NEW HARDWARE WIZARD Click NEXT 3 Windows will attempt to detect any new plug and play device and fail Click NEXT 4 Windows will ask you to let it detect the hardware or allow you to select from a list Select NO I WANT TO SELECT THE HARDWARE FROM A LIST and click NEXT 5 From the list select OTHER DEVICES and click NEXT 6 Click HAVE DISK and type the path to the driver files or select browse to find the driver 7 Click OK 8 The driver will be identified as EPSON PCI Bridge Card Click NEXT 9 Click FINISH S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date
108. a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debugging 3 1 Generic MPU Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping RdA Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to IO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 1D13504 X19A G 012 05 Page 10 Epson Research and Development Vancouver Design Center 3 2 Generic MPU Host Bus Interface Signals 1D13504 X19A G 012 05 The interface requires the following signals BUSCLK is a clock input which is required by the 1D13504 host bus interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset M R memory register may be considered an address line allowing system address A21 to be connected to the M R
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110. any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com S1D13504 X19A E 004 01 Page 4 Epson Research and Development Vancouver Design Center Building the Console Driver for Linux Kernel 2 2 x 1D13504 X19A E 004 01 Follow the steps below to construct a copy of the Linux operating system using the S1D13504 as the console display device These instructions assume that the GNU devel opment environment is installed and the user is familiar with GNU and the Linux operating system 1 Acquire the Linux kernel source code You can obtain the Linux kernel source code from your Linux supplier or download the source from ftp ftp kernel org The S1D13504 reference driver requires Linux kernel 2 2 x or greater The example S1D13504 reference driver available on www erd epson com was built using Red Hat Linux 6 1 kernel version 2 2 17 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13504 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13504 archive to a temporary directory e g tmp When completed the files s1d13xxxfb c s1d413504 h Config in fbmem c fbcon cfb4 c and Makefile should be located in the temporary directory
111. before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Wind River WindML v2 0 Display Drivers S1D13504 Issue Date 01 04 06 X19A E 002 03 Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2 0 Display Driver 1D13504 X19A E 002 03 The following instructions produce a bootable disk that automatically starts the UGL demo program These instructions assume that Wind River s Tornado platform is already installed Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the WindML display driver into it From a command prompt or GUI interface create a new directory e g x 13504 Unzip the file 13504windml zip to the newly created working directory The files will be unzipped to the directories x 13504 8bpp and x 13504 16bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13504 8bpp File config h or x 13504 1 6bpp File config h The new config h file removes networking co
112. connecting the S1D13504 RESET pin the system designer should be aware of all conditions that amy reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes Figure 5 1 SID13504 to TX3912 Connection using One IT8368E Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 S1D13504 X19A G 012 05 Page 16 Epson Research and Development Vancouver Design Center The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock This gives the system designer full flexibility in choosing the appropriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 5 2 Hardware Description Using Two IT8368E s S1D13504 X19A G 012 05 The following implementation uses a second IT8368E not in VGA mode in place of an address latch The pins LHA23 and LHA 20 13 provide the latch function instead Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Page 17 Vancouver Design Center
113. developer an easy way to modify panel types modes etc for the S1D13504 utilities without recompiling Once the correct operating environment has been deter mined the software hardware developer can modify the source code manually for a permanent change 13504CFG changes the hardware configuration setup for each of the 13504 utilities as well as any program designed by a software hardware developer using the Hardware Abstraction Layer HAL library 13504CFG runs in two modes one mode reads script files and the other mode is interactive In the interactive mode the 13504CFG DOS based program uses an interface similar to Windows to present one menu for each configuration section Each section has its own dialog box showing all of the relevant elements for that section 13504CFG reads the configuration from a specific EXE file for Intel platforms and from a specific S9 file for non Intel platforms 13504CFG can select all EXE files for configuration writes 13504CFG prints or displays the configuration setup 13504CFG supports scripts to quickly reprogram all files to a given configuration setup The given configuration is defined in an INI file 13504CFG is designed to work with a given version of the configuration setup structure If the structure is of a different version an error message is displayed and the program exits S1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Epson Research and Develop
114. evaluation board H lines Halts after lines of display This feature halts the display during long read operations to prevent data from scrolling off the display Set 0 to disable Q Quits this utility y 1 Displays Help information 13504PLAY Example Scripting 13504PLAY Diagnostic Utility Issue Date 01 02 01 Type 13504PLAY to start the program Type for help Type i to initialize the registers Type xa to display the contents of the registers Type x 5 to read register 5 Type x 3 10 to write 10 hex to register 3 Type f 0 ffff aa to fill the first FFFF hex bytes of display memory with AA hex Type f 0 1fffff aa to fill 2M bytes of display memory SO GO ON ON U S Type r 0 ff to read the first 100 hex bytes of display memory 10 Type q to exit the program 13504PLAY can be driven by a script file This is useful when e there is no display output and a current register status is required e various registers must be quickly changed to view results A script file is an ASCU text file with one 13504PLA Y command per line All scripts must end with a q quit command On a PC platform a typical script command line is 13504PLAY lt dumpregs scr gt results This causes the file dumpregs scr to be interpreted and the results to be sent to the file results Example Create an ASCII text file that contains the commands i xa and q This file initial
115. file in the directory x 13504 8bpp File If building for 16 bpp place the new mode0 h file in x 13504 16bpp File Note Mode0 h should be created using the configuration utility 13504DCFG For more infor mation on 13504DCFG see the 3504DCFG Configuration Program User Manual document number X19A B 008 xx available at www erd epson com 7 Open the S1D13504 workspace From the Tornado tool bar select File gt Open Workspace gt Existing gt Browse and select the file x 13504 8bpp 13504 wsp or x 13504 16bpp 13504 wsp 8 Add support for single line comments The WindML v2 0 display driver source code uses single line comment notation rather than the ANSI conventional comments To add support for single line comments follow these steps a Inthe Tornado Workspace Views window click on the Builds tab b Expand the 8bpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A Properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that contains g mpen tium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 9 Compile the VxWorks image Select the Builds tab in the
116. fine tune the non display width and the non display height As a general rule passive LCD panels and some CRTs are tolerant of a wide range of non display times Active panels and some CRTs are far less tolerant of changes to the non display period Displays the current Frame Rate based on clock and panel parameters Displays the current PCLK Frequency as set in the Clocks tab These settings allow fine tuning the TFT line pulse parameters and are only available when the selected panel type is TFT Refer to S1D13504 Hardware Functional Specification document number X19A B 001 xx for a complete description of the FPLINE pulse settings Specifies the delay in pixels from the start of the horizontal non display period to the leading edge of the FPLINE pulse Specifies the pulse width in pixels of the FPLINE output signal These settings allow fine tuning the TFT frame pulse parameters and are only available when the selected panel type is TFT Refer to S1D13504 Hardware Functional Specification document number X19A B 001 xx for a complete description of the FPFRAME pulse settings Specify the delay in lines from the start of the vertical non display period to the leading edge of the FPFRAME pulse S1D13504 X19A B 008 03 Page 18 Epson Research and Development Vancouver Design Center Pulse width Specifies the pulse width in lines of the FPFRAME output signal Predefined Panels 13504DCFG uses a file panels d
117. following bits per pixel values 1 2 4 8 15 and 16 4 Press lt ESC gt to exit the program S1D13504 13504VIRT Display Utility X19A B 004 05 Issue Date 01 01 30 Epson Research and Development Page 5 Vancouver Design Center Comments The maximum virtual display width is 1024 pixels except in 15 and 16 bits per pixel mode where the maximum width is 1023 pixels The PC must not have more than 12M bytes of system memory when used with the S53U13504B00C board Follow simultaneous display guidelines for correct simultaneous display operation To determine if the CRT will operate correctly when using a dual panel refer to the Maximum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing e A CRT cannot show 15 or 16 bits per pixel Do not attach a panel with a 16 bit interface to the S1D13504 when a CRT is also attached Program Messages 13504VIRT Display Utility Issue Date 01 01 30 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL can only manage 10 devices simultaneously ERROR Could not registe
118. in the example below To program index 3 of the current LUT with Green bank select bits set to 11b and 2 bpp gray shade mode selected you would program LUT address to 3 bank select value 4 entries in LUT 3 index to modify 1 to zero base the value 14 0Eh Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Vancouver Design Center Page 17 3 3 2 Look Up Table Organization e The Look Up Table LUT treats the value of a pixel as an index into an array of colors or gray shades For example a pixel value of zero would point to the first LUT entry a pixel value of 7 would point to the eighth LUT entry The value inside each LUT entry represents the intensity of the given color or gray shade This value ranges between 0 and OFh The S1D13504 LUT is linear increasing the LUT number results in a lighter color or gray shade For example a LUT entry of OFh into the red Look Up entry will always result in a bright red output Table 3 7 Look Up Table Configurations Display Mode 4 Bit Wide Look Up Table a ei Pn an RED GREEN BLUE 1 bpp gray 1 bank of 2 2 gray shades 2 bpp gray 4 banks of 4 4 gray shades 4 bpp gray 1 bank of 16 16 gray shades 8 bpp gray 2 banks of 8 8 gray shades 15 bpp gray 16 gray shades 16 bpp gray 16 gray shades 1 bpp color 1 bank of 2 1 bank of 2 1 bank of 2 2 colors 2 bpp color 4 banks of 4 4 banks of 4 4 banks of 4 4 colors 4 b
119. interface which is used to interface to the Philips PR31500 PR31700 processor The Generic MPU host bus interface is the least processor specific interface mode supported by the S1D 13504 and was chosen to implement this interface due to the simplicity of its timing Page 9 The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debugging 3 1 Generic MPU Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping RdA Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to IO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 1D13504 X19A G 005 09 Page 10 Epson R
120. is only to change the panel resolution the script would only have the following lines L File TEST INI L 640 480 Panel x Panel y To use this script file on the 13504PLAY utility type the following 13504CFG 13504PLAY EXE TEST INI In this example all of the other panel settings in the 13504 utility remain the same In general however it is necessary to set several more panel parameters before the panel is properly configured The full list of all the possible parameters to 13504CFG is included in the file 13504 INI 13504CFG EXE Configuration Program Issue Date 01 01 30 Epson Research and Development Page 11 Vancouver Design Center Interactive Mode 13504CFG Menu Bar SED1354 Configuration Utilit Files View Device Help Menu Bar 4 Figure 1 13504CFG Menu Bar 13504CFG has four main menus Files View Device and Help Menu contents can be viewed by using either the mouse or the keyboard Viewing 13504CFG Menu Contents Mouse Move the on screen arrow with the mouse and point at the desired menu Click the left mouse button and the contents of the menu will be displayed Keyboard Press lt Alt gt lt F gt to select the Files menu lt Alt gt lt V gt to select the View menu lt Alt gt lt D gt to select the Device menu lt Alt gt lt H gt to select the Help menu lt gt lt l gt or the highlighted letter in the menu to select a menu item
121. mode the pixel value indexes into one of 16 LUT entries The LUT bank bits are ignored in this mode The recommendation for this mode is to program the register values to data values equalling the register number i e G 0 0 G 1 1 G 2 2 G F 0Fh 8 bpp Gray Shade When the 1D13504 is configured for 8 bpp gray shade mode bits 7 5 are ignored bits 4 2 represent the green LUT index and bits 1 0 are ignored Only 3 bits of the 8 that actually represent any shade value therefore the maximum gray shade combination is 8 shades If this limitation is deemed appropriate for your application it is recommended that the LUTs are programmed according to the following format Red and Blue LUT entries are not important Green LUT indexes 0 7 should be programmed 0 F as in the table below Table 3 15 Recommended LUT Values for 8 bpp Gray Shade LUT Address Green LUT Data 00 00 01 02 02 04 03 06 04 08 05 0A 06 oC 07 OF This recommended LUT assumes that you are using only bank 0 Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 22 Epson Research and Development Vancouver Design Center 15 bpp Gray Shade Since the Look Up Table is bypassed in this mode the LUT programming is unimportant The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data Resulting in a maximum of 24 16 colors 16 bpp Gray
122. ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t6 RAS precharge time REG 22h bits 3 2 01 1 45t1 1 ns RAS precharge time REG 22h bits 3 2 10 1t1 1 ns 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 53 Vancouver Design Center 7 3 5 EDO DRAM Self Refresh Timing Stopped for Restarted for tl suspend mode active mode Memory Clock RAS CAS Figure 7 11 EDO DRAM Self Refresh Timing Table 7 11 EDO DRAM Self Refresh Timing Symbol Parameter Min Typ Max Units t1 Memory clock period 25 ns 2 RAS to CAS precharge time REG 22h bits 3 2 00 1 45 t1 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 0 45 t1 ns 3 CAS precharge time REG 22h bits 3 2 00 2t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 1t1 ns a CAS setup time REG 22h bits 3 2 00 or 10 0 45 t1 2 ns CAS setup time REG 22h bits 3 2 01 1t1 2 ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t5 RAS precharge time REG 22h bits 3 2 01 1 45t1 1 ns RAS precharge time REG 22h bits 3 2 10 1t1 1 ns Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 54 Epson Research and Development Vancouver Design Center 7 3 6 FPM DRAM Read Timing
123. of the three prime colors RGB be distributed evenly Table 6 3 shows the recommended RAMDAC palette data for 8 bpp Simultaneous Display Table 6 4 shows the related register data for some possible CRT options with an 8 bit Color 640X480 single passive panel 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 35 Vancouver Design Center Table 6 3 8 bpp Recommended RAMDAC palette data for Simultaneous Display Address R G B Address R G B Address R G B Address R G B 00 00 00 00 20 09 00 00 40 12 00 00 60 1B 00 00 01 00 00 15 21 09 00 15 41 12 00 15 61 1B 00 15 02 00 00 2A 22 09 00 2A 42 12 00 2A 62 1B 00 2A 03 00 00 3F 23 09 00 3F 43 12 00 3F 63 1B 00 3F 04 00 09 00 24 09 09 00 44 12 09 00 64 1B 09 00 05 00 09 15 25 09 09 15 45 12 09 15 65 1B 09 15 06 00 09 2A 26 09 09 2A 46 12 09 2A 66 1B 09 2A 07 00 09 3F 27 09 09 3F 47 12 09 3F 67 1B 09 3F 08 00 12 00 28 09 12 00 48 12 12 00 68 1B 12 00 09 00 12 15 29 09 12 15 49 12 12 15 69 1B 12 15 OA 00 12 2A 2A 09 12 2A 4A 12 12 2A 6A 1B 12 2A 0B 00 12 3F 2B 09 12 3F 4B 12 12 3F 6B 1B 12 3F 0C 00 1B 00 2C 09 1B 00 4C 12 1B 00 6C 1B 1B 00 0D 00 1B 15 2D 09 1B 15 4D 12 1B 15 6D 1B 1B
124. or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction sec sa AA A DA A A A ae 7 2 Interfacing to the MPC821 lt lt 8 2 1 The MPC8xxSystemBus 2 00 2 ee 8 2 2 MPC821 Bus Overview o 8 2 2 1 Normal Non Burst Bus Transactions ee 9 2 3 Memory Controller Module Pier Bl ake oy oat des e ae ie Bl aoe de AL 2 3 1 General Purpose Chip Select Module le GPCM ra at fas ho 11 2 3 2 User Programmable Machine UPM o e e 12 3 S1D13504 Host Bus Interface 13 3 1 Generic MPU Host Bus Interface Pin Mapping 2 2 2 13 3 2 Generic MPU Host Bus Interface Signals 2 2 0 14 4 MPC821 to S1D13504 Interface 15 4 1 Hardware Description e 1 4 2 Hardware Connections aia a a i Acs So Sa ee a DO 4 3 S1D13504 Ha
125. placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13504 Supported Evaluation Platforms 13504PWR has been tested with the following S1D13504 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC00O0 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13504 Programming Notes and Examples manual document number X19A G 002 xx Installation PC platform copy the file 13504PWR EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13504PWR to the system 13504PWR Software Suspend Power Sequencing Utility S1D13504 Issue Date 01 02 01 X19A B 007 04 Page 4 Usage Comments 1D13504 X19A B 007 04 Epson Research and Development Vancouver Design Center PC platform at the prompt type 13504pwr software 1cd enable disable i Embedded platform execute 13504pwr and at the prompt type the command line argument Where software selects software suspend 1cd selects the LCD enable activates software suspend or the LCD disable deactivates software
126. platforms e If you are running 13504CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number e At this time the drivers have been tested on the x86 CPUs and have been built with Plat form Builder v3 00 1D13504 Windows CE 3 x Display Drivers X19A E 006 01 Issue Date 01 05 08 EPSON S1D13XXX 32 Bit Windows Device Driver Installation Guide Document No X00A E 003 04 Copyright 1999 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32 Bit Windows Device Driver Installation Guide X00A E 003 04 Issue Date 01 04 17 Epson Research and Development Page 3 Vancouver Design
127. preo uonenien o i n04 sna vs ooogroseinss 30 0 DA ON ANNO BAG ANV HOWVASSH NOAA Na O Az Ags Of AE oun 6 638 oH am 2 visia A wi No 120 zel ano Z 4 v 30W 3381 oom E Z ZaSeenT yooanuy E Za Ti sony A IN so ejar X A T 7O fer ST HET oe LE eS veo oe or g i e SPINE l l l at doo tS v Y vy oss 2 os g ost ou z as Ls va Psa Po T su 2 ru Oem 020 Pio A El 1 se A OAV das e ae oon ana HE na eta PNW gz ame NAS 4 ps 7 a gt AMAS au eae a 7 7 z z e isu syova TT mn E 3 7 x z i a GY osu E osuova 9 El se z4 uw m9 ay LS umova sr SbLbNI t peah ca Faa Ta T UTE Tava rT 1vddy b LEE oo saved Tvt de Isiolas g f osova a srelv Oda O 09 nova ay 10 10 10 10 0699EOZ0Z1E Sdi TIHA 8 610024 38N0XO H434 LLLLOOSHZZ Ll Iv Epson Research and Development Vancouver Design Center S1D13504 X19A G 004 06 Figure 4 S1D13504B00C Schematic Diagram 4 of 6 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 Z wg Zes be equae S epsa 81d a Vancouver Design Center Epson Research and Development
128. register portions In this case 4 bpp the lower two bits are the pixel panning value and the upper bits are the start address pixel_pan pan_value AND 3 start_address pan_value SHR 3 shift right by 3 gives words 4 Write the pixel panning and start address values to their respective registers using the proce dure outlined in the registers section Example 5 Scrolling Up and Down To scroll down increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line To scroll up decrease the value in the Screen Display Start Address Register by the number of words in one virtual scan line Example 6 Scroll down one line for a 16 color 640x480 virtual image using a 320x240 single panel LCD 1 To scroll down we need to know how many words each line takes up At sixteen colors 4 bpp each byte contains two pixels so each word contains 4 pixels words offset pixels_per_line pixels_per_word 640 4 160 OxAO We now know how much to add to the start address to scroll down one line 2 Increment the start address by the number of words per virtual line start_address start_address words 3 Separate the start address value into three bytes Write the LSB to register 10h and the MSB to register 12h Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 28 4 3 Split Screen 4 3 1 Registers Epson Research and Development
129. shown in the screen 2 portion of the display Screen 1 memory is always the first memory displayed at the top of the screen followed by screen 2 memory However the start address for the screen 2 image may in fact be lower in memory than that of screen i e screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into display buffer While not particularly useful it is possible to set screen 1 and screen 2 to the same address 4 3 2 Examples Example 7 Display 380 scanlines of image 1 and 100 scanlines of image 2 Image 2 is locat Programming Notes and Examples Issue Date 01 02 01 ed immediately after image 1 in the display buffer Assume a 640x480 display and a color depth of 1 bpp The value for the line compare is not dependent on any other setting so we can set it immedi ately 380 0x17C Write the line compare registers OFh with 0x01 and register OEh with 0x7C Screen is coming from offset 0 in the display buffer Although not necessary ensure that the screen 1 start address is set to zero Write 0x00 to registers 10h 11h and 12h Calculate the size of the screen image so we know where the screen 2 image is located This calculation must be performed on the virtual size offset register Since a virtual size was not specified assume the virtual size to be the same as the physical size offset pixels_per_line pixels_pe
130. the Phi Issue Date 01 10 26 Page 5 List of Tables Generic MPU Host Bus Interface Pin Mapping o 9 S1D13504 Configuration for Direct Connection o o o 13 S1D13504 Host Bus Selection for Direct Connection o o oo 13 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping 19 PR31500 PR31700 to PC Card Slots Address Remapping using the IT8368E 19 S1D13504 Configuration using the IT8368E o o 20 S1D13504 Host Bus Selection using the IT8368 o 20 List of Figures Typical Implementation of S1D13504 to PR31500 PR31700 Direct Connection 11 S1D13504 to PR31500 PR31700 Connection using One IT8368 15 S1D13504 to PR31500 PR31700 Connection using Two IT8368E 17 lips MIPS PR31500 PR31700 Processor S1D13504 X19A G 005 09 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD CRT Controller and the Philips MIPS PR31500 PR31700 processor The designs described in this document are presented only as examples of how such interfaces migh
131. the S1D13504 Color Graphics LCD CRT Controller running under the Microsoft Windows CE 2 x operating system The driver is capable of 4 8 and 16 bit per pixel display modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at techpubs Oerd epson com Windows CE 2 x Display Drivers 1D13504 Issue Date 01 05 25 X19A E 001 05 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for 1 Windows CE 2 0 using a command line interface 2 Windows CE Platform Builder 2 1x using a command line interface In all examples x refers to the drive letter where Platform Builder is installed Build for CEPC X86 on Windows CE 2 0 using a Command Line Interface 1D13504 X19A E 001 05 To build a Windows CE v2 0 display driver for the CEPC X86 platform using a S5U13504B00C evaluation board follow the instructions below 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the E
132. the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504SHOW Demonstration Program X19A B 002 05 Issue Date 01 01 30 Epson Research and Development Page 3 Vancouver Design Center 13504SHOW 13504SHOW demonstrates 1D13504 display capabilities by drawing a pattern image at different pixel depths i e 16 bits per pixel 2 bits per pixel etc on the display The 13504SHOW display utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13504CFG EXE which can be used to configure 13504SHOW This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection
133. to complete operation because registers have not been initialized int seValidRegisteredDevice int device Description Determines if the device handle is valid Parameter device registered device ID Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seValidStdDevice int device Description Determines if the device handle is HAL_STDOUT or HAL_STDIN Parameter device registered device ID Return Value ERR_OK operation completed with no problems ERR_HAL_DEVICE_ERR could not find free device handle 8 2 2 Screen Manipulation int seDisplayEnable int device BYTE NewState Description Performs the necessary power sequencing to enable or disable the display Parameter device registered device ID NewState use the predefined definitions ENABLE and DISABLE Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_FAILED unable to complete operation because registers have not been initialized Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 42 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center int seGetBitsPerPixel int device BYTE pBitsPerPixel Description Determines the color depth of current display mode Parameter device registered device ID pBitsPerPixel if ERR_OK pBitsPerPixel set Return Value ERR_OK ope
134. to high and a 0 in this bit drives GPIO8 to low When GPIO8 is configured as an input a read from this bit returns the status of GPIO8 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO8 other wise the DACRSO pin is controlled automatically and this bit will have no effect on hardware Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Page 107 REG 22h Performance Enhancement Register 0 RW EDO Read Write Delay RC Timing Value Bit 1 RC Timing Value Bit 0 RAS to CAS Delay RAS Precharge Timing Bit 1 RAS Precharge n a Timing Bit 0 Reserved bit 7 bits 6 5 Note Changing this register to non zero value or to a different non zero value should be done only when there are no read write DRAM cycles This condition occurs when both the Display FIFO is disabled REG 23h bit 7 1 and the Half Frame Buffer is disabled REG 1Bh bit 0 1 For programming information see 1D13504 Programming Notes and Examples document number X19A G 002 xx EDO Read Write Delay This bit is used for EDO DRAM to select the delay during the read write transition A 0 selects 2 MCLK delay for the read write transition A 1 selects 1 MCLK delay for the read write DRAM This bit has no effect for FPM DRAM which always uses 1 MCLK delay for the read write transi tion
135. to the S1D13504 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1D13504 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS signal is not used for the Generic MPU host bus interface and must be connected to IO Vpp Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Page 11 Vancouver Design Center 4 Direct Connection to the Philips PR31500 PR31700 4 1 Hardware Description The S1D13504 is easily interfaced to the Philips PR31500 PR31700 processor In the direct connection implementation the S1D13504 occupies PC Card slot 1 of the PR31500 PR31700 Although the address bus of the PR31500 PR31700 is multiplexed it can be demultiplexed using an advanced CMOS latch e g 74ACT373 The direct connection implementation makes use of the Generic MPU host bus interface capability of the 1D 13504 The following diagram demonstrates a typical implementation of the PR31500 PR31700 to 1D13504 interface S1D13504 PR31500 PR31700 s gt RDO RD gt WE RD1 CARD1CSL ELAES cm gt WEO CARD1CSH e gt WE1 gt CS Latch A23 gt M R ALE gt gt System RE
136. top half The chip select should have its RO Read Only bit set to 0 and the WAIT field Wait states should be set to 111 to allow the S1D13504 to terminate bus cycles externally Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CKG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the Motorola MC68328 Dragonball Microprocessor S1D13504 Issue Date 01 10 26 X19A G 013 03 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Motorola Inc MC68328 DragonBall Integrated Microprocessor User s Manual Motorola Publication no MC68328UM AD Epson Research and Development Inc S1D13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx Epso
137. trademark of Seiko Epson Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Linux Console Driver X19A E 004 01 Issue Date 01 11 19 Epson Research and Development Page 3 Vancouver Design Center Linux Console Driver Linux Console Driver Issue Date 01 11 19 The Linux console driver for the S1D13504 Embedded Memory LCD Controller is intended as reference source code for OEMs developing for Linux and supports 4 and 8 bit per pixel color depths A Graphical User Interface GUI such as Gnome can obtain the frame buffer address from this driver allowing the Linux GUI the ability to update the display The console driver is designed around a common configuration include file called s1d13504 h which is generated by the configuration utility 13504DCFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13504DCFG see the 13504DCFG Driver Configuration Program User Manual document number X19A B 008 xx Note The Linux console driver is provided as reference source code only The driver is in tended to provide a basis for OEMs to develop their own drivers for Linux This document and the source code for the Linux console drivers are updated as appro priate Please check the Epson Research and Development website at http www erd epson com for the latest revisions or before beginning
138. view the entire image The 13504VIRT display utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13504CFG EXE which can be used to configure 13504VIRT This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13504 Supported Evaluation Platforms Installation 13504VIRT Display Utility Issue Date 01 01 30 13504VIRT has been tested with the following S1D13504 supported evaluation platforms PC system with an Intel 80x86 processor M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13504 Programming Notes and Examples manual document number X19A G 002 xx PC
139. wel reset breset inversion appears in pin declaration section 4 4 Register Memory Mapping 1D13504 X19A G 009 05 The S1D13504 is a memory mapped device The internal registers are mapped in the lower PC Card memory address space starting at zero The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card memory address space ranging from 200000h to 3fffffh The PC Card socket provides 64M bytes of address space Without further resolution on the decoding logic M R connected to A21 the entire register set is aliased for every 64 byte boundary within the specified address range above Since address bits A 25 22 are ignored the S1D13505 registers and display buffer are aliased 16 times Note If aliasing is not desirable the upper addresses must be fully decoded Interfacing to the PC Card Bus Issue Date 01 02 02 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and Windows CE v
140. 0 OF 00 03 00 0A 0A 0B 00 OF OF 04 0A 00 00 0C OF 00 00 05 0A 00 0A 0D OF 00 OF 06 0A 0A 00 0E OF OF 00 07 0A 0A 0A OF OF OF OF 8 bpp Color In 8 bpp color mode pixel bits 7 5 represent the red LUT index bits 4 2 represent the green LUT index and bits 1 0 represent the blue LUT index It is recommended that the three LUTs are programmed according to the following format Table 3 11 Recommended LUT Values For 8 bpp Color Mode Address Red Green Blue 00 00 00 00 01 03 03 05 02 05 05 OA 03 07 07 OF 04 09 09 bank 1 05 0B 0B bank 1 06 oD 0D bank 1 07 OF OF bank 1 Programming Notes and Examples 1D13504 X19A G 002 07 Page 20 Gray Shade Modes 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center This recommended palette assumes that you are using only bank 0 of the three color components By programming in the above fashion the following colors will result Table 3 12 Examples of 256 Pixel Colors Using Linear LUT Pixel Value Pixel Value binary Color inei Color 000 000 00 black 000 000 00 black 000 000 10 dark blue 000 000 11 bright blue 000 100 00 dark green 000 111 00 bright green 000 100 10 dark cyan 000 111 11 bright cyan 100 000 00 dark red 111 000 00 bright red 100 000 10 dark magenta 111 000 11 bright magenta 100 100 00 dark yellow 11
141. 000 10 Figure 4 1 Typical Implementation of MPC821 to S1D13504 Interface 15 Interfacing to the Motorola MPC821 Microprocessor S1D13504 Issue Date 01 10 26 X19A G 010 06 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD CRT Controller and the Motorola MPC821 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8xx System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of
142. 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 S1D13504 X19A G 013 03 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 EPSON 1D13504 Color Graphics LCD CRT Controller Interfacing to the PC Card Bus Document Number X19A G 009 05 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01
143. 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13504 X19A G 011 07 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MCF5307 Coldfire Microprocessor Issue Date 01 02 02 EPSON 1D13504 Color Graphics LCD CRT Controller Interfacing to the Toshiba MIPS TX3912 Processor Document Number X19A G 012 05 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON
144. 08 Issue Date 01 10 26 EPSON 1D13504 Color Graphics LCD CRT Controller Interfacing to the Motorola MC68328 Dragonball Microprocessor Document Number X19A G 013 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents dl INTFOGUCTION saaa 6 cer doce ay a AA as Ge ee a a 7 2 Interfacing to the MC68328 8 2 The 68328 System BSc a a a he a A 8 2 2 Chip Select Mod le s iio a A ee ce a 8 3 S1D13504 Host Bus Interface 9 3 1 Generic MPU Host Bus Interface Pin Ma
145. 1 gt 4 bit Green data output Blue Look Up Table 0 gt 1 gt 4 bit Blue data output Figure 12 4 1 Bit Per Pixel 2 Level Color Look Up Table Architecture Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 124 2 Bit Per Pixel Color Mode Epson Research and Development Vancouver Design Center Red Look Up Table Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits 1 0 00 01 Bank Select Logic 10 olla REG 27h bits 5 4 Selected Bank 4 bit Red data output Green Look Up Table Bank 0 0 1 2 3 Bank 1 4 5 6 ES Bank 2 8 9 A B Bank 3 C D E F Bank Select bits 1 0 00 01 Bank Select Logic 10 REG 27h bits 1 0 Selected Bank 4 bit Green data output A Blue Look Up Table k Bank 0 0 1 2 3 Bank 1 4 5 6 E Bank 2 8 9 A B Bank 3 C D E F Bank Select bits 1 0 00 01 Bank Select Logic 10 REG 27h bits 3 2 Selected Bank
146. 1 111 00 bright yellow 100 100 10 gray 111 111 11 white 15 bpp Color Since the Look Up Table is bypassed in this mode the LUT programming is unimportant The colors on the display are derived from only the top 4 bits of each color combination Resulting in a maximum of 2 2 4096 colors 16 bpp Color Since the Look Up Table is bypassed in this mode the LUT programming is unimportant The colors on the display are derived from only the top 4 bits of each color combination Resulting in a maximum of 2 2 4096 colors In gray shade mode the S1D13504 treats the Green LUT as a 16 position 4 bit wide monochrome LUT Depending on the selected pixel size this LUT will provide from 1 to 4 banks 1 bpp Gray Shade The S1D13504 has no true Black and White mode bpp Gray consists of a single bank of two entries For Black and White mode the LUT entry must be programmed as such Table 3 13 Recommended LUT Values for 1 bpp Gray Shades Index Look Up Table Data hex hex 00 00 01 OF Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 21 Vancouver Design Center 2 bpp Gray Shade In 2 bpp gray shade mode the 16 LUT entries are divided into four separate banks each having four entries Table 3 14 Recommended LUT Values for 2 bpp Gray Shades index Look Up Table Data hex hex 00 00 01 05 02 0A 03 OF 4 bpp Gray Shade In 4 bpp gray shade
147. 1 30 X19A B 001 04 Page 4 13504CFG EXE Program Requirements Table of Contents Installation Usage Script Mode Interactive Mode 13504CFG Menu Bar Viewing 13504CFG Menu Contents Making 13504CFG Menu Selections Files Menu Advanced Memory 020 eee eee ee eee Power Management 2 0 ssc oe a la we e Lookup Table LUD e iaa sewn tee a Se we Se oS i SETUP nie Gk BS is is ee AS ee ee oS Help Menu Comments Sample Program Messages 1D13504 X19A B 001 04 Epson Research and Development Vancouver Design Center 13504CFG EXE Configuration Program Issue Date 01 01 30 Epson Research and Development Page 5 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG EXE Configuration Program 1D13504 Issue Date 01 01 30 X19A B 001 04 Page 6 Epson Research and Development Vancouver Design Center List of Figures Figure 1 13504CFG Menu B f i o ye a A ee eh he ee eee ee ae ee 10 Fipgure 2 13504CFG Open Files se 2a chars aye ee ASE A Dew ee Pa OA ek Ro weal 11 Figure3 13504CFG Files Menu os ss ad Ae ae ee eA RRs Ee ees 12 Figure 4 13504CFG View Menu 0 00 00 a 13 Figure 5 13504CFG Current Configuration 14 Figure 6 13504CFG Advanced Configuration Partial View of Screen o o a 14 Figure 7 13504CFG Device Meda 2 tonar edia a e e eea ee 15 Figure 8 13504CFG Panel Setup 16 Figure 9 13504CFG Edit Panel Setup c o s ie eo Boe E a e a be 17 Figure 10 13504CFG Pa
148. 100 0000 0 set starting address of S1D13504 to 40 0000h e AT 0 2 0 ignore address type bits e PS 0 1 1 0 memory port size is 16 bit e PARE 0 disable parity checking e WP 0 disable write protect e MS 0 1 0 0 select General Purpose Chip Select module to control this chip select e V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits S1D13504 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by Y clock cycle from address lines e BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below SETA 1 the 1D13504 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 20 4 6 Test Software Epson Research and Development Vancouver Design Center The test software used to exercise this interface is very simple It carries out the following functions 1 Configures chip select 4 on the MPC821 to map the S1D13504 to an unused 4M byte block of address space Loads the appropriate values into the opti
149. 120 142 TOFP15 128 SIDI3504FOIA 2 2 ee 130 14 3 QFP20 144 S1D13504FO2A 2 20220202020 2 2 0 131 15 References a ees a SA ae a es la a ada acetal da ae es 132 16 Sales and Technical Support 4 2 133 Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 7 Vancouver Design Center List of Tables Table 2 1 1D13504 Series Package liSt ee ee 13 Table 5 1 Host Interface Pin Descriptions 0 0 0000000000 00004 21 Table 5 2 Memory Interface Pin Descriptions 0 0 0000000000004 24 Table 5 3 LCD Interface Pin Descriptions 0 2 20 000000000 0000 26 Table 5 4 Clock Input Pin Description 0 00200 000 000 0000 0000 26 Table 5 5 CRT and RAMDAC Interface Pin Descriptions e 27 Table 5 6 Miscellaneous Pin Descriptions 0 000 000 00 eee ee eee 29 Table 5 7 Power Supply Pin Descriptions 2 00 00 0 00000020000 29 Table 5 8 Summary of Power On Reset Options 0 000 000 0000 000 30 Table 5 9 Host Bus Interface Pin Mapping 0 000000 0 000000000004 31 Table 5 10 Memory Interface Pin Mapping 0 a 32 Table
150. 13504CFG EXE Configuration Program 1D13504 Issue Date 01 01 30 X19A B 001 04 Page 12 Epson Research and Development Vancouver Design Center Making 13504CFG Menu Selections 1D13504 X19A B 001 04 In 13504CFG a selection is made by clicking the left mouse button or by pressing the tab and arrow keys on the keyboard In the example below there are three ways to select and open 13504SHOW EXE in the Files box in the Open File window figure 2 Mouse e Click the left mouse button on 13504SHOW EXE to highlight it in the Files box Then click on the OK button e Point to the file 13504SHOW EXE with the arrow and click the left mouse button twice in rapid succession double clicking Keyboard Press lt Tab gt to highlight the Files box or press lt Alt gt lt F gt Press lt gt to highlight 13504SHOW EXE Press lt Enter gt All selections in 13504CFG can be made in one of the three ways listed above File Name 1354SHOW EXE C 1354 Files Drives 1354CFG EXE 1354MEM EXE 1354PLAY EXE GO32 EXE OBJCOPY EXE A C R System Disk 4 Directories LHL Figure 2 13504CFG Open File 13504CFG EXE Configuration Program Issue Date 01 01 30 Epson Research and Development Page 13 Vancouver Design Center Files Menu Files View Device Open Figure 3 13504CFG Files Menu The Files menu contains these functions e Open reads the HAL configuration for a g
151. 2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the PC Card Bus 1D13504 Issue Date 01 02 02 X19A G 009 05 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents PCMCIA JEIDA PC Card Standard March 1997 Epson Research and Development Inc S1D13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc 1D13504 Programming Notes and Examples Document Number X19A G 002 xx e Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx 6 2 Document Sources e PC Card Website http www pc card com e Epson Electronics America Website http www eea epson com 1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13504 Japan i North America Seiko Epson Corporation o Epson Electronics America Inc Electronic Devices Marketing Division 150 River Oaks Parkway 421 8 Hino Hino shi San Jose CA 95134 USA Tokyo 191 8501 Japan Tel 408 922 0200 Tel 042 587 5812 Fax 408 922 0238 Fax 042 587 5564 http www eea epson com http Awww epson co jp Hong Kong Europe Epson Hong Kong Lid Epson Europe Electronics GmbH 20 F Harbour Cent
152. 21 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de 8 2 Philips MIPS PR31500 PR31700 Processor Philips Semiconductors Handheld Computing Group 4811 E Arques Avenue M S 42 P O Box 3409 Sunnyvale CA 94088 3409 Tel 408 991 2313 http www philips com 8 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Page 23 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg S1D13504 X19A G 005 09 Page
153. 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 EPSON S1D13504 Color Graphics LCD CRT Controller Power Consumption Document Number X19A G 006 04 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Power Consumption X19A G 006 04 Issue Date 01 02 02 Epson Research and Development Page 3 Vancouver Design Center 1 S1D13504 Power Consumption Power Consumption Issue Date 01 02 02 S1D13504 power consumption is affected by many system design variables Input clock frequency CLKI the CLKI frequency determines the LCD frame rate CPU perfor mance to memory and other functions the highe
154. 3 t8 VRTC cycle time note 4 t9 VRTC pulse width shown active low note 5 t10 horizontal display period note 6 t11 HRTC setup to DACCLK rising edge 0 45 Ts t12 VRTC falling edge to FPLINE falling edge note 7 phase difference t13 BLANK to DACCLK rising edge setup time 0 45 Ts t14 BLANK pulse width note 8 t15 BLANK falling edge to HRTC falling edge note 9 t16 BLANK hold from DACCLK rising edge 0 45 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 t6min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 3 oe REG 07h bits 3 0 1 8 Ts 4 t8 min REG 09h bits 1 0 REG O8h bits 7 0 1 REG OAh bits 6 0 1 lines 5 eh REG OCH bits 2 0 1 lines 6 t1Omin REG 04h bits 6 0 1 8 Ts 7 tl2min REG O6h bits 4 0 1 8 Ts 8 t14min REG 04h bits 6 0 1 8 Ts 9 15min REG 06h bits 4 0 1 8 2 Ts Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 88 Epson Research and Development Vancouver Design Center 7 4 14 External RAMDAC Read Write Timing Read t1 t2 gt AB 20 0 CS y M R DACRS 1 0 X Valid RD Command depends on CPU bus DACRD Write Valid WR command depends on CPU bus t5 DACWR 4 18 gt Figure 7 41
155. 3504 Issue Date 01 11 06 X19A A 002 19 Page 118 Epson Research and Development Vancouver Design Center 11 Clocking 11 1 Maximum MCLK PCLK Ratios Table 11 1 Maximum PCLK Frequency with EDO DRAM Maximum PCLK Allowed Display type Nec E bpp 2bpp 4bpp 8bpp 16bpp e Single Panel e CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 4 3 MCLK e Simultaneous CRT Single Panel e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled Dual Monochrome Panel with Half Frame Buffer Enabled Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK MCLK MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Dual Color Panel with Half Frame Buffer Enabled e Simultaneous CRT Dual Color Panel with Half Frame Buffer Enable w i AJo AJA Table 11 2 Maximum PCLK Frequency with FPM DRAM Maximum PCLK allowed Display type NRC a bpocll 2bpp abp Sbpp 46 bpp e Single Panel e CRT e Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 4 3 MCLK e Simultaneous CRT Single Panel e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disa
156. 3504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Block Diagram of MC68328 to SID13504 Interface MC68000 Bus I Interface Mode 1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 X19A G 013 03 Page 12 Epson Research and Development Vancouver Design Center If UDS and or LDS are required for their alternate I O functions then the 68328 to S1D13504 interface may be realized using the S1D13504 Generic bus interface mode The electrical connections required for this interface are shown below Note that in either case the DTACK signal must be made available for the S1D13504 since it inserts a variable number of wait states depending upon CPU LCD synchronization and the LCD panel display mode being used A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle MC68328 S1D13504 A21 M R A 20 1 AB 20 1 D 15 0 SD 15 0 CSB3 CS Vcc 470 DTACK WAIT UWE WE1 LWE WEO OE RD1 RDO CLKO BUSCLK System RESET _________ RESET Note When connecting the S1D13504 55 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 55 e g CPU reset can be asserted during wake up from power down modes or during debug states 1D13504 X19A G 013 03 Fig
157. 3504 Host Bus Interface Page 9 This section is summary of the bus interface modes available on the S1D13504 and offers some detail on the Generic MPU host bus interface used to implement the interface to the MC68328 The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debugging 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping UPRA Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to IO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET 1D13504 X19A G 013 03 Page 10 Epson Research and Development Vancouver Design C
158. 39 x y LD1 1 65 Y 1 B10X 1 R16 X SS Y1 R640 x X LDO ee Ar anar XK 1 B640 Ly Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 29 Single Color 16 Bit Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAN bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 75 Vancouver Design Center Sync Timing a gt ES FPFRAME t4 la t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 E t9 t7 t14 t11 t10 4 gt FPSHIFT t12 t13 gt gt UD 7 0 1 2 LD 7 0 Figure 7 30 Single Color 16 Bit Panel A C Timing Table 7 24 Single Color 16 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT pe
159. 5 Note that for EDO DRAM and Npp 1 5 this bit is automatically forced to 0 to select 2 MCLK for Nrcp This is done to satisfy the CASH address setup time tasc The resulting tec is related to Npcp as follows Nrcp Tu 1 5 Tm Nrcp 0 5 TM Neco Tm if EDO and Npp or 2 if EDO and Npp 1 5 if FPM and Npp 1 or 2 if FPM and Npp 1 5 Table 8 12 RAS to CAS Delay Timing Select REG 22h Bit 4 Naco RAS to CAS Delay taco 0 2 Tu 1 mer RAS Precharge Timing Npp Bits 1 0 Minimum Memory Timing for RAS precharge These bits select the DRAM RAS Precharge timing parameter tgp These bits specify the number Npp of MCLK periods Ty used to create tpp see the following formulae Note these formulae assume an MCLK duty cycle of 50 5 Nrp 1 1 5 2 1f trr Ty lt 1 if 1 lt tap Tyy lt 1 45 if tap Ty gt 1 45 The resulting tgc is related to Npp as follows tre tre Npp Tu if FPM refresh cycle and Npp 1 or 2 for all other Table 8 13 RAS Precharge Timing Select REG 22h Bits 3 2 Npp RAS Precharge Width tpp 00 2 2 Tm 01 1 5 1 5 Ty 10 1 1 Tm 11 Reserved Reserved Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Optimal DRAM Timing The following table contains the optimally programmed values of Ngc Npp and Npcp for different DRAM types
160. 504 COLOR GRAPHICS LCD CRT CONTROLLER February 2001 E DESCRIPTION The S1D13504 is a low cost low power color monochrome LCD CRT controller interfacing to a wide range of CPUs and LCDs The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where Windows CE may serve as a primary operating system The S1D13504 supports LCD interfaces with data widths up to 16 bits Using Frame Rate Modulation FRM it can display 16 shades of gray on monochrome LCD panels up to 4096 colors on passive color LCD and 64K colors on active matrix TFT LCD panels CRT support is handled through the use of an external RAMDAC interface allowing simultaneous display of both the CRT and LCD panel A 16 bit memory interface supports up to 2M bytes of FPM DRAM or EDO DRAM Supports flexible operating voltages from 2 7V to 5 5V E FEATURES Memory Interface e 16 bit EDO DRAM or FPM DRAM interface e Memory size options 512K bytes using one 256Kx16 device 2M bytes using one 1Mx16 device e Addressable as a single linear address space CPU Interface e Supports the following interfaces Hitachi SH 3 Motorola M68K ISA bus MPU bus interface with programmable READY i386 486 bus Philips MIPS PR31500 31700 NEC MIPS VR4102 e CPU write buffer Display Support e 4 8 bit monochrome passive LCD interface e 4 8 16 bit color passive LCD interface
161. 7 of the S1D13504 11 Ground 12 Ground 13 Connected to DB8 of the S1D13504 14 Connected to DB9 of the S1D13504 15 Connected to DB10 of the S1D13504 16 Connected to DB11 of the S1D13504 17 Ground 18 Ground 19 Connected to DB12 of the S1D13504 20 Connected to DB13 of the S1D13504 21 Connected to DB14 of the S1D13504 22 Connected to DB15 of the S1D13504 23 Connected to RESETH of the S1D13504 24 Ground 25 Ground 26 Ground 27 12 volt supply 28 12 volt supply 29 Connected to WEO of the S1D13504 30 Connected to WAIT of the S1D13504 31 Connected to CS of the S1D13504 32 Connected to MR of the S1D13504 33 Connected to WE 1 of the S1D13504 34 Not connected S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 Epson Research and Development Vancouver Design Center Table 4 2 CPU BUS Connector H2 Pinout Connector Comments Pin No 1 Connected to ABO of the S1D13504 2 Connected to AB1 of the S1D13504 3 Connected to AB2 of the S1D13504 4 Connected to AB3 of the S1D13504 5 Connected to AB4 of the S1D13504 6 Connected to AB5 of the S1D13504 7 Connected to AB6 of the S1D13504 8 Connected to AB7 of the S1D13504 9 Ground 10 Ground 11 Connected to AB8 of the S1D13504 12 Connected to AB9 of the S1D13504 13 Connected to AB10 of the S1D13504 14 Connected to AB11 of the S1D13504 15 Connected to AB12
162. 7h 0000 0000 0000 0000 set look up table to bank O REG 2Ch Beene P set write mode address to 0 REG 2Eh load RAMDAC palette data Page 37 S1D13504 X19A G 002 07 Page 38 Epson Research and Development Vancouver Design Center 7 Identifying the S1D13504 Unlike previous generations of S1D1350x products the S1D13504 can be identified at any time after power on reset The S1D13504 and future 1D1350x products can be identified by reading REG 00h The value of this register for the S1D13504F00A is 04h 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 39 Vancouver Design Center 8 Hardware Abstraction Layer HAL 8 1 Introduction The HAL is a processor independent programming library provided by Seiko Epson HAL provides an easy method to program and configure the S1D13504 HAL allows easy porting from one S1D1350x product to another and between system architectures HAL is included in the utilities provided with the 1D13504 evaluation system 8 2 API for 13504HAL 8 2 1 Initialization The following is a description of the HAL library Updates and revisions to the HAL may include new functions not included in the following documentation int seDeRegisterDevice int device Description Removes a device s handle from the HAL library Parameter device registered device ID Return Value ERR_OK operation completed with no problems ERR_INVALID_REG
163. 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 7 26 Figure 7 27 Figure 7 28 Figure 7 29 Figure 7 30 Figure 7 31 Figure 7 32 Hardware Functional Issue Date 01 11 06 Page 9 List of Figures Typical System Diagram SH 3 Bus 1Mx16 FPM EDO DRAM 14 Typical System Diagram MC68K Bus 1 1Mx16 FPM EDO DRAM 16 Bit MC68000 14 Typical System Diagram MC68K Bus 2 256Kx16 FPM EDO DRAM 32 Bit MC68030 15 Typical System Diagram Generic Bus 1Mx16 FPM EDO DRAM 15 System Block Diagram Showing Datapaths 16 Pinout Diagram of FOOA caco o rc a a eG e a Se a 18 Pinout Diagram of FOTA comete mao ht a ee ee ee teca at 19 Pinout Diagramiof POZA oi AA A A ORR See ee RE 20 SH 3 Interface Timing ss bp ee Re ee ee eR eee 36 MC68K Bus 1 Interface Timing 0200 02 00 000 38 MC68K Bus 2 Interface Timing 40 Generic MPU Interface Synchronous Timing e 42 Generic MPU Interface Asynchronous TiMiNB e 44 Clock Input Requirements 2 0 00 0000000000000 0004 46 EFDO DRAM Read TIME 22 904 e A we Qi a a ee E PR a 46 EDO DRAM Write Timings oil E E we soe bod eed A Os 48 EDO DRAM Read Write Timing 50 EDO DRAM CAS Befo
164. AMDAC for a read mode address register access The RAM DAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits 7 0 in a Little Endian system or data bus bits 15 8 in a Big Endian system RAMDAC Write Mode Address Register REG 2Ch or REG 2Dh RW RAMDAC Address Bit 7 RAMDAC Address Bit 6 RAMDAC Address Bit 5 RAMDAC Address Bit 4 RAMDAC Address Bit 3 RAMDAC Address Bit 2 RAMDAC Address Bit 1 RAMDAC Address Bit 0 bits 7 0 RAMDAC Write Mode Address Bits 7 0 A CPU read or write to this register will generate a DACRD or DACWR pulse and DACRS1 0 and DACRSO 0 to the external RAMDAC for a write mode address register access The RAM DAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits 7 0 in a Little Endian system or data bus bits 15 8 in a Big Endian system RAMDAC Palette Data Register REG 2Eh or REG 2Fh RW RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 bits 7 0 RAMDAC Palette Data Bits 7 0 A CPU read or write to this register will generate a DACRD or DACWR pulse and DACRS1 0 and DACRSO to the external RAMDAC for a palette data register access The RAMDAC data must be transferred directly be
165. AR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write protect e AM 0 enable alternate bus master access to the S1D13504 e C I 1 disable CPU space access to the S1D13504 e SC 1 disable Supervisor Code space access to the S1D13504 e SD 0 enable Supervisor Data space access to the S1D13504 e UC 1 disable User Code space access to the S1D13504 e UD 0 enable User Data space access to the S1D13504 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 011 07 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CEG or by directly modifying the source The Windows CE v2 0 displa
166. AT6 13 and 4 D2 D6 UD2 D2 D6 D6 UD2 UD2 B2 B3 B5 FPDAT7 15 D3 D7 UD3 D3 D7 D7 UD3 UD3 B1 B2 B4 FPDAT8 17 LD4 BO B1 B3 FPDAT9 19 LD5 RO R2 FPDAT10 21 LD6 R1 FPDAT11 23 LD7 GO G2 FPDAT12 25 UD4 G1 FPDAT13 27 UD5 GO FPDAT14 29 UD6 BO B2 FPDAT15 31 UD7 B1 FPSHIFT 33 FPSHIFT DRDY 35 and 38 MOD FPSHIFT2 MOD DRDY FPLINE 37 FPLINE FPFRAME 39 FPFRAME 2 26 GND Even Pins a N C 28 N C VLCD 30 Adjustable 23 to 14V negative LCD bias LCDVCC 32 5V or 3 3V according to JP5 12V 34 12V VDDH 36 Adjustable 24 to 40V positive LCD bias LCDPWR 40 Panel Enable active low or active high according to JP6 Sa Driven low Note For FPDATxx to LCD interface hardware connections refer to the Display Interface AC Timing section of the 1D13504 Hardware Functional Specification document number X19A A 002 xx S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 1D13504 X19A G 014 01 Page 20 Epson Research and Development Vancouver Design Center 4 3 2 Buffered LCD Connector J1 provides the same LCD panel signals as those directly from S1D13504 but with voltage adapting buffers which can be set to 3 3V or 5V Pin 32 on this connector provides power for the LCD panel logic at the same voltage as the buffer power supply 4 3 3 Adjustable LCD Panel Positive Power Supply VDDH Most passive LCD color and passive single monochrome LCD panels require a positive bias voltage between 24V and 40V The S5U13504B00C use
167. Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 S1D13504 X19A G 012 05 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26
168. B Address R G B 80 24 00 00 AO 2D 00 00 CO 36 00 00 EO 3F 00 00 81 24 00 15 Al 2D 00 15 C1 36 00 15 E1 3F 00 15 82 24 00 2A A2 2D 00 2A C2 36 00 2A E2 3F 00 2A 83 24 00 3F A3 2D 00 3F C3 36 00 3F E3 3F 00 3F 84 24 09 00 A4 2D 09 00 C4 36 09 00 E4 3F 09 00 85 24 09 15 A5 2D 09 15 C5 36 09 15 E5 3F 09 15 86 24 09 2A A6 2D 09 2A C6 36 09 2A E6 3F 09 2A 87 24 09 3F A7 2D 09 3F C7 36 09 3F E7 3F 09 3F 88 24 12 00 A8 2D 12 00 C8 36 12 00 E8 3F 12 00 89 24 12 15 A9 2D 12 15 C9 36 12 15 E9 3F 12 15 8A 24 12 2A AA 2D 12 2A CA 36 12 2A EA 3F 12 2A 8B 24 12 3F AB 2D 12 3F CB 36 12 3F EB 3F 12 3F 8C 24 1B 00 AC 2D 1B 00 CC 36 1B 00 EC 3F 1B 00 8D 24 1B 15 AD 2D 1B 15 CD 36 1B 15 ED 3F 1B 15 8E 24 1B 2A AE 2D 1B 2A CE 36 1B 2A EE 3F 1B 2A 8F 24 1B 3F AF 2D 1B 3F CF 36 1B 3F EF 3F 1B 3F 90 24 24 00 BO 2D 24 00 DO 36 24 00 FO 3F 24 00 91 24 24 15 B1 2D 24 15 D1 36 24 15 F1 3F 24 15 92 24 24 2A B2 2D 24 2A D2 36 24 2A F2 3F 24 2A 93 24 24 3F B3 2D 24 3F D3 36 24 3F F3 3F 24 3F 94 24 2D 00 B4 2D 2D 00 D4 36 2D 00 F4 3F 2D 00 95 24 2D 15 B5 2D 2D 15 D5 36 2D 15 F5 3F 2D 15 96 24 2D 2A B6 2D 2D 2A D6 36 2D 2A F6 3F 2D 2A 97 24 2D 3F B7 2D 2D 3F D7 36 2D 3F F7 3F 2D 3F 98 24 36 00 B8 2D 36 00 D8 36 36 00 F8 3F 36 00 99 24 36 15 B9 2D 36 15 D9 36 36 15 F9 3F 36 15 9A 24 36 2A BA 2D 36 2A DA
169. B8 D8 P12 A15 DB7 D9 P12 C15 DB6 D10 P12 D15 DB5 D11 P12 A14 DB4 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center Page 17 Table 4 1 List of Connections from MPC821ADS to S1D13504 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13504 Signal Name D12 P12 B14 DB3 D13 P12 D14 DB2 D14 P12 B13 DB1 D15 P12 C13 DBO SRESET P9 D15 RESET SYSCLK P9 C2 BUSCLK CS4 P6 D13 CS TA P6 B6 WAIT WEO P6 B15 WE1 WE1 P6 A14 WEO OE P6 B16 RD1 RDO P12 A1 P12 B1 P12 A2 P12 B2 Gnd P12 A3 P12 B3 P12 A4 P12 B4 Vss P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Note Note that the bit numbering of the Power PC bus signals is reversed from convention e g the most significant address bit is AO the next is Al A2 etc Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 S1D13504 X19A G 010 06 Page 18 Epson Research and Development Vancouver Design Center 4 3 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx The tables below show only those configuration settings important to the MPC821 interface Table 4 2 Summary of
170. BBRERRBREBEBEE A 355555555555555535235555555555555555 NISBBISRLBRLSSSYAZ6OR anro aro aro santo ezo qe Tov Ha 5 3 Sd eeo 289 189 089 EN al ZN m sav IND 8z0w t 1A 4 ast 0199A szol ied 0801 EN 1201 ezv SSI Bo ASI zav 2801 osav 624 128 su tow Tedy s Hsu DIANO9 194 i Ke 7 f E E T XO t Ast ES lt WOHd3 uogeanbyuoo YOd4 l 89dlttt 9da ache ND sou M 3NOQ_3NO9 osvou 30 629 l aston oo ama SNIVISU 4 EEE net AS O ODA viva T viva em SAL SAL um o dd odo sou ved BEA BAILII LIAN ANH AZBERSSRRSHBOBARARAR Q C annn a EB EEL EE EEE EEL r r ran AS Ast Z rr1O191094d3 251001 EZH vi losia lt e vL loozlev lt vb 13934 ids vb 03M yl LIM Gano vb SO yl Ram E vi uwdd yL esa v i 08 L 19 WOds t T T T T T T T Epson Research and Development Vancouver Design Center S1D13504 X19A G 014 01 Figure 7 5 SSU13504B00C Rev 2 0 Evaluation Board Schematics 5 of 5 2002 12 02 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date Page 30 Epson Research and Development 8 Board Layout 1D13504 X19A G 014 01 6 819 al 5 a s 119 L Llozo 3i Eos gt Zia S142 i tla Ad 5 sul bd m r E C28 ll gz 203 ess BS IE 520 gar N xe ES 3 L 69 a y oe 05 BoE Figure 8 1 SSU13504B00C Rev 2 0 Evaluation Board Layout Vancouver Design Center S5U13504B00C Rev 2 0 PCI Evaluation Board User
171. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 11h Screen 1 Display Start Address 1 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 12h Screen 1 Display Start Address 2 Hie ala n wa Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16 These three registers form the address of the word in the display buffer where screen 1 will start displaying from Changing these registers by one will cause a change of 0 to 16 pixels depending on the current color depth Refer to the following table to see the minimum number of pixels affected by a change of one to these registers Table 4 1 Number of Pixels Panned Using Start Address Color Depth bpp Pixels per Word Number of Pixels Panned 1 16 16 2 8 8 4 4 4 8 2 2 15 1 1 16 1 1 REG 18h Pixel Panning Register Screen 2 Screen 2 Screen 2 Screen 2 Screen 1 Screen 1 Screen 1 Screen 1 Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 The pixel panning register offers finer control over pixel pans than is available with the Start Address Registers Using this register it is possible to pan the displayed image one pixel at a time Depending on the
172. C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 o 4 C10 C27 C28 68uF 10V 10 Kemet T491 D686K01 DAS or C44 equivalent 3 1 C17 C6032 10uF 25V T Kemet T494C106M025AS 4 2 C24 C18 C6032 22uF 10V T Kemet T494C226K016AS 5 2 042 043 33uF 20V 10 A A equivalent 6 2 C20 C26 CAP_PANA_D 10uF 63V T Panasonic ECG EEV FK1J100P 7 2 D1 D2 SOD123 1N5819HW Diodes Inc 1N5819HW 7 8 H1 H2 HEADER 17x2 HEADER 17X2 Molex 10 88 1341 or equivalent JP1 JP2 al 9 4 JPS JP6 HEADER 3 HEADER 3x1 0 1 pitch 10 3 JP3 JP4 JP7 HEADER 2 HEADER 2x1 0 1 pitch 11 1 J1 HEADER 20x2 CON40A Amp103308 8 or equivalent 12 2 L1 L2 INDPM105S 47uH JW Miller Inc PM105S 470M 13 1 Q1 SOT23 MMBT3906 Diodes Inc MMBT3906 7 14 1 Q2 SOT223 NDT3055L Fairchild Semiconductor NDT3055L 15 2 Q5 Q3 SOT23 MMBT3904 Diodes Inc MMBT3904 7 16 1 Q4 SOT223 FZT792A Zetex Inc FZT792ATA 17 1 RV1 200 POT Spectrol 635201 or equivalent 18 1 RV2 500k POT Spectrol 635504 or equivalent 19 4 R1 R2 R3 R23 R0805 100K 5 generic R4 R5 R6 R7 R8 R9 R10 9 i 20 12 R11 R26 R27 R0805 15K 5 generic R28 R29 21 1 R12 R0805 301 1 generic 22 1 R13 R0805 12 4K 1 generic 23 2 R15 R14 R0805 82K generic 24 1 R16 R0805 1K generic 25 1 R17 R0805 0 22 1 4W generic 26 1 R18 R0805 470 generic S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 1D13504 X19A G 014 01 Page 24 Epson
173. CD 20 4 4 Current Consumption Measurement 21 5 ROTerenCes a a areas 22 5A Documents s a A SB ee ct a BR eee 6S A oe eee E de 4 22 5 2 Document SOULCES as es So a ke BL Tew ew oa ee OE ca a a 2 6 Parts LISE Zia wd dates A aa aa a ds ah es dedo Sy 23 7 SENEMALUGCS sara A pee A AR a A ARA 25 9 Board Layouts a Bien A AO DAA AA A A A a A 30 9 Technical Support lata aoe ae ds a A ee ei ae 31 9 1 EPSON LCD CRT Controllers S1D13504 2 2 ee 31 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual S1D13504 Issue Date 2002 12 02 X19A G 014 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Vancouver Design Center List of Tables Table 3 1 Configuration DIP Switch Settings Table 3 2 Jumper Settings o e e o Table 4 1 CPU Interface Pin Mapping o Table 4 2 CPU BUS Connector H1 Pinout Table 4 3 CPU BUS Connector H2 Pinout Table 4 4 LCD Signal Connector J1 o o oo oo Table 4 5 Controlling the MAX754 o ooo Table 4 6 Controlling the MAX749 oo o o Table 6 1 Parts Listan i seid ge ae Bo wy HE eee BA List of Figures Figure 3 1 Configuration DIP Switch S1 Loc
174. CONFIG SYS on the hard drive to contain only the following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy NK BIN and HIMEM SYS to c e Boot the system 1D13504 Windows CE 2 x Display Drivers X19A E 001 05 Issue Date 01 05 25 Epson Research and Development Page 11 Vancouver Design Center Configuration Compile Switches WINCEVER There are several issues to consider when configuring the display driver The issues cover debugging support register initialization values and memory allocation Each of these issues is discussed in the following sections There are several switches specific to the S1D13504 display driver which affect the display driver The switches are added or removed from the compile options in the file SOURCES This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default 2 11 The display driver may test against this option to support different WinCE version specific features EpsonMessages This debugging option enables the display of EPSON specific debug messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the display driver as they will significantly impact the performance of the display driver Win
175. D C Characteristics catala a Eh ee ee ee we es 34 A C Characteristics comida al A eee ae ee ete e Ya tee ee ded Qe A 36 TA CPU Interface Timing ci a oe Be A a a d a ee a O TA SH 3 Interface Timings sec ee ee ek eevee ee BE Pa eR bbe we ede 36 Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 4 Epson Research and Development Vancouver Design Center 7 1 2 MC68K Bus 1 Interface Timing e g MC68000 naaa ee 38 7 1 3 MC68K Bus 2 Interface Timing e g MC68030 2 2 o o 40 7 1 4 Generic MPU Interface Synchronous Timing 2 00 42 7 1 5 Generic MPU Interface Asynchronous Timing _ e o 44 7 2 Clock Input Requirements 46 7 3 Memory Interface Timing 46 73 1 EDO DRAM Read Timing 46 732 lt EDO DRAM Write Timing e 534445 rada eee eee eS Be eed be ee oo 48 7 3 3 EDO DRAM Read Write Timing 00 0 0 2 0 0 000 50 734 EDO DRAM CAS Before RAS Refresh Timing a 52 7 3 5 EDO DRAM Self Refresh Timing 00 0 0 02 02 0000 53 7 3 6 FPM DRAM Read Timing 0 0 0 00 000000000 54 73 7 FPM DRAM Write Timing 220 sob be ee a ee a a ERE 56 7 3 8 FPM DRAM Read Write Timing 58 7 3 9 FPM DRAM CAS Before RAS Refresh Timing 0 60 7 3 10 FPM DRAM Self Refresh Timing e 61 7 4 Display Interface 62 VAL Power On Reset TMINE es oe es ela Se Pe eR ee we Pe
176. Date 01 04 17 EPSON S1D13504 Color Graphics LCD CRT Controller S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 06 Copyright O 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Vancouver Design Center oa DON 7 Parts List 8 Schematic Diagrams Introduction 1 1 Installation and Configuration LCD RAMDAC Interface Pin Mapping CPU BUS Interface Connector Pinouts Host Bus Interface Pin Mapping Technical Description 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 6 10 6 11 6 12 6 13 6 14 6 15 6 16 Table of Contents Features ISA Bus Support Non ISA Bus Suppo
177. EPSON 1D13504 Color Graphics LCD CRT Controller S1D13504 TECHNICAL MANUAL Document Number X19A Q 002 14 Copyright O 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 TECHNICAL MANUAL X19A Q 002 14 Issue Date 01 04 18 Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems Evaluation Demonstration Board e Assembled and fully tested graphics evaluation board with installation guide and schematics e To borrow an evaluation board please contact your local Seiko Epson Corp sales representative Chip Documentat
178. G 04h 0x4F REG 05h 0x1F REG 06h 0x00 REG 07h 0x00 REG 08h OxEF REG 09h 0x00 REG OAh 0x01 REG OBh 0x00 REG OCh 0x00 REG OEh 0xFF REG OFh 0x03 REG 10h 0x00 REG 11h 0x00 REG 12h 0x00 REG 13h 0x00 REG 14h 0x00 REG 15h 0x00 REG 16h 0xA0 REG 17h 0x00 REG 18h 0x00 REG 19h 0x01 REG 1Ah 0x00 REG 1Eh 0x00 REG 1Fh 0x00 Enable Host Interface Disable the Display FIFO Set Memory Type Set Performance Register Set Dual Single Panel MOD Rate Horizontal Display Width Horizontal Non Display Period HSYNC Start Position HSYNC Pulse Width Vertical Display Height Vertical Non Display Period VSYNC Start Position VSYNC Pulse Width Screen 1 Line Compare Screen 1 Display Start Address Screen 2 Display Start Address Memory Address Offset Pixel Panning Clock Configuration Power Save Configuration General I O Configuration Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 11 Vancouver Design Center REG 20h 0x00 REG 21h 0x00 REG 24h 0x00 Look Up Table Address for index 0 index lt 16 index REG 26h RED index REG 26h GREEN index REG 26h BLUE index program REG 27h 0x00 Look Up Table Bank Select REG 23h 0x10 Enable the Display FIFO REG ODHh 0x09 Enable Display Table 2 1 Initializing the SID13504 Registers Continued General I O Contr
179. G 05h bits 4 0 1 8 16 Ts Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 66 Epson Research and Development Vancouver Design Center 7 4 4 Single Monochrome 8 Bit Panel Timing VDP VNDP i FPFRAME o j FPLINE _ fl fl Ll I I MOD ie UD 3 0 LD 3 0 LINE X LINE2 X LINES X LINE4 X XLINE479XLINE480 A LINE1 X LINE2 X FPLINE MOD ut HDP HNDP lt 4 rle gt RRSHIET e A ele al UD3 ee XK 14 X O X A X X ues UD2 n 12 X 1 10 X X X X 1 634 e UD1 de A 13 TD X SA X X X Kes oh UDO as 14 2X X S XX BA LD3 es 15 Y 1 13 Y X YX DM 1637 kK LD2 Eo 16 X 1 14 X X Y 1 638 LD1 E 17 X 115 X X A Y Y 1 639 LDO zi 1 8 X 1 16 X X Y Y 1 640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 21 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAN bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06
180. Generic Bus RAMDAC Read Write Timing Table 7 30 Generic Bus RAMDAC Read Write Timing Symbol Parameter Min Typ Max Units TBcLk Bus clock period 30 ns ti AB 20 0 CS M R delay to DACRS 1 0 10 ns t2 DACRSJ1 0 hold from AB 20 0 CS M R negated 10 ns t3 Valid RD command to DACRS 1 0 delay 8 33 ns t4 DACRD hold from valid RD command negated 3 14 ns t5 Valid WR command to DACWR delay 2 TBcLK ns t6 DACWRi pulse width low 2 45 TBCLK 2 55 Tack ns 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 89 Vancouver Design Center 8 Registers 8 1 Register Mapping The 1D13504 registers are all memory mapped The system must provide the external address decoding through the CS and M R input pins When CS 0 and M R 0 the registers are mapped by address bits AB 5 0 e g REG OOh is mapped to AB 5 0 000000 REG O1h is mapped to AB 5 0 000001 See the table below Table 8 1 S1D13504 Addressing CS M R Access Register access 0 0 REG 00h is addressed when AB 5 0 0 e REG 01h is addressed when AB 5 0 1 REG n is addressed when AB 5 0 n 0 1 Memory access the 2M byte display buffer is addressed by AB 20 0 1 X S1D13504 not selected 8 2 Register Descriptions Note Unless specified otherwise all register bits are reset to O during power up Reserved bits should be written 0 when programming unless otherwi
181. Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to IO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 011 07 Page 12 Epson Research and Development Vancouver Design Center 3 2 Generic MPU Host Bus Interface Signals 1D13504 X19A G 011 07 The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13504 It is separate from the pixel clock CLKD and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space M R is driven high for memory accesses or low for S1D13504 register accesses On CPUs which implement memory mapped IO this pin is typically tied to an address line on CPUs with separate IO spaces this pin is typically driven by control logic from the CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 RD and RD1 are read enable
182. HALON QONA AVTHSIQNON TVOUHAA INES Jamo 94 PUL SNq eJep Add 34 jo a1 q MOJ Y o pajpauuoo aq PINOYS OYANYH y ueipug om7 Buisn uaym MY yalsioay JTavsiq SNOINVT139SIW 4811938 13834 UO Jamod Je POSE ALS 9u Aytuap 0 pasn axe syqasey Z 818 618 eju eju eu eju eju eju 0 ay UM eq snw s iq pamasa puedsns Ove Lia aiqesiq eu eju eju eu 1yBlaH ejds q yeoman 0 UaHM aq Pinoys Sq eJu SIEMYoS josjes ysayaey puadsng 9M0d 097 MY a1SIDSY LH9IIH AVIASIG 1VILLUZA 4601534 SO10N Mu 831SI93Y NOILLVENDIANOJ JAYS Y3MOd yv 11934 oud Lua cua e 18 vid sia 918 Auld i I l l f I l l I oud Lua oud ena vil sua 918 Zug Lua aping Eu eu eu eju eju 1 938 1y6leH Aejdsig eoma eed OVOWVY 10d ATOM My 0 8315 93 LHDISH AVIASIQ 1V91183A yg0l9 34 My 831SI93Y VIVO 3L131Vd OVONVE yaz 934 0 uazlo3u Y31SI93H NOILVENDIANOY 49079 4611938 oud 118 zua eng Aue og Auejod eju eju i y 0118 Lua zua eng vid gid 918 4a 0118 Lua zua eng 0118 Lua 218 eng 1 938 8 UPIM SNd INITd 3 0 LHH NMd3 LHH ssaippy OVGNWHY Bujuued ex1g U39190 Bujuueg ex1g Z uses My Y3LSI93Y HLGIM 3S1Nd 3NI1d3 9 L9H u0J0 38 Mu ya4s1934 SSauday 300 3LIYM OVGWVH luazlo34 0 yoz 934 Mu 4315 0938 ONINNVd 13XId 811934 oud Lua eid e ug vid 018 Lua eve erg vid sua 918 dud 88 618 L 8 UONISOd YR eu eN bes i I I I i i i f l il eju eju eju eju eju eju 934 8 ISO HES ANI1d4 O LYH ssaippy OVGNVY 19syO ssaippy ouayy My Y31SI93Y NOILISOd 18VIS 3NI1d3 9 8H u901938 Mu Ya
183. Hz 64 ms bit 2 WE Control When this bit 1 2 WE DRAM is selected When this bit 0 2 CAS DRAM is selected bit 0 Memory Type When this bit 1 FPM DRAM is selected When this bit 0 EDO DRAM is selected This bit should be changed only when there are no read write DRAM cycles This condition occurs when both the Display FIFO is disabled REG 23h bit 7 1 and the Half Frame Buffer is disabled REG 1Bh bit 0 1 For programming information see 1 D13504 Programming Notes and Examples document number X19A G 002 xx 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center 8 2 3 Panel Monitor Configuration Registers Page 91 Panel Type Register REG 02h RW mia ja Panel Data Panel Data Panel Data Color Mono Dual Single a Width Bit 1 Width Bit 0 Format Select Panel Select Panel Select Select bits 5 4 Panel Data Width Bits 1 0 These bits select passive LCD TFT panel data width size Table 8 3 Panel Data Width Selection Panel Data Width Bits 1 07 Passive LCD Panel Data TET Panel Data Width Size Width Size 00 4 bit 9 bit 01 8 bit 12 bit 10 16 bit 16 bit 11 Reserved Reserved bit 3 Panel Data Format Select When this bit 1 8 bit single color passive LCD panel data format 2 is selected This bit must be set to 0 for all other LCD panel formats bit 2 Color Mono Panel Sele
184. I93H SS3YAUY LYVLS AVIASIO Z N33u0s ueLlo38 zi F T za i Sr T aril Siy Howay eju jonuog HIM eju 018 Lua eid eu i na oysa fe _ejds s fa e le oalateidsig js sso x E Aejdsi i ee i SA He ee bibs 2 Su eens i ploysaxy 1 O4l4 Aejdsiq 4 Ppy Hels ejdsig L S My o k Y31SI93H NOLLVENDIANOD AYOWIWN y4 LOJDIY My 831SI93H INIWIINVHN3 39NVWHO483d yezlO38 Mu Z U3LSIDIH SSIUAUY LYVLS AVIASIO N33Y9S UzLlO38 na gu 018 tua kequsyo 018 Lug keea aum 88 618 0118 EEE ZL 18 erua vig stig 0 7 k 7 9 o o o Buy obieyood eva OF SVH o Buw OW peay 003 sselppy els Aejdsiq U39195 apo9 uosney Apoo papeld MY 0 1 0 H31SID3Y ININZINVHN3 3ONVWHOWJ83d uzzl038 MY U31SIOIY SSIYAQDY LEVLS AVTdsiq N3349S y L1 038 ou z U3LSIO3Y 3009 NoIsIAaY 400 934 0 100 O V6TX Arewuing 1935 39Y VYOOAPOSETAIS TO TO TO 0 100 O V6TX panasoy LL ATOM L OL TOW SL LO WON Z 00 UIPIM 9BIeyoald SVH 0 1 sug Buw abreyosld SVH pajas Bunu abs panesey a ATOM Ol WON LO WONS 00 UPIM 31949 wopuey wnw o 1 sua Sur Ou ysaley ON XL ysaJoy JJ9S LO ysa y YEO 00 ad L yseyoy WVHA 0 1 sug 199 95 yse4yoy puedsng v LL e OL Z LO L 00 oney Aouanbely YI9d AI9WN o 1 sug 199 98 apIAIG 419d uonoajas panasey LLL OLL 94 LOL SL ool 8 LLO v OLO zZ 400 L 000 9XId SUA JO 19QUINN 0 2 sua 199198 9XId S1H 40 49QUINN 7 9384 e
185. IFO ji 4 Data I F Look Up F gt Table DAC Control CRTC Bus Clock Memory Clock Pixel Clock Figure 4 1 System Block Diagram Showing Datapaths S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 17 Vancouver Design Center 4 2 Functional Block Descriptions 4 2 1 4 2 2 4 2 3 4 2 4 4 2 5 4 2 6 Host Interface The Host Interface block provides the means for the CPU MPU to communicate with the display buffer and internal registers via one of the supported bus interfaces Memory Controller The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16 bit memory devices FPM DRAM or EDO DRAM Display FIFO The Display FIFO block fetches display data from the Memory Controller for display refresh Look Up Table The Look Up Table block contains three 16x4 Look Up Tables one for each primary color In monochrome mode only one of these Look Up Tables is selected and used LCD Interface The LCD Interface block performs frame rate modulation for passive LCD panels It also generates the correct data format and timing control signals for various LCD and TFT panels Power Save The Power Save block contains the power save mode circuitry Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 18 5 Pin Out
186. IFT O 73 83 CN3 Output O Shift Clock Pulse LCD power control output The active polarity of this output is selected by the state of MD10 at the rising edge of RESET see Section 5 5 Summary of Configuration LCDPWR O 71 81 CO1 Output Options on page 30 This output is controlled by the power save mode circuitry see Section 13 Power Save Modes on page 127 for details This pin has multiple functions which are automatically selected depending on panel type used For TFT panels this is the display enable output DRDY For passive LCDs with Format 1 interfaces this is the DRDY O 72 82 CNS OutputO ong Shift Clock FPSHIFT2 For all other LCD panels this is the LCD backplane bias signal MOD See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 and REG 02h for details 1 Output may be 1 or 0 5 4 4 Clock Input Table 5 4 Clock Input Pin Description Pin Reset 3 eset roe Pin Name Type FOOA FOOA Driver 0 Value Description FO1A Input clock for the internal pixel clock PCLK and memory CLKI 105 119 C Hi Z clock MCLK PCLK and MCLK are derived from CLKI see REG 19h for details 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 27 Vancouver Design Center 5 4 5 CRT and External RAMDAC Interface Table 5 5 CRT and RAMDAC Interface Pin Descriptions Pin Pin Na
187. ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Page 13 Vancouver Design Center 6 Technical Description 6 1 ISA Bus Support The S5U13504BO00C directly supports the 16 bit ISA bus environment All the configuration options MD15 0 are either hard wired or selectable through the five position DIP Switch S1 Refer to Table 2 1 Configuration DIP Switch Settings on page 8 for details Note 1 The 8 bit ISA bus is not supported by the SSU13504BO00C board design 2 The S1D13504 is a memory mapped device with 2M bytes of linear addressed display buffer memory as well as a separate 37 byte register space On the S5U13504B00C the S1D13504 registers have been mapped to a start address of C00000h and the 2M byte display buffer has been mapped to a start address of E00000h 3 When using this board in a PC environment system memory must be limited to 12M bytes as more than this will conflict with the S1D13504 display buffer register addresses Note Due to backwards compatibility with the S3U13504B00B Evaluation Board which supports both an 8 and a 16 bit CPU interface third party software must perform a write to address D00000h to enable a 16 bit ISA environment This must be done prior to initializing the S1D13504 Failure to do so will result in the S1D13504 being configured as a 16 bit device de fault power up with the ISA Bus interface supported through the PAL U4
188. If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13504 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfree86 org Linux Console Driver 1D13504 Issue Date 01 11 19 X19A E 004 01 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Linux Console Driver X19A E 004 01 Issue Date 01 11 19 EPSON 1D13504 Color Graphics LCD CRT Controller Windows CE 3 x Display Drivers Document Number X19A E 006 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Micr
189. In this version of 13504CFG the Help files are unavailable F Power Assignment for Device POWER TYPE O POWER TYPE 1 POWER TYPE 2 CURRENT CONFIGURATION gt Edit Cancel Help YOM Figure 17 13504CFG Power Setup 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 24 1D13504 Epson Research and Development Vancouver Design Center Edit Power Setup When a selection is highlighted in the Power Setup window and Edit is clicked the Edit Power Setup window is displayed The Edit Power Setup window lists parameters which can be edited as shown below in Figure 18 13504CFG Edit Power Setup In this example window Suspend Refresh CBR Refresh is highlighted d CBR REFRESH SOFT SUSPEND DISABLE for Device Suspend Refresh CBR REFRESH Software Suspend DISABLE Edit Cancel Help OEE N Figure 18 13504CFG Edit Power Setup Power Parameter Edit When a selection is highlighted for editing in the Edit Power Setup window and Edit is clicked the Power Parameter Edit window displays for parameter editing See figure 19 13504CFG Power Parameter Edit below In this example window Suspend Refresh CBR Refresh can be edited d Suspend Refresh CBR REFRESH Cancel SELF REFRESH 4 Help Figure 19 13504CFG Power Parameter Edit 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30
190. LSIO3Y SS3YAUY 300W OV3H DVONVE luazlo34 HO yvzlo34 Mu 431SID3Y 135340 SS3YAIY AYOMAN yL 11038 oud Lua eg erg ta eju eju eju oud Lua zwa e 18 vid Sua 918 dug oud Lua zwa e 18 vid Sua 98 dud 1 538 8 ponad Aejdsiq uoy JejuoZ LOH ed OVGWVHY 19SyO sseippy Aiwa My YALSIDSY 0Ol83d AVIdSIG NON 1VLNOZIHOH ySOJO3H My 43 1SI938 JSV 0V3Y 13XId OVONWVE luszlo3u Ho uszlo34 MY 0 431S193H 13S440 ss34aay AYOWaWN y911938 oud Lua eid eg vid Sua gud eu if I l l r I I l l I oud Lua 018 Lua oud Lua eju eu 91 Ya 2118 81 ua 61 ua eu eju eju eu L D38 8 ulpIM Aejdsig euozuoH pajas yueg Uso 109195 yueg anid 109 95 ueg Poy ssalppy els eidsig z U39195 My 431SI93Y HLGIM AV1dSIG 1VLNOZIHOH ypvoJ9 38 MY 31SID3Y 193135 ANVg 3179Y 1 dn 4007 y 21938 Mu Z Y3LSIOIH SSIYAUY LYVLS AVIASIO Z N3389S YSL Day oud Lua cua e 18 vid sia eju eju oud bud oud eng eu eu eju eu 818 6 118 0118 Ll 18 cl 18 l ng pl ua si ua y GOW ejeg aqe da 1007 sselppy uels ejdsig z uaalos My Ya1sI93Y 3 vy GOW ysolo3 4 MY Y31SI93Y VIVO aav 1 dn 1007 y9z D4y Mu U31SIOIH SSIYAOY LHVLS AVIASIQ Z Na3uos yv 1 o34 yoajas Sue y wales eue q 1oajas jaueg auc 018 118 eju eju if l l l r I if l l if i I I l oud Lua E ua e 18 oud Lua eju e oud bud zua e 18 Aa vid sia 918 aud NSSEd L4AL a us 1eng Ouo 40 0D eJeg jaueg c UIPIM eed eueg sseuppy alge L dn 4007 xepul goy ssaippy ues ejdsiq z uaaros ma a ToT ae See My waisioay SSauday 3718Y 1 dn 1007 upzlo38 Mu 0 834S
191. M E BUBBLE 256 Colors 2 33 MHz input clock 2 MB of 60 ns FPM memory k k EE This is sample code only This means 1 Generic C is used I assume that pointers can access the FR relevant memory addresses this is not always the case KK i e using the 13504B00B card on an Intel 16 bit platform will require kR changes to use a DOS extender to access memory and registers 2 Register setup is done with discreet writes rather than being apr table driven This allows for clearer commenting A real program KR would probably store the register settings in an array and loop Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 56 xk Ap unsigned char LUT8 8 3 Epson Research and Development Vancouver Design Center through the array writing each element to a control register 3 The pointer assignment for the register offset does not work on Intel 16 bit platforms Created 1998 Copyright c All rights reserved Epson Research amp Development Vancouver Design Centre 1998 Epson Research and Development InG Header SRevision Slog 0x00 0x00 0 x00 0x02 0x02 0x05 0x04 0x04 0x0A 0x06 0x06 0x0F 0x09 0x09 0x00 0x0B 0x0B 0x00 0x0D 0x0D 0x00 OxOF 0x0F 0x00 y REGISTER_OFES define REGISTER_OFFSET void main void u
192. MC68000 0 1 0 MC68K Bus 2 e g MC68030 1 x x Reserved Si configuration for PC Card interface Interfacing to the PC Card Bus 1D13504 Issue Date 01 02 02 X19A G 009 05 Page 14 Epson Research and Development Vancouver Design Center 4 3 PAL Equations The PAL equations used for the implementation presented in this document are as follows Note that PALASM syntax uses positive logic Active low pins are inverted in the pin declaration section CHIP PCCAPP PAL16L8 PIN 1 oe COMBINATORIAL bus read enable PIN 2 we COMBINATORIAL bus write enable PIN 3 cel COMBINATORIAL bus low byte enable PIN 4 ce2 COMBINATORIAL bus high byte enable PIN 5 pcreg COMBINATORIAL bus CIS cycle enable PIN 6 breset COMBINATORIAL bus reset active high PIN 12 we0 COMBINATORIAL S1D13504 low byte write PIN 13 wel COMBINATORIAL 1D13504 high byte write PIN 14 cs COMBINATORIAL S1D13504 chip select PIN 15 rdo0 COMBINATORIAL S1D13504 low byte read PIN 16 rdl COMBINATORIAL S1D13504 high byte read PIN 17 reset COMBINATORIAL S1D13504 reset PIN 10 gnd supply PIN 20 vec supply EQUATIONS rd0 oe cel pcreg pcreg means disable in attribute mode rdl oe ce2 pcreg pcreg means disable in attribute mode we0 we cel pcreg pcreg means disable in attribute mode wel we ce2 pcreg pcreg means disable in attribute mode cs rd0 rdl we0
193. MC68K bus 2 interface e g MC68030 0 1 1 4 Generic bus interface e g ISA bus 1 x x 5 Reserved Closed 1 or high open 0 or low required settings for ISA bus support Table 2 3 Jumper Settings Description 1 2 2 3 JP1 BS signal pin 6 selection Pulled up to IO Vpp for ISA bus Ne oe ee JP2 3 3V 5 0V IO Vpp selection 5 0V IO Vpp 3 3V IO Vpp IPS ORDY signal selection RRR J default settings for ISA bus and LCD panel support 1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Vancouver Design Center 3 LCD RAMDAC Interface Pin Mapping Table 3 1 LCD Signal Connector J6 Page 9 Color TFT Color Passive Mono Passive S1 D13504 Connector ANDA Pin Names Pin No 9 bit 12 bit 18 bit 4 bit 8 bit 16 bit 4 bit 8 bit CRT FPDATO 1 R2 R3 R5 LDO LDO LDO FPDAT1 3 R1 R2 R4 LD1 LD1 LD1 FPDAT2 5 RO R1 R3 LD2 LD2 LD2 FPDAT3 7 G2 G3 G5 LD3 LD3 LD3 FPDAT4 9 G1 G2 G4 UDO UDO UDO UDO UDO FPDAT5 11 GO G1 G3 UD1 UD1 UD1 UD1 UD1 FPDAT6 13 B2 B3 B5 UD2 UD2 UD2 UD2 UD2 FPDAT7 15 B1 B2 B4 UD3 UD3 UD3 UD3 UD3 FPDAT8 17 BO B1 B3 LD4 FPDAT9 19 RO R2 LD5 DACP7 FPDAT10 21 R1 LD6 DACP6 FPDAT11 23 GO G2 LD7 DACP5 FPDAT12 25 G1 UD4 DACP4 FPDAT13 27
194. Manual Issue Date 2002 12 02 Epson Research and Development Page 31 Vancouver Design Center 9 Technical Support 9 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 S1D13504 X19A G 014 01 Page 32 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 E
195. OO Pin IO Status IO Status IO Status IO Status IO Status IO Status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O GPIO7 Pin IO Status When GPIO7 is configured as an output a 1 in this bit drives GPIO7 to high and a 0 in this bit drives GPIO7 to low When GPIO7 is configured as an input a read from this bit returns the status of GPIO7 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO7 other wise the DACWR pin is controlled automatically and this bit will have no effect on hardware GPIO6 Pin IO Status When GPIO6 is configured as an output a 1 in this bit drives GPIO6 to high and a 0 in this bit drives GPIO6 to low When GPIO6 is configured as an input a read from this bit returns the status of GPIO6 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO6 other wise the DACPO pin is controlled automatically and this bit will have no effect on hardware GPIOS Pin IO Status When GPIOS is configured as an output a 1 in this bit drives GPIOS to high and a 0 in this bit drives GPIOS to low When GPIOS is configured as an input a read from this bit returns the status of GPIOS Note the MD8 pin must be high at the rising edge of RESET to enable GPIOS other wise the BLANK pin is controlled automatically and this bit will have no effect on hardware GPIO4 Pin IO Status When GPIO4 is configured as an output a
196. POSELNSS ONI LNINd073A30 ONY HOBV3S3Y NOSd3 Vancouver Design Center Epson Research and Development SSI NOO LW anor vio F z sno ano 299 0 0A nt o Mare nee o nee F 10 in euaqvaH a01 O _ z ano Ast zoua ova 908a syva waisvi g1s90V LSW nee oE zar nai w N09 LW awa lt nosna lt D0 ely Hs3u438 lt 13534 lt OL a OA ano oso Ast awa oL ANO EOY YONI soul 904 081 mo Loya XOVG oud EXA Yol mov was ano neit SMO Aah zoya AS SoY Ast 13538 ano HSau4au MWS EZ AOL AOL ou sia Ob 0A vie 9A 20 WS gt ams y E gt lezan TIN F gt ros ar aava OL ziy 9A _ lt gt bros Page 22 Issue Date 01 02 02 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Figure 3 S1D13504B00C Schematic Diagram 3 of 6 1D13504 X19A G 004 06 Page 23 z poo r TES Ze e oes e oeg a ER T SSA ano
197. PR31700 11 4 1 Hardware Description 2 ee ee 11 4 2 Memory Mapping and Aliasing 12 43 1D13504 Configuration o a a a ee 13 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description Using One IT8368E aoaaa a a aaa aaa 14 5 2 Hardware Description Using Two IT8368E s 2 2 2 17 5 3 IT8368E Configuration 18 5 4 Memory Mapping and Aliasing 19 5 5 S1D13504 Configuration 2 o 20 SOMWAT sia Ae ae A aaa E eg EA A A ARAN 21 Referentes vta tra Wa are wee la e A a Soe Re 22 TI Documents e mts da e a Be a Ae Be ae a Aa e a 2 7 2 Document Sources 2 1 a ee ee ee ee 2 amp Technical Support lt ssia 24s os Se ARA 23 8 1 EPSON LCD CRT Controllers S1D13504 2 2 a ee 23 8 2 Philips MIPS PR31500 PR31700 Processor 2 1 ee 23 8 3 LE TISIOSE a 5 e Bap al BES es eae a a Da Oe 2S Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13504 Issue Date 01 10 26 X19A G 005 09 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 Epson Research and Development Vancouver Design Center Table 3 1 Table 4 1 Table 4 2 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Figure 4 1 Figure 5 1 Figure 5 2 Interfacing to
198. PSON 1D13504 Color Graphics LCD CRT Controller Interfacing to the Philips MIPS PR31500 PR31700 Processor Document Number X19A G 005 09 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introduction 5 6 a are ay aa as Gia ARABIA a a Bebo 7 Interfacing to the PR31500 PR31700 2 2 2 2 2 eee ee ee 8 S1D13504 Host Bus Interface 2 65 oca ec ee ee wa ee 9 3 1 Generic MPU Host Bus Interface Pin Mapping 2 2 2 2 2 2 2 2 9 3 2 Generic MPU Host Bus Interface Signals 2 2 2 2 10 4 Direct Connection to the Philips PR31500
199. Pixel Mode Epson Research and Development Vancouver Design Center Green Look Up Table Bank 0 0 2 00 3 Bank 1 E 01 Selected Bank 6 7 Bank i og ze 4 bit display data output Bank 2 Select i Logic 8 Logic E A 10 A BL I Bank 3 D E 11 F Bank Select bits 1 0 REG 27h bits 1 0 2 bit pixel data Note the above depiction is intended to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations Figure 12 2 2 Bit Per Pixel 4 Level Gray Shade Mode Look Up Table Architecture 4 Bit Per Pixel Mode Green Look Up Table gt 0110 Entry 4 bit display data output Select gt 1001 Logic TMMUOWEPOONOUARWNAO o o o 4 bit pixel data S1D13504 X19A A 002 19 Figure 12 3 4 Bit Per Pixel 16 Level Gray Shade Mode Look Up Table Architecture Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center 12 2 Color Display Modes 1 Bit Per Pixel Color Mode Page 123 1 bit pixel data Red Look Up Table 0 gt 1 gt 4 bit Red data output Green Look Up Table 0 P
200. Rat RA HDP HNDP VDP VNDP Xx 8 250 000 ER 320 HNDP 240 VNDP HNDP and VNDP must be calculated such that the desired frame rate is achieved 87 pRegs 0x05 Ox0OF 0000 1111 Programming Notes and Examples Issue Date 01 02 01 Page 57 1D13504 X19A G 002 07 Page 58 Epson Research and Development Vancouver Design Center Register 6 HRTC FPLINE Start Position applicable to CRT TFT only y pRegs 0x06 0x00 0000 0000 Register 7 HRTC FPLINE Pulse Width applicable to CRTI TFT only EL pRegs 0x07 0x00 0000 0000 Registers 8 9 Vertical Display Height VDP 240 lines ax 240 1 239t OxEF xy pRegs 0x08 OXEF 1110 1111 pRegs 0x09 0x00 0000 0000 Jx Register A Vertical Non Display Period VNDP ai This register must be programed with register 5 HNDP EK to arrive at the frame rate closest to the desired XX frame rate Ey pRegs 0x0A 0x01 0000 0001 Register B VRTC FPFRAME Start Position applicable to CRT TET only ay pRegs 0x0B 0x00 0000 0000 Register C VRTC FPFRAME Pulse Width applicable to CRT TFT only ty pRegs 0x0C 0x00 0000 0000 Registers E F Screen 1 Line Compar unless setting up for ER split screen operation use 0x3FF E pRegs 0x0E
201. Reg 2Fh Note When accessing the External RAMDAC Control registers with either of the Little Endian or Big Endian architectures described above accessing the adjacent unused registers is prohibited Table 6 2 shows some example register data for setting up CRT only mode for certain combinations of resolutions frame rates and pixel clocks All the examples in this chapter are assumed to be for a Little Endian system 8 bpp color depth and 2M bytes of 60ns EDO DRAM Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 34 Epson Research and Development Vancouver Design Center Table 6 2 Related Register Data for CRT Only Register 640X480 60Hz 640X480 75Hz 800X600 56Hz 800X600 60Hz Notes PCLK 25 175MHz PCLK 31 500MHz PCLK 36 0 MHz PCLK 40 0 MHz REG 04h 0100 1111 0100 1111 0110 0011 0110 0011 set horizontal display width REG 05h 0001 0011 0001 1000 0001 1011 0001 1111 set horizontal non display period REG 06h 0000 0001 0000 0001 0000 0010 0000 0100 set HSYNC start position REG 07h 0000 1011 0000 0111 1000 1000 1000 1111 set HSYNC polarity and pulse width REG 08h LOT TUTT 1101 1111 0101 0111 0101 0111 set vertical display height bits 7 0 REG O09h 0000 0001 0000 0001 0000 0010 0000 0010 set vertical display height bits 9 8 REG OAh 0010 1100 0001 0011 0001 1000
202. S1D13504 3 Connected to DB2 of the S1D13504 4 Connected to DB3 of the S1D13504 5 Ground 6 Ground 7 Connected to DB4 of the S1D13504 8 Connected to DB5 of the S1D13504 9 Connected to DB6 of the S1D13504 10 Connected to DB7 of the S1D13504 11 Ground 12 Ground 13 Connected to DB8 of the S1D13504 14 Connected to DB9 of the S1D13504 15 Connected to DB10 of the S1D13504 16 Connected to DB11 of the S1D13504 17 Ground 18 Ground 19 Connected to DB12 of the S1D13504 20 Connected to DB13 of the S1D13504 21 Connected to DB14 of the S1D13504 22 Connected to DB15 of the S1D13504 23 Connected to RESET of the S1D13504 24 Ground 25 Ground 26 Ground 27 12 volt supply required in non PCl applications 28 12 volt supply required in non PCl applications 29 Connected to WEO of the S1D13504 30 Connected to WAIT of the S1D13504 31 Connected to CS of the S1D13504 32 Connected to MR of the S1D13504 33 Connected to WE1 of the S1D13504 34 S1D13504 supply provided by the S5U13504B00C S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 Epson Research and Development Vancouver Design Center The pinouts for Connector H2 are listed in the following table Table 4 3 CPU BUS Connector H2 Pinout Pin No Function 1 Connected to ABO of the S1D13504 2 Connected to AB1 of the S1D13504 3 Connected to AB2 of
203. S1D13504 Interface 4 1 Hardware Description The S1D13504 is interfaced to the PC Card bus with a minimal amount of glue logic A PAL is used to decode the read and write signals of the PC Card bus which generate RD RD WR WE0 WE1 and CS for the S1D13504 The PAL also inverts the reset signal of the PC card since it is active high and the 1D13504 uses an active low reset PAL equations for this implementation are listed in Section 4 3 PAL Equations on page 14 In this implementation the address inputs AB 20 0 and data bus DB 15 0 connect directly to the CPU address A 20 0 and data bus D 15 0 M R is treated as an address line so that it can be controlled using system address A21 BS bus start is not used and should be tied low connected to GND The PC Card interface does not provide a bus clock so one must be supplied for the S1D13504 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI The following diagram shows a typical implementation of the PC Card to 1D13504 interface WE A 21 0 Note PC Card PAL16L8 10 S1D13504 gt RD OE A gt RD WR CE1 gt gt WEO CE2 gt gt WE1 REG gt gt CS RESET gt gt RESET A21 gt M R gt AB 20 0 D 15 0 gt DB 15 0 15K pull up WAIT 4 b WAIT 7 BUSCLK Oscil
204. SA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Page 17 Vancouver Design Center 6 15 CPU Bus Interface Header Strips All of the CPU Bus interface pins of the S1D13504 are connected to the header strips H1 and H2 for easy interface to a CPU Bus other than the ISA bus Refer to Table 4 1 CPU BUS Connector H1 Pinout on page 10 and Table 4 2 CPU BUS Connector H2 Pinout on page 11 for specific settings Note These headers only provide the CPU Bus interface signals from the S1D13504 When another host bus interface is selected through MD3 1 configuration appropriate external decode logic MUST be used to access the S1D13504 See the section Host Bus Interface Pin Mapping of the S1D13504 Hardware Functional Specification document number X19A A 002 xx 6 16 Schematic Notes The following schematics are for reference only and may not reflect actual implementation Please request updated information before starting any hardware design S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date 01 02 02 X19A G 004 06 Page 18 7 Parts List Epson Research and Development Vancouver Design Center Item Qty board Designation Part Value Description 1 4 ms Cai our 10uF 25V Tantalum D Size 2 16 C1 C12 C15 C18 0 01uF 0 01uF 1206 package
205. SET RESET A120 A 20 13 AB 20 13 gt AB 12 0 D 31 24 gt DB 7 0 D 23 16 e gt DB 15 8 Von 15K pull up CARD1WAIT WAIT m ENDIAN See text _ 5 BUSCLK V DCLKOUT gt Clock divider Of Oscillator gt CLKI Note When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of SID13504 to PR31500 PR31700 Direct Connection Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Philips MIPS PR31500 PR31 700 Processor 1D13504 Issue Date 01 10 26 X19A G 005 09 Page 12 Epson Research and Development Vancouver Design Center The host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock This gives the system designer full flexibility in choosing the appro priate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 4 2 Memory Mapping and Aliasing S1D13504 X19A G 005 09 The S1D13504 requires an addressing spa
206. Schematic Diagram 4 of 6 2 0 2 cee ee nee 23 Figure 5 S1D13504B00C Schematic Diagram 5 of 6 12 2 eee eee nee 24 Figure 6 S1D13504B00C Schematic Diagram 6 of 6 2 1 cee eee 25 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date 01 02 02 X19A G 004 06 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the S5U13504B00C Rev 1 0 Evaluation Board when used with the S1D13504 Color Graphics LCD CRT Controller in the ISA bus environment For more information regarding the S1D13504 refer to the S1D13504 Hardware Functional Speci fication document number X19A A 002 xx 1 1 Features 128 pin QFP15 package SMT technology for all appropriate devices 4 8 bit monochrome passive LCD panels support 4 8 16 bit color passive LCD panels support 9 12 18 bit LCD TFT panels support External RAMDAC support 16 bit ISA bus support Oscillator support for CLKI up to 40 0MHz 5 0V 1M x 16 EDO DRAM Support for software power save modes 3 3V Core Vpp power supply Selectable 3 3V or 5 0V IO Vpp power supply via jumper JP2 On board adjustable LCD BIAS negative power supply 14V to 24V On board adjustable LCD BIAS positive
207. Seiko Epson does not assume liability for any damage done to the display device as a result of configuration errors 13504DCFG Driver Configuration Program 1D13504 X19A B 008 03 Issue Date 01 10 26 Page 6 Epson Research and Development Vancouver Design Center Installation Create a directory for 13504dcfg exe Copy the files 13504dcfg exe and panels def to that directory Panels def contains configuration information for a number of panels and must reside in the same directory as 13504dcfg exe Usage 13504DCFG can be started from the Windows desktop or from a Windows command prompt To start 13504DCFG from the Windows desktop double click the program icon in the directory which the program was installed To start 13504DCFG from a Windows command prompt change to the directory 13504dcfg exe was installed to and type the command 13504dcfg The basic procedure for using 13504DCFG is 1 Start 13504DCFG as described above 2 Modify the configuration settings For specific information on editing the configura tion see 13504DCFG Configuration Tabs on page 7 3 Save the configuration Several ASCII text file formats are supported Most are formatted C header files used to build display drivers 1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Epson Research and Development Page 7 Vancouver Design Center 13504DCFG Configuration Tabs 13504DCFG provides a series of tabs at the top of the main w
208. T 15 8 is used for RAMDAC data and is not available for LCD Refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx for details Refer to Table 3 1 LCD Signal Connector J6 on page 9 for connection information 6 9 External CMOS RAMDAC Support This evaluation board design provides CRT support with the addition of an external RAMDAC BrookTree BT481A or equivalent The presence of an external RAMDAC CRT can be determined by software once the S1D13504 is properly initialized after power up The BT481A RAMDAC is provided on the board to fully test all of the CRT display modes available Refer to the section Display Support of the S1D13504 Hardware Functional Specifi cation document number X19A A 002 xx for details The overlay function and sprite hardware cursor display features are not supported S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date 01 02 02 X19A G 004 06 Page 16 Epson Research and Development Vancouver Design Center 6 10 Power Save Modes The S1D13504F00A supports one hardware and one software suspend Power Save Mode The hardware suspend mode is not supported by the S3U13504B00C The software suspend mode is controlled by the utility 13504PWR Software Suspend Power Sequencing 6 11 Core Vpp Power Supply An independent fixed 3 3V power supply for Core Vpp is provided A National LP2960AIN 3 3 voltage regulator is used for the power supply an
209. TC VRTC VRTC ae na FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME Start Position Start Position Start Position Start Position Start Position Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5 0 VRTC FPFRAME Start Position Bits 5 0 For CRTs and TFTs these bits specify the delay in lines from the start of the vertical non display period to the leading edge of the VRTC pulse and FPFRAME pulse respectively For passive LCDs FPFRAME is automatically created and these bits have no effect VRTC FPFRAME start position lines VRTC FPFRAME Start Position Bits 5 0 1 The maximum VRTC start delay is 64 lines Note This register must be programmed such that REG OAh bits 5 0 1 gt REG OBh 1 REG OCH bits 2 0 1 1D13504 X19A A 002 19 Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 95 Vancouver Design Center VRTC FPFRAME Pulse Width Register REG OCh RW VRTC VRTC VRTC VRTC Polarity ES da iS ia FPFRAME FPFRAME FPFRAME Select ee Pulse Width Pulse Width Pulse Width Bit 2 Bit 1 Bit 0 bit 7 VRTC Polarity Select For CRTs this bit selects the polarity of the VRTC When this bit 1 the VRTC pulse is active high When this bit 0 the VRTC pulse is active low bit 6 FPFRAME Polarity Select This bit selects the polarity of the FPFRAME for TFT and passive LCD When this bit 1 the FPFRAME pulse is act
210. TEE i gaa SSA SSA Ll SSA SSA SSA SSA oh A AN3HHNO Ol var SOId9 ISUOVO SSA mum 801d 0SuOvG E PR moft mof m im x 0ldo tamova aano Horr 89 ta PA o aono aono Sr roido auova GAO s SHE SOldO ANVE aano Sor HOIDLA aono 2 dog Gaheaene suce Sor 0 Od9 OLYH rye a 4 x v0 aana400 one a0 3800 1 e one F F aena sR K R A aeS LOFTSSGGAO AS ear siivads N3IS3L rival vaa i apts aptos aoa uo gar JO pue z uTd 31045 Tiai aodain 2x apts zeptos goa uo gar Jo pue z utd 31048 ELIvad3 vaa EUA eg 1001 su ees bvads 00149 aano oLuvads CEEE eien e1vadd aim Py iin S7 L1Vdd3 Aivads suvadd oo LL oro S1Vddy yLWGdd m9 Ly osna Eee ae oas E 2v0 ZLWOd4 89 L _ _ _ __ _________ 80 sv 1IVada Aare CET OLYadd YIN EA ZHINS2 en nice e lovstlivads 13834 KK 1483 91 No z2 e aoyo lo silivags a aitisdavaauaaow As QQ ts 88 sa Sy 99 Lp a anrids 04 404 Sy me a el Veda 403M 403M S Y EN aM Sv uwad FUME sv E MN 4 umao1 siga viga erga z HAM 43M zisa onosna z svon svon uga svo1 svo1 orga z Sva svu 6ga 890 za SLOW 9ga z losion ion ssa eron vaa zian ega 108 y LOW zaa oran 180 q119808 eon osa 80n anosna 4 z LON ozay gt gt losga s y 3 san ergy a san Bey va
211. TK compact disc 1 4 Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK v2 0 Alternately use the current DEMO project included with the ETK v2 0 Follow the steps below to create a X86 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit e Drag the icon X86 DEMO1 onto the desktop using the right mouse button f Click on Copy Here g Rename the icon X86 DEMO1 on the desktop to X86 DEMO7 by right click ing on the icon and choosing rename h Right click on the icon X86 DEMO7 and click on Properties to bring up the X86 DEMO7 Properties window 1 Click on Shortcut and replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish 5 Create a sub directory named S1D13504 under x wince platform cepc drivers dis play 6 Copy the source code to the S1D13504 subdirectory Windows6 CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 5 Vancouver Design Center 7 Edit the file x wince platform cepc drivers display dirs and add S1D13504
212. This bit may be programmed to when the MCLK frequency is less than 30MHz RC Timing Value Npc Bits 1 0 These bits select the DRAM random cycle timing parameter tac These bits specify the number Nec of MCLK periods Ty used to create tac Ngc should be chosen to meet tre as well as tras the RAS pulse width Use the following two formulae to calculate Ngc then choose the larger value Note these formulae assume an MCLK duty cycle of 50 5 Ngc Round Up trc Tm Ngc Round Up tras Tm Nrp if Nrp lor2 Round Up tras Tm 1 55 if Nrp 1 5 The resulting tro is related to Ngc as follows tRC Nec Tm Table 8 11 Minimum Memory Timing Selection REG 22h Bits 6 5 Nac jale ES eye 00 5 Tu 01 4 4Tu 10 3 3 Tm 11 Reserved Reserved Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 108 bit 4 bits 3 2 1D13504 X19A A 002 19 RAS to CAS Delay Necp This bit selects the DRAM RAS to CAS delay parameter trop This bit specifies the number Nrcp of MCLK periods Ty used to create tecp Nrcp must be chosen to satisfy the RAS access time trac Note these formulae assume an MCLK duty cycle of 50 5 Nrcp Round Up trAc Su 1 Round Up tp ac TM 1 Round Up tp ac TM a 0 45 Epson Research and Development Vancouver Design Center if EDO and Ngp 1or2 if EDO and Npp 1 5 if FPM and Npp 1 or 2 if FPM and Npp 1
213. Tornado Workspace Views window Right click on Sbpp files or 16bpp files and select Dependencies Click on OK to regenerate project file dependencies for All Project files Right click on Sbpp files or 16bpp files and select ReBuild All vxWorks to build VxWorks 10 Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13504 8bpp default vx Works or x 13504 16bpp default vx Works to the bootable disk created in step 4 11 Start the VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO auto matically Wind River WindML v2 0 Display Drivers 1D13504 Issue Date 01 04 06 X19A E 002 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Wind River WindML v2 0 Display Drivers X19A E 002 03 Issue Date 01 04 06 EPSON 1D13540 Color Graphics LCD CRT Controller Wind River UGL v1 2 Display Drivers Document Number X19A E 003 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurat
214. Wee we ee we a He 16 4 1 Functional Block Diagram n oao a a ee d6 4 2 Functional Block Descriptions 2 ee ee ee ee 17 4 2 1 Host Interface to 40 24h wis a Go ee Be eee Athlon bh bo bee Ss 17 422 Memory Controller ve vta e teal PO ee OP oe oe Se oe lee aoe 17 42 3 Display FIFO 2 2 4 oe ae ees aha ae gee ee we Ge ee a ee ee a ge Ba wee 17 424 Took Up Table 4 3 e446 se Bw Eee RA Eee eee Bea oe ae A 17 423 LCD Interfaces oi 6 6 uk Bee ta eee eA ee o Bee bt A leads 17 ALDO Power Saven en 75 4h A a ee T ape aa ee ee Be ee ee A 17 5 SPIN OULU e ra Sas oS ee ee See Gh ee ea te Bae Gre Bln Sloe A Os eX 18 5 1 Pinout Diagram forSID13504FOOA 2 aaa 18 5 2 Pinout Diagram forSIDI3504FOIA 2 ee 19 5 3 Pinout Diagram for SID13504F02A 2 2 ee 20 34 Pin Description s s a 6 Be eM RR eR ara a 2 5 4 1 Host Interface iog cde a eh MR biol SE OP A eh SO bE ee ets 21 54 2 Memory Interface one ok ee ee eee Soe ee EA Pe eR Os 24 AO EGD Interface i 2 eee ES a eee BOE REP SOE MAS See Ee Bae be ee ee 26 SAA ClockInput 2c 28 a4 4 2 pain wh hE ES ee SRS ON ee ee nee ole SEES QS 26 5 45 CRT and External RAMDAC Interface 020 0 000000004 27 5 4 0 Miscellaneous sorga e a bh SG ee eee aE aE Os See 29 DAT Power Supply ita a Sl ge a a Ped De bog a a ale ar ws 29 5 5 Summary of Configuration Options 2 2 ee 30 5 6 Multiple Function Pin Mapping 2 a 31
215. When MD 10 9 11 at rising edge of RESETH this pin is an output with a reset state of 1 lts state is controlled by REG 21h bit 7 GPIOO IO 12 14 C TS1 Hi Z General Purpose IO pin 0 TSTEN 107 424 CD Hi Z Test Enable TMS in should be connected to Vgg for pulled 0 normal operation 1 2 35 38 71 NC j 74 107 E No connect 110 143 144 1 When configured as IO pin Output may be 1 or 0 5 4 7 Power Supply Table 5 7 Power Supply Pin Descriptions Pin Name Type Pin FOOA FOIA Driver FO2A Description COREVDD 33 97 39 111 P Core Vop IOVDD 110 14 46 83 16 52 93 124 IO Vpp VSS 96 104 109 15 32 51 17 34 57 68 74 87 78 84 97 106 118 123 Common Vss Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 30 5 5 Summary of Configuration Options Epson Research and Development Vancouver Design Center Table 5 8 Summary of Power On Reset Options value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface 16 bit host bus interface Select host bus interface 000 SH 3 bus interface MD 3 1 001 MC68K bus 1 e g MC68000 010 MC68K bus 2 e g MC68030 011 Generic bus interface e g Philips MIPS PR31500 PR31700 NEC MIPS Vr4102 1XX reserved
216. Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O bits 6 0 Horizontal Display Width Bits 6 0 These bits specify the LCD panel and or the CRT horizontal display width as follows Contents of this Register Horizontal Display Width 8 1 For passive LCD panels the Horizontal Display Width must be divisible by 16 and for TFT LCD panels CRTs the Horizontal Display Width must be divisible by 8 The maximum horizontal dis play width is 1024 pixels Note This register must be programmed such that REG 04h gt 3 32 pixels Horizontal Non Display Period Register REG 05h RW Horizontal Horizontal Horizontal Horizontal Horizontal n a n a n a Non Display Non Display Non Display Non Display Non Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bits 4 0 Horizontal Non Display Period Bits 4 0 These bits specify the horizontal non display period width in 8 pixel resolution as follows Contents of this Register Horizontal Non Display Period 8 1 The minimum value which should be programmed into this register is 3 32 pixels The maximum value which can be programmed into this register is 1F which gives a horizontal non display period width of 256 pixels Note This register must be programmed such that REG 05h gt 3 and REG O5h 1 gt REG 06h 1 REG 07h bits 3 0 1
217. _DEVICE device argument is not valid void seGetHalVersion const char pVersion const char pStatus const char pStatusRevision Description Gets HAL library version Parameter p Version must point to an allocated string of size VER_SIZE pStatus must point to an allocated string of size STATUS_SIZE pStatusRevision must point to an allocated string of size STAT_REV_SIZE Return Value None Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 40 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center int seGetld int device BYTE pld Description Reads the revision code register to determine the ID Parameter device registered device ID pld pointer to allocated byte The following are the possible values set to pld ID_S1D13504FO0A ID_S1D13703FO0A ID_S1D13505FO0A ID_UNKNOWN Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Note seGetId will disable hardware suspend on the Intel platform only and will enable the host in terface on all platforms int selnitHal void Description Initializes HAL library variables Must be called once when application starts see note below Parameter None Return Value ERR_OK operation completed with no problems Note For Intel platforms seRegisterDevice automatically calls seInitHal once Consecutive calls to seRegisterDe
218. able and can be selected by clicking on the Options button The options dialog appears as WinCE Header File Export Options 4 selects the mode number for use in the header file Cancel The mode information is used in the WinCE display driver for multi resolution support 13504DCFG Driver Configuration Program S1D13504 Issue Date 01 10 26 X19A B 008 03 Page 22 Epson Research and Development Vancouver Design Center Enable Tooltips Tooltips provide useful information about many of the items on the configuration tabs Placing the mouse pointer over nearly any item on any tab generates a popup window containing helpful advice and hints To enable disable tooltips check uncheck the Tooltips option form the Help menu Note Tooltips are enabled by default Tooltip Delay The pop up menu is used to select the delay before the tooltip appears ERD on the Web This Help menu item is a hotlink to the Epson Research and Development website Selecting Help then ERD on the Web starts the default web browser and points it to the ERD web site The latest software drivers and documentation for the S1D13504 is available at this website Update Common Controls Many of the dialog controls used by 13504DGFG require the latest version of the Microsoft Windows Common Controls Selecting Help then Update Common Controls starts the process of updating the Microsoft Windows Common Controls
219. able for these alternate functions This requirement may be accommodated through use of the Generic Bus interface mode on the 1D13504 2 2 Chip Select Module 1D13504 X19A G 013 03 The 68328 can generate up to 16 chip select outputs organized into four groups A through D Each chip select group has a common base address register and address mask register to set the base address and block size of the entire group In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s address block Finally each chip select may be individually programmed to control an 8 or 16 bit device and each may be individually programmed to generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally through use of the standard MC68000 DTACK signal Groups A and B can have a minimum block size of 64K bytes so these are typically used to control memory devices Chip select AO is active immediately after reset so it is typically used to control a boot EPROM device Groups C and D have a minimum block size of 4K bytes so they are well suited to controlling peripheral devices Chip select D3 is associated with the 68328 on chip PCMCIA control logic Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 3 S1D1
220. ace to look for the necessary files and in structions on this process is on the Internet at www xfree86 org S1D13504 Linux Console Driver X19A E 004 01 Issue Date 01 11 19 Epson Research and Development Page 7 Vancouver Design Center Building the Console Driver for Linux Kernel 2 4 x Linux Console Driver Issue Date 01 11 19 Follow the steps below to construct a copy of the Linux operating system using the S1D13504 as the console display device These instructions assume that the GNU devel opment environment is installed and the user is familiar with GNU and the Linux operating system 1 Acquire the Linux kernel source code You can obtain the Linux kernel source code from your Linux supplier or download the source from ftp ftp kernel org The S1D13504 reference driver requires Linux kernel 2 4 x or greater The example S1D13504 reference driver available on www erd epson com was built using Red Hat Linux 6 1 kernel version 2 4 5 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13504 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13504 archive to a temporary directory e g tmp When completed the files Config in fbmem c fbcon cfb4 c Makefile should be located in the temporary directory
221. al Support 7 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de 7 2 NEC Electronics Inc VR4102 NEC Electronics Inc U S A Santa Clara California Tel 800 366 9782 Fax 800 729 9288 http Awww nec com Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the NEC VR4102 Microprocessor Issue Date 01 10 26 1D13504 X19A G 007 08 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007
222. am Messages 13504SPLT Display Utility Issue Date 01 01 30 The PC must not have more than 12M bytes of system memory when used with the 5U13504BO00C board Follow simultaneous display guidelines for correct simultaneous display operation To determine if the CRT will operate correctly when using a dual panel refer to the Maximum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing A CRT cannot show 15 or 16 bits per pixel Do not attach a panel with a 16 bit interface to the S1D13504 when a CRT is also attached ERROR Too many devices registered There are too many display devices attached to the HAL The HAL can only manage 10 devices simultaneously ERROR Could not register S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program ERROR Did not detect S1D13504 The HAL was unable to read the revision code register on the S1D13504 Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly S1D13504 X19A B 003 05
223. ast Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg S1D13504 X19A A 002 19 Page 134 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 EPSON 1D13504 Color Graphics LCD CRT Controller Programming Notes and Examples Document Number X19A G 002 07 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 3 Vancouver Design Cen
224. at the beginning of each frame the pixel panning value is latched immediately upon being set Setting the registers in the wrong sequence or at the wrong time will result in a tearing or jitter on the display The correct sequence for programing these registers is 1 Wait until just after a vertical non display period read register OAh and watch bit 7 for the non display status 2 Update the start address registers 3 Wait until the next vertical non display period 4 Update the pixel paning register Note The S1D13504 provides a false indication of vertical non display period when used with a dual panel display In this case it is impossible to identify the false signal from the true non display period The result is that panning operations at less than 15 bpp may exhibit an occasional tear as the result of updating registers in the wrong order This effect is barely noticeable at 8 bpp but becomes pronounced at 4 bpp and lower color depths Setting the registers out of sequence will make the tear more apparent Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 26 4 2 1 Registers Epson Research and Development Vancouver Design Center REG 10h Screen 1 Display Start Address 0 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6
225. ate 01 04 17 X00A E 003 04 Page 4 Windows 2000 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards 9 Install the evaluation board in the computer and boot the computer Windows will detect the new hardware as a new PCI Device and bring up the FOUND NEW HARDWARE dialog box Click NEXT The New Hardware Wizard will bring up the dialog box to search for a suitable driver Click NEXT When Windows does not find the driver it will allow you to specify the location of it Type the driver location or select BROWSE to find it Click NEXT Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card Select this file and click OPEN Windows then shows the path to the file Click OK 10 Click NEXT 11 Click FINISH All ISA Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD REMOVE HARDWARE click NEXT Select ADD TROUBLESHOOT A DEVICE and click NEXT Windows 2000 will attempt to detect any new plug and play device and fail The CHOOSE HARDWARE DEVICE dialog box appears Select ADD NEW HARDWARE and click NEXT Select NO IWANT TO SELECT FROM A LIST and click NEXT Select OTHER DEVICE from the list and click NEXT Click HAVE DISK Specify the location of the driver files select the SID13XXX INF file and click OPEN Click OK S1D13XXX 32 Bit
226. ation Figure 3 2 Configuration Jumper JP1 Location Figure 3 3 Configuration Jumper JP2 Location Figure 3 4 Configuration Jumper JP3 Location Figure 3 5 Configuration Jumper JP4 Location Figure 3 6 Configuration Jumper JP5 Location Figure 3 7 Configuration Jumper JP6 Location Figure 3 8 Configuration Jumper JP7 Location Figure 7 1 S5U13504B00C Rev 2 0 Evaluation Board Schematics 1 of 5 Figure 7 2 S5U13504B00C Rev 2 0 Evaluation Board Schematics 2 of 5 Figure 7 3 S5U13504B00C Rev 2 0 Evaluation Board Schematics 3 of 5 Figure 7 4 S5U13504B00C Rev 2 0 Evaluation Board Schematics 4 of 5 Figure 7 5 S5U13504B00C Rev 2 0 Evaluation Board Schematics 5 of 5 Figure 8 1 S5U13504BO0C Rev 2 0 Evaluation Board Layout S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 Page 5 S1D13504 X19A G 014 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the S5U13504B00C Rev 2 0 PCI Evalu ation Board The S5U13504BO0C is designed as an evaluation platform for the S1D13504 Color LCD Controller chip
227. ation X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 19 Vancouver Design Center 5 2 Pinout Diagram for S1D13504F01A 295 as 9929 oo lso ss 27 ee e5 e4 es lez eo Izo zs 77 z zs z a 727 zo 60 lee e7 lee 6s YN UY UUUVOVUUO SeSPSTTVIVVVVVIVADVAOCVAHRFOS 0 O O OOG O O OT D OO DO y U VUUUOOOODOOOSO 0 y Uucmnoao zos AAA AS ozy a IXIZJ a F 2223232200 fP TY aa konto FT Ems 9 corevoD MD1 ae _ 98 DACPO MD13 P 2 22 nacre MD2 he 1 100 bacrso MD12 ieee 101 pacers MD3 _102 HRTC MD11 P 103 vatc MD4 EN 104 _ vss MD10 E 05 ci MDS 106 SUSPEND MD9 ee 107 TESTEN MD6 FE 108 53 BUSCLK MD8 Mn 109 52 VSS MD7 110 51 IOVDD vss H 111 AB20 LCAS ee de agia ucast 2 _ 113 48 114 ABIS S1 D1 3504F01 A WE ar AB17 RAS H 15 apis lovop 46 116 AB15 MA9 17 a matt 44 118 9B 13 mas PE 119 42 AB12 MA10 KH 121 AB10 mao 40 122 ABQ MA6 39_ 123 ABg Mai 138 _ 124 AB7 mas 197 125 ABe Maz 36_ 126 ABs mag 3 127 34 AB4 MAS 128 aps COREVpD 198 gp z g mo 5 n gt gt ro oo An MR255588888 800000909005 PSR ERRE REGSPFUONARAOoa agg gg PERDO f E E la E E E ls o hof 12 hra frais re fiz fts 1020 21 22 2 24 25 28 27 28 2030132 Figure 5 2 Pinout Diagram of FOIA Package type 128 pin surface mount TQFP15 Hardware Functional Spe
228. ay S 1D13504 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the display driver If the default does not match the configura tion you are building for then MODEO H will have to be regenerated with the correct information Use the program 13504CFG to generate the header file For information on how to use 13504CFG refer to the 13504CFG Configuration Program User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the original configuration file Edit the file PLATFORM REG to match the screen resolution color depth and rota tion information in MODE H PLATFORM REG is located in x wince300 plat form cepc files For example the display driver section of PLATFORM REG should be as follows when using a 640x480 LCD panel with a color depth of 8 bpp and a SwivelView mode of 0 landscape Default for EPSON Display Driver 640x480 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x 1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D 13504
229. be tied low connected GND The following diagram shows a typical implementation of the MCF5307 to S1D13504 interface MCF5307 S1D13504 A21 M R A 20 0 AB 20 0 D 31 16 DB 15 0 Freq 74AC08 or equiv CS4 CS CS5 Vcc 470 TA a WAIT WE1 WE1 WEO WEO OE RD1 RDO BCLKO BUSCLK System RESET RESET Note 7 When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MCF 5307 to S1D13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 01 1 07 Page 14 4 2 S1D13504 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13504 uses MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx Table 4 1 SID13504 Configuration Settings S1D13504 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 MDO 8 bit host bus interface MD1 MD2 MD3
230. below color color of line For 1 2 4 and 8 bpp color refers to the pixel value which points to the respective LUT DAC entry For 15 and 16 bpp color refers to the pixel value which stores the red green and blue intensities within a WORD Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Note seDrawLine only draws horizontal and vertical lines and that the line drawn does not include the endpoint x2 y2 int seDrawText int device char fmt Description For Intel platforms draws text to standard output For embedded platforms draws text to terminal Parameter device registered device ID fmt identical to printf formatting strings identical to printf arguments for formatting strings Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_INVALID_STD_DEVICE device is not HAL_STDOUT or HAL_STDIN but don t use HAL_STDIN for seDrawText Note seDrawText currently doesn t write text to the display buffer 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 51 Vancouver Design Center int seFillRect int device int x1 int y1 int x2 int y2 DWORD color Description Draws a solid rectangle on the display Parameter device registered device ID x1 y1 top left corner of rectangle x2 y2 bott
231. bled Dual Monochrome Panel with Half Frame Buffer 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Enabled 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 e Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable 3 MCLK MCLK MCLK MCLK 2 MCLK 2 Dual Color Panel with Half Frame Buffer Enabled 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 e Simultaneous CRT Dual Color Panel with Half 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Frame Buffer Enable 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Page 119 11 2 Frame Rate Calculation The frame rate is calculated using the following formula PCLK FrameRate IA AAA HDP HNDP x VDP VNDP Where VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 in table below HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts given in table below Ts Pixel Clock PCLK Table 11 3 Example Frame Rates Color Maximum Minimum Maximum Frame 1 PRAM Type Display Resolution Depth ee Panel pete ie Speed Grade bpp Clock HNDP T
232. bpp Color In 2 bpp color mode the 16 LUT entries are divided into four separate 4 entry banks per color The following table demonstrates recommended LUT data values which produce Bank 0 low intensity Bank high intensity Bank 2 inverted low intensity Bank 3 inverted high intensity Table 3 9 Recommended LUT Values for 2 bpp Color Mode Address Red Green Blue Address Red Green Blue 00 00 00 00 08 07 07 07 01 03 03 03 09 05 05 05 02 05 05 05 0A 03 03 03 03 07 07 07 0B 00 00 00 04 00 00 00 0C OF OF OF 05 OA 0A 0A 0D 0D 0D 0D 06 0D 0D 0D OE 0A 0A 0A 07 OF OF OF OF 00 00 00 Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 19 Vancouver Design Center Issue Date 01 02 01 4 bpp Color In 4 bpp color mode the LUT is limited to a single 16 entry bank per color The LUT bank select bits have no effect in this mode The following table is a recommended set of data values to simulate the 16 colors ina VGA The second recommendation for this mode is to program the register values to data values equalling the register number i e R O 0 G 0 0 B 0 0 R 1 1 R F 0Fh Table 3 10 Recommended LUT Values to Simulate VGA Default 16 Color Palette Address Red Green Blue Address Red Green Blue 00 00 00 00 08 00 00 00 01 00 00 0A 09 00 00 OF 02 00 0A 00 0A 0
233. buffer On user input or elapsed time the line compare register value is changed to adjust the amount of area displayed on either screen The 13504SPLT display utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13504CFG EXE which can be used to configure 13504SPLT This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13504 Supported Evaluation Platforms Installation 13504SPLT has been tested with the following 1D13504 supported evaluation platforms PC system with an Intel 80x86 processor M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC00O0 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13504 Programming Note
234. by FRM on monochrome passive LCD panels a 16x4 Look Up Table is used to map 1 2 4 bit per pixel modes into these shades Up to 4096 colors on color passive LCD panels three 16x4 Look Up Tables are used to map 1 2 4 8 bit per pixel modes into these colors 16 bit per pixel mode is mapped directly using the 4 most significant bits of the red green and blue colors Up to 64K colors in 16 bit per pixel mode on TFT panels Split screen mode allows two different images to be simultaneously displayed Virtual display mode displays images larger than the panel size through the use of panning and scrolling Double buffering multi pages for smooth animation and instantaneous screen update Fast Update feature accelerates screen update by allocating full display buffer bandwidth to CPU see REG 23h bit 7 Single clock input for both pixel and memory clocks Memory clock can be input clock or input clock 2 this provides flexibility to use CPU bus clock as input clock Pixel clock can be memory clock memory clock 2 memory clock 3 or memory clock 4 The memory data bus MD 15 0 is used to configure the chip at power on Up to 12 General Purpose Input Output pins are available e GPIOO is always available e GPIO 3 1 are available if upper Memory Address pins are not required for DRAM support e GPIO 11 4 are available if there is no external RAMDAC Suspend power save mode is initiated by hardware or softwar
235. can be interfaced with the PR31500 PR31700 without using a PC Card slot Instead the S1D13504 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the 1D13504 virtually transparent to PC Card devices that use the same slot 5 1 Hardware Description Using One IT8368E 1D13504 X19A G 005 09 The ITE IT8368E has been specifically designed to support EPSON LCD CRT controllers The IT8368E provides eleven Multi Function IO pins MFIO Configuration registers can be used to allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU interface The Philips PR31500 PR31700 processor only provides addresses A 12 0 therefore devices that occupy more address space must use an external device to latch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address However when using the S1D13504 five MFIO pins are utilized for S1D13504 control signals and cannot provide latched addresses In this case an external latch must be used to provide the high order address bits For a solution that does not require a latch refer to Section 5 2 Hardware Description Using Two IT8368E s Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Page 15 Vancouver Design Center
236. ce of 2M bytes for the display buffer and 64 bytes for the registers This is divided into two address ranges by connecting A23 demultiplexed from the PR31500 PR31700 to the M R input of the S1D13504 Using A23 makes this implementation software compatible with the two implementations that use the ITE IT8368E see Section 5 System Design Using the IT8368E PC Card Buffer on page 14 All other addresses are ignored The S1D13504 address ranges as seen by the PR31500 PR31700 on the PC Card slot 1 memory space are as follows e 6400 0000h S1D13504 registers aliased 131 072 times at 64 byte intervals over 8M bytes e 6480 0000h S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M bytes e 6500 0000h S1D13504 registers and display buffer aliased another 3 times over 48M bytes Since the PR31500 PR31700 control signal CARDREG is ignored the S1D13504 takes up the entire PC Card slot 1 configuration space The address range is software compatible with both ITE IT8368E implementations e 0900 0000h S1D13504 registers aliased 131 072 times at 64 byte intervals over 8M bytes e 0980 0000h S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M bytes Note If aliasing is undesirable additional decoding circuitry must be added Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Page 13 Vancouver Design Center 4 3 S1D13504 Configura
237. cification Issue Date 01 11 06 Epson Research and Development Page 65 Vancouver Design Center tl t2 Sync Timing dl FPFRAME 13 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 p t9 tit t12 FPSHIFT gt 4 gt UD 3 0 d 2 x Figure 7 20 Single Monochrome 4 Bit Panel A C Timing Table 7 19 Single Monochrome 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t8 FPSHIFT period 4 Ts t9 FPSHIFT falling edge to FPLINE falling edge note 6 t10 FPLINE falling edge to FPSHIFT rising edge 18 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPSHIFT pulse width low 2 Ts t13 UD 3 0 setup to FPSHIFT falling edge 2 Ts t14 UD 3 0 hold to FPSHIFT falling edge 2 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 min t4min 9TS 3 min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG 04h bits 6 0 1 8 1 Ts 5 t6min REG 05h bits 4 0 1 8 25 Ts 6 t9min RE
238. cification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 20 5 3 Pinout Diagram for S1D13504F02A Epson Research and Development Vancouver Design Center hobohobodhobohodohodobebrlobsbalo bob bokokolrkokslee bolo 1 hobobal7hobsbabo 5855333222125 SH 2033332020305 03022555558 EEE ERA IIS 3334353353333 033033333333 EXZ2PZZ o E O SO o 5 2 Y Noor won o 3 5 m gt m 109 ye no 72 110 Nc NG 171 111 POLEN MD1 70 112 nae MD13 69 113 RUS MD2 68 14 AT MD12 67 0 a 15 paons ups Les 447 HRTC MD11 pg 7 VRTC MD4 64 _ 118 vss MD10 163 19 ouni alee Ec SUSPEND iDa st Ee TESTEN MD6 Re 27 BUSCLK MD8 gt 123 ss mp7 158 124 ovpp vss 5 125 Ano Lcas 28 126 aero ucast 85 127 S1D13504F02A 54 AB18 WE 128 AB17 RASH 53 129 1816 lovop 92 130 apis mag 5 131 AB14 matt SO 132 Ars mag 2 Em AB12 MATO 135 Ae MA 46 Tan AB10 MAO Das 136 ABg Mas gt Fale MAI Tg Seal MAS ap Taa Mae E ABS MA4 141 ap 40 MA3 142 aps 39 COREVDD 143 nc e e 144 Ne E ne BO Sm S 20 z SS 20u5 lt UVUUUOUOO gt gt gt O U0 gt 3mm Miio5Y U0vwUvu woouoyouoouoyuuyuouyououS NAAA O P28 OF oe on oe ee gpp h e o A b b 7 b b hohihzhahahshehzhsho 0 1b abapspeb7ps Po Bot B2j88 babs be Figure 5 3 Pinout Diagram of FO2A Package type 144 pin surface mount QFP20 S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver
239. configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Specification document number X19A A 002 xx The partial table below only shows those configuration settings relevant to the IT8368E implementation Table 5 3 SID13504 Configuration using the IT8368E S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 MDO 8 bit host bus interface MD1 MD2 MD3 MD4 MD5 See Host Bus Selection table below WAIT signal is active high See Host Bus Selection table below 0 Big Endian ee required configuration for connection using ITE IT8368E Table 5 4 SID13504 Host Bus Selection using the IT8368E MD3 MD2 MD1 Host Bus Interface SH 3 bus interface MC68K bus 1 interface e g MC68000 ojojo O O oj o X MC68K bus 2 interface e g MC68030 Reserved 1 x required configuration for connection using ITE IT8368E 1D13504 X19A G 005 09 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Page 21 Vancouver Design Center 6 Software Test utilities and display drivers are available for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program ca
240. configured for an 8 bit interface The Epson supplied software performs this function automatically S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date 01 02 02 X19A G 004 06 Page 14 Epson Research and Development Vancouver Design Center 6 2 Non ISA Bus Support This evaluation board is specifically designed to support the standard 16 bit ISA bus however the 1D13504 directly supports many other host bus interfaces Header strips H1 and H2 have been provided and contain all the necessary IO pins to interface to these buses See Section 4 CPU BUS Interface Connector Pinouts on page 10 Table 2 1 Configuration DIP Switch Settings on page 8 and Table 2 3 Jumper Settings on page 8 for details When using the header strips to provide the bus interface observe the following All IO signals on the ISA bus card edge must be isolated from the ISA bus do not plug the card into a computer Voltage lines are provided on the header strips U3 a TIBPAL22V 10 PAL is currently used to provide the S1D13504 CS pin 4 M R pin 5 and other decode logic signals for ISA bus use This functionality must now be provided exter nally remove the PAL from its socket to eliminate conflicts resulting from two different outputs driving the same input Refer to Table 5 1 Host Bus Interface Pin Mapping on page 12 for connection details Note When using a 3 3V CPU Interface JP2 must be used t
241. connection 1D13504 Supported Evaluation Platforms Installation 13504PLAY Diagnostic Utility Issue Date 01 02 01 13504PLAY has been tested with the following 1D13504 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D 13504 Programming Notes and Examples manual document number X19A G 002 xx PC platform copy the file 13504PLAY EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13504PLAY to the system 1D13504 X19A B 005 05 Page 4 Usage 1D13504 X19A B 005 05 Epson Research and Development Vancouver Design Center PC platform at the prompt type 13504play Embedded platform execute 13504play and at the prompt type the command line argument Where displays program revision information The following commands are valid within the 13504PLAY program X index data XA D index datal data2 data3 DA L index datal data2 data3 LA F W addrl addr2 data R W addr count W W addr data M bpp Reads writes the registers Writes data to
242. ct When this bit 1 color passive LCD panel is selected When this bit 0 monochrome passive LCD panel is selected bit 1 Dual Single Panel Select When this bit 1 dual passive LCD panel is selected When this bit 0 single passive LCD panel is selected Setting this bit for single panel mode should be done only when the Half Frame Buffer is idle The Half Frame Buffer is idle during vertical non display periods or while in suspend mode For programming information see 1D13504 Programming Notes and Examples document number X19A G 002 xx bit 0 TFT Passive LCD Panel Select When this bit 1 TFT panel is selected When this bit 0 passive LCD panel is selected MOD Rate Register REG 03h RW MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit n a n a 5 4 3 2 1 0 bits 5 0 MOD Rate Bits 5 0 Hardware Functional Specification Issue Date 01 11 06 For a non zero value these bits specify the number of FPLINE between toggles of the MOD output signal When these bits are all 0 s the MOD output signal toggles every FPFRAME These bits are for passive LCD panels only S1D13504 X19A A 002 19 Page 92 Epson Research and Development Vancouver Design Center Horizontal Display Width Register REG 04h RW Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal n a Display Width Display Width Display
243. ction 6 1 1 CRT Only The CRT timing is based on both the VESA Monitor Timing Standards Version 1 0 and Frame Rate Calculation Chapter 11 in S1D13504 Hardware Functional Specification The following sections describe CRT considerations For CRT only the Dual Single Panel Select bit of Panel Type Register REG 02h must first be set to single passive LCD panel The monitor configuration registers then need to be set to follow the VESA timing standard Note If only the CRT is used it is also useful to disable the LCD power set REG 1 Ah bit 4 1 This will reduce power consumption To program the external RAMDAC set the CRT Enable bit in the Display Mode Register REG ODh to 1 Once the CRT is enabled the GPIO registers will be automatically set to access the external RAMDAC Next program the RAMDAC Write Mode Address register and the RAMDAC Palette Data register as desired refer to sample code in 9 1 2 for details When programming the RAMDAC control registers connect the RAMDAC to the low byte of the CPU data bus for Little Endian architecture and the high byte for Big Endian architecture The RAMDAC registers are mapped as follows Table 6 1 RAMDAC Register Mapping for Little Big Endian Register Name Little Endian Big Endian RAMDAC Pixel Read Mask REG 28h REG 29h RAMDAC Read Mode Address REG 2Ah REG 2Bh RAMDAC Write Mode Address REG 2Ch REG 2Dh RAMDAC Palette Data REG 2Eh
244. ction 5 0 a se AA A DAA RA A arte 7 2 Interfacing to the NEC VR4102 8 2 1 The NEC VR4102 System Bus 2 2 2 8 2b OVNEN fogs so chee dl aks A a gard a GS 8 2 1 2 LCD Memory Access Cycles 2 0 20 00 0 ee 9 3 S1D13504 Host Bus Interface et 10 3 1 Generic MPU Host Bus Interface Pin Mapping 2 2 2 2 2 10 3 2 Generic MPU Host Bus Interface Signals 2 2 Td 4 VR4102toS1D13504 Interface 12 4 1 Hardware Description a a 1 4 2 S1D13504 Hardware Configuration 2 ee eee ee 13 4 3 NEC VR4102 Configuration 2 a a eee A 5 Software iins sate ee we a ees ee al Be ee a E 15 RGIGIENCES 2 Gc aon attend aa eel ae em Bede ao ee ea ee es la 16 GI DOCUMENTS ws ver Ad AW a ie ar e A a ae Se et we le a N 6 2 Document Sources nio a e E h e aa a aa 16 T Technical S pport see Sek E a AE E aa 17 7 1 EPSON LCD CRT Controllers S1D13504 a a a a a aaa aaa 17 7 2 NEC Electronics Inc VR4102 2 2 co e ee ee ee TT Interfacing to the NEC VR4102 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 007 08 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 Epson Research and Development Page 5 Vancouver De
245. current color depth certain bits of the pixel pan register are not used The following table shows this Table 4 2 Active Pixel Pan Bits Color Depth bpp Pixel Pan bits used 1 bits 3 0 2 bits 2 0 4 bits 1 0 8 bit 0 15 16 ca 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 27 Vancouver Design Center 4 2 2 Examples For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x200 viewport Refer to Section 2 2 Register Initialization on page 9 and Section 4 1 Virtual Display on page 23 for assistance with these settings Example 4 Panning Right and Left To pan to the right increment the pixel pan value If the pixel pan value is now equal to the current color depth then set the pixel pan value to zero and increment the start address value To pan to the left decrement the pixel pan value If the pixel pan value is now less than zero set it to the color depth bpp less one and decrement the start address value The following pans to the right by one pixel in 4 bpp display mode 1 It s better to keep one value call it pan_value to track both the pixel panning and start address rather than maintain separate values for each of these 2 To pan to the right increment pan_value pan_value pan_value 1 3 Mask off the values from pan_value for the pixel panning and start address
246. d for non Intel platforms Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 53 Vancouver Design Center WORD seRotateByteLeft BYTE val BYTE bits Description Rotates the bits in val left as many times as stated in bits Parameter val value to rotate bits how many bits to rotate Return Value bits 15 8 non zero if carry flag set bits 7 0 rotated byte WORD seRotateByteRight BYTE val BYTE bits Description Rotates the bits in val right as many times as stated in bits Parameter val value to rotate bits how many bits to rotate Return Value bits 15 8 non zero if carry flag set bits 7 0 rotated byte Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 54 Epson Research and Development Vancouver Design Center 9 Sample Code 9 1 Introduction The following code samples demonstrate two approaches to initializing the S1D13504 color graphics controller with without using the 13504HAL API These code samples are for example purposes only 9 1 1 Sample code using 13504HAL API k k Created 1998 Epson Research Development aK Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All rights reserved xk xy include lt stdio h gt include lt stdlib h gt include lt string h gt include hal h include appcfg h fis void mai
247. d the Edit LUT Setup window is displayed The Edit LUT Setup window lists parameters which can be edited as shown below in Figure 21 13504CFG Edit LUT Setup In this example window Bits Per Pixel 2 is highlighted Note A future release of 13504CFG will enable components in the lookup table palette to be edited For example the red green and blue components of LUT palette entry OFh could be edited Cancel Help E AAA Y Figure 21 13504CFG Edit LUT Setup LUT Parameter Edit When a selection is highlighted for editing in the Edit LUT Setup window and Edit is clicked the LUT Parameter Edit window displays for parameter editing See figure 22 13504CFG LUT Parameter Edit below In this example window Bits Per Pixel 2 can be edited Bits Per Pixel Cancel Help Figure 22 13504CFG LUT Parameter Edit 13504CFG EXE Configuration Program Issue Date 01 01 30 Epson Research and Development Page 27 Vancouver Design Center Setup When Setup is selected from the Device menu the Setup dialog box is displayed To select either Register Location Memory Location or Memory Size highlight it in the example window below Register Location 00C00000 hex is highlighted and click OK If the highlighted Setup assignment needs changes click Edit and see the next section Setup Parameter Edit In addition to OK Cancel and Edit commands a Help command is listed in the Set
248. d Aliasing When the TX3912 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table Note Bits CARDIIOEN and CARD2IOEN need to be set in the TX3912 Memory Configuration Register 3 Table 5 1 TX3912 to Unbuffered PC Card Slots System Address Mapping z Function Function TASSA BODIES size CARDnIOEN 0 CARDnIOEN 1 0800 0000h 64Mb Card 1 Attribute Card 1 IO 0C00 0000h 64Mb Card 2 Attribute Card 2 IO 6400 0000h 64Mb Card 1 Memory 6400 0000h 64Mb Card 2 Memory When the TX3912 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CARD2IOEN are ignored and the attribute IO space of the TX3912 is divided into Attribute IO and S1D13504 access Table 5 2 TX3912 to PC Card Slots Address Remapping using the IT8368E provides all the details of the Attribute IO address re allocation by the IT8368E Table 5 2 TX3912 to PC Card Slots Address Remapping using the IT8368E IT8368E Uses PC Card Slot TX3912 Address Size Function 0800 0000h 16M byte Card 1 IO S1D13504 registers 0900 0000h 8M byte aliased 131 072 times at 64 byte intervals 1 1D13504 display buffer 0980 0000h 8M byte aliased 4 times at 2Mb intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO S1D13504 registers 0D00 0000h 8M byte aliased 131 072 times at 64 byte inter
249. d LUT load LUT load Look Up Table REG 27h 0000 0000 0000 0000 0000 0000 set Look Up Table to bank 0 Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 62 1D13504 X19A G 002 07 Epson Research and Development Table 9 3 TFT Panel TFT 16 Bit Register aie Notes Color REG O2h 0010 0101 set panel type REG O3h 0000 0000 set MOD rate REG 04h 0100 1111 set horizontal display width REG O5h 0001 0011 set horizontal non display period REG 06h 0000 0110 set HSYNC start position REG O7h 0000 0111 set HSYNC polarity and pulse width REG O8h 1101 1111 set vertical display height bits 7 0 REG O9h 0000 0001 set vertical display height bits 9 8 REG OAh 0010 1101 set vertical non display period REG OBh 0000 0000 set VSYNC start position REG OCh 0000 0010 set VSYNC polarity and pulse width REG ODh 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0001 set MCLK and PCLK divide REG 24h 0000 0000 set Look Up Table address to 0 REG 26h load LUT load Look Up Table REG 27h 0000 0000 set Look Up Table to bank 0 Vancouver Design Center Programming Notes and Examples Issue Date 01 02 01
250. d delete x wince platform cepc bif Windows6 CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 9 Vancouver Design Center 12 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 13 Type BLDDEMO lt ENTER gt at the command prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN Windows CE 2 x Display Drivers 1D13504 Issue Date 01 05 25 X19A E 001 05 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK BIN file is built the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC after booting from a floppy drive a Create a bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain only the following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to ca f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C Search for the loadCEPC utility in your Windows CE directories b Edit
251. d is capable of supplying 500mA 3 3V 6 12 10 Vpp Power Supply The IO Vpp voltage is selectable between 3 3V and 5 0V through jumper JP2 For the 5 0V host bus interface select IO Vpp at 5 0V and for the 3 3V host bus interface select IO Vpp at 3 3V Refer to Table 2 3 Jumper Settings on page 8 6 13 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 18V and 23V LI 45mA For ease of implementation such a power supply has been provided as an integral part of this design The signal VLCD can be adjusted by R37 to supply an output voltage from 14V to 23V and is enabled disabled by the S1D13504 control signal LCDPWR Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 6 14 Adjustable LCD Panel Positive Power Supply Most passive LCD passive color panels and most single monochrome 640x480 passive LCD panels require a positive power supply to supply between 23V and 40V 45mA For ease of imple mentation such a power supply has been provided as an integral part of this design The signal VDDH can be adjusted by R31 to provide an output voltage from 23V to 40V and is enabled disabled by the S1D13504 control signal LCDPWR Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 1D13504 S5U13504B00C Rev 1 0 I
252. d to IO e For SH 3 mode these pins are connected to D 15 0 e For MC68K Bus 1 these pins are connected to D 15 0 e For MC68K Bus 2 these pins are connected to D 31 16 for 32 bit devices e g MC68030 or D 15 0 for 16 bit devices e g MC68340 e For Generic Bus these pins are connected to D 15 0 See Table 5 9 Host Bus Interface Pin Mapping on page 31 for summary Hardware Functional Specification Issue Date 01 11 06 1D13504 X19A A 002 19 Page 22 Epson Research and Development Vancouver Design Center Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin FOOA FOIA F02A Driver Reset 0 Value Description WE1 11 CS This pin has multiple functions e For SH 3 mode this pin inputs the write enable signal for the upper data byte WE1 e For MC68K Bus 1 this pin inputs the upper data strobe UDS e For MC68K Bus 2 this pin inputs the data strobe DS e For Generic Bus this pin inputs the write enable signal for the upper data byte WE1 See Table 5 9 Host Bus Interface Pin Mapping on page 31 M R This input pin is used to select between the memory and register address spaces of the S1D13504 M R is set high to access the memory and low to access the registers See Section 8 1 Register Mapping on page 89 See Table 5 9 Host Bus Interface Pin Mapping on page 31 CS Hi Z Chip
253. d to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where Windows CE may serve as a primary operating system The S1D13504 supports LCD interfaces with data widths up to 16 bits Using Frame Rate Modulation FRM it can display 16 shades of gray on monochrome LCD panels up to 4096 colors on passive color LCDs and 64K colors on active matrix TFT LCD panels CRT support is handled through the use of an external RAMDAC interface allowing simultaneous display of both the CRT and LCD panel A 16 bit memory interface supports up to 2M bytes of FPM DRAM or EDO DRAM Flexible operating voltages from 2 7V to 5 5V provide for very low power consumption Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 12 2 Features Epson Research and Development Vancouver Design Center 2 1 Memory Interface 2 2 CPU Interface 2 3 Display Support 1D13504 X19A A 002 19 16 bit DRAM interface e EDO DRAM up to 40MHz data rate 80M bytes per second e FPM DRAM up to 25MHz data rate 50M bytes per second Memory size options e 512K bytes using one 256Kx16 device e 2M bytes using one 1Mx16 device A configuration register can be programmed to enhance performance by tailoring the memory control output timing to the DRAM device Supports the following interfaces e 8 16 bit Hitachi SH 3 bus interface e 16 bit interface to 16 32 bit M
254. d to simplify the selection of input clock frequencies and the source of internal clocking signals For further information regarding clocking and clock sources refer to the 1D13504 Hardware Functional Specification document number X19A B 001 xx Note Changing clock values may modify or invalidate Panel or CRT settings Confirm all set tings on these two tabs after changing any clock settings CLKI These controls are used to inform 13A04DFGC of the clock frequency attached to CLKI Setting incorrect values will result in errors in the rest of the configu ration process Timing Use this control to set the CLKI frequency by selecting a frequency from the dropdown control If the dropdown does not contain the exact frequency then the frequency can be typed into the edit box 13504DCFG Driver Configuration Program S1D13504 Issue Date 01 10 26 X19A B 008 03 Page 14 Actual BUSCLK Timing Actual PCLK Source Divide Timing MCLK Source Divide Timing 1D13504 X19A B 008 03 Epson Research and Development Vancouver Design Center This field displays the CLKI frequency that 13A04DFG will use for configuration calculations These controls are used to inform 13A04DCFG of the clock frequency attached to BUSCLK Setting incorrect BUSCLK values result in errors in the rest of the configuration process Use this control to set the BUSCLK frequency by selecting a frequency from the dropdown control If the drop
255. d write to the LUT LUT Data 4 bit data value to write S1D13504 X19A G 002 07 Page 16 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center Bank Select Bits LUT banks are provided to give the application developer a choice of colors gray shades While the chosen color depth bpp may limit the simultaneous colors available the panel is capable of storing different combinations of colors in banks This is useful when an application developer chooses to set Bank 0 to low intensity colors and set Bank to high intensity The application can easily switch between low intensity output and high intensity output by using one register write Only two display modes support these bits 2 bpp and 8 bpp All other modes either bypass the LUT or have only Bank 0 starting at Index 00h In 2 bpp mode the 16 entry LUTs are logically split into 4 groups of 4 entries for each of R G B Bank 0 Indexes 00 03h Bank 1 Indexes 04 07h Bank 2 Indexes 08 OBh Bank 3 Indexes 0C OFh In 8 bpp mode the 16 entry LUTs are logically split into 2 groups of 8 entries for both Red and Green as follows Bank 0 Indexes 00 07h Bank 1 Indexes 08 OFh For Blue the 16 entry LUT is logically split into 4 groups of 4 entries as follows Bank 0 Indexes 00 03h Bank 1 Indexes 04 07h Bank 2 Indexes 08 OBh Bank 3 Indexes 0C OFh The bank select bits only affect data output CPU access to the LUT indexes are done directly as
256. d4 1vadd ory and adn ayez vp andur EN ng aes 1L recur sio 103138 MI 091 o z 20007 ur SNe Ed ar onst agnor 2 LIvdds EEEE 20001 9 Sivadd 103138 904 097 YOSLON STONIS YALHIANI has 0 ee oO Ager n t ZIVOdA K umddo1 Livdds MA e Olvadd sok K lovstlivads al oh 1 1 1 1 1 T 1 1 Epson Research and Development Vancouver Design Center Figure 7 3 SSU13504B00C Rev 2 0 Evaluation Board Schematics 3 of 5 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 I I I I y I 1 I L Y EE ENTES EE a Jequiny weuncog z s Vancouver Design Center Epson Research and Development oLnoz anee wounouangg SL oLnoL ango 2 219 ezo 129 o o note Net iS s104 viod loozlav s i ora ZN auva A zi ny ry 1380 st 0 Seay smog 1 LL uva s IN SL 59 YMWH SL s f8Yas gt an nto ons 0 AOL aNg9 s mitad aii an an mos s s masaa Ayy sav raV Qe dis K HAL o BE Zia gt gt tanvea s Tray oray s 23919 K Sv E Trav Tav EN Sav vay ora En ENT Te Tav Dev s zz EY yeaa K isa s az aano o Ham St si ung 0 S i Si ALIYM OM SL mito omit a3Au3S3u a3 u3834 T gt gt asau SL eo un
257. dle during vertical non display periods i e when REG OAh bit 7 1 or while in suspend mode For programming information see S1D13504 Programming Notes and Examples document number X19A G 002 xx MD Configuration Readback Register 0 REG 1Ch RO MD7 Status MD6 Status MD5 Status MD4 Status MD3 Status MD2 Status MD1 Status MDO Status MD Configuration Readback Register 1 REG 1 Dh RO MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 Status Status Status Status Status Status Status Status REG 1Ch bits 7 0 MD 15 0 Configuration Status REG 1Dh bits 7 0 These are read only status bits for the MD 15 0 pins configuration status at the rising edge of RESET See Table 5 8 Summary of Power On Reset Options on page 30 S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 103 Vancouver Design Center REG 1Eh GPIO Configuration Register 0 RW GPIO7 Pin IO Config GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIOO Pin 10 Config IO Config IO Config 10 Config IO Config IO Config bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O GPIO7 Pin IO Configuration When this bit 1 GPIO7 is configured as an output When this bit 0 default GPIO7 is config ured as an input Note the MD8 pin must be high at the rising edge of RESET
258. down does not contain the exact frequency then the frequency can be typed into the edit box This field displays the BUSCLK frequency that 13A04DFG will use for configuration calculations The PCLK controls allow adjustment of the pixel clock PCLK frequency PCLK source is always MCLK Set the MCKL divide ratio to derive PCLK Displays the PCLK frequency used by 13A04DCFG for configuration calculations The MCLK controls allow adjustment of the memory clock MCLK frequency MCLK source is always CLKI Set the CLKI divide ratio to derive MCLK Displays the MCLK frequency used by 13A04DCFG for configuration calculations 13504DCFG Driver Configuration Program Issue Date 01 10 26 Epson Research and Development Page 15 Vancouver Design Center Panel Tab Format2 Panel Data Width Mono Color Single Dual Half Frame Buffer Enable 51D13504 Configuration Utility Build 3 EA Panel A Regkters Polarit Panel Type fl l p 9 s Format 2 ed fe 9 9 FPFRAME 9 oi E y O Polarity jeso 232 Frame Rate 20 E Pixel Clock Panel Dimensions Predefined eed ml Panels En DOS Start pos Custom panel SSS TFT FPLINE _f Pulse width __ Pulse Width a SI Non Display TFT FPFRAME Period The S1D13504 supports many panel types This tab allows configuration of most panel settings such as panel dimensions type and timings Panel Type Selects between passive STN
259. dows CE 2 x Display Drivers 1D13504 Issue Date 01 05 25 X19A E 001 05 Page 12 Mode File 1D13504 X19A E 001 05 Epson Research and Development Vancouver Design Center A second variable which will affect the finished display driver is the register configurations contained in the mode file The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13504CFG EXE The display driver comes with example MODE tables By default only MODEO H is used by the display driver New mode tables can be created using the 13504CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13504 Width dword 280 Height dword 1E0 Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags
260. dword 2 Note that all dword values are in hexadecimal therefore 280h 640 1E0h 480 and 3Ch 60 The value for Flags should be 1 LCD 2 CRT or 3 both LCD and CRT When the display driver starts it will read these values in the registry and attempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the FIRST mode table in your list A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that controls these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request Windows CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 13 Vancouver Design Center Comments e The display driver is CPU independent allowing use of the driver for several Windows CE Platform Builder supported platforms e When using 13504CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number e At this time the drivers have been tested on the x86 CPUs and have been run w
261. e The SUSPEND pin is used either as an input to initiate Suspend mode or as a General Purpose Output that can be used to control the LCD backlight its power on polarity is selected by an MD configuration pin 2 7 Package and Pin Table 2 1 SID13504 Series Package list Name Package Pin 1D13504F00A QFP15 128 1D13504F01A TQFP15 128 1D13504F02A QFP20 144 Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Power Oscillator Management SH 3 BUS 3 z A21 p MIRE 2 A o N CSn gt cs 2 A 20 0 P AB 20 0 i i FPDAT 15 8 pup 7 0 D 15 0 le P DB 15 0 FPDATIZO Lovz 0 4 8 16 bit eid esr FPSHIFT FPSHIFT i BSH gt ES 1D13504 ROAR S RDAVHE FPFRAME FPFRAME Display RD gt ADE FPLINE gt FPLINE WEO P WEo proy mop WAITH be WAIT LCDPWR CEO P BUSCLK TB ak B a RESET gt RESET fog lt zas fo 8 1Mx16 FPM EDO DRAM Figure 3 1 Typical System Diagram SH 3 Bus 1Mx16 FPM EDO DRAM Power Oscillator Management MC68000 BUS 5 E Eco cet P Decoder O gt M R z a o N __ Decoder 0 CS a A 20 1 gt
262. e 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install Platform Builder 2 1x by running SETUP EXE from compact disk 1 4 Follow the steps below to create a Build Epson for x86 shortcut which uses the current Minshell project icon shortcut on the Windows desktop a Right click on the Start menu on the taskbar b Click on the item Explore and Exploring Start Menu window will come up c Under x winnt profiles all users start menu programs microsoft windows ce platform builder x86 tools find the icon Build Minshell for x86 d Drag the icon Build Minshell for x86 onto the desktop using the right mouse button Windows CE 2 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 7 Vancouver Design Center e Choose Copy Here f Rename the icon Build Minshell for x86 to Build Epson for x86 by right clicking on the icon and choosing rename g Right click on the icon Build Epson for x86 and click on Properties to bring up the Build Epson for x86 Properties window h Click on Shortcut and replace the string Minshell under the entry Target with Epson i Click on OK to finish 5 Create an EPSON project a Make an Epson directory under xAwincelpublic b Copy MAXALL and its sub directories x wince public maxall to the E
263. e Memory Type WE Control Memory Performance S1D13504 display buffer Note Memory Configuration Memory Clock Access Time S1D13504 X19A B 008 03 These settings must be configured based on the specifi cation of the DRAM being used For each of the following settings refer to the DRAM manufacturer s specification unless otherwise noted The current Memory Clock MCLK frequency is displayed here Selects the access time of the DRAM The S1D13504 evaluation boards use 50ns DRAM 13504DCFG Driver Configuration Program Issue Date 01 10 26 Epson Research and Development Vancouver Design Center Memory Type WE Control Refresh Time 1 MCLK R W Delay Memory Performance Suspend Mode Refresh CAS before RAS Self refresh No refresh 13504DCFG Driver Configuration Program Issue Date 01 10 26 Page 11 Selects the memory type either Extended Data Out EDO or Fast Page Mode FPM The S1D13504 evaluation boards use EDO DRAM Selects the WE control used for the DRAM DRAM uses one of two methods of control when writing to memory These methods are referred to as 2 CAS and 2 WE The S5U13504 evaluation boards use DRAM requiring the 2 CAS method This value represents the number of ms required to refresh 256 rows of DRAM Selects a delay during a read write transition for EDO DRAM This setting may be selected when MCLK is less than 30MHz These settings optimize the memory timings for bes
264. e 4 1 Typical Implementation of TX3912 to S1D13504 Direct Connection Figure 5 1 S1D13504 to TX3912 Connection using One IT8368E Figure 5 2 S1D13504 to TX3912 Connection using Two IT8368E Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Page 5 1D13504 X19A G 012 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD CRT Controller and the Toshiba TX3912 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Toshiba MIPS TX3912 Processor 1D13504 Issue Date 01 10 26 X19A G 012 05 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TX3912 1D13504 X19A G 012 05 The Toshiba MIPS TX3912 process
265. e 7 20 Single Monochrome 8 Bit Panel A C Timing 67 Table 7 21 Single Color 4 Bit Panel A C Timing 2 ee ee ee ee 69 Table 7 22 Single Color 8 Bit Panel A C Timing Format 1 o o 71 Table 7 23 Single Color 8 Bit Panel A C Timing Format 2 00 0 73 Table 7 24 Single Color 16 Bit Panel A C Timing _ e 75 Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 8 Epson Research and Development Vancouver Design Center Table 7 25 Dual Monochrome 8 Bit Panel A C Timing e 77 Table 7 26 Dual Color 8 Bit Panel A C Timing 79 Table 7 27 Dual Color 16 Bit Panel A C Timing saasaa aaa 81 Table 28 TEE A C Timing y cain died ke A See ee ERE BOOM eee BA 84 Table 7 29 CRTA C Timing ociosa eee ee N 87 Table 7 30 Generic Bus RAMDAC Read Write Timing e 88 Tables S1D13504 Addressing te a ee se gS eee ee ee ee pee tele eee ee de 89 Table 8 2 DRAM Refresh Rate Selection 000000000000 02 00004 90 Table 8 3 Panel Data Width Selection 0 0 020000 0000000000000 91 Table 8 4 FPLINE Polarity Selection 00 0 00 00 0000000000000 93 Table 8 5 FPFRAME Polarity Selection 0 0 000 000 0000 0000004 95 Table 8 6 Simultaneous Display Option Selection e 96 Table 8 7 Number of Bits Per Pixel Selection
266. e Date 01 11 06 Epson Research and Development Vancouver Design Center Table 7 8 EDO DRAM Write Timing Page 49 Symbol Parameter Min Typ Max Units t1 Memory clock period 25 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t2 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns Row address setup time REG 22h bits 3 2 00 2 45 t1 ns t3 Row address setup time REG 22h bits 3 2 01 2t1 ns Row address setup time REG 22h bits 3 2 10 1 45 t1 ns i Row address hold time REG 22h bits 3 2 00 or 10 0 45t1 1 ns Row address hold time REG 22h bits 3 2 01 ti 1 ns t5 Column address setup time 0 45t1 1 ns t6 Column address hold time 0 45t1 1 ns t7 CAS pulse width 0 45 t1 0 55t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 1t1 ns RAS precharge time REG 22h bits 3 2 00 2ti 1 ns t10 RAS precharge time REG 22h bits 3 2 01 1 45t1 1 ns RAS precharge time REG 22h bits 3 2 10 1t1 1 ns REC nora bits 3 2 00 or 10 a eu E a PER E a bits 3 2 00 or 10 pine MH ie RAS to CAS delay time REG 22h bits 3 2 01 1 45t1 2 1 55 t1 ns t12 Write command setup time 0 45 t1 1 ns t13 Write command hold time 0 45 t1 ns t14 Write Data setup time 0 45 t1 3 ns t15 Write Data hold time
267. e Single panel single drive displays e Dual panel dual drive displays e Direct support for 9 12 bit TFT 18 bit TFT is sup ported up to 64K color depth 16 bit data e External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel data bus e Simultaneous display of CRT and 4 8 bit passive or 9 bit TFT panels regardless of resolution e Maximum resolution of 800x600 pixels at a color depth of 16 bpp Display Modes e 1 2 4 8 16 bit per pixel bpp support on LCD e 1 2 4 8 bit per pixel bpp on CRT e Up to 16 shades of gray using FRM on monochrome passive LCD panels e Up to 4096 colors on passive LCD panels e Up to 64K colors on active matrix TFT LCD in 16 bpp modes e Split Screen Display allows two different images to be simultaneously displayed e Virtual Display Support displays images larger than the panel size through the use of panning e Double Buffering multi pages provides smooth ani mation and instantaneous screen update e Acceleration of screen updates by allocating full display buffer bandwidth to CPU Clock Source e Single clock input for both pixel and memory clocks e Memory clock can be input clock or input clock 2 providing flexibility to use CPU bus clock as input e Pixel clock can be memory clock or memory clock 2 memory clock 3 or memory clock 4 Power Down Modes e Two power down modes one software one hardware e LCD Power Sequencing General Purpo
268. e disabled If suspend mode CBR refresh is selected all internal modules and clocks except the Memory I F are shut down If suspend mode self refresh or no refresh is selected all internal modules and clocks are shut down 13 2 Software Suspend Register read write allowed except for RAMDAC registers Memory read write disallowed LCD outputs are forced low see Note 1 of Section 13 4 Pin States in Power Save Modes on page 128 LCDPWR forced to Off state CRT outputs are disabled If suspend mode CBR refresh is selected all internal modules and clocks except the Host Bus I F and the Memory I F are shut down If suspend mode self refresh or no refresh is selected all internal modules and clocks except the Host Bus I F are shut down Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 128 13 3 Power Save Mode Function Summary Table 13 1 Power Save Mode Function Summary Epson Research and Development Vancouver Design Center Power Save Mode PSM Function Normal Software Hardware Active Suspend Suspend Display Active Yes No No Register Access Possible Yes Yes 1 No Memory Access Possible Yes No No Host Bus Interface Running Yes Yes No Memory Interface Running Yes No 2 No 2 Note 1 except for RAMDAC registers 2 Yes if CBR suspend mode refresh is selected 13 4 Pin States in Power Save Modes Table
269. e ee Ok te pelea 62 7A2Q Suspend Timing 2 he Sees rr ba eee A See Beet be as Bae 63 7 4 3 Single Monochrome 4 Bit Panel Timing e 64 744 Single Monochrome 8 Bit Panel TiMing e o 66 74 5 Single Color 4 Bit Panel Timing 2 2 2 e 68 74 6 Single Color 8 Bit Panel Timing Formatl o e 70 74 7 Single Color 8 Bit Panel Timing Format2 e 72 74 8 Single Color 16 Bit Panel Timing e 74 74 9 Dual Monochrome 8 Bit Panel Timing a 76 7 4 10 Dual Color 8 Bit Panel Timing e 78 74 11 Dual Color 16 Bit Panel Timing 00 2 0 0000 80 74 12 16 Bit TFT Panel Timing sereia sA a E SR Se eR Ae ea es 82 TA13 CRY IMNE he Ge Se cep hee bE SE ed A Peed e pee be EB ed 85 74 14 External RAMDAC Read Write Timing e 88 8 Registers gt k ea a a o dd a a ds E 89 8 1 Register Mapping 89 8 2 Register Descriptions 89 8 2 1 Revision Code Register 0 0 2 2 ee 89 8 2 2 Memory Configuration Registers 2 0 020000 0000000000004 90 8 2 3 Panel Monitor Configuration Registers 0 0 00000000004 91 8 2 4 Display Configuration Registers 96 8 2 5 Clock Configuration Register 2 0 2 2 0 0 0 0 0000000020004 101 8 2 6 Power Save Configuration Registers 2 2 0 000000000000 004 101 8 2 7 Miscellaneous Registers
270. e or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Wind River UGL v1 2 Display Drivers X19A E 003 02 Issue Date 01 02 01 Epson Research and Development Page 3 Vancouver Design Center Wind River UGL v1 2 Display Drivers The Wind River UGL v1 2 display drivers for the S1D13504 Color Graphics LCD CRT Controller are intended as reference source code for OEMs developing for Wind River s UGL v1 2 The drivers provide support for both 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13504 Source code modification is required to provide a smaller more efficient driver for mass production The UGL display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13504DCFG This design allows for easy customization of display type clocks addresses etc by OEMs For further infor mation on 13504DCFG see the 3504DCFG Configuration Program User Manual document number X19A B 008 xx This document and
271. e out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines DO through D15 are used and address line A30 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 1 3 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 Do not increment address bits A28 and A29 between successive transfers the addressed device must increment these address bits internally If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA and the processor will revert to normal bus cycles for the remaining data transfers 1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Page 11 Vancouver Design Center Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral dev
272. e time REG 22h bits 3 2 10 1t1 1 ns REC 22 bia Sp 8 2 00 or 10 e em ns i E on bits 3 2 00 or 10 ne aH ns RAS to CAS delay time REG 22h bits 3 2 01 1 45t1 2 1 55 t1 ns t9 Read Data turn off delay from WE 0 ns ag Write Data delay from WE REG 22h bit 7 0 1 45 t1 ns Write Data delay from WE REG 22h bit 7 1 0 45 t1 ns Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 52 Epson Research and Development Vancouver Design Center 7 3 4 EDO DRAM CAS Before RAS Refresh Timing tl Memory a Clock E 2 t3 gt RAS it CAS NA 2 a 4 pid b gt t6 Figure 7 10 EDO DRAM CAS Before RAS Refresh Timing Table 7 10 EDO DRAM CAS Before RAS Refresh Timing Symbol Parameter Min Typ Max Units t1 Memory clock period 25 ns b RAS to CASH precharge time REG 22h bits 3 2 00 1 45 t1 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 0 45 t1 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t3 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 tt ns CAS precharge time REG 22h bits 3 2 00 2t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 11 ns E CAS setup time REG 22h bits 3 2 00 or 10 0 45t1 2 ns CAS setup time REG 22h bits 3 2 01 1t1 2
273. e to the S1D13504 when a CRT is also attached 13504BMP Demonstration Program S1D13504 Issue Date 01 02 01 X19A B 006 04 Page 4 Epson Research and Development Vancouver Design Center Program Messages 1D13504 X19A B 006 04 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL can only manage 10 devices simultaneously ERROR Could not register S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program ERROR Did not detect S1D13504 The HAL was unable to read the revision code register on the S1D13504 Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly 13504BMP Demonstration Program Issue Date 01 02 01 EPSON 1D13504 Color Graphics LCD CRT Controller 13504PWR Software Suspend Power Sequencing Utility Document Number X19A B 007 04 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected u
274. ection using ITE IT8368E 1D13504 X19A G 012 05 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Page 21 Vancouver Design Center 6 Software Test utilities and display drivers are available for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CKG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the Toshiba MIPS TX3912 Processor S1D13504 Issue Date 01 10 26 X19A G 012 05 Page 22 Epson Research and Development Vancouver Design Center 7 References 7 1 Documents e Toshiba America Electrical Components Inc TX3905 12 Specification e Epson Research and Development Inc D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 xx e Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 7 2 Document Sources e Toshiba America Elect
275. ed In 8 bpp mode the 16 position Red LUT is arranged into two 8 position banks Only bit 0 of these two bits controls which bank is currently selected These bits have no effect in 1 bpp 4 bpp 15 16 bpp mode or all monochrome modes bit 3 2 Blue Bank Select Bits 1 0 In both 2 bpp and 8 bpp modes the 16 position Blue LUT is arranged into four 4 position banks These two bits control which bank is currently selected These bits have no effect in 1 bpp 4 bpp 15 16 bpp mode or all monochrome modes bits 1 0 Green Bank Select Bits 1 0 In 2 bpp mode the 16 position Green LUT is arranged into four 4 position banks These two bits control which bank is currently selected In 8 bpp mode the 16 position Green LUT is arranged into two 8 position banks Only bit 0 of these two bits controls which bank is currently selected These bits have no effect in 1 bpp 4 bpp and 15 16 bpp modes 8 2 9 External RAMDAC Control Registers Note 1 Ina Little Endian architecture the RAMDAC should be connected to the low byte of the CPU data bus and the following registers are accessed at the lower address given for each register 28h 2Ah 2Ch and 2Eh In a Big Endian architecture the RAMDAC should be connected to the high byte of the CPU data bus and the following registers are accessed at the higher address given for each register 29h 2Bh 2Dh and 2Fh 2 When accessing the External RAMDAC Control registers with eit
276. ed in SOURCES file or new OEM specific code must be added to the display driver to save off screen data to system memory when the system is suspended and restored when resumed If off screen data is used provided that the OEM has provided code to save off screen data when the system suspends additional code must be added to the display driver s surface allocation routine to prevent the display driver from allocating the main memory save region in display memory When WinCE OS attempts to allocate a buffer to save the main display data WinCE OS marks the allocation request as preferring display memory We believe this is incorrect Code must be added to prevent this specific allocation from being allocated in display memory it MUST be allocated from system mem ory Since the main display data is copied to system memory on suspend and then simply copied back on resume this mode is FAST but not as fast as mode 0 Windows CE 3 x Display Drivers Issue Date 01 05 08 Epson Research and Development Page 15 Vancouver Design Center c PORepaint 2 e This mode tells WinCE to not save the main display data on suspend and causes WinCE to REPAINT the main display on resume e This mode is used if display memory power is going to be turned off when the system is suspended and there is not enough system memory to save the im age e Any off screen data in display memory is LOST and since there is insuffi cient system memor
277. een asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Interfacing to the Motorola MCF5307 Coldfire Microprocessor Issue Date 01 02 02 Epson Research and Development Page 9 Vancouver Design Center The following figure illustrates a typical memory read cycle on the MCF5307 system bus scko LJ LJ LJ LI LI LI LI U TS TA TP A 31 0 X l X RW XX SIZ 1 0 TT 1 0 X DIst 0 XXX AXA AI X Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 MCF5307 Memory Read Cycle The following figure illustrates a typical memory read cycle on the MCF5307 system bus sex _ LI LI LJ LI LI LUI LI TS TA T A 31 0 i i x R W SIZ 1 0 TT 1 0 D 31 0 0000 valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory Write Cycle Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 011 07 Page 10 Epson Research and Development Vancouver Design Center 2 1 3 Burst Cycles Burst cycles are very similar to normal cycles except they occur as a series of four back to back 32 bit memory reads or writes with the TIP Transfer In Progress output asserted co
278. ef which lists various panel manufacturers recommended settings If the file panels def is present in the same directory as 13504dcfg exe the settings for a number of predefined panels are available in the drop down list If a panel is selected from the list 13504DCFG loads the predefined settings contained in the file 1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Epson Research and Development Vancouver Design Center Page 19 Simultaneous Display Options CRT Tab 51D13504 Configuration Utility Build 3 CRT Display Dimensions 640x480 60Hz f Interlace F Line doubling Even sca The CRT tab configures settings specific to the CRT display device CRT Display Dimensions Simultaneous Display Options Note Select the CRT resolution and frame rate from the drop down list The available options vary based on selec tions made in the Clocks tab If no selections are available the CRT pixel clock settings on the Clocks tab must be changed When both the LCD and CRT are operating in simulta neous display mode a method of displaying both images must be selected based on the vertical resolution height of the images If both displays are the same resolution select Normal Otherwise refer to the S1D13504 Hardware Functional Specification document number X19A B 001 xx for information on selecting the best option For CRT operations 13504DCFG supports VESA timings
279. egistered device ID pDac pointer to an array of BYTE dac 256 3 dac x 0 RED component dac x 1 GREEN component dac x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGetDacEntry int device BYTE index BYTE pEntry Description Reads one DAC entry Parameter device registered device ID index index to DAC entry 0 to 255 pEntry pointer to an array of BYTE entry 3 entry x 0 RED component entry x 1 GREEN component entry x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGetLut int device BYTE pLut Description Reads the entire LUT into an array Parameter device registered device ID pLut pointer to an array of BYTE lut 16 3 lut x 0 RED component lut x 1 GREEN component lut x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 48 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center int seGetLutEntry int device BYTE index BYTE pEntry Description Reads one LUT entry Parameter device registered device ID index index to LUT entry 0 to 15 pEntry pointer to an array of BYTE entry 3
280. enter 3 2 Generic MPU Host Bus Interface Signals 1D13504 X19A G 013 03 The interface requires the following signals BUSCLK is a clock input which is required by the 1D13504 host bus interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset M R memory register may be considered an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the 1D13504 is accessed by the host CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RDO and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13504 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13504 may occur asynchronously t
281. entry x 0 RED component entry x 1 GREEN component entry x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seSetDac int device BYTE pDac Description Writes the entire DAC from an array into the DAC registers Parameter device registered device ID pDac pointer to an array of BYTE dac 256 3 dac x 0 RED component dac x 1 GREEN component dac x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seSetDacEntry int device BYTE index BYTE pEntry Description Writes one DAC entry Parameter device registered device ID index index to DAC entry 0 to 255 pEntry pointer to an array of BYTE entry 3 entry x 0 RED component entry x 1 GREEN component entry x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 49 Vancouver Design Center int seSetLut int device BYTE pLut Description Writes the entire LUT from an array into the LUT registers Parameter device registered device ID pLut pointer to an array of BYTE lut 16 3 lut x 0 RED component lut x 1 GREEN component lut x 2 BLUE component Return Value ERR_OK
282. equires the following signals BUSCLK is a clock input which is required by the S1D13504 host bus interface It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset M R memory register may be considered an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the S1D13504 is accessed by the host CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RDO and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13504 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13504 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13504 interna
283. er REG OEh Screen 1 Line Compare Register 0 RW Screen 1 Line Compare Bit 7 Screen 1 Line Compare Bit 6 Screen 1 Line Compare Bit 5 Screen 1 Line Compare Bit 4 Screen 1 Line Compare Bit 3 Screen 1 Line Compare Bit 2 Screen 1 Line Compare Bit 1 Screen 1 Line Compare Bit 0 REG OFh Screen 1 Line Compare Register 1 RW n a n a n a n a n a n a Screen 1 Line Compare Bit 9 Screen 1 Line Compare Bit 8 REG 0Eh bits 7 0 REG OFh bits 1 0 1D13504 X19A A 002 19 Screen 1 Line Compare Bits 9 0 In split screen mode the panel is divided into screen 1 and screen 2 with screen 1 above screen 2 These registers form a 10 bit value that specify the screen 1 size in 1 line resolution The maximum screen vertical size is 1024 lines Screen 2 is visible only if the screen line compare is less than the vertical panel size The starting address for screen 1 is given by the Screen 1 Display Start Address registers REG 10h REG 1 1h REG 12h The starting address for screen 2 is given by the Screen 2 Display Start Address registers REG 13h REG 14h REG 15h For normal operation no split screen this register must be set greater than the vertical display height REG 08h and REG 09h e g set to 3FFh For split screen on a single panel Split screen 1 vertical size in number of lines ContentsOfThisRegister
284. er pixels_per_line pixels_per_word Example 2 Determine the offset value required for 800 pixels at a color depth of 8 bpp A color depth of 8 bpp means each pixel requires one byte therefore each word contains two pixels offset pixels_per_line pixels_per_word 800 2 400 0x190 words Register 17h would be set to 0x01 and register 16h would be set to 0x90 Example 3 Program the Memory Address Offset Registers to support a 16 color 4 bpp 640x480 virtual display on a 320x240 LCD panel To create a virtual display the offset registers must be programmed to the horizontal size of the larger virtual image After determining the amount of memory used by each line do a calculation to see if there is enough memory to support the desired number of lines 1 Initialize the 1D13504 registers for a 320x240 panel See Section 2 2 Register Initialization on page 9 2 Determine the number of words required per line the offset In this case we want a width of 640 pixels and there are four pixels to every word offset pixels_per_line pixels_per_word 640 4 160 words OxAO words 3 Check that we have enough memory for the required virtual height Each line uses 160 words and we need 480 lines 160 480 for a total of 76 800 words less than the minimum supported memory size of 512K bytes It is safe to continue with these values Programming Notes and Examples Issue Date 01 02 01 Epson Research and Deve
285. er HFB is active Note This register should be programmed only during initialization and never changed after that However it still must be programmed BEFORE the HFB starts to R W the memory see Register Initialization in Section 2 1 5 Programming Notes and Examples 1D13504 X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 9 Vancouver Design Center 2 1 4 REG 1B bit 0 Half Frame Buffer Disable This bit must not be changed while the HFB is active This register might be disabled during normal operation for two reasons 1 to increase bandwidth for simultaneous display 2 to test all available memory To disable the HFB see Section 2 3 Disabling the Half Frame Buffer Sequence on page 11 Note The HFB is enabled after RESET default condition It will start to Read and Write the DRAM if the DUAL bit set Horizontal resolution gt 0 HFB enabled default power on state 2 1 5 REG 23 Display FIFO This register can be asynchronously enabled disabled Note The Display FIFO starts to access DRAM after RESET 2 2 Register Initialization 2 2 1 Initialization Sequence To initialize the S1D13504 after POWER ON or a HARDWARE RESET do the following 1 Enable the host interface REG 1Bh bit 7 0 2 Disable the display FIFO REG 23h bit 7 1 after stopping FIFO accesses to the DRAM 3 Set memory type REG 01h bit 0 4 Set performance register REG 22h 5 Set dual
286. er Design Center 7 3 8 FPM DRAM Read Write Timing t1 Memory Clock t2 4 gt t3 le t4 t5 1 16 MA R Ci C2 C3 RAS CAS Y WE a t7 a t8 gt t10 gt E MD Read d1 d2 MD Write d3 Figure 7 14 FPM DRAM Read Write Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 59 Vancouver Design Center Table 7 14 FPM DRAM Read Write Timing Symbol Parameter Min Typ Max Units t1 Memory clock 40 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t2 Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns Row address setup time REG 22h bits 3 2 00 2t1 ns t3 Row address setup time REG 22h bits 3 2 01 1 45 t1 ns Row address setup time REG 22h bits 3 2 10 111 ns i Row address hold time REG 22h bits 3 2 00 or 10 t1 1 ns Row address hold time REG 22h bits 3 2 01 0 45 t1 1 ns t5 Column address set up time 0 45t1 1 ns t6 Column address hold time 0 45t1 1 ns RAS precharge time REG 22h bits 3 2 0 2ti 1 ns t7 RAS precharge time REG 22h bits 3 2 01 1 45t1 1 ns RAS precharge time REG 22h bits 3 2 10 1t1 1 ns REC 22 bia aoe 3 2 00 or 10 Deis B ne t8 PESO
287. erface pins are mapped to each host bus interface according to the following table Table 4 1 CPU Interface Pin Mapping Pin Names Generic Hitachi SH 3 MegaK Bus 1 MCSEK Bus 2 AB20 A20 A20 A20 A20 AB19 A19 A19 A19 A19 AB18 A18 A18 A18 A18 AB17 A17 A17 A17 A17 AB 16 13 A 16 13 A 16 13 A 16 13 A 16 13 AB 12 1 A 12 1 A 12 1 A 12 1 A 12 1 ABO Ao Ao LDS AO DB 15 8 D 15 0 D 15 8 D 15 8 D 31 24 DB 7 0 D 7 0 D 7 0 D 7 0 D 23 16 WE1 WE1 WE1 UDS DS M R External Decode CS External Decode BUSCLK BCLK CKIO CLK CLK BS Connected to IOVpp BS AS AS RD WR RD1 RD WR R W R W RD RDO RD Connected to OVpp SIZ1 WEO0 WEO0 WEO0O Connected to IOVpp SIZO WAIT WAIT TRE 4 DTACKH DSACK1 RESET RESET RESET RESET RESET Note 1 AO for these busses is not used internally by the S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual 1D13504 Issue Date 2002 12 02 X19A G 014 01 Page 16 Epson Research and Development 4 2 2 CPU Bus Connector Pin Mapping 1D13504 X19A G 014 01 The pinouts for Connector H1 are listed in the following table Table 4 2 CPU BUS Connector H1 Pinout Vancouver Design Center Pin No Function 1 Connected to DBO of the S1D13504 2 Connected to DB1 of the
288. es register initialization 13504SHOW cannot show a greater color depth than the display allows The PC must not have more than 12M bytes of system memory when used with the S53U13504B00C board Follow simultaneous display guidelines for correct simultaneous display operation To determine if the CRT will operate correctly when using a dual panel refer to the Maximum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing e A CRT cannot show 15 or 16 bits per pixel Do not attach a panel with a 16 bit interface to the S1D13504 when a CRT is also attached Program Messages S1D13504 X19A B 002 05 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL can only manage 10 devices simultaneously ERROR Could not register S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program ERROR Did not detect S1D13504 The HAL was unable to read the revision code register on the S1D13504 Ensure that the S1D13504 hardware is installed a
289. esearch and Development Vancouver Design Center 3 2 Generic MPU Host Bus Interface Signals 1D13504 X19A G 005 09 The interface requires the following signals BUSCLK is a clock input which is required by the 1D13504 host bus interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the CPU address and data bus respectively The hardware engineer must ensure that MD4 selects the proper endian mode upon reset M R memory register may be considered an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the 1D13504 is accessed by the host CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RDO and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13504 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses
290. f the input clock frequency When this bit 0 the memory clock frequency is equal to the input clock frequency bits 1 0 PCLK Divide Select Bits 1 0 These bits determine the amount of divide from the memory clock to generate the pixel clock PCLK Table 8 9 PCLK Divide Selection PCLK Divide Select Bits 1 0 MCLK PCLK Frequency Ratio 00 1 01 2 10 3 11 4 See Section 11 2 Frame Rate Calculation on page 119 for selection of PCLK frequency 8 2 6 Power Save Configuration Registers Power Save Configuration Register REG 1Ah RW Suspend Suspend Software n a n a n a n a ee fa Refresh Refresh Suspend Select Bit 1 Select BitO Mode Enable bit 3 LCD Power Disable When this bit 1 the LCDPWR output is directly forced to the Off state The LCDPWR On Off state is configured by MD 10 at the rising edge of RESET When this bit 0 the LCDPWR output is controlled by the panel on off sequencing logic See Table 5 8 Summary of Power On Reset Options on page 30 bits 2 1 Suspend Refresh Select Bits 1 0 These bits specify the type of DRAM refresh to use in Suspend mode Table 8 10 Suspend Refresh Selection Suspend Refresh Select Bits 1 0 DRAM Refresh Type 00 CBR Refresh 01 Self Refresh 1x No Refresh Note These bits should not be changed when suspend mode is enabled bit O Software Suspend Mode Enable When this bit 1 software sus
291. face mode supported by the S1D13504 and was chosen to implement this interface due to the simplicity of its timing Epson Research and Development Vancouver Design Center The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debugging 3 1 Generic MPU Host Bus Interface Pin Mapping 1D13504 X19A G 007 08 The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping Elect Generic MPU AB 20 1 A 20 1 ABO AO DB 15 0 D 15 0 WE1 WE1 M R External Decode CS External Decode BUSCLK BCLK BS Connect to lO Vpp RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the NEC VR4102 Microprocessor Issue Date 01 10 26 Epson Research and Development Page 11 Vancouver Design Center 3 2 Generic MPU Host Bus Interface Signals The interface r
292. falling edge read cycle 0 ns t15 UDS and LDS high to D 15 0 invalid high impedance read 2 11 ne cycle t16 AS high setup to CLK 3 ns 1 Ifthe S1D13504 host interface is disabled the timing for DTACK driven high is relative to the falling edge of AS or the first positive edge of CLK after A 20 1 and M R become val id whichever occurs later 2 Ifthe S1D13504 host interface is disabled the timing for D 15 0 driven is relative to the fall ing edge of UDS LDS or the first positive edge of CLK after A 20 1 and M R become val id whichever occurs later Hardware Functional Specification Issue Date 01 11 06 1D13504 X19A A 002 19 Page 40 7 1 3 MC68K Bus 2 Interface Timing e g MC68030 Epson Research and Development Vancouver Design Center CLK f A 20 0 SIZ 1 0 M R CS AS DS R W DSACK1 D 31 16 write D 31 16 read t1 t2 t3 s t4 t11 t10 aa t12 t15 t13 lt mE S1D13504 X19A A 002 19 Figure 7 3 MC68K Bus 2 Interface Timing Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Table 7 3 MC68K Bus 2 Interface Timing Page 41 Symbol Parameter Min Max Units t1 Clock period 30 ns
293. ffer aliased another 3 times over 48M bytes Since the TX3912 control signal CARDREG is ignored the S1D13504 takes up the entire PC Card slot 1 configuration space The address range is software compatible with both ITE IT8368E implementations e 0900 0000h S1D13504 registers aliased 131 072 times at 64 byte intervals over 8M bytes e 0980 0000h S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M bytes Note If aliasing is undesirable additional decoding circuitry must be added Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 4 3 S1D13504 Hardware Configuration Page 13 The S1D13504 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Specification document number X19A A 002 xx The partial table below shows those configuration settings relevant to the direct connection implementation Table 4 1 SID13504 Configuration for Direct Connection value on this pin at rising edge of RESET is used to configure 1 0 0 S1D13504 Pin Name 1 MDO 8 bit host bus interface MD1 MD2 See Host Bus Selection table below MD3 MD4 MD5 WAIT signal is active high See Host Bus Selection table below Big Endian ae required configuration for direct connection w
294. fication Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Page 23 Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin FOOA FOIA F02A Driver Reset 0 Value Description WEO0 10 CS Hi Z This pin has multiple functions e For SH 3 mode this pin inputs the write enable signal for the lower data byte WEO e For MC68K Bus 1 this pin must be tied to IO Vpp e For MC68K Bus 2 this pin inputs the bus size bit 0 SIZO e For Generic Bus this pin inputs the write enable signal for the lower data byte WEO See Table 5 9 Host Bus Interface Pin Mapping on page 31 WAIT O 13 15 TS2 The active polarity of the WAIT output is configurable on the rising edge of RESET see Section 5 5 Summary of Configuration Options on page 30 This pin has multiple functions e For SH 3 mode this pin outputs the wait request signal WAIT MD5 must be pulled low during reset by the internal pull down resistor e For MC68K Bus 1 this pin outputs the data transfer acknowledge signal DTACK MD5 must be pulled high during reset by an external pull up resistor e For MC68K Bus 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 MD5 must be pulled high during reset by an external pull up resistor e For Generic Bus this pin outputs the wait signal WAIT MD5 must be pulled low during reset by
295. fire Microprocessor X19A G 011 07 Issue Date 01 02 02 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD CRT Controller and the Motorola MCF5307 Coldfire microprocessor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs Oerd epson com Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 01 1 07 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The MCF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section provides an overview of the operation of the MCF5307 bus in order to establish interface requirements The MCF5307 microprocessor family uses a synchronous add
296. for WAIT driven low is relative to the falling edge of CS and RDO RD1 WEO WE1 or the first positive edge of BCLK after A 20 0 and M R become valid whichever occurs later 2 Ifthe S1D13504 host interface is disabled the timing for D 15 0 driven is relative to the fall ing edge of RDO RD 1 or the first positive edge of BCLK after A 20 0 and M R become valid whichever occurs later Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 44 Epson Research and Development Vancouver Design Center 7 1 5 Generic MPU Interface Asynchronous Timing TBCLK A 20 0 A M R Valid tl CS Pa B RDO RD1 WEO WE1 5 t4 Hi Z Hi Z WAIT 6 7 Hi Z Hi Z D 15 0 write Valid 18 t9 t10 D 15 0 read Hi Z Valid mz Figure 7 5 Generic MPU Interface Asynchronous Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Table 7 5 Generic MPU Interface Asynchronous Timing Page 45 Symbol Parameter Min Max Units TBCLK Bus clock period 25 ns t1 RDO RD1 WE0 WE1 low to CS low 4 ns t2 A 20 0 M R valid to RDO RD1 WE0 WE1 low 0 ns t3 RDO RD1 WE0 WE1 high to A 20 0 CS M R invalid and CS high 0 ns 14 CS low to WAIT driven low 1 ns t5 RDO RD1 WEO WE1
297. form cepc driv ers display S 1D13504 sources In SOURCES there is a line which when uncom mented will instruct Windows CE to use off screen display memory if sufficient display memory is available CDEFINES CDEFINES DEnablePreferVmem In the file PROJECT REG under CE 3 0 there is a key called PORepaint search the Windows CE directories for PROJECT REG PORepaint is relevant when the Sus pend state is entered or exited PORepaint can be set to 0 1 or 2 as described below a PORepaint 0 This mode tells Windows CE not to save or restore display memory on sus pend or resume Since display data is not saved and not repainted this is the FASTEST mode Main display data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running Off screen data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running This mode cannot be used if power to the display memory is turned off b PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display data to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is LOST when suspended Therefore off screen memory usage must either be disabled in the display driver i e EnablePreferVmem not defin
298. g on page 32 for summary This pin has multiple functions For asymmetrical 2M byte DRAM this is memory address bit Hi Z 10 MA10 MA10 IO 42 48 C TS1 a ural For symmetrical 2M byte DRAM and all 512K byte DRAM p this pin can be used as general purpose IO GPIO1 See Table 5 10 Memory Interface Pin Mapping on page 32 for summary This pin has multiple functions e For asymmetrical 2M byte DRAM this is memory address bit HZ 11 MA11 MA11 IO 44 50 C TS1 Out utol For symmetrical 2M byte DRAM and all 512K byte DRAM p this pin can be used as general purpose IO GPIO2 See Table 5 10 Memory Interface Pin Mapping on page 32 for summary 1 When configured as IO pins Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 26 5 4 3 LCD Interface Epson Research and Development Vancouver Design Center Table 5 3 LCD Interface Pin Descriptions Pin z Reset Bad Pin Name Type FOOA cae Driver 0 Value Description FIA FPDAT 8 0 O 88 82 75 98 92 85 CN3 Output O Panel Data These pins have multiple functions Panel Data for 16 bit panels FPDAT 15 9 O 95 89 105 99 CN3 Output O e Pixel Data for external RAMDAC support See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 FPFRAME O 69 79 CN3 Output O Frame Pulse FPLINE O 70 80 CN3 Output O Line Pulse FPSH
299. g the display driver refer to the descriptions in the file MODEO H for the default settings of the driver If the default does not match the configuration you are building for then MODEO H will have to be regenerated with the correct informa tion Use the program 13504CFG to generate the header file For information on how to use 13504CFG refer to the 13504CFG Configuration Program User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODEO H in x wince platform cepc drivers display S 1D 13504 replacing the original configura tion file Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotation information in MODE H PLAT FORM REG is located in x wince platform cepc files For example the display driver section of PLATFORM REG should be as follows when using a 640x480 LCD panel with a color depth of 8 bpp in Swivel View 0 landscape mode Default for EPSON Display Driver 640x480 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13504 Width dword 280 Height dword 1E0 Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 Delete all the files in wince release directory an
300. ge on the 640x240 LCD will appear to be squashed though text will be readable Even Scan Only the 640x480 image on the CRT is normal The LCD 640x240 only receives the even scan lines The image on the LCD does not flicker but it may be hard to read text Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 97 Vancouver Design Center bits 4 2 Number of Bits Per Pixel Select Bits 2 0 These bits select the number of bits per pixel bpp for the displayed data Note 15 and 16 bpp modes bypass the LUT and are supported as 12 bpp on passive panels and 15 16 bpp on TFT panels These modes are not supported on CRT See Figure 10 2 15 16 Bit Per Pixel Format Memory Organization on page 116 for a description of passive panel support Table 8 7 Number of Bits Per Pixel Selection Number Of Bits Per Pixel Select Bits 2 0 Number of Bits Per Pixel 000 1 001 2 010 4 011 8 100 15 101 16 110 111 Reserved bit 1 CRT Enable This bit enables the CRT control signals Note REG 02h bit 1 must 0 when in CRT only mode bit O LCD Enable This bit enables the LCD control signals Programming this bit from a 0 to a starts the LCD power on sequence Programming this bit from a 1 to a 0 starts the LCD power off sequence Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 98 Epson Research and Development Vancouver Design Cent
301. gives the system designer full flexibility in choosing the appropriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Page 17 Vancouver Design Center 5 2 Hardware Description Using Two IT8368E s The following implementation uses a second IT8368E not in VGA mode in place of an address latch The pins LHA23 and LHA 20 13 provide the latch function instead PR31500 PR31700 1D13504 A 12 0 gt AB 12 0 ENDIAN gt V gt AB 20 13 D 31 24 DB 7 0 D 23 16 gt DB 15 8 System RESET gt RESET VoD pull up CARDXWAIT e i WAIT DCLKOUT LHA23 gt WR Clock divider gt IT8368E Ao Oscillator gt BUSCLK See text LHA 20 13 CLKI LHA23 10 Vop t____ BS IT8368E LHA23 MFIO10 WE1 LHA22 MFIO9 gt WEO LHA21 MFIO8 gt RD1F LHA20 MFIO7 RDO LHA19 MFIO6 f m r CS Chip Select Logic Notes The Chip Select Logic shown above is necessary t
302. gned to operate in a personal computer PC DOS environment and must be configured to work with your display hardware Consult documentation for the program 13504CFG EXE which can be used to configure 13504BMP 13504BMP is not supported on non PC platforms Installation Copy the file 13504BMP EXE to a directory that is in the DOS path on your hard drive Usage At the prompt type 13504bmp bmp file a lcd crt Where bmp file displays the bmp format file a automatically exits after 5 seconds 1lcd displays the image on a LCD crt displays the image on a CRT displays the Help screen Comments e 13504BMP only currently decodes Windows BMP format images e The PC must not have more than 12M bytes of memory when used with the S5U13504B00C board e Follow simultaneous display guidelines for correct simultaneous display operation e To determine if the CRT will operate correctly when using a dual panel refer to the Maximum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx e When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu e When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing e A CRT cannot show 15 or 16 bits per pixel e Do not attach a panel with a 16 bit interfac
303. gram of MC68328 to S1D13504 Interface MC68000 Bus 1 Interface Mode 11 Figure 4 2 Block Diagram of MC68328 to S1D13504 Interface Generic Interface Mode Interfacing to the Motorola MC68328 Dragonball Microprocessor S1D13504 Issue Date 01 10 26 X19A G 013 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to implement an interface between the S1D13504 Color Graphics LCD CRT Controller and the Motorola MC68328 Dragonball Microprocessor By implementing a dedicated display refresh memory the S1D13504 can reduce system power consumption improve image quality and increase system performance as compared to the Dragonball s on chip LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13504
304. h low note 5 t10 horizontal display period note 6 t11 FPLINE setup to FPSHIFT falling edge 0 45 Ts 112 FPFRAME falling edge to FPLINE falling edge note 7 phase difference t13 DRDY to FPSHIFT falling edge setup time 0 45 Ts t14 DRDY pulse width note 8 t15 DRDY falling edge to FPLINE falling edge note 9 t16 DRDY hold from FPSHIFT falling edge 0 45 Ts t17 FPLINE Falling edge to DRDY active note 10 250 Ts Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 t6min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts t7min REG O7h bits 3 0 1 8 Ts t8 min REG O9h bits 1 0 REG O8h bits 7 0 1 REG OAh bits 5 0 1 lines t9min REG OCh bits 2 0 1 lines 10min REG 04h bits 6 0 1 8 Ts t12min REG 06h bits 4 0 1 8 Ts t14 min REG 04h bits 6 0 1 8 Ts 15min REG O6h bits 4 0 1 1 8 2 Ts 0 t17min REG O5h bits 4 0 8 REG O6h bits 4 0 1 8 2 D 0 NO OTE 607 IN S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 85 Vancouver Design Center 7 4 13 CRT Timing Example Timing for 640x480 CRT VNDP VDP pie gt VRTC HRTC Uo U U U U i U U DACP
305. hat all dword values are in hexadecimal therefore 280h 640 1E0h 480 and 3Ch 60 The value for Flags should be 1 LCD 2 CRT or 3 both LCD and CRT When the display driver starts it will read these values in the registry and attempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the first mode table in your list A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that controls these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request Resource Management Issues The Windows CE 3 0 OEM must deal with certain display driver issues relevant to Windows CE 3 0 These issues require the OEM balance factors such as system vs display memory utilization video performance and power off capabilities The section Simple Display Driver Configuration on page 15 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display driver configuration as described below in Description of
306. he Device menu the Memory Setup dialog box is displayed To select a memory assignment highlight it in the example window below Memory Type 0 is highlighted and click OK If the highlighted memory assignment needs changes click Edit and see the next section Edit Memory Setup Whenever a memory assignment is edited or selected in the Memory Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configu ration In addition to OK Cancel and Edit commands a Help command is listed in the Memory setup windows In this version of 13504CFG the Help files are unavailable Memory Assignment for Device MEMORY TYPE MEMORY TYPE 1 MEMORY TYPE 2 MEMORY TYPE 3 CURRENT CONFIGURATION Cancel Help HEEL Figure 14 13504CFG Advanced Memory Setup 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 22 Epson Research and Development Vancouver Design Center Edit Advanced Memory Setup When a selection is highlighted in the Memory Setup window and Edit is clicked the Edit Advanced Memory Setup window is displayed The Edit Advanced Memory window lists parameters which can be edited as shown below in Figure 15 13504CFG Edit Advanced Memory Setup In this example window Refresh Time 4000 Cycles is highlighted 66 ns PERF ENABLE for Device Refresh Time 4666 cycles T Refresh Cycles 256 cycle
307. he location of this memory block the S5U13504B00C evalu ation board decodes the display buffer at the 12M byte location of system memory 3 2 Display Buffer Organization 3 2 1 Memory Organization for One Bit per pixel 2 Colors Gray Shades Eight pixels are grouped into one byte of display buffer as shown below Table 3 1 Pixel Storage for 1 bpp 2 Colors Gray Shades in One Byte of Display Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Bit O Bit O Bit O Bit 0 Bit O Bit O Bit O Bit O 3 2 2 Memory Organization for Two Bit per pixel 4 Colors Gray Shades Table 3 2 Pixel Storage for 2 bpp 4 Colors Gray Shades in One Byte of Display Buffer One bit per pixel provides two shades of gray by indexing into positions O and 1 of the Green Look Up Table LUT and two levels of color by indexing into positions O and 1 of the Red Green Blue LUTs Four pixels are grouped into one byte of display buffer as shown below Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 2 Pixel 2 Pixel 3 Pixel 3 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Two bit per pixel provides four shades of gray by indexing into positions 0 through 3 of the Green LUT and four levels of color by indexing into positions 0 through 3 of the Red Green Blue LUTs 1D13504 X19A G 002 07 Programming
308. her of the architectures described in note 1 accessing the adjacent unused registers is prohibited 3 To access the RAMDAC registers the CRT enable bit REG ODh bit 1 must be set to 1 RAMDAC Pixel Read Mask Register REG 28h or REG 29h RW RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 bits 7 0 RAMDAC Pixel Read Mask Bits 7 0 Hardware Functional Specification Issue Date 01 11 06 A CPU read or write to this register will generate a DACRD or DACWR pulse and DACRS1 1 and DACRSO 0 to the external RAMDAC for a pixel read mask register access The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits 7 0 in a Little Endian system or data bus bits 15 8 in a Big Endian system S1D13504 X19A A 002 19 Page 112 Epson Research and Development Vancouver Design Center RAMDAC Read Mode Address Register REG 2Ah or REG 2Bh RW RAMDAC Address Bit 7 RAMDAC Address Bit 6 RAMDAC Address Bit 5 RAMDAC Address Bit 4 RAMDAC Address Bit 3 RAMDAC Address Bit 2 RAMDAC Address Bit 1 RAMDAC Address Bit 0 bits 7 0 RAMDAC Read Mode Address Bits 7 0 A CPU read or write to this register will generate a DACRD or DACWR pulse and DACRS1 1 and DACRSO to the external R
309. hese registers Register 1E 1F General I O Pins Configuration these values nee may need to be changed according to your system pRegs 0x1E 0x00 0000 0000 pRegs 0x1F 0x00 0000 0000 jx Register 20 21 General I O Pins Control these values EE may need to be changed according to your system ef pRegs 0x20 0x00 0000 0000 pRegs 0x21 0x00 0000 0000 VES Registers 24 27 LUT control EE For this example do a typical 8BPP LUT setup In 8BPP mode only the first 8 red first 8 green EK and first 4 blue values are used k k Setup the pointer to the LUT data and reset the LUT index register Then loop writing each of the RGB LUT data elements Ar pLUT LUT8 pRegs 0x24 0 Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 60 for idx 0 idx lt 8 1dx for rgb 0 rgb lt 3 rgb pRegs 0x26 pLUT pLUT Registers 28 2E RAMDAC not used in this example Epson Research and Development Vancouver Design Center Programmed very ntries are used aK similarly to the LUT but al xy Register 23 Performance Enhancement displ EX performance ES pRegs 0x23 0x10 Register D Display Mode 8 BPP LCD enable E pRegs 0x0D 0x0D S1D13504 X19A G 002 07 0001 0000 0000 1101 lay FIFO enabled optim
310. ica Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor 1D13504 X19A G 010 06 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 EPSON S1D13504 Color Graphics LCD CRT Controller Interfacing to the Motorola MCF5307 Coldfire Microprocessor Document Number X19A G 011 07 Copyright O 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the conte
311. ices such as the S1D13504 therefore the interfaces described in this document do not attempt to support burst cycles However the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13504 address space 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Ya clock cycle The CSNT bit causes chip select and WE to be negated 1 2 clock cycle earlier than normal The TRLX relaxed timing bit will insert an additional one clock delay between asser tion of the address bus and chip select This accommodates memory and peripherals with long se
312. iguration errors 13504DCFG Driver Configuration Program 1D13504 Issue Date 01 10 26 X19A B 008 03 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 EPSON 1D13504 Color Graphics LCD CRT Controller Windows CE 2 x Display Drivers Document Number X19A E 001 05 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Windows CE 2 x Display Drivers X19A E 001 05 Issue Date 01 05 25 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 2 x DISPLAY DRIVERS The Windows CE display driver is designed to support
313. iko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction 1 2 ee 11 Ids Scope acto wont A eth ee A eR ak eA oh Se ae EP Oe eee ee add 12 Overview Description 2 yee Pet ee e Pe tee aie bw oe gle e e T 21 Features sr aie teria cdot ra a Taree a nar area Chk Bak wah Sa Bi Acta Se ee RD EL 12 2 1 Memory Interface 2 2 a a 1 22 CPU Mterface p ese a A eh o o p a Gd 23 Display Support cai aoe he a Bh a eee ee ee eS rs 2 24 Display Modes vos a ee tek ts tee A e Ah or hat ee IB 25 Clock Source Gos Soe oe A ir SO i lA as de bh se A A 2 6 Miscellaneous ess Se aE OE oe se OR a dee a we a ft eee dS 2 7 Package ad PIO ie goog hoo Oe a Be ee ke a ee ee a ee ee AS Typical System Implementation Diagrams 00 22002 4 14 Block Description s sos su a see
314. inate of the pixel starting from 0 y vertical coordinate of the pixel starting from 0 color for 1 2 4 8 BPP refers to index into LUT DAC For 15 16 BPP defines color directly not LUT DAC index Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid 8 2 5 Register Manipulation int seGetReg int device int index BYTE pVal Description Reads a register value Parameter device registered device ID index register index pVal returns value of the register Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seSetReg int device int index BYTE val Description Writes a register value Parameter device registered device ID index register index val value to write to the register Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid 8 2 6 Miscellaneous S1D13504 X19A G 002 07 int seDelay int device DWORD Seconds Description Delays for the given amount of time For non Intel platforms the 13504 registers must be initialized and the VNDP set active the VNDP is used as the timer Parameter device registered device ID Seconds delay time in seconds Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_FAILED registers have not been initialize
315. ind the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF CEPC_DDI_S1D13X0X Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT653X IF CEPC_DDI_VGASBPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATI Windows CE 3 x Display Drivers 1D13504 Issue Date 01 05 08 X19A E 006 01 Page 6 Epson Research and Development Vancouver Design Center 1D13504 11 12 ddi dll _FLATRELEASEDIR ddi_flat dll NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Modify MODE0 H The file MODEO H located in x wince300 platform cepc drivers display S 1D13504 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the console driver If the default does not match the configura tion you are building for then MODEO H will have to be regenerated with the correct information Use the program 13504CFG to generate the header file For information on how to use 13504CFG refer to the 13504CFG Configuration Program User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the
316. indow Each tab configures a specific aspect of S1D13504 operation The tabs are labeled General Preferences Memory Clocks Panel CRT and Registers The following sections describe the purpose and use of each of the tabs General Tab 51D13504 Configuration Utility Build 3 Decode Addresses Register Address Display Buffer Address The General tab contains S1D13504 evaluation platform specific information The values presented are used for configuring HAL based display drivers The settings on this tab specify where in CPU address space the registers and display buffer are located and the data bus size Decode Addresses Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer address fields The values used for each evalu ation platform are examples of possible implementa tions as used by the Epson S1D13504 evaluation boards If your hardware implementation differs from 13504DCFG Driver Configuration Program S1D13504 Issue Date 01 10 26 X19A B 008 03 Page 8 1D13504 X19A B 008 03 Register Address Display Buffer Address CPU Data Bus Width Epson Research and Development Vancouver Design Center these addresses select the User Defined option and enter the correct addresses for Register address and Display buffer address The physical address of the start of register decode space
317. ine argument software was selected more than once Select software only once ERROR Already selected HARDWARE Command line argument hardware was selected more than once Select hardware only once ERROR Already selected ENABLE Command line argument enable was selected more than once Select enable only once ERROR Already selected DISABLE Command line argument disable was selected more than once Select disable only once ERROR Select software or hardware Neither command line argument software or hardware was selected Select software or hardware ERROR Select enable or disable Neither command line argument enable or disable was selected Select enable or disable ERROR Too many devices registered There are too many display devices attached to the HAL The HAL can only manage 10 devices simultaneously ERROR Could not register S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program ERROR Did not detect S1D13504 The HAL was unable to read the revision code register on the S1D13504 Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly 13504PWR Software Suspend Power Sequencing Utility S1D13504 Issue Date 01 02 01 X19A B 007 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504PWR Softwa
318. ing to the NEC VR4102 Microprocessor S1D13504 Issue Date 01 10 26 X19A G 007 08 Page 14 4 3 NEC Vr24102 Configuration Epson Research and Development Vancouver Design Center The NEC Vr4102 provides the internal address decoding necessary to map to an external LCD controller Physical address 0A00 0000h to OAFF FFFFh 16M bytes is reserved for an external LCD controller The S1D13504 supports up to 2M bytes of display buffer The NEC Vr4102 address line A21 is used to select between the 1D13504 display buffer and internal register set The Vr4102 uses a read write and system high byte enable to interface to an external LCD controller The S1D13504 uses low and high byte read and write strobes and therefore minimal glue logic is necessary Table 4 2 NEC SID13504 Truth Table NEC Signals Cycle 1D13504 Signals SHB RD WR AO 8 bit even address RDO low 1 0 1 0 Read RD1 high r i 8 bit odd address RDO high Read RD1 low RDO low 0 0 1 x 16 bit Read RD1 low 8 bit even address WRO low 1 1 0 0 i Write WR1 high 8 bit odd address WRO high 1 1 0 1 Write WR1 low WRO low 0 1 0 xX 16 bit Write WR1 low 1D13504 X19A G 007 08 Interfacing to the NEC VR4102 Microprocessor Issue Date 01 10 26 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and display drivers are avai
319. into the list of directories 8 Edit the file PLATFORM BIB located in x wince platform cepc files to set the de fault display driver to the file EPSON DLL EPSON DLL will be created during the build in step 13 Replace or comment out the following lines in PLATFORM BIB IF CEPC_DDI_VGA2BPP ddi dll FLATRELEASEDIR Mddi_vga2 dll NK SH ENDIF IF CEPC_DDI_VGA8BPP ddi dil _ FLATRELEASEDIR ddi_vga8 dll NK SH ENDIF IF CEPC_DDI_VGA2BPP IF CEPC_DDI_VGASBPP ddi dill _FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF with this line ddi dll FLATRELEASEDIRNEPSON dll NK SH 9 The file MODEO H located in x wince platform cepc drivers display S 1D 13504 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the driver If the default does not match the configuration you are building for then MODEO H will have to be regenerated with the correct informa tion Use the program 13504CFG to generate the header file For information on how to use 13504CFG refer to the 13504CFG Configuration Program User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODEO H in xAwincel
320. ion e Technical manual includes Data Sheet Application Notes and Programmer s Reference Software e User Utilities OEM Utilities Evaluation Software e To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 TECHNICAL MANUAL Issue Date 01 04 18 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13504 X19A Q 002 14 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 TECHNICAL MANUAL X19A Q 002 14 Issue Date 01 04 18 EPSON amp GRAPHICS S1D13504 S1D13
321. ion pixels Help Figure 10 13504CFG Panel Parameter Edit 13504CFG EXE Configuration Program Issue Date 01 01 30 S1D13504 X19A B 001 04 Epson Research and Development Page 19 Vancouver Design Center CRT CRT Setup When CRT is selected from the Device menu the CRT Setup window is displayed To select a CRT assignment highlight it in the example window below CRT 640x400 85Hz CLKI 33 333MHz is highlighted and click OK If the highlighted CRT assignment needs changes click Edit and see the next section Edit CRT Setup Whenever a CRT assignment is edited or selected in the CRT Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configuration In addition to OK Cancel and Edit commands a Help command is listed in the CRT setup windows In this version of 13504CFG the Help files are unavailable RT Assignment for Device CRT 640x400 e 85Hz CLKI 33 333MHz CRT 640x480 68Hz CLKI 25 175MHz CRT 640x480 75Hz CLKI 33 333MHz CRT 880x600 56Hz CLKI 36 B88MHz CRT 800x600 68Hz CLKI 40 80MHz CURRENT CONFIGURATION gt Ye Edit Cancel Help i Current Frame Rate 75 Hz lt FROM PANEL CRT NOT ENABLED Figure 11 13504CFG CRT Setup 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 20 Edit CRT Setup Epson Research and Development Vancouver Design Center When a se
322. ion completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_HAL_BAD_ARG argument xVirt is too large Select x Virt such that the Memory Address Offset register does not exceed Ox3ff The maximum allowable xVirt is Ox3ff 16 bpp If bpp is 15 use the above equation with bpp 16 seSetInit must have been called before calling seVirtInit This is because the VNDP is used for timing and this would not be possible if the registers were not first initialized int seVirtMove int device BYTE WhichScreen int x int y Description Parameter Return Value Note Pans or scrolls the virtual display device registered device ID WhichScreen Use one of the following definitions SCREEN1 or SCREEN2 SCREEN is the top screen X new starting X position in pixels y new starting Y position in pixels ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_HAL_BAD_ARG argument WhichScreen is not SCREEN or SCREEN2 argument Y is too large bpp is invalid in HAL structure this would occur if the application changed the registers directly instead of calling seSetBitsPerPixel seVirtInit must have been called once before calling seVirtMove Programming Notes and Examples Issue Date 01 02 01 1D13504 X19A G 002 07 Page 46 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center int seWriteDispla
323. iption Using Two IT8368E s 2 2 2 2 2 2 2 16 5 3 IT8368E Configuration 18 5 4 Memory Mapping and Aliasing 19 5 5 S1D13504 Configuration 2 o 20 SoftWare aaa A ta 21 References tl a a Ae ee 28 a a Sn ias dara 22 TE Documents lt td ce eee a e a ra a e a 2 2 2 Document Sources o e ees a Wess A ti ad ds Pe a ees amp 22 8 Technical Support 2 24 202 sats oo Se AREA 23 8 1 EPSON LCD CRT Controllers S1D13504 2 2 ee 23 8 2 Toshiba MIPS TX3912 Processor 2 2 a eee 23 8330 IPE TESIOSE UL fot ca Su a ke A hoe oe A AS Interfacing to the Toshiba MIPS TX3912 Processor 1D13504 Issue Date 01 10 26 X19A G 012 05 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 Epson Research and Development Vancouver Design Center List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping Table 4 1 S1D13504 Configuration for Direct Connection Table 4 2 S1D13504 Host Bus Selection for Direct Connection Table 5 1 TX3912 to Unbuffered PC Card Slots System Address Mapping Table 5 2 TX3912 to PC Card Slots Address Remapping using the IT8368E Table 5 3 S1D13504 Configuration using the IT8368E Table 5 4 S1D13504 Host Bus Selection using the IT8368E List of Figures Figur
324. is configured as an output When this bit 0 default GPIO2 is config ured as an input Note the MD 7 6 pins must be properly configured at the rising edge of RESET to enable GPIO2 otherwise the MA11 pin is controlled automatically and this bit will have no effect on hardware GPIO1 Pin IO Configuration When this bit 1 GPIO1 is configured as an output When this bit 0 default GPIO1 is config ured as an input Note the MD 7 6 pins must be properly configured at the rising edge of RESET to enable GPIO1 otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware GPIO0 Pin IO Configuration When this bit 1 GPIOO is configured as an output When this bit 0 default GPIOO is config ured as an input Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 104 Epson Research and Development Vancouver Design Center REG 1Fh GPIO Configuration Register 1 RW n a n a GPIO11 Pin IO Config GPIO10 Pin IO Config GPIO9 Pin 10 Config GPIO8 Pin Ng na IO Config bit 3 bit 2 bit 1 bit O 1D13504 X19A A 002 19 GPIO11 Pin IO Configuration When this bit 1 GPIO11 is configured as an output When this bit 0 default GPIO11 is con figured as an input Note the MD8 pin must be high at the rising edge of RESET to enable GPIO11 otherwise the VRTC pin is controlled automatically and
325. ister clear rl point rl to start of S1D13504 mem space write 0 to disable register read revision code into rl branch forever Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 Epson Research and Development Page 21 Vancouver Design Center Note MPC8BUG does not support comments or symbolic equates these have been added for clarity Note It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled the MMU must be setup so the S1D13504 memory block is tagged as non cacheable This ensures that accesses to the 1D13504 will occur in proper order and the MPC821 will not attempt to cache any data read from or written to the S1D13504 or its display buffer Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 22 5 Software 1D13504 X19A G 010 06 Epson Research and Development Vancouver Design Center Test utilities and display drivers are available for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CEG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales suppor
326. ister may be considered an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the S1D13504 is accessed by the host CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RDO and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13504 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13504 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13504 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS signal is not used for the Generic MPU host bus interface and should be tied low connected to GND Interfacing to the PC Card Bus 1D13504 Issue Date 01 02 02 X19A G 009 05 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to
327. it 0 the GPO output is set to the reset state When this bit 1 the GPO output pin is set to the inverse of the reset state GPIO11 Pin IO Status When GPIO11 is configured as an output a 1 in this bit drives GPIO11 to high and a 0 in this bit drives GPIO11 to low When GPIO11 is configured as an input a read from this bit returns the status of GPIO11 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO11 otherwise the VRTC pin is controlled automatically and this bit will have no effect on hardware GPIO10 Pin IO Status When GPIO10 is configured as an output a 1 in this bit drives GPIO10 to high and a 0 in this bit drives GPIO10 to low When GPIO10 is configured as an input a read from this bit returns the status of GPIO10 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO10 otherwise the HRTC pin is controlled automatically and this bit will have no effect on hardware GPIO9 Pin IO Status When GPIO9 is configured as an output a 1 in this bit drives GPIO9 to high and a 0 in this bit drives GPIO9 to low When GPIO9 is configured as an input a read from this bit returns the status of GPIO9 Note the MD8 pin must be high at the rising edge of RESET to enable GPIOS9 other wise the DACRS1 pin is controlled automatically and this bit will have no effect on hardware GPIO8 Pin IO Status When GPIO8 is configured as an output a 1 in this bit drives GPIO8
328. ith version 2 0 of the ETK Platform Builder v2 1x Windows CE 2 x Display Drivers 1D13504 Issue Date 01 05 25 X19A E 001 05 Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Windows CE 2 x Display Drivers X19A E 001 05 Issue Date 01 05 25 EPSON 1D13504 Color Graphics LCD CRT Controller Wind River WindML v2 0 Display Drivers Document Number X19A E 002 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Wind River WindML v2 0 Display Drivers X19A E 002 03 Issue Date 01 04 06 Epson Research and Development Page 3 Vancouver Design Center Wind River WindML v2 0 Display Drivers The Wind River WindML v2 0 display drivers for the S1D13504 Embedded RAMDAC LCD CRT Con
329. ith TX3912 Table 4 2 S1D13504 Host Bus Selection for Direct Connection MD3 MD2 MD1 Host Bus Interface SH 3 bus interface MC68K bus 1 interface e g MC68000 ojojo O O oj o xX X MC68K bus 2 interface e g MC68030 eric bus interf 53 Reserved L required configuration for direct connection with TX3912 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 S1D13504 X19A G 012 05 Page 14 Epson Research and Development Vancouver Design Center 5 System Design Using the IT8368E PC Card Buffer If the system designer uses an ITE IT8368E PC Card and multiple function IO buffer the S1D13504 can be interfaced with the TX3912 without using a PC Card slot Instead the S1D13504 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the 1D13504 virtually transparent to PC Card devices that use the same slot 5 1 Hardware Description Using One IT8368E 1D13504 X19A G 012 05 The ITE IT8368E has been specifically designed to support EPSON CRT LCD controllers The IT8368E provides eleven Multi Function IO pins MFIO Configuration registers can be used to allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU interface The Toshiba TX3912 processor only provides addresses A 12 0 therefore devices that occupy more address space must use an external device to latch
330. its represent an index into the blue LUT Although eight bit per pixel only makes sense for a color panel this memory model can be set on a monochrome panel however only eight shades of gray will be visible Programming Notes and Examples Issue Date 01 02 01 1D13504 X19A G 002 07 Page 14 Epson Research and Development Vancouver Design Center 3 2 5 Memory Organization for 15 Bit per pixel 32768 Colors One pixel is stored in two bytes of display buffer as shown below Table 3 5 Pixel Storage for 15 bpp 32768 Colors in Two Bytes of Display Buffer Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reserved Red Bit 4 Red Bit 3 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit 4 Green Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 4 Blue Bit 3 Blue Bit 2 Blue Bit 1 Blue Bit 0 As shown above the 32768 color pixel is divided into four parts five bits for red five bits for green and five bits for blue and one reserved bit The output bypasses the LUT and goes directly into the Frame Rate Modulator Although 15 bit per pixel only make sense for a color panel this memory model can be set on a monochrome panel however only 16 shades of gray will be visible 3 2 6 Memory Organization for 16 Bit per pixel 65536 Colors One pixel is stored in two bytes of display buffer as shown below Table 3 6 Pixel Storage for 16 bpp
331. ive high for TFT and active low for passive LCD When this bit 0 the FRAME pulse is active low for TFT and active high for passive LCD Table 8 5 FPFRAME Polarity Selection FPFRAME Polarity Select passer Ce POERAME TFT FPFRAME Polarity Polarity 0 active high active low 1 active low active high bits 2 0 VRTC FPFRAME Pulse Width Bits 2 0 Hardware Functional Specification Issue Date 01 11 06 For CRTs and TFTs these bits specify the pulse width of VRTC and FPFRAME respectively For passive LCDs FPFRAME is automatically created and these bits have no effect VRTC FPFRAME pulse width lines VRTC FPFRAME Pulse Width Bits 2 0 1 The maximum VRTC pulse width is 8 lines Note This register must be programmed such that REG OAh bits 5 0 1 gt REG OBh 1 REG OCH bits 2 0 1 S1D13504 X19A A 002 19 Page 96 Epson Research and Development Vancouver Design Center 8 2 4 Display Configuration Registers REG ODh Display Mode Register RW n a Display Bit 1 Simultaneous Simultaneous Option Select Option Select Number Of Number Of Number Of Bits Pixel Bits Pixel Bits Pixel CRT Enable LCD Enable Select Bit 2 Select Bit 1 Select Bit 0 Display Bit 0 bits 6 5 1D13504 X19A A 002 19 Simultaneous Display Option Select Bits 1 0 These bits are used to select one of four different simultaneous display mode options Normal Line Doubling Inter
332. ive low for passive LCD When this bit 0 the FPLINE pulse is active low for TFT and active high for passive LCD Table 8 4 FPLINE Polarity Selection FPLINE Polarity Select Passive LCD FPLINE Polarity TFT FPLINE Polarity 0 active high active low 1 active low active high bits 3 0 HRTC FPLINE Pulse Width Bits 3 0 For CRTs and TFTs these bits specify the pulse width of HRTC and FPLINE respectively For pas sive LCDs FPLINE is automatically created and these bits have no effect HRTC FPLINE pulse width pixels HRTC FPLINE Pulse Width Bits 3 0 1 x 8 The maximum HRTC pulse width is 128 pixels Note This register must be programmed such that REG 05h 1 gt REG 06h 1 REG 07h bits 3 0 1 Vertical Display Height Register 0 REG 08h RW Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Display Display Display Display Display Display Display Height Bit7 Height Bit6 Height Bit5 Height Bit4 Height Bit3 Height Bit2 Height Bit 1 Height Bit 0 Vertical Display Height Register 1 REG 09h RW Vertical Vertical n a n a n a n a n a n a Display Display Height Bit 9 Height Bit 8 REG 08h bits 7 0 REG 09h bits 1 0 Hardware Functional Specification Issue Date 01 11 06 Vertical Display Height Bits 9 0 These bits specify the LCD panel and or the CRT vertical display height in 1 line resolution For a dual LCD pa
333. iven utility Note A utility must be opened before any other menu command can be executed e Save saves the current changes to the opened file e Save As saves a file to a different name and or different location e Save All saves modifications to all 13504 files that are in the same directory as the file being saved This function ensures that the display parameters are consistent Save All is only avail able for utilities run on an Intel EXE platform e Exit exits the 13504CFG application 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 14 View Menu Files Epson Research and Development Vancouver Design Center View Device Current Configuration S1D13504 X19A B 001 04 Figure 4 13504CFG View Menu The View menu displays the Current Configuration and the Advanced Configuration of an opened utility In the Current or Advanced Configuration window the configuration of an opened file can be viewed only not edited Configuration parameters must be edited in the Panel CRT Advanced Memory Power Management Look Up Table and Setup sub menus in the Device menu Some configuration parameters cannot be readily changed as they depend on several factors for consistency eg Frame Rate Clock Divides etc Refer to the S1D13504 Functional Hardware Specification manual document number X19A A 002 xx and the 1D13504 Programming Notes and Examples man
334. izes the S1D13504 and reads the registers Note after a semi colon all characters on a line are ignored de xa q S1D13504 X19A B 005 05 Page 6 Comments Program Messages 1D13504 X19A B 005 05 Epson Research and Development Vancouver Design Center All numeric values are considered to be hexadecimal unless identified otherwise For example 10 10h 16 decimal 10t 10 decimal 010b 2 decimal Redirecting commands from a script file PC platform allows those commands to be executed as though they were typed The PC must not have more than 12M bytes of memory when used with the S5U13504B00C board Follow simultaneous display guidelines for correct simultaneous display operation To determine if the CRT will operate correctly when using a dual panel refer to the Maximum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing A CRT cannot show 15 or 16 bits per pixel Do not attach a panel with a 16 bit interface to the S1D13504 when a CRT is also attached ERROR Too many devices registered There are too many display devices at
335. k Up Table Architecture 124 Figure 12 6 4 Bit Per Pixel 16 Level Color Mode Look Up Table Architecture 125 Figure 12 7 8 Bit Per Pixel 256 Level Color Mode Look Up Table Architecture 126 Figure 14 1 Mechanical Drawing QFP15 128 2002 000000000000 129 Figure 14 2 Mechanical Drawing TQFPI5 128 000000000000 130 Figure 14 3 Mechanical Drawing QFP20 144 2 ee ee ee 131 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 11 Vancouver Design Center 1 Introduction 1 1 Scope This is the Hardware Functional Specification for the S1D13504 Series Color Graphics LCD CRT Controller Chip Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers This document is updated as appropriate Please check for the latest revision of this document before beginning any development The latest revision can be downloaded at www erd epson com We appreciate your comments on our documentation Please contact us via email at documen tation erd epson com 1 2 Overview Description The 1D13504 is a low cost low power color monochrome LCD CRT controller interfacing to a wide range of CPUs and LCDs The S1D13504 architecture is designe
336. knowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks The following figure illustrates a typical memory read cycle on the Power PC system bus AA MINA AAN TS TA i l Afo 31 XO X RD WR TSIZ 0 1 AT O 3 X D10 311 LLORIA OLLA NAX Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 10 Epson Research and Development Vancouver Design Center The following figure illustrates a typical memory write cycle on the Power PC system bus evek LE LELELELI LIU Li TS TA i A 0 31 X ROMA A LR TSIZ 0 1 AT O 3 pjo 31 XXXXXXX_ Valid XXX Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus tim
337. l output from the S1D13504 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13504 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13504 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and must be inverted using MDS since the MPC821 wait state signal is active high The Bus Start BS signal is not used for the Generic MPU host bus interface and must be connected to IO Vpp Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 Epson Research and Development Page 15 Vancouver Design Center 4 MPC821 to S1D13504 Interface 4 1 Hardware Description The interface between the S1D13504 and the MPC821 requires no glue logic All lines are directly connected A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle BS bus start is not used in this implementation and must be connected to IO Vpp The following diagram shows a typical implementation of the MPC821 to S1D13504 interface MPC821 1D13504 A10 M R A 11 31 AB 20 0 S4 CS Vcc 470 TA ae WAIT EO WE1 WE1 WEO OE RD1 RDO SYSCLK BUSCLK System RESET
338. l registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS signal is not used for the Generic MPU host bus interface and must be connected to IO Vpp Interfacing to the NEC VR4102 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 007 08 Page 12 Epson Research and Development Vancouver Design Center 4 VR4102 to S1D13504 Interface 4 1 Hardware Description The NEC Vr4102 microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using this interface only minimal external glue logic is necessary The diagram below shows a typical implementation of the VR4102 to S1D13504 interface Read Write NEC VR4102 Decode Logic S1D13504 US A WEO WR SHB WE1 AO RDO RD l e RD1 LCDCS Pullup CS i LCDRDY WAIT A21 gt MIR System RESET gt RESET ADD 25 0 gt AB 20 0 DAT 15 0 DB 15 0 BUSCLK BUSCLK Notes The propagation delay of the Read write Decode Logic shown above must be less than 10 nsec When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from p
339. lable for the S1D13504 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CKG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the NEC VR4102 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 007 08 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents NEC Electronics Inc VR4102 Preliminary User s Manual Document Number U12739EJ2VOUMOO Epson Research and Development Inc 1D 13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc 1D13504 Programming Notes and Examples Document Number X19A G 002 xx 6 2 Document Sources e NEC Electronics Website http www necel com e Epson Research and Development Website http www erd epson com 1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 Epson Research and Development Page 17 Vancouver Design Center 7 Technic
340. lace or Even Scan Only The purpose of these modes is to manipulate the vertical resolution of the image so that it fits on both CRT typically 640 x 480 and LCD The following gives descriptions of the four modes using a 640x480 CRT as an example Table 8 6 Simultaneous Display Option Selection Simultaneous Display Option Select Bits 1 0 Simultaneous Display Option 00 Normal 01 Line Doubling 10 Interlace 11 Even Scan Only Note 1 Line doubling option is not supported with dual panel 2 Dual Panel Considerations When configured for a dual panel LCD and using Simultaneous Display the Half Frame Buffer Disable REG 1Bh bit 0 must be set to 1 This will result in a lower contrast on the LCD panel which then may require adjustment Normal the image is the same on both displays i e 640x240 CRT parameters determine the LCD image The LCD image will appear to be washed out due to the 1 525 duty cycle of the CRT Line Doubling each line is sent to the CRT twice giving a 640x480 image which has a long aspect ratio The image on the LCD has each line sent twice but only one FPLINE This gives a duty cycle of 2 525 which is very close to the LCD only mode duty cycle of 1 242 so the image on the LCD will have almost the same contrast as that of a single LCD Interlace odd frames receive odd scan lines and even frames receive even scan lines The 640x480 image on the CRT will be normal while the ima
341. lator CLKI When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13504 X19A G 009 05 Figure 4 1 Typical Implementation of PC Card to SID13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the PC Card Bus Issue Date 01 02 02 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx The tables below show only those configuration settings important to the PC Card interface Table 4 1 Summary of Power On Reset Options S1D13504 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface Y MD1 MD2 For host bus interface selection see Table 4 2 Host Bus Interface Selection MD3 MD4 Big Endian MD5 WAIT is active high 1 insert wait state Ei configuration for PC Card interface Table 4 2 Host Bus Interface Selection MD3 MD2 MD1 Host Bus Interface 0 0 0 SH 3 0 0 1 MC68K Bus 1 e g
342. le for S1D13504 Generic Drivers option Save the new configuration as 1d13504 h in the usr src linux drivers video replacing the original configuration file 5 Configure the video options From the command prompt in the directory usr src linux run the command make menuconfig This command will start a text based interface which allows the selection of build time parameters From the text interface under Console drivers options select Support for frame buffer devices Epson LCD CRT controllers support S1D13504 support Advanced low level driver options xBpp packed pixels support where x is the color depth being compile for Once you have configured the kernel options save and exit the configuration utility 6 Compile and install the kernel Build the kernel with the following sequence of commands make dep make clean make bzImage sbin lilo if running lilo Linux Console Driver 1D13504 Issue Date 01 11 19 X19A E 004 01 Page 6 Epson Research and Development Vancouver Design Center 7 Boot to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13504 console driver with X server you need to configure the X server to use the FBDEV device A good pl
343. lection is highlighted in the CRT Setup window and Edit is clicked the Edit CRT Setup window is displayed The Edit CRT Setup window lists parameters which can be edited as shown below in Figure 12 13504CFG Edit CRT Setup In this example window Horiz Non Display 240 pixels is highlighted 646x466 CLKI 33 333MHz for Device X Resolution Y Resolution Horiz Non Displa Non Display Start Position Start Position Polarity Polarity Pulse Width Pulse Width Divide Divide CLKI CRT Enable Disable Current Frame Rate Figure 12 13504CFG Edit CRT Setup CRT Parameter Edit 646 pixels 466 line lt s gt 246 pixels 45 linets gt 32 pixels 1 line lt s gt ACTIVE LOW ACTIVE HIGH 64 pixels 3 line lt s gt MCLK 1 PCLK 1 33 333 MHz ENABLE Cie Cancel CA CCRT SETTINGS OVERRIDE PANEL When a selection is highlighted for editing in the Edit CRT Setup window and Edit is clicked the CRT Parameter Edit window displays for parameter editing See figure 13 13504CFG CRT Parameter Edit below In this example window Horiz Non Display 240 pixels can be edited Figure 13 13504CFG CRT Parameter Edit 1D13504 X19A B 001 04 Horiz Non Display pixels Cancel Help 13504CFG EXE Configuration Program Issue Date 01 01 30 Epson Research and Development Page 21 Vancouver Design Center Advanced Memory Memory Setup When Advanced Memory is selected from t
344. line Chip Select CS must be driven low whenever the 1D13504 is accessed by the host CPU WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RDO and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13504 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13504 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1D13504 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS signal is not used for the Generic MPU host bus interface and must be connected to IO Vpp Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Page 11 Vancouver Design Center 4 Direct Connection to the Toshiba TX3912 4 1 Hardware Description The S1D13504 is easily interfaced to the Toshiba TX3912 p
345. lled 13504CKG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13504 Issue Date 01 10 26 X19A G 005 09 Page 22 Epson Research and Development Vancouver Design Center 7 References 7 1 Documents Philips Electronics PR31500 PR31700 Preliminary Specifications e Epson Research and Development Inc D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 xx e Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 7 2 Document Sources e Philips Electronics Website http www us2 semiconductors philips com e Epson Research and Development Website http www erd epson com 1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 8 Technical Support 8 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 4
346. lopment Page 25 Vancouver Design Center 4 Program the Memory Address Offset Registers Register 17h will be set to 0 and register 16h will be set to OxAO 4 2 Panning and Scrolling Panning and scrolling are typically used to navigate within an image which is too large to be shown completely on the display device Although the image is stored entirely in display buffer only a portion is actually visible at any given time Panning and scrolling refers to the direction the viewport appears to move Panning describes the action where the viewport moves horizontally When panning to the right the image in the viewport appears to slide to the left A pan to the left causes the image to appear as if it s sliding to the right Scrolling describes the up and down motion of the viewport Scrolling down causes the image to appear to slide upwards and scrolling up results in an image that appears to slide downwards On the S1D13504 panning is performed by setting two components the start address registers provide a word granularity in movement more than one pixel while the pixel panning register allows panning at the pixel level Scrolling requires changing only the start address registers There is an order these registers should be accessed to provide the smoothest apparent movement possible Understanding the sequence of operations performed by the S1D13504 will make it apparent why the order should be followed The start address is latched
347. ls are alter nated with grounds on the cable to reduce cross talk and noise related problems Refer to Table 3 1 LCD Signal Connector J6 on page 9 for connection information 6 7 Color Passive LCD Panel Support The S1D13504 directly supports 4 8 16 bit dual and single color passive LCD panels All the necessary signals are provided on the 40 pin ribbon cable header J6 The interface signals are alter nated with grounds on the cable to reduce cross talk and noise related problems The S1D13504 cannot support 12 or 18 bit TFT panels when CRT is enabled FPDAT 15 8 is used for RAMDAC data and is not available for LCD Refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx for details Refer to Table 3 1 LCD Signal Connector J6 on page 9 for connection information 6 8 Color TFT LCD Panel Support The 1D13504 supports 9 12 18 bit active matrix color TFT panels All the necessary signals can also be found on the 40 pin LCD connector J6 The interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems When supporting an 18 bit TFT panel the S1D13504 can display 64K of a possible 262K colors A maximum 16 of the possible 18 bits of LCD data is available from the S1D13504 Refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx for details The S1D13504 cannot support 12 or 18 bit TFT panels when CRT is enabled FPDA
348. luation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Page 21 Vancouver Design Center 4 4 Current Consumption Measurement The evaluation board has 2 headers JP3 and JP4 which allow the independent measurement of S1D13504 CoreVDD and IOVDD current consumption To measure the current remove the appropriate jumper and connect an ammeter to the corresponding header pins S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual S1D13504 Issue Date 2002 12 02 X19A G 014 01 Page 22 Epson Research and Development Vancouver Design Center 5 References 5 1 Documents e Epson Research and Development Inc S1D13504 Hardware Functional Specification document number X19A A 001 xx Epson Research and Development Inc S1D 13504 Programming Notes and Examples document number X19A G 002 xx 5 2 Document Sources e Epson Research and Development Website http www erd epson com S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Vancouver Design Center 6 Parts List Table 6 1 Parts List Page 23 Manufacturer Part No Assembly ltem Qty Reference Part Description Instructions C1 C2 C3 C4 C5 C6 C7 C8 C9 C11 C12 C13 C14 C15 C16 C19 C21 y _ 1 32 C22 C23 C29 C0805 0 1uF Panasonic ECJ 2VB1C104K generic
349. lue is equal to or greater than the physical number of lines being displayed there is no visible effect on the display When the line compare value is less than the number of physically displayed lines display operation works like this 1 From the end of vertical non display to the number of lines indicated by line compare the dis play data will be from the memory pointed to by the Screen 1 Display Start Address 2 After line compare lines have been displayed the display will begin showing data from Screen 2 Display Start Address memory S1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 29 Vancouver Design Center REG 13h Screen 2 Display Start Address Register 0 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 14h Screen 2 Display Start Address Register 1 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 15h Screen 2 Display Start Address Register 2 ia aia a Hs Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16 These three registers form the twenty bit offset to the first word in display buffer that will be
350. mage quality by buffering display data in a format directly usable by the panel This option is primarily intended for testing purposes It is recommended that the Dual Panel Buffer be enabled or reduced display quality results Selects the polarity of the FPLINE pulse Refer to the panel specification for the correct polarity of the FPLINE pulse Selects the polarity of the FPFRAME pulse Refer to the panel specification for the correct polarity of the FPFRAME pulse These fields specify the panel width and height A number of common widths and heights are available in the selection boxes If the width height of your panel is not listed enter the actual panel dimensions into the edit field 13504DCFG Driver Configuration Program Issue Date 01 10 26 Epson Research and Development Vancouver Design Center Non display period Frame Rate Pixel Clock TFT FPLINE pixels Start pos Pulse width TFT FPFRAME lines Start pos 13504DCFG Driver Configuration Program Issue Date 01 10 26 Page 17 Manually entered panel widths must be a multiple of 16 pixels for passive STN panels and 8 pixels for TFT panels If a manually entered panel width does not meet the above restrictions a notification box appears and 13504DCFG rounds up the value to the next allowable width It is recommended that these automatically generated non display values be used without adjustment However manual adjustment may be required to
351. me 16 56 200 S Buffer Disabled 1 2 4 8 32 200 MClk 33MHz 480x320 Nac 4 16 56 196 Npp 1 5 300x040 1 2 4 8 32 388 x Naco 2 16 56 380 E Dual Color with Half Frame Buffer go0x60028 1 2 4 8 16 5 32 66 xX y e 16 11 32 43 Dual Mono with Half Frame Buffer 1 2 4 8 165 30 103 Enabled 640x480 16 11 32 68 e Single Panel 2 1 2 4 8 32 50 800x600 e CRT 16 56 48 e Dual Mono Color Panel with Half Frame Buffer Disabled 640x480 ene ae as en e Simultaneous CRT Single Panel 16 56 75 60 Simultaneous CRT Dual 1 2 4 8 32 142 Mono Color Panel with Half Frame 640x240 16 25 56 136 F 60ns Buffer Disabled 1 2 4 8 32 152 FPM DRAM 480x320 16 56 145 MCIk 25MHz 1 2 4 8 32 294 Nac 4 320x240 N RC 15 16 56 280 Naep 2 Dual Mono with Half Frame Buffer 800x600 1 2 4 8 16 125 32 50 z EnADIRO 640x480 1 2 4 8 16 125 32 77 2 640x400 1 2 4 8 16 12 5 32 92 Dual Color with Half Frame Buffer 800x60023 1 2 4 8 12 5 32 50 x Prone 16 8 33 32 33 1 2 4 8 12 5 32 77 640x480 16 8 33 32 51 Must set Nec 4MCLK See REG 22h Performance Enhancement Register 0 800x600 16 bpp requires 2M bytes of display buffer for all display types 800x600 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled 4 Optimum frame rates for panels range from 60Hz to 150Hz If the maximum refresh rate is too high for a pa
352. me Buffer 1FFFFFh Figure 9 1 Display Buffer Addressing The display buffer will contain an image buffer and may also contain a half frame buffer Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 114 9 1 Image Buffer Epson Research and Development Vancouver Design Center The image buffer contains the formatted display data see Section 10 1 Display Mode Data Format on page 115 The displayed image s may take up only a portion of the image buffer the remaining area can be used for multiple images possibly for animation or general storage See Section 10 Display Configuration on page 115 for details on the relationship between the image buffer and the display 9 2 Half Frame Buffer 1D13504 X19A A 002 19 In dual panel mode with the half frame buffer enabled the top of the display buffer is allocated to the half frame buffer The size of the half frame buffer is a function of the panel resolution and whether the panel is color or monochrome Half Frame Buffer Size in bytes panel width x panel length factor 16 where factor 4 for color panel for monochrome panel For example for a 640x480 8 bpp color panel the half frame buffer size is 75K bytes In a 512K byte display buffer the half frame buffer resides from 6D400h to 7FFFFh In a 2M byte display buffer the half frame buffer resides from 1ED400h to 1 FFFFFh Hardware Functional
353. me Type FOOA Driver Hest Description FO2A Value FO1A This pin has multiple functions Hi Z e Read signal for external RAMDAC support DACRD IO 84 94 C TS1 Output 11 e General Purpose IO GPIO4 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 This pin has multiple functions Hi Z e Write signal for external RAMDAC support DACWR IO 99 113 C TS1 Output 11 e General Purpose IO GPIO7 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 This pin has multiple functions Hi Z e Register Select bit 1 for external RAMDAC support DACRS1 IO 101 115 C TS1 Output 01 e General Purpose IO GPIO9 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 This pin has multiple functions e Register Select bit 0 for external RAMDAC support DACRSO IO 100 114 C TS1 uA ol General Purpose IO GPIO8 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 This pin has multiple functions Hi Z e Pixel Data bit O for external RAMDAC support DACPO IO 98 112 C CN3 Output 01 e General Purpose IO GPIO6 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 28 Epson Research and Development Vancouver Design Center Table 5 5 CRT and RAMDAC Interface Pin Descriptions Continued Pin Pin Name Type FOOA Driver nen Descri
354. ment Page 5 Vancouver Design Center d Inthe Value box type 1 e Click the Set button f Click the OK button 7 Create a new directory S1D13504 under x wince300 platform cepc drivers display and copy the S1D13504 driver source code into this new directory 8 Add the S1D13504 driver component a From the Platform menu select Insert User Component b Set Files of type to All Files c Select the file x wince300 platform cepc drivers display S 1D13504 sources d Inthe User Component Target File dialog box select browse and then select the path and the file name of sources 9 Delete the component ddi_flat a Inthe Workspace window select the ComponentView tab b Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree c Right click on the ddi_flat component d Select Delete e From the File menu select Save Workspace 10 From the Workspace window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and then click on Hardware Specific Files and then double click on PLATFORM BIB Edit the file the PLATFORM BIB file and make the fol lowing two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13X0X ddi dll FLATRELEASEDIRAS1D13X0X dll NK SH ENDIF b F
355. ment Page 9 Vancouver Design Center Program Requirements Video Controller Any VGA Display Type LCD or CRT BIOS Any manufacturer s VGA BIOS DOS Program Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes Windows 3 1x and Windows 95 OS 2 DOS Full Screen Yes Installation Copy the following files to a directory that is in the DOS path on your hard drive 13504CFG EXE G032 EXE OBJCOPY EXE Note G032 EXE and OBJCOPY EXE are called by 13504CFG EXE for non Intel platforms Neither program is intended to run independent of 13504CFG Usage At the DOS Prompt type 13504cfg 13504cfg exe filename exe script ini Where filename exe is the 13504 utility to be modified script ini 1s the list of HAL configuration changes see See Script Mode on page 10 displays the usage screen no argument runs 13504CFG in the interactive mode 13504CFG EXE Configuration Program 1D13504 Issue Date 01 01 30 X19A B 001 04 Page 10 Script Mode 1D13504 X19A B 001 04 Epson Research and Development Vancouver Design Center In script mode a file provides 13504CFG with all the information necessary to reconfigure the selected 13504 utility Any changes which can be made by the interactive user interface can also be done by the script file Note that it is not necessary to list all of the possible items in the script file For example if the script
356. mponents and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build the WindML v2 0 library From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get src ugl and type the command make CPU PENTIUM ugl 4 Build a boot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as the image 5 Create a bootable disk in drive A From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get config pcPentium and type mkboot a bootrom_uncmp 6 If necessary generate a new mode0 h configuration file Wind River WindML v2 0 Display Drivers Issue Date 01 04 06 Epson Research and Development Page 5 Vancouver Design Center The file mode0 h contains the register values required to set the screen resolution col or depth bpp display type active display LCD CRT rotation etc The mode0 h file included with the drivers may not contain applicable values and must be regener ated The configuration program 13504DCFG can be used to build a new mode0 h file If building for 8 bpp place the new mode0 h
357. n 15 5 SOWING a A A a EA 16 ReTerentes ia a AA A A Se Oe Oa ead 17 6 1 Dociments ico a eta a a aras A 6 2 Document Sources a a a ee ee ee ee 17 T Technical SUppON gt lt 220 Se ee Ri Se Bs Ss Geb ew A E a 18 7 1 EPSON LCD CRT Controllers S1D13504 2 2 ee we 18 7 2 Motorola MCF5307 Processor 2 2 2 a a ee ee ee ee 18 Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 011 07 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A G 011 07 Issue Date 01 02 02 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping o 11 Table 4 1 S1D13504 Configuration Settings e 14 Table 4 2 S1D13504 Host Bus Selecti0d o ee ee 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle o o e 9 Figure 2 2 MCF5307 Memory Write Cycle o e 000000000000 9 Figure 4 1 Typical Implementation of MCF5307 to 1D13504 Interface 13 Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 011 07 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MCF5307 Cold
358. n a two IT8368E implementation must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the S1D13504 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the 1D13504 When accessing the S1D13504 the associated card side signals are disabled in order to avoid any conflicts Note When a second IT8368E is used it should not be set in VGA mode For mapping details refer to Section 5 4 Memory Mapping and Aliasing For further information on configuring the IT8368E refer to the IJT8368E PC Card GPIO Buffer Chip Specification Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Page 19 Vancouver Design Center 5 4 Memory Mapping and Aliasing When the PR31500 PR31700 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 5 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping Note Bits CARDIIOEN and CARD2IOEN need to be set in the PR31500 PR31700 Memory Configuration Register 3 Table 5 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping Function Function TARTE Address size CARDnIOEN 0 CARDnIOEN 1 0800 0000h 64M byte Card 1 Attribute Card 1 IO 0C00 0000h 64M byte Card 2 Attribute Card 2 IO 6400 0000h 64M byte Card 1 Memory
359. n void BYTE Chipld int Device switch seRegisterDevice 8Cfg Devicelnfo 0 amp Cfg DeviceChip amp Device case ERR_OK break case HAL DEVICE_ERR printf ERROR Too many devices registered n exit 1 default printf ERROR Could not register S1D13504 device n exit 1 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 55 Vancouver Design Center seGetId Device amp ChipId if ChipId ID_S1D13504F00A printf ERROR Did not detect 1D13504 n exit 1 if seSetInit Device ERR_OK printf ERROR Could not initialize device n exit 1 BOK KKK KARA RAR RAR RARA RAR RARA RR RR k k RRA RR RR RARA RRA RR RR KARA RARA Fill 2M bytes of memory with Oxffffffff white Note that 0x200000 2 M bytes Divide by 4 for number of Dwords to fill ARA RRA RARA RRA RR KARA RARA RRA RR RR RARA RRA RR RR RAR RAR RR RARA RARAS seWriteDisplayDwords Device 0 Oxffffffff 0x200000 4 exit 0 9 1 2 Sample code without using 13504HAL API k k INIT13504 C sample code demonstrating the initialization of the S1D13504 ER Beta release 2 0 98 10 22 k k The code in this example will perform initialization to the following specification k k 320 x 240 single 8 bit color passive panel EX oS Tos Hz iframe rates A
360. n Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Epson Research and Development Website http www erd epson com 1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de 7 2 Motorola MC68328 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax
361. n iav eon sav zan siav zawor zn nro Law vigy oan clay Ss 10 vOds ino GND aa 1 a Zola uav on 990A Lp uyw a odoorn orgy ca DIV 01d d 6vN say Em sav h Lyn Lav 05001 251001 ov sav a rs EN sav ryn vav evn cay zvn zav ivn vay ovn ogy z ov lww in lovozlav s va T T T i 4 T I i I Epson Research and Development Vancouver Design Center 7 Schematics S1D13504 X19A G 014 01 Figure 7 1 S5U13504B00C Rev 2 0 Evaluation Board Schematics 1 of 5 2002 12 02 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date Page 26 Epson Research and Development Vancouver Design Center y pe 15 a lo Fal 2 6 be als RIGS E S 3 la lt S a 5 gH Saz lo ls e j E jE E JER zj 3 3 8 lez g j l Eo lo Al ll ll H a 249 l Qoe gt 2 5 3 ll 5 3 o 2 2 3 iN 3 7 3 E 5 3 5 El M z 2 3l fe 3 1 ella sr so alo 2 glaz a sisisisis SSS J a A A a z 53 5 a we ags z al ie a lt 05 E eSo 3 Ss 3 ae E ATi i Figure 7 2 SSUI3504B00C Rev 2 0 Evaluation Board Schematics 2 of 5 S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Page 27
362. n page 32 for summary RAS O 47 53 CO1 Output 1 Row address strobe 67 65 76 70 These pins have multiple functions 63 61 68 66 Bi directional memory data bus 59 57 64 62 During reset these pins are inputs and their states at the 55 53 60 58 Hi Z rising edge of RESET are used to configure the chip MD 15 0 10 52 54 59 61 CD2 T81 pulled 0 Internal pull down resistors typical values of 56 58 163 65 100KQ 100KQ 120KQ at 5 0V 3 3V 3 0V respectively pull 60 62 167 69 the reset states to 0 External pull up resistors can be used 64 66 75 77 to pull the reset states to 1 See Section 5 5 Summary of i Configuration Options on page 30 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 25 Vancouver Design Center Table 5 2 Memory Interface Pin Descriptions Continued Pin Pin Name Type FOOA Driver nests e Description FO2A Value FO1A 43 41 46 44 39 37 42 40 MA 8 0 O 35 34 41 43 CO1 Output O Multiplexed memory address 36 38 45 47 40 49 This pin has multiple functions e For 2M byte DRAM this is memory address bit 9 MA9 e For asymmetrical 512K byte DRAM this is memory address Hi Z bit 9 MA9 MA9 IO 45 51 C TS1 Output 0 For symmetrical 512K byte DRAM this pin can be used as general purpose IO GPIO3 See Table 5 10 Memory Interface Pin Mappin
363. nal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle The figure below illustrates a typical memory read cycle on the PC Card bus T T T A 25 0 EEE ADDRESS VALID CE1 CE2 OE WAIT D 15 0 Hi Z ES DATA VALID Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle The figure below illustrates a typical memory write cycle on the PC Card bus A 25 0 o ADDRESS VALID CE1 CE2 OE WE WAIT l Hi Z T Hi Z D 15 0 i DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the PC Card Bus S1D13504 Issue Date 01 02 02 X19A G 009 05 Page 10 3 S1D13504 Host Bus Interface The S1D13504 implements a 16 bit Generic MPU host bus interface which is used to interface to the PC Card bus The Generic MPU host bus interface is the least processor specific interface mode supported by the 1D13504 and was chosen to implement this interface due to the simplicity of its timing Epson Research and Development Vancouver Design Center The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register
364. nd B C Canada V7A 5H7 Tel 604 275 5151 Fax 604 275 2167 J Email wince erd epson com microsoft http www erd epson com Windows CE Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 VDC Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation ey X19A C 002 11 9A C 002 11 EPSON 1D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 19 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Se
365. nd that the hardware platform has been set up correctly 13504SHOW Demonstration Program Issue Date 01 01 30 EPSON S1D13504 Color Graphics LCD CRT Controller 13504SPLT Display Utility Document Number X19A B 003 05 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SPLT Display Utility X19A B 003 05 Issue Date 01 01 30 Epson Research and Development Page 3 Vancouver Design Center 13504SPLT 13504SPLT demonstrates S1D13504 split screen capability by showing two different areas of display memory on the screen simultaneously Screen shows horizontal bars and Screen 2 shows vertical bars Screen 1 memory is located at the start of the display buffer Screen 2 memory is located immedi ately after Screen 1 in the display
366. nder U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504PWR Software Suspend Power Sequencing Utility X19A B 007 04 Issue Date 01 02 01 Epson Research and Development Page 3 Vancouver Design Center 13504PWR The 13504PWR Software Suspend Power Sequencing Utility enables or disables the S1D13504 software suspend mode and LCD Refer to the section titled LCD Power Sequencing and Power Save Modes in the 1D13504 Programming Notes and Examples manual document number X19A G 002 xx Also refer to the S1D13504 Functional Hardware Specification document number X19A A 002 xx for further information The 13504PWR display utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13504CFG EXE which can be used to configure 13504PWR This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then
367. nel MCLK should be reduced or PCLK should be divided down 5 Half Frame Buffer disabled by REG 1Bh bit 0 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 121 Vancouver Design Center 12 Look Up Table Architecture Table 12 1 Look Up Table Configurations Display Mode 4 Bit Wide Look Up Table RED GREEN BLUE Black amp White 1 bank of 2 entries 4 level gray 4 banks of 4 entries 16 level gray 1 bank of 16 entries 2 color 1 bank of 2 entries 1 bank of 2 entries 1 bank of 2 entries 4 color 4 banks of 4 entries 4 banks of 4 entries 4 banks of 4 entries 16 color 1 bank of 16 entries 1 bank of 16 entries 1 bank of 16 entries 256 color 2 banks of 8 entries 2 banks of 8 entries 4 banks of 4 entries Indicates the look up table is not used for that display mode The following depictions are intended to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations 12 1 Gray Shade Display Modes 1 Bit Per Pixel Mode Green Look Up Table 0 gt 0 1 1 4 bit display data output 5 1 bit pixel data Figure 12 1 1 Bit Per Pixel 2 Level Gray Shade Mode Look Up Table Architecture Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 122 2 Bit Per
368. nel Parameter Edit 2000 2000000000000 000 17 Figure 11 13504CFG CRT Setup eei 64 ek Sea A E Eee Shae eee EH 18 Figure 12 13504CFG Edit CRT Setup escisiones S 19 Figure 13 13504CFG CRT Parameter Edit 2 2 ee ee 19 Figure 14 13504CFG Advanced Memory Setup 20 Figure 15 13504CFG Edit Advanced Memory Setup 00000000000 21 Figure 16 13504CFG Memory Parameter Edit 0 20 00 0000 0000 21 Figure 17 13504CFG Power Setip 0 se eA rr Pe we ae A AD Ree ee OS 22 Figure 18 13504CFG Edit Power Setup 2 2 2 2000 0 000 000000000000 008 23 Figure 19 13504CFG Power Parameter Edit 20 0 0 000000 000000000 23 Figure 20 13504CEG LUT S tup eir oi ae Sw Eek Oe ie Se Bae Se WAS A See 24 Figure 21 13504CFG Edit LUT Setup iv ci BSc ee ae Se edge Be aoe Ree 25 Figure 22 13504CFG LUT Parameter Edits sa 2 oa aoe eek eg Se Re ee ae ye a N 25 Figure 23 13504CEG Setup oe cn kb a a a a ba A a eb 26 Figure 24 13504CFG Setup Parameter Edit For Register Location Memory Location and Memory Size 27 1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Epson Research and Development Page 7 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG EXE Configuration Program 1D13504 Issue Date 01 01 30 X19A B 001 04 Page 8 Epson Research and Development Vancouver Design Center 13504CFG EXE 13504CFG gives a software hardware
369. nel only configuration this register should be programmed to half the panel size Vertical display height in number of lines ContentsOf ThisRegister 1 The maximum vertical display height is 1024 lines S1D13504 X19A A 002 19 Page 94 Epson Research and Development Vancouver Design Center Vertical Non Display Period Register RO REG OAh RW NE la Vertical Vertical Vertical Vertical Vertical Vertical Period E n a Non Display Non Display Non Display Non Display Non Display Non Display Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit O bit 7 bits 5 0 Vertical Non Display Period Status This is a read only status bit A 1 indicates that a vertical non display period is occurring A 0 indicates that display output is in a vertical display period Note When configured for a dual panel this bit will toggle at twice the frame rate Vertical Non Display Period Bits 5 0 These bits specify the vertical non display period height in 1 line resolution Vertical non display period height in number of lines ContentsOf ThisRegister 1 The maximum vertical non display period height is 64 lines Note This register must be programmed such that REG OAh gt 1 and REG OAh bits 5 0 1 gt REG OBh 1 REG OCh bits 2 0 1 VRTC FPFRAME Start Position Register REG OBh RW VRTC VRTC VRTC VR
370. ng edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 2 t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 UD 7 0 LD 7 0 setup to FPSHIFT falling edge 1 Ts t13 UD 7 0 LD 7 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge 10 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 min t3min 9TS 3 38min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG O4h bits 6 0 1 8 1 Ts 5 min REG O5H bits 4 0 1 8 18 Ts 6 t min REG O5h bits 4 0 1 8 9 Ts Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 82 7 4 12 16 Bit TFT Panel Timing Epson Research and Development Vancouver Design Center VNDP VDP 4 pi gt FPFRAME J FPLINE Wo U U Uo U UY R 5 1 G 5 0 B 5 1 LINEABO A O uine1 Y LINE480 i D FPLINE FEE HNDP HDP HNDP gt FPSHIFT tido ME Seen leh A DRDY Re E a oe eee di o a e we O ey E BEA 0 A t X12 Keep Note DRDY is used to indicate the first pixel
371. nning Bit 1 Screen 1 Pixel Panning Bit 0 This register is used to control the horizontal pixel panning of screen and screen 2 Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a non zero value This value represents the number of pixels panned The maximum pan value is dependent on the display mode as shown in the table below Table 8 8 Pixel Panning Selection Number of Bits Per Pixel Screen 2 Pixel Panning Bits Used 1 Bits 3 0 2 Bits 2 0 4 Bits 1 0 8 Bit 0 15 16 a bits 7 4 bits 3 0 1D13504 X19A A 002 19 Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address register See Section 10 Display Configuration on page 115 and S1D13504 Programming Notes and Examples document number X19A G 002 xx Section 4 for details Screen 2 Pixel Panning Bits 3 0 Pixel panning bits for screen 2 Screen 1 Pixel Panning Bits 3 0 Pixel panning bits for screen 1 Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center 8 2 5 Clock Configuration Register Page 101 Clock Configuration Register REG 19h RW ia n nia n A MCLK Divide PCLK Divide PCLK Divide Select Select Bit 1 Select Bit 0 bit 2 MCLK Divide Select When this bit 1 the memory clock MCLK frequency is half o
372. nologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A INTFOQUCIION rar at A Date a a iG ae aes a ee eR ais Bat Bie 7 Features ida A Gs Se A A ae el T aE 8 Installation and Configuration 9 3 1 Configuration DIP Switches dD 3 2 Configuration Jumpers 2 e a A ee ee LO 4 Technical Description lt lt 14 4 1 PELBUOS SUpport v e ee ri aada e o we 14 4 2 Non PCI Host Interface Support 2 2 2 2 14 4 2 1 CPU Interface PinMapping 2 002 000 00000048 15 4 2 2 CPU Bus Connector Pin Mapping e o 16 4 3 ECD Support s s n ia las eee RO a a TS 4 3 1 LCD Interface Pin Mapping 2 200000 00000045 19 4 3 2 Buffered LCD Connector e 20 4 33 Adjustable LCD Panel Positive Power Supply VDDH 20 4 3 4 Manual Software Adjustable LCD Panel Negative Power Supply VL
373. nsigned char 0x1234 unsigned char pRegs unsigned char pLUT int idx int rgb pRegs jx R EGIST ER_OFFS ET Initialize the chip xy Step 1 xk Enable the host interface Register 1B Miscellaneous Disable host interfac buffer enabled x 1D13504 X19A G 002 07 ET points to the starting address of the S1D13504 registers nabled half frame Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Vancouver Design Center pRegs 0x1B 0x00 0000 0000 Step 2 Disable the display FIFO Ky pRegs 0x23 0x80 Step 3 Set the memory type k k Register 1 Memory Configuration 4 ms refresh EDO pRegs 0x01 0x30 0011 0000 Step 4 Set the performance register k k Register 22 Performance Enhancement pRegs 0x22 0x24 0010 0100 Step 5 Set dual single panel WK Register 2 Panel Type 8 bit format 2 color single passive pRegs 0x02 0x1C 0001 1100 Step 6 Set the rest of the registers in order Register 3 Mod Rate mi pRegs 0x03 0x00 0000 0000 Jx Register 4 Horizontal Display Width HDP 320 pixels ER 320 8 1 39t 27h Er pRegs 0x04 0x27 0010 0111 Register 5 Horizontal Non Display Period HNDP EX PCLK de Frame
374. ntinuously through the burst Burst memory cycles are mainly intended to facilitate cache line fill from program or data memory They are typically not used for transfers to from IO peripheral devices such as the S1D13504 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them 2 2 Chip Select Module S1D13504 X19A G 011 07 In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Read Write R W signal which is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select O can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each has a unique fixed offset from a common programmable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for e Port size 8 16 32 bit e Number of wait states 0 15 or external acknowledge e Address space type e Burst or non burst cycle support e Write protect Interfacing t
375. nts of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A G 011 07 Issue Date 01 02 02 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction 5 ses a seers a a Se Sow ee EO ee a a we ie Bate 7 2 Interfacing to the MCF5307 2 ee ee 8 2 1 The MCF5307 System Bus o 8 QV hs SOVERVICW oi a a a a rs dio te 8 2 1 2 Normal Non Burst Bus Transactions e e 8 ZAS BUSE CY CIES il A A get A AA gue Aa A 10 2 2 Chip Select Module sAd aisa a A a asa 10 3 1D13504 Bus Interface o 5220 bs eee ee ee Pe ES ee 11 3 1 Generic MPU Host Bus Interface Pin Mapping 2 2 2 2 2 11 3 2 Generic MPU Host Bus Interface Signals 2 2 2 a a eee 12 4 MCF5307 To S1D13504 Interface o 13 4 1 Hardware Connections ee ee ee 13 4 2 S1D13504 Hardware Configuration 2 a a a a ee ee ee 14 4 3 Memory Register Mapping 2 2 ee ee 5 4 4 MCF5307 Chip Select Configuratio
376. o U OU U ee U UD7 LD7 oe oat A 24B X a at ON o A X UD6 LD6 ots 2061 anes X X a gt EON X UD5 LD5 PEIR 2uret aida X X E X jor ee X UD4 LD4 gt ik autre N 24164 X y X S NEEN ner A X UDS LD3 Ria AN Pies X SS X or haus i x UD2 LD2 a ee ais X X A Kare KX UD1 LD1 eae 24 s Meat Bs X X X aia eee k A X UDO LDO E AX out ns X A TAS A X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 35 Dual Color 16 Bit Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 81 Vancouver Design Center tt t2 Sync Timing gt FPFRAME FPLINE t5 MOD Data Timing FPLINE FPSHIFT UD 7 0 LD 7 0 Figure 7 36 Dual Color 16 Bit Panel A C Timing Table 7 27 Dual Color 16 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falli
377. o configure the S1D13504 IO Vpp to 3 3V In this configuration all S1D13504 IO pins are configured for 3 3V output e g LCD inter face DRAM interface RAMDAC interface etc Although the DRAM and RAMDAC devices are 5 0V parts they only require a TTL Vyy of 2 4V therefore they will operate correctly with the CMOS level output drive of the 1D13504 6 3 DRAM Support 6 4 Decode Logic The S1D13504 supports 256K x 16 as well as 1M x 16 DRAM FPM and EDO in symmetrical and asymmetrical formats The S5U13504B00C board supports 5 0V 1M x 16 EDO DRAM 42 pin SOJ package in symmet rical format providing a 2M byte display buffer This board design utilizes the Generic MPU Interface of the S5U13504 see the 1D13504 Hardware Functional Specification document number X19A A 002 xx All required decode logic between the ISA bus and the S1D13504 is provided through a TIBPAL22V10 PAL U3 socketed 6 5 Clock Input Support 1D13504 X19A G 004 06 The input clock frequency can be up to 40 0MHz for the 1D13504 A 40 0MHz oscillator U4 socketed is provided as the clock CLKI source S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 Epson Research and Development Page 15 Vancouver Design Center 6 6 Monochrome LCD Panel Support The S1D13504 supports 4 and 8 bit dual and single monochrome passive LCD panels All necessary signals are provided on the 40 pin ribbon cable header J6 The interface signa
378. o guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 5 2 S1D13504 to PR31500 PR31700 Connection using Two IT8368E Interfacing to the Philips MIPS PR31500 PR31 700 Processor 1D13504 Issue Date 01 10 26 X19A G 005 09 Page 18 Epson Research and Development Vancouver Design Center Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock This gives the system designer full flexibility in choosing the appropriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 5 3 IT8368E Configuration 1D13504 X19A G 005 09 The IT8368E provides eleven multi function IO pins MFIO The IT8368E or the first i
379. o the Motorola MCF5307 Coldfire Microprocessor Issue Date 01 02 02 Epson Research and Development Page 11 Vancouver Design Center 3 S1D13504 Bus Interface The S1D13504 implements a 16 bit Generic MPU host bus interface which is used to interface to the MCF5307 microprocessor The Generic MPU host bus interface is the least processor specific interface mode supported by the S1D13504 The Generic MPU host bus interface was chosen to implement this interface due to the simplicity of its timing and compatibility with the control signals available from the MCF5307 s General Purpose Chip Select Module The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debugging 3 1 Generic MPU Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping ros
380. o the display update it is possible that contention may occur in accessing the 1D13504 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS signal is not used for the Generic MPU host bus interface and must be connected to IO Vpp Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 Epson Research and Development Page 11 Vancouver Design Center 4 MC68328 To S1D13504 Interface 4 1 Hardware Description As mentioned earlier in this application note the MC68328 multiplexes dual functions on some of its bus control pins specifically UDS LDS and DTACK If all of these pins are available for use as bus control pins then the S1D13504 interface is a straightforward implementation of the MC68000 Bus 1 interface mode as described in the D 3504 Hardware Functional Specification document number X19A A 002 xx Following are the electrical connections required for this interface MC68328 A21 1D13504 A 20 1 D 15 0 CSB3 DTACK Vcc 470 AS UDS LDS RW CLKO Vcc Note System RESET M R AB 20 1 SD 15 0 cs WAIT BS WE1 ABO RD1 RDO BUSCLK RESET When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D1
381. o use 13504DCFSG refer to the 13504DCFG Driver Configuration Program User Manual document number X19A B 008 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header File for S1D13504 Generic Drivers option Save the new configuration as s1d413504 h in the usr src linux drivers video replacing the original configuration file Configure the video options From the command prompt in the directory usr src linux run the command make menuconfig This command will start a text based interface which allows the selection of build time parameters From the options presented select Code maturity level options Prompt for development and or incomplete drivers Console drivers options Frame buffer support Support for frame buffer devices EXPERIMENTAL EPSON LCD CRT TV controller support EPSON S1D13504 Support Advanced low level driver options xbpp packed pixels support where x is the color depth being compile for Once you have configured the kernel options save and exit the configuration utility Linux Console Driver Issue Date 01 11 19 Epson Research and Development Page 9 Vancouver Design Center 6 Compile and install the kernel Build the kernel with the following sequence of commands make dep make clean make bzImage sbin lilo if running lilo 7 Boot to the Linux operating system
382. of the S1D13504 16 Connected to AB13 of the S1D13504 17 Ground 18 Ground 19 Connected to AB14 of the S1D13504 20 Connected to AB14 of the S1D13504 21 Connected to AB16 of the S1D13504 22 Connected to AB17 of the S1D13504 23 Connected to AB18 of the S1D13504 24 Connected to AB19 of the S1D13504 25 Ground 26 Ground 27 5 volt supply 28 5 volt supply 29 Connected to RD WRH of the S1D13504 30 Connected to BS of the S1D13504 31 Connected to BUSCLK of the S1D13504 32 Connected to RD of the S1D13504 33 Connected to AB20 of the S1D13504 34 Not connected S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 Page 11 S1D13504 X19A G 004 06 Page 12 5 Host Bus Interface Pin Mapping Epson Research and Development Table 5 1 Host Bus Interface Pin Mapping Vancouver Design Center ae SH 3 MC68K Bus 1 MC68K Bus 2 Generic MPU AB 20 1 A 20 1 A 20 1 A 20 1 A 20 1 ABO AO LDS AO AO DB 15 0 D 15 0 D 15 0 D 31 16 D 15 0 WE1 WE1 UDS DS WE1 M R External Decode External Decode External Decode External Decode CS CSn External Decode External Decode External Decode BUSCLK CKIO CLK CLK BCLK BS BS AS AS Connect to lO Vpp RD WR RD WR R W R W RD1 RD RD Connect to lO Vpp SIZ1 RDO WEO WEO Connect to lO Vpp SIZO WEO WAIT WAIT DTACK DSACK1 WAIT RESET RESET RESET RESET RESET 1D13504 S5U13504B00C Rev 1 0
383. ol Update Look Up Table based on the RED 16 GREEN 16 and BLUE 16 tables defined earlier in your 2 2 3 Re Programming Registers The only register which may require modification after the initialization sequence is the Half Frame Buffer The Memory Type DUAL SINGLE and the Performance Register bits should never be modified after initialization 2 3 Disabling the Half Frame Buffer Sequence The Half Frame Buffer can be ENABLED asynchronously To DISABLE the Half Frame Buffer do the following 1 2 Disable the display FIFO REG 23 bit 7 1 Set the horizontal resolution to 0 REG 04 0 Setting the horizontal resolution 0 will shut off any Half Frame Buffer DRAM accesses within 1024 PCLK s or less 1024 PCLK s is the worst case Wait for VNDP 1 gt 0 gt 1 transitions REG OA bit 7 Waiting for 1 FRAME delay will guarantee that the Half Frame Buffer is idle Disable the Half Frame Buffer REG 1B bit 0 1 Re program the horizontal resolution to your original value Programming Notes and Examples Issue Date 01 02 01 1D13504 X19A G 002 07 Page 12 Epson Research and Development Vancouver Design Center 3 Display Buffer This section discusses how the 1D13504 stores pixels in the display buffer and where the display buffer is located 3 1 Display Buffer Location The S1D13504 requires either a 512K byte or a 2M byte block of memory to be decoded by the system System logic will determine t
384. om right corner of rectangle see note below color color of rectangle For 1 2 4 and 8 bpp color refers to the pixel value which points to the respective LUT DAC entry For 15 and 16 bpp color refers to the pixel value which stores the red green and blue intensities within a WORD Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Note seFillRect does not fill the rectangle s right and bottom sides int seGetchar void Description Gets a character from platform typically from a terminal Parameter none Return Value Character returned from platform int sePutchar int ch Description Writes a character to platform typically to a terminal Parameter ch character to send to platform Return Value ERR_OK operation completed with no problems ERR_FAILED operation failed int sePutc int device int ch Description Writes a character to platform typically to a terminal Parameter device registered device ID ch character to send to platform Return Value ERR_OK operation completed with no problems ERR_FAILED operation failed Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 52 Epson Research and Development Vancouver Design Center int seSetPixel int device int x int y DWORD color Description Writes a pixel to the display buffer Parameter device Registered device ID x horizontal coord
385. on table below Configure DACRD BLANK DACPO Configure DACRD BLANK DACPO MD8 DACWR DACRSO DACRS1 HRTC DACWR DACRSO DACRS1 HRTC VRTC VRTC as GPIO4 11 as DAC CRT outputs MD9 Configure SUSPEND pin as GPO output MD10 Active low On LCDPWR GPO polarity Active high On LCDPWR GPO polarity MD11 Reserved MD12 Reserved MD13 Reserved MD14 Reserved MD15 Reserved MN required settings for MC68328 support Table 4 2 SID13504 Host Bus Selection F Xx Xx 5 MD3 MD2 MD1 Option Host Bus Interface 0 0 0 1 SH 3 bus interface 0 0 1 2 MC68K bus 1 interface e g MC68000 0 1 0 3 MC68K bus 2 interface e g MC68030 Reserved _ required settings for MC68328 support Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 S1D13504 X19A G 013 03 Page 14 Epson Research and Development Vancouver Design Center Table 4 3 Memory Configuration MD7 MD6 Option Memory Selection 0 0 1 Symmetrical 256K x 16 DRAM 0 1 2 Symmetrical 1M x 16 DRAM 1 0 3 Asymmetrical 256K x 16 DRAM 1 1 4 Asymmetrical 1M x 16 DRAM 4 3 MC68328 Chip Select Configuration 1D13504 X19A G 013 03 In the example interface chip select CSB3 is used to control the S1D13504 A 4M byte address space is used The S1D13504 control registers are mapped into the bottom half of this address block while the display buffer is mapped into the
386. on register for CS4 Enables the S1D13504 host bus interface by writing the value 0 to REG 1 Bh At that point the software runs in a tight loop which reads the S1D13504 Revision Code Register REG 00h This allows monitoring of the bus timing on a logic analyzer This source code for the following test routine was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board It was run on the ADS and a logic analyzer was used to verify operation of the interface hardware 4 6 1 Source Code BR4 OR4 MemStart DisableReg RevCodeReg Start Loop end 1D13504 X19A G 010 06 equ equ equ equ equ mfspr andis andis oris ori stw andis oris ori stw andis oris stb lbz b 124 40 r1 IMMR Pipris Steet E20 0 r2 r2 MemStart r2 r2 0801 r2 BR4 r1 r2 r0 0 r2 r2 ffc0 r2 r2 5 0708 r2 OR4 r1 r1 r0 0 r1 r1 MemStart r1 DisableReg r1 r0 RevCodeReg r1 Loop lt r 1 CS4 base register CS4 option register upper word of S1D13504 start address address of S1D13504 Disable Register address of Revision Code Register get base address of internal registers clear lower 16 bits to 0 clear r2 write base address port size 16 bits select GPCM enable write value to base register clear r2 address mask use upper 10 bits normal CS negation delay CS clock inhibit burst write to option reg
387. on the 40 pin LCD connector J1 The interface signals are alternated with grounds on the cable to reduce cross talk and noise When supporting an 18 bit TFT D TFD panel the S1D13504 can display 64K of a possible 256K colors because only 16 of the 18 bits of LCD data are available from the 1D13504 For details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx For S1D13504 FPDAT 15 0 pin mapping for various types of panel see Table 4 4 LCD Signal Connector J1 on page 19 1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Vancouver Design Center 4 3 1 LCD Interface Pin Mapping Table 4 4 LCD Signal Connector J1 Page 19 Monochrome Passive Color Passive Panels 1D13504 Connector a z 7 Eii aa a Pin Names Pin No Single Dual Single Single Single Dual ener Format 1 Format 2 4 bit 8 bit 8 bit 4 bit 8 bit 8 bit 8 bit 16 bit 9 bit 12 bit 18 bit FPDATO 1 and 6 DO LDO DO DO LDO LDO R2 R3 R5 FPDAT1 3 D1 LD1 D1 D1 LD1 LD1 R1 R2 R4 FPDAT2 5 D2 LD2 D2 D2 LD2 LD2 RO R1 R3 FPDAT3 7 D3 LD3 D3 D3 LD3 LD3 G2 G3 G5 FPDAT4 9 DO D4 D4 D4 UDO UDO G1 G2 G4 FPDAT5 11 D1 D5 UD1 D1 D5 D5 UD1 UD1 GO G1 G3 FPD
388. only Overriding these regis ter values on the Registers page may cause the CRT to display incorrectly 13504DCFG Driver Configuration Program Issue Date 01 10 26 S1D13504 X19A B 008 03 Page 20 Epson Research and Development Vancouver Design Center Registers Tab 51D13504 Configuration Utility Build 3 The Registers tab allows viewing and direct editing the S1D13504 register values Scroll up and down the list of registers and view their configured value Hovering the mouse pointer over a register line will pop up a tooltip containing a breakdown of the contents of that register Register settings may be changed by double clicking on the register in the list Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values It is strongly recommended that the D13504 Hardware Functional Specification document number X19A B 001 xx be referred to before making an manual register settings Manually entered values may be changed by 13504DCFG if further configuration changes are made on the other tabs In this case the user is notified of the changes when they return to the registers tab Note Manual changes to the registers may have unpredictable results if incorrect values are entered S1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Epson Research and Development Page 21 Vancouver Design Center 13504DCFG Menus The following secti
389. onochrome panels only The option causes palette colors to be grayscaled for correct display on a mono panel For use with color panels this option should not be enabled The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13504CFG EXE The display driver comes with example MODE tables By default only MODEO H is used by the display driver New mode tables can be created using the 13504CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13504 Width dword 280 Height dword 1E0 Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags dword 2 Windows CE 3 x Display Drivers Issue Date 01 05 08 Epson Research and Development Page 13 Vancouver Design Center Note t
390. ons describe each of the options in the File and Help menus Export After determining the desired configuration Export permits the user to save the register information as a variety of ASCII text file formats The following is a list and description of the currently supported output formats e A C header file which lists each register and the value it should be set to e A C header file for use in developing Window CE display drivers e AC header file for use in developing display drivers for other operating systems such as Linux QNX and VxWorks UGL or WindML e A comma delimited text file containing an offset a value and a description for each S1D13504 register e An HTML file containing a Register Quick Reference C Header File Defining a Map of 51013504 Registers C Header File for S1D13504 WinCE Drivers mode0 h C Header File for 51013504 Generic Drivers s1d13504 h Close Comma Delimited File Containing Current Configuration s1d13504 csv 51013504 Register Quick Reference s1d13504 html After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Before saving the configuration file clicking the Preview button starts Notepad with a copy of the configuration file about to be saved When the C Header File for S1D13504 WinCE Drivers option is selected as the export type additional options are avail
391. or an Ethernet connection 1D13504 Supported Evaluation Platforms 13504SHOW has been tested with the following S1D13504 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC00O0 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13504 Programming Notes and Examples manual document number X19A G 002 xx Installation PC platform copy the file 13504SHOW EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13504SHOW to the system 13504SHOW Demonstration Program S1D13504 Issue Date 01 01 30 X19A B 002 05 Page 4 Usage Comments Epson Research and Development Vancouver Design Center PC platform at the prompt type 13504show b a led crt vertical Embedded platform execute 13504show and at the prompt type the command line argument Where b starts 13504SHOW at a user specified bits per pixel bpp level where can be 1 2 4 8 15 or 16 a automatically cycles through all video modes 1cd displays on the LCD panel ert displays on the CRT vertical displays vertical line pattern displays the help screen noinit bypass
392. or details Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 100 Epson Research and Development Vancouver Design Center Memory Address Offset Register 0 REG 16h RW Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 Memory Address Offset Register 1 REG 1 7h RW Memory Memory n a n a n a n a n a n a Address Address Offset Bit 9 Offset Bit 8 REG 16 bits 7 0 Memory Address Offset Bits 9 0 REG 17 bits 1 0 These bits are the 10 bit address offset from the starting word of line n to the starting word of line n 1 This value is applied to both screen 1 and screen 2 Note This value is in words and must be programmed gt REG 04h A virtual image can be formed by setting this register to a value greater than the width of the dis play The displayed image is a window into the larger virtual image See Section 10 Display Configuration on page 115 for details REG 18h Pixel Panning Register RW Screen 2 Pixel Panning Bit 3 Screen 2 Pixel Panning Bit 2 Screen 2 Pixel Panning Bit 1 Screen 2 Pixel Panning Bit O Screen 1 Pixel Panning Bit 3 Screen 1 Pixel Panning Bit 2 Screen 1 Pixel Pa
393. or supports up to two PC Card PCMCIA slots It is through this host bus interface that the S1D13504 connects to the TX3912 processor The S1D13504 can be successfully interfaced using one of three configurations e Direct connection to TX3912 see Section 4 Direct Connection to the Toshiba TX3912 on page 11 e System design using one ITE8368E PC Card GPIO buffer chip see Section 5 1 Hard ware Description Using One IT8368E on page 14 e System design using two ITE8368E PC Card GPIO buffer chips see Section 5 2 Hardware Description Using Two IT8368E s on page 16 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 3 S1D13504 Host Bus Interface The S1D13504 implements a 16 bit Generic MPU host bus interface which is used to interface to the Toshiba TX3912 processor The Generic MPU host bus interface is the least processor specific interface mode supported by the S1D13504 and was chosen to implement this interface due to the simplicity of its timing Page 9 The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until
394. ore than 40MHz REG 19h bit 2 must be set to 1 MCLK CLKI 2 There is no minimum frequency for CLKI 7 3 Memory Interface Timing 7 3 1 EDO DRAM Read Timing t1 Memory Clock t2 nl gt 13 t4 t5 t6 t7 t8 t9 al gt lt 4 gt 4 Pi Pid gt MA R C1 C2 C3 C4 RAS y CASH t10 tii rie t12 t14 i gt leti5 gt t16 gt E gt t13 MD Read di d2 XX d3 d4 Y 1D13504 X19A A 002 19 Figure 7 7 EDO DRAM Read Timing Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 47 Vancouver Design Center Table 7 7 EDO DRAM Read Timing Symbol Parameter Min Typ Max Units t1 Memory clock period 25 ns Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns t2 Random read or write cycle time REG 22h bits 6 5 01 4t1 ns Random read or write cycle time REG 22h bits 6 5 10 31 ns Row address setup time REG 22h bits 3 2 00 2 45 t1 ns t3 Row address setup time REG 22h bits 3 2 01 2t1 ns Row address setup time REG 22h bits 3 2 10 1 45 t1 ns id Row address hold time REG 22h bits 3 2 00 or 10 0 45 t1 1 ns Row address hold time REG 22h bits 3 2 01 t1 1 ns t5 Column address setup time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 CAS
395. original configuration file From the Platform window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and click on Hardware Specific Files then double click on PLATFORM REG Edit the file PLATFORM REG to match the screen resolution color depth and rotation information in MODE H For example the display driver section of PLATFORM REG should be as follows when using a 640x480 LCD panel with a color depth of 8 bpp and a SwivelView mode of 0 landscape Default for EPSON Display Driver 640x480 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x 1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D 13504 Width dword 280 Height dword 1E0 Bpp dword 8 Windows CE 3 x Display Drivers X19A E 006 01 Issue Date 01 05 08 Epson Research and Development Page 7 Vancouver Design Center ActiveDisp dword 1 Rotation dword 0 13 From the Build menu select Rebuild Platform to generate a Windows CE image file NK BIN in the project directory x myproject myplatform reldir x86_release nk bin Build for CEPC X86 on Windows CE Platform Builder 3 00 using the Command Line Interface 1 Windows CE 3 x Display Drivers Issue Date 01 05 08 Install Microsoft Windows 2000 Professional or Windows NT Workstation
396. orporates a DIP switch and several jumpers which allow both evalu ation board and S1D13504 LCD controller settings to be configured for a specified evalu ation platform 3 1 Configuration DIP Switches The S1D13504 LCD controller has 16 configuration inputs MD 15 0 which are read on the rising edge of RESET Where appropriate the S5U13504B00C hard wires some of these configuration inputs but in order to configure the S1D13504 for multiple host bus interfaces a five position DIP switch is required The following figure shows the location of DIP switch S1 on the S5U13504B00C board DIP Switch S1 Figure 3 1 Configuration DIP Switch S1 Location The following DIP switch settings configure the 1D13504 Table 3 1 Configuration DIP Switch Settings Value on this pin at rising edge of RESET is used to configure Switch Signal Closed On 1 Open Off 0 S1 1 MDO Select host bus interface MD2 MD1 Host Bus Interface 0 0 SH 3 S1 3 2 MD 2 1 0 1 MC68K 1 1 0 MC68K 2 S1 4 MD4 Big Endian S1 5 MD5 WAIT is active high MO Required configuration when used in a PCI environment S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual S1D13504 Issue Date 2002 12 02 X19A G 014 01 Page 10 Epson Research and Development Vancouver Design Center 3 2 Configuration Jumpers The S5U13504B00C has seven jumper blocks which configure various boa
397. osoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Windows CE 3 x Display Drivers X19A E 006 01 Issue Date 01 05 08 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 3 x DISPLAY DRIVERS The Windows CE 3 x display driver is designed to support the S1D13504 Color Graphics LCD CRT Controller running the Microsoft Windows CE operating system version 3 0 The driver is capable of 4 8 and 16 bit per pixel display modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at techpubs Oerd epson com Windows CE 3 x Display Drivers 1D13504 Issue Date 01 05 08 X19A E 006 01 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for 1 Windows CE Platform Builder 3 00 using the GUI interface 2 Windows CE Platform Builder 3 00 using the command line interface In all examples x refers to the drive letter where Platform Builder is installed
398. ot valid int seReadDisplayDword int device DWORD offset DWORD pDword Description Reads a dword from the display buffer Parameter device registered device ID offset offset from start of the display buffer pDword returns value of dword Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Programming Notes and Examples 1D13504 Issue Date 01 02 01 X19A G 002 07 Page 44 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center int seSetBitsPerPixel int device BYTE BitsPerPixel Description Sets the number of bpp This function is equivalent to a mode set Parameter device registered device ID BitsPerPixel desired number of bpp Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_COULD_NOT_GET_VALUE value read from registers is invalid ERR_HAL_BAD_ARG argument BitsPerPixel is invalid int seSplitInit int device DWORD Scrn1 Addr DWORD Scrn2Addr Description Sets the relevant registers for split screen Parameter device registered device ID Scrn1 Addr starting address of top image addr 0 refers to beginning of the display buffer Sern2A ddr starting address of bottom image addr 0 refers to beginning of the display buffer Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid
399. ote 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 2 Ts t13 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge 10 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 timin 13min 9TS 3 t3min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG 04h bits 6 0 1 8 1 Ts 5 t6min REG O5h bits 4 0 1 8 17 Ts 6 t7min REG O5h bits 4 0 1 8 8 Ts Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 78 Epson Research and Development Vancouver Design Center 7 4 10 Dual Color 8 Bit Panel Timing VDP VNDP k be gt FPFRAME ae FPLINE l l Mirae ti fl l l l f MOD ES X UD 3 0 LD 3 0 LINE 1 241 LINE 2 242 X LINE 239 479XLINE 240 480 LINE 1 241 X X FPLINE MOD y HDP HNDP FPSHIFT ae a es de a AT tal bl i beta elle gA ae UD3 EN Atar X aa X 1 83 X 1 R5 X 1 46 X 1 87 Y Y 1 8639 X UD2 O 1 G1 X 1 82 X 1 R4 X 1 5 X 1 B6 Y 1 R8 MH y 1 R640 E X UD1 ao 1 81 X 1 R3 X 1
400. otorola MC68K microprocessors microcontrollers e Philips MIPS PR31500 PR31700 e NEC MIPS VR4102 e 8 16 bit generic interface bus One Stage write buffer for minimum wait state CPU writes Registers are memory mapped M R pin selects between memory and register address space The complete 2M byte display buffer address space is directly and contiguously available through the 21 bit address bus 4 8 bit monochrome or 4 8 16 bit color passive LCD interface for single panel single drive displays 8 bit monochrome or 8 16 bit color passive LCD interface for dual panel dual drive displays Direct support for 9 12 bit TFT 18 24 bit TFT are supported up to 64K color depth 16 bit data External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel data bus Simultaneous display of CRT and 4 8 bit passive panel or 9 bit TFT panel e Normal mode for cases where LCD and CRT image sizes are identical e Line Doubling mode for simultaneous display of 240 line images on 240 line LCD and 480 line CRT e Even Scan and interlace modes for simultaneous display of 480 line images on 240 line LCD and 480 line CRT Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 13 Vancouver Design Center 2 4 Display Modes 2 5 Clock Source 2 6 Miscellaneous 1 2 4 8 16 bit per pixel modes supported on LCD 1 2 4 8 bit per pixel modes supported on CRT Up to 16 shades of gray
401. ower down modes or during debug states S1D13504 Figure 4 1 Typical Implementation of VR4102 to S1D13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping X19A G 007 08 Interfacing to the NEC VR4102 Microprocessor Issue Date 01 10 26 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx The tables below show only those configuration settings important to the PC Card host bus interface Table 4 1 Summary of Power On Reset Options S1D13504 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface MD1 MD2 For host bus interface selection see Table 4 2 Host Bus Interface Selection MD3 MD4 Big Endian MD5 WAIT is active high 1 insert wait state j configuration for NEC VR4102 interface Table 4 2 Host Bus Interface Selection MD3 MD2 MD1 Host Bus Interface 0 0 0 SH 3 bus interface 0 1 MC68K bus 1 interface e g MC68000 0 1 0 MC68K bus 2 interface e g MC68030 1 xX x Reserved E configuration for NEC VR4102 interface Interfac
402. oz anee EE 7a i evo eraa ziad ARRA Gaquasay L LNSUd Trea wea i sad ad Taq EX sad vad Taq zaa 180 oad K foisted s i I T Li 1 E t i i T Page 28 Issue Date 2002 12 02 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Figure 7 4 SSUI3504B00C Rev 2 0 Evaluation Board Schematics 4 of 5 1D13504 X19A G 014 01 Page 29 I I I I 1 I 1 E P E ES 200801 19qUAdas epson Seg 8 Jequiny juawinsog ER dIyO VOXp0SE1 sng Idd D008r0SELNSS ONI SW3LSAS SONES 0390 v Hago v Y9 d4 alqesip 0 saduin d peia P uuad gt dOLS v Y 318vSIa vods leha z AQUI y L Hanves anyo ANO anyo ANTO y DIANODU 2390 v ddr Wo ovo 680 889 ane ASAL oct Bra lt lonelaw y a A E EBRRREB E BEBPERER BE anyo anyo anyo anyo PERET Pe PrPPPEPP Is Le 969 sto veo 4 adno LE
403. p Table These tables are bypassed in 15 16 bpp mode These three 16 position Look Up Tables can be arranged in many different configurations to accom modate all the gray shade color display modes Look Up Table Address Register REG 24h RW an hja RGB Index RGB Index LUT Address LUT Address LUT Address LUT Address Bit 1 Bit O Bit 3 Bit 2 Bit 1 Bit 0 bits 5 4 RGB Index Bits 1 0 These bits are also used to provide access to the three internal Look Up Tables RGB Table 8 15 RGB Index Selection RGB Index Bits 1 0 Look Up Table Access Pointer Sequence 00 Auto Increment R G B LUT R n G n Bin R n 1 G n 1 01 Auto Increment Red LUT only Rin R n 1 R n 2 10 Auto Increment Green LUT only G n G n 1 G n 2 11 Auto Increment Blue LUT only B n B n 1 B n 2 bits 3 0 A write to this register with RGB Index bits 00 selected will position the internal pointer to the Red LUT Each read write access to the LUT data will increment the counter to point to the next LUT in order R to G to B to R A read write access to the Blue LUT will also automatically increment the LUT address by 1 This provides an efficient method for sequential writing of RGB data When the RGB Index bits 01 10 or 11 the internal pointer always points to the respective R G or B LUT A read write access to the LUT data will increment the LUT address by 1
404. pend mode is enabled When this bit 0 software suspend mode is disabled 1D13504 X19A A 002 19 Hardware Functional Specification Issue Date 01 11 06 Page 102 Epson Research and Development Vancouver Design Center 8 2 7 Miscellaneous Registers Miscellaneous Disable Register REG 1 Bh RW Host Interface aa wa Ala Aja a n Half Frame Disable Buffer Disable bit 7 Host Interface Disable This bit must be programmed to 0 to enable the Host Interface This bit goes high on reset When this bit is high all memory and all registers except REG 1Ah read only REG 28h through REG 2Fh and REG 1Bh are inaccessible bit O Half Frame Buffer Disable This bit is used to disable the Half Frame Buffer When this bit 1 the Half Frame Buffer is disabled When this bit 0 the Half Frame Buffer is enabled When a single panel is selected the Half Frame Buffer is automatically disabled and this bit has no hardware effect The Half Frame Buffer is needed to fully support dual panels Disabling the Half Frame Buffer reduces memory bandwidth requirements and increases the supportable pixel clock frequency but results in reduced contrast on the LCD panel This mode is not normally used except in special circumstances such as simultaneous display on a CRT and dual panel LCD See Section 11 2 on page 119 for details Note The Half Frame Buffer should be disabled only when idle The Half Frame Buffer is i
405. per is at position 2 3 the CLKI source is the same as BUSCLK provided by the non PCI host system AM Ma Innon E O JP2 an Ma LH Ey CLKI same CLKI from f as BUSCLK Oscillator U3 Figure 3 3 Configuration Jumper JP2 Location JP3 CoreVDD Current JP3 allows the mesurement of S1D13504 CoreVDD current consumption When the jumper is at position 1 2 the evaluation board is operating normally default setting When no jumper is installed Core VDD current comsumption can be measured by connecting an ampmeter to JP3 des JP3 ESO CoreVDD Normal a ries Measurement Operation Figure 3 4 Configuration Jumper JP3 Location S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 1D13504 X19A G 014 01 Page 12 JP4 IOVDD Current Epson Research and Development Vancouver Design Center JP4 allows the mesurement of S1D13504 IOVDD current consumption When the jumper is at position 1 2 the evaluation board is operating normally default setting When no jumper is installed IOVDD current comsumption can be measured by connecting an ampmeter to JP4 JP4 IOVDD Measurement a Normal Operation Figure 3 5 Configuration Jumper JP4 Location JP5 LCD Panel Voltage JP5 selects the voltage level to the LCD panel When the j
406. per pixel formats Ra Gn B represent the red green and blue color components 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 117 Vancouver Design Center 10 2 Image Manipulation The figure below shows how screen and screen 2 images stored in the image buffer are positioned on the display The screen and screen 2 images can be parts of a larger virtual image or images e REG 17h REG 16h defines the width of the virtual image s e REG 12h REG 11h REG 10h defines the starting word of the screen 1 REG 15h REG 14h REG 13h defines the starting word of the screen 2 e REG 18h bits 3 0 define the starting pixel within the starting word for screen 1 REG 18h bits 7 4 define the starting pixel within the starting word for screen 2 e REG OFh REG OEh define the last line of screen 1 the remainder of the display is taken up by screen 2 Image Buffer Display REG 1 2h REG 11h REG 10h REG 18h bits 3 0 oo Af REG 09h REG 08h 1 lines Screen 1 Line 0 ae Line 1 Screen 1 REG 15h REG 14h REG 13h Line REG OFh REG OEh REG 18h bits 7 4 as Screen 2 A Screen 2 REG 04h 1 8 pixels REG 17h REG 6h Figure 10 3 Image Manipulation Hardware Functional Specification S1D1
407. platform copy the file 13504VIRT EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13504VIRT to the system S1D13504 X19A B 004 05 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform at the prompt type 13504virt A W Embedded platform execute 13504virt and at the prompt type the command line argument Where no argument panning and scrolling is performed manually a panning and scrolling is performed automatically W for manual mode specifies the width of the virtual display which must be a multiple of 8 and less than 1024 the default width is 1024 pixels the maximum height is based on the display memory and the width of the virtual display The following keyboard commands are for navigation within the program Manual mode T scrolls up y scrolls down E pans to the left gt pans to the right HOME moves the display screen so that the upper right of the virtual screen shows in the upper right of the display END moves the display screen so that the lower left of the virtual screen shows in the lower left of the display Automatic mode Z changes the direction of screen Both modes B changes the color depth bits per pixel ESC exits 13504VIRT 13504VIRT Example 1 Type 13504virt a to automatically pan and scroll 2 Press b to change the bits per pixel from 1 bit per pixel to 2 bits per pixel 3 Repeat steps and 2 for the
408. platformicepcidriversidisplayiS1D13504 replacing the original configura tion file 10 Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotation information in MODE H PLAT FORM REG is located in x wince platform cepc files Windows CE 2 x Display Drivers 1D13504 Issue Date 01 05 25 X19A E 001 05 Page 6 Epson Research and Development Vancouver Design Center For example the display driver section of PLATFORM REG should be as follows when using a 640x480 LCD panel with a color depth of 8 bpp in Swivel View 0 landscape mode Default for EPSON Display Driver 640x480 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13504 Width dword 280 Height dword 1E0 Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 11 Delete all the files in the x wince release directory and delete x wince plat form cepc bif 12 Generate the proper building environment by double clicking on the sample project icon i e X86 DEMO7 13 Type BLDDEMO lt ENTER gt at the command prompt of the X86 DEMO7 window to generate a Windows CE image file NK BIN Build for CEPC X86 on Windows CE Platform Builder 2 1x using a Command Line Interface 1D13504 X19A E 001 05 Throughout this section 2 1x refers to either 2 11 or 2 12 as appropriat
409. power supply 23V to 40V CPU Bus interface header strips for non ISA bus support S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date 01 02 02 X19A G 004 06 Page 8 2 Installation and Configuration Epson Research and Development Vancouver Design Center The 1D13504 has 16 configuration inputs MD 15 0 which are read on the rising edge of RESET S1D13504 configuration inputs MD 5 1 are fully configurable on this evaluation board for different host bus selections one five position DIP switch is provided for this purpose All remaining config uration inputs are hard wired See the S1D13504 Hardware Functional Specification document number X19A A 002 xx for more information When using the S5Ul13504B00C with the ISA bus the following are the recommended settings Table 2 1 Configuration DIP Switch Settings Switch Signal Closed Open SW1 1 MD1 SW1 2 MD2 See Host Bus Selection table below See Host Bus Selection table below SW1 3 MD3 SW1 4 MD4 Little Endian Big Endian SW1 5 MD5 Wait signal is active high Wait signal is active low The polarity of the Configuration DIP Switches is closed 1 or high open 0 or low required settings for ISA bus support Table 2 2 Host Bus Selection MD3 MD2 MD1 Option Host Bus Interface 0 0 1 SH 3 bus interface 0 0 1 2 MC68K bus 1 interface e g MC68000 0 1 0 3
410. pp color 1 bank of 16 1 bank of 16 1 bank of 16 16 colors 8 bpp color 2 banks of 8 2 banks of 8 4 banks of 4 256 colors 15 bpp color 4096 colors 16 bpp color 4096 colors On a TFT panel the effective colors are determined by the interface width i e 9 bit 512 12 bit 4096 18 bit 64K colors Passive panels are limited to 12 bits 4096 through the frame rate modulator Indicates the look up table is not used for that display mode Programming Notes and Examples Issue Date 01 02 01 1D13504 X19A G 002 07 Page 18 Color Modes 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center In color mode the S1D13504 supports three 16 position 4 bit wide color LUTs red green and blue Depending on the selected pixel size these LUTs will provide from 1 to 4 banks 1 bpp Color In 1 bpp color mode the LUT is limited to a single 2 entry bank per color The LUT bank select bits have no effect in this mode The following table shows the recommended values for obtaining a Black and White mode while on a color panel Table 3 8 Recommended LUT Values for 1 bpp Color Mode Address Red Green Blue Address Red Green Blue 00 00 00 00 08 00 00 00 01 OF OF OF 09 00 00 00 02 00 00 00 0A 00 00 00 03 00 00 00 0B 00 00 00 04 00 00 00 0C 00 00 00 05 00 00 00 0D 00 00 00 06 00 00 00 OE 00 00 00 07 00 00 00 OF 00 00 00 2
411. pping 2 2 2 9 3 2 Generic MPU Host Bus Interface Signals 2 2 2 10 4 MC68328 To S1D13504 Interface 11 4 1 Hardware Description 2 2 eee ee 11 4 2 S1D13504 Hardware Configuration 2 2 2 eee ee ee 13 4 3 MC68328 Chip Select Configuration 14 SOMWare ac ae te es AAA dn ee co ete a a as aA See 15 References Wii it a As an eel aed 16 6 1 Documents i a a th se ee we a a a oe ee ias 16 6 2 Document Sources 2 0 0 0 0 0 ee ee ee ee ew ew 6 7 Technical Support cer asi eee A eee IR ees 17 7 1 EPSON LCD CRT Controllers S1D13504 2 2 02 2 2 2 2 2 17 72 Motorola MC68328 Processor 2 2 ee ee 17 Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13504 Issue Date 01 10 26 X19A G 013 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping o 9 Table 4 1 Summary of Power On Reset Options o e o 13 Table 4 2 S1D13504 Host Bus Selection 2 0 2 0 0 00200000022 ee 13 Table 4 3 Memory Configuration 0 0 2 ee 14 List of Figures Figure 4 1 Block Dia
412. processor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 3 S1D13504 Host Bus Interface The S1D13504 implements a 16 bit Generic MPU host bus interface which is used to interface to the MPC821 processor The Generic MPU host bus interface is the least processor specific interface mode supported by the S1D13504 Although the Power PC bus is similar in many respects to the M68K bus the Generic MPU host bus interface was chosen for this interface due to the simplicity of its timing and compatibility with the control signals available from the MPC821 General Purpose Chip Select Module Page 13 The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the 1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debugging 3 1 Generic MPU Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Table 3 1 Generic MPU Host Bus Interface Pin Mapping
413. products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A INTFOQUCIION sun oars 6 arabs 8 ay a CGO ae ae aN Go Ae a Saree 7 Interfacing to the TX3912 8 S1D13504 Host Bus Interface 9 3 1 Generic MPU Host Bus Interface Pin Mapping 2 2 2 2 2 2 2 2 9 3 2 Generic MPU Host Bus Interface Signals 2 wee 10 4 Direct Connection to the Toshiba TX3912 2 000002 2 eee 11 4 1 Hardware Description 2 ee ee 11 4 2 Memory Mapping and Aliasing 12 4 3 1D13504 Hardware Configuration 2 eee ee eee 18 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description Using One IT8368E 2 2 2 2 14 5 2 Hardware Descr
414. pson di rectory xcopy s e x wince public maxall wince public epson c Rename x wince public epson maxall bat to epson bat d Edit EPSON BAT to add the following lines to the end of the file echo on set CEPC_DDI_S1D13504 1 echo off 6 Make an S1D13504 directory under x wince platform cepc drivers display and copy the 1D13504 driver source code into x wince platform cepc drivers dis play S 1D13504 7 Edit the file x wince platform cepc drivers display dirs and add S1D13504 into the list of directories 8 Edit the file x wince platform cepc files platform bib and make the following two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13504 ddi dll FLATRELEASEDIR epson dll NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_S1D13504 Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGASBPP Windows CE 2 x Display Drivers 1D13504 Issue Date 01 05 25 X19A E 001 05 Page 8 10 11 S1D13504 X19A E 001 05 Epson Research and Development Vancouver Design Center ddi dll S FLATRELEASEDIRNddi_s364 dll NK SH ENDIF ENDIF ENDIF ENDIF Insert this line The file MODEO H located in x wince platform cepc drivers display S 1D13504 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before buildin
415. ption FO2A Value FO1A This pin has multiple functions Hi Z e Horizontal Retrace signal for CRT HRTC IO 102 116 C CN3 Oo o General Purpose IO GPIO10 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 This pin has multiple functions Hi Z e Vertical Retrace signal for CRT VRTC IO 103 117 C CN3 Supe 0 General Purpose IO GPIO11 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 This pin has multiple functions Hi Z e Blanking signal for DAC BLANK IO 85 95 C CN3 Sl o General Purpose IO GPIO5 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 DACCLK O 86 96 C CN3 OutputO Pixel Clock for RAMDAC 1 When configured as IO pins 1D13504 X19A A 002 19 Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center 5 4 6 Miscellaneous Table 5 6 Miscellaneous Pin Descriptions Page 29 Pin Pin Name Type FOOA Driver Heseree Description F02A Value FO1A This pin has multiple functions e When MD9 0 at rising edge of RESET this pin is an active low input used to place the S1D13504 into suspend mode see Section 13 Power Save Modes Hi Z on page 127 for details SUSPEND IO 106 120 CSITST output When MD 10 9 01 at rising edge of RESET this pin is an output with a reset state of 0 Its state is controlled by REG 21h bit 7 e
416. r S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program ERROR Did not detect S1D13504 The HAL was unable to read the revision code register on the S1D13504 Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly S1D13504 X19A B 004 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504VIRT Display Utility X19A B 004 05 Issue Date 01 01 30 EPSON 1D13504 Color Graphics LCD CRT Controller 13504PLAY Diagnostic Utility Document Number X19A B 005 05 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504PLAY Diagnostic Utility X19A
417. r the area in which the S1D13504 resides must be set to a non zero value 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Table 7 1 SH 3 Interface Timing Page 37 Symbol Parameter Min Max Units t1 Clock period 25 ns t2 Clock pulse width high 5 ns t3 Clock pulse width low 5 ns t4 A 20 0 M R RD WR setup to CKIO 4 ns t5 A 20 0 M R RD WR hold from CS 0 ns t6 BS setup 3 ns t7 BS hold 0 ns t8 CSn setup 0 ns t9 Falling edge RD to D 15 0 driven 3 ns t10 Rising edge CSn to WAIT tri state 0 4 ns t111 Falling edge CSn to WAIT driven 1 11 ns t12 CKIO to WAIT delay 3 15 ns t13 D 15 0 setup to first CKIO after BS write cycle 0 ns t14 D 15 0 hold write cycle 0 ns t15 D 15 0 valid to WAIT rising edge read cycle 0 ns t16 Rising edge RD to D 15 0 tri state read cycle 2 9 ns 1 If the S1D13504 host interface is disabled the timing for WAIT driven is relative to the fall ing edge of CSn or the first positive edge of CKIO after A 20 0 and M R become valid whichever occurs later 2 Ifthe S1D13504 host interface is disabled the timing for D 15 0 driven is relative to the fall ing edge of RD or the first positive edge of CKIO after A 20 0 and M R become valid whichever occurs later Hardware Functional Specification Issue Date 01 11 06
418. r the input clock frequency the higher the frame rate performance and power consumption CPU interface the S1D13504 IO Vpp current consumption depends on the BUSCLK frequency data width number of toggling pins and other factors the higher the BUSCLK the higher the CPU performance and power consumption Core Vpp IO Vpp voltage levels the voltage levels of the two independent VDD groups Core IO affect power consumption the higher the voltage the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There are two power save modes in the S1D13504 Software and Hardware SUSPEND The power consumption of these modes is also affected by various system design variables DRAM refresh mode CBR or self refresh self refresh capable DRAM allows the S1D13504 to disable the internal memory clock thereby saving power CPU bus state during SUSPEND the state of the CPU bus signals during SUSPEND has a substantial effect on power consumption An inactive bus e g BUSCLK low Addr low etc reduces overall system power consumption CLKI state during SUSPEND disabling the CLKI during SUSPEND has substantial power savings 1D13504 X19A G 006 04
419. r_word 640 16 40 words per line screenl_size offset lines 40 480 19 200 words 0x4B00 words Set the screen 2 start address to the value we just calculated Write the screen 2 start address registers 13h 14h and 15h with the values 0x00 0x4B and 0x00 respectively 1D13504 X19A G 002 07 Page 30 Epson Research and Development Vancouver Design Center 5 LCD Power Sequencing and Power Save Modes 5 1 Introduction to LCD Power Sequencing LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD signals Power sequencing is required to prevent long term damage to the panel and to avoid unsightly lines on power down and start up LCD Power Sequencing is performed on the S1D13504 through a software procedure even when using hardware power save modes Most green systems today use some sort of software power down procedure in conjunction with external circuitry to set hardware suspend modes These proce dures typically save restore state information or provide a timer prior to initiating power down The S1D13504 requires a timer between the time the LCD power is disabled and the time the LCD signals are shut down Conversely the LCD signals must be active prior to the power supply starting up For simplicity we have chosen to use the same time value for power up and power down proce dures The time interval required varies depending on the power supply design The power s
420. ration completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_COULD_NOT_GET_VALUE value read from registers is invalid int seGetBytesPerScanline int device int pBytes Description Determines the number of bytes per scan line of current display mode It is assumed that the registers have already been correctly initialized before seGetBytesPer Scanline is called Parameter device registered device ID pBytes pointer to an integer which indicates the number of bytes per scan line Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGetLastUsableByte int device DWORD pLastByte Description Determines the address of the last byte in the display buffer which can be used by applications Addresses following LastByte are reserved for system use such as the half frame buffer for dual panels It is assumed that the registers have already been correctly initialized before seGetLastUsableByte is called Parameter device registered device ID pLastByte pointer to an integer which indicates the number of bytes per scan line Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGetLinearDispAddr int device DWORD pDispLogicalAddr Description Determines the logical address of the start of the display buffer This address may be used in programs for direct control o
421. rch and Development Page 35 Vancouver Design Center Table 6 4 Output Specifications Symbol Parameter Condition Min Typ Max Units Low Level Output Voltage Type 1 TS1 CO1 TS1D lo 3mA VoL Type 2 TS2 CO2 lo 6mA 0 4 X Type 3 TS3 CO3 loL 12mA High Level Output Voltage Type 1 TS1 CO1 TS1D lo 1 5 mA g VoH Type 2 TS2 CO2 loL 3 mA IO Nop 0 4 E Type 3 TS3 CO3 lo 6 mA IO Vop Max loz Output Leakage Current Vou Vpp 1 1 uA VoL Vss Cout Output Pin Capacitance 10 pF CID Bidirectional Pin Capacitance 10 pF Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 36 Epson Research and Development Vancouver Design Center 7 A C Characteristics Conditions IO Vpp 2 7V to 5 5V unless otherwise specified Ta 40 C to 85 C Tise and Tra for all inputs must be lt 5 nsec 10 90 C 50pF Bus MPU Interface C 100pF LCD Panel Interface C 10pF Display Buffer Interface C 10pF CRT DAC Interface 7 1 CPU Interface Timing 7 1 1 SH 3 Interface Timing t4 t5 gt A 20 0 M R RD WR t6 t7 gt gt BS iz t8 t12 t CSn t9 t10 gt e WEn RD t11 t12 gt i gt WAIT ti3 __ p t14 D 15 0 write t15 t16 gt e sa D 15 0 read y Figure 7 1 SH 3 Interface Timing Note The SH 3 Wait State Control Register fo
422. rd settings The jumper positions for each function are shown below Table 3 2 Jumper Settings Jumper Function Position 1 2 Position 2 3 Jumper Off JP1 BUSCLK Selection BUSCLK from H2 header n a JP2 CLKI Selection CLKI is the same as BUSCLK n a Current measurement for JP3 CoreVDD current n a CoreVDD Current measurement for JP4 IOVDD current n a IOVDD JP5 LCD Panel Voltage 5V LCDVCC n a JP6 Panel Enable Polarity LCDPWR active low n a JP7 PCI FPGA enable Diable FPGA for non PCl host n a JP1 BUSCLK Selection JP1 selects the source for BUSCLK When the jumper is at position 1 2 the BUSCLK source is provided by the oscillator at U2 default setting When the jumper is at position 2 3 the BUSCLK source is provided by the non PCI host system Note When used in a PCI environment JP1 must be set to the 1 2 position inon E JP1 or lil O aa A i i E BUSCLK BUSCLK from i M gt gt from H2 Oscillator U2 O Figure 3 2 Configuration Jumper JP 1 Location S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Vancouver Design Center JP2 CLKI Selection JP2 selects the source for CLKI Page 11 When the jumper is at position 1 2 the CLKI source is provided by the oscillator at U3 default setting When the jum
423. rdware Coup ibe badge te ae SY fo 38 Ee ae a ae ES 4 4 Register Memory Mapping 2 2 2 2 19 4 5 MPC821 Chip Select Configuration 19 4 6 Test Softwares Ses fe we eh eet ib gt Ap Ae A A ee Oe eee es e 4 61 Source Codes L y eri o Gos oP he Sao ee E a andaa 4 ed wae a 20 SoftWare a sd ee eS Re ws ee Gee ae Re eae ees 22 References sta as Ge A ee ee eA ee re AA A a 23 6 1 Documents 2 38 48 A A che RO A A a DS 6 2 Document Sources e 2 7 Technical Support s sa 4 a eaa 0 RA A A AA A A 24 7 1 EPSON LCD CRT Controllers S1D13504 2 2 24 7 2 Motorola MPC821 Processor 1 ee ee ee A Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping Table 4 1 List of Connections from MPC821ADS to 1D13504 Table 4 2 Summary of Power On Reset Options 2 000000 2 eee 18 Table 4 2 Host Bus Interface Selection 0 2 0 0 0000000002 2G 18 List of Figures Figure 2 1 PowerPC Memory Read Cycle o o 00000200007 9 Figure 2 2 PowerPC Memory Write Cycle o 02 20 0000 0000
424. re RAS Refresh Timing 52 EDO DRAM Self Refresh Timing e 53 FPM DRAM Read Timing 2 000 000 0002 eee ee 54 FPM DRAM Write Tiago 56 FPM DRAM Read Write Timing 2 2 2 2 0 0 000 000 00000000 58 FPM DRAM CAS Before RAS Refresh Timing o 60 FPM DRAM CBR Self Refresh Timing e 61 LCD Panel Power On Reset Timing 0 00000 00 0000000 62 LCD Panel Suspend Timing 0 2 200 000 0200 00000 63 Single Monochrome 4 Bit Panel Timing e 64 Single Monochrome 4 Bit Panel A C Timing e 65 Single Monochrome 8 Bit Panel Timing o 66 Single Monochrome 8 Bit Panel A C Timing e e 67 Single Color 4 Bit Panel Timing 68 Single Color 4 Bit Panel A C Timing 0 0 02 0 0000 69 Single Color 8 Bit Panel Timing Format 1 o o e 70 Single Color 8 Bit Panel A C Timing Format 1 oo o e 71 Single Color 8 Bit Panel Timing Format 2 0 0 00 00 0040 72 Single Color 8 Bit Panel A C Timing Format 2 o a 73 Single Color 16 Bit Panel Timing 2 00 0 0000008 74 Single Color 16 Bit Panel A C Timing 2 2 2 20 0 0 000 020 0000 008 75 Dual Monochrome 8 Bit Panel Timing e 76 Dual Monochrome 8 Bit Panel A C Timing e
425. re Riesstrasse 15 25 Harbour Road 80992 Munich Germany Wanchai Hong Kong Tel 089 14005 0 Tel 2585 4600 Fax 089 14005 110 Fax 2827 4346 7 2 PC Card Standard PCMCIA Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pc card com Interfacing to the PC Card Bus Issue Date 01 02 02 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13504 X19A G 009 05 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 EPSON S1D13504 Color Graphics LCD CRT Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X19A G 010 06 Copyright O 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate
426. re Suspend Power Sequencing Utility X19A B 007 04 Issue Date 01 02 01 EPSON S1D13504 Color Graphics LCD CRT Controller 13504DCFG Driver Configuration Program Document Number X19A B 008 03 Copyright O 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 13504DCEG iE arc a es he ea oe be eee eh en ee O pe aie ee EA 5 Installation oo ok ee a e ee a oe fe a HO Usar S45 E a te er he Seog 13504DCFG Configuration Tabs General Tab ci a A Se a Pe Boe Bix 7 Preferences Tab w tie ied A ia BNE ek ee byte rk a 9 Memor
427. re must be taken when enabling Suspend Mode with respect to the external Power Supply used to provide the LCD Drive voltage The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage Controlling the LCD Drive Power Supply can be done using the S1D13504 LCDPWR output signal or by other means The following example assumes that the LCDPWR pin is being used 5 4 1 Suspend Enable Sequence Enable Suspend Software Suspend REG 1A bit 0 1 or Hardware Suspend enabled by the SUSPEND input pin MA9 0 LCDPWR will go to its inactive state within one vertical frame while maintaining the LCD interface signals for 128 Vertical Frames with the exception of FPFRAME which goes inactive at the same time as LCDPWR If 128 frames is not enough time to allow the LCD Drive power supply to decay to OV LCDPWR can be controlled manually using REG 1A bit 3 After the 128 frame delay the various clock sources may be disabled depending on the specific application and DRAM Refresh options The actual time for the 128 frame delay can be shortened by using the following example Shortening the 128 Frame delay using Software Suspend 1 Disable the Display FIFO blank the screen 2 Change the Horizontal and Vertical resolution to the minimum values allowed by the registers 3 Enable Software Suspend this same 128 frame delay still applies however the actual frame period is now greatly reduced 4
428. recharge time REG 22h bits 3 2 10 1t1 1 ns RECs ey bits 3 2 00 or 10 anne Loot ME t11 AE A bits 3 2 00 or 10 a ASS ns RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 01 1t1 2 11 ns RAS to CAS delay time REG 22h bit 4 0 and bits 3 2 01 2t1 2 2t1 ns Access time from RAS 2t1 2 hs REG 22h bit 4 1 and bits 3 2 00 or 10 t12 EN nae Ae bits 3 2 00 or 10 dls ns Access time from RAS REG 22h bit 4 1 and bits 3 2 01 1 45t1 2 ns Access time from RAS REG 22h bit 4 0 and bits 3 2 01 2 45 t1 2 ns t13 Access time from CAS 0 45 t1 1 ns t14 Access time from CAS precharge 111 2 ns t15 Read Data hold from CASH or RAS 2 ns Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 56 Epson Research and Development Vancouver Design Center 7 3 7 FPM DRAM Write Timing ti Memory Clock 4 gt la 13 Pa t4 gt t5 t6 t8 t9 MA R C1 C2 C3 C4 A A t7 RAS basal CAS WE t12 t13 e t10 be t11 i t14 t15 gt MD Write dt X d3 d4 Figure 7 13 FPM DRAM Write Timing 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Vancouver Design Center Table 7 13 FPM DRAM Write Timing Page 57 Symbol
429. ress and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the MCF5307 architecture The bus can support two types of cycle normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions S1D13504 X19A G 011 07 The bus master initiates a data transfer by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size indicates whether the bus cycle is 8 16 or 32 bits in width e R W set high for read cycles and low for write cycles e TT 1 0 Transfer Type Signals provides more detail on the type of transfer being attempted e TIP Transfer In Progress asserts whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle completing the bus transaction Once TA has b
430. rical Components Website http www toshiba com taec e Epson Research and Development Website http www erd epson com 1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 Epson Research and Development Page 23 Vancouver Design Center 8 Technical Support 8 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de 8 2 Toshiba MIPS TX3912 Processor http www toshiba com taec nonflash indexproducts html 8 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http
431. riod 5 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 UD 7 0 LD 7 0 setup to FPSHIFT falling edge 2 Ts t13 UD 7 0 LD 7 0 hold to FPSHIFT falling edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge 18 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 min t3min 9TS 3 min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 33 Ts 4 t5min REG O4h bits 6 0 1 8 1 Ts 5 min REG O5h bits 4 0 1 8 25 Ts 6 t min REG 05h bits 4 0 1 8 16 Ts Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 76 Epson Research and Development Vancouver Design Center 7 4 9 Dual Monochrome 8 Bit Panel Timing VDP VNDP f T FPFRAME FPLINE I j j Hee 20 ll fl fl j j MOD tee X UD 3 0 LD 3 0 LINE 1 241 X LINE 21242 X LINE 3 243 X LINE 4 244 XLINE 299 479 LINE 240 480 LINE 1 241 LINE 2l242 FPLINE MOD a HDP ds HNDP gt id AIDA NL E UD3 a A 11 Xis X X eX X X 1 637 f Y UD2 ek me X 16 XX RN AO O EN X UDI q va X 17 XK AX X XK Ka X UDO 14 X18 y 4 X Y X 1 640 i LD3 o 241 1 X 241 5 X Y S
432. rocessor In the direct connection implementation the S1D13504 occupies PC Card slot 1 of the TX3912 Although the address bus of the TX3912 is multiplexed it can be demultiplexed using an advanced CMOS latch e g 74ACT373 The direct connection implementation makes use of the Generic MPU host bus interface capability of the S1D13504 The following diagram demonstrates a typical implementation of the TX3912 to S1D13504 interface S1D13504 TX3912 i gt RDO RD gt RD1 WE CARD1CSL 0 gt WEO CARD1CSH e gt WE1 q j gt CS Latch A23 gt M R ALE System RESET RESET A 12 0 A 20 13 AB 20 13 gt AB 12 0 D 31 24 gt DB 7 0 D 23 16 4 gt DB 15 8 Von 15K pull up CARD1WAIT WAIT ENDIAN See text gt BUSCLK DCLKOUT Clock divider gt Or Oscillator gt CLKI Note When connecting the S1D13504 RESET pin the system designer should be aware of all conditions that may reset the S1D13504 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of TX3912 to SID13504 Direct Connection Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping Interfacing to the Toshiba MIPS TX3912 Processor 1D13504 Issue Date 01 10 26 X19A G 012 05
433. roller providing an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 Microprocessor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 2 1 2 LCD Memory Access Cycles Page 9 Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS H is driven low The read or write enable signals RD or WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable SHB is driven low for 16 bit transfers and high for 8 bit transfers The following figure illustrates typical NEC VR4102 memory read and write cycles to the LCD controller interface TCLK H US wy UY VY YZ ADD 25 0 x VALID SHB x LCDCS WR RD D 15 0 write VALID Hi Z E Y VALID hiz LCDRDY Figure 2 1 NEC VR4102 Read Write Cycles Interfacing to the NEC VR4102 Microprocessor S1D13504 Issue Date 01 10 26 X19A G 007 08 Page 10 3 S1D13504 Host Bus Interface The S1D13504 implements a 16 bit Generic MPU host bus interface which is used to interface to the VR4102 microprocessor The Generic MPU host bus interface is the least processor specific inter
434. rt DRAM Support Decode Logic Clock Input Support Monochrome LCD Panel een Color Passive LCD Panel Support Color TFT LCD Panel Support External CMOS RAMDAC Support Power Save Modes Core VDD Power Supply IO VDD Power Supply Adjustable LCD Panel Negative Power Supply Adjustable LCD Panel Positive Power Supply CPU Bus Interface Header Strips Schematic Notes S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 02 Page 3 1D13504 X19A G 004 06 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Configuration DIP Switch Settings 2 2 ee 8 Table 2 2 Host Bus Sel ctiom s 23 0 cea Dia a he a OE Ae A AE A A O ee g 8 Table2 3 Jumper Settngs Hor A BERLE RSS ole Fee a Be SARS Gale ee 8 Table 3 1 LCD Signal Connector J6 ee 9 Table 4 1 CPU BUS Connector H1 Pinout aoaaa ee ee 10 Table 4 2 CPU BUS Connector H2 Pinout ee 11 Table 5 1 Host Bus Interface Pin Mapping 12 List of Figures Figure 1 S1D13504B00C Schematic Diagram 1 of 6 2 0 Lc eee eee 20 Figure 2 S1D13504B00C Schematic Diagram 2 of 6 2 0 2 ce eee eens 21 Figure 3 S1D13504B00C Schematic Diagram 3 of 6 1 2 2 eects 22 Figure 4 S1D13504B00C
435. rtain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13504 8bpp File config h or x 13504 1 6bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build aboot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as the image 4 Create a bootable disk in drive A From a command prompt in the directory x Tornado target config pcPentium type mkboot a bootrom_uncmp 5 Ifnecessary generate a new mode0 h configuration file The file mode0 h contains the register values required to set the screen resolution col or depth bpp display type active display LCD CRT etc The mode0 h included with the drivers sets the display for 640x480 60 Hz output to a CRT display If this setting is inappropriate then mode0 h must be regenerated The configuration program 13504DCFG can be used to build a new mode0 h file If building for 8 bpp place the new mode0 h file in x 13504 8bpp File If building for 16 bpp place the new mode0 h file in x1113504 16bppWFile Wind River UGL v1 2 Display Drivers Issue Date 01 02 01 Epson Research and Development Page 5 Vanco
436. rtical non display period REG ODh 0000 1101 0000 1101 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0110 0000 0110 0000 0001 0000 0001 0000 0001 set MCLK and PCLK divide REG 24h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT load LUT load LUT load LUT load LUT load Look Up Table REG 27h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table to bank 0 Table 9 2 Passive Dual Panel Passive Passive Passive Register 8 Bit Dual 8 Bit Dual 16 Bit Dual Notes 640X480 60Hz 640X480 60Hz 640X480 60Hz Monochrome Color Color REG 02h 0001 0010 0001 0110 0010 0110 set panel type REG O3h 0000 0000 0000 0000 0000 0000 set MOD rate REG 04h 0100 1111 0100 1111 0100 1111 set horizontal display width REG O5h 0000 0101 0000 0101 0000 0101 set horizontal non display period REG O8h 1110 1111 1110 1111 1110 1111 set vertical display height bits 7 0 REG O9h 0000 0000 0000 0000 0000 0000 set vertical display height bits 9 8 REG OAh 0000 0001 0000 0001 0000 0001 set vertical non display period REG ODh 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0011 0000 0011 0000 0011 set MCLK and PCLK divide REG 1Bh 0000 0000 0000 0000 0000 0000 enable half frame buffer REG 24h 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT loa
437. s Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES and click NEXT Click Have Disk Specify the location of the driver files and click OK Click Next Click Finish Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 Ze Install the evaluation board in the computer and boot the computer Windows will detect the card Select DRIVER FROM DISK PROVIDED BY MANUFACTURER Click OK Specify a path to the location of the driver files Click OK Windows will find the S1D13XXX INF file Click OK Click OK and Windows will install the driver S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 8 Epson Research and Development Vancouver Design Center All ISA Bus Evaluation Cards X00A E 003 04 10 11 12 13 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES from the HARDWARE TYPES list Click HAVE DISK Specify the location of the driver files and click OK Select the file S1D13XXX INF and click OK Click OK The EPSON PCI Bridge Card should be selected in the list window Click NEXT Click NEXT Click Finish S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue
438. s refer to Section 6 References on page 16 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO access cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles 1D13504 X19A G 009 05 A data transfer is initiated when the memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus Issue Date 01 02 02 Epson Research and Development Page 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable sig
439. s S WEH Control 2 CASH DRAM S Memory Type EDO DRAM S EDO R W Delay 2 MCLE S DRAM Speed 68 ns S Perf Enhancement ENABLE S Page Size FFFFFFFF Chex S Figure 15 13504CFG Edit Advanced Memory Setup Memory Parameter Edit When a selection is highlighted for editing in the Edit Advanced Memory Setup window and Edit is clicked the Memory Parameter Edit window is displayed for parameter editing See figure 16 13504CFG Memory Parameter Edit below In this example window Refresh Time 4000 Cycles can be edited d Refresh Time 4000 cycles Cancel Help Figure 16 13504CFG Memory Parameter Edit 1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Epson Research and Development Page 23 Vancouver Design Center Power Management Power Setup When Power Management is selected from the Device menu the Power Setup dialog box is displayed To select a power assignment highlight it in the example window below Power Type 0 is highlighted and click OK If the highlighted power assignment needs changes click Edit and see the next section Edit Power Setup Whenever a power assignment is edited or selected in the Power Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configu ration In addition to OK Cancel and Edit commands a Help command is listed in the Power setup windows
440. s a Maxim MAX754 LCD Contrast Controller to provide this voltage range VDDH can be adjusted using RV 1 200Q potentiometer to provide an output voltage from 24V to 40V To enable the VDDH power supply the evaluation board uses the LCDPWR output from the 1D 13504 inverted by U6 to control the MAX754 as shown in the following table Table 4 5 Controlling the MAX754 1D13504 Output Signal Turn MAX754 On Turn MAX754 Off LCDPWR low high Note When manually adjusting the voltage set the potentiometer according to the panel s specific power requirements before connecting the panel 4 3 4 Manual Software Adjustable LCD Panel Negative Power Supply VLCD Most passive monochrome LCD panels require a negative bias voltage between 14V and 24V The S5U13504B00C uses a Maxim MAX749 Digitally Adjustable LCD Bias Supply to provide this voltage range VLCD can be adjusted using RV2 500K potentiometer to provide an output voltage from 16V to 23V To enable the VLCD power supply the evaluation board uses the LCDPWR output from the S1D13504 inverted by U6 to control the MAX749 as shown in the following table Table 4 6 Controlling the MAX749 S1D13504 Output Signal Turn MAX749 On Turn MAX749 Off LCDPWR low high Note When using manual adjust set the potentiometer according to the panel s specific power requirements before connecting the panel 1D13504 S5U13504B00C Rev 2 0 PCI Eva
441. s and Examples manual document number X19A G 002 xx PC platform copy the file 13504SPLT EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13504SPLT to the system 13504SPLT Display Utility Issue Date 01 01 30 S1D13504 X19A B 003 05 Page 4 Usage Epson Research and Development Vancouver Design Center PC platform at the prompt type 13504splt a Embedded platform execute 13504sp1t and at the prompt type the command line argument Where no argument a enables manual split screen operation enables automatic split screen operation The following keyboard commands are for navigation within the program Manual mode T y HOME END Automatic mode Z Both modes B ESC 13504SPLT Example 1 Type 13504splt a to automatically move the split screen 1D13504 X19A B 003 05 moves Screen 2 up moves Screen 2 down covers Screen with Screen 2 displays only Screen 1 changes the direction of split screen movement changes the color depth bits per pixel exits 13504SPLT 2 Press b to change the bits per pixel from 1 bit per pixel to 2 bits per pixel 3 Repeat step 2 for the remaining bits per pixel colour depths 1 2 4 8 15 and 16 4 Press lt ESC gt to exit the program 13504SPLT Display Utility Issue Date 01 01 30 Epson Research and Development Page 5 Vancouver Design Center Comments Progr
442. s for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 WAIT is a signal which is output from the 1D13504 to the host CPU which indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13504 may occur asynchronously to the display update it is possible that contention may occur in access to the 13504 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and needs to be inverted using MDS since the MCF5307 wait state signal is active high The Bus Status BS signal is unused in general purpose bus mode and should be tied high connected to IO Vpp Interfacing to the Motorola MCF5307 Coldfire Microprocessor Issue Date 01 02 02 Epson Research and Development Page 13 Vancouver Design Center 4 MCF5307 To S1D13504 Interface 4 1 Hardware Connections The interface between the S1D13504 and the MCF5307 requires minimal glue logic Since the S1D13504 has a single chip select input for both display RAM and registers a single external gate is required to produce a negative OR function of the two MCF5307 chip selects A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle BS bus start is not used in this implementation and should
443. s option for systems with 512K bytes of video memory and VGA 640x480 panels ENABLE_ANTIALIASED_FONTS This option enables the display driver support of antialiased fonts in WinCE Fonts created with the ANTIALIASED_QUALITY attribute will be drawn with font smoothing If you want all fonts to be antialiased by default add the following line to PLATFORM REG HKEY_LOCAL_MACHINESYSTEMIGDI Fontsmoothing This registry option causes WinCE to draw all fonts with smoothing Font smoothing is only applicable to 16bpp mode EpsonMessages This debugging option enables the display of EPSON specific debug messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the display driver as they will significantly impact the performance of the display driver Windows CE 3 x Display Drivers 1D13504 Issue Date 01 05 08 X19A E 006 01 Page 12 Epson Research and Development Vancouver Design Center DEBUG_MONITOR GrayPalette Mode File 1D13504 X19A E 006 01 This option enables the use of the debug monitor The debug monitor can be invoked when the display driver is first loaded and can be used to view registers and perform a few debugging tasks The debug monitor is still under development and is UNTESTED This option should remain disabled unless you are performing specific debugging tasks that require the debug monitor This option is intended for the support of m
444. se IO pins e Up to 12 General Purpose IO pins are available Operating Voltage e 2 7 volts to 5 5 volts Package e 128 pin QFP15 surface mount package e 144 pin QFP20 surface mount package X19A C 002 11 9A C 002 1 1 NES MW SYSTEM BLOCK DIAGRAM EPSON Control CPU Clock el mm DRAM FPM DRAM St D1 3504 Digital Out p Out RAMDAC gt gt a Analog Out Flat Panel CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS e S1D13504 Technical Manual e S5U13504 Evaluation Boards e Windows CE Display Driver e CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Copyright 1997 2001 Epson Research and Development Inc All rights reserved FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS CE CONTACT Epson Research amp Development Inc Suite 320 11120 Horseshoe Way Richmo
445. se noted 8 2 1 Revision Code Register Revision Code Register REG 00h RO Product Code Product Code Product Code Product Code Product Code Product Code Revision Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code Bit 1 Code Bit 0 bits 7 2 Product Code Bits 5 0 This is a read only register that indicates the product code of the chip The product code is 000001 bits 1 0 Revision Code Bits 1 0 This is a read only register that indicates the revision code of the chip The revision code is 00 Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 90 Epson Research and Development Vancouver Design Center 8 2 2 Memory Configuration Registers Memory Configuration Register REG 01h RW Refresh Rate Refresh Rate Refresh Rate n a Bit 2 Bit 1 Bit 0 n a WE Control n a Memory Type bits 6 4 DRAM Refresh Rate Select Bits 2 0 These bits specify the amount of divide from the input clock CLKT to generate the DRAM refresh clock rate which is equal to 2ValucOfTheseBits 6 Table 8 2 DRAM Refresh Rate Selection Refresh Rate CLKI Divide Amount Refresh Rate for 33MHz DRAM Refresh Bits 2 0 CLKI Time 256 Cycles 000 64 520 kHz 0 5 ms 001 128 260 kHz 1 ms 010 256 130 kHz 2ms 011 512 65 kHz 4ms 100 1024 33 kHz 8 ms 101 2048 16 kHz 16 ms 110 4096 8 kHz 32 ms 111 8192 4 k
446. select input See Table 5 9 Host Bus Interface Pin Mapping on page 31 BUSCLK 108 122 Hi Z System bus clock See Table 5 9 Host Bus Interface Pin Mapping on page 31 BS CS This pin has multiple functions e For SH 3 mode this pin inputs the bus start signal BS e For MC68K Bus 1 this pin inputs the address strobe AS e For MC68K Bus 2 this pin inputs the address strobe AS e For Generic Bus this pin must be tied to IO Vpp See Table 5 9 Host Bus Interface Pin Mapping on page 31 RD WR 10 12 CS Hi Z This pin has multiple functions e For SH 3 mode this pin inputs the RD WR signal The S1D13504 needs this signal for early decode of the bus cycle e For MC68K Bus 1 this pin inputs the R W signal e For MC68K Bus 2 this pin inputs the R W signal e For Generic Bus this pin inputs the read command for the upper data byte RD1 See Table 5 9 Host Bus Interface Pin Mapping on page 31 RD CS Hi Z This pin has multiple functions e For SH 3 mode this pin inputs the read signal RD e For MC68K Bus 1 this pin must be tied to 1O Vpp e For MC68K Bus 2 this pin inputs the bus size bit 1 SIZ1 e For Generic Bus this pin inputs the read command for the lower data byte RDO See Table 5 9 Host Bus Interface Pin Mapping on page 31 1D13504 X19A A 002 19 Hardware Functional Speci
447. sign Center List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping o 10 Table 4 1 Summary of Power On Reset Options o e e 13 Table 4 2 Host Bus Interface Selection o ee 13 Table 4 2 NEC S1D13504 Truth Table o o e 14 List of Figures Figure 2 1 NEC VR4102 Read Write Cycles 2 o o o 02000000008 9 Figure 4 1 Typical Implementation of VR4102 to S1D13504 Interface 12 Interfacing to the NEC VR4102 Microprocessor S1D13504 Issue Date 01 10 26 X19A G 007 08 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD CRT Controller and the NEC Vr4102 Microprocessor uPD30102 The NEC Vr4102 Microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate
448. single panel REG 02h bit 1 6 Program all other registers as required 7 Enable the display FIFO REG 23h bit 7 0 8 Enable display Note The Half Frame Buffer does not actually start to access DRAM until step 5 therefore this initialization sequence will not cause any problems Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 10 2 2 2 Initialization Example 1D13504 X19A G 002 07 Epson Research and Development Vancouver Design Center This section presents an example of how to initialize the S1D13504 registers Example 1 Initialize the registers for a 16 color 640x480 dual passive LCD using a 16 bit data interface assume 2M byte of display buffer Program the 1D13504 registers in the following order with the data supplied Note that for this example it is assumed that the arrays unsigned char RED 16 GREEN 16 BLUE 16 are defined and initialized for the required colors For example RED 2 GREEN 2 and BLUE 2 refer to the color components of pixel value 2 In addition it is assumed that there is no external RAMDAC since only the LCD is being programmed Consequently the RAMDAC registers are not programmed For code examples see Section 9 Sample Code on page 54 Table 2 1 Initializing the S1D13504 Registers Operation Description REG 1Bh 0x00 REG 23h 0x80 REG 01h 0x30 REG 22h 0x24 REG 02h 0x26 REG 03h 0x00 RE
449. sumption depends on the desired CPU perfor mance and LCD frame rate whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the 1D13504 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility S1D13504 X19A G 006 04 Power Consumption Issue Date 01 02 02 EPSON S1D13504 Color Graphics LCD CRT Controller Interfacing to the NEC VR4102 Microprocessor Document Number X19A G 007 08 Copyright O 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introdu
450. suspend or the LCD i initializes registers displays this usage message Examples To enable software suspend mode use the following arguments software enable To disable software suspend mode use the following arguments software disable To enable the LCD use the following arguments 1cd enable To disable the LCD use the following arguments 1cd disable The i argument is to be used when the registers have not been previously initialized The PC must not have more than 8M bytes of memory when used with the S5U13504B00B board Follow simultaneous display guidelines for correct simultaneous display operation Do not use a dual panel with a CRT Select Panel Single whenever using a CRT even if a panel is not attached Also the panel section of 13504CFG must be programmed to Single Panel When a CRT is enabled the settings for the CRT will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing e A CRT cannot show 15 or 16 bits per pixel Do not attach a 16 bit panel when using the CRT 13504PWR Software Suspend Power Sequencing Utility Issue Date 01 02 01 Epson Research and Development Page 5 Vancouver Design Center Program Messages ERROR Unknown command line argument An invalid command line argument was entered Enter a valid command line argument ERROR Already selected SOFTWARE Command l
451. t contact or on the internet at http www erd epson com Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 10 26 Epson Research and Development Page 23 Vancouver Design Center 6 References 6 1 Documents Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM AD Epson Research and Development Inc 1D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S5U 3504BO0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc 1D 3504 Programming Notes and Examples Document Number X19A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Website http www mot com e Epson Research and Development Website http www erd epson com Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 24 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk North Amer
452. t performance The default values change based on the memory configuration access time memory type etc For further information on configuring these settings refer to the S1D13504 Hardware Functional Specifi cation document number X19A B 001 xx and the DRAM manufacturer s specification Selects the DRAM refresh method used during power save mode Select this setting for DRAM that requires timing where the CAS signal occurs before the RAS signal for low power memory refresh Select this setting for DRAM that requires no signal from the 1D 13504 to maintain memory refresh This selection does not refresh the memory during power save mode If this option is selected the memory contents are lost during power save The S5U13504 evaluation boards use DRAM requiring Self Refresh For all other implementations refer to the manufacturer s specification for DRAM refresh requirements S1D13504 X19A B 008 03 Page 12 1D13504 X19A B 008 03 Installed Memory Epson Research and Development Vancouver Design Center Selects the amount of DRAM available for the display buffer The S1D13504 evaluation boards have 2M bytes of DRAM installed 13504DCFG Driver Configuration Program Issue Date 01 10 26 Epson Research and Development Page 13 Vancouver Design Center Clocks Tab 51D13504 Configuration Utility Build 3 CLKI PCLK Source PCLK Source BUSCLK MCLK Source MCLK Divide The Clocks tab is intende
453. t Timing Table 7 17 LCD Panel Power On Reset Timing Symbol Parameter Min Typ Max Units TRESET RESET pulse time 100 us LCD Enable bit high to FPLINE FPSHIFT FPDAT 15 0 DRDY i active i A TrprramMe 6Tpcik ns FPLINE FPSHIFT FPDAT 15 0 DRDY active to LCDPWR on 42 F 5 and FPFRAME active j pe Note Where TrprERAME is the period of FPFRAME and Trey x is the period of the pixel clock 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 63 Vancouver Design Center 7 4 2 Suspend Timing SUSPEND Software Suspend tl Note 1 gt CLKI Note 2 t2 p 13 ae RENG Inactive Active t4 5 gt gt Ry Active Inactive Active FPSHIFT i j FPDAT 15 0 Active S Active t6 7 ma lt gt Memory Access Allowed J Not Allowed Allowed Figure 7 18 LCD Panel Suspend Timing Table 7 18 LCD Panel Suspend Timing Symbol Parameter Min Typ Max Units t1 LCDPWR inactive to CLKI inactive 128 Frames t2 SUSPEND active to FPFRAME LCDPWR inactive 0 1 Frames 13 First CLKI after SUSPEND inactive to FRFRAME LCDPWR 4 Frames active t4 LCDPWR inactive to FPLINE FPSHIFT FPDAT 15 0 DRDY 128 Frames active First CLKI after SUSPEND inactive to FPLINE FPSHIFT t5 E 0 F FPDAT 15 0 DRDY active ela t6 LCDPWR inactive to Memory
454. t be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13504 Issue Date 01 10 26 X19A G 005 09 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PR31500 PR31700 1D13504 X19A G 005 09 The Philips PR31500 PR31700 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the S1D13504 connects to the PR31500 PR31700 processor The S1D13504 can be successfully interfaced using one of three configurations Direct connection to PR31500 PR31700 see Section 4 Direct Connection to the Philips PR31500 PR31700 on page 11 System design using one ITE8368E PC Card GPIO buffer chip see Section 5 1 Hard ware Description Using One IT8368E on page 14 e System design using two ITE8368E PC Card GPIO buffer chips see Section 5 2 Hardware Description Using Two IT8368E s on page 17 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 10 26 Epson Research and Development Vancouver Design Center 3 S1D13504 Host Bus Interface The S1D13504 implements a 16 bit Generic MPU host bus
455. tached to the HAL The HAL can only manage 10 devices simultaneously ERROR Could not register S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program 13504PLAY Diagnostic Utility Issue Date 01 02 01 EPSON 1D13504 Color Graphics LCD CRT Controller 13504BMP Demonstration Program Document Number X19A B 006 04 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504BMP Demonstration Program X19A B 006 04 Issue Date 01 02 01 Epson Research and Development Page 3 Vancouver Design Center 13504BMP 13504BMP demonstrates S1D13504 display capabilities by rendering bitmap images on the display The 13504BMP display utility is desi
456. te 01 02 01 X19A G 002 07 Epson Research and Development Page 8 Vancouver Design Center 2 Programming the S1D13504 Registers This section describes how to program the 1D13504 registers that require special consideration It also provides the correct sequence for initializing the S1D13504 and disabling the half frame buffer For further information on the any of the registers described below refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx 2 1 Registers Requiring Special Consideration 2 1 1 REG 01 bit 0 Memory Type This bit must not be changed during a DRAM R W access Configuring this bit during a DRAM Refresh will not cause any problems Note This register should be programmed only during initialization and never changed after that However it still must be programmed BEFORE the internal blocks start to R W the memory see Register Initialization in Section 2 1 5 2 1 2 REG 22 bits 7 2 Performance Enhancement Register 0 This bit must not be changed during a DRAM R W access Configuring this bit during a DRAM Refresh will not cause any problems Note This register should be programmed only during initialization and never changed after that However it still must be programmed BEFORE the internal blocks start to R W the memory see Register Initialization in Section 2 1 5 2 1 3 REG 02 bit 1 Dual Single Panel Type This bit must not be changed while the Half Frame Buff
457. te lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 23 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Ac
458. ter Table Of Contents A INtrOdUCHON s cit a a See ae a a aa iat eas a ae ee Ge at at 7 2 Programming the S1D13504 Registers lt lt 8 2 1 Registers Requiring Special Consideration 6 hs He ee 8 2 1 1 REG O1 bitO Memory Type 000 0 E 0000000000000 8 2 1 2 REG 22 bits 7 2 Performance Enhancement Register O o 8 2 1 3 REG 02 bit 1 Dual Single Panel Type o o 8 2 14 REG 1B bit 0 Half Frame Buffer Disable 9 25 REG 23 Display FIFO 02000 a a td e AR ed 9 2 2 Register Initialization 9 2 224 Initialization Sequence 2 s 8 4 S eae a ae A RH ee ae a he a ed 9 222 Initiahzatiom Examples uscar ce a bie rs bed cele ci e wl aes 10 2 2 3 Re Programming Registers osas 5 sane Go ed He WR ra A eS Ss 11 2 3 Disabling the Half Frame Buffer Sequence 11 3 Display Butler ia Be eet ee ee Bee bees ore Gee ee eee ee 12 3 1 Display Buffer Location ae 12 3 2 Display Buffer Organization 2 o 12 3 2 1 Memory Organization for One Bit per pixel 2 Colors Gray Shades 12 3 2 2 Memory Organization for Two Bit per pixel 4 Colors Gray Shades 12 3 2 3 Memory Organization for Four Bit per pixel 16 Colors Gray Shades 13 3 2 4 Memory Organization for Eight Bit per pixel 256 Colors 0 13 3 2 5 Memory Organization for 15 Bit per pixel 32768 Colors
459. tes and Examples manual document number X19A G 002 xx for information In addition the 13504CFG user must know the hardware setup for the panel and CRT and the setup for the given hardware platform such as memory addresses and memory speed Sample Program Messages ERROR Could not open lt filename gt Could not open the 13504 utility called lt filename gt This message is generated from the command line 13504CFG filename script ini ILLEGAL VALUE Choose between 8 and 800 in multiples of 8 pixels The user entered an invalid number when changing the Panel X Resolution ERROR Failed to open the file The selected program does not have the HAL structure therefore cannot be opened by 13504CFG 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 30 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 EPSON 1D13504 Color Graphics LCD CRT Controller 13504SHOW Demonstration Program Document Number X19A B 002 05 Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that
460. the S1D13504 4 Connected to AB3 of the S1D13504 5 Connected to AB4 of the S1D13504 6 Connected to AB5 of the S1D13504 7 Connected to AB6 of the S1D13504 8 Connected to AB7 of the S1D13504 9 Ground 10 Ground 11 Connected to AB8 of the S1D13504 12 Connected to AB9 of the S1D13504 13 Connected to AB10 of the S1D13504 14 Connected to AB11 of the S1D13504 15 Connected to AB12 of the S1D13504 16 Connected to AB13 of the S1D13504 17 Ground 18 Ground 19 Connected to AB14 of the S1D13504 20 Connected to AB15 of the S1D13504 21 Connected to AB16 of the S1D13504 22 Connected to AB17 of the S1D13504 23 Connected to AB18 of the S1D13504 24 Connected to AB19 of the S1D13504 25 Ground 26 Ground 27 5 volt supply required in non PCl applications 28 5 volt supply required in non PCl applications 29 Connected to RD WR of the S1D13504 30 Connected to BS of the S1D13504 31 Connected to S1D13504 BUSCLK if JP1 is in position 2 3 32 Connected to RD of the S1D13504 33 Connected to AB20 of the S1D13504 34 Not Connected S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 Page 17 S1D13504 X19A G 014 01 Page 18 Epson Research and Development Vancouver Design Center 4 3 LCD Support The S1D13504 supports 4 8 bit dual and single passive monochrome panels 4 8 bit single passive color panels 8 16 bit dual passive color panels and 9 12 18 bit active matrix color TFT D TFD panels All necessary signals are provided
461. the internal pull down resistor See Table 5 9 Host Bus Interface Pin Mapping on page 31 RESET 11 13 CS Input 0 Active low input to clear all internal registers and to force all signals to their inactive states Hardware Functional Specification Issue Date 01 11 06 S1D13504 X19A A 002 19 Page 24 5 4 2 Memory Interface Epson Research and Development Vancouver Design Center Table 5 2 Memory Interface Pin Descriptions Pin Pin Name Type FOOA Driver Mearan Description F02A Value F01A This pin has multiple functions e For dual CASH DRAM this is the column address strobe for the lower byte LCAS LCAS O 50 56 CO1 Output 1 For single CASH DRAM this is the column address strobe CAS See Table 5 10 Memory Interface Pin Mapping on page 32 for summary This pin has multiple functions e For dual CAS DRAM this is the column address strobe for the upper byte UCAS UCAS O 49 55 CO1 Output 1 For single CASH DRAM this is the write enable signal for the upper byte UWE See Table 5 10 Memory Interface Pin Mapping on page 32 for summary This pin has multiple functions For dual CASH DRAM this is the write enable signal WE For single CAS DRAM this is the write enable signal for the WE O 48 54 CO1 Output 1 lower byte LWE See Table 5 10 Memory Interface Pin Mapping o
462. the operation of the CPU bus in order to establish interface requirements 2 2 MPC821 Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four by
463. the register specified by the index when data is specified otherwise the register is read Reads all registers Reads writes DAC values Writes data to the DAC index when data is specified otherwise the register is read Data consists of 3 bytes 1 red 1 green 1 blue Reads all DAC values Reads writes Look Up Table LUT values Writes data to the LUT index when data is specified otherwise the LUT index is read Data consists of 3 bytes 1 red 1 green 1 blue Reads all LUT values Fills bytes or words from address 1 to address 2 with data Data can be multiple values e g F 0 20 1 2 3 4 fills O to 0x20 with a repeating pattern of 1 2 3 4 Reads number of bytes or words from the address specified by addr If count is not specified then 16 bytes words are read Writes bytes or words of data to address specified by addr Data can be multiple values e g w 0 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0 Initializes the chip with user specified configuration Gets current mode information If bpp is specified then set that pixel depth 13504PLAY Diagnostic Utility Issue Date 01 02 01 Epson Research and Development Page 5 Vancouver Design Center P 1 0 1 set 0 reset hardware suspend power mode This feature only works on the S5U13504B00B ISA evaluation board while operating in the x86 environment Do not use with the S5U13504B00C
464. the source code for the UGL display drivers are updated as appropriate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com Wind River UGL v1 2 Display Drivers 1D13504 Issue Date 01 02 01 X19A E 003 02 Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1 2 Display Driver 1D13504 X19A E 003 02 The following instructions produce a bootable disk that automatically starts the UGL demo software These instructions assume that the Wind River Tornado platform is correctly installed Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the UGL display driver into it Using a command prompt or GUI interface create a new directory e g x 13504 Unzip the file 13504ugl zip to the newly created working directory The files will be unzipped to the directories x 13504 8bpp and x 13504 16bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk ce
465. this bit will have no effect on hardware GPIO10 Pin IO Configuration When this bit 1 GPIO10 is configured as an output When this bit 0 default GPIO10 is con figured as an input Note the MD8 pin must be high at the rising edge of RESET to enable GPIO10 otherwise the HRTC pin is controlled automatically and this bit will have no effect on hardware GPIO9 Pin IO Configuration When this bit 1 GPIO9 is configured as an output When this bit 0 default GPIO9 is config ured as an input Note GPIO9 and GPIO8 must always be set to the same function both to input or both to output The MD8 pin must be high at the rising edge of RESET to enable GPIO9 otherwise the DACRS1 pin is controlled automatically and this bit will have no effect on hardware GPIO8 Pin IO Configuration When this bit 1 GPIO8 is configured as an output When this bit 0 default GPIO8 is config ured as an input Note GPIO8 and GPIO9 must always be set to the same function both to input or both to output The MD8 pin must be high at the rising edge of RESET to enable GPIO8 otherwise the DACRSO pin is controlled automatically and this bit will have no effect on hardware Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Page 105 Vancouver Design Center REG 20h GPIO Status Control Register 0 RW GPIO7 Pin IO Status GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPI
466. tion The S1D13504 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Specification document number X19A A 002 xx The partial table below shows those configuration settings relevant to the direct connection implementation Table 4 1 SID13504 Configuration for Direct Connection S1D13504 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface 16 bit host bus interface MD1 MD2 See Host Bus Selection table below See Host Bus Selection table below MD3 MD4 Big Endian MD5 WAIT signal is active high E required configuration for direct connection with PR31500 PR31700 Table 4 2 S1D13504 Host Bus Selection for Direct Connection MD3 MD2 MD1 Host Bus Interface 0 0 0 SH 3 bus interface 0 0 1 MC68K bus 1 interface e g MC68000 0 1 0 MC68K bus 2 interface e g MC68030 x x Reserved C required configuration for direct connection with PR31500 PR31700 Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13504 Issue Date 01 10 26 X19A G 005 09 Page 14 Epson Research and Development Vancouver Design Center 5 System Design Using the IT8368E PC Card Buffer If the system designer uses an ITE IT8368E PC Card and multiple function IO buffer the S1D13504
467. to C Search for the loadCEPC utility in your Windows CE directories b Edit CONFIG SYS on the hard drive to contain only the following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy NK BIN and HIMEM SYS to c e Boot the system 1D13504 Windows CE 3 x Display Drivers X19A E 006 01 Issue Date 01 05 08 Epson Research and Development Page 11 Vancouver Design Center Configuration There are several issues to consider when configuring the display driver The issues cover debugging support register initialization values and memory allocation Each of these issues is discussed in the following sections Compile Switches There are several switches specific to the S1D13504 display driver which affect the display driver The switches are added or removed from the compile options in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default 2 11 The S1D display driver may test against this option to support different WinCE version specific features EnablePreferVvmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable thi
468. torage for 4 bpp 16 Colors Gray Shades in One Byte of Display Buffer 13 Table 3 4 Pixel Storage for 8 bpp 256 Colors in One Byte of Display Buffer 13 Table 3 5 Pixel Storage for 15 bpp 32768 Colors in Two Bytes of Display Buffer 14 Table 3 6 Pixel Storage for 16 bpp 65536 Colors in Two Bytes of Display Buffer 14 Table 3 7 Look Up Table Configurati0ns 0 2 0 0 000000000000 17 Table 3 8 Recommended LUT Values for 1 bpp Color Mode o o 18 Table 3 9 Recommended LUT Values for 2 bpp Color Mode o oo 18 Table 3 10 Recommended LUT Values to Simulate VGA Default 16 Color Palette 19 Table 3 11 Recommended LUT Values For 8 bpp Color Mode o o e 19 Table 3 12 Examples of 256 Pixel Colors Using Linear LUT o ooo 20 Table 3 13 Recommended LUT Values for 1 bpp Gray Shades o 20 Table 3 14 Recommended LUT Values for 2 bpp Gray Shades o e 21 Table 3 15 Recommended LUT Values for 8 bpp Gray Shade o ee 21 Table 4 1 Number of Pixels Panned Using Start Address 2 2 2 o o 26 Table 4 2 Active Pixel Pan Bits sus see e e WARE Ae eee ee 26 Table 6 1 RAMDAC Register Mapping for Little Big Endiad o 33 Table 6 2 Related Register Data for CRTOMlY
469. troller are intended as reference source code for OEMs developing for Wind River s WindML v2 0 The driver package provides support for both 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13504 Source code modification is required to provide a smaller more efficient driver for mass production e g CRT support may be removed for products not requiring a CRT The WindML display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13504DCFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13504DCFG see the 3504DCFG Configuration Program User Manual document number X19A B 008 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to develop their own drivers for WindML v2 0 These drivers are not backwards compatible with UGL v1 2 For information on the UGL v1 2 display drivers see Wind River UGL v1 2 Display Drivers document number X19A E 003 xx This document and the source code for the WindML display drivers is updated as appro priate Please check the Epson Electronics America website at http www eea epson com orthe Epson Research and Development website at http www erd epson com for the latest revisions
470. ts 4 0 1 8 27 Ts 6 t8min REG 05h bits 4 0 1 8 18 Ts 7 t8min REG 05h bits 4 0 1 8 18 T11 Ts Hardware Functional Specification 1D13504 Issue Date 01 11 06 X19A A 002 19 Page 72 Epson Research and Development Vancouver Design Center 7 4 7 Single Color 8 Bit Panel Timing Format 2 le VDP se VNDP gt FPFRAME SE FPLINE fl l j Fe j j l I j j MOD X S X UD 3 0 LD 3 0 LINE X_LINE2 X LINES X LINE4 E XLINE479XLINE480 LINE1 X LINE2 FPLINE l MOD p HDP si HNDP R FPSHIFT ot AAA 1a eG ale keh al UD3 a R1 X 1 B3 X 1 G6 X y C638 A X UD2 oe 1 41 X 1 R4 X 1 86 X BES UD1 a B1 X 1 G4 X 1 R7 xX R63 x Y UDO EN R2 X_1 84 X_1 67 X TS C639 LD3 S 1 X 1 R5 X 1 B7 X 1 B639 X LD2 o B2 YX 1 65 X 1 R8 R640 LD1 o R3 Y 1 B5 Y 1 68 a E G640 es Y LDO ee 1 3 X 1 R6 X 1 88 e B640 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 27 Single Color 8 Bit Panel Timing Format 2 VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period
471. tup times The EHTR Extended hold time bit will insert an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC821 Microprocessor 1D13504 Issue Date 01 10 26 X19A G 010 06 Page 12 Epson Research and Development Vancouver Design Center 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the S1D13504 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM 1D13504 Interfacing to the Motorola MPC821 Micro
472. tween the system data bus and the external RAMDAC through either data bus bits 7 0 in a Little Endian system or data bus bits 15 8 in a Big Endian system 1D13504 X19A A 002 19 Hardware Functional Specification Issue Date 01 11 06 Epson Research and Development Vancouver Design Center 9 Display Buffer The system addresses the display buffer through the CS M R and AB 20 0 input pins When CS 0 and M R 1 the display buffer is addressed by bits AB 20 0 as shown in the following table Table 9 1 1D13504 Addressing CS M R Access Register access REG 00h is addressed when AB 5 0 0 e REG 01h is addressed when AB 5 0 1 REG n is addressed when AB 5 0 n Memory access the 2M byte display buffer is addressed by AB 20 0 1D13504 not selected Page 113 The display buffer address space is always 2M bytes However the physical display buffer may be either 512K bytes or 2M bytes See Section 5 5 Summary of Configuration Options on page 30 The 512K byte display buffer is replicated in the 2M byte address space as shown below 512K byte Memory Image Buffer Half Frame Buffer Image Buffer Half Frame Buffer Image Buffer Half Frame Buffer Image Buffer Half Frame Buffer AB 20 0 2M byte Memory 000000h O7FFFFh 080000h OFFFFFh 100000h Image Buffer 17FFFFh 180000h Half Fra
473. ual 1D13504 Issue Date 2002 12 02 X19A G 014 01 Page 14 Epson Research and Development Vancouver Design Center 4 Technical Description The S5U13504B00C operates with both PCI and non PCI evaluation platforms It supports passive LCD panels 4 8 16 bit and TFT D TFD panels 9 12 18 bit 4 1 PCI Bus Support The S5U13504B00C does not have on chip PCI bus interface support The S5U13504B00C uses the PCI FPGA to support the PCI bus 4 2 Non PCI Host Interface Support The S5U13504B00C is specifically designed to support a standard PCI bus environment using the PCI Bridge Adapter FPGA However the S5U13504B00C can directly support many other Host Bus Interfaces When the FPGA is disabled using jumper JP7 headers H1 and H2 provide the necessary IO pins to interface to the Host Bus Interfaces listed in Table 4 1 CPU Interface Pin Mapping on page 15 Note The S5U13504B00C is designed to work only with 3 3V systems To use it with a 5V system some modifications must be done to the board as follows a Replace the 3 3V DRAM U5 on the board with a 5V DRAM b Cut the trace between JP8 2 and JP8 3 on the solder side of the board c Connect JP8 1 and JP8 2 This will set IOVDD to 5V S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 Epson Research and Development Page 15 Vancouver Design Center 4 2 1 CPU Interface Pin Mapping The functions of the S1D13504 host int
474. ual document number X19A G 002 xx for formulas and other infor mation Note Epson R amp D Inc cannot be held liable for damage done to the display as a result of software con figuration errors Cancel and Print commands are available in the Current Advanced Configuration windows Help is listed but is not available for this version of 13504CFG 13504CFG EXE Configuration Program Issue Date 01 01 30 Epson Research and Development Vancouver Design Center CRT ADUANCED MEMORY POWER MANAGEMENT LOOKUP TABLE Register Location Memory Location Memory Size 1354 SPECIFIC X Resolution Y Resolution Data Width Panel Format Modulation Rate Horiz Non Disp lt TFT gt Vert Non Disp lt TFT gt HSYNC Start Pos lt TFT gt USYNC Start Pos lt TFT gt Current Configuration Help Cancel Print Page 15 STN 16 BIT COLOR DUAL 866x666 866x666 CLKI 40 MHz 66 ns PERF ENABLE CBR REFRESH SOFT SUSPEND DISABLE LUT 8 BPP COLOR BBCOBBBA Chex OBEGBBBA lt hex gt 66266666 lt hex gt CHIP 1354 SPECIFIC TYPE Figure 5 13504CFG Current Configuration 866 pixels 666 line lt s gt 16 bits COLOR DUAL STN B 32 pixels 1 line lt s gt 8 pixels linets gt Figure 6 13504CFG Advanced Configuration Partial View of Screen 13504CFG EXE Configuration Program Issue Date 01 01 30 S1D13504 X19A B 001 04 Page 16 Device Menu Files Epson Research and De
475. um Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 61 Vancouver Design Center Appendix A Supported Panel Values A 1 Supported Panel Values The following tables show related register data for different panels All the examples are based on 8 bpp 40MHz pixel clock and 2M bytes of 60 ns EDO DRAM Table 9 1 Passive Single Panel Passive Passive Passive Passive Passive Register 4 Bit Single 8 Bit Single 8 Bit Single 8 Bit Single 16 Bit Single Notes 320X240 60Hz 320X240 60Hz 640X480 60Hz 640X480 60Hz 640X480 47Hz Monochrome Color Monochrome Color Color REG O2h 0000 0000 0001 0100 0001 0000 0001 0100 0010 0100 set panel type REG O3h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 set MOD rate REG 04h 0010 0111 0010 0111 0100 1111 0100 1111 0100 1111 set horizontal display width REG O5h 0001 0000 0001 0000 0000 0101 0000 0101 0000 0101 set horizontal non display period REG O8h 1110 1111 1110 1111 1101 1111 1101 1111 1101 1111 set vertical display height bits 7 0 REG O9h 0000 0000 0000 0000 0000 0001 0000 0001 0000 0001 set vertical display height bits 9 8 REG OAh 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 set ve
476. umper is at position 1 2 the LCD panel voltage level is configured for 5 0V When the jumper is at position 2 3 the LCD panel voltage level is configured for 3 3V default setting ee O D E L 5 om 1 JP5 3 3 LCDVCC 5V LCDVCC 1D13504 X19A G 014 01 Figure 3 6 Configuration Jumper JP5 Location S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual Issue Date 2002 12 02 Epson Research and Development Page 13 Vancouver Design Center JP6 Panel Enable Polarity JP6 selects the polarity of the LCDPWR panel enable signal When the jumper is at position 1 2 the LCDPWR signal is active high default setting When the jumper is at position 2 3 the LCDPWR signal is active low JP6 LCDPWR LCDPWR Active Low Active High Figure 3 7 Configuration Jumper JP6 Location JP7 PCI FPGA Enable JP7 controls the PCI FPGA When no jumper is installed the PCI FPGA is enabled and the evaluation board may be used in a PCI environment default setting When the jumper is in position 1 2 the PCI FPGA is disabled and the evaluation board may be used with a non PCI host system Note Non PCI host system must be connected to headers H1 and H2 JP7 non PCl PCI FPGA Disabled FPGA Enabled Figure 3 8 Configuration Jumper JP7 Location S5U13504B00C Rev 2 0 PCI Evaluation Board User Man
477. up windows In this version of 13504CFG the Help files are unavailable Device Register Location PACHANA Chex Memory Location BBEGOOHH Chex Memory Size 66266666 lt hex gt Cancel Help E Ls N Figure 23 13504CFG Setup 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Page 28 Epson Research and Development Vancouver Design Center Setup Parameter Edit When a selection is highlighted in the Setup window and Edit is clicked a Setup Parameter Edit window is displayed for parameter editing The Setup Parameter Edit windows for Register Location Memory Location and Memory Size respectively are shown below Register Location Memory Location G6E60006_ chex Memory Size 512 ge H Figure 24 13504CFG Setup Parameter Edit For Register Location Memory Location and Memory Size Help Menu There are three files in the Help menu e Help not available in this version of 13504CFG e Help on Help not available in this version of 13504CFG e About displays copyright and program version information 1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Epson Research and Development Page 29 Vancouver Design Center Comments It is assumed that the 13504CFG user is familiar with S1D13504 hardware and software Refer to the S1D13504 Functional Hardware Specification document number X19A A 002 xx and the S1D13504 Programming No
478. upply on the S5U13504B00C Evaluation board requires 0 5 seconds to fully discharge Your power supply design may vary Below are the procedures for all cases in which power sequencing is required 5 2 Introduction to Power Save Modes 5 3 Registers The S1D13504 has two power save modes One is hardware initiated via the SUSPEND pin the other is software initiated through REG 1A bit 0 Both require power sequencing as described above Register bits discussed in this section are highlighted Display Mode Register REG 0D Simultaneous Simultaneous Displa Displa Number of Number of Number of n a play pay BPP Select BPP Select BPP Select CRT Enable LCD Enable Option Select Option Select h a Bit 2 Bit 1 Bit O Bit 1 Bit O Power Save Configuration Register REG 1A LCD Power Suspend Suspend Software n a n a n a n a Disable Refresh Refresh Suspend Select Bit 1 Select Bit 0 Mode Enable Suspend Refresh Select bits 1 0 should be set on power up depending on the type of DRAM available See the Hardware Functional Specification document number X19A A 002 xx 1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 Epson Research and Development Page 31 Vancouver Design Center All other bits should be masked into the register on a write i e do a read modify with mask and write to set the bits 5 4 Suspend Sequencing Ca
479. ure 4 2 Block Diagram of MC68328 to S1D13504 Interface Generic Interface Mode The S1D13504 requires a 2M byte address space for the display buffer plus a few more locations to access its internal registers To accommodate this relatively large block size it is preferable to use one of the chip selects from groups A or B but this is not required Virtually any chip select other than CSAO or CSD3 would be suitable for the 1D 13504 interface Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 10 26 Epson Research and Development Page 13 Vancouver Design Center 4 2 1D13504 Hardware Configuration The S1D13504 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET Table 4 2 shows the settings used for the S1D13504 in these interfaces MD1 MD2 and MD3 should be set to select either MC68000 Bus 1 mode or Generic bus mode as desired The other settings are identical for either bus mode Table 4 1 Summary of Power On Reset Options S1D13504 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface MD1 MD2 See Host Bus Selection table below See Host Bus Selection table below MD3 MD4 Little Endian MD5 Wait signal is active low MD6 MD7 See Memory Configuration table below See Memory Configurati
480. ust be properly configured at the rising edge of RESET to enable GPIO1 otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware GPIOO Pin IO Status When GPIOO is configured as an output a 1 in this bit drives GPIOO to high and a 0 in this bit drives GPIOO to low When GPIOO is configured as an input a read from this bit returns the status of GPIOO Hardware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Page 106 Epson Research and Development Vancouver Design Center REG 21h GPIO Status Control Register 1 RW GPO Control n a GPIO11 Pin IO Status GPIO10 Pin IO Status GPIO9 Pin IO Status GPIO8 Pin Wa na IO Status bit 7 bit 3 bit 2 bit 1 bit O 1D13504 GPO Control This bit is used to control the state of the SUSPEND pin when it is configured as GPO The SUS PEND pin can be used as a power down input SUSPEND or as an output GPO possibly used for controlling the LCD backlight power e When MD9 0 at rising edge of RESET SUSPEND is an active low Schmitt input used to put the 1D13504 into suspend mode see Section 13 Power Save Modes on page 127 for details e When MD 10 9 01 at rising edge of RESET SUSPEND is an output with a reset state of 1 e When MD 10 9 11 at rising edge of RESET SUSPEND is an output with a reset state of 0 When this b
481. uver Design Center Note Mode0 h should be created using the configuration utility 13504DCFG For more infor mation on 13504DCFG see the 3504DCFG Configuration Program User Manual document number X19A B 008 xx available at www erd epson com 6 Open the S1D13504 workspace From the Tornado tool bar select File gt Open Workspace gt Existing gt Browse and select the file x 13504 8bpp 13504 wsp or x 13504 16bpp 13504 wsp 7 Add support for single line comments The UGL v1 2 display driver source code uses single line comment notation rather than the ANSI conventional comments P To add support for single line comments follow these steps a In the Tornado Workspace window click on the Builds tab b Expand the Sbpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A properties win dow will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that con tains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 8 Compile the VxWorks image Select the Files tab in the Tornado Workspace window Right click on Sbpp files or 16bpp files and select Dependencies
482. vals 2 S1D13504 display buffer 0D80 0000h 8M byte aliased 4 times at 2Mb intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory Interfacing to the Toshiba MIPS TX3912 Processor 1D13504 Issue Date 01 10 26 X19A G 012 05 Page 20 5 5 S1D13504 Configuration Epson Research and Development Vancouver Design Center The S1D13504 latches MDO through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the S1D13504 Hardware Specification document number X19A A 002 xx The partial table below only shows those configuration settings relevant to the IT8368E implementation Table 5 3 SID13504 Configuration using the IT8368E S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 MDO 8 bit host bus interface MD1 MD2 MD3 MD4 MD5 See Host Bus Selection table below WAIT signal is active high See Host Bus Selection table below 0 Big Endian ee required configuration for connection using ITE IT8368E Table 5 4 SID13504 Host Bus Selection using the IT8368E MD3 MD2 MD1 Host Bus Interface SH 3 bus interface MC68K bus 1 interface e g MC68000 ojojo O O oj o X MC68K bus 2 interface e g MC68030 Reserved 1 x required configuration for conn
483. velopment Vancouver Design Center Device Hel Panel 1D13504 Figure 7 13504CFG Device Menu The Device menu contains the following sub menus where parameters for a S1D13504 utility can be edited e Panel e CRT e Advanced Memory e Power Management e Look Up Table e Setup 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Epson Research and Development Page 17 Vancouver Design Center Panel Panel Setup When Panel is selected from the Device menu the Panel Setup dialog box is displayed To select a panel assignment highlight it in the example window below STN 4 Bit Mono Single 320x240 is highlighted and click OK If the highlighted panel assignment needs changes click Edit and see the next section Edit Panel Setup Whenever a panel assignment is edited or selected in the Panel Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configuration In addition to OK Cancel and Edit commands a Help command is listed in the Panel Setup windows In this version of 13504CFG the Help files are unavailable STN 8 BIT COLOR SINGLE 326x246 STN 8 BIT MONO SINGLE 646x486 STN 8 BIT MONO DUAL 640x480 STN 8 BIT COLOR SINGLE 640x480 STN 8 BIT COLOR DUAL 646x486 STN 16 BIT COLOR SINGLE 646x486 SIN 16 BIT COLOR DUAL 640x480 16 BIT COLOR SINGLE 646x486 lt SHARP LQ1 D311 gt CURRENT CONFIGURATION Help E Lia
484. ver the display buffer Parameter device registered device ID pDispLogicalAddr logical address is returned in this variable Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 43 Vancouver Design Center int seGetScreenSize int device int width int height Description Determines the width and height of the active display device LCD or CRT Parameter device registered device ID width width of display in pixels height height of display in pixels Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seReadDisplayByte int device DWORD offset BYTE pByte Description Reads a byte from the display buffer Parameter device registered device ID offset offset in bytes from start of the display buffer pByte returns value of byte Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seReadDisplayWord int device DWORD offset WORD pWord Description Reads a word from the display buffer Parameter device registered device ID offset offset in bytes from start of the display buffer pWord returns value of word Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is n
485. version 4 0 with Service Pack 5 or later Install Windows CE Platform Builder 3 00 Create a batch file called x wince300 cepath bat Put the following in cepath bat x cd wince300 public common oak misc call wince x86 i486 CE MINSHELL CEPC set IMGNODEBUGGER 1 set WINCEREL 1 set CEPC_DDI_S1D13X0X 1 Generate the build environment by calling cepath bat Create a new folder called 1D13504 under x wince300 platform cepc drivers dis play and copy the 1D13504 driver source code into x wince300 platform cepc driv ers display S 1D 13504 Edit the file x wince300 platform cepc drivers display dirs and add S1D13504 into the list of directories Edit the file x wince300 platform cepc files platform bib and make the following two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13X0X ddi dll FLATRELEASEDIRAS1D13X0X dll NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF CEPC_DDI_S1D13X0X Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGASBPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATI S1D13504 X19A E 006 01 Page 8 1D13504 X19A E 006 01 Epson Research and Development Vancouver Design Center ddi dll _FLATRELEASEDIR ddi_flat dll NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Modify MODE0 H The file MODEO0 H located in x wince300 platform cepc drivers displ
486. vice will not call seInitHal again For embedded platforms the startup code which is linked in addition to the HAL library will call seInitHal In this case seInitHal is called before main is called in the application int seRegisterDevice const DevicelnfoDef pDevicelnfo const DEVICE_CHIP_DEF pDeviceChip int Device Description Registers a device with the HAL library The setup for the device is provided in the structures pDeviceInfo and pDeviceChip In addition it allocates memory addressing space for accessing registers and the display buffer Parameter pDevicelInfo pointer to HAL library structures pDeviceChip pointer to HAL library structure dealing with chip specific features Device pointer to an allocated INT This routine will set Device to the registered device ID Return Value ERR_OK operation completed with no problems ERR_INVALID_STD_DEVICE device argument is not HAL_STDOUT or HAL_STDIN Note No registers are actually changed by calling seRegisterDevice Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 41 Vancouver Design Center int seSetinit int device Description Sets the system to an operational state by initializing memory size clocks panel and CRT parameters etc Parameter device registered device ID Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid ERR_FAILED unable
487. virtual display An image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling 320x240 Viewport 640x480 Virtual Display Figure 4 1 Viewport Inside a Virtual Display Programming Notes and Examples S1D13504 Issue Date 01 02 01 X19A G 002 07 Page 24 4 1 1 Registers Epson Research and Development Vancouver Design Center REG 16h Memory Address Offset Register 0 Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Offset Offset Offset Offset Offset Offset Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 17h Memory Address Offset Register 1 Memory Memory n a n a n a n a n a n a Madress AOOrESS Offset Offset Bit 9 Bit 8 4 1 2 Examples S1D13504 X19A G 002 07 Registers 16h and 17h form a ten bit value referred to as the memory offset This offset is the number of words from the first byte of one line of display buffer to the first byte in the next line This value takes into account the number of non displayed pixels on each line Different color depths have different numbers of pixels per word To represent an offset of a given number of pixels the offset registers will contain different values at different color depths The formula to calculate the offset to write to these registers is offset_regist
488. y y X e41 637 X X LD2 0 241 2 241 6 X X lt x X X e41 638 LD1 ee 241 3 X 241 7 X Y E Y Y ZET LDO e 241 4 241 8 X Y y X Y241 640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 31 Dual Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG O9h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts 1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Epson Research and Development Page 77 Vancouver Design Center Sync Timing t i FPFRAME i 14 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 gt 10 t7 t14 t11 t10 gt gt gt FPSHIFT t12 t13 UD 3 0 1 2 LD 3 0 Figure 7 32 Dual Monochrome 8 Bit Panel A C Timing Table 7 25 Dual Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge n
489. y Taba Ses tha Bare ee Ware eee Whew Sb Se Lee E hale ass 10 Clocks Tabia ti a o ete ais ti A eg fae ws oh Cag ever nee 13 Panel Wabi phat a Cotes hae eke shes eta Ls beste a es Ph ese 15 CRE Tab om toa at Be ee ee I St ed A Bh E Poh one 19 Registers Taba cn 4 8 0 Shan kd eal ae Re Ee Ble Be en ie 20 T3504DCEG Menus loe BO ee A el ok eee des ek ey od Mees OR pth ee in Bk be de oh DE ERXPOTE 4 0 4 o Saris Ware tase ae ee SO AL ook Gr Sa ers Bins 21 Enable Tooltips 00 2 ee SE ay ee Be a eS ee eS 22 ERD on the Webi ss execs Yo Bens Bite eels A ee obits an a E etd tees 22 Update Common Controls s sain aiei ee 22 About T3504DCFG sa a ee hc ES Pe ee bh ee ee be See 22 Comments ta ae an ee eek Ae Se ie abe A ML eat Par et ke ke a a He EZ 13504DCFG Driver Configuration Program 1D13504 Issue Date 01 10 26 X19A B 008 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Epson Research and Development Page 5 Vancouver Design Center 13504DCFG 13504DCFG is an interactive Windows 9x ME NT 2000 program that generates C header files containing user specified display configurations The header files are intended to be used by a software hardware developer in the development of display drivers Note It is possible to override recommended register settings and select incorrect panel tim ings using 13504DCFG
490. y drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com 1D13504 Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A G 011 07 Issue Date 01 02 02 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF 5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM AD Epson Research and Development Inc 1D 3504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc 1D13504 Programming Notes and Examples Document Number X19A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Website http www mot com e Epson Electronics America Website www eea epson com Interfacing to the Motorola MCF5307 Coldfire Microprocessor 1D13504 Issue Date 01 02 02 X19A G 011 07 Page 18 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13504 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel
491. y to save display data off screen memory usage MUST be disabled e When the system is resumed WinCE instructs all running applications to re paint themselves This is the SLOWEST of the three modes Simple Display Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 Windows CE 3 x Display Drivers Issue Date 01 05 08 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S 1D 13504 sources and change the line CDEFINES CDEFINES DEnablePreferVmem to CDEFINES CDEFINES DEnablePreferVmem This step causes the system to redraw the main display upon power on This step is only required if display memory loses power when Windows CE is shut down If dis play memory is kept powered up set the S1D13504 in powersave mode then the dis play data will be maintained and this step can be skipped Search for the file PROJECT REG in your Windows CE directories and inside PROJECT REG find the key PORepaint Change PORepaint as follows PORepaint dword 2 S1D13504 X19A E 006 01 Page 16 Epson Research and Development Vancouver Design Center Comments e The display driver is CPU independent allowing use of the driver for several Windows CE Platform Builder supported
492. yBytes int device DWORD addr BYTE val DWORD count Description Parameter Return Value Writes one or more bytes to the display buffer device registered device ID addr offset from start of the display buffer val value to write count number of bytes to write ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seWriteDisplayWords int device DWORD addr WORD val DWORD count Description Parameter Return Value Writes one or more words to the display buffer device registered device ID addr offset from start of the display buffer val value to write count number of words to write ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seWriteDisplayDwords int device DWORD addr DWORD val DWORD count Description Parameter Return Value Writes one or more dwords to the display buffer device registered device ID addr offset from start of the display buffer val value to write count number of dwords to write ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Programming Notes and Examples Issue Date 01 02 01 Epson Research and Development Page 47 Vancouver Design Center 8 2 3 Color Manipulation int seGetDac int device BYTE pDac Description Reads the entire DAC into an array Parameter device r
493. ynchronous with respect to the S1D13504 bus clock This gives the system designer full flexibility in choosing the appropriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 5 3 IT8368E Configuration 1D13504 X19A G 012 05 The IT8368E provides eleven multi function IO pins MFIO The IT8368E or the first in a two IT8368E implementation must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the S1D13504 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the 1D13504 When accessing the S1D13504 the associated card side signals are disabled in order to avoid any conflicts Note When a second IT8368E is used it should not be set in VGA mode For mapping details refer to Section 5 4 Memory Mapping and Aliasing For further information on configuring the IT8368E refer to the T8368E PC Card GPIO Buffer Chip Specification Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 10 26 Epson Research and Development Page 19 Vancouver Design Center 5 4 Memory Mapping an
494. yoald SVY LL uonsajag Buruy Aiowayy wnwu OL uonoajes ys y puedsng 6 Spina 19d 8 1099 98 2XId Jad Siig JO 19QUINN Z Alu UBOS uang bk a9ej1ajul OL Buqnog aun t0 EWJON 00 uondo Aejdsig snoaueynwis o 1 sua 1319S uondo Aejdsiq snosueynuis uooajas uodo Aejdsiq snosuey nuis 9 ATeUILUNG 19351394 VOOAPOSEI CIS EPSON 1D13504 Color Graphics LCD CRT Controller 13504CFG EXE Configuration Program Document Number X19A B 001 04 Page 2 Epson Research and Development Vancouver Design Center Copyright 1997 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners 1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Epson Research and Development Page 3 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG EXE Configuration Program 1D13504 Issue Date 01 0

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