73S8009R Demo Board User Manual
Contents
1. 5 73S8009R Demo Board Schematics PCB Layouts and Bill of Materials 5 1 Schematics CLKIN VPC E DEE SELECT SCLK 1 T 1 SCLK sa SIO 5 2 am sc4 3 3 EXTCLK 4 OFF a 5V GND 2 GND END Ho ct our PGND 5V J7 E 57 q c ojj aae SSM 110 L SV 2 V gt 2 al R2 1 T VDD 3 S C4 49 9 SELECT S C8 E INT2 Cl C2 and C8 must be placed TP9 3 3V 6 within 5mm of the Ul pins and Nie T connected by thick track wider 8 than 0 5mm 5 0V 3 3V 27 sv J ca l 10 Bletz ut VDD TSM 110 01 L SV Vv R4 0 1 28 cs VDD ia RESET GND HE RDY 1 x AL PRES 2 cs 2 59 OFF 1 0 Fog 0 1uF RESET 3 vouc AUX 53 j TEST 4 7 AUXIUC AUX2 55 SE PWRDN 5 5 Auxeuc voc L CMDVCC5 6 9d CMDVCCS RST 5g CMDVCC3 7 799 CMDVCC3 GND 4g ii RSTIN e 1 AS2. card 5 OFF Interrupt signal to the processor Indicator of card presence and any card fault conditions 6 GND Ground 7 GND Ground 8 GND Ground 9 VPC IN Must be between 2 7 V and 6 5 V 10 VPC IN Must be between 2 7 V and 6 5 V Connections should be made in this order e Power Supplies Apply 3 3 V to pin 10 of J4 or 5 V to pins 9 and 10 of J2 depending on the setting of JP2 e Press the ON OFF button e Control signals to the device can be connected through J2 and J4 See Figure 2 and Figure 4 e Apply the clock signal 8 Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual 3 Jumpers Switches and Test Points The items marked in Figure 3 are described in Table 5 L LJ ra o m om J4 emm emm SSEQOPR om v A e GT e CC ype 6 a Eer Seleg a a Ll e e o Figure 3 7358009R Demo Board Description Rev 1 2 9 73S8009R Demo Board User Manual UM_8009R_065 Table 5 7358009R Demo Board Description Item Schematic amp Hame Use Figure 3 PCB Reference 1 JP1 Clock selection Jumper to select between a clock from 12xx device or external clock as the frequency reference to the device 2 JP5 Card Polarity The setting of these two jumpers depends on the type detect select of smart card connector used whether switch is 13 JP6 nominally open or closed and which of the card presence switch inp
3. HOTEN DIAN SEMICONDUCTOR CORP Simplifying System Integration 73S8009R Demo Board User Manual May 7 2010 Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual UM_8009R_065 O 2010 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Simplifying System Integration is a trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http Awww teridian com or by checking with your sales representative Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com 2 Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual Table of Contents 1 ue 0 Ces e EE 5 tl Package Contents lcitao tes 5 1 2 7
4. Layer 1 Ground Plane 00000000 Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual Figure 10 7358009R Demo Board Bottom Signal Layer Rev 1 2 73S8009R Demo Board User Manual UM 8009R 065 5 3 73S8009R Demo Board Bill of Materials Table 6 7388009R Demo Board Bill of Materials Qty Reference Part PCB Footprint ee Part Number Manufacturer 3 C1 C3 C10 10 uF 805 PCC2225CT ND ECJ 2FB0J106M Panasonic 2 C2 C8 0 1 uF 603 PCC1762CT ND ECJ 1VB1C104K Panasonic 1 C11 3 3 uF 805 PCC1925CT ND ECJ 2YB0J335K Panasonic 2 C12 C13 27 pF 603 PCC270ACVCT ECJ 1VC1H270J Panasonic ND 3 JP1 JP5 Header 3 3pins 2 54mm pitch S1011E 36 ND PBC36SAAN Sullins JP6 2 J1 J3 SSM 110 L SV SSM 110 L SV X SSM 110 L SV Samtec 2 J2 J4 TSM 110 01 L SV TSM 110 01 L SV X TSM 110 01 SV Samtec 1 1J5 Smart Card ITT CCMO02 2504 CCMO2 2504 ND CCMO02 2504 ITTCannon Connector 1 J6 SIM SAM Connector TTT CCMO3 3754 CCMO3 3754CT CCMO03 3754 ITTCannon ND 1 BNC1 BNC Connector BNC A24539 ND 414373 1 AMP 2 R4 R7 0 603 P0 0GCT ND ERJ 3GEYOROOV Panasonic 1 Ri 20K 603 P20KGCT ND ERJ 3GEYJ203V Panasonic 1 R2 49 9 603 P49 9HCT ERJ SEKF49ROV Panasonic 3 R8 R9 R10 Ru 603 X X 3 R11 R12 Rd 603 X X R13 9 TP1 TP2 TP2 2X1 Header S1011 36 ND PZC36SAAN Sullins TP3 TP4 TP5 TP6 TP7 TP8 TP9 1 U1 73S8009R 28SOP X 7358009R Teridian No
5. Safety and ES BD Notes cruise 5 1 3 Recommended Operating Conditions and Absolute Maximum Hatmgs 6 E e ul TEE 7 3 Jumpers Switches and Test Points oonnnnnncccccnnonnnnnicccnccnncnnnnnn nacer 9 4 Design CONSI MONOS asngassa ado zer reed nae emere Da c cada anna aaa Dn cE lara 11 451 General E ef 11 4 2 Optimization for Compliance with EM 11 5 73S8009R Demo Board Schematics PCB Layouts and Bill of Materials 12 E Men ocaso ea EE EE Eo oo EE Eo E SETA aia aaa duda dd dd da du dada 12 5 2 73S8009R PCB Layouts rir nn rn etren ree entane niae raaa iani eanna 13 5 3 7358009R Demo Board Bill of Materas errar anna 16 6 Ordering UU tel ue ET 17 7 Contact intormation EE EE EE 17 lala dili 18 Rev 1 2 3 73S8009R Demo Board User Manual UM_8009R_065 Figures Figure 1 1358009R Demo Board n eee eme vd a 5 Figure 2 7358009R Demo Board External Connechors rear rn n cnn 7 Figure 3 7358009R Demo Board Description 9 Figure 4 7358009R Electrical Schematic e ncnn nn non nnnnn nn n cnn nn rra nan rrnnn rra 12 Figure 5 73S8009R Demo Board Top View 13 Figure 6 73S8009R Demo Board Bottom View 13 Figure 7 7358009R Demo Board Top Signal Layer 14 Figure 8 73S8009R Demo Board Middle Layer 1 Ground Plane once 14 Figure 9 7388009R Demo Board Middle Layer 2 Supply Plane nar ncncnnn nano 15 Figure 10 7358009R Demo Board Bottom Signal Layer 15 Tables Table 1 Re
6. TIN CLK H GND 9 D i2 PCLKIN we HE 3 3V 10 z 13 RDY M Ee SSM 110 L SV 14 PWRDN PRES Pas TEST VPC J4 TP H 1 EWRDN 73S8009R 2 3 2 PULL DOWN E SELECT d R8 R9 E Ru Ru 8 Ri These resistors are d d not populated TSM_110_01 LSV Lar 1 T Y 20K R10 rac a NM R11 R12 Ru 3 3uF Rd Rd Y S tes gt 1 qu a Jl and J3 are placed on the bottom J2 and J4 T 1 vee are placed on the top side TP4 2 R1 N TP5 Jl and J3 must be aligned with J8 and J9 on the Rd 1 0 i d 1 1121 evaluation board El121T8 respectivly in Io RST order for this board to be stacked on it TP6 TP3 to TP8 to be placed JP5 ERES S E i TPZ very close to the pads c8 of J5 Jl must be aligned with J2 and J3 must be 1 Zi T d 1 CLK aligned with J4 in order for this daughter sa 37 TPS board to be stacked on another PRES 1 He c4 CARD DETECT SS POLARITY SELECT dr 4 JP6 GND A NY uos hi 2 T c12 C13 JT N 3 27pF 27pF VDD bd Y comico xe e al NEN GR A N 23000000 eoo J5 J6 Smart Card Connector SIM SAM Connector Figure 4 73S8009R Electrical Schematic 12 Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual 5 2 73S8009R PCB Layouts JPS GCLK JP1EXT CLIK Mm E _ 7358009R 10 G N DBOO9RCIA ad ES R1 r TPZ m CUBE da A e Lo S gj Select Ge Figure 6 7358009R Demo Board Bottom View Rev 1 2 73S8009R Demo Board User Manual UM_8009R_065 Figure 8 7388009R Demo Board Middle
7. commended Operating Conditions 6 Table 2 Absolute Maximum Hatings nnn nnn nr rr nr rn nn r e n nnns nennen nnns 6 Tabl 3 J4 Pin DESCIIDLONS eerte eet Ete but E ne Le EEUU LU E REEL UNE RE CE CREER CE UE ER Pone Rte ERR E RE NL EA 7 Table 4 J2 Pin Descriptions eseu le ee ee ae 8 Table 5 7388009R Demo Board Description 10 Table 6 7388009R Demo Board Bill of Materials cnn nnnrrrnncn nan cn nan rr nn 16 Table 7 7358009R Demo Board Order Number 17 4 Rev 1 2 UM_8009R_065 7358009R Demo Board User Manual 1 Introduction The Teridian Semiconductor Corporation 7358009R Demo Board is a platform for evaluating the Teridian 7388009R Smart Card Interface IC It incorporates the 73S8009R integrated circuit and it is designed to operate either as a standalone platform to be used in conjunction with an external microcontroller or as a daughter card to be used in conjunction with the 73S12xxF evaluation platform 1 4 Package Contents o o IER CH PTERIDI N j SEMICONDUCTOR CORP J d Ly LU 4 7358009R PEJE accu og M TP2 TP VPC En _JP6 ISelect Gls Figure 1 73S8009R Demo Board The 73S8009R Demo Board Kit includes e A 7388009R Demo Board Rev 1 e The following documents e 7358009R Data Sheet e 73S8009R Demo Board User Manual this document 1 2 Safety and ESD Notes Connecting live voltages to the 7358009R Demo Board system will result in potentially hazardous voltages on the boards E
8. igital signals and power supply connections are made through 10 pin header connectors labeled J2 and J4 in Figure 2 l OUC AUX1UC AUX2UC OFF GND GND GND VPC VPC Vpc Power Supply 4 5V to 5 5V 5V Typ 200mA External clock source JP1 must be in position SCLK when an external clock is used from the motherboard or from an external signal generator Figure 2 7388009R Demo Board External Connectors Table 3 describes the pins for the J4 connector Table 3 J4 Pin Descriptions Pin Pin Name Function 1 RDY Indicates when smart card power supply is stable and ready 2 CS Chip Select active high 3 RESET 4 TEST 5 PWRDN 6 CMDVCC5 Controls the turn on output voltage value and turn off of Voc 7 CMDVCC3 8 RSTIN Controls the card reset signal 9 GND Ground 10 VDD System interface supply voltage and supply voltage for companion controller circuitry Voo Power Supply 2 7V to 3 6V 3 3V Typ 50mA VDD GND RSTIN CMDVCC3 CMDVCC5 PWRDN TEST RESET cs RDY Rev 1 2 73S8009R Demo Board User Manual UM 8009R 065 Table 4 describes the J2 connector pins Table 4 J2 Pin Descriptions Pin Pin Name Function 1 SCLK Clock source input 2 OUC System controller data I O to from the card 3 AUX1UC System controller auxiliary data C4 to from the card 4 AUX2UC System controller auxiliary data C8 to from the
9. o ground e Keep 0 1 uF and 10 pF close to VPC pin of the device and directly take other end to ground e Keep 3 3 uF 1 0 uF for NDS close to VCC pin of the smart card connector and directly take other end to ground 4 2 Optimization for Compliance with EMV Default configuration of the Demo Board contains a 27 pF capacitor C12 from the CLK pin of the smart connector to ground and a 27 pF capacitor C13 from the RST pin of the smart connector to ground These capacitors serve as filters for CLK and RST signals in the case of long traces or test equipment perturbations The capacitor on CLK reduces ringing on the trace reduces coupling to other traces and slows down the edge of the CLK signal The capacitor on RST helps the perturbation specification in a noisy environment The filter capacitors can be useful in the EMV test environment and have no effect on NDS testing C12 and C13 are represented on both schematic and BOM These capacitors are optional filter capacitors on the smart card lines CLK and RST respectively for each card interface These capacitors may be adjusted value not to exceed 30 pF or removed to optimize performance in each specific application PCB card clock frequency compliance with applicable standards etc The default VCC capacitor of 3 3 uF is required to meet the dynamic VCC smart card supply transient current requirement in EMV2000 version 4 0 Rev 1 2 11 7358009R Demo Board User Manual UM_8009R_065
10. ry Delivery 8 Lifecycle Information Maxim Integrated 73S8009R DB
11. t card size format contacts must face up 16 TP1 VPC select Two pin header Shorting bar jumper must be in place for normal operation The shorting jumper can be replaced with an ammeter to measure the VPC current to the IC VPC must be at set with a 5V supply 17 J2 Board 5V Connector that gathers the 5V supply of the board the supply and host digital interface 73S8009R interface IOU external clock SCLK and interrupt OFF pins Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual 4 Design Considerations 4 1 General Layout Rules Follow these layout rules e Route I O and auxiliary signals away from card interface signals e Keep CLK trace as short as possible and with minimal bends in the trace If possible keep routing of the CLK trace to one layer avoid vias to other layers Keep CLK trace away from other traces especially RST I O and VCC Filtering of the CLK trace is allowed for noise purposes Up to 30 pF to ground is allowed at the CLK pin of the smart card connector Also the zero Q series resistor R7 can be replaced with a small resistor for additional filtering no more than 100 Q e Keep VCC trace as short as possible Make trace a minimum of 0 5 mm thick Also keep VCC away from other traces especially RST and CLK e Keep RST trace away from VCC and CLK traces Up to 30 pF to ground is allowed for filtering e Keep 0 1 uF close to VDD pin of the device and directly take other end t
12. te The resistors noted Ru and Rd in the schematic are not populated on the board They can be implemented to adjust the features of the smart card reader Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual 6 Ordering Information Table 7 lists the order number used to identify the 7358009R Demo Board Table 7 7388009R Demo Board Order Number Part Description Order Number 73S8009R 28 Pin SO Demo Board 7358009R DB 7 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8009R contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email scr support teridian com For a complete list of worldwide sales offices go to http www teridian com Rev 1 2 17 73S8009R Demo Board User Manual UM 8009R 065 Revision History Revision Date Description 1 0 5 22 2007 First publication 1 1 8 9 2007 Corrected schematic error 1 2 5 7 2010 Formatted in the new Teridian style Added Section 1 1 Package Contents Added Section 1 2 Safety and ESD Notes Added Table 3 J4 Pin Descriptions Added Table 4 J2 Pin Descriptions Added Section 7 Ordering Information Added Section 9 Contact Information Miscellaneous editorial corrections Rev 1 2 Mouser Electronics Authorized Distributor Click to View Pricing Invento
13. ut of the 73S8009R is used In this demo board the switch is nominally open The jumpers can be set in one of two ways 1 Default setting Use of PRES JP5 must be set to PRES and JP6 set to VDD 2 Alternative use Use of PRES JP5 must be set to PREB and JP6 set to GND 3 BNC1 EXTCLK BNC input for external clock when JP1 is in the EXTCLK selection jumper JP1 between terminal 2 and 3 Test Points 4 TP7 CLK 5 TP8 C4 Two pin test points for each respective smart card 6 TP5 RST signal The pin label name is the respective signal i e 7 TP3 VCC VCC CLK and the other pin is GND 11 TP4 UO 12 TP6 C8 8 TP9 VDD Select Two pin header Shorting bar jumper must be in place for normal operation The shorting jumper can be replaced with an ammeter to measure the VDD current to the IC VDD must be at set with a 3 3V supply 9 J4 Board 3 3V Connector that gathers the 3 3V supply of the board supply and the 73S8009R host control signal pins RDY CS digital control RESET TEST PWRDN CMDVCC5 CMDVCCS and signals RSTIN 10 J6 Smart Card SIM SAM smart card format connector Connector Note that J6 is wired in parallel to the smart card connector J5 underneath the PCB No SIM SAM should be inserted when using the credit card size connector J5 14 TP2 PWRDN Pull Two pin header When shorted with a jumper the Down Selection device is in power down mode 15 J5 Smart Card Smart card connector Connector When inserting a card credi
14. xtreme caution should be taken when handling the 7388009R Demo Board after connection to live voltages The 73S8009R Demo Board is ESD sensitive ESD precautions should be taken when handling this board Rev 1 2 5 73S8009R Demo Board User Manual UM_8009R_065 1 3 Recommended Operating Conditions and Absolute Maximum Ratings Table 1 Recommended Operating Conditions Parameter Rating Supply Voltage Voo 2 7 to 3 6 VDC Supply Voltage Vpc 4 75 to 5 5 VDC ISO 7816 and EMV applications 4 85 V to 5 5 VDC NDS applications Ambient Operating Temperature 40 C to 85 C Input Voltage for Digital Inputs 0 V to Voo 0 3 V Table 2 Absolute Maximum Ratings Parameter Rating Supply Voltage Vpp 0 5 to 4 0 VDC Supply Voltage Vpc 0 5 to 6 5 VDC Input Voltage for Digital Inputs 0 3 to Vpp 0 5 VDC Storage Temperature 60 to 150 C Pin Voltage except card interface 0 3 to Vpp 0 5 VDC Pin Voltage card interface 0 3 to Vcc 0 5 VDC Pin Current 100 mA ESD Tolerance Card interface pins t6kV ESD Tolerance Other pins t2kV Operation outside these rating limits may cause permanent damage to the device ESD testing on Card pins is HBM condition 3 pulses each polarity referenced to ground 6 Rev 1 2 UM_8009R_065 73S8009R Demo Board User Manual 2 Connections This section describes the 7358009R Demo Board external connectors All the d
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