Module CC9P9360_2 Users Manual
Contents
1. eese 30 Karl Rudolf 17 January 2006 Page 3 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual Forth Systeme GmbH A Digi International Company TEN I years 33 KOPN pl 4010 Tier de 1 e 33 11 References rre e Ee He a x e Y X an 33 12 FAUST 33 13 Detailed Specification ee 33 VSA TEL NO DV C EE ET 33 13 2 Mechanical Reouirements enne nennen nnne ene 33 139 Block EE E rrt 33 14 Board Connechors norse iranan aa ERANA ERARE N ENARA ai 33 Karl Rudolf 17 January 2006 Page 4 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual 1 Revision History 2005 03 09 V1 00 KR Initial Version derived from A9M9360 1 spec 2005 04 05 V1 00 KR Transfer to standard document format 2005 05 30 V1 00 KR Migration to ABM9360 2 Karl Rudolf 17 January 2006 Page 5 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual 2 General A9M9360 Module is a member of the ModARM9 family with a NetSilicon NS9360 CPU The ModARMS family includes several modules with the same size connectors and a set of common pins and functions see Arm9 module pinning table xls with CPUs from different manufacturers There are two modules with Netsilicon CPUs in this family available A9M9750 and A9M9360 2 1 Common Features Below are the common features of this module which wil2. The internal USB PHY in the NS9360 CPU can be used for the USB host or device channel USB_INTPHY_DP USB_INTPHY_DN These signals are not 5V tolerant and have to be protected on the base board A 2 independant USB device channel is provided when an external unidirectional or bidirectional PHY is connected to the USB device control signals GPIO42 45 48 In this case the internal PHY has to be used in host mode 3 16 UART Channels Karl Rudolf 17 January 2006 Page 20 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Up to 4 UART channels with all handshake signals are provided channels A GP108 15 B GPIOO 7 C GPIO20 23 amp GPIO40 43 D GPIO24 27 amp GPIO44 47 They can be used in asynchronous mode as UART Baud rates are supported up to 1 8MHz in asynchronous mode 3 17 SPI Channels Four SPI channels are provided by the NS9360 Usage in master or slave mode is possible SPI channel B GPIOO 1 6 7 is connected to the serial 8Kx8 SPI EEPROM containing the boot program and the initial SDRAM parameters for booting via SPI when RESET is asserted External usage of this channel after boot at runtime is provided with additional hardware The other SPI channels can be used free if not used in UART or LCD or USB mode or blocked by other GPIO usage 3 18 Usage UART and SPI on A9M9360 Module ARMS modules have 2 serial ports A B wired with at least TXD RXD RTS
3. 2303 2015 SS 237 251 167 47 143 125 83 47 41 27 A9M9360 module is using PLL so modules with 177MHz 155MHz and 103MHz will use the values from column 1 allowing baud rates from 75 921600Bd 3 20 PC Bus This bus with the signals IIC_SCL GPIO70 and muxed signal A26 lost and IIC SDA GPIO71 and muxed signal A27 lost is connected on the module to a serial EEPROM with DC interface on device address OxAO OxA1 Device address OxDO OxD1 connects to an RTC on board All other addresses can be used externally Due to a timing bug in the I C state machine the maximum clock frequency in slow mode should be 50KHz and 200KHz in fast mode Otherwise minimum setup time for the target can be Karl Rudolf 17 January 2006 Page 22 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual violated SDA changes after half low time of SCK instead of shortly after falling edge so setup time for data is 2 5us 100KHz and 612 5ns 400KHz Important Use only 3 3V devices 3 21 LCD Controller STN amp TFT An LCD interface for STN or TFT LCD s is provided with up to 18 data lines and 6 control lines Usage for LCD disables serial ports C D and most GPIOs The module provides the full LCD interface 18 data lines LCCDO 17 GPIO24 41 and 6 control lines GPIO18 23 This interface allows connection of most TFT and STN monchrome and col
4. ssssseeeeeeeeeetetnte nnne ennt tens 15 3 12 73 GPIO Pins multiplexed with other Functions nn 16 3 13 External Intermupts ener ener n nnr nnns nnn nr nns 20 3 14 10 100Mbps Ethernet Port 20 3 15 USB 2 0 full and low speed Host and Device Controller 20 316 UART Channels oee EHI ee ehren 20 3 47 SPI Channels een 21 3 18 Usage UART and SPI on A9M9360 Module essem 21 3 19 Baudrate Table 22 SOM eh E 22 321 LER Controller SINA TR nase 23 3 22 Serial EEPROM for storing Configuration Parameters AAA 23 323 A e 23 3 24 JTAG Boundary Scan ssssssssssssseeeeenennnenerennnn nenne nnr nnne n nne nnns ennenen nnne 23 3 25 Single 3 3V Power Supply Power Sequencing evernnnnnnnrnnnnnnnnnrnnnnennnnnnannnvnnnennrennnn 24 d Bootloader i ce E ER C RE RE UOCE RED TR RE EE LEA RR ER RR ER 25 SPEO IRURE NEN 25 5 1 Software Hints ee een 25 Os MECHANICS RE 26 6 1 Extended 0 0 LU lt nnne nter nnne nnns nnns nnns n nnn nennen 27 7 Known Faults and Limitations nennen nenne nennen nn 29 7 1 SDRAM Clocks Clockout1 3 not switchable nn nnnnnnnnnnnnnnnnnnn 29 7 2 12C Setup Time Data always half low time of Clock nn 29 7 3 SPI Boot System needs Hardware Workaround nn 29 D AP NN 30 LPEN 30 8 2 Pinning Description Module ser ann 30 8 3 Pinning Module on A9MVali Validation Board 30 8 4 Pinning Module on Development Board
5. 2 Users Manual 3 Detailed Description 3 1 Size 60 x 44 mm The A9M9360 module has a size of 60 X 44 mm 3 2 2x 120 pin Connectors Two 120 pin connectors on the long side of the module allow accessing most signals of the NetSilicon NS9360 CPU An optional extension with another two 60 pin connectors is planned This will extend the length of the module from 60mm to approximately 95mm Pin compatible in power supply and main port functions to other ModARM9 modules 3 3 NS9360 CPU For details see 9360 HardwareReferenceManual pdf from NetSilicon The CPU is offered in three speed and temperature variants e 177MHz 0 70 C e 155MHz 40 85 C e 103MHz 0 70 C 3 4 Configuration Pins CPU Several pins allow configuration of the CPU before booting CPU pins have weak pull ups value range is 15 300K for a default configuration Most pins do not have configuration options some are connected for internal configuration on the module 32 of the 73 GPIO pins allow user specific configurations They are latched in the GEN_ID register address 0xA0900210 5 clock cycles after the rising edge of RESET Important configuration pins are protected i e not accessible externally until strapping information configured on module is latched For details see Spec A9M9360 2 pdf Normally the hardware module configuration needs never to be changed by the client wrong configuration can make the module unbootable Module configuration d
6. a spare SDRAM chip select the successful initialization of the SDRAM controller chip select toggling for refresh Otherwise a 2 reset is necessary which will always result in a proper setup and the system will start This workaround is implemented in the A9M9360 2 module Karl Rudolf 17 January 2006 Page 29 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 8 Appendix 8 1 Pinning Module The pinning for all currently planned and realised modules are defined in the file Arm9 Module Pinning Table XLS 8 2 Pinning Description Module A detailed pin description is available as Pin Description A9M9360 X pdf or doc 8 3 Pinning Module on A9MVali Validation Board This pinning is included in the specification of the validation board A9MVali_X doc or pdf Important If possible avoid usage of A9M9360 modules on A9MVALI X boards due to missing power sequencing on this base board Module powerup and powerdown may be disturbed by backfeeding 3 3V signals from base board Prefered base board is A9YM9750DEV 1 8 4 Pinning Module on Development Board This pinning is included in the specification of the Development board Spec Devkit A9M9750 A9M9360 X doc or pdf Module CC9P9360 2 1 Erste Fu note Karl Rudolf 17 January 2006 Page 30 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Man
7. changed from normal to set mode command while starting the 2 bank So the initialization routine has to be run either from NOR flash if booting with flash or from another memory place A good choice may be the ethernet TX buffer descriptor RAM starting at address 0xA0601000 with a space of 256 32bit words Before using this RAM it must be enabled by setting bit 23 of the Ethernet General Control register 1 to high Karl Rudolf 17 January 2006 Page 15 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 3 12 73 GPIO Pins multiplexed with other Functions NS9360 has 73 GPIO pins 23 more than NS9750 All pins are multiplexed with other functions UART SPI USB Ethernet DMA parallel port IEEE1284 IIC port LCD port timers interrupt inputs some memory bus address and control pins Using a pin as GPIO means always to give up another functionality GPIOO 48 GPIO66 72 are accessible on the connectors GPIO13 is used for RTC interrupt on module allows sharing with open drain ORing GPIO49 65 are used on the module and not external accessible All GPIOs are set to GPIO input function after RESET Usage in another function needs configuring the GPIO registers at start up Port Name Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up GPIOO TXD
8. for M2 screws catercornered are provided to enable fixing of the module on the base board Board to Board Module Connector X3 X4 Base Board Connector X3 X4 Distanceh No of Pins Qty Supplier Order No No Of Supplier Order No Pins 5mm 60 AMP 177984 2 Berg 61083 061009 6mm 60 AMP 179029 2 60 2 AMP 177983 2 Berg 61083 062009 7mm Berg 61082 061009 60 AMP 179030 2 Berg 61083 063009 8mm 60 AMP 179031 2 Berg 61083 064009 Karl Rudolf 17 January 2006 Page 28 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 7 Known Faults and Limitations 7 1 SDRAM Clocks Clockout1 3 not switchable Only SDM CLKOUTO can be switched off by software Switching SDM CLKOUT1 3 does not work CPU fault can be fixed only by NetSilicon Workaround None all 4 signals used on module with 2 SDRAM banks equipped 7 2 BC Setup Time Data always half low time of Clock I2C_SDA from NS9360 changes after half low time of DC SCL instead of short time after high to low edge of clock as other I2C devices do CPU fault can be fixed only by NetSilicon Workaround Use half clock speed i e 50KHz in slow mode and 200KHz in fast mode 7 3 SPI Boot System needs Hardware Workaround The SPI EEPROM boot engine has a fault that prevents sometimes a proper setup of the SDRAM controller A hardware workaround is necessary that watches via
9. 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 3 25 Single 3 3V Power Supply Power Sequencing The module has 3 3V IN and VLIO 3 3V too for A9M9360 supply pins Internal voltages 1 5V core voltage with up to 400mA will be converted by a switching regulator from VLIO to keep losses small Power up and power down behaviour recommended by NetSilicon for the NS9360 see 9360 power sequencing doc from NetSilicon will be ensured by hardware Due to generation of 1 5V from 3 3V IN or VLIO with a step down switching regulator the core voltage will rise later than the I O voltage 3 3V IN A FET switch controls the switching of the I O voltage 3 3V into the module Important Every base board has to switch its 3 3V supply according to the module Otherwise power sequencing on the module is influenced by backfeeding the module with 3 3V from the base board The signal PWREN is provided for this purpose Karl Rudolf 17 January 2006 Page 24 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 4 Bootloader Every module is delivered with a bootloader UBOOT pre installed in NAND Flash The bootloader is capable of booting the Operating System from NAND Flash via a serial port or via Ethernet Parameters can be passed to the kernel from the bootloader 5 Software The ARM926 core in the NS9360 contains an MMU thus allowing Operating S
10. B SPI Boot DMAO Timer 1 TXDB DO DONE dupe SPI Boot DO SPIB DO dupe or external SPIB DO GPIO1 RXDB SPI Boot DMAO EIRQO RXDB DI REQ Dupe SPI Boot DI SPIB DI or external SPIB DI GPIO2 RTSB DMA1 ACK RTSB DMA GPIO3 CTSB 1284 ACK DMAO CTSB DMA REQ GPIO4 DTRB 1284 DMAO DTRB BUSY DONE GPIO5 DSRB 1284 ERR DMAO ACK DSRB DMA GPIO6 RIB SPI Boot 1284 Timer 7 RIB CLK P_JAM dupe SPI_Boot_CL SPIB_CLK K or external ext SPIB_CLK RXCLK_A GPIO7 DCDB SPI Boot DMAO Ack EIRQ1 DCDB CEH dupe SPI Boot CE SPIB CES or external ext SPIB_CE TXCLK_A GPIO8 TXDA SPIA_DO TXDA SPI A GPIO9 RXDA SPIA DI RXDB SPI A dupe dupe dupe dupe GPIO13 DSRA EIRQO PWM2 EIRQO dupe dupe connected to RTC_INT on module GPIO14 RIA SPIA_CLK Timer 1 PWM3 SPIA Karl Rudolf 17 January 2006 Page 16 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Forth Systeme GmbH A Digi International Company Port Name Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up ext RXCLK_B N GPIO16 1284 Reserved USB_OVCUR mM AC t dupe GPIO17 USB Reserved Reserved USB PREL mI mE Relay CAM PWREN dupe Reject GPIO19 Ethernet LCD DMA1 ACK LCD CAM HSYNC dupe Request GPIO20 DTRC LCD CLK VFSYNC GPIO22 RICA SPIC_CLK L
11. CD Reserved LCD RXCLK_C N GPIO23 DCDC SPIC_ LCD Reserved LCD EN ext LINE END TXCLK_C GPIO24 DTRD LCDDO GPIO25 DSRDH LCDD1 ext RXCLK D GPIO27 DCDD SPID_ LCDD3 Timer 4 LCD ee TXCLK_D IT SS me ae dupe dupe GE Boni cl cl dupe a a dupe GPIO31 Timer 7 LCDD7 LCDD11 dupe GPIO32 EIRQ2 1284D1 LCDD8 LCD GPIO33 Reserved 1284D2 LCDD9 LCD GPIO34 HC SCL 1284D3 LCDD10 LCD GPIO35 IIC SDA 1284D4 LCDD11 LCD GPIO36 PWMO 1284D5 LCDD12 LCD GPIO37 PwMmi 1284D6 LCDD13 LCD Karl Rudolf 17 January 2006 Page 17 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Port Name Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up GPIO38 PWM2 1284D7 LCDD14 LCD GPIO39 PWM3 1284D8 LCDD15 LCD res toer em _D Y D DIRCON _D Y_D Ek SPID DO 1284 USB PHY USB EXTPH SELECT TXOUT Y_OE EN GPIO45 SPID_DI i id USB EXTPH Bal Tee ro _RXD GPIO47 CTSD 1284 INIT USB_PHY GPIO47 _RXD drives DEBUG LED _SUSP P_SEL REQ Y _SUSP d USB PHY 1284 DMA1 R B NAND SPEED P LOG DONE Flash GPIO control on mo Dte fee om cn ER m _D dupe Reserved USB_PHY _TXOUT_ EN GPIO53 Reserved USB_PHY oes a le il dupe Be ee _S
12. Module CC9P9360 2 Users Manual Module CC9P9360 2 Users Manual Forth Systeme GmbH A Digi International Company Copyright 2005 FS Forth Systeme GmbH a DIGI Company Postfach 1103 79200 Breisach Germany Release of Document January 17 2006 Filename UM Module CC9P9360 2 doc Author Karl Rudolf Program Version All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of FS Forth Systeme GmbH Karl Rudolf 17 January 2006 Page 2 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual Table of Contents 1 Revision iib en 5 EE EE 6 2 1 GCommon Feat res E 6 2 2 Differences between A9M9750 and A9M9360 Modules nenn 1 2 3 Existing Variants OF A9M9360_1 WEE 8 2 4 Existing Variants E EE 8 3 Detailed Description 9 3 1 Size 60 x 44 mm 9 3 2 2x 120 pin Connectors cece cccccceccceeceeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeceeseeeeeeeeeeeseneeeneeseneeeness 9 NNN NE 9 JA Config ration Pins PULS 9 3 5 Configuration Pins Module cta end de nhe ep ala 10 3 6 Clock Generatton n nme nnn nnnnnnn nnne nnns n nnn nnr senes nnns 12 3 Boot Process aerian aai eiaa at ae E Ea A A Ea aaa A AAAA Ea ae Eaa daR ERE 13 3 8 Chip Selects Memory Map 13 3 9 NAND FE c 13 3 10 12 16 64 MBytes SPAM ne aesdedeme bands 15 3 11 Usage of 2 SDRAM bank
13. USP dupe Reserved USB_PHY _SPEED dupe MII_RXD3 Reserved USB_PHY BENE Jd dupe GPIO57 MII TXEN Reserved USB PHY MI TXEN mm sn he oil dupe GPIO58 MILTXER MII TXER GPIO59 MIITXDO MI TXDO Karl Rudolf 17 January 2006 Page 18 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Forth Systeme GmbH Port Name Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up GPIO60 MIITXD1 Reserved Reserved MII TXD1 GPIO61 MII_TXD2 Reserved Reserved MII TXD2 GPIOG2 Iw TXD3 Reserved Reserved MII TXD3 GPIO63 MIL COL Reserved Reserved ML COL GPIOG4 MILCRS Reserved Reserved MILCRS _ NT GPIO 6 A22 Reserved Reserved A22 GPIO67 I A23 Reserved Reserved A23 IRQO dupe GPIO69 En MCKE 1 IRQi dupe A25 EE dupe is m PIER dupe GPIO7Z2 TA STB ext WAIT Karl Rudolf 17 January 2006 Page 19 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 3 13 External Interrupts 4 external interrupts are multiplexed with other functions on the GPIO pins Every interrupt is routed to two or three different GPIOs to increase the chance of using them without giving up another vital functi
14. Users Manual A9M9360 has 32Mx8 64Mx8 or 128Mx8 NAND Flash onboard Optionally greater sizes can be populated depending on availability The NS9360 limits the address range of a single chip select to 256MByte but this is not relevant for NAND Flash as the interface to the NAND flash needs always 32 kByte here due to usage of A13 14 for address and command control The NAND flash is accessed with EXT_CS1 The chip can be write protected externally with the signal FWP Karl Rudolf 17 January 2006 Page 14 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 3 10 1 2 16 64 MBytes SDRAM Two SDRAM banks are available on the module They are connected to CS4 D CSO0 and CS5 D CS1 CS6 D_CS2 and CS7 D CS3 are lost The module does not provide external SDRAM connection A9M9360 has one or two 1X4MX32 2X4MX32 or 4X4MX32 SDRAM onboard The highest address connected is A12 Range of chip select is 256M BAO 1 are connected to A13 14 The SDRAM controller connects the right address line to allow a gapless memory space at different SDRAM sizes 3 11 Usage of 2 SDRAM bank The SPI loader used on A9M9360 module initializes only SDRAM bank 0 with SD CS0 When the system is running from SDRAM the 2 bank cannot be initialized because it uses the same registers for different parameters as the running bank Especially the Dynamic Memory Control Register has to be
15. and CTS as common port lines The NS9360 chip allows only the usage of UART channels A B for UART and or SPI function if the LCD function is used too If all signals of the LCD function realised on the module are used channel C for UART and or SPI function is blocked Usage USB with external PHY needs GPIOs providing SPI channel D Karl Rudolf 17 January 2006 Page 21 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Forth Systeme Gmbh 3 19 Baudrate Table Baud rate generators in the NS9360 have different clock sources selectable 1 X1 SYS OSCIM It is the frequency of the input crystal divided by M M depends on the multiplier settings PLL_ND of the PLL M 2 at PLL_ND gt 8 decimal 14 7456MHz with 29 491 2MHz quartz unusable for PLL ND lt 8 baud clock instable and or wrong frequency at CPU speeds lt 58 9824MHz Cannot be used with PLL bypassed 2 BCLK For 176 9472MHz CPU clock is BCLK AHBCLK 2 44 2368MHz Only internal source when PLL bypassed 3 External receive clock from GPIO6 14 22 26 pins 4 External transmit clock from GPIO7 15 23 27 pins Count values vs Baud Rate Clock Baud Rate N X1_SYS 2 N BCLK N BCLK N BCLK 44 236800MHz 38 707200MHz 25 804800MHz 14 745600MH Error Error Error z Error 75 12287 32255 21503 GOO 1535 4607 4031 2687 767
16. d software SCONF2 read Bit 30 GEN ID configuration pin can be read in GEN ID register bit 30 default high GPIO41 User defined software SCONF3 read Bit 31 GEN ID configuration pin can be read in GEN ID register bit 31 default high Recommended Combinations of DEBUG ENZ and OCD EN on om eme jr Karl Rudolf 17 January 2006 Page 10 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Forth S OFF ON not recommended may hang avoid ow ov Rome 8 Karl Rudolf 17 January 2006 Page 11 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 3 6 Clock Generation Summary Clock Frequencies on 177MHz Module Clock Tape Settings Result Crystal 29 4912MHz PLL ND 4 0 PLL Multiplier b10010 d24 CPU PLL active PLL FS 1 0 PLL divider b11 d2 CPU PLL active PLL IS 1 0 value b11 ND16 31 CPU PLL active resulting PLL clock 353 8944 MHz CPU clock 176 9472 MHz AHB SDRAM and external clock 88 4736 MHz BCLK clock 44 2368 MHz UART Baud Rate Clock BBus 44 2368 MHz LCD clock 88 4736MHz 44 2368MHz 22 1184MHz or 11 0592MHz By writing in the NDSW CPCC FSEL and PLLSW fields of the SCON PLLCR register the CPU speed can be changed IMPORTANT Changing PLL parameters ends with a 4 ms RESET to allow changed PLL to stabilize Applications using this fea
17. etails see specification A9M9360 2 pdf e little endian mode selected e PLL active PLL bypassed not allowed e PLL FS divider set to 2 e PLL ND multiplier set to 24 177MHz 21 154MHz or 14 103MHz e Boot from SPI EEPROM spi bin Karl Rudolf 17 January 2006 Page 9 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual 3 5 Configuration Pins Module Module configuration pins change either hardware configurations on the module HCONFO 3 or they are user specific and can be read in the GEN ID register SCONFO 3 Signal name PU PD external Comment pin name DEBUG EN CPU Mode Select PU 10K HCONFO 0 Disconnects TRST and PWRGOOD for JTAG and Boundary scan debug mode 1 TRST and PWRGOOD connected for normal mode default FWP internal NAND flash PU 10K HCONF1 write protect 0 write protect active 1 no write protect OCD_EN JTAG Boundary Scan PU 10K HCONF2 Select JTAG mode function selection DEBUG ENG has to 0 ARM Debug Mode be low too BISTEN set to high 1 Boundary Scan Mode BISTEN set to low default unused HCONF3 no function nc GPIO38 User defined software SCONFO read Bit 28 GEN ID configuration pin can be read in GEN ID register bit 28 default high GPIO39 User defined software SCONF1 read Bit 29 GEN ID configuration pin can be read in GEN ID register bit 29 default high GPIO40 User define
18. l be covered in further detail later in the document e ARMO9 core with MMU e Size 60mm x 44mm with 240 pin connectors e SDRAM 16MB 256MB e NAND Flash 32MB 256MB e 4 Serial RS232 interfaces e Host and device USB interface USB2 0 compliant e 10 100Mbps Ethernet interface e BC interface 100KHz and 400KHz e SPI interfaces e JTAG interface Karl Rudolf 17 January 2006 Page 6 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual 2 2 Differences between A9M9750 and A9M9360 Modules Netsilicon CPU NS9360 is a low cost version of the NS9750 It has many features from the NS9750 including CPU core and most peripherals Differences 1 CPU clock is 100 177MHz NS9750 up to 200MHz 2 Two SDRAM banks allowing up to 2 256MByte memory 3 No PCI CardBus on A9M9360 All pins used by PCI on A9M9750 are unconnected on A9M9360 4 NS9360 has 73 GPIOs multiplexed with other functions NS9750 has 50 The same number of GPIOs are available on the A9M9360 connectors as the A9M9750 provides GPIOO 48 Additional GPIO66 72 are available too but have non GPIO function names A22 A25 DC SCL DC SDA WAIT and will be used normally in this function 5 LCD function limited to 18bit LCD data LCD adapters with 18bit TFT LCD used for A9M9750 will run with A9M9360 too 6 Dedicated I2C pins IIC SDA and IC SCK on A9M9750 can be GPIO70 71 or A26 A27 on A9M9360 also 7 8
19. on External 1 Pos other functions 1 Pos 2 Pos other functions 2 Interr dupe Pos RXDB SPIBoot DI GPIO13 DSRA PWM2 dupe SPIB DI DMAO REQ used on module for dupe RTC interrupt EIRQ1 GPIO7 DCDB Z SPIBoot CEZ GPIO28 LCD D4 LCD D8 and SPIB_CE dupe DMAOACK dupe Be GPIO32 LCDD8 1284 DO GPIO11 CTSA TimerO dupe ll GPIO40 TXDC SPIC_DO GPIO18 LCD_PWREN LCDD16 ETH CAMREJ EIRQO and EIRQ1 have a third position on the NS9360 EIRQO dupe GPIO68 also A24 EIRQ1 dupe GPIO69 also A25 Both address lines are routed to the modules connectors If not used on the base board or application the interrupts are available by changing the GPIO configuration 3 14 10 100Mbps Ethernet Port The 10 100Mbps Ethernet port of the NS9360 allows a glueless connection of a 3 3V MII or RMII PHY chip that generates the physical Ethernet signals The module has a MII PHY chip LXT972 in a LQFP 64 case on board No transformer or Ethernet connector is on the module these parts have to be provided by the base board PHY clock of 25MHz is generated in the PHY chip with a 25MHz crystal 3 15 USB 2 0 full and low speed Host and Device Controller The USB section of the NS9360 CPU provides USB signals for a host and device channel All external configuration for a USB host and or a USB device interface has to be made on the base board 48MHz USB clock is generated on the CPU with a 48MHz crystal in fundamental configuration
20. or LCDs Details see NS9360 hardware user manual 3 22 Serial EEPROM for storing Configuration Parameters The nonvolatile storage of parameters like MAC address etc is supported with a serial 8Kx8 EEPROM 24LC64 or similar in TSSOP8 case connected to the I C bus at device address OxAO OxA1 Write protect WP and optional address lines AO A1 A2 are grounded some manufacturers leave these pins n c 3 23 RTC An RTC MAXIM DALLAS DS1337 in uSOP8 case on the module is connected to the I C bus device address OxDO OxD1 It has its own 32 768KHz clock crystal Power is taken from 3 3V when provided otherwise from Vor fed by an external battery An interrupt line GPIO13 configured as IRQO is connected to the RTC pin AINT open drain default disabled the connection can be opened by depopulating resistor R2 3 24 JTAG Boundary Scan NS9360 support JTAG and boundary scan with the signals TCK TMS TDI TDO and TRST The signal RTCK is not connected to external Selection between normal mode and debug mode is done with the external signal DEBUG ENZ HCONFO Selection between ARM debug mode and boundary scan mode is done with the signal OCD EN HCONF2 See table below DEBUG EN OCD ENZ Mode Comments 1 1 nom 1 not recommended Boundary Scan possible here too but TRST is connected with SRST system may hang 0 1 ARMdebug pO 0 BoundaryScan Karl Rudolf 17 January 2006 Page 23
21. ted at the top side should not exceed 4 1mm Board to Board Module Connector X1 X2 Base Board Connector X1 X2 Distance h No of Pins Qty Supplier Order No No Of Pins Supplier Order No 5mm 120 AMP 177984 5 Berg 61083 121000 6mm 120 2 AMP 177983 5 120 AMP 179029 5 Berg 61082 121000 Berg 61083 122000 7mm 120 AMP 179030 5 Berg 61083 123000 8mm 120 AMP 179031 5 Berg 61083 124000 Mechanical Drawing from TOP View 44 39 8 34 2 2 2x o 9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual A Digi Mechanical Drawing from Side View The size of h depends on the board to board connectors The size between the board to board connectors is measured from pad to pad 6 1 Extended Module For further modules in the ModARM9 family it might be necessary to have some additional hardware placed on the module which will need more signal lines connected between module and base board than currently available To meet these future requirements an extended board was defined which has two additional board to board connectors with 60 pins each Karl Rudolf 17 January 2006 Page 27 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Forth Systeme GmbH A Digi international Company The size of the extended module is defined as 92 x 44mm Two holes
22. timers on A9M9360 16 on A9M9750 8 4 PWM channels added on A9M9360 each uses 2 timers 9 Additional USB device modul on A9M9360 needs external USB PHY connected to GPIO42 48 Karl Rudolf 17 January 2006 Page 7 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360 2 Users Manual 2 3 Existing Variants of A9M9360 1 B Current state 02 2005 1 0381 CPU speed 177MHz 16MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 2 0382 CPU speed 177MHz 32MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 3 0383 CPU speed 177MHz 64MByte SDRAM 64MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 Due to a bug in the NS9360 CPU the module generation A9M9360 1 is stopped A safe start in SPI boot mode needs a hardware workaround realised in A9M9360 2 2 4 Existing Variants of A95M9360 2 Current state 05 2005 4 0381 CPU speed 177MHz 16MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 5 0382 CPU speed 177MHz 32MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 6 0383 CPU speed 177MHz 64MByte SDRAM 64MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 Karl Rudolf 17 January 2006 Page 8 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936C Module CC9P9360
23. ture have to discriminate between cold start and warm start Karl Rudolf 17 January 2006 Page 12 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 3 7 Boot Process A9M9360 modules are preconfigured to boot with SPI channel B from a serial SPI EEPROM containing memory controller setup for SDRAM bank 0 and an initial boot program that moves the boot loading program from NAND flash to SDRAM bank 0 and starts it The serial SPI EEPROM has a size of 8KByte 3 8 Chip Selects Memory Map NS9360 CPU provides 8 chip selects divided in 4 channels for dynamic RAMs and 4 static chip selects Every chip select has a 256MB range Below the whole memory map of the NS9360 chip Address Size Comments Range Mbyte OxOFFFFFFF Ox1FFFFFFF module Pe rer BI LI Ox2FFFFFFF Pee Gore ST Ox3FFFFFFF Pree al ce Ox4FFFFFFF Ox5FFFFFFF PSA EI IT Ox6FFFFFFF EOM ES Joe o Ox7FFFFFFF pers gee NEN Ox8FFFFFFF eeu emm Ox9FFFFFFF pes fame a OxAO3FFFFF gt zl OxAOAFFFFF Bridge o El OxAO5FFFFF Ethernet 0xA0600000 1 Ethernet OxAOGFFFFF Communication Module power eee mE OxAO7FFFFF Controller Loose TD o OxAO8FFFFF ren NN id NN OxAO9FFFFF Module pem i 1 e qe P OxFFFFFFFF 3 9 NAND Flash Karl Rudolf 17 January 2006 Page 13 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2
24. ual e Gmi Users Manual 17 January 2006 D 79200 Breisach Germany D 79206 Breisach Germany Fax 49 7667 908 200 http www fsforth de P O Box 1103 a Kueferstrasse 8 49 7667 908 0 Forth Systeme GmbH sales fsforth de A Digi International Company Karl Rudolf 17 January 2006 Page 31 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Table of Contents QE e 33 PANE reelle e RE ENEMIES LLLI NM 33 3 References nee ee ee EXER EYE ERES 33 A FUSA 33 5 Detailed Specification nen rrr rnnt rrr rrr rires 33 Di Lar FONN ms 33 5 2 Mechanical Requirements non nn nn nn rne nnne nennen 33 9 3 Block Diagfam an keine 33 6 Board CGonnechors nennen enne nennen nennen rrr rennen enne 33 Karl Rudolf 17 January 2006 Page 32 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual 9 History Date Version Responsible Description 2004 07 28 0 1 Dieter F gele Initial Version preliminary for proposal 10 Introduction 11 References 12 Features 13 Detailed Specification 13 1 Technology 13 2 Mechanical Requirements 13 3 Block Diagram 14 Board Connectors Karl Rudolf 17 January 2006 Page 33 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936
25. ystems such as Linux and Windows CE to be supported Board Support Packages for Windows CE net 4 2 and Linux using kernel 2 6 x are in development Other Operating Systems can be supported on request 5 1 Software Hints This chapter just lists some problems which occurred while bringing a NS9360 FORTH into life UARTs all four channels have their RESET bit set Reset bits in SCON MRES other wise system hangs at access to UART registers 12C Reset bit in SCON MRES Same effect as mentioned for UARTs System Memory Chip Select X Memory Mask register Bit O has to be 1 otherwise chip select is blocked Is undocumented chip select enable now documented SDRAM bank 1 can be used if initilization is running not from SDRAM bank 0 see chapter SDRAM Karl Rudolf 17 January 2006 Page 25 33 192 168 40 10 projekte modarm9 a9m9360 doc um_module_cc9p936 Module CC9P9360 2 Users Manual Forth Systeme GmbH A Digi international Company 6 Mechanics The module size is defined to 60 x 44mm Two holes for M2 screws catercornered are provided to enable fixing of the module on the base board Two board to board connectors are used on the module Depending on the counterpart on the base board different distances between module and base board can be realized The minimum distance is 5mm Therefore the height of the parts mounted on the bottom side of the module should not exceed 2 5mm The height of the parts moun
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