Home

Specs - TRS RenTelco

1. Twelve Single wide or Six Dual wide Slots for Instrument Expansion Modules w4 ES BF B10 tT 12 j gt TLA7XM Expansion Mainframe Tektronix Logic Analyzers gt Detailed Product Information 17 00 in 17 50 in 431 80 mm 444 50 mm OO O Gsep 9 25 in apop 234 95 mm QO asap co OodDgD _ _ _ o0o00000000 oo0o0co0o0o0o0D0oOo0n fame J ae J oe Je on oe os es E i gt TLA715 Portable Mainframe gt TLA715 Series with TDS7000 Series oscilloscope Symbolic Support 16 70 in 26 5 in Number of Symbols Ranges Unlimited limited only Cem eres ini by amount of virtual memory available on TLA Object File Formats Supported 13 65 in gt IFFE695 345 71 mm 13 25 in gt OMF 51 OMF 86 OMF 166 OMF 286 eee mt OMF 386 gt COFF Elf Dwarf 1 and 2 gt TLA721 and TLA7XM Benchtop and Expansion Mainframes gt Elf Stabs gt TSF if your software development tools do not generate output in one of the above formats i Ee ne y hk on e aa oe TSF or the Tektronix symbol file a generic ASCII file format is supported The generic ASCII file fo HHH HH format is documented in the TLA User Manual 13 65 in E If a format is not listed please contact your oe a local Tekt
2. CD ROM HH C AC Power Fuse 3 5 Floppy Disk Drive o0 Keyboard PS2 SVGA External Display Ports Port Serial Port Mouse PS2 Port USB Ports 0 1 71 MA Parallel Port NY External Signal IN External Signal OUT Indicator Lights PC Card Expansion Slots 3 5 Floppy Disk Drive SVGA External b o 4 iS mife al Display Ports USB Ports 0 1 fall N la Mouse TJ PS2 Port Keyboard PS2 Port External Signal OUT gt TLA721 Benchtop Mainframe Soft ON Standby Power Switch Expansion Replaceable a System Trigger IN System Trigger OUT External Signal IN U3 Ju 4 JUS 3 6 Ten Single wide or Five Dual wide Slots for Instrument Expansion Modules 7 8 JS jet j Module Indicator H Light Expansion Cable Connectors lt A B C HHH eee ereneeeeeeee b fe p Adi smil 4
3. Expansion Capability Multiple monitor support each with up to 1600 x 1200 resolution to see more data By connecting up to 10 expansion mainframes you can simultaneously view time correlated data for multi bus designs up to 60 TLAVu PatGenVu Offline Analysis individual buses using up to 8160 channels each with up to 256 Mb memory depth Utilize this free application software to analyze data or create setups on a separate PC Upgrade kits offer upgrades to system RAM hard disk TLA application software operating system software iView capability and Upgrade trade in capability controllers to help protect investments and allow test equipment to change as measurement needs change PowerFlex program provides customer installable upgrades on measurement modules including faster state speed and additional memory depth to allow the flexibility to upgrade instrumentation over time Mainframe and module trade in programs protect investments by providing discounts on future measurement equipment Measurement Modules and Key Interface Features 8 GHz MagniVu timing 120 to 800 MHz state acquisition up to 1 25 Gb s data rate 128 Kb to 256 Mb memory depth capability TLA7Axx Logic Analyzer Modules provide enough power to capture and debug the fastest and most complex high speed digital designs 2 GHz MagniVu timing 100 to 200 MHz state acquisition up to 400 Mb s data rate and 64 Kb to 12
4. gt 4 Channel Digital Oscilloscope with up to 1 GHz 5 GS s Provides High fidelity signal Quality Measurements of Digital Signals gt 64 Channel Pattern Generator with up to 268 MHz and up to 2 Mb Depth Provides Stimulus for Functional Verification Debugging and Stress Testing gt Integrated View iView Capability Provides up to 6 GHz 20 GS s and 32 Mb with a Stand alone Tektronix TDS Digital Storage Oscilloscope gt TLAVu and PatGenVu Off line Analysis Capability for Viewing Data and Creating Setups on a Separate PC gt Microsoft Windows 2000 Professional PC Platform Provides Familiar User Interface with Network Connectivity Applications gt Hardware Debug and Verification gt Processor Bus Debug and Verification gt Embedded Software Integration Debug and Verification Tektronix Enabling Innovation Tektronix Logic Analyzers gt Detailed Product Information 2 www tektronix com la TLAZOO Series Performance and Modular Flexibility for Your Toughest Design Challenges a n SSS ae gt Benchtop Modular Mainframe gt Portable Modular Mainframe TLA721 with logic analyzer pattern generator TLA715 with logic analyzer pattern generator and digital oscilloscope modules and digital oscilloscope modules TLAGOO Series Affordable Timing and State Logic Analyzers for Your Mainstream Design Needs gt Logic Analyzer with Internal Display gt Logic Analyzer with External Display TLA6
5. 34 channel High density Compression Probe with Differential Clock and Single ended Data Order P6860 Part Number Description 010 6860 00 34 channel P6860 Probe 020 2453 00 2 each Nut block used on lt 0 093 in thick PCB 020 2451 00 2 each Elastomer Holder Assembly Thin used on lt 0 093 in thick PCB 020 2452 00 2 each Elastomer Holder Assembly Thick used on gt 0 093 in thick PCB 335 0346 00 1 each Sheet of Probe Labels 020 2457 00 1 each Mictor on PCB to Compression Adapter 020 2455 00 1 each Compression on PCB to Mictor Adapter 17 channel 020 2456 00 1 each Compression on PCB to Mictor Adapter 34 channel NOTE Recommend PEM KFS 256 or equivalent for gt 0 093 in thick PCB P6860 Probe Cable Length 1 9 m 6 25 ft gt P6880 P6880 TLA7Axx Option 4P The P6880 is a 34 channel high density compression probe with differ ential clock and differential data This probe uses a connectorless probe attach mechanism for quick and reliable connection to your system under test This probe is recommended for high density applications that require a full differential probe 34 channel High density Compression Probe with Differential Clock and Differential Data and Accessories for TLA7Axx Logic Analyzer Modules Order P6880 Part Number Description 010 6880 00 34 channel P6880 Probe 020 2453 00 2 each Nut block used on lt 0 093 in thick PCB 020 24
6. 0 ns to 50 ns with reference to Ch 0 Ch 6 Output Modes Normal Ch 6 OR Ch 7 Ch 6 AND Ch 7 Ch 6 OR NOT Ch 7 Ch 6 AND NOT Ch 7 Delay Accuracy 3 of Delay Time 0 8 ns to Ch 0 At maximum slew rate setting Slew Rate Control 0 5 V ns to 2 5 V ns 100 mV ns step Data Output Skew lt 295 ps between all data output pins of all modules in the mainframe after inter module skew is adjusted manually lt 280 ps between all data output pins of all probes of a single module lt 250 ps between all data output pins of a single probe Tektronix Logic Analyzers gt Detailed Product Information Data Output to Clock Output Delay 940 ps External Clock Input to Clock Output Delay 62 ns Number of External Event Inputs 2 Number of External Inhibit Inputs 1 External Inhibit to Output Enable Delay 30 ns for data output External Inhibit Input to Output Disable Delay 28 ns for data output Probe D Data Output to Output Enable Delay 100 ps for data output Probe D Data Output to Output Disable Delay 4 4 ns for data output External Event Input to Clock Output Setup Full channel mode 1 5 Clocks 180 ns Half channel mode 2 Clocks 180 ns External Event Input and Inhibit Input Polarity Positive True Impedance 1 KQ to ground Threshold level 2 5 V to 2 5 V Event and Inhibit are independent Threshold resolution 20
7. 100 mV Input Voltage Range Operating 6 5 V centered around the programmed threshold Nondestructive 15 V Minimum Input Signal Swing 250 mV or 25 of Signal swing whichever is greater P6417 amp P6418 300 mV or 25 of signal swing P6434 Input Signal Minimum Slew Rate 200 mV ns typical State Acquisition Characteristics with P6417 P6418 or P6434 probes State Clock Rate 100 MHz standard 200 MHz optional State Data Rate half full channels 400 200 Mb s typical Requires 200 MHz State option State Memory Depth with Timestamps 64 Kb 206 Kb 1 Mb Setup Time Selection Range From 8 5 ns before to 7 0 ns after clock edge Setup and hold Window 2 0 ns typical Minimum Clock Pulse Width 2 ns Active Clock Edge Separation 5 ns Demux Channel Selection Channels can be demultiplexed to other channels through the user interface with 8 channel granularity Timing Acquisition Characteristics with P6417 P6418 or P6434 probes MagniVu Timing 500 ps 2 Ghz MagniVu Timing Memory Depth 2 Kb per channel Deep Timing Resolution half full channels 2 ns 4 ns to 50 ms Deep Timing Resolution with Glitch Storage Enabled 10 ns to 50 ms Deep Timing Memory Depth half full channels with timestamps and with or without transitional storage 128 64 Kb 512 256 Kb 2 1 Mb Deep Timing Memory Depth with Glitch Storage Enabled Half of defau
8. Opt 5S Increase to 256 K depth at 200 MHz state Opt 6S Increase to 1 M depth at 200 MHz state Opt 7S Increase to 4 M depth at 200 MHz state Logic Analyzer P Module Options Base configuration is 16 M depth at 100 MHz state Opt 1S Increase to 16 M depth at 200 MHz state Logic Analyzer Q Module Options Base configuration is 64 M depth at 100 MHz state Opt 1S Increase to 64 M depth at 200 MHz state TLAZOO Series Module Upgrades You can increase the memory depth and state speed of most existing TLA700 Series logic analyzer modules You can also install a TLA7Nx Px Qx logic analyzer module into an existing TLA714 715 720 721 7XM mainframe Please refer to the TLA Family Upgrade Guide for further details Logic Analyzer Probe Selection Guidelines For the TLA7Nx Px Qx logic analyzer modules you have the choice of three probe options Tektronix Logic Analyzers gt Detailed Product Information Logic Analyzer Module Probes and Accessories P6418 TLA7Nx Px Qx Opt 1P The P6418 is a 1 channel general purpose probe with leadsets and grabber tips for use with 1 probing individual test points within your target system either directly or with a test clip or 2 direct connection to legacy TLA family processor bus support probe adapters with 8 Channel probe connectors The P6418 works with a wide range of industry standard probing accessories for flexible attachment to your
9. 1J Data Correlation After TDS oscilloscope acquisition Sound Built in PC speaker transducer 16 Bit 1 0 is complete data is automatically transferred to the and Mic In port re TLA and time correlated with the TLA acquisition data l ale els Hard Disk Drive 10 GB 30 GB with Opt 1J Deskew TDS and ILA data is automatically dleskewed and time correlated when using the iView CD ROM Internal 16 8 32 CD RW external oscilloscope cable Floppy Disk Drive Built in 3 5 in 1 44 MB drive iView External Oscilloscope Cable Length 2 m f f 2 Bs Ey SA j gt TLA600 Series with TDS3000 Series Oscilloscope www tektronix com la 29 Tektronix Logic Analyzers gt Detailed Product Information 18 00 in 457 20 mm i 11 10 in 281 94 mm gt TLA60x Logic Analyzer with external display 48 00 in 457 20 mm gt l c a o o 3 11 10 in o gt 281 94 mm CND 00000000000000 o0o0oo0000000000 oo0oo0000000000 690000000000000 ooo0000000c0000 gt TLA61x 62x Logic Analyzer with internal display TLAGOO Integral Controls TLAG1x 6G2x only Front Panel Display size 10 4 in diagonal Type Active matrix color TFT LCD with backlight Resolution 800x600 Colors 16 8 M true color Simultaneous Display Capability The front panel and external
10. Characteristics gt TLAZOO Series Mainframes General TLA715 TLA721 TLA7XM Instrument Slots TLA715 Holds 4 single wide or 2 double wide modules TLA721 Holds 10 single wide or 5 double wide modules TLA7XM Holds 12 single wide or 6 double wide modules Quantity of TLA7XMs The TLA700 Series Mainframes can support multiple TLA7XM mainframes TLA715 Up to two TLA7XM mainframes can be used providing 13 dual 26 single instrument slots 2 TLA721 Up to ten TLA7XM mainframes can be used providing 60 dual 120 single instrument slots 2 Mainframe LA 3 PG 3 DSO 3 Max channels 136 ch 64 ch 4 ch per module TLA715 1 768 832 52 TLA721 8 160 3 840 240 For configurations beyond ten TLA7XM expansion mainframes please contact your local Tektronix account manager TLAZOO PC Characteristics TLA715 and TLA721 Operating System Microsoft Windows 2000 Professional Processor Intel Pentium Ill Chipset Intel 815E DRAM TLA715 256 MB SDRAM 512 MB with Opt 18 TLA721 512 MB SDRAM Display Memory 4 MB Dual Monitor Support 1600x1200 Resolution Sound Built in PC speaker transducer multimedia sound can be added via PC Card interface Replaceable Hard Disk Drive TLA715 10 GB 30 GB with Opt 1S TLA721 30 GB CD ROM Internal 8 4 32 CD RW Floppy Disk Drive Built in 3 5 in 1 44 MB drive 1 TLA7XM Expansion Module occupies one singl
11. Clock Strobe Output ZA Complies with TIA EIA 644 standard SS Ff ok gt 7 o oe gt P6473 16 channel LVDS Probe and Accessories for TLA7PG2 Pattern Generator Module Order P6473 Part Number Description 012 1581 00 2 each 8 channel leadsets 012 1580 00 1 each 5 channel leadset 012 1570 00 Probe cable optional std with TLA7PG2 module 071 1017 01 Pattern Generator Probe User Manual i Data Clock ycia 750 Strobe Output 4 Event Inhibit Input 744016244 012 1 e gt 206 0364 00 optional gt P6474 16 channel LVCMOS Probe and Accessories for TLA7PG2 Pattern Generator Module Order P6474 Part Number Description 012 1581 00 2 each 8 channel leadsets 012 1580 00 1 each 5 channel leadset 012 1570 00 Probe cable optional std with TLA7PG2 module 071 1017 01 Pattern Generator Probe User Manual Tektronix Logic Analyzers gt Detailed Product Information SN 012 1570 00 gt P6475 8 channel Variable Probe and Accessories for TLA7PG2 Pattern Generator Module Order P6475 Part Number Description 012 1504 00 SMB to header Coaxial cable set 012 1570 00 Probe cable optional std with TLA7PG2 module 071 1017 01 Pattern Generator Probe User Manual 012 A224 00 Time alignment cable for use with P6470 P6473 P6474 www tektronix com l
12. Data Width 64 channel full channel mode 32 channel half channel mode Module Merging Five modules can be merged to make up to a 320 channel module Merged mod ules exhibit the same depth as the lesser of the 5 individual modules Number of Mainframe Slots Required 2 Data Rate Internal Clock 0 5 Hz to 134 MHz full channel mode 1 0 Hz to 268 MHz half channel mode External Clock DC to 134 MHz full channel mode DC to 268 MHz half channel mode External Clock Input Polarity positive or negative Threshold 2 56 V to 2 54 V nominal programmable in 20 mV increments Sensitivity lt 500 MV p Impedance 1 KQ terminated to ground Data Depth 206 k full channel 51 2 k half channel 1 M full channel 2 M half channel optional 24 www tektronix com la Pattern Sequencing Characteristics Blocks Separate sections of pattern program that are output in a user definable order by the Sequencer Block pattern depth can be from 40 sequences full channel mode or 80 sequences half channel mode up to the entire depth of the TLA7PG2 A maximum of 4 000 Blocks may be defined Sequencer A 4 000 line memory that allows the user to pick the output order of individual Blocks Each line in the sequencer allows the definition of a Block to be output a Repeat Count for that Block A Wait For event condition for the Block the Signal state for that Block asserted or unasserted and
13. Multi processor Bus Analysis Digital Stimulus and Control Digital Signal Quality Analysis System Validation TLA Mainframe Selection Type of Mainframe Number of Module Slots Operating System Internal Display Resolution External Display Resolution Number of External Displays Standard Data Window Types Remote Control with Microsoft COM DCOM TLA Logic Analyzer Selection Channels Max Channels per Timebase merged Max Channels per Mainframe Max Channels per System Max Independent Buses per System State Clock Rate Max State Clock Rate half channel mode Max State Data Rate MagniVu Timing all channels all the time Simultaneous State and Timing Through Same Probe Analog Measurements Through Same Probe 4 www tektronix com la TLAGxx TLA715 TLA721 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes TLAGxx TLA715 TLA721 TLA7XM Non modular Modular Modular Expansion Modular N A 2 5 6 Microsoft Windows 2000 Professional N A 800x600 TLA61x 62x only 800x600 Requires external display N A TLA6Ox requires external display 1280x1024 1600x1200 1600x1200 N A 1 4 with two 4 with two N A PCMCIA video adapters PCMCIA video adapters Waveform Listing Histogram Performance Analysis Source Code N A Yes Yes Yes N A TLAGxx TLA7Nx Px Qx TLA7ZAxx 34 68 102 136 per instrument 34 68 102 136 per module 34 68 102 136 per module 136 272 in TLA715 272 in TL
14. do away with add on connectors and attach directly to printed circuit boards These connectorless probes use Silicon Germanium SiGe technology to provide high quality signal measurements Stimulus for Functional Verification System verification often requires you to stimulate your designs with ideal or faulty digital patterns The TLA pattern generator controls your circuit at full speed or steps through individual states With the combination of logic analyzer and pattern generator modules you can control and monitor real time system operation The Integrated View Today almost every design is a high speed design with fast clock edges and data rates on even the most common IC devices So nearly every design requires signal integrity analysis Engineers need to see the analog characteristics of high speed digital signals in relation to complex digital events in the circuit The solution iView The iView Integrated View capability seamlessly integrates data from Tektronix TLA logic analyzers and TDS oscilloscopes allowing designers to transfer analog waveforms from the oscilloscope to the logic analyzer display and automatically time correlate them The result engineers can quickly track down elusive signal integrity problems in their designs The new iView package includes TLA Application software and an interconnect cable to integrate TLA6OO or TLA700 Series logic analyzers with a wide range of external TDS Series oscillo
15. high as 800 MHz The inputs have provisions for differential and or parallel termination The input power is provided via two leads that are connected to a lower voltage and a higher voltage each DC isolated from the output allowing operation in both ECL and PECL systems Differential LVDS TTL to Single ended TTL Converter Pod Each channel is converted via a National semiconductor DS9OLV032A receiver supporting data rates in excess of 400 Mb s 200 MHz The inputs have provisions for differential terminations and have resistor diode input protection from over voltage For information or ordering please contact Dragonfly Software Development 4905 SW Griffith Drive Suite 100 Beaverton OR 97005 8724 503 643 3800 phone 503 626 9653 fax gt TLA7Dx Ex Digital Storage Oscilloscope Modules Includes Probes user manual certificate of calibra tion and one year warranty return to Tektronix TLA7D1 2 channel DSO module 500 MHz bandwidth 2 5 GS s sample rate 15 K depth includes two P6243 1 0 GHz active FET probes probe calibration adapter and manual TLA7D2 4 channel DSO module 500 MHz bandwidth 2 5 GS s sample rate 15 K depth includes four P6243 1 0 GHz active FET probes probe calibration adapter and manual TLA7E1 2 channel DSO module 1 GHz bandwidth 5 GS s sample rate 15 K depth includes two P6245 1 5 GHz active FET probes probe calibration adapter and manual TLA7E2 4 channel
16. 12 blue 25 mil 0 65 mm pitch oF503 SureFoot probe tip adapter pkg of 12 red 0 5 mm pitch SMG50 SMT KlipChip grabber tip 20 each SMK4 Micro KlipChip adapter 4 each 070 9408 00 P6243 Instruction Manual 070 8995 01 P6245 Instruction Manual www tektronix com la 39 Tektronix Logic Analyzers gt Detailed Product Information gt TLA7PG2 Pattern Generator Module TLA7PG2 64 channel pattern generator module 134 Mhz data rate 256 K depth please select probe option below Includes Four probe cables user manual certificate of calibration and one year warranty return to Tektronix Opt 1C Add 168 SMT KlipChip grabber tips Opt 1M Increase to 1 M depth Opt 1P Add four 16 channel P6470 TTL CMOS probes each includes two 8 channel leadsets and one 5 channel leadset Opt 2P Add four 16 channel P6471 ECL probes each includes two 8 channel leadsets and one o channel leadset Opt 3P Add four 16 channel P6472 PECL probes each includes one 8 channel leadset and one 5 channel leadset Opt 4P Add four 8 channel P6473 LVDS probes each includes two 8 channel leadsets and one o channel leadset Opt 5P Add four 16 channel P6474 LVCMOS probes each includes two 8 channel leadsets and one 5 channel leadset Opt 6P Add one 8 channel P6475 Variable probe with 115 V US Std power plug Includes 12 SMB to header coax cables Opt 7P Add one 8 channel P6475 Variable p
17. 61X 62X Wheeled Transport Case Order 016 1522 00 17 in Monitor Transport Case Order 016 1653 00 21 in Monitor Transport Case Order 016 1652 00 83 Key Notebook Keyboard PS2 Compatible Order 118 9402 00 TLA7QS TLA Family training package TLA configuration required 102 channels Opt A1 Universal Euro Opt A2 United Kingdom Opt A6 Japan TLA7QS Technical Reference Support Kit Order 020 2211 02 Tektronix Logic Analyzers gt Detailed Product Information TLAGOO Series Manuals TLA Family User Manual Order 071 0863 02 for Version 4 2 TLA application software TLA7QS Quickstart Training Manual Order 070 971 7 05 TLAGOO Series Service Manuals and Test Fixtures TLA60x 61x 62x Service Manual includes performance verification and adjustment procedures Order 071 0728 02 TLA Logic Analyzer Adjustment Fixture includes AC adapter requires local power cord Order 671 3599 00 gt TLA Family Service Options TLA6GXX TLA715 721 TLA7XM TLA7Axx TLAZNX PX QX TLA7PG2 TLA7DX EX Opt IN X X X X X X COE Ci em MS MS OC Cid Opt S1 C O Opt S3 E O Opt C5 __ H _ _ Opt D3 e e O X X X X Opt C3 X X X X X X X X X X X Opt D1 X X X X X X X X X Opt D5 O TLA Family Service Options Opt IN Product installation service on site configuration and user familiarization exc
18. Add full complement of P6417 17 channel general purpose probes that allow you to separate the 8 channel podlet groups into individual channels each includes two 8 channel leadsets one 1 channel leadset 20 SMT KlipChip grabber tips TLAGOX 61X Logic Analyzer Options Base configuration is 64 K depth at 100 MHz state Opt 1S Increase to 256 K depth at 100 MHz state Opt 4S Increase to 64 K depth at 200 MHz state Opt 5S Increase to 256 K depth at 200 MHz state TLAG2X Logic Analyzer Option Base configuration is 1 M depth at 100 MHz state Opt 6S Increase to 1 M depth at 200 Mtz state TLAGOO Series Upgrades You can upgrade the operating system TLA applica tion software increase DRAM and hard disk of your existing TLA600 logic analyzer You can also increase the memory depth and state speed of most existing TLA600 Series logic analyzers Please refer to TLA Family Upgrade Guide for further details TLAGOX 61X G2X Options Opt 1C Add iView external oscilloscope cable kit 012 1614 00 TLAGOX 61X 62X International Power Plugs Opt A1 Universal Euro 220 VAC 50 Hz Opt A2 UK 240 VAC 50 Hz Opt A3 Australian 240 VAC 50 Hz Opt A4 North American 240 VAC 60 Hz Opt A5 Switzerland 220 VAC 50 Hz Opt A99 No Power Cord TLAGOX 61X 6G2X Optional Accessories Logic Analyzer Cart LACART K4000 TLA60X 61X 62X Rackmount Kit Order 016 1790 00 TLA60X
19. And simultaneous state high speed timing and analog analysis pinpoints elusive faults The TLA Family also works with the world s first con nectorless logic analyzer probes only from Tektronix These high performance low capacitance 0 7 pF total capacitance active logic analyzer probes pro vide cleaner signals and reduce layout complexity and cost The probes support both single ended and differential signals with the same pattern This is the kind of performance you expect from Tektronix with productivity and connectivity tools that will greatly shorten your time to market Timing Resolution Whether you are debugging a high performance computer or part of an embedded system the timing parameters of your designs demand sub nanosec ond resolution Logic analyzers that only offer 4 ns timing resolution are simply not adequate to capture today s complex problems Nobody wants to trade off channels for resolution buy separate timing modules or trade up to more expensive hardware to get the resolution today s designs require The TLA Family with MagniVu acquisition provides 8 Ghz 125 ps timing resolution on every channel MagniVu Acquisition Technology A Breakthrough for Logic Analyzers The TLA Family includes a wide selection of logic ana lyzers with unprecedented measurement capabilities At the heart is a breakthrough acquisition technology called MagniVu MagniVu is a super high speed sam pling architec
20. DSO module 1 GHz bandwidth 5 GS s sample rate 15 K depth includes four P6245 1 5 GHz active FET probes probe calibration adapter and manual P6243 1 0 GHz active FET probe and accessories length 1 5 m P6245 1 5 GHz active FET probe and accessories length 1 5 m TLAZOO Series DSO Module Upgrades You can install a TLA7Dx Ex digitizing oscilloscope module into an existing TLA714 715 720 721 7XM mainframe Please refer to the TLA Family Upgrade Guide for further details Tektronix Logic Analyzers gt Detailed Product Information 131 9638 11 LK YY amp 214 4207 00 S503 WG z SF502 i AA SF501 A 196 3410 00 Z S AF QP 906 0364 00 196 3410 00 003 1433 00 SMG50 ZO 196 3410 00 ru D J by 214 4227 00 ong gt DSO Module Accessories gt TLAZOO Series DSO Module Upgrades 003 1383 00 Part Number Description 003 1383 00 Compensation box and cover removal tool 003 1433 00 Adjustment tool 016 1315 00 2 each 5 colors of cable markers 131 5638 10 10 each solderable probe tips 131 5777 00 100 mil square pin ground adapter 196 3410 00 Ground lead set includes N A 2 each 1 in 3 in 6 in ground leads w square pin receptacle N A 2 each Y lead adapters 196 3439 00 1 in ground lead 206 0364 00 SMT KlipChip 1 each 214 4227 00 Right angle square pin adapter SFog1 SureFoot probe tip adapter pkg of 12 yellow 50 mil pitch oFa02 sureFoot probe tip adapter pkg of
21. Modules Service Manual includes performance verification and adjustment procedures Order 070 9780 03 TLAZOO Series Mainframe Upgrades You can upgrade the operating system TLA application software increase DRAM and hard disk capabilities to your existing TLA 14 715 720 721 mainframe Please refer to TLA Family Upgrade Guide for further details gt TLAZAxx Logic Analyzer Modules Includes Probe retainer bracket probe manual user manual certificate of calibration one year warranty return to Tektronix Probes must be ordered separately Order Opt 2P P6810 or Opt 3P P6860 or Opt 4P P6880 You can also choose to order any combination and quantity of probes by ordering the P6810 P6860 or P6880 individually TLA7AA1 34 channel logic analyzer module 8 GHz timing 120 MHz state 128 K depth must select one probe option below Options for up to 32 M depth and or up to 450 MHz state TLA7AA2 68 channel logic analyzer module 8 GHz timing 120 MHz state 128 K depth must select one probe option below Options for up to 32 M depth and or up to 450 Mrz state TLA7AA3 102 channel logic analyzer module 8 GHz timing 120 MHz state 128 K depth must select one probe option below Options for up to 32 M depth and or up to 450 MHz state TLA7AA4 136 channel logic analyzer module 8 GHz timing 120 MHz state 128 K depth must select one probe option below Options for up to 32 M dept
22. Probe Connector 300 Vays but no greater than 420 V 1 MQ Or ground input coupling Probe Input Characteristics Probe Input Interface TEKPROBE probe interface Input Loading Less than 1 pF in parallel with 1 MQ with either P6243 or P6245 Usable Input Voltage Range at Probe Tip P6243 Probe 8 V P6245 Probe 18 V Trigger Actions Trigger trigger all set signal arm immediate wait for system trigger Edge Trigger Conventional level driven trigger positive or negative slope on any channel or exter nal trigger input Coupling Selections DC AC noise reject HF reject LF reject Pulse Width Trigger Triggers on width of positive or negative pulse either within or not within selec table time limits settable from 2 ns to 1 s Timeout Trigger Triggers when a pulse fails to complete when specified settable from 2 ns to 1 s Acquisition System Sample Rate Range 200 ps to 200 ms in 1 2 5 5 sequence Timebase Accuracy 100 ppm over any interval 1 ms Record Length Range 512 to 15 000 samples per channel in all modes Acquisition Modes Single shot repetitive Trigger System Trigger Modes Normal auto Trigger Position Anywhere in the acquired record pre fill can be set anywhere from 0 to 100 Trigger Types Edge pulse width timeout glitch runt slew rate logic pattern setup and hold violation Setup and hold Trigger Triggers
23. and Modularity Familiarity 1y Documents Eile Edit View Favorites Tools Actions Help anew amp B xX Ce Reply FoReply to All YE Forward GA sendjReceive BpFind ig Organize Inbox s EE Aa e a ea ment with the Microsoft Windows operating sys lt TITLA Waveform 1 Outlook Today Z File Edit View Data System Window Help A sa a DE L sas iae Bom Al tem the platform upon which the entire TLA Family Calendar BE Listing 1 is a L Hae seer AlAl ah Scan Listing Later gt He ed Ee el ena a alal ann is based perce eh C1 E cS E gt a 32 pzs al 32 pzs Delta Time 1 5us Inbox 1 a ee peeli TLA applications operate like any other PC un Samp le Address Physical Fe Mnemonic Internet F h E w en Sends Sent Items ee nt chr FILE device 52765 ee Sod ES application i tch Cch putc b041BA F28 MOVE L return Coutch chr T 32767 fputc 4 S04 1BC C e BE Work in a familiar open and connected environ T Debtedtem J stackei2c 00619 0000 Familiar Microsoft Windows toolbar and desktop t Out Pees a ie en Ce Ue wae ee OO612E D fgetc standard lib Stack 124 006124 pe eee Stack 126 006126 urns cha EOF YASIR SIN Inn Inna nanan aa nanananigy Fputc 8 6041c0 ill m P fputc A 6041 2 Remote Operation ie oe eee Fputc c 6041c4 getc evice Stack 120 006120 WRITE
24. bias voltage leadset 0 100 amp 2mm pins optional 100 ohm series resistor molded into barrel connector housing signal only Replacement available in 020 2196 00 Standard with LA Module The input resistance when used with a Reduced Bias Voltage leadset is 10 Kohms SMK4 optional gt P6417 gt P6417 TLAZP2 TLAZN2 TLAZN3 TLAZN4 4 6 8 4 2 3 4 2 4 6 8 4 TLAZP4 TLA7Q2 TLA7Q4 8 4 8 4 2 4 8 4 8 Part Number Description 010 6417 00 17 channel probe N A 2 each 8 channel podlet holders installed N A 1 set of 17 podlet color coding bands installed 334 9239 00 1 sheet of probe labels not installed 196 3431 01 1 each 8 channel leadset barrel connectors support 0 100 spacing 196 3432 00 1 each 1 channel leadset barrel connectors support 0 100 spacing 196 3477 00 1 each 8 channel reduced bias voltage leadset barrel connectors support 0 100 spacing 196 3478 00 1 each 1 channel reduced bias voltage leadset barrel connectors support 0 100 spacing SMG50 20 each SMT KlipChip grabber tips 013 0280 00 One to two adapter optional SMK4 Micro KlipChip grabber tip adapter 4 each optional 071 0567 00 P6417 P6418 Instruction Manual P6417 Probe Cable Length 1 8 m 6 ft P6434 Equivalent Grouit D 2 24 user 20K ohn LA Module l en a P6434 Option 01 407 4435
25. coi F 120 65 mm gt K4000 Instrument Cart 25 00 in 18 60 in 635 00 mm 472 20 mm Environmental Temperature Operating 5 C to 50 C Nonoperating 20 C to 60 C gt LACART Instrument Cart adjustable probe skyhook not shown Humidity Power Physical Characteristics 20 to 80 TLA715 TLA715 Portable Operating lt 30 C 80 relative humidity Voltage range frequency 90 250 VAC at 45 66 Hz Dimensions mm in 29 C maximum wet bulb temperature 100 132 VAC at 360 440 Hz Height 235 9 25 Nonoperating 8 to 80 29 C maximum wet Input current 6 A maximum at 90 VAC 70 A surge Width 432 17 bulb temperature Power consumption 600 W maximum Doh 4 amp 5 5 Altitude TLA721 and TLA7XM Weight kg Ib Operating 1 000 ft to 10 000 ft 305 meters Voltage range frequency 90 250 VAC at 45 66 Hz Net w o modules 11 4 25 to 3 050 meters 100 132 VAC at 360 440 Hz hiopina tvoical 255 56 _ i 7 Input current 16 5 A maximum at 90 VAC 70 A surge 2 ae a a A Power consumption 1 450 W maximum TLA721 Benchtop amp TLA7XM Expansion Dimensions mm in Height 346 12 65 Width 425 16 7 Depth 673 26 5 Weight kg Ib Net w o modules 22 1 50 Shippin ical 51 8 114 18 www tektronix com la sani PA i 0 a a gt TLAZAxx Logic Analyzer Modules General Number of Channels all channels are acquired including clo
26. for applications applications requiring for most for most applications uses that require requiring many many differential general purpose general purpose requiring many maximum flexibility for channels to be channels to be uses that require uses channels to be single ended or differential requirements quickly connected in a small footprint quickly connected in a small footprint maximum flexibility quickly connected in a small footprint Attachment to Target System Probe leadsets Connectorless Connectorless Probe leadsets Probe leadsets AMP Mictor 34 adapt to industry compression contact compression contact adapt to industry adapt to industry channel connector standard interfaces Adapter for Adapter for standard interfaces standard interfaces Adapter to use P6434 leads spread over Mictor connector Mictor connector leads spread over with P6860 80 a wide area available available a wide area high density compression land footprint available Probe Type General purpose High density High density General purpose General purpose High density 34 channel 34 channel 34 channel 17 channel 17 channel 34 channel active probe active probe active differential passive probe passive probe passive probe probe AMP Mictor connector required Pin Spacing Supported 0 100 in and 2 mm N A N A 0 100 in 0 100 in N A Logic Signals Supported Differential Clock Differential Clock Differential Clock Single ended Clock Single ended Clock Si
27. glitches and intermittently alter the timing of otherwise stable signals Connecting an external digitizing oscilloscope to your TLA system with Integrated View capability provides up to 6 GHz analog signal bandwidth along with the hundreds of logic signals you are already monitoring Since the external Tektronix dig ital oscilloscope data is automatically time corre lated the iView capability lets you easily observe the quality of critical signals alongside the original behavior they affect Probing Solutions Whether you are building high density test connec tors into your verification platform using a config ured probe adapter for popular microprocessors or buses or just hooking up signals as you need more visibility Tektronix has the probing solution 10 www tektronix com la Digital and Analog Through a Single Probe Here is an innovation the world of test and meas urement has needed simultaneous analog and digi tal measurements through a single logic analyzer probe No more having to get out your oscilloscope probe for analog information Now one probe does it all You get quick signal access with no double probing no double loading and no more trying to handle two probes at once Nothing is easier or yields cleaner signals gt Digital analog overlay P68S60 8S0 Connectorless Logic Analyzer Probes Tektronix offers a family of new high performance low capacitance active logic analyzer probes which
28. hardware signals Real time Instruction Trace TLA software includes disassembly capability for analyzing every bus transaction and determining what instructions were read across the bus The software then places the assembly mnemonic in the display with the associated address This disas sembly display enables you to view the data at dif ferent levels of abstraction The state display provides a view of raw hex data The hardware display shows every bus cycle type with instructions The software display filters out the noninstruction cycles The flow control shows only instructions that cause a change in the pro gram flow and the subroutine display shows only the entry and exit points to subroutines Real time Correlation to Hardware With the TLA s time stamp always running every acquisition and every bus cycle has a unique 125 ps time stamp Because of this capability the TLA700 Series provides precision time correlation across ALL the modules in the TLA700 system even across expansion mainframes This allows you to see how the event on one bus affects the opera tion of another bus in the system www tektronix com la 11 Tektronix Logic Analyzers gt Detailed Product Information Al Al 2 0l tages Based Or All Samples 163 850 Range Count Process_Data 24 516 4 Init_1I o 14 901 9 Output 14 896 9 StopLite 9 235 5 Display_Routine 7 446 4 Empty_Queue 441 4 Destroy_Queue 3 084 ii Init Queue
29. logic analysis data to generate simulation vectors Easily perform hardware verification by comparing captured data with simulation data Documentation Remote Programming Documentation Capability Data Export Remote Programming with Microsoft s COM DCOM Interface TLA Application Software Microsoft Windows 2000 Professional Multiple Analysis Windows Global Cursors and Marks Flexible Data Views Web Enabled System Network Security 8 www tektronix com la Utilize the pre installed Snaglt graphical capture software to save graphics as TIF PCX JPG BMP GIF files or send them directly to a local or networked printer Capture any window region or object on the screen Start Snaglt directly from the TLA application software Export data in ASCII binary or Tektronix tla file formats for offline use Control logic analyzer operation using TLA Programmatic Interface TPI providing automated operation of the TLA Open Windows interface provides a familiar user interface and network connectivity View data in waveform listing source or histogram windows to better analyzer cross domain data from a target system Lock multiple windows of data together for improved analysis of correlated data Utilize multiple cursors and user definable marks to aid in the analysis of data across multiple data windows Lock cursors together in data windows providing constant offsets to make
30. logic analyzer module 2 GHz timing 100 MHz state 16 M depth must select one probe option below Option for up to 200 MHz state TLA7P4 136 channel logic analyzer module 2 GHz timing 100 MHz state 16 M depth must select one probe option below Option for up to 200 MHz state TLA7Q2 68 channel logic analyzer module 2 GHz timing 100 MHz state 64 M depth must select one probe option below Option for up to 200 MHz state TLA7Q4 136 channel logic analyzer module 2 GHz timing 100 MHz state 64 M depth must select one probe option below Option for up to 200 MHz state Logic Analyzer N P amp Q Module Probe Options Opt 1P Add full complement of P6418 17 channel general purpose probes each includes two 8 channel leadsets one 1 Channel leadset 20 SMT KlipChip grabber tips Opt 2P Add full complement of P6434 34 channel high density probe s Opt 3P Add full complement of P6417 17 channel general purpose probes that allow you to separate the 8 channel podlet groups into individual channels each includes two 8 channel leadsets one 1 channel leadset 20 SMT KlipChip grabber tips Logic Analyzer N Module Options Base configuration is 64 K depth at 100 MHz state Opt 1S Increase to 256 K depth at 100 MHz state Opt 2S Increase to 1 M depth at 100 MHz state Opt 3S Increase to 4 M depth at 100 MHz state Opt 4S Increase to 64 K depth at 200 MHz state
31. mV Minimum pulse width 150 ns P6475 Probe Cable Length 1 6 m 5 ft www tektronix com la 27 Tektronix Logic Analyzers gt Detailed Product Information esas Seem 2 gt TLAGOO Series General Number of Channels all channels are acquired including clocks TLA601 611 621 TLA7N1 34 channels 2 are clock channels TLA602 61 2 622 TLA7N2 TLA7P2 68 channels 4 are clock channels TLA603 61 3 623 TLA7N3 102 channels 4 are clock and 2 are qualifier channels TLA604 61 4 624 TLA7N4 TLA7P4 136 channels 4 are clock and 4 are qualifier channels Channel Grouping No limit to number of groups or number of channels per group all channels can be reused in multiple groups Time Stamp 50 Bit at 500 ps resolution 6 5 day range Clocking Acquisition Modes Internal internal 2X external 2 GHz MagniVu high speed timing is available simultaneous with all modes Input Characteristics with P6417 P6418 or P6434 probes Capacitive Loading 1 4 pF typical data 2 pF typical clock P6418 2 pF typical data and clock P6417 amp P6434 Threshold Selection Range From 5 0 V to 2 0 V in 50 mV increments Threshold Selection Channel Granularity separate selection for clock 1 and data 16 for each 17 channel probe connector 28 www tektronix com la we ET CN sf ERRES 2d3938 7 FRERES JJJ JII LEE Threshold Accuracy including probe
32. of Transition Recognizers 1 Number of Counter Timers 2 www tektronix com la 21 Tektronix Logic Analyzers gt Detailed Product Information Trigger Event Types Word group channel transition range anything counter value timer value signal glitch setup and hold violation Trigger Action Types Trigger module trigger all Store don t store start store stop store increment counter reset counter start timer stop timer reset timer goto state set clear signal do nothing Trigger Sequence Rate DC to 250 MHz 4 ns Counter Timer Range 51 Bits each gt 100 days at 4 ns Counter Rate DC to 250 MHz 4 ns Timer Clock Rate 250 MHz 4 ns Counter Timer Latency None can be tested or reset immediately after starting Range Recognizers Double bounded can be as wide as any group must be grouped according to specified order of significance Setup and hold Violation Recognizer Setup Time Range From 8 ns before to 7 ns after clock edge in 0 5 ns increments Setup and hold Violation Recognizer Hold Time Range From 7 ns before to 8 ns after clock edge in 0 5 ns increments Trigger Position Any data sample MagniVu Trigger Position MagniVu data is centered around the module trigger Storage Control data qualification Global conditional by state start stop by trigger action or transitional Storage Window Granularity Single sample
33. 01 105 1088 00 01 epi al 00 optional 105 1089 00 For ordering contact Amp Inc x Standard with LA Module gt P6434 P6434 TLA7Nx Px Qx Option 2P The P6434 is a lightweight probe with quick connect disconnect and a positive latching mechanism to ensure a secure reliable connection It is for use with 1 applications where you have designed in the AMP Mictor high density connectors into your target system or 2 direct connection to newer TLA family processor bus support probe adapters with AMP Mictor 34 channel probe connectors An optional low profile adapter for low clearance applications is also available This probe is recommended for all high density applications 34 channel High density Probe and Accessories for TLA7LX Mx TLA7Nx Px Qx Logic Analyzer Modules Order P6434 Tektronix Logic Analyzers gt Detailed Product Information gt UPIK3M P6417 to 3M Type 3592 2x10 0 1 in Adapter Order UPIK3M 5 ea Order 671 2508 00 1 ea gt P6434 34 channel Probe Interface Kit w Barrel Connectors Order 020 2199 00 34 channel Probe Interface Kit w Mini PV Part Number Description Connectors Order 020 3000 00 010 6434 00 34 channel probe N A 1 sheet of probe labels not installed 105 1088 00 1 latch housing assembly edge mount 105 1089 00 1 latch housing assembly vertical 070 9793 02 P6434 Instruction Manual 131 6134 01 1 each AMP mictor conne
34. 1x and TLA62x TLA60x Table of Contents Logic Analyzers TLA Family Selection Guide Tektronix Logic Analyzer Probe Selection Guide system Overview Breakthrough Solutions for Real time Digital Systems Analysis Find and Analyze your Difficult Real time software Problems Enhance Productivity through Familiarity Connectivity and Modularity Tektronix Logic Analyzers gt Detailed Product Information J Characteristics 4 TLA700 Series Mainframes ooa ca saamata meea 15 6 TLA7Axx Logic Analyzer Modules 00000 19 7 TLA7Nx Px Qx Logic Analyzer Modules 21 TLA7Dx Ex Digital Storage g Oscilloscope Modules 0 0000 ee 22 TLA7PG2 Pattern Generator Module 24 11 TLAGQO SerieS 0 cece eect eee 28 Ordering Information Ue TLA700 Series Mainframes oa ra saanee paene 32 TLA7Axx Logic Analyzer Modules 000005 30 TLA7Nx Px Qx Logic Analyzer Modules 05 30 TLA7Dx Ex Digital Storage Oscilloscope Modules 0 0 0 cee ee 39 TLA7PG2 Pattern Generator Module 40 WEABUO SGiIES Fo aurea een erew cr aeimrne aan teenies 42 TLA Family Service Options 0 cee ee 43 www tektronix com la 3 Tektronix Logic Analyzers gt Detailed Product Information TLA Family Selection Guide Applications Timing and State Analysis Single processor Bus Analysis Real time Instruction Trace Analysis Source Code Debug Performance Analysis
35. 232 Interface Module required for iView Active Matrix TFT LCD 3 5 Floppy Disk Drive System Trigger IN PARE capability on any TDS3000 Series TDS3GV Sieg GPIB RS232 VGA Interface Module required for e o General Purpose UZ n EE iView capability on any TDS3000B Series If using o is P b6b0 gt Serial Port iView with a TDS6604 order a TCA BNC connector eee eal ans to be compatible with BNC cable run from a opooaboooaaooa BaseT LAN TLA7 A d I Retractable i mane y SER Number of TDS Oscilloscopes that Can be E A saeco fies A aah Sven Connected to a TLA system 1 Soft On Standby FulLOWERTY Power Switch Expansion Slots PS2 Port Power Switch Keypad External Oscilloscopes Supported Logic Analyzer Horizontal Vertical TDS3012 TDS3014 TDS3032 TDS3034 EOE SUNN TDS3052 TDS3054 TDS301 2B TDS301 4B TDS3032B TDS3034B TDS3052B TDS3054B TDS5052 TDS5054 TDS5104 gt TLA61x 62x Logic Analyzer with internal display TDS6604 TLA Connections USB Trigger In Trigger Out TLAGOO PC Characteristics 1057054 TDS7104 1057154 TDS7404 Clock Out Operating System Microsoft Windows 2000 esa oa TDS Connections GPIB Trigger In Trigger Out pices CSA7154 CSA7404 Clock In when available Processor Intel Celeron TDS754C TDS784C TDS724D TDS754D o Grineck iieii TDS784D TDS794D Setup iView external oscilloscope wizard ipset Inte l automates setup DRAM 256 MB SDRAM 512 MB with Opt
36. 3 078 aks Processor Support ee nN SW tch 2 3 485 1 TLA processor support provides an easy to use _ System Performance Analysis acquisition and analysis package The software l l d pees This feature lets you nonintrusively monitor capture and analyze the system s real time software and hardware automatically sets up the TLA including assignin ee y P 9 Bg performance Using the performance analysis tool you can quickly identify software and hardware areas to channels and programming the clocking state ae be optimized machine for your particular processor This enables the TLA to acquire every bus cycle quickly and seamlessly in real time Many of the support pack ages provide a probe adapter using the Tektronix P6434 high density probe to connect to the processor or bus being analyzed The probe pro vides quick connection to 34 channels and elimi nates possible human error Tektronix Embedded Systems Tool Partners Over 25 industry leading Embedded Systems Tools Partners deliver a wide range of development and debug solutions that work with Tektronix logic analyzers Software development tools such as software debuggers and emulators running on the TLA logic analyzer provide you with the complete system control and insight critical to verifying debugging and optimizing your system 12 www tektronix com la Tektronix Logic Analyzers gt Detailed Product Information Enhance Productivity through Familiarity Connectivity
37. 4 TDS754C TDS784C TDS724D TDS754D TDS784D TDS794D TLA Connections USB Trigger In Trigger Out Clock Out TDS Connections GPIB Trigger In Trigger Out Clock In when available Setup iView external oscilloscope wizard automates setup Data Correlation After TDS oscilloscope acquisition is complete the data is automatically transferred to the TLA and time correlated with the TLA acquisition data Deskew TDS and TLA data is automatically deskewed and time correlated when using the iView external oscilloscope cable iView External Oscilloscope Cable Length 2 m 16 www tektronix com la General Purpose Knob Snaps for Removable Pouch Trackball _1_ Four Single wide _2 or Two Dual wide _3 Slots for Instrument _4 Expansion Modules Rear Feet Cord Wrap CD ROM Active Matrix TFT LCD Horizontal Vertical Function Soft ON Standby Run Stop Mini QWERTY Retractable Replaceable Hard Disk Handle Tilting Feet Power Switch Key Keypad PC Card Expansion Slots System Trigger IN System Trigger OUT gt TLA715 Portable Mainframe Soft On Standby Power Switch
38. 51 00 2 each Elastomer Holder Assembly Thin used on lt 0 093 in thick PCB 020 2452 00 2 each Elastomer Holder Assembly Thick used on gt 0 093 in thick PCB 335 0697 00 1 each Sheet of Probe Labels NOTE Recommend PEM KFS 256 or equivalent for gt 0 093 in thick PCB P6880 Probe Cable Length 1 5 m 5 ft gt TLAZNx Px Qx Logic Analyzer Modules Includes Probe retainer bracket probe manual user manual certificate of calibration one year warranty return to Tektronix Probes must be ordered separately Order Opt 1P P6418 or Opt 2P P6434 or Opt 3P P6417 You can also choose to order any combination and quantity of probes by ordering the P6418 P6434 or P6417 individually TLA7N1 34 channel logic analyzer module 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 4 M depth and or 200 MHz state TLA7N2 68 channel logic analyzer module 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 4 M depth and or 200 MHz state TLA7N3 102 channel logic analyzer module 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 4 M depth and or 200 MHz state TLA7N4 136 channel logic analyzer module 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 4 M depth and or 200 MHz state TLA7P2 68 channel
39. 62669 USP 26562761 gt stop tePause 1C SFC 66666666 DFC 66666667 stop itePause 1E stop itePause C stop itePause E stop itePause 10 36 stop itePauseCint speed 3 int idlel idle2 for Cidist speed idlel gt A idlel r Cidle2 SPEED C idle2 tt tcurrentstate _ _ re or Help nae Fi l Client Connected l za Tektronix AMstart E 6 A Ayocd Commander E TLA 700 Listing 1 BS 5 01 PM Tektronix TLA 7XX Logic Analyzer OF x Seq Address Data Ctrl Timestamp C Use This TLA 0 FF60457E 0000 8FC7 171000 aq Uae Remote TLA fw TLA253 r TLA Setup Dialog 1 FF604580 0007 8FC7 546000 z gt Remote operation www tektronix com la 13 Tektronix Logic Analyzers gt Detailed Product Information PC CARD TYPE 2 TYPE 3 sys TRIG I N T gt Connectivity Connectivity and Modularity All models of the TLA family except the TLA6Ox come standard with dual display capability for extended desktop viewing These models also fea ture an internal CD R W hard disk and PC card Slots for expansion such as for a LAN connection Other industry standard PC connections include SVGA printer serial USB mouse and keyboard Trigger in out connections provide an interface to other external instrumentation for coordinating measurement results The replaceable hard disk is standard on the TLA700 series ideal for security or enabling individual team members to store personal se
40. 8 Mb memory depth TLA7Nx Px Qx Logic Analyzer Modules TLA6xx Logic Analyzers TLA7Dx Ex Digital Oscilloscope Modules capability provide the tools necessary to address a wide range of digital designs 2 GHz MagniVu timing 100 to 200 MHz state acquisition up to 400 Mb s data rate and 64 Kb to 2 Mb memory depth capability provide analysis tools to address mainstream digital design and debug 500 MHz and 1 GHz 2 5 and 5 GS s 2 and 4 channel oscilloscope modules provide analog trace capture time correlated with TLA7PG2 Pattern Generator Module digital data 64 Channel up to 268 MHz and up to 2 Mb vector depth along with probes supporting multiple logic levels and variable delays provides a flexible solution for device simulation and hardware verification Up to 6 GHz 20 GS s 4 channel TDS oscilloscope data automatically time correlated with TLA digital data on the logic analyzer Integrated View iView MagniVu Technology display Route any four logic analyzer input channels to the four analog signal output BNC connectors on the TLA7Axx module Connect an internal oscilloscope module or external TDS oscilloscope to view analog signal information Analog signal outputs are always active allowing visibility of analog information at all times MagniVu acquisition technology provides up to 125 ps timing resolution simultaneous with state acquisition on all channels all the time www tektronix co
41. 81 94 11 1 Input current 6 A maximum at 90 VAC 70 A surge Width 457 2 18 Power consumption 400 W maximum Doth asao B3 Weight kg Ib Net w o probes 16 8 of Shippin ical 38 6 85 TLA61x 62x Dimensions mm in Height 281 94 11 1 Width 457 2 18 Depth 414 02 16 3 Weight kg Ib Net w o probes 17 3 38 Shippin ical 39 1 86 Tektronix Logic Analyzers gt Detailed Product Information i 28 75 in 731 mm 24 00 in 610 mm 56 00 in 1423 mm 4 75in 30 50 in DA EA 25 00 in 775mm 635 mm gt K4000 Instrument Cart Environmental Temperature Operating 5 C to 50 C Nonoperating 20 C to 60 C Humidity 20 to 80 Operating lt 30 C 80 relative humidity 29 C maximum wet bulb temperature Nonoperating 8 to 80 29 C maximum wet bulb temperature Altitude Operating 1 000 ft to 10 000 ft 305 meters to 3 050 meters Safety UL3111 1 CSA1010 1 EN61010 1 IEC61010 1 www tektronix com la 31 Tektronix Logic Analyzers gt Detailed Product Information Ordering Information gt TLAZOO Series Mainframes TLAZ15 Dual Monitor Portable Mainframe Includes Wheel mouse keyboard LAN PC Card front panel cover accessory pouch two dual wide panel fillers for empty slots printer adapter power cord North American 120 VAC 60 Hz software user manual certificate of calibration and one year warrant
42. A715 408 in TLA721 680 in TLA721 136 272 in TLA715 272 in TLA715 680 in TLA721 680 in TLA721 136 1 768 with TLA715 and two TLA7XMs 1 768 with TLA715 and two TLA7XMs 8 160 with TLA721 and ten TLA7XMs 8 160 with TLA721 and ten TLA7XMs 1 13 with TLA715 and two TLA7XMs 13 with TLA715 and two TLA7XMs 60 with TLA721 and ten TLA7XMs 60 with TLA721 and ten TLA7XMs 100 MHz std 100 MHz std 120 MHz std 200 MHz opt 200 MHz opt 235 450 MHz opt 200 MHz 200 MHz 800 MHz 400 200 Mb s half full channels 2 GHz 500 ps with 2 Kb depth Yes No 400 200 Mb s half full channels 2 GHz 500 ps with 2 Kb depth Yes No 1 250 900 450 Mb s quarter half full channels 8 GHz 125 ps with 16 Kb depth Yes Yes TLA Logic Analyzer Selection cont Deep Timing Memory Depth Source Synchronous Clocking Analog Outputs four per module analog MUX Digital Storage Oscilloscope Capability Channels per Module Max Channels per Mainframe Max Channels per System Bandwidth Sample Rate Vertical Resolution Memory Depth TLA Pattern Generator Module Channels Max Channels per Bus merged Max Channels per Mainframe Max Channels per System Pattern Speed half full channels Memory Depth half full channels Logic Families Supported TLA6xx 500 MHz 2 ns 250 MHz 4 ns half full channels 128 64 Kb to 2 1 Mb half full channels with timestamp Tektronix Logic Analyzers TLAZNx Px Qx 500 MHz 2 n
43. Clock Output Delay 2 4 ns typical External Clock Input to Clock Output Delay Full channel mode 61 5 ns typical Half channel mode 61 5 ns typical Number of External Event Inputs 1 Number of External Inhibit Inputs 1 External Inhibit Input to Output Enable Delay 34 ns typical for Data Output External Inhibit Input to Output Disable Delay 86 ns typical for Data Output Probe D Data Output to Output Enable Delay for Internal Inhibit 7 ns typical for Data Output Probe D Data Output to Output Disable Delay for Internal Inhibit 8 ns typical for Data Output External Event Input to Clock Output Setup for inhibit event filter off Full channel mode 1 5 clocks 150 ns typical Half channel mode 2 clocks 150 ns typical External Event Input and Inhibit Input Input Type 74LVC14A Minimum Pulse Width 100 ns Tektronix Logic Analyzers gt Detailed Product Information P6470 TTL CMOS Probe Rise Fall Time 20 to 80 Timing values measured using 75 Q termination internal to probe 1 MQ lt 1 pF load and Vp set to 5 0 V Clock Strobe Output Rise 640 ps typical Fall 1 1 ns typical Data Output Rise 680 ps typical Fall 2 9 ns typical Timing values measured using 75 Q termination internal to probe 510 Q 51 pF load and Voy set to 5 0 V Clock Strobe Output Rise 6 5 ns typical Fall 6 3 ns typical Data Output Rise 0 2 ns typical Fall 4 5
44. Del 2 ns for data output ata Output to Strobe Output Delay 2 93 ns when strobe delay set to zero Probe D Data Output to Output Disable Delay Data Output to Clock Output Delay 1 12 Ora up ata Output to Clock Output Delay 1 12 ns P External Event Input to Clock Output Setup External Clock Input to Clock Output Delay Full channel mode 1 5 Clocks 180 ns 90 ns Half channel mode 2 Clocks 180 ns Event Input Voltage Level PECL LVPECL External Event Input and Inhibit Input Input Type 100EL91 unterminated Input Type LVDS positive true Minimum Pulse Width 150 ns Minimum Pulse Width 150 ns 26 www tektronix com la P6474 LVCMOS Probe Number of External Event Inputs 2 Number of External Inhibit Inputs 1 Output Type 74AVC16244 for data clock strobe outputs Series Terminator Resistor 75 Q standard 43 100 and 150 Q optional Rise Fall Time 20 to 80 Load 1 MQ lt 1 pF Rise lee NS Fall 610 ps typical Load 512 Q 50 pF Rise 3 4 ns Fall 3 2 11S Output Voltage Level 1 2 V to 3 3 V 25 mV step into 1 MQ Data Output Skew lt 590 ps between all data output pins of all modules in the mainframe after inter module skew is adjusted manually lt 500 ps between all data output pins of all probes of a single module lt 460 ps between all data output pins of a single probe Data Output to Strobe Output Delay 460 ps when stro
45. Ges i You can remotely operate the TLA user interface ia SULEN 2 eee mae from another Windows or UNIX workstation and F http C1 10 1ns ns Delta Time 1 5ns B File Edit View Favorites Tools Hf 32 Magq_IFETCH 1 1 d TE customize the TLA user interface to fit your Back o gt 2 Qisea D j Address CPU se Maa_Semph working style FAIRIES A19 A16 DSO IFETCH Control your TLA remotely using a Web browser mso Develop your own custom tools that access TLA ee data using the TLA Programmatic Interface TPI any based upon Microsoft COM DCOM Remotely view your target system operation across the network using a Webcam from the a TLA 700 Listing 1 comfort of your office File Edit View Data System Window Help S S BE 2 Status ide Run TLA Camera j m OCD Commander File Logging Defaults Commands Help E Listino 1 AP SE e aA tal e cou ee ago aaj rome aa Teer 55 z fea ro 6660624A SFC 68606066666 DFC 66666067 G Q Start Address ae O8060065E 006 04468 currentState 2 stop i ter ausatig 53 666661F6 66666296 stop itePause stop itePause 1C FFFFFFFF FFFFF 6686 pa heir ir 53 FFFFFFFF 666 04302 stop itePause stop itePause E 66666669 666 042E2 Topli Ra 0 FFFFFFFF 66666166 stop itePause stop itePause 14 1 666663E8 66666666 stopli taP asat16 7 66666464 6666624A currentSta erent hata ei CAP 53 686664588 CR 666
46. Logic Analyzers gt Detailed Product Information INILNd WO m o z z am ior gt So wn heed ht 4s A Ty Selle Sr a T or a D E a y k J ee ne a a a nM ee fm 2 gt TLA600 and TLA700 Series Logic Analyzers TLA Family The TLA Family of logic analyzers consists of the TLA600 Series and the TLA700 Series The TLAGOO Series offers a selection of stand alone logic analyzer instruments at prices that make 500 ps timing resolution available to designers of today s mainstream embedded systems The TLA700 Series offers the highest performance for today s demanding applications and consists of portable and benchtop modular mainframes with expansion mainframe capability Instrument modules include logic analyzer pattern generator and digital oscilloscope A full line of complementary support products for popular processors and buses is available for the entire TLA family P 8 GHz MagniVvu Acquisition Technology Provides up to 125 ps Timing Resolution on All Channels All the Time Through the Same Probe gt Up to 800 MHz State Acquisition with 1 25 Gb s Data Rate for Advanced Processors and Buses gt Simultaneous State High speed Timing and Analog Measurement Analysis Through the Same Probe Pinpoints Elusive Faults 1 www tektronix com la gt 34 68 102 136 Channel Logic Analyzers with up to 256 Mb Depth with Hardware accelerated Waveform Display and Search Functions to Rapidly Analyze Acquired Data
47. NCA Event Inhibit Input 72014A P6470 TTUCMOS Equivalent Circuit 012 1580 00 lt ase 206 0364 00 optional gt P6470 r Data Output 1006151 Strobe Output 100EL16 Clock Output 100EL04 Event Input 10H 116 P6471 ECL 75ko Equivalent Circuit VBB 7 Fd gt P6471 16 channel ECL Probe and Accessories for TLA7PG2 Pattern Generator Module Order P6471 Part Number Description 012 1581 00 2 each 8 channel leadsets 012 1580 00 1 each 5 channel leadset 012 1570 00 Probe cable optional std with TLA7PG2 module 071 1017 01 Pattern Generator Probe User Manual j 43 ohm 1 Data Output 100EP90 012 1570 00 10 mA GND 43 ohm Clock Strobe Output 100EP90 43 ohm 10 MA 10 MA GNDGND Event Input L E 206 0364 00 optional gt P6472 8 channel PECL LVPECL Probe and Accessories for TLA7PG2 Pattern Generator Module Order P6472 Part Number Description 012 1581 00 1 each 8 channel leadset 012 1580 00 1 each 5 channel leadset 012 1570 00 Probe cable optional std with TLA7PG2 module 071 1017 01 Pattern Generator Probe User Manual Data Out Complies with TI AEI A 644 standard oa 570 00 ES
48. a 41 Tektronix Logic Analyzers gt Detailed Product Information gt TLAGOO Series TLAGOx Logic Analyzer with External Display Includes Wheel mouse keyboard front panel cover accessory pouch probe retainer bracket probe man ual power cord North American 120 VAC 60 Hz software user manual certificate of calibration and one year warranty return to Tektronix Display is not included Probes must be ordered separately Order Opt 1P P6418 or Opt 2P P6434 or Opt 3P P6417 You can also choose to order any combination and quantity of probes by ordering the P6418 P6434 or P6417 individually TLA601 34 channel logic analyzer 2 GHz timing 100 Mhz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mhz state Requires external display TLA602 68 channel logic analyzer 2 GHz timing 100 Mhz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mhz state Requires external display TLA603 102 channel logic analyzer 2 GHz timing 100 Mhz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mhz state Requires external display TLA604 136 channel logic analyzer 2 GHz timing 100 Mhz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mhz state Requires external display 42 www tektronix com la gt Quant
49. a Jump If event Condition with a sequence line to jump to if the condition is satisfied Sub sequences Up to 50 contiguous lines of the Sequencer memory may be defined as a sub sequence A Sub sequence can then be treated like a block Example 15 Sequences of Blocks are defined as Sub sequence A1 Now any line in the sequencer can output A1 Five calls to Sub sequence A1 will be flattened out to 75 sequences at run time Jump If Jumps to the specified sequence if a user defined event is true The user defined event is a boolean combination of the eight external event input lines and the one of four intermodule signals The user defined event is selectable between level and edge event going from false to true One Jump If may be defined for every Block The Jump If command works at all clock rates including the maximum half channel mode rate of 268 MHz Wait For Pattern output is paused until the user defined Event is true One Wait For may be defined for every Block Assert Signal One of the four inter module signals is selected to be controlled from the pattern generator program Signals may be asserted and unasserted allowing true interaction with the logic analyzer modules and with other pattern generator modules Signal action assert or unassert may be defined for every Block Repeat Count The sequence is repeated from 1 to 65 536 times Infinite may also be selected One Repeat Count may be defined
50. alyzers gt Detailed Product Information Setup and hold Violation Recognizer Setup Time CD ROM Range From 8 ns before to 7 ns after clock edge Esteinal Signal OUT ne in 0 5 ns increments External Signal IN Audio OUT Setup and hold Violation Recognizer Hold Time Snaps Tor egov e Fouc Baiso g Disk Dri Range From 7 ns before to 8 ns after clock edge ogee te i Se a 7 a A T SVGA External in 0 5 ns increments Display Port F4 a D Trigger Position Any data sample i i Serial Port MagniVu Trigger Position MagniVu data is ina centered around the module trigger oO BaseT LAN Storage Control data qualification Global SS a conditional by state start stop by trigger action Primary ON OFF Fuses AC Power PCCard Keyboard or transitional Soft On Standby loge Anilyzer Retractable Power Switch Expansion Slots PS2 Port Power Switch Probe Connectors Tilting Feet Storage Window Granularity Single sample or block of 31 samples before and after gt TLAGOx Logic Analyzer with external display Integrated View iView Capability TLA Mainframe Configuration Requirements TLA6XX instruments TLA App S W V 4 1 or greater eae CD ROM 256 MB DRAM Minimum 512 MB recommended N a TDS Configuration Requirements TDS3GM Snaps for Removable Pouch System Trigger OUT USB Port 0 GPIB RS
51. be delay set to Zero Data Output to Clock Output Delay 1 84 ns External Clock Input to Clock Output Delay 90S External Inhibit to Output Enable Delay 36 ns for data output External Inhibit Input to Output Disable Delay 18 ns for data output Probe D Data Output to Output Enable Delay 6 ns for data output Probe D Data Output to Output Disable Delay 7 ns for data output External Event Input to Clock Output Setup Full channel mode 1 5 clocks 180 ns Half channel mode 2 clocks 180 ns External Event Input and Inhibit Input 74AVC16244 Positive True 1 KQ to ground The Vcc of the input receiver is variable and is the same as the output driver Minimum Pulse Width 150 ns P6470 Probe Cable Length 1 6 m 5 ft P6471 Probe Cable Length 1 6 m 5 ft P6472 Probe Cable Length 1 6 m 5 ft P6473 Probe Cable Length 1 6 m 5 ft P6474 Probe Cable Length 1 6 m 5 ft P6475 Variable Probe Rise Fall Time 20 to 80 Load 1 MQ lt 1 pF Rise 000 ps Fall 640 ps Load 512 Q 50 pF Rise 430 ps Fall 010 ps Output Voltage Level Vo 3 V to 6 5 V 10 mV step into 1 MQ Voy 2 5 V to 7 V 10 mV step into 1 MQ Output Voltage Swing 250 MV to 9 Vp p Output Voltage Control Ch 0 to Ch 5 Common Ch 6 to Ch 7 clock Independent Accuracy 3 of value 0 1 V Delay Channels Ch 6 and Ch 7 Independent Delay Time
52. below Options for up to 256 K depth and or 200 Mrz state TLAG2x Logic Analyzer with Internal Display Includes Wheel mouse keyboard front panel cover accessory pouch probe retainer bracket probe man ual power cord North American 120 VAC 60 Hz software user manual certificate of calibration one year warranty return to Tektronix Probes must be ordered separately Order Opt 1P P6418 or Opt 2P P6434 or Opt 3P P6417 You can also choose to order any combination and quantity of probes by ordering the P6418 P6434 or P6417 individually TLA621 34 channel logic analyzer 2 GHz timing 100 Mhz state 1 M depth must select one probe option below Option for up to 200 Mrz state TLA622 68 channel logic analyzer 2 GHz timing 100 Mhz state 1 M depth must select one probe option below Option for up to 200 Mrz state TLA623 102 channel logic analyzer 2 GHz timing 100 Mhz state 1 M depth must select one probe option below Option for up to 200 Mrz state TLA624 136 channel logic analyzer 2 GHz timing 100 Mhz state 1 M depth must select one probe option below Option for up to 200 Mrz state Logic Analyzer Probe Options Opt 1P Add full complement of P6418 17 channel general purpose probes each includes two 8 channel leadsets one 1 channel leadset 20 SMT KlipChip grabber tips Opt 2P Add full complement of P6434 34 channel high density probe s Opt 3P
53. cks TLAZAAT1 34 channels 2 are clock channels TLA7AA2 TLA7AB2 68 channels 4 are clock channels TLA7ZAAS 102 channels 4 are clock and 2 are qualifier channels TLA7AA4 TLA7AB4 136 channels 4 are clock and 4 are qualifier channels Channel Grouping No limit to number of groups or number of channels per group all channels can be reused in multiple groups gt State Acquisition Full Channel 120 MHz Standard Half Channel 235 MHz 235 Mb s or TLA700 Module Merging Five 102 channel or 136 channel modules can be merged to make up to a 680 channel module Merged modules exhibit the same depth as the lesser of the five individual modules Word setup and hold glitch transition recognizers span all five modules Range recognizers limited to three module merge Only one set of clock connections is required Time Stamp 51 Bits at 125 ps resolution 3 25 days duration Clocking Acquisition Modes Internal internal 2X internal 4X external external 2X external 4X source synchronous 8 GHz MagniVu high speed timing is available simultaneous with all modes Number of Mainframe Slots Required per TLA700 Module 2 Quarter Channel 235 MHz 470 Mb s 120 MHz 240 Mb s DDR 235 MHz Optional 450 MHz 450 Mb s or 450 MHz 900 Mb s 235 MHz 470 Mb s DDR 450 MHz Optional 800 MHz 800 Mb s or 625 MHz 1 25 Gb s 450 MHz 900 Mb s DDR Tektronix Logic Analyz
54. cognizers 16 Number of Range Recognizers 4 Number of Counter Timers 2 Trigger Event Types Word group channel transition range anything counter value timer value signal glitch setup and hold violation snapshot Trigger Action Types Trigger module trigger all modules trigger main trigger MagniVu store don t store start store stop store increment counter decrement counter reset counter start timer stop timer reset timer snapshot current sample goto state set clear signal do nothing Maximum Triggerable Data Rate 1250 Mb s Trigger Sequence Rate DC to 500 MHz 2 ns Counter Timer Range 51 Bits each gt 50 days at 2 ns Counter Rate DC to 500 MHz 2 ns Timer Clock Rate 500 MHz 2 ns Counter Timer Latency 2 ns Range Recognizers Double bounded can be as wide as any group must be grouped according to specified order of significance Setup and hold Violation Recognizer Setup Time Range From 8 ns before to 7 ns after clock edge in 125 ps increments This range may be shifted towards the positive region by 0 ns 4 ns or 8 ns Setup and hold Violation Recognizer Hold Time Range From 7 ns before to 8 ns after clock edge in 125 ps increments This range may be shifted towards the positive region by 0 ns 8 8 ns 4 ns 12 4 ns or 8 ns 16 0 ns Trigger Position Any data sample MagniVu Trigger Position MagniVu posit
55. ctor surface mount optional 020 2228 00 21 each AMP mictor connector surface mount optional 34 channel Low profile Adapter for P6434 Order P6434 Option 01 Part Number 010 0612 00 Low profile leadset for P6434 optional P6434 Probe Cable Length 1 5 m 5 ft Description www tektronix com la 37 Tektronix Logic Analyzers gt Detailed Product Information 196 3431 00 4 each 196 3432 00 2 each 012 1377 00 12 each 012 1378 00 020 2199 00 4 each 100 Q series resistor molded into barrel connector housing signal only 196 3441 00 4 EA 012 1427 00 4 EA j 012 1426 00 P A 4 EA p 10 x 1 6 EA 8x 1 6 EA a l 4x1 12 EA By gt Y Y 2x1 12 EAKL 020 3000 00 38 www tektronix com la gt Differential to single ended converter pods Differential to single ended Converters Each podlet converts 8 input differential pairs to a sin gle ended output for use with the TLA logic analyzer They draw their power from separate wires connected to the system under test The units are shipped with out any input termination connected and a supply of 100 Q termination resistors for use and installation by the user if desired The units are shipped without input leadsets Leadsets are also available Differential ECL PECL to Single ended ECL Converter Pod Each channel is converted via an ON Semiconductor MC10E416 buffer which will support speeds as
56. displays can be used simultaneously each with independent resolutions Front panel Knobs Special function knobs for instrument control Front panel QWERTY Keypad Mini QWERTY keypad 30 www tektronix com la 16 30 in 414 02 mm 16 60 in 421 64 mm TLAGOO External Peripheral Interfaces External Display Port Type Female DB15 SVGA connector External Display Resolution Up to 1280x1024 noninterlaced at 16 M colors LAN Port Type 10 100Base 1 RJ 45 External Keyboard Port Type PS2 mini DIN External Mouse Port Type PS2 mini DIN Parallel Interface Port Type Female DB25 Parallel Interface Modes Centronics mode EPP Extended Parallel Port ECP Microsoft high speed mode Serial Interface Port Type Male DB9 Audio Out Port Type Stereo minijack Mic In Port Type Minijack PC Card CardBus Slot Types Two slots two PC card type I II or one PC card type Ill USB Port One 1 Symbolic Support Number of Symbols Ranges Unlimited limited only by amount of virtual memory available on TLA Object File Formats Supported gt IEEE695 gt OMF 51 OMF 86 OMF 166 OMF 286 OMF 386 gt COFF gt Elf Dwarf 1 and 2 gt Elf Stabs gt TSF if your software development tools do not generate outp
57. e to 32 Mb Depth at 120 MHz State Opt 5S Increase to 128 Kb Depth at 235 MHZ State Opt 6S Increase to 512 Kb Depth at 235 MHz State Opt 7S Increase to 2 Mb Depth at 235 MHz State Opt 8S Increase to 8 Mb Depth at 235 MHz State Opt 9S Increase to 32 Mb Depth at 235 MHz State Opt AS Increase to 128 Kb Depth at 450 MHZ State Opt BS Increase to 512 Kb Depth at 450 MHZ State Opt CS Increase to 2 Mb Depth at 450 MHz State Opt DS Increase to 8 Mb Depth at 450 MHz State Opt ES Increase to 32 Mb Depth at 450 MHz State Logic Analyzer TLA7ABx Module Options Base configuration is 64 M depth at 120 MHz state Opt 1S Increase to 64 Mb Depth at 235 MHz State Opt 2S Increase to 64 Mb Depth at 450 MHz State TLAZOO Series Module Upgrades You can increase the memory depth and state speed of most existing TLA700 Series logic analyzer mod ules You can also install a TLA7Axx logic analyzer module into an existing TLA714 715 720 721 7XM mainframe Please refer to the TLA Family Upgrade Guide for further details www tektronix com la 33 Tektronix Logic Analyzers gt Detailed Product Information gt P6810 Logic Analyzer Probe Selection Guidelines For the TLA7Axx logic analyzer modules you have the choice of three probe options Logic Analyzer Module Probes and Accessories P6810 TLA7Axx Option 2P The P6810 is a 34 channel general purpose probe with differe
58. e wide slot in both the TLA715 TLA721 mainframes and the TLA7XM expansion mainframe 2 Using a TLA7XM expansion mainframe with an existing TLA714 TLA720 mainframe requires Version 4 0 or higher TLA application software TLA720 benchtop mainframes S N B019999 and lower require TLA7UP Option 09 TLA720 Benchtop Mainframe Upgrade Please refer to the TLA Upgrade Guide for further details 3 All logic analyzer LA pattern generator PG and digitizing oscilloscope DSO modules are dual wide or occupy two single wide slots Tektronix Logic Analyzers gt Detailed Product Information TLAZOO Integral Controls TLA715 only Front Panel Display size 10 4 in diagonal Type Active matrix color TFT LCD with backlight Resolution 800x600 Colors 16 8 M true color Simultaneous Display Capability Both the front panel and one external display can be used simultaneously at 800x600 resolution Front panel Knobs Special function knobs for instrument control Front panel QWERTY Keypad Mini QWERTY keypad and Hex keypad Front panel Pointing Device Trackball TLAZOO External Peripheral Interfaces TLA715 and TLA721 External Display Port Type 2 Female DB15 connectors External Display Resolution Up to 1600x1200 noninterlaced at 256 colors for both primary and secondary displays External Display Compatibility DDC2B dynamic display configuration 2 External Keyboard Port Type PS2 min
59. ers gt Detailed Product Information Input Characteristics with P6810 P6860 or P6880 probes Capacitive Loading 0 7 pF typical clock data 1 0 pF for P6810 in group configuration Threshold Selection Range From 2 0 V to 4 5 V in 10 mV increments Threshold presets include TTL 1 5 V CMOS 1 65 V ECL 1 3 V Differential 0 V and user defined Threshold Selection Channel Granularity Separate selection for each of the clock qualifier channels and one per group of 16 data channels for each 34 channel probe Threshold Accuracy including probe 25 mV 1 Input Voltage Range Operating 2 5 V to 5 0 V Nondestructive 15 V Minimum Input Signal Swing 300 mV or 25 of signal swing whichever is greater single ended Vmax Vmin gt 150 mV differential Input Signal Minimum Slew Rate 200 mV ns typical State Acquisition Characteristics with P6810 P6860 or P6880 probes State Memory Depth with Timestamps quarter half full channels 512 256 1 28 Kb 2 M 1 M 512 Kb 8 4 2 Mb 32 16 8 Mb 128 64 32 Mb 256 128 64 Mb per channel Setup and Hold Time Selection Range From 8 ns before to 8 ns after clock edge Range may be shifted towards the setup region by O ns 8 8 ns 4 ns 12 4 ns or 8 ns 16 0 ns Setup and hold Window All Channels 625 ps typical single Channel 500 ps typical Minimum Clock Pulse Width 400 ps Active Cloc
60. etup and hold Window 2 0 ns typical Minimum Clock Pulse Width 2 ns Active Clock Edge Separation 5 ns Demux Channel Selection Channels can be demultiplexed to other channels through user interface with 8 channel granularity Timing Acquisition Characteristics with P6417 P6418 or P6434 probes MagniVu Timing 500 ps MagniVu Timing Memory Depth 2 Kb 2048 per channel Deep Timing Resolution half full channels 2 4 ns to 50 ms Deep Timing Resolution with Glitch Storage Enabled 10 ns to 50 ms Deep Timing Memory Depth half full channels with timestamps and with or without transitional storage 128 64 Kb 512 256 Kb 2 1 Mb 8 4 Mb 32 16 Mb 128 64 Mb per channel Deep Timing Memory Depth with Glitch Storage Enabled Half of default main memory depth Channel to channel Skew lt 1 ns typical Minimum Recognizable Pulse Width single channel 2 ns Minimum Recognizable Glitch Width single channel 2 ns Minimum Recognizable Multi channel Trigger Event Sample period 2 ns Trigger Characteristics Independent Trigger States 16 Maximum Independent If then Clauses per State 16 Maximum Number of Events per If then Clause 8 Maximum Number of Actions per If then Clause 8 Maximum Number of Trigger Events 18 2 counter timers plus any 16 other resources Number of Word Recognizers 16 Number of Range Recognizers 4 Number
61. for every block Note that a repeat value of 10 000 takes one sequence line in memory not 10 000 Step While in Step mode the TLA7PG2 the user can manually satisfy i e click an icon Wait For and Jump conditional events This allows the user to debug the logic flow of the program s sequencing Initialization Block The unconditional Jump command allows the user to implement an equivalent function Logic Analyzer Pattern Generator Connectivity to Simulation Environments The TLAGOO and TLA700 Series logic analyzers capture waveform data in a form that can be read by SynaptiCAD WaveFormer Pro VeriLogger Pro and TestBencher Pro software tools SynaptiCAD s tools can convert the logic analyzer waveform data into stimulus vectors for VHDL Verilog SPICE ABEL and pattern generators including the TLA7PG2 imulation y Results Captured Waveforms A Testbenches WaveFormer Pro LASTA TJ f y VHDL Verilog SPICE Test Stimulus DG Link DG2020A foal cg oe gt Easily Create TLA7PG2 Stimulus Files The TLA7PG2 Pattern Generator stimulus can be created from a mixture of VHDL and Verilog test benches simulation waveforms real world data acquired by a logic analyzer and wave forms created within SynaptiCAD s timing diagram editing environment synaptiCAD s WaveFormer Pro product offers a timing diagram editing environment that enables stimulus to be created using a combination of g
62. h and or up to 450 MHz state TLA7AB2 68 channel logic analyzer module 8 GHz timing 120 MHz state 64 M depth must select one probe option below Option for up to 450 MHz state TLA7AB4 136 channel logic analyzer module 8 GHz timing 120 MHz state 64 M depth must select one probe option below Option for up to 450 Mrz state Tektronix Logic Analyzers gt Detailed Product Information gt Quantity of Probes Per Option Option TLA7ZAA1 TLA7AA2 TLA7AAS TLA7AA4 TLA7AB2 TLA7AB4 2P Add P6810 Probes 1 2 5 4 2 4 3P Add P6860 Probes 2 3 4 2 4 4P Add P6880 Probes 2 4 2 4 Logic Analyzer TLAZAxx Module Probe Options Opt 2P Add full complement of P6810 general purpose probe 34 ch differential clock differential data probes each includes four single ended and four differential 8 channel leadsets two 1 channel leadsets single ended and differential 40 SMT KlipChip grabber tips Opt 3P Add full complement of P6860 high density compression probe 34 ch differential clock single ended data probes Opt 4P Add full complement of P6880 high density compression probe 34 ch differential clock differential data probe s Logic Analyzer TLA7AAx Module Options Base configuration is 128 K depth at 120 MHz state Opt 1S Increase to 512 Kb Depth at 120 MHz State Opt 2S Increase to 2 Mb Depth at 120 MHz State Opt 3S Increase to 8 Mb Depth at 120 MHz State Opt 4S Increas
63. i DIN External Mouse Port Type PS2 mini DIN Parallel Interface Port Type IEEE 1284 C connector comes standard with adapter to female DB25 connector Parallel Interface Modes Centronics mode EPP Extended Parallel Port ECP Microsoft high speed mode Serial Interface Port Type Male DB9 PC Card CardBus Slot Types Two slots two PC Card Type I II or one PC Card Type III USB Port Two 2 gt Example of TLA721 with ten TLA7XM Mainframes www tektronix com la 15 Tektronix Logic Analyzers gt Detailed Product Information Integrated View iView Capability TLA Mainframe Configuration Requirements TLA714 720 715 721 Series mainframes TLA App S W V 4 1 or greater 256 MB DRAM Minimum 512 MB recommended TDS Configuration Requirements TDS3GM GPIB RS232 Interface Module required for iView capability on any TDS3000 series TDS3GV GPIB RS232 VGA Interface Module required for iView capability on any TDS3000B series If using iView with TDS6604 order a TCA BNC connector to be compatible with a BNC cable run from a TLA7Axx module analog output Number of TDS Oscilloscopes that Can be Connected to a TLA System 1 External Oscilloscopes Supported TDS3012 TDS3014 TDS3032 TDS3034 TDS3052 TDS3054 TDS3012B TDS3014B TDS3032B TDS3034B TDS3052B TDS3054B TDS5052 TDS5054 TDS5104 TDS6604 TDS7054 TDS7104 TDS7154 TDS7404 TDS684C TDS694C CSA7154 CSA740
64. ion can be set from 0 to 60 centered around the MagniVu trigger Storage Control data qualification Global conditional by state start stop block by trigger action or transitional Also force main prefill selection available Physical Characteristics Dimensions mm in Height 262 10 3 Width 61 2 4 Depth 381 15 Weight kg Ib Net 3 1 6 7 Shipping 6 3 13 7 P6810 Probe Cable Length 1 8 m 6 ft P6860 Probe Cable Length 1 8 m 6 ft P6880 Probe Cable Length 1 8 m 6 ft All three probes have the same electrical length and are delay matched gt TLAZNx Px Qx Logic Analyzer Modules General Number of Channels all channels are acquired including clocks TLA7N1 34 channels 2 are clock channels TLAZN2 TLA7P2 68 channels 4 are clock channels TLA7N3 102 channels 4 are clock and 2 are qualifier channels TLA7N4 TLA7P4 136 channels 4 are clock and 4 are qualifier channels Channel Grouping No limit to number of groups or number of channels per group all channels can be reused in multiple groups TLA700 Module Merging Three 102 channel or 136 channel modules can be merged to make up to a 408 channel module Merged modules exhibit the same depth as the lesser of the three individual mod ules Word range setup and hold glitch transition rec ognizers span all three modules Only one set of clock connections is required Time Stamp 50 Bit at 500 ps res
65. ity of Probes per Option Option TLA601 611 621 TLAG6GO02 612 622 TLA6O3 613 623 TLA6GO4 614 624 1P Add P6418 Probes 2 2P Add P6434 Probes 1 3P Add P6417 Probes 2 6 8 3 4 6 8 Please refer to the Logic Analyzer Probe Selection Guidelines for further details on the probe which is best for your application TLAG1x Logic Analyzer with Internal Display Includes Wheel mouse keyboard front panel cover accessory pouch probe retainer bracket probe manual power cord North American 120 VAC 60 Hz software user manual certificate of calibration and one year warranty return to Tektronix Probes must be ordered separately Order Opt 1P P6418 or Opt 2P P6434 or Opt 3P P6417 You can also choose to order any combination and quantity of probes by ordering the P6418 P6434 or P6417 individually TLA611 34 channel logic analyzer 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mrz state TLA612 68 channel logic analyzer 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mrz state TLA613 102 channel logic analyzer 2 GHz timing 100 MHz state 64 K depth must select one probe option below Options for up to 256 K depth and or 200 Mrz state TLA614 136 channel logic analyzer 2 GHz timing 100 MHz state 64 K depth must select one probe option
66. k Edge Separation 400 ps Demux Channel Selection Channels can be demultiplexed to other channels through user interface with 8 channel granularity Source Synchronous Clocking Up to four Fast Latches per module 20 max per 5 way merge to strobe source synchronous buses into TLA7Axx modules Four sets of any predefined Fast Latches may be combined with qualification data and data pipelining to store four independent source synchronous data buses Two Fast Latches may be combined to address DDR applications www tektronix com la 19 Tektronix Logic Analyzers gt Detailed Product Information Differential input 150 mV swing each side V max N V OV Difference V min Differential equivalent signal input 300 mV swing as viewed by the logic analyzer and the analog probe output V 150 mV TH OV OV Difference Note For differential inputs the module threshold should be set to OV assuming no common mode error Note See online help for further analog output details gt Differential inputs Timing Acquisition Characteristics with P6810 P6860 and P6880O probes MagniVu Timing 125 ps max adjustments to 250 ps 500 ps 1 ns and 2 ns MagniVu Timing Memory Depth 16 Kb per channel with adjustable trigger position Deep Timing Resolution quarter half full channels 500 ps 1 ns 2 ns to 50 ms Deep Timing Resolution with Glitch Storage E
67. lt main memory depth Channel to channel Skew lt 1 ns typical Minimum Recognizable Pulse Glitch Width single channel 2 ns Minimum Recognizable Multi channel Trigger Event Sample period 2 ns Trigger Characteristics Independent Trigger States 16 Maximum Independent If then Clauses per State 16 Maximum Number of Events per If then Clause 8 Maximum Number of Actions per If then Clause 8 Maximum Number of Trigger Events 18 2 counter timers plus any 16 other resources Number of Word Recognizers 16 Number of Range Recognizers 4 Number of Transition Recognizers 1 Number of Counter Timers 2 Trigger Event Types Word group channel transition range anything counter value timer value signal glitch setup and hold violation Trigger Action Types Trigger module trigger all Store don t store start store stop store increment counter reset counter start timer stop timer reset timer goto state set clear signal do nothing Trigger Sequence Rate DC to 250 MHz 4 ns Counter Timer Range 51 Bits each gt 100 days at 4 ns Counter Rate DC to 250 MHz 4 ns Timer Clock Rate 250 MHz 4 ns Counter Timer Latency None can be tested or reset immediately after starting Range Recognizers Double bounded can be as wide as any group must be grouped according to specified order of significance Tektronix Logic An
68. luding network integration Opt R3 Extends depot repair warranty service period to three years Opt R5 Extends depot repair warranty service period to five years Opt S1 Uplifts standard one year warranty service of mainframe and installed modules to on site service Opt S3 Uplifts Opt C3 and or R3 of mainframe and installed modules to on site service must be ordered with Opt C3 and or R3 Opt C3 Three years of calibration service includes initial calibration and two annual calibrations Opt C5 Five years of calibration service includes inital calibration and four annual calibrations Opt D1 Add calibration test data report Opt D3 Provides test data for each calibration must be ordered with Opt C3 Opt D5 Provides test data for each calibration must be ordered with Opt C5 www tektronix com la 43 Tektronix Logic Analyzers gt Detailed Product Information 44 www tektronix com la Contact Tektronix ASEAN Australasia Pakistan 65 6356 3900 Austria 43 2236 8092 262 Belgium 32 2 715 89 70 Brazil amp South America 55 11 3741 8360 Canada 1 800 661 5625 Central Europe amp Greece 43 2236 8092 301 Denmark 45 44 850 700 Finland 358 9 4783 400 France amp North Africa 33 0 1 69 86 80 34 Germany 49 221 94 77 400 Hong Kong 852 2585 6688 India 91 80 2275577 Italy 39 02 25086 1 Japan 81 3 3448 3111 Mexico Central Ame
69. m la 7 Tektronix Logic Analyzers gt Detailed Product Information Measurement Modules and Key Interface Features cont Easy Trigger PowerTrigger Triggering Processor and Bus Support Direct Links to EDA Tools Graphical and textual trigger descriptions to easily define a trace event Trigger interface quickly sets up the powerful trigger state machine to save time in debug efforts Over 100 pre defined categorized trigger programs to choose from Programmable trigger interface for creating specialized triggers to aid in tracking down elusive problems State based trigger machine with 16 states available to aid in finding complex problems in digital designs Decrement counters 16 transition recognizers Snapshot trigger that loads a current state on the fly for use later in a trigger program Separate MagniVu trigger action to view high speed timing information where it is needed most Acquire real time trace of processor or bus cycles without interfering with bus operation High level source code analysis correlates high level language with real time trace Symbolic debug with unlimited number of symbols Object file formats supported include IEEE695 OMF51 86 166 286 386 COFF Elf Dwarf 1 amp 2 Elf Stabs and TSF Tektronix Symbol Format Monitor and correlate multiple processors or buses simultaneously with the TLA700 series logic analyzer Use captured
70. measurements quickly Quickly zoom in on areas of interest resize waveforms overlay analog and digital waveforms make analog measurements label waveforms and color code symbols to customize the display for easy analysis of complex digital systems Quickly and easily run a TLA over a network from a workstation or over the Internet Transfer data over the network for offline analysis using TLAVu Utilize the built in security of Windows 2000 Professional to protect the data integrity of your files Tektronix Logic Analyzers gt Detailed Product Information Breakthrough Solutions for Real time Digital Systems Analysis As a digital design engineer you re dealing with faster edge speeds and tighter timing margins that create more signal integrity issues than ever before The Tektronix TLA Family of logic analyzers delivers a wide range of powerful solutions The TLA s iView capability enables you to observe how the digital and analog worlds interact Connecting an external oscilloscope to your TLA delivers an integrated measurement solution that can capture and display both domains in a single time correlated view For every task you face the TLA s innovative MagniVu technology provides 125 ps timing resolution on all channels all the time through the same probe Our industry leading logic analyz ers provide up to 800 MHz state acquisition with 1 25 Gb s data rate for advanced processors and buses
71. nabled 4 ns to 50 ms Deep Timing Memory Depth quarter half full channels with timestamps and with or without transitional storage 512 256 128 Kb 2 Mb 1 Mb 512 Kb 8 4 2 Mb 32 16 8 Mb 128 64 32 Mb 256 128 64 Mb per channel Deep Timing Memory Depth with Glitch Storage Enabled Half of default main memory depth Channel to channel Skew 250 ps typical Minimum Recognizable Pulse Glitch Width single channel 500 ps P6810 P6860 P6880 1 ns Minimum Detectable Setup Hold Violation 200 ps Minimum Recognizable Multi channel Trigger Event Sample period 400 ps 20 www tektronix com la OV 150 mV Analog Acquisition Characteristics with P6810 P6860 and P6880 probes Bandwidth 2 GHz typical Attenuation 10x 1 DC Offset 1 mV Channels Demultiplexed 4 Run Stop Requirements None analog outputs are always active iView Analog Outputs Compatible with any internal TLA7Dx Ex DSO module or supported TDS external oscilloscope iView Analog Output BNC Cable Low loss 10x 36 in Trigger Characteristics Independent Trigger States 16 Maximum Independent If then Clauses per State 16 Maximum Number of Events per If then Clause 8 Maximum Number of Actions per If then Clause 8 Maximum Number of Trigger Events 18 2 counter timers plus any 16 other resources Number of Word Recognizers 16 Number of Transition Re
72. nd 220 VAC 50 Hz Opt A99 No power cord 32 www tektronix com la TLA715 TLA721 TLAZ7XM Factory Configuration Opt 88 Install modules in mainframe at factory excludes merging of logic analyzer modules TLA704 714 715 TLAZ711 720 721 TLAZ7XM Optional Accessories Logic Analyzer Cart LACART K4000 TLA711 Rackmount Kit Order 020 2197 00 TLA720 TLA721 TLA7XM Rackmount Kit Order 020 2369 00 TLA704 714 715 Wheeled Transport Case Order 016 1522 00 TLA711 720 721 TLA7XM Wheeled Transport Case Order 016 1651 00 18 in 1280x1024 Flat panel Display with U S Standard 120 V 60 Hz Power Plug Order 119 6568 00 21 in 1600x1200 Flat panel Display with U S Standard 120 V 60 Hz Power Plug Order 119 6569 00 Power Cord IEC320 C5 Universal Euro Straight Order 161 0311 00 Power Cord IEC320 C5 UK Straight Order 161 0312 00 Power Cord IEC320 C5 Australian Straight Order 161 0313 00 Power Cord IEC320 C5 Switzerland Straight Order 161 0314 00 Wheeled Transport Case for 18 in 1280x1024 Flat panel Display Order 016 1895 00 Wheeled Transport Case for 21 in 1600x1200 Flat panel Display Order 016 1896 00 83 Key Notebook Keyboard PS2 Compatible Order 118 9402 00 TLA7QS TLA Family training package TLA700 configuration required 102 channel logic analyzer module required plus 2 channel digitizing oscillo scope module optional plus 64 cha
73. nectors support 0 100 spacing 196 3477 00 1 each 8 channel reduced bias voltage leadset barrel connectors support 0 100 spacing 196 3478 00 1 each 1 channel reduced bias voltage leadset barrel connectors support 0 100 spacing SMG50 20 each SMT KlipChip grabber tips 013 0280 00 One to two adapter optional SMK4 Micro KlipChip grabber tip adapter 4 each optional 071 0567 00 P6417 P6418 Instruction Manual P6418 Probe Cable Length 1 9 m 6 25 ft 36 www tektronix com la P6417 TLA7Nx Px Qx Opt 3P The P6417 is a 17 channel general purpose probe that is similar to the P6418 with the additional capability of allowing you to separate the 8 channel podlet groups into individual channels for both maximum electrical performance and maximum distance between adjacent channels This probe is recommended for those general purpose applications that require maximum flexibility 17 channel General purpose Probe and Accessories for TLA7Lx 7Mx TLA7Nx 7Px 7Qx Logic Analyzer Modules Order P6417 010 6417 00 334 9239 00 A P6417 Equivalent Circuit yw i user 20K ohm LA Module 2 0pf D 407 4435 01 334 9239 00 L 196 3431 01 0 100 pins standard 196 3476 00 0 100 amp 2mm pins optional 196 3477 00 Reduced bias voltage leadset 0 100 amp 2mm pins optional 196 3432 00 0 100 pins standard 196 3479 00 0 100 amp 2mm pins optional 196 3478 00 Reduced
74. ngle ended Clock Differential Data Single ended Data Differential Data and Data Differential and Data Differential and Data signal adapters signal adapters available available Simultaneous State 800 MHz 800 MHz 800 MHz 200 MHz 200 MHz 200 MHz Timing to 8 GHz 8 GHz 8 GHz 2 GHz 2 GHz 2 GHz Simultaneous State 800 MHz 800 MHz 800 MHz N A N A N A Timing Analog to 8 GHz 2 GHz 8 GHz 2 GHz 8 GHz 2 GHz Minimum Signal Amplitude Minimum Single ended 300 mV 300 mV 300 mV 500 mV 500 mV 500 mV Minimum Differential Vmax Vmin2 t150mV Vi Vni 150mV Vmax Vmin 2150 mV N A N A N A Probe Load AC DC 1 2 pF 20 KQ 0 7 pF 20 KQ 0 7 pF 20 KQ 2 pF 20 KQ 2 pF 20 KQ 2 pF 20 KQ to Ground to Ground to Ground to 2 2 V to 2 2 V to 2 2 V Low voltage adapters Low voltage adapters that work with that work with low voltage signals low voltage signals are available are available Notes Works with a No connector required No connector required Works with a Works with a Requires AMP wide range of only land pads only land pads wide range of wide range of Mictor connector industry standard accessories for required to be laid out on target system required to be laid out on target system industry standard accessories for flexible attachment PCB for 17 and or PCB for 17 and or flexible attachment to your target system 34 channels 34 channels to your target system Please refer to Please refer to P6860 6880 probe P6860 6880 p
75. nnel pattern generator module optional Opt A1 Universal Euro Opt A2 United Kingdom Opt A6 Japan TLA7QS Technical Reference Support Kit Order 020 2211 02 TLAZOO Series Manuals TLA Family User Manual Order 071 0863 02 for Version 4 2 TLA application software TLA7QS Quickstart Training Manual Order 070 9717 05 TLAZOO Series Service Manuals and Test Fixtures TLA715 Service Manual includes performance verification and adjustment procedures Order 071 0913 01 TLA721 7XM Service Manual includes perform ance verification and adjustment procedures Order 071 0912 01 TLA Logic Analyzer Performance Verification and Adjustment Fixture for TLA6xx and TLA7LxX Mx Nx Px Qx includes AC adapter requires local power cord Order 671 3599 00 TLA Logic Analyzer Performance Verification and Adjustment Fixture for TLA7Axx refer to TLA7Axx Logic Analyzer Module Service Manual for the list of required equipment including P6860 and P6880 probes Order TLACAL2 TLA7Nx 7Px 7Qx Logic Analyzer Modules Service Manual includes performance verification and adjustment procedures Order 071 0864 01 TLA7Axx Logic Analyzer Modules Service Manual includes performance verification and adjust ment procedures Order 071 1043 00 TLA7PG2 Pattern Generator Module Service Manual includes performance verification and adjustment procedures Order 071 0714 01 TLA7Dx 7Ex DSO
76. ns typical P6471 ECL Probe Output Type 100E151 for data output 100EL16 for strobe output 100EL04 for clock output All outputs are unterminated Data Output Skew lt 170 ps typical between all data output pins of all modules in the mainframe after inter module skew is adjusted manually lt 140 ps typical between all data outout pins of single probe www tektronix com la 25 Tektronix Logic Analyzers gt Detailed Product Information Data Output to Strobe Output Delay 2 94 ns P6472 PECL LVPECL Probe P6473 LVDS Probe typical when strobe delay set to Zero Number of Data Outputs 8 in full channel Number of External Event Inputs 1 Data Output to Clock Output Delay 780 ps mode or half channel mode Number of External Inhibit Inputs 1 typical Number of Clock Outputs 1 only one of Output Type External Clock Input to Clock Output Delay clock output and strobe output can be enabled LVDS TIAVEIA 644 compatible for data output 51 ns typical Number of Strobe Outputs 1 only one of LVDS TIA EIA 644 compatible for clock strobe output Number of External Event Inputs 2 clock output and strobe output can be enabled Rise Fall Time 20 to 80 External Event Input Number of External Event Inputs 2 Rise 910 ps typical Input Level ECL Number of External Inhibit Inputs 0 Fall 750 ps typical Input Type 10H116 Clock Output Polarity Positive Minimum Pulse Width 50 ns St
77. ntial clock differential data for use when 1 probing indi vidual test points within your target system either directly or with a test clip or 2 direct connection to legacy TLA family processor bus support probe adapters with 8 channel probe connectors The P6810 works with a wide range of industry standard probing accessories for flexible attachment to your target system This probe is recommended for most general purpose applications Fits both 0 100 in and 2 mm square pin configurations 34 channel General purpose Probe with Differential Clock Differential Data and Accessories for TLA7Axx Logic Analyzer Modules Order P6810 Part Number Description 010 6810 00 17 channel P6810 Probe 352 1097 00 Podlet Holders Bag of 4 335 0345 00 1 Sheet of Probe Labels 196 3471 01 2 each 1 ch leadset single ended and Differential 196 3470 00 4 each 8 ch leadset single ended 196 3472 00 4 each 8 ch leadset Differential SMG50 20 each SMT KlipChip grabber tips P6810 Probe Cable Length 1 8 m 6 ft 34 www tektronix com la gt P6860 P6860 TLA7Axx Option 3P The P6860 is a 34 channel high density compression probe with differential clock and single ended data This probe uses a connectorless probe attach mechanism for quick and reliable connections to your system under test This probe is recommended for those applica tions that require higher signal density or a connector less probe attach
78. olution 6 5 day range Clocking Acquisition Modes Internal internal 2X external 2 GHz MagniVu high speed timing is available simultaneous with all modes Number of Mainframe Slots Required per TLA700 Module 2 Input Characteristics with P6417 P6418 or P6434 probes Capacitive Loading 1 4 pF typical data 2 pF typical clock P6418 2 pF typical data and clock P6417 amp P6434 Threshold Selection Range From 5 0 V to 2 0 V in 50 mV increments Threshold Selection Channel Granularity separate selection for clock 1 and data 16 for each 17 channel probe connector Threshold Accuracy including probe 100 mV Input Voltage Range Operating 6 5 V centered around the programmed threshold Nondestructive 15 V Minimum Input Signal Swing 250 mV or 25 of signal swing whichever is greater P6417 amp P6418 300 mV or 25 of signal swing P6434 Input Signal Minimum Slew Rate 200 mV ns typical State Acquisition Characteristics with P6417 P6418 or P6434 probes State Clock Rate 100 MHz standard 200 MHz optional State Data Rate half full channels 400 200 Mb s typical Requires 200 MHz State option Tektronix Logic Analyzers gt Detailed Product Information State Memory Depth with Timestamps 64 Kb 256 Kb 1 Mb 4 Mb 16 Mb or 64 Mb per channel Setup and hold Time Selection Range From 8 5 ns before to 7 0 ns after clock edge S
79. on violations of both setup time and hold time between clock and data which are on separate input channels setup time settable from 100 ns to 100 ns in 200 ps increments hold time settable from 1 ns to 102 ns minimum settable window of setup time hold time is 2 ns Tektronix Logic Analyzers gt Detailed Product Information Glitch Trigger Triggers on or rejects glitches of positive negative or either polarity settable from 2 ns to 1 s Minimum glitch width 2 0 ns with 200 ps resolution 2 ns to 10 ns settings Runt Pulse Trigger Triggers on a pulse that crosses one threshold but fails to cross a second threshold before crossing the first again settable from 2 ns to 1s Slew Rate Trigger Triggers on pulse edge rates that are either faster or slower than a set rate edges can be rising falling or either settable from ZnS to 1s Logic Pattern Trigger Triggers when a logical combination AND OR of all the input channels Hi Lo Don t Care stays true or false for a specified period of time settable from 2 ns to 1 s Physical Characteristics Dimensions mm in Height 262 10 3 Width 61 2 4 Depth 381 15 Weight kg Ib Net 2d 9 8 Shipping 5 8 12 8 P6243 Probe Cable Length 1 3 m 51 in P6245 Probe Cable Length 1 3 m 51 in www tektronix com la 23 Tektronix Logic Analyzers gt Detailed Product Information gt TLAZ7PG2 Pattern Generator Module General
80. or block of 31 samples before and after Physical Characteristics Dimensions mm in Height 262 10 3 Width 61 2 4 Depth 381 15 Weight kg Ib Net w o probes 3 1 6 7 Shippin ical 6 3 13 7 P6417 Probe Cable Length 1 8 m 6 ft P6418 Probe Cable Length 1 9 m 6 25 ft P6434 Probe Cable Length 1 5 m 5 ft All three probes have the same electrical length 22 www tektronix com la gt TLA7Dx Ex Digital Storage Oscilloscope Modules General Number of Channels per Module TLA7D2 TLA7E2 4 channels TLA7D1 TLA7E1 2 channels Sample Rate TLAZE1 TLA7E2 5 GS s on all channels TLA7D1 TLA7D2 2 5 GS s on all channels Bandwidth at probe tips TLAZE1 TLA7E2 100 mV to 10 V range 1 GHz 90 mV to 99 8 mV range 900 MHz 20 mV to 49 8 mV range 600 MHz All others 900 Mrz TLA7D1 TLA7D2 500 MHz on all channels in all ranges Memory Depth 15 000 samples per channel in all modes Number of Mainframe Slots Required 2 Vertical System Input Sensitivity Range 10 mV to 100 V full scale Vertical Resolution 8 Bit 256 levels DC Gain Accuracy 1 5 of full scale range Analog Bandwidth Selections 20 MHz 250 MHz and Full Input Coupling AC DC or GND Input Impedance Selections 1 MQ in parallel with 10 pF or 50 Q AC Coupled Lower Frequency Limit lt 10 Hz when AC 1 MQ coupled lt 200 kHz when AC 50 Q coupled Maximum Input Voltage at
81. raphically drawn signals timing parameters that constrain edges clock signals and temporal and Boolean equations for describing complex quasi repetitive signal behavior Advanced operations on signals such as time scaling and shifting and block copy and pasting of signal behavior over an interval of time are also supported Physical Characteristics Dimensions mm in Height 262 10 3 Width 61 2 4 Depth 381 15 Weight kg Ib Net 9 6 0 Shipping 6 2 EE Common to P6470 TTL CMOS P6471 ECL P6473 LVDS P6474 LVCMOS Probes Number of Data Outputs 16 in full channel mode 8 in half channel mode Number of Clock Outputs 1 Only one of Clock Output and Strobe Output can be enabled Number of Strobe Outputs 1 Only one of Clock Output and Strobe Output can be enabled Clock Output Polarity Positive Strobe Type RZ only Strobe Delay Zero or Trailing Edge P6470 TTL CMOS Probe Output Type HD74LVC541A for Data Output HD74LVC244A for Clock Strobe Output Output Voltage nominal load 1 MQ Voy 2 0 V to 5 5 V tri stateable programmable in 25 mV increments Vor O V Data Output Skew lt 510 ps typical between all data output pins of all modules in the mainframe after inter module skew is adjusted manually lt 480 ps typical between all data output pins of single probe Data Output to Strobe Output Delay 1 7 ns typical when strobe delay set to Zero Data Output to
82. rica amp Caribbean 52 55 56666 333 The Netherlands 31 0 23 569 5555 Norway 47 22 07 07 00 People s Republic of China 86 10 6235 1230 Poland 48 0 22 521 53 40 Republic of Korea 82 2 528 5299 Russia CIS amp The Baltics 358 9 4783 400 South Africa 27 11 254 8360 Spain 34 91 372 6055 Sweden 46 8 477 6503 4 Taiwan 886 2 2722 9622 United Kingdom amp Eire 44 0 1344 392400 USA 1 800 426 2200 USA Export Sales 1 503 627 1916 For other areas contact Tektronix Inc at 1 503 627 7111 Updated 17 June 2002 Our most up to date product information is available at www tektronix com gq S0001 ACCREDITED BY THE DUTCH COUNCIL FoR CERTIACATION Copyright 2002 Tektronix Inc All rights reserved Tektronix products are covered by U S and foreign patents issued and pending Information in this publication super sedes that in all previously published material Specification and price change privileges reserved TEKTRONIX and TEK are registered trademarks of Tektronix Inc All other trade names referenced are the service marks trademarks or registered trademarks of their respective companies 07 02 OAWWW O2W 14255 2 Tektronix Enabling Innovation
83. robe design guide to your target system to be installed on target system PCB for every 34 channels Please refer to P6434 probe manual industry standard accessories for flexible attachment design guide 6 www tektronix com la System Overview System Capability Flexible Acquisition and Stimulus Tektronix Logic Analyzers gt Detailed Product Information Features and Benefits TLA600 Series offers similar measurement capability as modular series in fixed channel widths for mainstream digital designers Logic Analyzer Acquisition Modules Digital Oscilloscope Modules Pattern Generator Modules Integrated View iView Enhanced TLA700 Mainframe Hardware TLA700 Series modular approach allows you to select the optimum combination of stimulus and acquisition to fit your performance feature and budget requirements System software setup information data files common to both TLA600 and TLA700 instruments enabling easy data and file sharing between groups or instruments Real time correlated data views provide system level visibility from high level source code to high speed state amp timing to analog characteristics of digital signals Utilize industry leading TDS oscilloscopes to view time correlated analog and digital data in the same TLA display Pentium Ill processor with up to 60 GB hard disk 512 MB system RAM and CDRW provides a powerful platform for data analysis
84. robe Type RZ only Data Output Skew P6471 ECL Probe Rise Fall Time lt 365 ps between all data output pins of all Strobe Delay Zero or Trailing Edge 20 to 80 modules in the mainframe after inter module Timing values measured using 51 Q to 2 0 V Output Type skew is adjusted manually Clock Output 100EP90 for data output lt 350 ps between all data output pins of all Rise 390 ps typical 100EP90 for clock strobe output probes of a single module i i 0 320 ps between all data output pins Fall 330 ps typical Rise Fall Time 20 to 80 P a at put p e o Rise 330 ps typical 9 i Data Output Fall 870 ns hcl Data Output to Strobe Output Delay tal UPS TYPICAE SS 280 ps when strobe delay set to zero Rise 1200 ps typical Fall 710 vs tvoical Output Voltage Level PECL LVPECL Data Output to Clock Output Delay 1 2 ns Data Output Skew i Clock Input to Clock Output Delay Strobe Output lt 385 ps between all data output pins of all Rise 290 ps typical modules in the mainframe after inter module External Inhibit to Output Enable Delay Fall 570 pa qoical skew is adjusted manually 9 ns for data output lt 370 ps between all data output pins of all External Inhibit Input to Output Disable Delay probes of a single module 12 ns for data output lt 340 ps between all data output pins of a single probe Probe D Data Output to Output Enable Delay Hata Output to Strobe Outoui
85. robe with 220 V Euro power plug Includes 12 SMB to header coax cables Opt 8P Add one 8 channel P6475 Variable probe with 240 V UK power plug Includes 12 SMB to header coax cables Opt 9P Add one 8 channel P6475 Variable probe with 240 V Australian power plug Includes 12 SMB to header coax cables Opt AP Add one 8 channel P6475 Variable probe with 240 V N American power plug Includes 12 SMB to header coax cables Opt BP Add one 8 channel P6475 Variable probe with 220 V Swiss power plug Includes 12 SMB to header coax cables Opt CP Add one 8 channel P6475 Variable probe with no power plug Includes 12 SMB to header coax cables 40 www tektronix com la TLAZOO Series Pattern Generator Module s Upgrades You can increase the memory depth of most existing TLA700 Series pattern generator modules You can also install a TLA7PG2 pattern generator module into and existing TLA714 715 720 721 7XM mainframe Please refer to the TLA Family Upgrade Guide for further details TLAZPG2 Pattern Generator Probes 16 channel TTL CMOS Probe and Accessories for TLA7PG2 Pattern Generator Module Order P6470 Part Number Description 012 1581 00 2 each 8 channel leadsets 012 1580 00 1 each 5 channel leadset 012 15 70 00 Probe cable optional std with TLA7PG2 module 071 1017 01 Pattern Generator Probe User Manual Data Output 74LVC541A Clock Strobe Output TA
86. ronix representative External Instrumentation Interfaces System Trigger Output Asserted whenever a system trigger occurs TTL compatible output back terminated into 50 Q System Trigger Input Forces a system trigger triggers all modules when asserted TTL compatible edge sensitive falling edge latched gt TLA721 and TLA7XM Benchtop and Expansion Mainframes with TLA721 TLA7XM Rackmount Kit External Signal Output Can be used to drive external circuitry from a module s trigger mechanism TTL compatible output back terminated into 50 Q External Signal Input Can be used to provide an external signal to arm or trigger any or all modules ITL compatible level sensitive P6041 External Signal Cable Length SMB to BNC adapter cable two each TLA721 only 1 1 m 42 in www tektronix com la 17 Tektronix Logic Analyzers gt Detailed Product Information T 28 75 in 731 mm 24 00 in 610 mm i 22 00in p 559 mm a E 24 00 in 609 60 mm 3 75 in 95 25 mm 56 00 in 1423 mm 3 00 in 76 20 mm m 20 00 in 15 75 in 30 50 in 508 00 mm 400 05 mm 774 70 mm 4 75in 30 50 in x 121mm Y 25 00 in 775mm 635 mm 24 00 in 609 60 mm i 4 75 in Br
87. s 250 MHz 4 ns half full channels 128 64 Kb to 128 64 Mb half full channels with timestamp No No No No TLA7Dx Ex Modules Internal 2 amp 4 8 TLA715 20 TLA721 52 with TLA715 and two TLA7XMs 240 with TLA721 and ten TLA7XMs 500 MHz amp 1 GHz 2 5 GS s amp 5 GS s 8 Bits 15 Kb TLA7PG2 64 128 with TLA715 320 with TLA721 128 with TLA715 320 with TLA721 832 with TLA715 and two TLA7XMs 3 840 with TLA721 and ten TLA7XMs 268 134 MHz 512 256 Kb to 2 1 Mb gt Detailed Product Information TLAZAXx 2 GHz 500 ps 1 GHz 1 ns 500 MHz 2 ns quarter half full channels 512 256 128 Kb to 256 128 64 Mb quarter half full channels with timestamp Yes Yes TDS Oscilloscopes 1 External 2 amp 4 4 100 MHz to 6 GHz 1 25 GS s to 20 GS s 8 Bits and 9 Bits 10 Kb to 32 Mb CMOS TTL ECL LVCMOS PECL LVPECL LVDS Variable 1 For a complete list of currently supported TDS oscilloscopes please visit our website http www tektronix com iview www tektronix com la 5 Tektronix Logic Analyzers gt Detailed Product Information Tektronix Logic Analyzer Probe Selection Guide Logic Analyzer Used TLA7AAx Logic Analyzer Modules TLA6xx Logic Analyzers TLA7ABx Logic Analyzer Modules TLA7Lx 7Mx Logic Analyzer Modules TLA7Nx 7Px 7Qx Logic Analyzer Modules Recommended Use Recommended for Recommended Recommended for Recommended Recommended Recommended for most general purpose
88. scopes iView capability couples selected Tektronix TDS family oscilloscopes with TLA Series logic analyzers producing a solution that shows on the same logic analyzer display time correlated views of both digi tal and analog waveforms set up is easy through the use of an external oscil loscope wizard in the TLA Series logic analyzer user interface that guides the user through set up and connection No user calibration or calibration fixture is required And once set up is completed the iView capability is completely automated Tektronix Logic Analyzers gt Detailed Product Information Find and Analyze your Difficult Real time Software Problems aee Ee SCOP ICEF StopLite 3c StopLite 46 initQueue 1n1tQueue 6 1nitQueue c StopLite 4c gt Real time instruction trace C2 1 872us Delta Time QSTART Address C1 initQ gt 4 C2 initQ gt 8 ee aaa oe QSTART Sample QSTART Address QSTART Data MOVE L 00001001 stopLignts 1l0 MOVE L 00000401 stopLights 14 Rin aaa i MOVEQ 00000000 D7 48ns QSTART Control PREFETC PREFETCH QSTART RWY DSO 1 Channel gt Real time correlation to hardware Source Code Debugging Tektronix logic analyzers provide real time debug visibility by nonintrusively capturing instruction exe cution and system signals This maximizes source code debugging productivity by linking the source code to instruction trace history correlated to sys tem
89. target system This probe is recommended for most general purpose applications 17 channel General purpose Probe and Accessories for TLA7Lx 7Mx TLA7Nx 7Px 7Qx Logic Analyzer Modules Order P6418 P6418 Equivalent Circuit _ 334 9979 00 gt _ Ww gt 2 2V user 20K ohm LA Module 1 4pf data _ 2 0pf clock 010 6418 00 013 0280 00 optional res ee E 407 4435 01 st ae RY L a L 196 3431 01 0 100 pins standard 196 3476 00 0 100 amp 2mm pins optional 196 3477 00 Reduced bias voltage leadset 0 100 amp 2mm pins optional 196 3432 00 0 100 pins standard 196 3479 00 0 100 amp 2mm pins optional 196 3478 00 Reduced bias voltage leadset 0 100 amp 2mm pins optional 100 ohm series resistor molded into barrel connector housing signal only Standard with LA Module The input resistance when used with a Reduced Bias Voltage leadset is 10 Kohms SMK4 optional gt P6418 gt P6418 www tektronix com la 35 Tektronix Logic Analyzers gt Detailed Product Information gt Quantity of Probes Per Option Option TLAZ7N1 1P Add P6418 Probes 2 2P Add P6434 Probes 1 3P Add P6417 Probes 2 Part Number Description 010 6418 00 17 channel probe 334 9979 00 1 sheet of probe labels not installed 196 3431 01 1 each 8 channel leadset barrel connectors support 0 100 spacing 196 3432 00 1 each 1 channel leadset barrel con
90. tups and data The TLA700 Series is card modular so you can configure the number and type of logic analyzer pattern generator or digitizing oscilloscope modules to meet your requirements 14 www tektronix com la ait ty biifis gt Up to 8 160 logic analyzer channels acquire real time data gt Expandability Expandable to Meet Future Needs A variety of flexible options such as new products field upgrade kits and special programs are avail able to enhance the measurement capabilities of your TLA bh pdt Mew pout hd babe ibia DSR AAF S eS r ERAEN E EE arne HBX BS 2747 Ww TAT an Gar TonTon Sraros Teen hile ararau e nj Private muh GerDara Gor Tha PITRT TAN RAIAR Macia lar In gt Advanced data analysis via Microsoft Excel Advanced Data Analysis The TLA Family s remote control command set based on Microsoft COM DCOM technology inter faces seamlessly with advanced Windows applica tions such as Microsoft Excel shown at right to provide powerful advanced data analysis and the graphical presentation of results either directly on the TLA or remotely over a network Offline Data Analysis The TLAVu Offline Data Viewer increases produc tivity From their desks designers can view data and create setups for the next time they are in the lab TLAVu software is a version of the TLA soft ware that installs on a PC running Windows 95 98 NT4 ME XP or 2000
91. ture that dramatically changes the way logic analyzers work and enables them to provide startling new measurement capabilities Capturing and Correlating Elusive Faults Complex system problems especially intermittent ones that show up late in product development can derail the most carefully planned schedules TLA logic analyzers Keep embedded hardware and soft ware designers on track by providing a non intru sive tool to monitor capture and analyze these elu sive real time system problems By capturing and correlating multiple views of data including analog digital and embedded software the design team can quickly identify the source of a problem wher ever it is World s Fastest Logic Analyzer Modules These remarkable high performance logic analyzer modules plug into your existing Windows 2000 Professional logic analyzer mainframe to deliver unmatched accuracy speed and ease of use for debug and verification work You may also route the analog signal of any 4 logic analyzer channels to an oscilloscope And all of the modules offer PowerFlex customer installable memory and speed upgrades to satisfy future needs www tektronix com la 9 Tektronix Logic Analyzers gt Detailed Product Information Find Digital Signal Integrity Problems Faster edge speeds and tighter timing margins are creating more signal integrity issues than ever before Overshoot ringing crosstalk reflections and ground bounce can cause
92. ut in one of the above formats TSF or the Tektronix symbol file a generic ASCII file format is supported The generic ASCII file format is documented in the TLA User Manual lf a format is not listed please contact your local Tektronix representative External Instrumentation Interfaces System Trigger Output Asserted whenever a system trigger occurs TTL compatible output back terminated into 50 Q System Trigger Input Forces a system trigger triggers all modules when asserted TTL compatible edge sensitive falling edge latched External Signal Output Can be used to drive external circuitry from a module s trigger mechanism ITL compatible output back terminated into 50 Q External Signal Input Can be used to provide an external signal to arm or trigger any or all modules TTL compatible level sensitive 24 00 in 609 60 mm 3 75 in 95 25 mm 3 00 in 76 20 mm B y 15 75 in 30 50 in 400 05 mm 774 70 mm C oS O 0 18 60 in t 472 20 mm 20 00 in 508 00 mm 24 00 in 609 60 mm 8 50 in 215 90 mm 25 00 in 635 00 mm gt LACART Instrument Cart adjustable probe skyhook not shown 4 75 in 120 65 mm Power Physical Characteristics TLA60x 61x 62x TLA60x Voltage range frequency 90 250 VAC at 45 66 Hz Dimensions mm in 100 132 VAC at 360 440 Hz Height 2
93. y return to Tektronix TLAZ21 Dual Monitor Benchtop Mainframe Includes Wheel mouse keyboard LAN PC Card five dual wide panel fillers for empty slots printer adapter two P6041 SMB to BNC adapter cables power cord North American 120 VAC 60 Hz software user manual certificate of calibration and one year warranty return to Tektronix Display is not included order Opt 3M or Opt 4M or use any SVGA monitor TLAZ7XM Expansion Mainframe Includes Iwo expansion modules three expansion cables six dual wide panel fillers for empty slots one single wide panel filler for empty slot manual power cord North American 120 VAC 60 Hz Statement of compliance and one year warranty return to Tektronix If installing a TLA7XM expansion mainframe into a TLA700 Series mainframe please consult the TLA Family Upgrade Guide for upgrade information TLA715 721 Options Opt 1C Add iView external oscilloscope interface kit 012 1614 00 Opt 1K Add LACART logic analyzer cart Opt 1S 512 MB DRAM 30 GB replaceable hard disk TLA715 only Opt 3M Add 18 in 1280x1024 flat panel display 119 6568 00 Opt 4M Add 21 in 1600x1200 flat panel display 119 6569 00 TLA7Z715 TLAZ21 TLAZXM International Power Plugs Opt A1 Universal Euro 220 VAC 50 Hz Opt A2 UK 240 VAC 50 Hz Opt A3 Australian 240 VAC 50 Hz Opt A4 North American 240 VAC 60 Hz Opt A5 Switzerla

Specs - TRS RenTelco

Contents

Download Pdf Manuals

Related Search

Related Contents