MC68341 Integrated Processor Use
Contents
1. ie ie A AA l A 4 0 20 0 008 H A B TD 0 20 0 008 A B r Ss gt 0 20 0 008 C AB D y 202 SEATING PLANE 0 10 0 004 si D DETAIL C i Case 86 MOTOROLA MC68341 USER S MA 65 Corrections to 8 16 Bit DMA Cont On page 11 10 the logic driving OE on the 74F245 in F though not detailed the byte enables for the memory bl tention between the upper and lower bytes of the data b DEVICE D15 D8 RW MC68341 A0 DACKx Figure 11 14 Circuit For Interfacin in Single Addre 66 X1 and BSW Input Levels On page 12 5 the Clock Input High Voltage spec also i 67 Operating IDD Limits On page 12 5 the spec operating RUN currents are sl Product Frequency Max Idd 68341 FT16V 16 78MHz 95mMA 3 6V 68341FT16 16 78MHz 150mMA 5 25 68341FT25 25 16MHz 210mMA 5 25 68 Input Clock Duty Cycle in Externa On page 12 7 External Clock With PLL Mode The inpt mode can be used when the VCO is not turned off durin the input clock is used for clocking the SIM and must External Clock Mode Without PLL 69 Clock Skew Notes 12 7 External Clock With PLL Mode Clock Input to CLI MOTOROLA MC68341 USER S MA edges of the clock signals the PLL phase locks the fall 70 Data Setup Time for 3 3V On page 12 9 electrica2. 27 MBAR Register Reset Values On page 4 22 the reset values for MBAR bits 31 12 are 28 MBAR AS7 Bit and IACK Cycles On page 4 23 the second code sequence initializes the dress decode for the internal 4K register block from res vents the register block decode of FFFFFxxx from inte possibly corrupting the vector number returned Normal ules is not affected by this change Early versions of the MC68330 User s Manual original Rev 1 releases did not show AS7 set Code which was be checked for this problem when porting to the MC68 MC68330 and or MC68340 29 Additional Note on VCO Overshoxc On page 4 30 place the following note under the Y bits MOTOROLA MC68341 USER S MA A VCO overshoot can occur when increasing the opera register The effects of this overshoot can be controlled 1 Write the X bit to zero This will reduce the previous 2 Write the Y bits to the desired frequency divided by 3 After the VCO lock has occurred write the X bit to c clock frequency to the desired frequency Steps 1 and 2 may be combined 30 RCCR Initialization Add to the RCCR description on page 4 41 the RCCR re an arbitrary value on initial powerup of the RTC Calibre beginning the calibration process since RTC operation reserved on current silicon it always reads 0 and shou 31 RCCR Typos On page 4 42 delete the first description for RCD4 RCI 32 MONTH Register Range The valid range for the MONTH register on page
3. 47 Typo in DAPI On page 6 26 for DAPI 1 the DAR is incremented ac 48 Additional note on DMA limited rez On page 6 27 in the BB Bus Bandwidth Field The DMA is the bus master each channel has its own counter relinquish the bus before completion of the active count Higher priority requests could come from 1 the other CPU32 core if either the interrupt mask level in the SR channel s ISM level or 3 an external bus request WI releases the bus and the idle count increments regarc 49 Configuration Error The Configuration Error description paragraph at the top error results when 1 either the SAR or DAR contains a in the CCR or 2 the BTC register does not match the l 50 Additional Note on DMA Interrupt Add to the Interrupt Register description on page 6 31 W interrupt level channel 1 is higher priority than channel MOTOROLA MC68341 USER S MA 51 Single Address Enable 6 33 SE Single Address Enable The note used for in 68341 does not support intermodule single address tran Q7 52 Code Examples Immediate Addr On pages 6 40 through 6 44 make the following change and NUMBYTE change to immediate addressing mode MOVE L SARADD DMASAR1 A0 should be MOVE MOVE L DARADD DMADAR1 A0 should be MOVE MOVE L NUMBYTE DMABTC1 A0 should be MOVE 53 Serial Oscillator Problems with DI Add to the Crystal Input or External Clock X1 section o 1MHz with excessive undershoot on DREQ1 can resuli
4. LWE DSACK DTC D15 D8 OP2 D7 D0 OP3 lt _ WORD WRITE gt lt Figure 3 14 M68000 MOTOROLA MC68341 USER S MA Parts Not Suitabl For Additiona End Of Life Prod MOTOROL Microprocessor and Memory 30 so s4 S0 Technologies Group CLKOUT ao ae ieee ee ADDENDUM TO aN j MC68341 Integrated Pro Eo April 19 1995 This addendum to the initial release of the MC68341 S z1 text plus additional information not included in the or is maintained on the AESOP BBS which can be ee 512 891 3650 Configure modem for up to 14 4Kk Sizo should support VT100 emulation Internet acce 129 38 233 1 or through the World Wide Web at ht RW 1 Signal Index es In jf N On page 2 4 Table 2 4 the QSPI serial clock QSCL 2 5 FC3 DTC is an output only signal ox If K 2 Operand Alignment wo o TO N On page 3 9 last paragraph change the first two li ar instructions to be word aligned That is word and k AS68K Long word operands do not have to be long word al UDS LDS 3 WE on Fast Termination wE AN y o O EEE E wooo N a On page 3 17 Figure 3 6 UWE and LWE do not as reo DSACK 4 Write Cycle Timing Waveforms On page 3 25 the M68300 write cycle timing diagra DI LWE On page 3 28 the M68000 write cycle timing CSx UDS LDS and UWE LWE Replace these figu D15 D8 ____0P2 5 Additional Note on MBAR Decod D 0 s Add to the CPU Space Cycles description o
5. 4 When HALT and BERR are ass bus cycle relative timing of HALT and BERR must be c MOTOROLA MC68341 USER S MA mination case 3 This can be done by asserting HALT control which edge each is recognized on or asynchro 47B ns before BERR to guarantee recognition on or be 13 Active Negate on Bus Arbitration The 68341 actively pulls up all tri stateable bus pins oth arbitration This pullup function is not guaranteed to res reduce rise time on these signals when using weak exte 14 Additional Note on Bus Arbitratio For the bus arbitration description beginning on page 3 lt ters for this device is external request via BR highest p channels 1 and 2 relative to each other is selected by th 15 Additional Note on Bus Arbitratio For the bus arbitration description beginning on page 3 when a higher priority request is recognized For examp results in a sequence of four bus cycles to complete the until the completion of the fourth bus cycle A single addi a dual address DMA transfer the read and write portion tion between the read and write bus cycles Also if diffe for the source and destination arbitration can occur be must be made to the smaller port for each operand acce for a TAS instruction is also indivisible to guarantee dati erand transfer of a multi operand operation such asa M 16 Additional Notes on RESET Intera Add to the Reset Operation description beginning page Hardware resets are held off unt
6. 4 43 is responding to December 33 SIM41 Example Code On page 4 49 about mid page change MOVEQ 8 1 lects 34 Bus Error Stack Frame On page 5 61 in the next to last paragraph delete the and the SSW is located at SP 12 The stack space all internal count register and SSW remains the same The counter location SP 10 and SP 12 will contain invalic frames look at the first nibble of the faulted exception fi the four word frame and 2 for the six word frame 35 DSO Timing On page 5 71 Figure 5 23 DSO transitions one clock I 36 Typo on BDM RSREG Command On page 5 77 Section 5 6 2 8 6 RSREG register bit 8 37 IPIPE Timing On page 5 88 Figure 5 29 shows the third IPIPE assert additional 0 5 CLKs IPIPE transitions occur after the fal MOTOROLA MC68341 USER S MA Timer register offsets from timerl ba IR EQU S4 interrupt regist CR EQU 6 control register SR EQU 8 status register CNTR EQU SA counter register PRLD1 EQU SC preload register COM EQU 10 compare register On page 8 27 change the last code line from CLR W S TC interrupt status bits are cleared by writing a 1 to cleared without affecting the other bits On page 8 28 second code line down the MOVE W initialized vector change the 0F to a user definable v just past mid page 61 MC68341 BSDL File An electronic copy of the BSDL file for the MC68341 is m of this document for information on accessing AESOP 62 Addit
7. ck can be supplied directly input both serial channels must use the same baud rate and the other in the 16x mode When using this method quired 56 68341 Serial Module RTS Differen Add to the description for receiver controlled RTS operai the 68681 the RTSx signal does not have to be manually flow capability on the receiver 57 Additional Note on Serial multidrc Add to the Multidrop Mode section beginning on page 7 the transmitter to manipulate the A D bit as generally ii the previous character completes transmission i e TxE pends it to the data character when the character is tre shift register Once this transfer occurs as indicated changed without affecting the character in progress TI bit for the next character would be 1 poll TxRDY until asserted or interrupt on TxRDY 2 set clear A D bit in MR1 for new character 3 write character to transmit buffer TB 4 A D bit can be changed only after TXRDY assert No other bits in MR1 should be modified when changing 58 Typo in CPE Description The CPE bit header on page 8 20 should be Counter P 59 Typo in Status Register Configure On page 8 26 Section 8 5 1 the Status Register SR bits to reset the interrupts 60 Typos in Timer Initialization Exar On pages 8 27 and 8 29 the Timer register offsets shou base address The correct equates for the Timer regist MOTOROLA MC68341 USER S MA D L niuuaiaa aad anataniadnnnt
8. electing either EXTCLK or EXTCLK 2 as referenc divided by 2 is used both for CLKOUT as well as the fee V 0 resulting in an initial processor operating frequenc For applications using external clock mode the 32KHz c if the realtime clock function is needed ground EXTAL CLK should be very clean when the 32KHz oscillator is fast edge rates may result in coupling to the adjacent X 22 Recommended XFC Capacitor Va On page 4 12 third paragraph and page 11 2 last para to 0 1uF applies specifically to crystal mode operation detector refernce frequencies gt 1MHz start with a cay 16 0MHz the recommended XFC capacitance is approxi standard value available 23 CLKOUT and VCO Frequency Pro On pages 4 13 and 4 14 the column for W 1 Z 0 X 1 column is 2x the frequency in the X 0 column immediate ing pages Note that although a complete table is shown frequency limits must be observed when programming t cy CLKOUT of 25 16MHz can be selected with W X Y However programming W X Y Z 1 0 47 1 to achieve th quency of greater than 100MHZz which is outside the sp 24 Additional Note for Global Chip S On page 4 16 section 4 2 4 2 When operating as a glc either the MBAR or to internal peripheral module registe MOTOROLA MC68341 USER S MA 38 Additional Notes on DMA Feature In the feature set listed on page 6 1 bullet six is Oper fers This packing is for transfers between different por e g Byte lt gt Word transfe
9. es without further notice to any prod the suitability of its products for any particular purpose nor does Motorola asst specifically disclaims any and all liability including without limitation conseque applications All operating parameters including Typicals must be validated fi convey any license under its patent rights nor the rights of others Motorola pro intended for surgical implant into the body or other applications intended to sup product could create a situation where personal injury or death may occur unauthorized application Buyer shall indemnify and hold Motorola and its office costs damages and expenses and reasonable attorney fees arising out of unintended or unauthorized use even if such claim alleges that Motorola was registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Af Literature Distribution Centers USA Motorola Literature Distribution P O Box 20912 Arizona 85036 EUROPE Motorola Ltd European Literature Centre 88 Tanners Drive JAPAN Nippon Motorola Ltd 4 32 1 Nishi Gotanda Shinagawa ku ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour C Tai Po N T Hong Kong TT0tttHGt E SEMICONDUCTOR PRC
10. il completion of the curr herency The processor resets at the end of the bus cycle or after the bus monitor has timed out The bus monitor not for the period of time that the BMT bits are set to The following reset sources reset all internal registers tc double bus fault loss of clock Execution of a RESET ir the exception of the MCR registers The MCR register in are not affected by execution of a RESET instruction 17 External Reset On page 3 56 Figure 3 33 the RESET signal negates fo not one Note that RESET is not actively negated and il 18 Power On Reset On page 3 57 Figure 3 34 Power Up Reset Timing Dia ternal control signals and can begin toggling as soon operating For crystal mode and external clock with VCO MOTOROLA MC68341 USER S MA stable value the 328 TCLKIN delay is counted down a delay For external clock mode without VCO the 328 TC are recognized See note for page11 3 for more POR in 19 Internal IMB Arbitration On page 4 6 first paragraph change the first sentence tc bus masters on the MC68341 to access the inter modul 20 Additional Note for External Clocl On page 4 9 Table 4 1 External Clock Mode with PLL falling edge of the EXTCLK input clock Maximum skew signals is specified in the Section 12 Electrical Characte 21 External Clock Mode Operation The next to last paragraph on page 4 11 incorrectly state the system frequency in external clock mode In externa cy by s
11. ional Note on Oscillator Lay Add to the Processor Clock Circuitry page 11 1 and S short connections and place external oscillator compone through or near the oscillator circuit especially high fre note above on DREQ1 and serial oscillator for page7 5 a separate trace for ground to the oscillator so that it do 63 Recommended 32KHz Oscillator On page 11 2 Figure 11 2 a 10M resistor can be subst R1 330 XTAL R2 MC683xx 10M EXTAL Figure 11 2 Sampl 64 SRAM Interface The SRAM interface shown in Figure 11 5 on page 11 4 LWE do not assert for 2 clock writes MOTOROLA MC68341 USER S MA 43 Additional Note on Cycle Steal For the external cycle steal mode description on page held off until after the channel is started If DREQx is alr the channel start bit an internal DREQx assertion is ger to start 44 DREQx Negation on Burst On page 6 8 Figure 6 5 and on page 6 10 Figure 6 7 one clock earlier than shown to prevent another DMA 6 5 on Burst Transfer DREQx Negation 45 DREQ Assert Time On page 6 21 Figure 6 13 The second DREQx assertio antee recognition on 2 consecutive clock falling edges 1 should be deleted 46 Fast Termination and Burst Requi On the last paragraph of page 6 21 delete the referenc incorrectly it actually shows operation with fast termina second DREQx signal should be held for 2 consecutive 1 clock edge Note 1 of Figure 6 14 should be deleted
12. l specification 27 Data Setu changed from 5ns to 8ns 71 UWE and LWE Signals In Figure 12 3 on page 12 12 UWE and LWE will asser In the fast termination write cycle in Figure 12 5 on pag like DS 72 Serial Module Specs Note 1 on page 12 25 should reference synchronous or 73 Ordering Information Replace the the ordering information table in Section 11 Supply Package Type Frequen Voltage MHz 5 0 V_ Plastic Quad Flat Pack 0 25 FT Suffix 5 0V_ Plastic Quad Flat Pack 0 16 7 FT Suffix 3 3 V Plastic Quad Flat Pack 0 16 7 FT Suffix 74 Upper and Lower Data Strobes In paragraph 3 2 8 page 3 6 change D15 D0 to D15 75 Figure 3 2 Change Note 1 to reference MC68341 instead of MC68 76 Figure 4 8 The Periodic Interrupt Control Register PICR and Perio instead of 2 bytes Disregard the Scale Select Register 77 Page 4 24 Refer to 4 17 for more information on the AVEC Autom 78 Page 4 48 The lake at the start of the code should be INIT341 inste MOTOROLA MC68341 USER S MA 79 Page 6 5 Paragraph 6 3 1 2 The table reference in the last sentence should be 6 4 r 80 Page 9 19 The timing diagrams reference as Figures 9 24 9 27 81 Page 9 29 DT Delay A value of 1 enable this bit and 0 disables it 82 Package Dimensions The package dimension drawing on page 13 3 should b MOTOROLA MC68341 USER S MA Motorola reserves the right to make chang
13. lator X1 pin damping out oscillation Avoid routing DREC use termination techniques such as series termination o of the signal and accompanying undershoot 54 Additional Note on RTSx operatio Add to the RTSA and RTSB descriptions on page 7 6 T logic O when set and a logic 1 when cleared RTSx can be set output logic level 0 by any of the follo e Writing a 1 to the corresponding bit in the OPSET Issuing an Assert RTS command using command e If RXxRTS 1 set by receiver FIFO transition from FL RTSx can be cleared output logic level 1 by any of the e Hardware reset of the serial module e Writing a 1 to the corresponding bit in the OPRES e Issuing a Negate RTS command using command e If RXxRTS 1 cleared by receiver FIFO transition fror e If TXRTS 1 cleared by completion of last character 55 Serial Frequency Restriction On page 7 8 place the following notes at the end of Sec The current implementation of the serial module restrict rate generators can be used to approximately 8 3MHz nized internal clock which is at a lower frequency than th One method to extend the minimum CLKOUT frequen shown in the table below The corresponding baud rates MOTOROLA MC68341 USER S MA scaled by the same factor This method preserves most Serial XTAL Frequency CLKOUT Fr 3 6864MHz 8 29MHz 1 8432 4 15 0 9216 2 07 CLKOUT min 2 25 XTAL frequency Alternatively the baud rate clo
14. n page lt WORD Wart gt lt block from 3FFO0 3FFFF to the SIM module An in for any access to this range but selection of specific Accesses to the MBAR register at long word 3FFO cycles Users should directly access only the MBAR LPSTOP broadcast access to 3FFFE The remainir Figure 3 12 M68300 should not be accessed This document contains information on a product under development Motor TIT SEMICONDUCTOR F MOTOROLA MC68341 USER S MA MOTOROLA 1995 Table 4 2 System Frequencies CLKOUT kHz ce ECuEGE 16 33 Oo AN OO FPF WOOD O lt OwWNNNNNNNNNND BF a a d Fete ser se O O AN OA FPF WOND FB OCOD AN OA F ON CO a ae 262 524 786 1049 1311 1573 1835 2097 2359 2621 2884 3146 3408 3670 3932 4194 4456 4719 4981 5243 5505 5767 6029 6291 6554 6816 7078 7340 7602 7864 8126 8389 VCO kHz W 0 Z xX X xX 524 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 1048 1101C 11534 1205 12582 13107 13631 1415 1468C 15204 1572 16252 16777 MOTOROLA MC68341 USER S MA 6 Additional Notes on CPU Space Ac On page 3 31 Figure 3 16 the BKPT field for the Brea and the T bit is on bit 1 The Interrupt Acknowledge LE 7 Breakpoints On page 3 31 the last paragraph implies that either a breakpoint can be used to insert an instruction As breakpoint can be used to inser
15. ock accesses using cycle incomplete overlap of the DMA transfer with internal IM single address 2 clock transfers and 2 dual address tra completely overlapped for all other cases MOTOROLA MC68341 USER S MA Table 4 2 System Frequencies from lt CLKOUT kHz VCO kHz W 0 Z xX X xX 17302 1782 18350 18874 1939 19923 20447 20972 2149 2202C 22544 2306 2359 24117 24642 2516 2569C 26214 2673 2726 27787 28312 2883 29360 29884 3040 3093 31457 31982 3250 3303C 33554 NOTES 1 Some W X Y Z bit combinations shown may select a CLI tion 11 Electrical Characteristics for CLKOUT and VC 2 Any change to W or Y results in a change in the VCO frequ MOTOROLA MC68341 USER S MA 25 Additional Note on PORTA B Out Add to the External Bus Interface Operation description sition after the S4 falling edge for the internal write to tht tions at roughly the same time DS negates for the data specified in the Electrical Specifications 26 RTC Memory Map The RTC register offsets shown on page 4 21 are incor dresses within the RTC can be accessed as either byte offset 0CE Note that RTC registers marked S U are re user mode ADDR FC 15 8 oco s RTC INTER 0c2 S U MINUTES MIN 0c4 S U DATE oc S U MONTH oc8 Ss RTC CONTROL STATUS RCR OCA S U MINUTES ALARM MINA occ S U DATE ALARM DATEA 0CE RESERVED
16. rs The DMA controller does n problem of residual bytes left in the controller when a ch 39 Additional Note on Internal Reque Add to the Internal Request Generation section on page Ex are not active as outputs during transfers DONEx i operation if asserted pull up if not used 40 Additional Note on DMA Transfer Add to the External Request Generation section beginnii synchronization and IMB bus arbitration activity before sertion will preempt the next CPU bus cycle if it is recogr bus cycle unless the current cycle is not the last cycle o Operand transfers and RMC read write sequences are i not be arbitrated from the CPU until the complete oper sizing results in multiple bus cycles For a DREQx assertion during an idle bus period bus sti clock falling edge which DREQx is recognized on Thi DREQx is recognized on to the falling edge that AS for table for various memory speeds DREQ Latency Clocks vs Bus Maximum I Access Type 16 Bit Bus Clocks Bus Cyc 2 3 4 Longword 7 9 11 RMC TAS 10 12 14 41 Additional Note on Burst Transfer On page 6 5 replace the 2nd paragraph of 6 3 2 1 Exte negated one clock before the end of the last DMA bus c being generated Also DREQx must be negated two cloc an idle clock between that transfer and the following CP 42 Additional Note on Cycle steal DN Add to the External Cycle Steal Mode description on pz ently However for some 2 cl
17. t an instruction on the br 8 Interrupt Latency Add to the Interrupt Acknowledge Bus Cycles section prefetch of the first instruction in the interrupt handler clocks using 2 clock memory and autovector terminatio DIVS L with worst case lt fea gt 108 clocks worst ce shorter interrupt response time the latency can be reduce use of longer instructions specifically DIVS L DIVULL 9 Interrupt Hold Time and Spurious Add to the Interrupt Acknowledge Bus Cycles section asserted until the corresponding IACK cycle otherwise rupt may be ignored entirely This is also true for level se ing either the AVEC signal or the AVEC register since tr on the IMB if the external interrupt at that level has been sitive only have to be held a minimum of 1 5 clocks lt REGISTER PIR Note that the level 7 interrupt is also level sensitive and interrupt is unique in that it cannot be masked anothe IACK cycle by negating IRQ7 and reasserting even thc level 7 10 Typos in IACK Cycle Timing Wave On page 3 38 Figure 3 21 the text VECTOR FROM FROM 8 BIT PORT should be on D15 D8 The respond nificant byte of the data port 11 Additional Note on Internal Autov Add to the Autovector Interrupt Acknowledge Cycle s autovectored either by the AVEC register programming started and terminated internally The interrupting devic resulting operation is undefined 12 Additional Notes on Retry Termin On page 3 42 Table 3
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