Home

i87 User Manual i87 User Manual V1.2

1. Ox4E Clear the watchdog timer clear code OxB1 Disable the watchdog timer operation and clear WDTCR2 Write watchdog timer control codes the 8 bit up counter when WDCTR lt WDTEN gt is 0 disable code Others Invalid Page 36 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BT RPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 8 bit Up Counter Monitor WDCNT 3 OxOFD6 Bit Symbol Read Write After reset Monitor the count value of the 8 bit The count value of the 8 bit up counter is read up counter Watchdog Timer Status WDST OxOFD7 x 2 1 Bit Symbol WINTST2 WINTST1 Read Write R R R R After reset 0 0 0 0 No watchdog timer interrupt request signal has occurred WINTST2 Watchdog timer interrupt request signal factor
2. TTN Q Q Q gt Vv Figure 4 6 Voltage Detection Circuit 4 3 2 Control The voltage detection circuit is controlled by voltage detection control registers 1 2 and 3 Voltage Detection Control Register 1 VDCRI Ox0FC6 z Bit Symbol Read Write After reset Voltage detection 1 flag Retain the state when 0 VDD2VDILVL VDD lt VD1LVL is detected 1 VDD lt VDILVL Voltage detection 1 status flag Magnitude relation 0 VDD 2 VDILVL of VDD and VD1LVL when they are read 1 VDD lt VDILVL Note 1J VDCR1 is initialized by a power on reset or an external reset input Note 2 When VDIF is cleared by the software and is set due to voltage detection at the same time the setting due to voltage detection Is given priority Note 3 VDIF cannot be programmed to 1 by the software Voltage Detection Control Register 2 VDCR2 Ox0FC7 6 2 Bit Symbol Read Write After reset Page 29 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entire
3. 0 Disable Enable disable the divider output 1 Enable Normal 1 2 IDLE 1 2 mode SLOW 1 2 mode DV9CK 0 DV9ICK 1 SLEEP 1 2 mode Select the divider output frequency fegck 2 2 fs 2 fs 2 Unit Hz fcgck 2 fs 24 fs 24 fegck 2 9 fs 23 fs 23 fcgck 2 Reserved Reserved Note 1 fegck Gear clock Hz fs Low frequency clock HZ Note 2 DVOCR lt DVOEN gt is cleared to 0 when the operation is switched to STOP or IDLEOQ SLEEPO mode DVOCR lt DVOCK gt holds the value Note 3 When SYSCRI lt DV9CK gt is 1 in the NORMAL 1 2 or IDLE 1 2 mode the DVO frequency Is subject to some fluctuations to synchronize fs and fcgck Note 4 Bits 7 to 3 of DVOCR are read as 0 5 2 3 Function Select the divider output frequency at DVOCR lt DVOCK gt The divider output is enabled by setting DVOCR lt DVOEN gt to 1 Then the rectangular waves selected by DVOCR lt DVOCK gt are output from DVOB pin It is disabled by clearing DVOCR lt DVOEN gt to 0 And DVOB pin keeps H level When the operation is changed to STOP or IDLEO SLEEPO mode DVOCR lt DVOEN gt is cleared to 0 and the DVOB pin outputs the H level The divider output source clock operates regardless of the value of DVOCR lt DVOEN gt Therefore the frequency of the first divider output after DVOCR lt DVOEN2 gt is set to 1 is not the frequency set at DVOCR lt DVOCK gt When t
4. PWMDUTY is a 7 bit register used to set the duty pulse width value the time before the first output change in a cycle 128 counts of the source clock PWMAD is a register used to set the additional pulse When PWMAD is 1 an additional pulse that corresponds to 1 count of the source clock is added to the 2 x n th duty pulse n 1 2 3 In other words the 2 x n th duty pulse has the output of PWMDUTY 1 The additional pulse is not added when PWMAD is 0 Additional pulse Additional Timer start pulse g Duty pulse Duty pulse width width TOOPWM TOOPWM 1 lt gt lt gt PWMO pin output TFFO 1 1 i 1 i H j i i i i i PWMO pin output TFFO 0 wm gt lt gt 128 counts 128 counts i cycle width cycle width INTTCOO interrupt request Cycle 1 Cycle 2 Cycle 3 Cycle 4 Figure 5 13 PWMOB Pulse Output Set the initial state of the PW MOB pin at TOOMOD lt TFFO gt Setting TOOMOD lt TFFO gt to 0 selects the L level as the initial state of the PWMOB pin Setting TOOMOD lt TFFO gt to 1 selects the H level as the initial state of the PW MOB pin If the PW MOB pin is set as the function output pin in the port setting while the timer is stopped the value of TOOMOD lt TFFO gt is output to the PW MOB pin Table 5 9 shows the list of output levels of the PX MOB pin Page 57 82 The information contained herein shall n
5. Set the count value to be used for the match detection as a 16 bit value at the timer registers TOOREG and TOIREG Set the lower 8 bits of the 16 bit value at TOOREG and set the higher 8 bits at TOIREG Hereinafter the 16 bit value specified by the combined setting of TOIREG and TOOREG is indicated as TO1 OOREG The timer register settings are reflected on the double buffer or TO1 OOREG when a write instruction is executed on TOIREG Be sure to execute the write instructions on TOOREG and TO1REG in this order When data is written to the high order register the set values of the low order and high order registers become effective at the same time Set TOIMOD lt DBE1 gt to 1 to use the double buffer Setting TOOICR lt TO1IRUN gt to 1 starts the operation After the timer is started writing to TOIMOD becomes invalid Be sure to complete the required mode settings before starting the timer Make settings when TO0O1CR lt TOORUN gt and lt T01RUN gt are 0 b Operation Setting TOO1CR lt TO1RUN gt to 1 allows the 16 bit up counter to increment at the falling edge of the TCOO pin When a match between the up counter value and the T00 O1REG set value is detected an INTTCO1 interrupt request is generated and the up counter is cleared to Ox0000 After being cleared the up counter restarts counting Setting TOOICR lt TO1RUN gt to 0 during the timer operation makes the up counter stop counting and be cleared to Ox0000
6. KWUCRn lt KWmLE gt 0 KWUCRn lt KWmLE gt 1 H level Rising edge Pinname SYSCR1 lt RELM gt 0 edge release mode L level H level Don t use Table 3 3 STOP Mode Release Level Edge Page 19 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 4 Reset Function 4 1 Reset Control Circuit The reset circuit controls the external and internal factor resets and initializes the system 4 1 1 Configuration The reset circuit controls the external and internal factor resets and initializes the system External reset input external factor Power on reset internal factor Voltage detection reset internal factor Watchdog timer reset internal factor System clock reset internal factor P10 RESET O P10 port Internal factor reset detection status register gt Voltage detection circuit reset signal Power on reset signal External reset
7. TOOREG x Match detection Match detection o n Match detection j Reflected by Jj as data is written into TOOREG A INTTCOO0 interrupt request while the timer is stopped an interrupt Figure 5 10 Timer Mode Timing Chart TOOMOD lt DBE0 gt Source clock Counter Write to TOOREG TOOREG Match detection INTTCOO0 interrupt request Figure 5 11 Operation When TOOREG and the Up Counter Have the Same Value Page 54 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMQ from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 5 4 4 2 8 bit Event Counter Mode In the 8 bit event counter mode the up counter counts up at the falling edge of the input to the TCOO or TCO pin The operation of TCOO is described below and the same applies to the operation of TCO1 a Setting Set the count value to be used for the match detection as an 8 bit value at the timer register TOOREG TCOO is put into the 8 bit event counter mod
8. fegck 8MHz fs 32 768KHz fegck 8MHz fs 32 768KHz 488 2us 65 2ms 124 5ms 244 1us 32 6ms 62 3ms 8 2ms fegck 2 fegck 2 fegck 2 fegck 24 fegck 22 fegck 22 fegck 2 fegck 2 fegck fegck Table 5 8 8 bit Timer Mode Resolution and Maximum Time Setting Page 53 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use EZ SFR DARA S iMO Technology Inc Title IMO i87 User Manual Version V1 2 Timer start Timer stop TOO1CR lt TOORUN gt TOOMOD lt DBEO gt Source clock Counter E a 1X X3 Counter clear Counter clear Write to TOOREG Match detection TOOREG Y m A INTTCO0 interrupt request A Reflected by writing to TOOREG Reflected by writing to TOOREG When the double buffer is disabled TOOMOD lt DBEO gt 0 4 Timer start TOO1CR lt TOORUN gt TOOMOD lt DBEO gt Source clock Counter A Ki x Ko y X Wola A See Se Write to TOOREG Double buffer
9. INTRTC interrupt request fs 32 768 kHz Figure 5 25 Real Time Clock 5 5 2 Control The real time clock is controlled by following registers Low Power Consumption Register 2 POFFCR2 7 6 OxOF76 Bit Symbol Read Write After reset 0 Disable RTC control 1 Enable Real Time Clock Control Register RTCCR Ox0FC8 4 6 2 7 Bit Symbol RTCSEL RTCRUN Read Write R R R R R W R W After reset 0 0 0 0 000 2 5 fs 1 000 s fs 32 768kHz 001 2 4 fs 0 500 s fs 32 768kHz 010 213 fs 0 250 s fs 32 768kHz Selects the interrupt generation 011 2 2 5 125 0 ms fs 32 768kHz interva 100 2 fs 62 50 ms fs 32 768kHz 101 21075 31 25 ms fs 32 768kHz 110 29 5 15 62 ms fs 32 768kHz 111 28 fs 7 81 ms fs 32 768kHz RTCRUN Fnabies disanies the real time clock 0 Disable operation 1 Enable Page 80 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or ex
10. The maximum frequency to be supplied is fegck 2 Hz in NORMAL1 2 or IDLE1 2 mode or fs 2 Hz in SLOW1 2 or SLEEP1 mode and a pulse width of two machine cycles or more is required at both the H and L levels c Double Buffer Refer to 5 4 4 5 c Double Buffer Page 69 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use EZ SFR AAAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 4 Timer start 4 Timer stop TOOICR lt TO1RUN gt TCOO pin input Counter Counter Write to TOOREG i i deer Write to TOTREG T01 00REG Ykm INTTCOO interrupt A Reflected by writing to TO1REG A pnn Reflected by writing to TO1REG When the double buffer is disabled T01MOD lt DBE1 gt 0 TOO1CR lt TO1RUN gt a ey AER E Ny Es Ah She A Counter ACounter Write to TOOREG i dear writes cear 4 Timer start Write to TOTREG Double buffer T01 00REG Reflected by p IN
11. The time base timer generates the time base for key scanning dynamic display and other processes It also provides a time base timer interrupt INTTBT in a certain cycle 5 3 1 Configuration fegck 272 or fs 215 fegck 279 or fs 213 fegck 2 5 or fs 2 IDLEO SLEEPO _ or pa Falling edge Release request icgck 2 lt or paso or fs 24 INTTBT fegck 2 or fs 23 Interrupt request fegek 2 JO E ES Figure 5 7 Time Base Timer Configuration Page 43 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 5 3 2 Control The time base timer is controlled by the time base timer control register TBTCR Time Base Timer Control Register TBTCR 7 6 0x0039 Bit Symbol Read Write After reset Enable disable the time base timer 0 Disable interrupt requests 1 Enable Normal 1 2 IDLE 1 2 mode SLOW 1 2 mode DV9CK 0 D
12. 1 VF 0 The following table shows how the A and WA registers and the PSW bits are affected by various instructions AorWA ADDC A HL SUBB A HL CMP A HL AND A HL LD A HL ADD A 0x66 INCA ROLC A RORC A ADD WA 0xF508 MUL WA SET A 5 soeesoesoos s Table 3 2 Examples of How A and WA Registers and the PSW Bits Affected by Various Instructions 3 5 7 Register Bank Selector RBS The RBS is a single bit register that selects one of the two banks of the general purpose registers For example when RBS 1 Bank 1 is selected Upon reset the RBS bit is cleared to 0 causing Bank 0 to be selected The RBS bit can be set or cleared by the load immediate instructions LD RBS n and LD PSW n and the push and pop instructions PUSH PSW and POP PSW The instructions LD PSW n and PUSH PSW affect all the PSW bits including the RBS bit To modify only the RBS bit the instruction LD RBS n should be used Upon an interrupt the CPU saves the RBS bit onto the stack together with the other bits of the PSW At that time the RBS bit remains unchanged The return from interrupt instruction restores Page 14 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO device
13. 32 8ms 62 5ms 710 3 fegck 2 iaz 524 3ms 1000ms 8 2ms 78 28 fegck 2 fegck 2 131 1ms 2 0ms 32 8ms A 512us kyz 8192us 128us 2048us fegck 2 fegck 2 feg ck 2 fcg ck 2 64us fegck 2 fcgck 2 g g 1024us 32us 31 3ms 512us 500ms fegck fegck Table 5 15 Resolutions and Cycles in the 12 bit PWM Mode 5 4 4 8 16 bit Programmable Pulse Generate PPG Output Mode In the 16 bit PPG mode TCOO and TCO1 are cascaded to output the pulses that have a resolution of 16 bits and arbitrary pulse width and duty Two 16 bit registers TO1 OOREG and T01 O0PWM are used to output the pulses This enables output of longer pulses than an 8 bit timer a Setting Setting T001CR lt TCAS gt to 1 connects TCOO and TCO1 and activates the 16 bit mode All the settings of TCOO are ignored and those of TCO1 are effective in the 16 bit mode The 16 bit PPG mode is selected by setting TOIMOD lt TCM1 gt to 11 To use the internal clock as the source clock set TOIMOD lt EIN1 gt to 0 and select the clock at TOIMOD lt TCK1 gt To use an external clock as the source clock set TOIMOD lt EINO gt to 1 Set TOIMOD lt DBE 1 gt to 1 to use the double buffer Set the count value that corresponds to a cycle as a 16 bit value at the timer registers TO1REG and TOOREG Set the count value that corresponds to a duty pulse as a 16 bit value at TOIPWM and TOOPWM Hereinafter the 16 bit
14. 7 Addressing Space of Program Data Memory and Special Function Registers SFR and 8 Operation Modes This IMO i87 User Manual illustrates parts 1 to 6 in detail As to parts 7 and 8 please refer to MO8S MCU datasheet specifically The system clock is derived from either a crystal or an oscillator It is internally divided into default four non overlapping clocks which can be no division too One instruction cycle consists of four system clock cycles Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle If an instruction changes the value of the program counter two cycles are required to complete the instruction 3 2 Stack Area and Stack Pointer 3 2 1 Stack Area A stack is an area in memory for temporarily saving the PC PSW and other values during subroutines and interrupts When a subroutine is called by the CALL mn or CALLV n instruction the CPU pushes saves the high order and low order bytes of the return address on the stack before jumping to the subroutine entry address When the software interrupt instruction SWI is executed and when a hardware interrupt is accepted the CPU saves the PSW and then return address on the stack When the return from subroutine instruction RET is executed the CPU p
15. CF v ZF 0 SFv VF 1 SFv VF 0 ZF v SF v VF 1 ZF v SF v VF 0 Table 3 1 Condition Code cc Table The instruction LD PSW n not only affects the RBS bit but also clears all the other bits in the PSW To switch the register bank without changing other PSW bits the instruction LD RBS O or LD RBS 1 should be used instead of LD PSW n An attempt to write to the address 0x3F using a load instruction is ignored Instead the PSW bits are set or cleared as predefined for a given instruction Upon an interrupt the PSW is pushed saved onto the stack together with the Program Counter The content of the stack is popped restored to the PSW by the return from interrupt instructions RETI and RETN Page 12 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMQO from any and all damages claims suits or expenses resulting from such use SZET RDARAS iMQ Technology Inc Title iMQ i87 User Manual Version V1 2 The values of the PSW bits become undefined upon power up and reset except RBS The RBS bit is cleare
16. If these are problems enable the double buffer When a write instruction is executed on TOOPWM TOOREG while the timer is stopped the set value is immediately stored in TOOPWM TOOREG Y Timer start Timer stop TOO1CR lt TOORUN gt TOOMOD lt TFFO gt Source clock UUU UUU UU P i 5 MR p ee AE DE ee E a Counter E Kt Kat m ine KNOX 1 t r EN ox NN 1 t ENOC 0 j Counter i Counter clear clear Counter Counter i clear i clear Write to TOOPWM Write m write r I Write t Double buffer TOOPWM Write to TOOREG Double buffer TOOREG PPGO pin output A i Retums to the Becomes the level selected at t h level selected INTTCOO interrupt TFFO while the timer is stopped l i 1 f at TFFO request 7 t 1 7 t m i r i F i i Duty pulse Duty pulse Duty pulse Duty pulse s p t s f w 1 cycle 1 cycle 1 cycle 1 cycle When the double buffer is enabled TOOMOD lt DBE0 gt 1 Figure 5 17 8 bit PPG Mode Timing Chart Page 64 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify a
17. the PPGOB pin changes from the L to H level At this time an INTTCOO interrupt request is generated When TO01CR lt TOORUN gt is set to 0 during the operation the up counter is stopped and cleared to 0x00 The PPGOB pin returns to the level selected at TOOMOD lt TFFO gt When the external source clock is selected the maximum frequency to be supplied is fegck 2 Hz in NORMAL1 2 or IDLE1 2 mode or fs 2 Hz in SLOW1 2 or SLEEP1 mode and a pulse width of two machine cycles or more is required at both the H and L levels c Double Buffer The double buffer can be used for TOOPWM and TOOREG by setting TOOMOD lt DBEO gt The double buffer is disabled by setting TOOMOD lt DBEO gt to 0 or enabled by setting TOOMOD lt DBEO gt to 1 1 When the Double Buffer is Enabled When a write instruction is executed on TOOPWM TOOREG during the timer operation the set value is first stored in the double buffer and TOOPWM TOOREG is not updated immediately TOOPWM TOOREG compares the previous set value with the up counter value When an INTTCOO interrupt request is generated the double buffer set value is stored in TOOPWM TOOREG Subsequently the match detection is executed using a new set value When a read instruction is executed on TOOPWM TOOREG the value in the double buffer the last set value is read out not the TOOPWM TOOREG value the currently effective value When a write instruction is executed
18. Figure 3 4 General Purpose Registers The W A B C D E H and L registers are individually used by the 8 bit load store and ALU instructions The WA BC DE and HL register pairs are used by the 16 bit load store and ALU instructions These registers also provide the functionalities discussed in the following subsections in addition to the common characteristics as general purpose registers Note that some iMO MCU such as MQ8602 has only general purpose register banko 3 4 1 A Registers Bit manipulation instructions can use the A register to specify a bit position in a register whose value should be tested or changed The A register is also used as an offset register in PC Relative Register Indirect Addressing PC A 3 4 2 C Registers For divide instructions the C register holds the divisor The remainder is written back into the upper byte of the register pair specified as the dividend the quotient is written back into the lower byte The C register is also used as an offset register in Register Indexed Addressing HL C Page 10 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer ag
19. L H ee Figure 4 2 External Reset Input when the power is turned on Recommended operating voltage Reset time RESET pin f gt gt During reset Warm up operation CPU and peripheral circuits Reset signal 7 start operation Figure 4 3 External Reset Input when the power is stabilized Page 24 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 If the supply voltage is lower than the recommended operating voltage range for example when the power is turned on the supply voltage is raised to the operating voltage range with the RESETB pin kept at the L level and a reset is applied 5 us after the oscillation is stabilized If the supply voltage is within the recommended operating voltage range the RESETB pin is kept at the L level for 5 us with the stabilized oscillation and then a reset is applied In each case after a reset is applied i
20. WDT The watchdog timer is a fail safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions and return the CPU to a system recovery routine The watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request signals or watchdog timer reset signals Note Care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturbing noise and other effects 5 1 1 Configuration 0 3 fegck 2 or fs 2 gt Sen diauk 8 bit up counter fogck 2 or fs 25 gt Interrupt ati 7 request reset fegck2 or fs 2 gt Clear signal control Watchdog timer reset signal Meee A circuit B Watchdog timer interrupt request fegeki2 or fs 2 gt CPUlperipheral circuits reset Clear time control circuit Disable control circuit _wocnT Figure 5 1 Watchdog Timer Configuration 5 1 2 Control The watchdog timer is controlled by the watchdog timer control register W DCTR the watchdog timer control code register W DCDR the watchdog timer counter monitor WDCNT and the watchdog timer status W DST The watchdog timer is enabled automatically just after the warm up operation that follows reset is finished Watchdog Timer Control Register WDCTR O
21. it can be designated as a pin for receiving a STOP mode release signal irrespective of whether the key on wakeup function is used or not 3 7 3 1 Setting KWUCRn and P4PU Registers To designate a key on wakeup pin KWIm as a STOP mode release pin set KWUCRn lt KW mEN gt to 1 After KWIm pin is set to 1 at KWUCRn lt KWmEN gt a specific STOP mode release level can be specified for this pin at KWUCRn lt KWmLE gt If KWUCRn lt KWmLE gt is set to 0 STOP mode is released when an input is at a low level If it is set to 1 STOP mode is released when an input is at a high level For example if you want to release STOP mode by inputting a high level signal into a KWIO pin set KWUCRO lt KWOEN gt to 1 and KW UCRO lt KWOLE gt to 1 Each KWlIm pin can be connected to internal pull up resistors Before connecting to internal pull up resistors the corresponding bits in the pull up control register P4PU at port P4 must be set to 1 3 7 3 2 Starting STOP Mode To start the STOP mode set SYSCR1 lt RELM gt to 1 level release mode and SYSCR1 lt STOP gt to io hee To use the key on wakeup function do not set SYSCR1 lt RELM gt to 0 edge release mode If the key on wakeup function is used in edge release mode STOP mode cannot be released although a rising edge is input into the STOPB pin This is because the KWIm pin enabling inputs to be received is at a release level after the STOP mode starts 3 7 3 3 Releasi
22. lt DV9CK gt 0_ lt DV9CK gt 1 000 fegck 2 fs 24 fs 24 001 fegck 2 9 fs 23 fs 23 Operation clock selection 010 fegck 2 fegck 28 011 fegck 2 fegck 2 100 fegck 24 fegck 2 lt 101 fcgck 22 fcgck 22 110 fcgck 2 fcgck 2 111 fcgck fcgck fs 22 0 Select the internal clock as the source clock 1 Select an external clock a s the source clock the falling edge of the TCOO pin Selection for using external source clock Page 47 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use ze RDAAd iMO Technology Inc Title IMO i87 User Manual Version V1 2 8 bit timer event counter modes 8 bit timer event counter modes Operation mode selection 8 bit pulse width modulation output PWM mode 8 bit programmable pulse generate PPG mode Note 1 fegck Gear clock Hz fs Low frequency clock Hz Note 2 Set TOOMOD while the
23. order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 2 Overview of iMO i87 User Manual iIMQ MQO8S MCU series 8 bit MCU adopts iMO i87 8 bit MCU core It s a powerful MCU core with 1T instruction cycle various timer counter resources interrupt resources I O options multiple operation modes and flexible memory configuration Integrated with accurate analog features such as voltage regulators internal external clocking circuits voltage detectors power on reset and analog to digital converters ADC MO8S MCU series provides complete solutions for wide MCU applications In this IMO i87 User Manual general functions of the MCU such as registers flag information timers counter information and reset detection circuit are described in detailed For specific functions of each MOB8S MCU product such as program data memory special function register interrupts system clocking operation modes and I O port information please refer to the MO8S MCU datasheet Please note that in this document 64K Bytes or smaller memory style is used Therefore the address format will be Ox0000 or OxOO00H to OxFFFF or OxXFFFFH Note that pin names
24. 05V 0 2 V 0101 3 42V 0 2 V 0101 2 91V 0 2 V 0110 3 27V 0 2 V 0110 2 78V 0 2 V 0111 3 11V 0 2 V 0111 2 65V 0 2 V VDILVL Selection for detection voltage 1 1000 2 96V 0 1 V 1000 2 52V 0 1 V 1001 2 80V 0 1 V 1001 2 38V 0 1 V 1010 2 65V 0 1 V 1010 2 25V 0 1 V 1011 2 49V 0 1 V 1011 2 12V 0 1 V 1100 2 33V 0 1 V 1100 1 99V 0 1 V 1101 2 18V 0 1 V 1101 1 86V 0 1 V 1110 2 03V 0 1 V 1110 1 73V 0 1 V 1111 1 88V 0 1 V 1111 1 60V 0 1 V For 3 3V 5V such as MO8601 MQ8801 For 3 3V only such as MO8602 MQ8603 4 3 3 Function One detection voltage VD1LVL can be set in the voltage detection circuit Enabling disabling the voltage detection and the operation to be executed when the supply voltage VDD becomes lower than the detection voltage VD1LVL can be programmed 4 3 3 1 Enabling Disabling the Voltage Detection Operation Setting VDCR2 lt VD1EN gt to 1 enables the voltage detection operation Setting it to 0 disables the operation VDCR2 lt VDI1EN gt is cleared to 0 immediately after a power on reset or a reset by an external reset input is released Page 30 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product s
25. 2 512us 64us 2 2 fcgck 2 fegck 2 128us 32us fegck 2 fegck 2 64us 16us 15 6ms fegck fegck 122 1us 32us 31 3ms Table 5 10 Resolutions and Cycles in the 8 bit PWM Mode 5 4 4 4 8 bit Programmable Pulse Generate PPG Output Mode In the 8 bit PPG mode the pulses with arbitrary duty and cycle are output by using the TOOREG and TOOPWM registers By setting the T001CR lt OUTAND gt register a pulse that is a logical ANDed product of the TCOO and TCO outputs can be output to the TCO1 pin This function facilitates the generation of remote controlled waveforms for example The operation of TCOO is described below and the same applies to the operation of TCO1 Page 61 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 a Setting TCOO is put into the 8 bit PPG mode by setting TOOMOD lt TCMO0O gt to 1 and TOOICR lt TCAS gt t
26. 4 2 2 Timer Counter 01 5 4 2 3 Common to Timer Counters 00 and 01 5 4 2 4 Operation Modes and Usable Source Clocks 5 4 3 Low Power Consumption Function 5 4 4 Function 5 4 4 1 5 4 4 2 5 4 4 3 5 4 4 4 5 4 4 5 5 4 4 6 5 4 4 7 5 4 4 8 8 bit Timer Mode 8 bit Event Counter Mode 8 bit Pulse Width Modulation PWM Output Mode 8 bit Programmable Pulse Generate PPG Output Mode 16 bit Timer Mode 16 bit Event Counter Mode 12 bit Pulse Width Modulation PWM Output Mode 16 bit Programmable Pulse Generate PPG Output Mode Real Time Clock RTC 5 5 1 Configuration 5 5 2 Control 5 5 3 Function 5 5 3 1 5 5 3 2 5 5 3 3 Low Power Consumption Function Enabling Disabling the Real Time Clock Operation Selecting the Interrupt Generation Interval 5 5 4 Real Time Clock Operation 5 5 4 1 5 5 4 2 Enabling the Real Time Clock Operation Disabling the Real Time Clock Operation Page 4 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG i
27. After reset 7 Bits 7 to 4 of TO1PWM are not used in the 12 bit PWM mode However data can be written to these bits of TO1PWM and the written values are read out as they are when the bits are read Normally set these bits to 0 PWMDUTYH and PWMDUTYL are 4 bit registers They are combined to set an 8 bit value of duty pulse width time before the first change in the output for one cycle 256 counts of the source clock Hereinafter an 8 bit value specified by the combined setting of PWMDUTYH and PWMDUTYL is indicated as PWMDUTY PWMAD3 to PWMADO are the additional pulse setting register Additional pulses can be inserted in specific cycles of the duty pulse by setting each bit to 1 The additional pulses Page 71 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMQ i87 User Manual Version V1 2 are inserted in the positions listed in Table 5 13 PWMAD3 to PWMADO
28. Set VDCR2 lt VD1EN gt to 1 to enable the voltage detection operation 5 Wait for 5 us or more until the voltage detection circuit becomes stable 6 Make sure that VDCR1 lt VD1SF gt is 0 7 Set VDCR2 lt VD1MOD gt to 1 to set the operation mode to generate voltage detection reset signals Note 1 VDCRI and VDCR2 are initialized by a power on reset or an external reset input only If the supply voltage VDD becomes lower than the detection voltage VDILVL in the period from release of the voltage detection reset until clearing of VDCR2 lt VDIEN gt to 0 a voltage detection reset signal is generated immediately Note JJ The voltage detection reset signals are generated continuously as long as the supply voltage VDD is lower than the detection voltage VD 1LVL Page 34 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 5 Timer Counter 5 1 Watchdog Timer
29. TBTEN gt value Page 44 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 A time base timer interrupt is generated at the first falling edge of the source clock after a time base timer interrupt request is enabled Therefore the period from the time TBTCR lt TBTEN gt is set to 1 to the time the first interrupt request occurs is shorter than the frequency period set at TBTCR lt TBTCK gt Source clock 1 TBTCR lt TBTEN gt A i l INTTBT interrupt request l lt gt Interrupt period Time base timer enable Figure 5 8 Time Base Timer Interrupt When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL mode the interrupt request will not occur at the expected timing due to synchronization of the gear clock fcgck and the low frequency clock fs It is recommended that the operation mode is ch
30. TOOPWM TOOREG Operation coe matched matched Soppan initial state initial state Table 5 11 List of Output Levels of PPGOB Pin Page 62 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use EZ SFR DARA S iMO Technology Inc Title iMQ i87 User Manual Version V1 2 b Operation Setting TOO1CR lt TOORUN gt to 1 allows the up counter to increment based on the selected source clock When a match between the internal up counter value and the value set to TOOPWM is detected the output of the PPGOB pin is reversed When TOOMOD lt TFFO gt is 0 the PPGOB pin changes from the L to H level When TOOMOD lt TFFO gt is 1 the PPGOB pin changes from the H to L level Subsequently the up counter continues counting up When a match between the up counter value and TOOREG is detected the output of the PPGOB pin is reversed again When TOOMOD lt TFFO gt is 0 the PPGOB pin changes from the H to L level When TOOMOD lt TFFO gt is 1
31. Voltage Detection Status Flag Selecting the STOP Mode Release Signal 4 3 4 Register Setting 5 Timer Counter 5 1 Watchdog Timer WDT 5 1 1 Configuration 5 1 2 Control 5 1 3 Function 5 1 3 1 5 1 3 2 543 3 5 1 3 4 5 1 3 5 5 1 3 6 5 1 3 7 Setting of Enabling Disabling the Watchdog Timer Operation Setting the Clear Time of the 8 bit Up Counter Setting the Overflow Time of the 8 bit Up Counter Setting an Overflow Detection Signal of the 8 bit Up Counter Writing the Watchdog Timer Control Codes Reading the 8 bit Up Counter Reading the Watchdog Timer Status Page 3 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use EZ SFR DARA S iMO Technology Inc Title iMQ i87 User Manual Version V1 2 5 2 Divider Output DVOB 5 2 1 Configuration 5 2 2 Control 5 2 3 Function Time Base Timer TBT 5 3 1 Configuration 5 3 2 Control 5 3 3 Function 8 bit Timer Counters 5 4 1 Configuration 5 4 2 Control 5 4 2 1 Timer Counter 00 5
32. and TO1REG in this order When data is written to the high order register the set values of the low order and high order registers become effective at the same time Set TOIMOD lt DBE1 gt to 1 to use the double buffer Setting TOO1CR lt TOIRUN gt to 1 starts the operation After the timer is started writing to TO1MOD becomes invalid Be sure to complete the required mode settings before starting the timer Make settings when TOO1CR lt TOORUN gt and lt T01RUND gt are 0 b Operation Setting TOOICR lt TOIRUN gt to 1 allows the 16 bit up counter to increment based on the selected internal source clock When a match between the up counter value and the TOO 01REG set value is detected an INTTCO1 interrupt request is generated and the up counter is cleared to Ox0000 After being cleared the up counter restarts counting Setting TOO1CR lt TOIRUN gt to 0 during the timer operation makes the up counter stop Page 65 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from suc
33. as the function output pin in the port setting while the timer is stopped the value of TOIMOD lt TFF 1 gt is output to the PPG1B pin Table 5 16 shows the list of output levels of the PPG1B pin PPG1 pin output level T T01 00PWM T01 00REG eee e Zz pam matched matched pati initial state initial state Table 5 16 List of Output Levels of PPG1B Pin b Operation Setting TOO1CR lt T01RUN gt to 1 allows the up counter to increment based on the selected source clock When a match between the up counter value and the value set to TO1 00PWM is detected the output of the PPG1B pin is reversed When TO1MOD lt TFF 1 gt is 0 the PPG1B pin changes from the L to H level When TOIMOD lt TFF I gt is 1 the PPG1B pin changes from the H to L level At this time an INTTCOO interrupt request is generated The up counter continues counting up When a match between the up counter value and the value set to T01 00REG is detected the output of the PPG1B pin is reversed again When TOIMOD lt TFFI gt is 0 the PPG1B pin changes from the H to L level When TOIMOD lt TFFI gt is 1 the PPG1B pin changes from the L to H level At this time an INTTCO1 interrupt request is generated and the up counter is cleared to Ox0000 When TO01CR lt TO1RUN2 gt is set to 0 during the timer operation the up counter is stopped and cleared to Ox0000 The PPG1B pin returns to the level selected at TOIMOD lt TFF 1 gt Whe
34. double buffer can be used for TO1 O0PWM by setting TO1MOD lt DBE1 gt The double buffer is disabled by setting TOIMOD lt DBEI gt to 0 or enabled by setting TOIMOD lt DBE1 gt to 1 1 When the Double Buffer is Enabled When write instructions are executed on TOOPWM and T01PWM in this order during the timer operation the set value is first stored in the double buffer and TO1 00PWM is not updated immediately TO1 OOPWM compares the previous set value with the up counter value When the 16 x n th overflow occurs an INTTCO1 interrupt request is generated and the double buffer set value is stored in TO1 OOPWM Subsequently the match detection is executed using a new set value When a read instruction is executed on TO1 OOPWM TOOREG the value in the double buffer the last set value is read out not the TO1 OOPWM value the currently effective value When write instructions are executed on TOOPWM and TOIPWM in this order while the timer is stopped the set value is immediately stored in both the double buffer and TO 1 00PWM 2 When the Double Buffer is Disabled When write instructions are executed on TOOPWM and TO1PWM in this order during the timer operation the set value is immediately stored in TO1 OOPWM Subsequently the match detection is executed using a new set value If the value set to T01 00PWM is Page 74 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reser
35. executed on TOOREG TO1REG and TOOPWM while the timer is stopped the set values are immediately stored in TO1 OOPWM and T01 00REG When read instructions are executed on TO1 OOPWM and T01 00REG the last value written into TO1 00REG is read out regardless of the TOOMOD lt DBE I gt setting Page 78 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Timer start Timer stop 4 TOO1CR lt TO1RUN gt TO1MOD lt TFF1 gt Sowcacock ILA 4 ULL Counter EX KAKA MON DEO E Ye MOXA KEKE Oe Counter Counter Counter Counter clear clear clear clear l Write f f WritetoTOOREG Writeb i Write to TO1REG Double buffer T01 00REG Match detection ef Write to TOOPWM write Write to TO1PWM write g Double buffer y gh Se ee 6 et ee ee ee ee BS ee ee Seen eee Ag O Coes CES E SerepTiers queers TO1 00PWM Yon i Ai PPG1 pin outpu
36. fulfill its functions due to noises and other disturbances Note 2 After IRSTSR lt FCLR gt is modified SYSCR4 should be written 0x71 Enable code for IRSTSR lt FCLR gt in NORMAL mode when fcgck Is f6 4 CGCR lt FCGCKSEL gt 00 Otherwise IRSTSR lt FCLR gt may be enabled at unexpected timing 4 1 4 7 Howto Use P10 as an External Reset To use P10 as an external reset keep P10 at the H level until the power is turned on and the warm up operation that follows reset release is finished After the warm up operation that follows power on reset is finished set P1CRO to 0 and connecta pull up resistor to P10 Then clear SYSCR3 lt RSTDIS gt to 0 and write OxB2 to SYSCR4 This enables the external reset function and makes P10 as a reset input pin To use the pin as an IO pin when it is used as a reset set SYSCR3 lt RSTDIS gt to 1 and write OxB2 to SYSCR4 This enables the IO function and makes the pin usable as an open drain IO pin Note 1 Ifyou switch the external reset input pin to a port or switch the pin used as a port to the external reset input pin do it when the pin Is stabilized at the H level Switching the pin function when the L level is input may cause a reset Note JJ If the external reset input is used as a port the statement which clears SYSCR3 lt RSTDIS gt to 0 is not written ina program By this abnormal execution of program the external reset input set as a port may be changed as the external
37. is selected and the supply voltage VDD is equal to or higher than the detection voltage VDILVL STOP mode cannot be activated Setting VDCR2 lt SRSS gt to 00 allows STOP mode to be released depending on the state of the STOP pin Setting it to 01 allows STOP mode to be released when the supply voltage VDD becomes equal to or higher than the detection voltage VD1ILVL Setting it to 10 allows STOP mode to be released depending on the state of the STOP pin or when the supply voltage VDD becomes equal to or higher than the detection voltage VD1LVL Note 1J After STOP mode is released by a voltage detection STOP mode release signal the interrupt latch becomes 1 If it is undesirable to accept an interrupt after STOP mode is released disable interrupts before STOP mode is activated In addition clear the interrupt latch before enabling interrupts after STOP mode is released Note 2 If the supply voltage VDD becomes equal to or higher than the detection voltage VDILVL within 1 machine cycle after SYSCRI lt STOP gt is set to 1 and STOP mode is activated STOP mode is not released Note 3 When the voltage detection interrupt request signal of the voltage detection circuit is used as the STOP mode release signal take into account sudden fluctuations in the supply voltage VDD and changes near the detection voltage VDILVL in setting the detection voltage VD 1ILVL and the warm up time VDD level 1 I i i I Detec
38. latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 overflow time of the 8 bit up counter If the operation for releasing the 8 bit up counter is attempted outside the clear time a watchdog timer interrupt request signal occurs At this time the watchdog timer is not cleared but continues counting If the 8 bit up counter is not cleared within the clear time a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs due to the overflow depending on the WDCTR lt WDTOUT gt setting 5 1 3 3 Setting the Overflow Time of the 8 bit Up Counter WDCTR lt WDTT gt sets the overflow time of the 8 bit up counter When the 8 bit up counter overflows a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs depending on the WDCTR lt WDTOUT gt setting If the watchdog timer interrupt request signal is selected as the malfunction detection signal the watchdog counter continues counting even after the overflow has occurred The watchdog timer temporarily stops counting up in the STOP mode including warm up or in the IDLE SLEEP mode and
39. of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use ez TAR DARAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 To disable the watchdog timer operation clear WDCTR lt WDTEN gt to 0 and write OxB1 into WDCDER Disabling the watchdog timer operation clears the 8 bit up counter to 0 Note If the overflow of the 8 bit up counter occurs at the same time as OxB 1 disable code is written into WDCDR with WDCTR lt WDTEN gt set at 1 the watchdog timer operation is disabled preferentially and the overflow detection is not executed To re enable the watchdog timer operation set WDCTR lt WDTEN gt to 1 There is no need to write a control code into WDCDR Watchdog timer source clock a Aee cree ee eer ees amp bit up counter value 00H MH xX FFH 00H WDCTR lt WDTEN gt _ WDCTR lt WDTEN gt Overflow time Interrupt request signal lt 1 clock max gt l Figure 5 2 WDCTR lt WDTEN gt Set Timing and Overflow Time Note The amp bit u
40. on TOOPWM TOOREG while the timer is stopped the set value is immediately stored in both the double buffer and TOOPWM TOOREG Page 63 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMQ i87 User Manual Version V1 2 2 When the Double Buffer is Disabled When a write instruction is executed on TOOPWM TOOREG during the timer operation the set value is immediately stored in TOOPWM TOOREG Subsequently the match detection is executed using a new set value If the value set to TOOPWM TOOREG is smaller than the up counter value the PPGOB pin is not reversed until the up counter overflows and a match detection is executed using a new set value If the value set to TOOPWM TOOREG is equal to the up counter value the match detection is executed immediately after data is written into TOOPWM TOOREG Therefore the timing of changing the PPGOB pin may not be an integral multiple of the source clock Figure 5 18
41. request interval may be longer than the selected time If the value set to T01 00REG is equal to the up counter value the match detection is executed immediately after data is written into T0O1 OOREG Therefore the interrupt request interval may not be an integral multiple of the source clock If these are problems enable the double buffer When write instructions are executed on TOOREG and TO1REG in this order while the timer is stopped the set value is immediately stored in TO1 OOREG When a read instruction is executed on T01 00REG the last value written into TO1 OOREG is read out regardless of the TOOMOD lt DBE I gt setting Page 66 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 Source clock Hz Resolution Maximum time setting TO1MOD NORMAL 1 2 or IDLE 1 2 mode lt TCK1 gt SLOW 1 2 or _ D _ SYSCR1 lt DV9CK gt SYSCR1 lt DV9CK gt SLEEP1 mode fegck 8MHz fs 3
42. reset input at unexpected timing Note 3J After SYSCR lt RSTDIS gt is modified SYSCR4 should be written OxB2 Enable code for SYSCR lt RSTDIS gt in NORMALI mode when fcgck Is f6 4 CGCR lt FCGCKSEL gt 00 Otherwise SYSCR3 lt RSTDIS gt may be enabled at unexpected timing 4 2 Power on Reset Circuit The power on reset circuit generates a reset when the power is turned on When the supply voltage is lower than the detection voltage of the power on reset circuit a power on reset signal is generated 4 2 1 Configuration The power on reset circuit consists of a reference voltage generation circuit and a comparator The supply voltage divided by ladder resistor is compared with the voltage generated by the reference voltage generation circuit by the comparator Page 26 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version Comparator 4 Reference voltage generation c
43. restarts counting up after the STOP IDLE SLEEP mode is released To prevent the 8 bit up counter from overflowing immediately after the STOP IDLE SLEEP mode is released it is recommended to clear the 8 bit up counter before the operation mode is changed Watchdog timer overflow time s NORMAL mode DV9CK 1 32 77 m 62 50 m 62 50 m 131 1m 250 0 m 250 0 m 524 3 m 1 000 1 000 2 097 4 000 4 000 Table 5 1 Watchdog Timer Overflow Time fcgck 8 0 MHz fs 32 768 KHz Note The amp bit up counter source clock operates out of synchronization with WDCTR lt WDTEN gt Therefore the first overflow time of the 8 amp bit up counter after WDCTR lt WDTEN gt Is set to 1 may get shorter by a maximum of 1 source Clock The amp bit up counter must be cleared within a period of the overflow time minus 1 source clock cycle 5 1 3 4 Setting an Overflow Detection Signal of the 8 bit Up Counter WDCTR lt WDTOUT gt selects a signal to be generated when the overflow of the 8 bit up counter is detected a When Watchdog Timer Interrupt Request Signal is Selected as WDCTR lt WDTOUT gt is 0 Releasing WDCTR lt WDTOUT gt to 0 causes a watchdog timer interrupt request signal to occur when the 8 bit up counter overflows Page 39 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without pr
44. risk and the buyer agrees to defend indemnify and hold harmless IMQ from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 3 Clear VDCR2 lt VD1IMOD gt to 0 to set the operation mode to generate voltage detection interrupt request signals 4 Set VDCR2 lt VD1EN gt to 1 to enable the voltage detection operation 5 Wait for 5 us or more until the voltage detection circuit becomes stable 6 Make sure that VDCR1 lt VD1SF gt is 0 7 Clear the voltage detection circuit interrupt latch to 0 and set the interrupt enable flag to 1 to enable interrupts Note If the set value of detection voltage VDILVL is close to the supply voltage VDD voltage detection request signals may be generated frequently At the return from the voltage detection interrupt processing execute appropriate walt processing depending on fluctuations in the system power supply and clear the interrupt latch 2 When the Operation Mode is Set to Generate Voltage Detection Reset Signals When the operation mode is set to generate voltage detection reset signals make the following setting 1 Clear the voltage detection circuit interrupt enable flag to 0 2 Set the detection voltage at VDCR3 lt VDILVL gt 3 Clear VDCR2 lt VD1IMOD gt to 0 to set the operation mode to generate voltage detection interrupt request signals 4
45. the double buffer and TOOPWM is not updated immediately TOOPWM compares the previous set value with the up counter value When the 2 x n th overflow occurs an INTTCOO interrupt request is generated and the double buffer set value is stored in TOOPWM Subsequently the match detection is executed using a new set value When a read instruction is executed on TOOPWM the value in the double buffer the last set value is read out not the TOOPWM value the currently effective value When a write instruction is executed on TOOPWM while the timer is stopped the set value is immediately stored in both the double buffer and TOOPWM 2 When the Double Buffer is Disabled When a write instruction is executed on TOOPWM during the timer operation the set value is immediately stored in TOOPWM Subsequently the match detection is executed using a new Set value If the value set to TOOPWM is smaller than the up counter value the PWMOB pinis not reversed until the up counter overflows and match detection is executed using a new set value If the value set to TOOPWM is equal to the up counter value the match detection is executed immediately after data is written into TOOPWM Therefore the timing of changing the PWMOB pin may not be an integral multiple of the source clock Figure 5 15 Similarly if TOOPWM is set during the additional pulse output the timing of changing the PWMOB pin may not be an integral multiple of the source clock If these are probl
46. timer is stopped Writing data into TOOMOD Is invalid during the timer operation Note 3J In the 82 bit timer event modes the TFFO setting Is invalid In this mode when the PWMOB and PPGOB pins are set as the function output pins in the port setting the pins always output the H level Note 4 When EINO is set to 1 and the external clock input is selected as the source clock the TCKO setting is ignored Note 5 When the TOOICR lt TCAS gt bit is 1 timer 00 operates in the 16 bit mode The TOOMOD setting is invalid and timer 00 cannot be used independently in this mode When the PWMOB and PPGOB pins are set to the function output pins in the port setting the pins always output the H level Note 6 When the 16 bit mode is selected at TOO1CR lt TCAS gt the timer start is controlled at TOOICR lt TOIRUN gt Timer 00 is not started by writing data into TOOICR lt TOORUN gt 5 4 2 2 Timer Counter 01 Timer counter 01 is controlled by timer counter 01 mode register TOIMOD and two 8 bit timer registers TOIREG and TO1PWM Timer Register 01 TOIREG 15 0x0027 Bit Symbol Read Write After reset Timer Register 01 TOIPWM 0x0029 Bit Symbol Read Write After reset 7 Note For the configuration of TOIPWM in the 8 bit and 12 bit PWM modes refer to 5 4 4 3 amp bit pulse width modulation PWM output mode and 5 4 4 7 12 bit pul
47. value is detected an INTTCOO interrupt request is generated and the up counter is cleared to 0x00 After being cleared the up counter restarts counting Setting TOOTCR lt TOORUN gt to 0 during the timer operation makes the up counter stop counting and be cleared to 0x00 c Double Buffer The double buffer can be used for TOOREG by setting TOOMOD lt DBEO gt The double buffer is disabled by setting TOOMOD lt DBEO gt to 0 or enabled by setting TOOMOD lt DBEO gt to 1 Page 52 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 1 When the Double Buffer is Enabled When a write instruction is executed on TOOREG during the timer operation the set value is initially stored in the double buffer and TOOREG is not immediately updated TOOREG compares the previous set value with the up counter value When the values match an INTTCOO interrupt request is generated and t
48. 1 When STOP mode is started TOORUN and TOIRUN are cleared to 0 and the timers stop Set TOOICR again to use timers 00 and 01 after STOP mode is released Note 2 When a read instruction is executed on TOOICR bits 7 to 4 are read as O Note 3 When OUTAND is 1 output is obtained from the PWM1B and PPG1B pins only There is no timer output to the PWMOB and PPGOB pins If the PWMOB and PPGOB pins are set as the function output pins in the port setting the pins always output H Note 4 OUTAND and TCAS can be changed only when both TCOIRUN and TCOORUN are 0 When either TCOIRUN or TCOORUN is 1 or both are 1 the register values remain unchanged by executing write instructions on OUTAND and TCAS OUTAND and TCAS can be changed at the same time as TCOIRUN and TCOORUN are changed from 0 to 1 5 4 2 4 Operation Modes and Usable Source Clocks The operation modes of the 8 bit timers and the usable source clocks are listed below 8 bit timer modes Operation mode 8 bit timer fegck 2 9 or fs 2 fegck 2 TCOi pin input 8 bit event counter 8 bit PWM 8 bit PPG 16 bit timer modes 16 bit timer 16 bit event counter 12 bit PWM 16 bit PPG Table 5 6 Operation Modes and Usable Source Clocks NORMAL1 2 and IDLE 1 2 Modes Page The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the i
49. 1 gt to 0 and select the clock at TOIMOD lt TCK1 gt To use an external clock as the source clock set TOIMOD lt EIN1 gt to 1 Set TOIMOD lt DBE I gt to 1 to use the double buffer Setting TOOICR lt TO1RUN gt to 1 starts the operation After the timer is started writing to TOIMOD becomes invalid Be sure to complete the required mode settings before starting the timer Make settings when TOO1CR lt TOORUN gt and lt T01RUN gt are 0 Set the count value to be used for the match detection and the additional pulse value as a 12 bit value at the timer registers TOOPW M and TO1PWM Set bits 11 to 8 of the 12 bit value at the lower 4 bits of TOIPWM and set bits 7 to 0 at TOOPWM Refer to the following table for the register configuration Hereinafter the 12 bit value specified by the combined setting of TOOPWM and TOIPWM is indicated as TO1 OOPWM The timer register settings are reflected on the double buffer or TO1 OOPWM when a write instruction is executed on TO1PWM Be sure to execute the write instructions on TOOPWM and TO1PWM in this order When data is written to the high order register the set values of the low order and high order registers become effective at the same time Timer Register 00 TOOPWM 0x0028 7 2 7 l 2 Bit Symbol PWMAD3 PWMAD2 PWMAD1 PWMADO Read Write R W R W R W R W After reset 1 1 1 1 Timer Register 01 TOIPWM 0x0029 Bit Symbol Read Write
50. 2 768KHz fegck 8MHz fs 32 768KHz g r fegck 2 fegck 2 9 fs 23 fegek 2 fegek 2 fegck 2 fegck 2 524 3ms fegck 2 fegck 2 131 1ms fegck 2 fegck 2 fegck 2 fegck 2 Table 5 12 16 bit Timer Mode Resolution and Maximum Time Setting Page 67 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMQ i87 User Manual Version V1 2 Timer start Timer stop TO001CR lt TO1RUN gt TO1MOD lt DBE1 gt Source clock Counter Write to TOOREG Write to TO1REG T01 00REG A A INTTCO1 interrupt Reflected by writing to TO1REG meaa Reflected by writing to TOIREG When the double buffer is disabled T01MOD lt DBE1 gt 0 4 Timer start TO01CR lt TO1RUN gt TO1MOD lt DBE1 gt Source clock i m Counter p Hires X 4 0 A Counter clear Write to TOOREG Write to TO1TREG Double buffer T01 00REG Match detection Reflected si
51. 26 0x0028 Ox002A TOOICR POFFCRO Timer counter 01 Higher TOIREG TOIPWM TEOIMOD R Sere g Ox0027 Ox0029 Ox002B Table 5 4 SFR Address Assignment 16 bit mode Timer Input Pin PWM Output Pin Timer counter 00 TCOO pin PWMOB pin Timer counter 01 TCO1 pin PWM1B pin Table 5 5 Pin Names 5 4 1 Configuration intemal bus Reading and writing Reading and Reading and Reading and of TOOREG writing of writing of writing of TOIREG TOIPWM fo tt Double buffer Double buffer ty AE Cae aL TOIREG TOIPWM Tooo pin input J p fegek 2 or fs 2 gt fogck 210 or fs 23 gt fogek 2 gt fogck 2 gt fegck 2 gt ftgek 2 gt gt fogek 2 gt fc or fs 2 gt TCO1 pin input hy fogck 2 or fsi2 gt fogek 2 or f2 gt fogck 2 gt fogek 2 gt fegck 2 _ gt fogok 22 gt fogck 2 gt fc or fs 27 gt ra ntmooor lt i ant FPG moce a Sty o X gt gt Teo y Timerevent A z iz mterrupt request count modes 3 SD2 PWM mode court modes gt gt INnTTCOO 12 40 PWM mode t niemupt request Soi PAM mode Overton 1th Pwu mode 8 bit up counter rannoomr Intemal bus Figure 5 9 8 bit Timer Counters 00 and 01 Page 46 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the
52. 87 User Manual Version V1 2 3 7 2 Control Key on wakeup control registers KWUCRO and KWUCR1I can be configured to designate the key on wakeup pins KWI7 through KWIO as STOP mode release pins and to specify the STOP mode release levels of each of these designated pins Key on Wakeup Control Register 0 KWUCRO OxOFC4 z 6 gt E Bit Symbol KW2LE KW2EN Read Write R W R W After reset 0 0 Low level KW3LE STOP mode release level of KWI3 pin wae High level Disable KW3EN Input enable disable control of KWI3 pin Enable Low level KW2LE STOP mode release level of KWI2 pin ae High level Disable KW2EN Input enable disable control of KWI2 pin Enable Low level KW ILE STOP mode release level of KWI1 pin oe High level Disable KWI1EN Input enable disable control of KWI1 pin Enable Low level KWOLE STOP mode release level of KWIO pin ote High level Disable KWOEN Input enable disable control of KWIO pin Enable Key on Wakeup Control Register 1 KWUCRI OxOFC5 7 6 2 f E Bit Symbol KW6LE KWG6EN KW5EN Read Write R W R W R W After reset 0 0 0 Low level KW7LE STOP mode release level of KWI7 pin oe High level Disable KW7EN Input enable disable control of KWIZ pin Enable Low level KW6LE STOP mode rele
53. B of the result of the last arithmetic operation is one Otherwise the SF bit is cleared to 0 3 5 5 Overflow Flag VF The VF bit is set to 1 when there is an overflow as a result of an arithmetic operation Otherwise the VF bit is cleared to 0 For example the VF bit is set when adding two positive numbers gives a negative result or when adding two negative numbers gives a positive result Page 13 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use ez TAR DARAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 3 5 6 Jump Status Flag JF The JF bit is usually set to 1 and is cleared to 0 or hold a carry according to a specific instruction The JF bit is used as a condition for conditional jump instructions JR T F a and JRS T F a where T and F represent true and false condition codes Example The assumptions are WA register Ox219A HL register OxOOC5 Data Memory location at OxO00C5 OxD7 CF 1 HF 0 SF
54. IMQ Your First and Best MCU i87 User Manual V1 2 Page 1 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Contents 1 Change History 2 Overview of iMQ i87 User Manual 3 Central Processing Unit CPU 3 1 General Concept 3 2 Stack Area and Stack Pointer 3 2 1 Stack Area 3 2 2 Stack Pointer Program Counter PC 3 3 1 Program Counter PC 3 3 2 Effects of Jump Instructions on the PC Value General Purpose Register 3 4 1 A Registers 3 4 2 C Registers 3 4 3 DE Registers 3 4 4 HL Registers 3 4 5 16 Bit General Purpose Registers IX IY Program Status Word PSW 3 5 1 Zero Flag ZF 3 5 2 Carry Flag CF 3 5 3 Half Carry Flag HF 3 5 4 Sign Flag SF 3 5 5 Overflow Flag VF 3 5 6 Jump Status Flag JF 3 5 7 Register Bank Selector RBS Low Power Consumption Function for Peripherals Key on Wakeup KWU 3 7 1 Configuration 3 7 2 Control 3 7 3 Function 3 7 3 1 Set
55. MO Technology Inc Title iMQ i87 User Manual Version V1 2 Change History Version Approved Description Issuer Date 2011 09 23 243207 1 Stack Area Point Program Counter amp CPU HR ERRIA 2011 10 14 3 1 General Concept 2 1 Registers 2 Program Status Word PSW F amp fi E wT ARE 2011 12 06 l Functional Description AX CPU Reset Function 4 Timer Counter 6 UDEA Z1E Figure 4 1 P 887 MOSS 44 m ORBEA External Reset Input Z zt 81E 4 1 2 Controls Z SYSCR4 HFR ARN 14 5 3 2 Controli TBTCR 4232 TBTCK 110 H DV9CK 1 FZ 38 A fs 2 AA fs 2 E ff 5 4 2 3 Z POFFCRO Low Power Consumption Register OH GRAB p erg INTTOO 8 INTTOI PIAA INTTCOO 4 INTTCO1 Wi 5 20 5 23 45 24 INTTCOO interrupt requests 1ER INTTCO1 interrupt request 4 3 4 2 General Purpose Register 1 P HIREK IMO IC J BE A 1 48 Bank 0 LEY MQ8602 SL 4 3 2 Controls P VDCR3 B28 Z LVD REE LL RPGR RIAGR 4 3 3 Functions ZAR LAE IMO IC BERRI 5 2 3 Function Z4 EAMG te aR F Table 5 6 4 Table 5 7 2012 05 18 2012 11 27 FA FA 2013 02 01 W UW We FA Page 5 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your
56. NTOEN Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable INT5EN INT5 Control INT4EN INT4 Control INT3EN INT3 Control INT2EN INT2 Control INTIEN INT1 Control INTOEN INTO Control 3 7 Key on Wakeup KWU The key on wakeup is a function for releasing the STOP mode at the STOPB pin or at pins KWI7 through KWIO 3 7 1 Configuration SYSCR1 lt RELM gt Stop mode Y S 0 release signal 1 to be released fsetio 1 Selector OFC4H 76543210 KWUCRO _ i KWUCR1 _ OFCSH 76543210 Figure 3 6 Key on Wakeup Circuit Page 16 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i
57. OG tay clear aad Write s 0011 j Write r 7 ne irh dear write m 0001 Write k Double buffer ib 0011 Y km 0001 SS ee ee ee PWMAD3 to 0 0001 E n O S E S O A PWMDUTY X km EEEE EEN ENA eee GEROA ee y T ERA INTTCO1 interrupt request im Duty pulse 256 counts H 2 H 2 H Cycle 1 Cycle 2 Cycle 9 Cycle 16 Cycle 17 When the double buffer is enabled T01MOD lt DBE1 gt 1 Figure 5 23 12 bit PWM Mode Timing Chart Page 75 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMQ devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 8 bit cycle Source clock Hz Resolution A period x 16 TOM is Sei NORMAL1 2 or IDLE1 2 mode lt TCK1 gt SLOW1 2 or SYSCR1 lt DV9CK gt SYSCR1 lt DVSCK gt SLEEP1 mode GA Rin fegck 8MHz fs 32 768KHz fcgck 8MHz fs 32 768KHzZ 65 5ms 125ms m11 z4 fegck 2 fs 2 1048 6ms 2000ms
58. PU loads the reset vector stored in the vector table at OXxFFFF and OxFFFE in MCU mode into the PC thus the program can start at an arbitrary address The iMO i87 Series is pipelined that is CPU instructions are pre fetched Therefore the PC points to an address two bytes after the address of the instruction being executed For example the PC contains 0xC125 while the single byte instruction stored at OxC123 is being executed MSB LSB 15 141312111098 76543210 Program counter PC PCH PCL Instruction execution cycle a Program counter b PC vs Instruction execution cycle Figure 3 3 Program Counter 3 3 2 Effects of Jump Instructions on the PC Value There are relative and absolute jump instructions The jump destination is limited within the code area a jump cannot occur to the data area The following describes the effects of jump instructions on the PC value 1 Relative Jump Instruction with a 5 bit Displacement JRS cc 2 d When the memory location at OxE8C4 contains the instruction JRS T 2 0x08 if JF 1 the PC is incremented by 0x08 i e a jump occurs to the address OxE8CE The PC points to an address two bytes after the address of the instruction being executed In this example the PC contains OxE8C4 2 OxE8C6 before the jump Relative Jump Instructions with an 8 bit Displacement JR cc 2 d JRcc 3 d When the memory location at OxE8C4 contains the instruction JR Z 2 0x80
59. R2 lt VD1EN gt Write 0 to VDCR1 lt VD1F gt VDCR1 lt VD1F gt VDCR1 lt VD1SF gt i The flag is not set because VDCR2 lt VD1EN gt is 0 Figure 4 8 Changes in the Voltage Detection Flag and the Voltage Detection Status Flag 4 3 3 5 Selecting the STOP Mode Release Signal By setting VDCR2 lt SRSS gt to select the voltage detection STOP mode release signal as the STOP mode release signal STOP mode can be released when the supply voltage VDD becomes equal to or higher than the detection voltage VDILVL To use this function set VDCR2 lt VDIMOD gt to 0 and set the operation mode to generate voltage detection interrupt request signals In addition before the operation is switched to STOP mode clear SYSCR1 lt RELM gt to 0 and select the edge release mode Page 32 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMQ from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 If the level release mode
60. TTCOO interrupt an interrupt l Reflected by writing to TO1REG When the double buffer is enabled T01MOD lt DBE1 gt 1 Figure 5 20 16 bit Event Counter Mode Timing Chart 5 4 4 7 12 bit Pulse Width Modulation PWM Output Mode In the 12 bit PWM output mode TCOO and TCO are cascaded to output the pulse width modulated pulses with a resolution of 8 bits An additional pulse of 4 bits can be inserted which enables PWM output with a resolution nearly equivalent to 12 bits a Setting Setting TOO1CR lt TCAS gt to 1 connects TCOO and TCO1 and activates the 16 bit timer mode All the settings of TCOO are ignored and those of TCO are effective in the 16 bit timer mode Page 70 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMQ from any and all damages claims suits or expenses resulting from such use EZ SFR DARA S iMO Technology Inc Title iMQ i87 User Manual Version V1 2 The 12 bit PWM mode is selected by setting TOIMOD lt TCM1 gt to 10 To use the internal clock as the source clock set TOIMOD lt EIN
61. V9ICK 1 SLEEP 1 2 mode fogck 222 fs 2 gt fs 2 gt fegck 229 fs 2 3 fs 2 3 Select the time base timer interrupt fegck 2 5 fs 28 Reserved TBTCK frequency Unit Hz fegck 2 3 fs 2 Reserved fegck 2 2 fs 2 Reserved fegck 2 fs 24 Reserved fegck 2 0 fs 23 Reserved fegck 28 Reserved Reserved Note 1 fogck Gear clock Hz fs Low frequency clock HZ Note 2 When the operation is changed to the STOP mode TBTCR lt TBTEN gt is cleared to O and TBTCR lt TBTCK gt maintains the value Note 3J TBTCR lt TBTCkK gt should be set when TBTCR lt TBTEN gt Is 0 Note 4 When SYSCRI lt DV9CK gt is 1 in the NORMAL 1 2 or IDLE 1 2 mode the interrupt request is subject to some fluctuations to synchronize fs and fcgck Note 5J Bits 7 to 4 of TBTCR are read as 0 5 3 3 Function Select the source clock frequency for the time base timer by TBTCR lt TBTCK gt TBTCR lt TBTCK gt should be changed when TBTCR lt TBTEN gt is 0 Otherwise the INTTBT interrupt request is generated at unexpected timing Setting TBTCR lt TBTEN gt to 1 causes interrupt request signals to occur at the falling edge of the source clock When TBTCR lt TBTEN gt is cleared to 0 no interrupt request signal will occur When the operation is changed to the STOP mode TBTCR lt TBTEN gt is cleared to 0 The source clock of the time base timer operates regardless of the TBTCR lt
62. anged when TBTCR lt TBTEN gt is 0 Time base timer interrupt frequency Hz NORMAL 1 2 IDLE1 2 mode NORMAL 1 2 IDLE 1 2 mode SLOW1 2 SLEEP 1 2 mode DV9CK 0 DV9CK 1 1 91 1 7 63 4 244 14 Reserved 976 56 Reserved 1953 13 Reserved 3906 25 Reserved 7812 5 Reserved Table 5 3 Time Base Timer Interrupt Frequency Example fcgck 8 0 MHz fs 32 768 kHz 5 4 8 bit Timer Counters The MQ8S MCU contains 2 channels of high performance 8 bit timer counters 00 and 01 TCO Each timer can be used for time measurement and pulse output with a prescribed width Two 8 bit timer counters are cascadable to form a 16 bit timer Page 45 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAG iMQ Technology Inc Title iMOi87 User Manual Version V1 2 TOxREG TOxPWM TCOxMOD TOxxCR Low power Address Address Address Address consumption register Timer co rter Lower TOOREG TOOPWM TCOOMOD Ox00
63. ase level of KWI6 pin sae High level Disable KW6EN Input enable disable control of KWI6 pin Enable Low level KW5LE STOP mode release level of KWI5 pin aan High level Disable KW5EN Input enable disable control of KWI5 pin Enable Low level KW4LE STOP mode release level of KWI4 pin nae High level Disable KW4EN Input enable disable control of KW14 pin Enable Page 17 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 3 7 3 Function By using the key on wakeup function the STOP mode can be released at a STOPB pin or at KWim pin m O through 7 After resetting the STOPB pin is the only STOP mode release pin To designate the KWIm pin as a STOP mode release pin it is necessary to configure the Key on wakeup control register KWUCRn n 0 or 1 Because the STOPB pin lacks a function for disabling inputs
64. can be combined to specify the number of times of inserting the additional pulses in 16 cycles to any number from 1 to 16 Examples of inserting additional pulses are shown in Figure 5 21 Cycles in which additional pulses are inserted among e 1to16 PWMADO 1 PWMAD1 1 oo 13 PWMAD2 1 3 7 11 15 PWMAD3 1 2 4 6 8 10 12 14 16 Table 5 13 Cycles in Which Additional Pulses Are Inserted Additional Timer start pulse Timer stop K PWM1 pin output TFF1 1 PWM1 pin output TFF1 0 di INTTCOO interrupt request eono INTTCO1 interrupt request d an eee See nana banana nn E YL Y gt oo Cycle wn 10 N w A a wn n N h When PWMAD1 1 Additional Additional Additional Additional Additional Timer start pulse pulse pulse pulse pulse Timer stop PWM1 pin output ot TFF1 1 FF PWM1 pin output PLL TFF1 0 i l s N y Li _ i INTTCOO interrupt request INTTCO1 interrupt request 4 SSL peed Lee H i i i 1 i i T H 1 i i i 1 1 i i T i i 1 r Cycle 5 6 7 10 When PWMADO 1 and PWMAD2 Figure 5 21 Examples of Inserting Additional Pulses Page 72 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves th
65. cillation enabled Oscillation enabled Oscillation disabled Oscillation disabled Oo o o Disabled or enabled Disabled or enabled Refer to the SFR map Refer to the SFR map Table 4 1 Initialization of Built in Hardware by Reset Operation and Its Status after Release Page 23 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 Note IJ The voltage detection circuits are disabled by an external reset input or power on reset only Note 2 HiZ indicates high impedance 4 1 4 Reset Signal Generating Factors Reset signals are generated by each factor as follows 4 1 4 1 External Reset Input RESETB Pin Input Port P10 is also used as the RESETB pin and it serves as the RESETB pin after the power is turned on Recommended operating voltage Reset time RESET pin r gt During reset Warm up operation CPU and peripheral circuits CPU peripheral circuits reset
66. clock at TOOMOD lt TCKO gt To use an external clock as the source clock set TOOMOD lt EINO gt to 1 Set the count value to be used for the match detection and the additional pulse value at the PWM register TOOPWM Set TOOMOD lt DBEO gt to 1 to use the double buffer Setting TOO01CR lt TOORUN gt to 1 starts the operation After the timer is started writing to TOOMOD becomes invalid Be sure to complete the required mode settings before starting the timer In the 8 bit PWM mode the TOOPWM register is configured as follows Timer Register 00 TOOPWM 7 4 0x0028 Bit Symbol PWMDUTY Read Write R W After reset 1 Page 56 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use ez TAR DARAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 Timer Register 01 TOIPWM 0x0029 4 Bit Symbol PWMDUTY Read Write R W After reset 1
67. ct specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 4 Timer start Timer stop TOO1CR lt TOORUN gt TCOO pin input AA AARAA RY Counter o XiX2XaX 4 X yA XKOX 1 EB 3X Xn o X1X2X 0 A Counter clear A Counter clear Write to TOOREG Write m Write n Match detection Maich defection TOOREG Y m Xn j A 1 A INTTCOO interrupt request Reflected by writing to TOOREG X Reflected by writing to TOOREG When the double buffer is disabled TOOMOD lt DBED 0 Figure 5 12 Event Counter Mode Timing Chart 5 4 4 3 8 bit Pulse Width Modulation PWM Output Mode The pulse width modulated pulses with a resolution of 7 bits are output in the 8 bit PWM mode An additional pulse can be added to the 2 x n th duty pulse This enables PWM output with a resolution nearly equivalent to 8 bits n 1 2 3 The operation of TCOO is described below and the same applies to the operation of TCO1 a Setting TCOO is put into the 8 bit PWM mode by setting TOOMOD lt TCMO gt to 10 and TOOICR lt TCAS gt to 0 To use the internal clock as the source clock set TOOMOD lt EINO gt to 0 and select the
68. d by ddaring the 8 bit up couhter outside the clear tinje Reading of WDST Interrupt reqy est signal generated by the overflow of fie amp bitup counter T i n Watchdog timer interrupt request signal WDST lt WINTST1 gt WDST lt WINTST2 gt Figure 5 4 Changes in the Watchdog Timer Status 5 2 Divider Output DVOB This function outputs approximately 50 duty pulses that can be used to drive the piezoelectric buzzer or other device 5 2 1 Configuration fegck 2 2 or fs 2 fegck 2 or fs 24 fegck 2 or fs 23 fegck 2 Selector Figure 5 5 Divider Output Page 41 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 5 2 2 Control The divider output is controlled by the divider output control register DVOCR Divider Output Control Register DVOCR 7 6 0x0038 Bit Symbol Read Write After reset
69. d upon reset causing Register Bank 0 to be selected 3 5 1 Zero Flag ZF The ZF bit is set to 1 when the result of the last ALU instruction or the operand of the last load store instruction is 0x00 for 8 bit ALU or load store operations or Ox0000 for 16 bit ALU operations The ZF bit is also set to 1 when the value of the bit specified by the last bit manipulation instruction is zero otherwise the ZF bit is cleared to 0 Also the ZF bit is set when the high order eight bits of the product of the last multiply instruction or the remainder of the last divide instruction is 0x00 otherwise the ZF bit is cleared to 0 3 5 2 Carry Flag CF The CF bit contains a carry from an addition or a borrow as a result of subtraction The CF bit is also set to 1 when the divisor of the last divide instruction is 0x00 divided by zero error or the quotient is equal to or greater than 0x100 quotient overflow error Shift and rotate instructions operate with and through the CF bit For bit manipulation instructions the CF bit serves as a single bit Boolean accumulator The CF bit can be set cleared and complemented via instructions 3 5 3 Half Carry Flag HF The HF bit contains a carry to bit 4 or a borrow from bit 4 as a result of an 8 bit addition or subtraction The HF bit is used for binary coded decimal BCD addition subtraction and correction DAA r and DASr 3 5 4 Sign Flag SF The SF bit is set to 1 when the most significant bit MS
70. e by setting TOOMOD lt TCMO gt to 00 T001CR lt TCAS gt to 0 and TOOMOD lt EINO gt to 1 Set the count value to be used for the match detection as an 8 bit value at the timer register TOOREG Set TOOMOD lt DBEO gt to 1 to use the double buffer Setting TOOICR lt TOORUN gt to 1 starts the operation After the timer is started writing to TOOMOD becomes invalid Be sure to complete the required mode settings before starting the timer b Operation Setting TOO1CR lt TOORUN gt to 1 allows the 8 bit up counter to increment at the falling edge of the TCOO pin When a match between the up counter value and the TOOREG set value is detected an INTTCOO interrupt request is generated and the up counter is cleared to 0x00 After being cleared the up counter restarts counting Setting TO01CR lt TOORUN gt to 0 during the timer operation makes the up counter stop counting and be cleared to 0x00 The maximum frequency to be supplied is fegck 2 Hz in NORMAL1 2 or IDLE 1 2 mode or fs 2 Hz in SLOW1 2 or SLEEP1 mode and a pulse width of two machine cycles or more is required at both the H and L levels c Double Buffer Refer to 5 4 4 1 c Double Buffer Page 55 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of produ
71. e right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 Set the initial state of the PWM1B pin at TOIMOD lt TFFI gt Setting TOIMOD lt TFF1 gt to 0 selects the L level as the initial state of the PWM1B pin Setting TOIMOD lt TFF1 gt to 1 selects the H level as the initial state of the PWM1B pin If the PWM1B pin is set as the function output pin in the port setting while the timer is stopped the value of TOIMOD lt TFF1 gt is output to the PWM1B pin Table 5 14 shows the list of output levels of the PWM 1B pin PWM 1pin output level PWMDUTY Before the start wistchod Operation of operation Overflow stopped cas after the addi oy do initial state initial state tional pulse Table 5 14 List of Output Levels of PWM 1B Pin b Operation Setting TOO1CR lt T01RUN gt to 1 allows the up counter to increment based on the selected source clock When a match between the lower 8 bits of the up counter value and the value set to PWMDUTY is detected the output of the PWM1B
72. ees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 WDST lt WDTST gt is set to 1 when the watchdog timer operation is enabled and it is cleared to 0 when the watchdog timer operation is disabled WDST lt WINTST2 gt is set to 1 when a watchdog timer interrupt request signal occurs due to the overflow of the 8 bit up counter WDST lt WINTST1 gt is set to 1 when a watchdog timer interrupt request signal occurs due to the operation for releasing the 8 bit up counter outside the clear time You can know which factor has caused a watchdog timer interrupt request signal by reading WDST lt WINTST2 gt and WDST lt WINTST 1 gt in the watchdog timer interrupt service routine WDST lt WINTST2 gt and WDST lt WINTST 1 gt are cleared to 0 when WDST is read If WDST is read at the same time as the condition for turning WDST lt WINTST2 gt or WDST lt WINTSTI gt to 1 is satisfied WDST lt WINTST2 gt or WDST lt WINTST1 gt is set to 1 rather than being cleared 8 bit up counter value FFHXOOHXOTHX ser XaarX TREO m BrNCOX FFHXOOHXO1HX l When WDCTR lt WDTW2 is 10 _ Outside the clear time gt ___ Clear time gt Writing of 4EH clear code I T n Interrupt request signal generatg
73. ems enable the double buffer When a write instruction is executed on TOOPWM while the timer is stopped the set value is immediately stored in TOOPWM Page 60 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 TOOMOD lt DBEO gt Source clock Counter Write to TOOPWM TOOPWM lt PWMDUTY gt PWMO pin output Figure 5 15 Operation When TOOPWM and the Up Counter Have the Same Value T bit cycle Source clock Hz Resolution period x 2 x TOOMOD NORMAL1 2 or IDLE1 2 mode lt TCKO gt Sanita SYSCR1 lt DV9CK gt SYSCR1 lt DV9CK gt SLEEP1 mode fegck 8MHz fs 32 768KHz fcgck 8MHz fs 32 768KHz 0 fs 24 32 8ms 62 5ms 488 ag 65 5ms 125ms fegck 2 16 4ms 31 3ms 10 3 fegck 2 fs 2 a 32 8ms 62 5ms 4 1ms 8 8 fcgck 2 fcgck 2 8 2ms 1 0ms 6 6 fegck 2 fegck 2 2 0ms 256us 4 4 fegck 2 fegck
74. er ARAS dens D NOX i E OE W e Coiler i famh Counter clear clear clear clear Double buffer TOOPWM i i lt PWMAD gt y Reflected by an i interrupt request Reflected by an interrupt request na oie eee eed ieceteiaieremaiate a a es TOOPWM lt PWMDUTY gt PWMO pin output A i Becomes the level sefected at t gt Additional pulse Returns to the TFFO while the timer is stopped A j i level selected No interrupt request No interrupt request at TFFO INTT COO interrupt j i YI is generated Interrupt request is generated request la gt Ta gt a m m Duty pulse Duty pulse Duty pulse Duty pulse Y 128 counts 3 128 counts A 128 counts a 128 counts Cycle 1 Cycle 2 Cycle 3 Cycle 4 When the double buffer is enabled TOOMOD lt DBE0 gt 1 Figure 5 14 8 bit PWM Mode Timing Chart Subsequently the up counter continues counting up When the up counter value reaches 128 an overflow occurs and the up counter is cleared to 0x00 At the same time the output of PWMOB pin is reversed When TOOMOD lt TFFO gt is 0 the PWMOB pin changes from the H to L level When TOOMOD lt TFFO gt is 1 the PW MOB pin changes from the L to H level If the 2 x n th overflow occurs at this time an INTTCOO interrupt request is generated No interrupt request is generated at the 2 x n th 1 overflow Subsequently the up co
75. ers The supply voltage VDD is divided by the ladder resistor and input to the detection voltage selection circuit A voltage is selected in the detection voltage selection circuit depending on the detection voltage VD1LVL and compared to the reference voltage in the comparator When the supply voltage VDD becomes lower than the detection voltage VDILVL a voltage detection interrupt request signal or a voltage detection reset signal is generated Either the voltage detection interrupt request signal or the voltage detection reset signal can be selected by programming the software Page 28 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Voltage detect reset gt Interrupt generation circuit LVD interrupt Level selection circuit Reference voltage generation circuit
76. fore operating the control register for the peripheral function When a peripheral function is operating the corresponding bit of the low power consumption registers POFFCRn must not be changed to 0 If it is changed the peripheral function may operate unexpectedly Low Power Consumption Register 0 POFFCRO Ox0F74 6 E Bit Symbol TCOO1EN Read Write R W After reset o 0 0 0 Disable TCOOIEN TCOO1 enable control 1 Enable Low Power Consumption Register 2 POFFCR2 7 6 0x0F76 Bit Symbol Read Write After reset 0 Disable RTC enable control 1 Enable Page 15 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 Low Power Consumption Register 3 POFFCR3 Ox0F77 7 6 5 4 3 2 1 0 Bit Symbol INT5EN INT4EN INT3EN INT2EN INTIEN I
77. g Ox4E clear code into WDCDR the 8 bit up counter is cleared to 0 and continues counting the source clock When WDCTR lt WDTEN gt is 0 writing OxB1 disable code into WDCDR disables the watchdog timer operation To prevent the 8 bit up counter from overflowing clear the 8 bit up counter in a period shorter than the overflow time of the 8 bit up counter and within the clear time By designing the program so that no overflow will occur the program malfunctions and deadlock can be detected through interrupts generated by watchdog timer interrupt request signals By applying a reset to the microcomputer using watchdog timer reset request signals the CPU can be restored from malfunctions and deadlock 5 1 3 6 Reading the 8 bit Up Counter The counter value of the 8 bit up counter can be read by reading WDCNT The stoppage of the 8 bit up counter can be detected by reading WDCNT at random times and comparing the value to the last read value 5 1 3 7 Reading the Watchdog Timer Status The watchdog timer status can be read at WDST Page 40 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agr
78. h use SZET RDARAS iMQ Technology Inc Title iMQ i87 User Manual Version V1 2 counting and be cleared to 0x0000 c Double Buffer The double buffer can be used for TO1 OOREG by setting T01MOD lt DBE1 gt The double buffer is disabled by setting TOIMOD lt DBEI gt to 0 or enabled by setting TOIMOD lt DBE1 gt to 1 1 When the Double Buffer is Enabled When write instructions are executed on TOOREG and TO1REG in this order during the timer operation the set value is first stored in the double buffer and TO1 00REG is not updated immediately T01 OOREG compares the previous set value with the up counter value When the values are matched an INTTCO1 interrupt request is generated and the double buffer set value is stored in TO1 OOREG Then the match detection is executed using a new set value When write instructions are executed on TOOREG and T0O1REG in this order while the timeris stopped the set value is immediately stored in both the double buffer and TO 1 00REG 2 When the Double Buffer is Disabled When write instructions are executed on TOOREG and TO1REG in this order during the timer operation the set value is immediately stored in TO1 OOREG Subsequently the match detection is executed using a new set value If the value set to TO1 OOREG is smaller than the up counter value the match detection is executed using a new set value after the up counter overflows Therefore the interrupt
79. he double buffer set value is stored in TOOREG Subsequently the match detection is executed using a new set value When a write instruction is executed on TOOREG while the timer is stopped the set value is immediately stored in both the double buffer and TOOREG 2 When the Double Buffer is Disabled When a write instruction is executed on TOOREG during the timer operation the set value is immediately stored in TOOREG Subsequently the match detection is executed using a new set value If the value set to TOOREG is smaller than the up counter value the match detection is executed using a new set value after the up counter overflows Therefore the interrupt request interval may be longer than the selected time If the value set to TOOREG is equal to the up counter value the match detection is executed immediately after data is written into TOOREG Therefore the interrupt request interval may not be an integral multiple of the source clock Figure 5 11 If these are problems enable the double buffer When a write instruction is executed on TOOREG while the timer is stopped the set value is immediately stored in TOOREG When a read instruction is executed on TOOREG the last value written into TOOREG is read out regardless of the TOOMOD lt DBEO gt setting Source clock Hz Resolution Maximum time setting TOOMOD NORMAL 1 2 or IDLE1 2 mode lt TCKO gt SLOW1 2 or SYSCR1 lt DV9CK gt SYSCR1 lt DV9CK gt sj FEP1 mode 0 4
80. he operation is changed to the software STOP or IDLEO SLEEPO mode is activated and Page 42 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 DVOCR lt DVOEN gt is cleared to 0 the frequency of the divider output is not the frequency set at DVOCR lt DVOCK gt DVOCR lt DVOEN gt DVO output PL LILI LIL Divider output timing chart Figure 5 6 Divider Output Timing When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL mode the divider output frequency does not reach the expected value due to synchronization of the gear clock fcgck and the low frequency clock fs Divider output frequency Hz DVOCK NORMAL 1 2 IDLE 1 2 mode SLOW1 2 SLEEP1 2 DV9CK 0 DV9CK 1 mode 3 906 k 2 048 k 2 048 k 7 813 k 4 096 k 4 096 k Table 5 2 Divider Output Frequency Example fcgck 8 0 MHz fs 32 768 kHz 5 3 Time Base Timer TBT
81. if ZF 1 a jump occurs to an address that is calculated by PC OxFF80 128 Thus the jump destination is OxE846 16 bit Absolute Jump Instruction JP a When the memory location at OxE8C4 contains the instruction JP OxC235 a jump occurs unconditionally to the address 0xC235 The absolute jump instruction can jump to a location within the full range of the code area for example 4K Bytes for MOQ8601 MQ8602 and MQ8801 Page 9 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 3 4 General Purpose Register The iMO i87 Series has two duplicate banks of eight 8 bit registers called W A B C D E H and L These registers can be used as 16 bit register pairs called WA BC DE and HL The general purpose registers are not mapped to the address space The contents of the general purpose registers are undefined after power up and reset BankO Bank1 16 bits 16 bits
82. ime be sure to set POFFCR2 lt RTCEN gt to 1 in the initial setting of the program before the real time clock control registers are operated Do not change POFFCR2 lt RTCEN gt to 0 during the real time clock operation Otherwise real time clock may operate unexpectedly 5 5 3 2 Enabling Disabling the Real Time Clock Operation Setting RTCCR lt RTCRUN gt to 1 enables the real time clock operation Setting RTCCR lt RTCRUN gt to 0 disables the real time clock operation RTCCR lt RTCRUND gt is cleared to 0 just after reset release 5 5 3 3 Selecting the Interrupt Generation Interval The interrupt generation interval can be selected at RTCCR lt RTCSEL gt RTCCR lt RTCSEL gt can be rewritten only when RTCCR lt RTCRUN gt is 0 If data is written into RTCCR lt RTCSEL gt when RTCCR lt RTCRUN2 gt is 1 the existing data remains effective RTCCR lt RTCSEL gt can be rewritten at the same time as enabling the real time clock operation but it cannot be re written at the same time as disabling the real time clock operation 5 5 4 Real Time Clock Operation 5 5 4 1 Enabling the Real Time Clock Operation Set the interrupt generation interval to RTCCR lt RTCSEL gt and at the same time set RTCCR Page 81 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to ob
83. input enable reset signal Voltage detection reset signal CPU peripheral circuits reset signal Warm up counter watchdog timer reset signal Warm up counter reset signal System clock reset signal o System clock control circuit Figure 4 1 Reset Control Circuit Notej Some of MO8S MCU series ICs might not have external reset input such as MQ8602 4 1 2 Control The reset control circuit is controlled by system control register 3 SYSCR3 system control register 4 SYSCR4 system control status register SYSSR4 and the internal factor reset detection status register IRSTSR System Control Register 3 SYSCR3 OxOFDE 7 6 5 4 3 2 1 0 Bit Symbol E RVCTR RAREA RSTDIS Read Write Read Only Read Only Read Only Read Only Read Only R W R W R W After reset 0 0 0 0 0 0 0 1 0 Enable the external reset input RSTDIS External reset input enable register 1 Disable the external reset input Page 20 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify a
84. ior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use ze RRARAS iMO Technology Inc Title IMO i87 User Manual Version V1 2 A watchdog timer interrupt is a non maskable interrupt and its request is always accepted regardless of the interrupt master enable flag IMF setting Note When a watchdog timer interrupt is generated while another interrupt including a watchdog timer interrupt is already accepted the new watchdog timer interrupt Is processed immediately and the preceding interrupt is put on hold Therefore if watchdog timer interrupts are generated continuously without execution of the RETN instruction too many levels of nesting may cause a malfunction of the microcontroller When Watchdog Timer Reset Request Signal is Selected as WDCTR lt WDTOUT is 1 Setting WDCTR lt WDTOUT gt to 1 causes a watchdog timer reset request signal to occur when the 8 bit up counter overflows This watchdog timer reset request signal resets the MO8S MCU series IC and starts the warm up operation 5 1 3 5 Writing the Watchdog Timer Control Codes The watchdog timer control codes are written into WDCDR By writin
85. ircuit Power on reset signal Figure 4 4 Power on Reset Circuit 4 2 2 Function When power supply voltage goes on if the supply voltage is equal to or lower than the releasing voltage of the power on reset circuit a power on reset signal is generated and if it is higher than the releasing voltage of the power on reset circuit a power on reset signal is released When power supply voltage goes down if the supply voltage is equal to or lower than the detecting voltage of the power on reset circuit a power on reset signal is generated Until the power on reset signal is generated a warm up Circuit and a CPU is reset When the power on reset signal is released the warm up Circuit is activated The reset of the CPU and peripheral circuits is released after the warm up time that follows reset release has elapsed Increase the supply voltage into the operating range during the period from detection of the power on reset release voltage until the end of the warm up time that follows reset release If the supply voltage has not reached the operating range by the end of the warm up time that follows reset release the MO8S MCU cannot operate properly Supply voltage VDD Operating voltage Power on reset signal Warm up A i counter clock l tpwup i CPU peripheral circuits reset signal Figure 4 5 Operation Timing of Power on Reset Page 27 82 The information contained herein shall not be changed
86. ld be written 0xB2 Enable code for SYSCR3 lt RSTDIS gt in NORMAL mode when fcgck Is f 4 CGCR lt FCGCKSEL gt 00 Otherwise SYSCR lt RSTDIS gt may be enabled at unexpected timing Note 3J After IRSTSR lt FCLk gt is modified SYSCR4 should be written 0x71 Enable code for IRSTSR lt FCLR gt in NORMAL mode when fcgck is f6 4 CGCR lt FCGCKSEL gt 00 Otherwise IRSTSR lt FCLR gt may be enabled at unexpected timing System Control Status Register 4 SYSSR4 OxOFDF Z 6 2 1 0 Bit Symbol RVCTRS RAREAS RSTDISS Read Write Read Only ReadOnly Read Only After reset 0 0 1 0 The enabled SYSCR3 lt RSTDIS gt data is 0 RSTDISS External reset input enable register 1 The disabled SYSCR3 lt RSTDIS gt data is 1 Note 1 The enabled SYSCR3 lt RSTDIS gt is initialized by a power on reset only and cannot be initialized by any other reset signals The value written in SYSCR3 Is reset by a power on reset and other reset signals Note JJ Bits 7 to 3 of SYSCR4 are read as 0 Page 21 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s ri
87. ly at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BT RPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 00 Release STOP mode depending on the state of the STOPB pin 01 Release STOP mode when the supply voltage VDD becomes higher than the detection voltage VD1LVL Selection for the STOP mode release source 10 Release STOP mode depending on the state of the STOPB pin or when the supply voltage VDD becomes higher than the detection voltage VD1LVL 11 Reserved Select the operation mode of 0 Generate a voltage detection interrupt request signal voltage detection 1 1 Generate a voltage detection reset signal Enable disable the VDIEN operation of voltage detection 1 VD1IMOD 0 Disable the operation of voltage detection 1 1 Enable the operation of voltage detection 1 Note 1J VDCR2 Is initialized by a power on reset or an external reset input Note JJ Bits 7 and 6 of VDCR2 are read as 0 Voltage Detection Control Register 3 VDCR3 OxOFBF 7 Bit Symbol Read Write After reset 0000 4 40V 0 2 V 0000 3 74V 0 2 V 0001 4 25V 0 2 V 0001 3 61V 0 2 V 0010 4 10V 0 2 V 0010 3 48V 0 2 V 0011 3 79V 0 2 V 0011 3 22V 0 2 V 0100 3 58V 0 2 V 0100 3
88. mode 00 8 bit timer event counter modes 16 bit timer event counter modes Operation clock selection Selection for using external source clock Operation mode selection 01 8 bit timer event counter modes 16 bit timer event counter modes 8 bit pulse width modulation 12 bit pulse width modulation output PWM mode output PWM mode 8 bit programmable pulse generate 16 bit programmable pulse generate PPG mode PPG mode 10 11 Note 1J fcgck Gear clock Hz fs Low frequency clock Hz Note 2 Set TOIMOD while the timer is stopped Writing data into TOIMOD is invalid during the timer operation Note 3J In the 8 bit timer event modes the TFF1 setting Is invalid In this mode when the PWM1B and PPG1IB pins are set as the function output pins in the port setting the pins always output the H level Note 4 When EINI is set to 1 and the external clock input Is selected as the source clock the TCK1 setting is ignored 5 4 2 3 Common to Timer Counters 00 and 01 Timer counters 00 and 01 have the low power consumption register POFFCRO and timer 00 and 01 control registers in common Low Power Consumption Register 0 POFFCRO Ox0F74 4 4 Bit Symbol TCOO1EN Read Write R W After reset o 0 Disable TCOO1EN TCOO 01 control z 1 Enable Page 49 82 The information contained he
89. multaneously by writing to TO1REG while the timer INTTCO01 interrupt pi is stopped an interrupt request Reflected by writing to TOIREG When the double buffer is enabled T01MOD lt DBE1 gt 1 Figure 5 19 16 bit Timer Counter Timing Chart 5 4 4 6 16 bit Event Counter Mode In the 16 bit event counter mode the up counter counts up at the falling edge of the input to the TCOO pin TCOO and TCO are cascaded to form a 16 bit timer counter which can measure a longer period than an 8 bit timer Page 68 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMQ from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 a Setting Setting TOO1CR lt TCAS gt to 1 connects TCOO and TCO1 and activates the 16 bit timer mode All the settings of TCOO are ignored and those of TCO1 are effective in the 16 bit timer mode The 16 bit timer mode is activated by setting TOIMOD lt TCMI gt to 00 or 01 and TOIMOD lt EINO gt to 1
90. n an external source clock is selected input the clock at the TCOO pin The maximum frequency to be supplied is fegck 2 Hz in NORMAL1 2 or IDLE 1 2 mode or fs 2 Hz in SLOW 1 2 or SLEEP1 mode and a pulse width of two machine cycles or more is required at both the H and L levels c Double Buffer The double buffer can be used for TO1 OOPWM and T01 00REG by setting TOIMOD lt DBE1 gt The double buffer is enabled by setting TOIMOD lt DBE1 gt to 0 or disabled by setting TOIMOD lt DBE1 gt to 1 Page 77 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 1 When the Double Buffer is eEabled When a write instruction is executed on TOIPWM after write instructions are executed on TOOREG TOIREG and TOOPWM during the timer operation the set values are first stored in the double buffer and TO1 OOPWM and TO1 00REG are not updated immediately TO1 OOPWM and T01 00REG c
91. n registers POFFCRO that save power when the timers are not used Setting POFFCRO lt TCOO1EN gt to 0 disables the basic clock supply to timer counters 00 and 01 to save power Note that this renders the timers unusable Setting POFFCRO lt TCOO1EN gt to 1 enables the basic clock supply to timer counters 00 and 01 and allows the timers to operate After reset POFFCRO lt TCOO1EN gt are initialized to 0 and this makes the timers unusable When using the timers for the first time be sure to set POFFCRO lt TCOOITEN gt to 1 in the initial setting of the program before the timer control registers are operated Do not change POFFCRO lt TCOO1EN gt to 0 during the timer operation Otherwise timer counters 00 and 01 may operate unexpectedly Page 51 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 5 4 4 Function Timer counters TCOO and TCO1 have 8 bit mode
92. n voltage VD1LVL Note If the voltage detection mode Is set to generate voltage detection interrupt request signals and the supply voltage VDD becomes lower than the detection voltage VDILVL in the STOP IDLEO or SLEEPO mode a voltage detection interrupt request signal is generated after the operation mode Is released and returned to NORMAL or SLOW mode VDD level Detection voltage level VDCR2 lt VD1EN gt Voltage detection interrupt i l i request signal r I I Voltage detection reset signal i i Figure 4 7 Voltage Detection Interrupt Request Signal and Voltage Detection Reset Signal 4 3 3 3 Selecting the Detection Voltage Level Select a detection voltage at VDCR3 lt VD 1 LVL gt 4 3 3 4 Voltage Detection Flag and Voltage Detection Status Flag The magnitude relation between the supply voltage VDD and the detection voltage VD1LVL can be checked by reading VDCR1 lt VD1F gt and VDCR1 lt VD1SF gt If VDCR2 lt VDIEN gt is set at 1 when the supply voltage VDD becomes lower than the Page 31 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defe
93. nd hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Note 1 The enabled SYSCR3 lt RSTDIS gt is initialized by a power on reset only and cannot be initialized by an external reset input or internal factor reset The value written in SYSCR3 is reset by a power on reset external reset input or internal factor reset Note JJ The value of SYSCR3 lt RSTDIS gt is invalid until OxB2 is written into SYSCR4 Note 3 After SYSCR3 lt RSTDIS gt is modified SYSCR4 should be written OxB2 Enable code for SYSCR3 lt RSTDIS gt in NORMAL 1 mode when fcgck Is 6 4 CGCR lt FCGCKSEL gt 00 Otherwise SYSCR 3 lt RSTDIS gt may be enabled at unexpected timing Note 4J Bits 7 to 3 of SYSCR3 are read as 0 System Control Register 4 SYSCR4 3 OxOFDF Bit Symbol SYSCR4 Read Write Write only After reset o 0 OxB2 Enable the contents of SYSCR3 lt RSTDIS gt OxD4 Enable the contents of SYSCR3 lt RAREA gt and SYSCR3 SYSCR4 Write the SYSCR3 data control code lt RYGTRZ 0x71 Enable the contents of IRSTSR lt FCLR gt Others Invalid Note 1J SYSCR4 is a write only register and must not be accessed by using a read modify write instruction such as a bit operation Note 2 After SYSCR3 lt RSTDIS gt is modified SYSCR4 shou
94. nd hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 TOOMOD lt DBEO0 gt Source clock Counter Write to TOOPWM TOOREG Write n 2 TOOPWM TOOREG Match detection n 2 Y PPGO pin output Figure 5 18 Operation When TOOPWM TOOREG and the Up Counter Have the Same Value 5 4 4 5 16 bit Timer Mode In the 16 bit timer mode TCOO and TCO1 are cascaded to form a 16 bit timer counter which can measure a longer period than an 8 bit timer a Setting Setting T001CR lt TCAS gt to 1 connects TCOO and TCO1 and activates the 16 bit mode All the settings of TCOO are ignored and those of TCO1 are effective in the 16 bit mode The 16 bit timer mode is activated by setting TOIMOD lt TCM1 gt to 00 or 01 and TOIMOD lt EIN1 gt to 0 Select the source clock at TOIMOD lt TCK1 gt Set the count value to be used for the match detection as a 16 bit value at the timer registers TOOREG and TOIREG Set the lower 8 bits of the 16 bit value at TOOREG and the higher 8 bits at TO1REG Hereinafter the 16 bit value specified by the combined setting of TOIREG and TOOREG is indicated as TO1 OOREG The timer register settings are reflected on the double buffer or TO1 OOREG when a write instruction is executed on TOIREG Be sure to execute the write instructions on TOOREG
95. nd indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 detection voltage VD1ILVL VDCR1 lt VD1F gt is set to 1 and is held in this state VDCR1 lt VD1F gt is not cleared to 0 when the supply voltage VDD becomes equal to or higher than the detection voltage VD1LVL When VDCR2 lt VD1EN gt is cleared to 0 after VDCR1 lt VD1F gt is set to 1 the previous state is still held To clear VDCR1 lt VD1F gt 0 must be written to it If VDCR2 lt VDIEN gt is set at 1 when the supply voltage VDD becomes lower than the detection voltage VDILVL VDCR1 lt VDI1SF gt is set to 1 When the supply voltage VDD becomes equal to or higher than the detection voltage VDILVL VDCR1 lt VDISF gt is cleared to o Unlike VDCR1 lt VD1F gt VDCR1 lt VD1SF gt does not hold the set state Note 1 When the supply voltage VDD becomes lower than the detection voltage VDILVL in the STOP IDLEO or SLEEPO mode the voltage detection flag and the voltage detection status flag are changed after the operation mode Is returned to NORMAL or SLOW mode Note 2 Depending on the voltage detection timing the voltage detection status flag VD1SF may be changed earlier than the voltage detection flag VD IF by a maximum of 2 fcgck s VDD level Detection voltage level VDC
96. nformation in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMQ from any and all damages claims suits or expenses resulting from such use 50 82 ez TAR DARAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 Note 1 o Usable Unusable Note 2 Set the source Clock in the 16 bit modes on the TCO side TCK 1 Note 3 When the low frequency clock fs is not oscillating it must not be selected as the source Clock If fs is selected when it is not oscillating no source Clock is supplied to the timer and the timer remains stopped Note 4 0 1 f 0 only in the 16 bit modes TCKO Operation mode 8 bit timer TCO pin input 8 bit event counter 8 bit PWM 8 bit timer modes 8 bit PPG 16 bit timer 16 bit event counter 12 bit PWM 16 bit timer modes 16 bit PPG Table 5 7 Operation Modes and Usable Source Clocks SLOW 1 2 and SLEEP1 Modes Note 1 o Usable Unusable Note 2 Set the source Clock in the 16 bit modes on the TCO side TCK 1 Note 3 0 1 i 0 only in the 16 bit modes 5 4 3 Low Power Consumption Function Timer counters 00 and 01 have the low power consumptio
97. ng STOP Mode To release STOP mode input a high level signal into the STOPB pin or input a specific release level into the KWIm pin for which receipt of inputs is enabled If you want to release STOP mode at the KWIm pin rather than the STOPB pin continue inputting a low level signal into the STOPB pin throughout the period from the start of the STOP mode to the release of the STOP mode If the STOPB pin or KWIm pin is already at a release level when the STOP mode starts the following instruction will be executed without starting the STOP mode with no warm up performed Note Do not applied an analog voltage to KWim pin for which receipt of inputs is enabled by the key on wakeup control register KWUCRn setting or a penetration current will flow Page 18 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 Release level edge SYSCR1 lt RELM gt 1 level release mode
98. o 0 To use the internal clock as the source clock Set TOOMOD lt EINO gt to 0 and select the clock at TOOMOD lt TCKO gt To use an external clock as the source clock set TOOMOD lt EINO gt to 1 Set the duty pulse width at TOOPWM and the cycle width at TOOREG Set TOOMOD lt DBEO gt to 1 to use the double buffer Setting TOO1CR lt TOORUN gt to 1 starts the operation After the timer is started writing to TOOMOD becomes invalid Be sure to complete the required mode settings before starting the timer z start Timer stop Duty pulse Duty pulse iTOOPWM TOOPWM lt gt o PPGO pin output TFFO 0 i P ere TOOREG TOOREG 1cycle 1 cycle TFFO 1 PPGO pin output Figure 5 16 PPGOB Pulse Output Set the initial state of the PPGOB pin at TOOMOD lt TFFO gt Setting TOOMOD lt TFFO gt to 0 selects the L level as the initial state of the PPGOB pin Setting TOOMOD lt TFFO gt to 1 selects the H level as the initial state of the PPGOB pin If the PPGOB pin is set as the function output pin in the port setting while the timer is stopped the value of TOOMOD lt TFFO gt is output to the PPGOB pin Table 5 11 shows the list of output levels of the PPGOB pin Setting the TOOICR lt OUTAND gt bit to 1 allows the PPGOB pin to output a pulse that is a logical ANDed product of the TCOO and TCO1 outputs PPGO pin output level Before the start
99. ombination that puts the CPU into deadlock Refer to System Clock Control section of each product s datasheet 4 1 4 6 Internal Factor Reset Detection Status Register By reading the internal factor reset detection status register IRSTSR after the release of an internal factor reset except the power on reset the factor which causes a reset can be detected Page 25 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 The internal factor reset detection status register is initialized by an external reset input or power on reset Set IRSTSR lt FCLR gt to 1 and write 0x71 to SYSCR4 This enables IRSTSR lt FCLR gt and the internal factor reset detection status register is clear to 0 IRSTSR lt FCLR gt is cleared to 0 automatically after initializing the internal factor reset detection status register Note 1 Care must be taken in system designing since the IRSTSR may not
100. ompare the previous set values with the up counter value When a match between the up counter value and the TO1 00REG set value is detected an INTTCO1 interrupt request is generated and the double buffer set values are stored in TO1 OOPWM and T01 00REG Subsequently the match detection is executed using new set values When a write instruction is executed on TOIPWM after write instructions are executed on TOOREG TOIREG and TOOPWM while the timer is stopped the set values are immediately stored in both the double buffer and TO1 OOPWM and TO1 00REG 2 When the Double Buffer is Disabled When a write instruction is executed on TOIPWM after write instructions are executed on TOOREG TOIREG and TOOPWM during the timer operation the set values are immediately stored in TO1 OOPWM and T01 00REG Subsequently the match detection is executed using new set values If the value set to TO1 OOPWM or T01 00REG is smaller than the up counter value the PPG1B pin is not reversed until the up counter overflows and a match detection is executed using a new set value If the value set to T01 OOPWM or TO1 00REG is equal to the up counter value the match detection is executed immediately after data is written into T01 OOPWM and T01 00REG Therefore the timing of changing the PPGIB pin may not be an integral multiple of the source clock If these are problems enable the double buffer When a write instruction is executed on TOIPWM after write instructions are
101. on status register Note 5J After IRSTSR lt FCLk gt is modified SYSCR4 should be written 0x71 Enable code for IRSTSR lt FCLR gt in NORMAL mode when fcgck is f6 4 CGCR lt FCGCKSEL gt 00 Otherwise IRSTSR lt FCLR gt may be enabled at unexpected timing Note 6 Bit 7 of IRSTSR is read as O 4 1 3 Function The power on reset external reset input and internal factor reset signals are input to the warm up circuit of the clock generator During reset the warm up counter circuit is reset and the CPU and the peripheral circuits are reset After reset is released the warm up counter starts counting the high frequency clock fc and executes the warm up operation that follows reset release During the warm up operation that follows reset release the trimming data is loaded from the embedded non volatile memory eNVM for adjustment of the ladder resistor that generates the comparison voltage for the power on reset and the voltage detection circuits Note J The eNVM includes OTP and flash types Please see MO8 amp S MCU datasheet for detailed description Page 22 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at
102. ops restores the return address into the PC When the return from interrupt instruction RETI or RETN is executed the CPU restores the PC and PSW from the stack A stack can be allocated anywhere in the data area 3 2 2 Stack Pointer The Stack Pointer SP is a 16 bit register that holds the address of the next available location on the stack The SP is post decremented on subroutine calls PUSH operations and interrupts and pre incremented on returns from subroutines and interrupts and POP operations The stack grows downwards from high addresses to low addresses as it is filled Page 7 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use EZ SFR DARA S iMO Technology Inc Title iMOi87 User Manual Version V1 2 lt 16 bits gt Figure 3 1 Stack Pointer Figure 3 2 shows the contents of the stack and the SP register as each of the following instructions is executed The SP register defaults to OxOOFF upon hardware reset Like an inde
103. ot be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 PWMO pin output level TOOPWM Before the start lt PWMDUTY gt Operation of operation matched stopped initial state after the addi initial state tional pulse Table 5 9 List of Output Levels of PW MOB Pin And by setting 1 to TO01CR lt OUTAND gt bit a logical product AND pulse of TCOO and TCO1 s output can be output to PWMOB pin By using this function the remote control waveform can be created easily b Operation Setting TOO1CR lt TOORUN gt to 1 allows the up counter to increment based on the selected source clock When a match between the lower 7 bits of the up counter value and the value set to TOOPWM lt PWMDUTY gt is detected the output of the PWMOB pin is reversed When TOOMOD lt TFFO gt is 0 the PW MOB pin changes from the L to H level When TOOMOD lt TFFO gt is 1 the PWMOB pin changes from the H to L level If TOOPWM l
104. p counter source clock operates out of synchronization with WDCTR lt WDTEN gt Therefore the first overflow time of the amp bit up counter after WDCTR lt WDTEN gt Is set to 1 may get shorter by a maximum of 1 source Clock The amp bit up counter must be cleared within the period of the overflow time minus 1 source Clock cycle 5 1 3 2 Setting the Clear Time of the 8 bit Up Counter WDCTR lt WDTW gt sets the clear time of the 8 bit up counter i 8 bit up counter value 3FHX40HX TFA BOR X BFA CORK FFHXOOHX When WDCTR lt WDTW gt is 00 e Clear time oH When WDCTR lt WDTW gt is 01 F Outside the clear time gt j Clear time r When WDCTR lt WDTW gt is 10 Outside the clear time Clear time When WDCTR lt WDTW gt is 11 outside the clear time gt Clear time gt I Figure 5 3 WDCTR lt WDTW gt and the 8 bit Up Counter Clear Time When WDCTR lt WDTW gt is 00 the clear time is equal to the overflow time of the 8 bit up counter and the 8 bit up counter can be cleared at any time When WDCTR lt WDTW gt is not 00 the clear time is fixed to only a certain period within the Page 38 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the
105. pecification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use ez TAR DARAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 Note When the supply voltage VDD is lower than the detection voltage VDILVL setting VDCR2 lt VDIEN gt to generates a voltage detection interrupt request signal or a voltage detection reset signal at the time 4 3 3 2 Selecting the Voltage Detection Operation Mode If the voltage detection operation mode is set to generate voltage detection interrupt request signals VDCR1 lt VD1IMOD gt 0 and VDCR2 lt VDIEN gt is set to 1 a voltage detection interrupt request signal is generated when the supply voltage VDD becomes lower than the detection voltage VDILVL If the voltage detection operation mode is set to generate voltage detection reset signals VDCR1 lt VDIMOD gt 1 and VDCR2 lt VDIEN gt is set to 1 a voltage detection reset signal is generated when the supply voltage VDD becomes lower than the detection voltage VD1LVL VDCR1 is initialized by a power on reset or an external reset input only Therefore the voltage detection reset signals are generated continuously as long as the supply voltage VDD is lower than the detectio
106. penses resulting from such use RTCSEL 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Note 1 fs Low frequency clock Hz Note 2J RTCCR lt RTCSEL gt can be rewritten only when RTCCR lt RTCRUN gt is 0 If data is written into RTCCR lt RTCSEL gt when RTCCR lt RTCRUN gt Is 1 the existing data remains effective RTCCR lt RTCSEL gt can be rewritten at the same time as enabling the real time Clock but it cannot be rewritten at the same time as disabling the real time clock Note 3 If the real time clock Is enabled and when 1 SYSCR2 lt XTEN gt Is cleared to 0 to stop the low frequency clock oscillation circuit or 2 the operation is changed to the STOP mode or the SLEEPO mode the data in RTCCR lt RTCSEL gt is maintained and RTCCR lt RTCRUN gt is cleared to 0 5 5 3 Function 5 5 3 1 Low Power Consumption Function Real time clock has the low power consumption registers POFFCR2 that save power when the real time clock is not being used Setting POFFCR2 lt RTCEN gt to 0 disables the basic clock supply to real time clock to save power Note that this renders the real time clock unusable Setting POFFCR2 lt RTCEN gt to 1 enables the basic clock supply to real time clock and allows the real time clock to operate After reset POFFCR2 lt RTCEN gt are initialized to 0 and this renders the real time clock unusable When using the real time clock for the first t
107. pin is reversed When TOIMOD lt TFF1 gt is 0 the PWM1B pin changes from the L to H level When TOIMOD lt TFF 1 gt is 1 the PWM1B pin changes from the H to L level If any of PWMAD3 to PWMADO is 1 an additional pulse that corresponds to 1 count of the source clock is inserted in specific cycles of the duty pulse In other words the PWM1B pin output is reversed at the timing of PW MDUTY 1 When TOOMOD lt TFFO gt is 0 the period of the L level becomes longer than the value set to PWMDUTY by 1 source clock When TOOMOD lt TFFO gt is 1 the period of the H level becomes longer than the value set to PWMDUTY by 1 source clock This function allows 16 cycles of output pulses to be handled with a resolution nearly equivalent to 12 bits No additional pulse is inserted when PWMAD3 to PWMADO are all 0 Subsequently the up counter continues counting up When the up counter value reaches 256 an overflow occurs and the up counter is cleared to 0x00 At the same time the output of the PWM1B pin is reversed When TOIMOD lt TFF1 gt is 0 the PWM1B pin changes from the H to L level When TOIMOD lt TFFI gt is 1 the PWM1B pin changes from the L to H level At this time an INTTCOO interrupt request is generated an INTTCOO interrupt request is generated each time an overflow occurs An INTTCO1 interrupt request is generated at the 16 x n th overflow n 1 2 3 Subsequently the up counter continues counting
108. r RBS Page 11 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use ze TRH AAG iMQ Technology Inc Title iMO i87 User Manual Version V1 2 Dedicated instructions are available to access the PSW General load instructions can also be used to read the PSW Organization of the PSW PSW 0x003FH The PSW consists of seven bits of status information that are set or cleared by CPU operations The flags can be specified as a condition code cc in conditional jump instructions JR cc a and JRS cc a except RBS and HF a a T True JF 1 False JF 0 Zero ZF 1 Not zero ZF 0 Carry set CF 1 Carry clear CF 0 Overflow set VF 1 Overflow clear VF 0 Minus SF 1 Plus SF 0 Equal ZF 1 Not equal ZF 0 Unsigned less than CF 1 Unsigned greater than or equal to CF 0 Unsigned less than or equal to Unsigned greater than Signed less than Signed greater than or equal to Signed less than or equal to Signed greater than CF vZF 1
109. r is cleared by writing the clear code after the first half of the overflow time has elapsed 11 A watchdog timer interrupt request is generated by writing the clear code at a point within the first three quarters of the overflow time of the 8 bit up counter The 8 bit up counter is cleared by writing the clear code after the first three quarters of the overflow time have elapsed NORMAL mode DV9CK 0 DV9CK 1 SLOW mode Set the overflow time of the 00 2 8 fcgck 2 fs 2 fs 8 bit up counter 01 220 fegck 2 3 fs 2 3 fs 10 272 fegck 2 9 fs 2 3 fs 11 224 fcgck 2 7 fs 217 fs Select an overflow detection 0 Watchdog timer interrupt request signal signal of the 8 bit up counter 1 Watchdog timer reset request signal WDTOUT Note 1 fcgck Gear clock Hz fs Low frequency clock HZ Note 2 WDOCTR lt WDTW gt WDCTR lt WDTT gt and WDCTR lt WDTOUT gt cannot be changed when WDCTR lt WDTEN gt is 1 lf WDCTR lt WDTEN gt is 1 clear WDCTR lt WDTEN gt to 0 and write the disable code OxB1 into WDCDR to disable the watchdog timer operation Note that WDCTR lt WDTW gt WDCTR lt WDTT gt and WDCTR lt WDTOUT gt can be changed at the same time as setting WDCTR lt WDTEN gt to 7 Note 3 Bit 7 and bit 6 of WDCTR are read as 1 and 0 respectively Watchdog Timer Control Code Register WDCDR OxOFD5 4 gt Bit Symbol Read Write After reset
110. rees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use ez TR DARA iMQ Technology Inc Title iMOi87 User Manual Version V1 2 3 4 3 DE Registers In Register Indirect Addressing the DE register holds the address of the memory location where the operand resides 3 4 4 HL Registers In Register Indirect Addressing the HL register holds the address of the memory location where the operand resides In Indexed Addressing the HL register is used as an index register 3 4 5 16 Bit General Purpose Registers IX IY The device has two duplicate banks of two 16 bit general purpose registers called IX and IY In Register Indirect Addressing these registers hold the address of the memory location where the operand resides In Indexed Addressing they are used as index registers The contents of the IX and IY registers are undefined after power up and reset BankO Bank1 lt 16 bits gt 16bits gt Figure 3 5 16 Bit General Purpose Registers The load store and ALU instructions can also use the IX and IY registers as 16 bit general purpose registers 3 5 Program Status Word PSW The Program Status Word which resides at address 0x003F in the SFR consists of the following seven Jump Status Flag JF Zero Flag ZF Carry Flag CF Half Carry Flag HF Sign Flag SF Overflow Flag VF Register Bank Selecto
111. rein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use Ned RZ cat Ae 1B BRZ Sl iMQ Technology Inc Title IMO i87 User Manual Version V1 2 Timer 00 and 01 Control Register TOOICR 0x002C 7 6 3 1 0 Bit Symbol OUTAND TOTRUN TOORUN Read Write R W R W R W After reset 0 0 0 OUTAND Timer 00 and 01 output control 0 Output the timer 00 output from the PW MOB and PPGOB pins and the timer 01 output from the PWM 1B and PPG1B pins 1 Output a pulse that is a logical ANDed product of the outputs of timer 00 and 01 from the PWM1B and PPG1B pins TCAOEN Timer 00 and 01 cascade control 0 Use timer 00 and 01 independently 8 bit mode 1 Cascade timer 00 and 01 16 bit mode TOTRUN Timer 01 control Timer mode 00 01 control 16 bit 0 Stop and clear the timer 1 Start TOORUN Timer 00 control 0 Stop and clear the timer 1 Start Note
112. right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 5 4 2 Control 5 4 2 1 Timer Counter 00 The timer counter 00 is controlled by the timer counter 00 mode register TOOMOD and two 8 bit timer registers TOOREG and TOOPWM Timer Register 00 TOOREG 15 0x0026 Bit Symbol Read Write After reset Timer Register 00 TOOPWM 7 0x0028 Bit Symbol Read Write After reset Note For the configuration of TOOPWM in the 8 bit and 12 bit PWM modes refer to 5 4 4 3 8 amp bit pulse width modulation PWM output mode and 5 4 4 7 12 bit pulse width modulation PWM output mode Timer Counter 00 Mode Register TOOMOD 7 6 Ox002A Bit Symbol Read Write After reset 0 Clear Timer F FO control 1 Set 0 Disable the double buffer Poupe purer control 1 Enable the double buffer Normal 1 2 IDLE 1 2 mode SLOW 1 2 mode SYSCRI SYSCRI SLEEP 1 mode
113. s suits or expenses resulting from such use
114. s in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 the RBS bit from the stack as part of the PSW The active register bank changes according to the restored RBS value 3 6 Low Power Consumption Function for Peripherals The MO8S MCU has low power consumption registers POFFCRn that save power when specific peripheral functions are unused Each bit of the low power consumption registers can be set to enable or disable each peripheral function n 0 2 3 The basic clock supply to each peripheral function is disabled for power saving by setting the corresponding bit of the low power consumption registers POFFCRn to 0 The disabled peripheral functions become unavailable The basic clock supply to each peripheral function is enabled and the function becomes available by setting the corresponding bit of the low power consumption registers POFFCRn to 1 After reset the low power consumption registers POFFCRn are initialized to 0 and thus the peripheral functions are unavailable When each peripheral function is used for the first time be sure to set the corresponding bit of the low power consumption registers POFFCRn to 1 in the initial settings of the program be
115. s in which they are used independently and 16 bit modes in which they are cascaded The 8 bit modes include four operation modes 8 bit timer mode 8 bit event counter mode 8 bit pulse width modulation output PWM mode and 8 bit programmable pulse generated output PPG mode The 16 bit modes include four operation modes the 16 bit timer mode the 16 bit event counter mode the 12 bit PWM mode and the 16 bit PPG mode 5 4 4 1 8 bit Timer Mode In the 8 bit timer mode the up counter counts up using the internal clock and interrupts can be generated regularly at specified times The operation of TCOO is described below and the same applies to the operation of TCO1 Replace TCOO by TCO1 a Setting TCOO is put into the 8 bit timer mode by setting TOOMOD lt TCMO gt to 00 or 01 TOOICR lt TCAS gt to 0 and TOOMOD lt EINO gt to 0 Select the source clock at TOOMOD lt TCKO gt Set the count value to be used for the match detection as an 8 bit value at the timer register TOOREG Set TOOMOD lt DBEO gt to 1 to use the double buffer Setting TOOICR lt TOORUN gt to 1 starts the operation After the timer is started writing to TOOMOD becomes invalid Be sure to complete the required mode settings before starting the timer b Operation Setting TOO1CR lt TOORUN gt to 1 allows the 8 bit up counter to increment based on the selected internal source clock When a match between the up counter value and the TOOREG set
116. se width modulation PWM output mode Timer Counter 01 Mode Register TOIMOD 7 6 O0x002B Bit Symbol Read Write After reset Page 48 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BT RPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 0 Clear Timer F F1 control 1 Set 0 Disable the double buffer DOUDIE BUTER e antrel 1 Enable the double buffer Normal 1 2 IDLE 1 2 mode SLOW 1 2 mode SYSCR1 lt DV9CK gt 0 SYSCR1 lt DV9CK gt 1 SLEEP 1 mode 000 fegck 2 fs 2 fs 2 001 fegck 2 9 fs 23 fs 23 010 fegck 28 fegck 28 d 011 fcgck 2 fcgck 2 J 100 fegck 24 fegck 2 a 101 fegck 2 fegck 2 d 110 fcgck 2 fcgck 2 111 fcgck fcgck fs 22 0 Select the internal clock as the source clock 1 Select an external clock as the source clock the falling edge of the TCO1 pin TO0O1CR lt TCAS gt 0 TOO1CR lt TCAS gt 1 8 bit mode 16 bit
117. sk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Internal Factor Reset Detection Status Register IRSTSR OxOFCC A gt 2 1 o Bit Symbol FCLR LVD1RF SYSRF WDTRF Read Write Write Only Read Only ReadOnly Read Only After reset 0 0 0 0 0 Pore Bee LAE AS 1 Clear the internal factor reset flag to 0 0 LVD1RF Voltage detection reset 1 detection flag 1 Detect the voltage detection 1 reset 0 SYSRF System clock reset detection flag 1 Detect the system clock reset 0 WDTRF Watchdog timer reset detection flag 1 Detect the watchdog timer reset Note 1J IRSTSR is initialized by an external reset input or power on reset Note 2J Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other effects Note 3 IRSTSR lt FCLR gt is initialized by a power on reset an external reset input or an internal reset factor Note 4 Set IRSTSR lt FCLR gt to 1 and write Ox71 to SYSCR4 This enables IRSTSR lt FCLR gt and the internal factor reset detection status register is Clear to 0 IRSTSR lt FCLR gt is cleared to 0 automatically after initializing the internal factor reset detecti
118. status 2 1 A watchdog timer interrupt request signal has occurred due to the overflow of the 8 bit up counter 0 No watchdog timer interrupt request signal has occurred WINTST1 Watchdog timer interrupt request signal factor status 1 1 A watchdog timer interrupt request signal has occurred due to releasing of the 8 bit up counter outside the clear time Watchdog timer operating state 0 Operation disabled status 1 Operation enabled Note 1J WDST lt WINTST2 gt and WDST lt WINTST I gt are Cleared to O by reading WDST Note JJ Values after reset are read from bits 7 to 3 of WDST 5 1 3 Function The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8 bit up counter and detecting releasing of the 8 bit up counter outside the clear time The watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8 bit up counter at random times and comparing the value to the last read value 5 1 3 1 Setting of Enabling Disabling the Watchdog Timer Operation Setting WDCTR lt WDTEN gt to 1 enables the watchdog timer operation and the 8 bit up counter starts counting the source clock WDCTR lt WDTEN2 gt is initialized to 1 after the warm up operation that follows reset is released This means that the watchdog timer is enabled Page 37 82 The information contained herein shall not be changed without prior written permission
119. t A INTTCOO interrupt I request T 1 i Becomes the level selected at INTTCOO interrupt TFF1 while the timer is stopped request if i Returns to the level selected at TFF1 N lt gt ao e g i km km Duty pulse Duty pulse Duty pulse i ab t cd cd Cycle 1 Cycle 1 Cycle 1 Cycle 1 a a a A When the double buffer is enabled T01MOD lt DBE1 gt 1 Figure 5 24 16 bit PPG Output Mode Timing Chart 5 5 Real Time Clock RTC The real time clock is a function that generates interrupt requests at certain intervals using the low frequency clock The number of interrupts is counted by the software to realize the clock function The real time clock can be used only in the operation modes where the low frequency clock oscillates except for SLEEPO Page 79 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMQ from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 5 5 1 Configuration
120. t PWMAD gt is 1 an additional pulse that corresponds to 1 count of the source clock is added at the 2 x n th match detection n 1 2 3 In other words the PW MOB pin output is reversed at the timing of TOOPWM lt PWMDUTY gt 1 When TOOMOD lt TFFO gt is 0 the period of the L level becomes longer than the value set to TOOPWM lt PWMDUTY gt by 1 source clock When TOOMOD lt TFFO gt is 1 the period of the H level becomes longer than the value set to TOOPWM lt PWMDUTY gt by 1 source clock This function allows two cycles of output pulses to be handled with a resolution nearly equivalent to 8 bits No additional pulse is inserted when TOOPWM lt PW MAD gt is 0 Page 58 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use EZ SFR AAAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 4 Timer start Timer stop 4 TO01CR lt TOORUN gt TOOMOD lt TFFO gt Sawee UUU p JUU JUUN UUUUUUUUUUUUUUUUWUU gaa Overfiow TET ayy Count
121. t is released by turning the RESETB pin to H and the warm up operation that follows reset release gets started Note When the supply voltage is equal to or lower than the detection voltage of the power on reset circuit the power on reset remains active even if the RESEBT pin is turned to H 4 1 4 2 Power on Reset The power on reset is an internal factor reset that occurs when the power is turned on When power supply voltage goes on if the supply voltage is equal to or lower than the releasing voltage of the power on reset circuit a reset signal is generated and if it is higher than the releasing voltage of the power on reset circuit a reset signal is released When power supply voltage goes down if the supply voltage is equal to or lower than the detecting voltage of the power on reset circuit a reset signal is generated Refer to 4 2 Power on Reset circuit 4 1 4 3 Voltage Detection Reset The voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage has reached a predetermined detection voltage Refer to 4 3 Voltage Detection Circuit 4 1 4 4 Watchdog Timer Reset The watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer is detected Refer to 5 1 Watchdog Timer 4 1 4 5 System Clock Reset The system clock reset is an internal factor reset that occurs when it is detected that the oscillation enable register is set to a c
122. tain the latest version of product specification before placing your order Use of iMQO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use ez TR DARA iMO Technology Inc Title iMQ i87 User Manual Version V1 2 lt RTCRUN gt to 1 When RTCCR lt RTCRUN gt is set to 1 the binary counter for the real time clock starts counting of the low frequency clock When the interrupt generation interval selected at RTCCR lt RTCSEL gt is reached a real time clock interrupt request INTRTC is generated and the counter continues counting 5 5 4 2 Disabling the Real Time Clock Operation Clear RTCCR lt RTCRUN gt to O When RTCCR lt RTCRUND gt is cleared to 0 the binary counter for the real time clock is cleared to 0 and stops counting of the low frequency clock Page 82 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claim
123. the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use B22 BT RPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 When the warm up operation that follows reset release is finished the CPU starts execution of the program from the reset vector address stored in addresses OxFFFE to OxFFFF When a reset signal is input during the warm up operation that follows reset release the warm up counter circuit is reset The reset operation is common to the power on reset external reset input and internal factor resets except for the initialization of some special function registers and the initialization of the voltage detection circuits When a reset is applied the peripheral circuits become the states as shown in Table 4 1 During the warm up Immediately after the Built in Hardware During Reset operation that follows warm up operation that reset release follows reset release Program counter PC OxFFFE OxFFFE OxFFFE Stack pointer SP OxOOFF OxOOFF OxOOFF General purpose registers W A B C D E H L IX and IY Register bank selector RBS a i Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate a E i i C aaa Os
124. ting KWUCRn and P4PU Registers 3 7 3 2 Starting STOP Mode 3 7 3 3 Releasing STOP Mode 4 Reset Function 4 1 Reset Control Circuit Page 2 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use EZ SFR DARA SS iMO Technology Inc Title iMQ i87 User Manual Version V1 2 4 1 1 Configuration 4 1 2 Control 4 1 3 Function 4 1 4 Reset Signal Generating Factors 4 1 4 1 4 1 4 2 4 1 4 3 4 1 4 4 4 1 4 5 4 1 4 6 4 1 4 7 External Reset Input RESETB Pin Input Power on Reset Voltage Detection Reset Watchdog Timer Reset System Clock Reset Internal Factor Reset Detection Status Register How to Use P10 as an External Reset Power on Reset Circuit 4 2 1 Configuration 4 2 2 Function Voltage Detection Circuit 4 3 1 Configuration 4 3 2 Control 4 3 3 Function 4 3 3 1 4 3 3 2 4 3 3 3 4 3 3 4 4 3 3 5 Reading the 8 bit Up Counter Selecting the Voltage Detection Operation Mode Selecting the Detection Voltage Level Voltage Detection Flag and
125. tion voltage level h l I I i j I 1 i VDCR1 lt VD1SF gt e l lL l i i i l 1 Voltage detection interrupt request signal I l I NORMAL mode gt STOP mode i Warmup gt NORMAL mode 3 STOP mode Si lt Warm up ie NORMAL mode STOP mode is E STOP mode is i STOP mode is released at the activated by STOP mode is released at the falling edge of VDCR1 lt VD1SF gt falling edge of VDCR1 lt VD1SF gt programming programming activated by Figure 4 9 STOP Mode Release by VDCR1 lt VD1SF gt 4 3 4 Register Setting 1 When the Operation Mode is Set to Generate Voltage Detection Interrupt Request Signals When the operation mode is set to generate voltage detection interrupt request signal make the following setting In this case setting VDCR2 lt SRSS gt allows STOP mode to be released when the supply voltage VDD becomes equal to or higher than the detection voltage VD1LVL 1 Clear the voltage detection circuit interrupt enable flag to 0 2 Set the detection voltage at VDCR3 lt VDILVL gt Page 33 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s
126. unter continues counting up When T001CR lt TOORUN gt is set to 0 during the timer operation the up counter is stopped and cleared to 0x00 The PWMOB pin returns to the level selected at TOOMOD lt TFFO gt When an external source clock is selected the maximum frequency to be supplied is fegck 2 Hz in NORMAL1 2 or IDLE1 2 mode or fs 2 Hz in SLOW1 2 or SLEEP1 mode and a pulse width of two machine cycles or more is required at both the H and L levels Page 59 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 c Double Buffer The double buffer can be used for TOOPWM by setting TOOMOD lt DBEO gt The double buffer is disabled by setting TOOMOD lt DBEO gt to 0 or enabled by setting TOOMOD lt DBEO gt to 1 1 When the Double Buffer is Enabled When a write instruction is executed on TOOPWM during the timer operation the set value is first stored in
127. up When TO0O1CR lt TO1RUN2 gt is set to 0 during the timer operation the up counter is stopped Page 73 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMO from any and all damages claims suits or expenses resulting from such use ez TAR DARAS iMQ Technology Inc Title iMOi87 User Manual Version V1 2 and cleared to 0x00 The PWM1B pin returns to the level selected at T01MOD lt TFF 1 gt When an external source clock is selected input the clock at the TCOO pin The maximum frequency to be supplied is fegck 2 Hz in NORMAL1 2 or IDLE 1 2 mode or fs 2 Hz in SLOW 1 2 or SLEEP1 mode and a pulse width of two machine cycles or more is required at both the H and L levels Additional pulse 1 source clock Timer start y Duty pulse Duty pulse width width PWMDUTY PWMDUTY lt _ PWM1 pin output TFFO 1 i PWM1 pin output i TFFO 0 q ale g 256 counts 256 counts cyclewidth cycle width Figure 5 22 PWM1B Pin Output c Double Buffer The
128. value specified by the combined setting of TO1REG and TOOREG is indicated as TO1 OOREG and the 16 bit value specified by the combined setting of TOIPWM and TOOPWM is indicated as TO1 OOPWM The timer register settings are reflected on the double buffer or TO1 OOPWM and T01 00REG when a write instruction is executed on TOI1PWM Be sure to execute the write instructions on TOOREG TOIREG and TOOPWM before executing a write instruction on TOIPWM When data is written to TO1PWM the set values of the four timer registers become effective at the same time Page 76 82 The information contained herein shall not be changed without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMO Technology Inc Title iMOi87 User Manual Version V1 2 Set the initial state of the PPG1B pin at TOIMOD lt TFFI1 gt Setting TOIMOD lt TFF1 gt to 0 selects the L level as the initial state of the PPG1B pin Setting TOIMOD lt TFF1 gt to 1 selects the H level as the initial state of the PPG1B pin If the PPGIB pin is set
129. ves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless IMQ from any and all damages claims suits or expenses resulting from such use EZ SFR AAAS iMO Technology Inc Title iMOi87 User Manual Version V1 2 smaller than the up counter value the PWM1B pin is not reversed until the up counter overflows and a match detection is executed using a new set value If the value set to TO1 00PWM is equalto the up counter value the match detection is executed immediately after data is written into TO1 OOPWM Therefore the timing of changing the PWM 1B pin may not be an integral multiple of the source clock Similarly if TO1 OOPWM is set during the additional pulse output the timing of changing the PWM 1B pin may not be an integral multiple of the source clock If these are problems enable the double buffer When write instructions are executed on TOOPWM and TO1PWM in this order while the timer is stopped the set value is immediately stored in TO 1 00PWM y Timer start TOO1CR lt TO1RUN gt TO1MOD lt TFF1 gt S LEUE FUUUU UU UU UU UU UU UU UU UU Counter ad HOG HNC Nf 1 Write to TOOPWM Write to T01PWM ace maak B
130. with low active values such as STOP PWMO PWM1 PPGO PPG1 INTO INT5 DVO and so on are presented by ending with B in the content meaning bar for inversion Therefore they are written as STOPB PWMOB PWM1B PPGOB PPG1B INTOB INT5B DVOB and so on Besides to indicate certain bit name in a register the representation REGISTER_NAME lt BIT_NAME gt is used in this document For example ILL lt IL5 gt indicates the bit IL5 of the ILL Interrupt Latch register Page 6 82 The information contained herein shall not be changed without prior written permission of iMQ iMO reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAD iMO Technology Inc Title iMQ i87 User Manual Version V1 2 3 Central Processing Unit CPU 3 1 General Concept The introduction of the powerful central processing unit CPU of iMO i87 8 bit MCU core can be divided into eight major parts 1 Stack Area Pointer 2 Program Counter PC 3 General Purpose Registers 4 Program Status Word PSW 5 Low Power Consumption Function 6 Key on Wakeup
131. without prior written permission of iMQ iMQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BTRPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Note 1 The power on reset circuit may operate improperly depending on fluctuations in the supply voltage VDD Refer to the electrical characteristics and take them into consideration when designing equipment Note 2 For the AC timing refer to the electrical characteristics of each MO8S MCU datasheet 4 3 Voltage Detection Circuit The voltage detection circuit detects any decrease in the supply voltage and generates voltage detection interrupt request signals and voltage detection reset signals Note The voltage detection circuit may operate improperly depending on fluctuations in the supply voltage VDD Refer to the electrical characteristics and take them into consideration when designing equipment 4 3 1 Configuration The voltage detection circuit consists of a reference voltage generation circuit a detection voltage level selection circuit a comparator and control regist
132. x register the SP register can be modified by using load store and ALU instructions The SP register can also be used as an index register in Indexed Addressing When interrupt When CALL or is aiana When RET When RETI or CALLY is axecuted SWI is executed is executed RETN is executed 0x0013C 0x0013C 0x0013C 0x0013C 0x0013D 0x0013D 0x0073D 0x0013D 0x0013E 0x0013E 2 0x0013E 1 0x0013E 0x0013F 1 0x0013F 1 0x0013F 0x0013F Bafore Bafore a PC and PSW in the stack Pushing and popping 0x00040 The stack grows downwards T OxOFFFF b Direction in which the stack grows Figure 3 2 Stack Page 8 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMQ to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 SBT RPARAD iMQ Technology Inc Title iMOi87 User Manual Version V1 2 3 3 Program Counter PC 3 3 1 Program Counter PC The Program Counter PC is an 8 bit register that holds the address of next instruction to be executed in the code area When the reset signal is released the C
133. xOFD4 4 6 0 Bit Symbol WDTOUT Page 35 82 The information contained herein shall not be changed without prior written permission of iMQ iMOQ reserves the right to change the information in this document without prior notice Please contact iMO to obtain the latest version of product specification before placing your order Use of iMO devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless iMO from any and all damages claims suits or expenses resulting from such use 22 BT RPARAG iMO Technology Inc Title iMQ i87 User Manual Version V1 2 Read Write R R W After reset Enable disable the 0 Disable watchdog timer 1 Enable 00 The 8 bit up counter is cleared by writing the clear code at any point within the overflow time of the 8 bit up counter 01 A watchdog timer interrupt request is generated by writing the clear code at a point within the first quarter of the overflow time of the 8 bit up counter The 8 bit up counter is cleared by writing the clear code after the first quarter of the overflow time has elapsed Set the clear time of the 8 bit 10 A watchdog timer interrupt request is generated by writing the up counter clear code at a point within the first half of the overflow time of the 8 bit up counter The 8 bit up counte

i87 User Manual i87 User Manual V1.2

Contents

Download Pdf Manuals

Related Search

Related Contents