User Manual for SMT784 - Sundance Multiprocessor Technology Ltd.
Contents
1. F 2 Es a LE Z EEEE SEJ d4 66b 6666646 LE E EEEE EEJ LE EEEE E EE LETEZETT LE Z EEEE SEJ T EELEE x T at amp ED sos 0000000008 e ett EEJ EELEE Figure 10 Bottom side of SMT700 Carrier 8 3 Side of 384 Mezzanine Figure 11 Top side of SMT384 Mezzanine Connector name silkscreen Description Location on the board and wass s ADCCAndogimput Right us Reference input _ cJ external Clock input _ Reference Output Top Right Clock Output Top Right saa ermal Tigger ADCASB Bottom Left qus Trigger ADCCSD Bottom Let 8 4 Bottom Side of 384 Mezzanine d LH LI a Ne om a a 2 a a LE Figure 12 Bottom side of SMT384 Mezzanine 9 Power and Thermal 9 1 Power Dissipation PXI Express chassis receiving the SMT 784 system should provide enough forced air flow in order to dissipate the heat generated by the modules The air flow must be going against gravity or upwa2. 449 2 2 2 6 H 28 Bottom Side of SMT384 Mezzanine 29 Power and Thermal t LLL LL Lu uu 30 Power DissipatiOn 30 MERE R 31 EMC msn mon onn RO 31 Physical Proper 6S III iISiiIISSSIIKIs s 31 Ordering InformiatOD aoc lll uuu u u usss 31 Table of Figures FIgUre le SM ZOO BLOCK DEO EU 9 Figure 2 SMT384 Block Diagrami u u uu 10 Figure 3 TAG pin out lll rra noon ai rr OR ac d 11 FIGHT Cock DOIDO ON y o u anata u ua nus 14 Figure ADC Data NOW 18 Figure 6 Software Interface tO Firmware 19 CS SIA 22 Figure 8 ANALYSIS mM 24 Figure 9 Top sid er SMI 700 COETIGI 26 Figure 10 Bottom side Of SMT 700 Carrier 27 Figure 11 Top side of SMT384 Mezzanine 28 Figure 12 Bottom side Of SMT384 Mezzanine 29 Foure 3 30 CaE DISSID abl NS 5 5 ae te Dane 30 List of Tables Table Glock u 15 9518 ADE Characteri aa ne dr a a ua 16 Table 3 Common Configurations of Sw
3. Unit Module Description Quad ADC 14 bit 125Msps System Unit Module Number SMT 784 Document Issue Number SS Original Author C H Gray User Manual for SMT 784 Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HP5 1 5 This document 1 the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2009 Certificate Number FM 55022 Revision History K Changes Made Original Document 19 03 09 Table of Contents 1 IntrOGCU C iO uu uu 6 2 Related Doc mentek uu u A Lu u 7 2 1 Referenced Documents l nn 7 22 AAppleoble DOCUMENTS u u Y 7 3 Acronyms Abbreviations and Definitions 8 34 Acronyms ADDrevViatiOnsS scandium 8 DST MITT 8 4 Functional Description 9 Al BOCK DIO 1 n s u uuu uu 9 5 System OVeEFVIGU uuu u u Tanu asna 11 us 11 ov B eee us 12 12 5 4 Front Panel Fibre Optic Modules 12 5 5 Front Panel RJ 45 Connector Ethernet 12 5 6 Front Panel SATA 5 u u u
4. be accessed at this point through the USB interface but if the PCI is to be recognized by the Host again there must be either a re boot of the PC or the equipment must be un installed then re installed as follows Connect a USB cable to the SMT 784 and start the SMT6002 Flash Utility for FPGA only Modules The system will appear in the utility as SMT700 through the PCI interface and as an SMT148 FX through the USB interface The TIM type will appear as an SMT35IT xxxx depending upon type of FPGA on carrier Select the interface of choice as noted in the above step PCI PCle or USB Two bit streams will be found in the flash the first is the default firmware for the SMT700 while the second bit stream at address 0x800000 is where the SMT784 configuration is stored These are selectable by SW1 POS 2 at boot Select the second bit stream delete and re assign the updated or custom firmware you have designed at user address 0x800000 Select Commit Once the firmware has been loaded into flash reset the board using SW1 POS l by turning it on then off to reconfigure the FPGA with the new bit stream check SW1 settings To make the board visible again to the Host right click My Computer and select Manage Under Device Manager select SMT700 under Sundance Right click disable click okay Right click SMT700 again select enable This will cause the PCI PCle address and resource allocation of the device
5. count the second SHB connector shares the PCI interface signals with the FPGA For this reason this SHB interface and the cannot be operated simultaneously unless a PCI express core is implemented in firmware 5 11 LEDs Two front panel LED s are available and connected directly to the FPGA A heartbeat Signal present indicates the FPGA has been configured correctly User Manual S Page 13 of 31 Last Edited 19 03 2009 14 12 00 5 12 Clock Distribution There is one integrated clock generator on the mezzanine module AD9510 Analog Devices The user can either use this clock on board or provide the module with an external clock input via MMCX connector ADCs can all receive the same clock or the integer multiple of it x2 x3 x32 the maximum being 125MHz for each ADC This clock can be coming from the on board VCXO or from an external source An extra connector outputs the reference clock for multiple module systems ADC Channel A ADC ChA ADS5500 TI A ADC Channel ADC ChB ADS5500 Tl Clock Distribution External Reference Analog Devices OUT1 ADC Channel C ADC ChC ADS5500 TI Clock In AD9510 14 bit 125MSPS OUTO ADC Channel D ADC ChD ADS5500 TI 14 bit 122MSPS OUT5 External Clock Out Multi module lt Synch Ref Clock Y Dual clock 2 to 1 mi SN65LVPC23 2 LVPECL Clock Signals k Single ended Signals External Clock O
6. to be discovered again as an 5 700 with the new firmware installed User Manual SMT784 Page 25 of 31 Last 8 5 784 Board Layout 8 1 Side of 5 700 Carrier FPGA DCDC RSL amp SHB header converters connectors sssssss Fibre module eee EE nes mm m mmmmmmmm ELLEI EI SATA jo 2 ene LEDs pamm Ethernet gum e USB RR m interface FPGA encryption DDR2 Virtex 5 Optional SHB connector Figure 9 Top sid of SMT700 Carrier 8 2 Bottom Side of 700 Carrier Ethernet PHY Flash memory eee 22 m a nm a f 1 442 IB e Y ET u e se Fibre module optional SLB data and power connectors on LE a w H as se a m m B NH J P m E De DDR2 memory 4 55959 E amp 5b amp 5 9 7999 amp tte ee o o o ses 2 te ee o o5 amp res 5 958559 9999 hit LAN EE E t t t O
7. FPGA s high speed serial links 3 2 Definitions 4 Functional Description 4 1 Block Diagram The major elements of the SMT 784 be broken down into the two main modules it is comprised of the SMT700 and SMT384 5 700 PXle carrier board block diagram can be viewed below 5 700 Block Diagram DDR2 1GByte 220MHz 64 bit data 19 address 13 control Ethernet 2 x 2 5Gb s serial links 8 x 2 5Gb s serial links FPGA Virtex5 LXT 50 FF1136 package 2 x 2 5Gb s serial links Ext clk 1 5GHz SATA 2 5GHz RSL PXle ref USB PETT 4 x 2 5Gb s serial links RSL Connector 4 lanes of 2 5Gb s Front Panel Connector mmy Rear Card Connector Figure 1 SMT700 Block Diagram The SMT 384 block diagram can be found below Power Supplies 3 3v and 54 Volts 12v Dc Temperature Sensors ADC Inguf Ch A MGX 50 Ohm ADC Inguf Ch B MCA 50 Ohm Channel Signal Conditioning Channel B Signal Conditioning External Clock In MMCX ADCs External Clock MMCX Extarnal Reterence Clark Cut External Reference Clock In MMCX ADS Input Ch C MMCX 1 0 ADG Input Gh D MMCK EJ Ohm Channel C Signal Canditianirg Channel D Signal Condiianirg ADSS5O0 ADC Ch 14 125MS PS ADS5500 ADC ChB 14 08 T25MSPS PECL Clock innaration and Distribution VLC coupled with AD3510
8. FPGA types speed grades clock speeds and signal coupling are available Please contact Sundance for further information 14 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it 1 installed within an adequate host system This module ts protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot User Manual SMT784 Page 31 of 31 Last Edited 19 03 2009 14 12 00
9. L One Comport X Link interface is used between the CPLD and Flash to the Host a second Comport link is used to access the 5 384 registers for control and data acquisition and one RSL connects directly to the connector on the front of the PCB A more detailed explanation of the communication resources that Sundance utilizes can be found in the SMT6400 and SMT6500 A Xilinx PCI PCle IP core is used to allow data transfer between the Host machine and the X Link 6 2 Xilinx PCI Core The PCI core supports target accesses and initiator accesses Data transfers are implemented using initiator accesses to ensure maximum bandwidth For this purpose a DMA engine is connected to the X Link and the PCI core to transfer the data The PCI PXIe interface used this design was generated by using the Xilinx Core Generator core version 4 8 included with ISE 10 1 Foundation software The user is free to implement the included netlist into custom firmware but if there is a need to re generate the core the full license must be purchased from Xilinx Licensing information and how to purchase this core can be found at the Xilinx website www xilinx com 6 3 Software Driver 5 784 is supported by the SMT6300 providing the Windows driver for the board 6 4 Carrier Board Registers the addressable resources are located in the BART register communication resources are presented to the host machine as X Link inter
10. T384 mezzanine Future expanded functionality can be achieved as well by utilizing any one of Sundance s long line of other mezzanine modules e Front panel SATA connectors carrying Virtex 5 serial interfaces e Front panel 45 for gigabit Ethernet e Front panel Fibre Optic modules carrying Virtex 5 Serial interfaces e Sundance Rocket Serial Link RSL connector with 4 serial interfaces e Front panel USB interface to allow re programming of the flash memory e Four 14 bit 125MSPS analogue to digital converters e Flexible on board low jitter clock generation e One external clock external triggers and one reference clock via MMCX connector e All analogue inputs to be connected to 50 ohm sources loads e Mezzanine module temperature sensors User Manual SMT 784 Page 6 of 31 Last Edite 2 Related Documents Sundance RSL specification RSL Xilinx Virtex5 datasheets Xilinx Virtex5 Texas Instruments ADS550 ADC datasheet ADS5500 Analog Devices AD9510 datasheet AD9510 Sundance High speed Bus SHB specifications SHB Sundance LVDS Bus SLB specifications SLB TIM specifications TIM MMCX specifications Surface Mount MMCX 2 1 Referenced Documents SMT 384 User Manual X Link Documentation 2 2 Applicable Documents 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations Sundance commonly used acronyms MGT GTP RSL are all used interchangeably and refer to the
11. and SN85LVPC23 AD 55506 ADR tbr 128 5 5 ADS3500 ADG Cho 14 bit 124 8 ChA 14 FeedBack Chock Che 0878114 ChE Data 141 Exiemal Trigger ADCC and ADCO Figure 2 SMT384 Block Diagram Daughber Card interface cannectar Power Daughter Card cannectar SLB 5 System Overview 5 1 FPGA The SMT784 uses a Xilinx Virtex 5 LXT or SXT to implement in firmware the interfaces the board provides Configuration of the FPGA is from one of two sources on board flash memory or a Xilinx J header connector 1 specifically dedicated for FPGA and CPLD detection and programming Both the CPLD and the FPGA are part of the JTAG chain A 14 position 2x7 connector 2mm 15 available and shows TDI and TMS lines well as a ground and a reference voltage as shown below 0 248 GND GND GND GND GND GND GND 0 020 0 5 mm SQ TYP Figure 3 JTAG pin out This connector has been chosen because it can connect easily to a Xilinx Parallel IV cable using the ribbon cable provided by Xilinx 5 2 SLB Connector The SLB connector is the interface used to connect the SMT700 carrier board to the SMT384 mezzanine module For a map out of SLB pin connections specific to this system please refer to the SMT384 user guide This connector is mounted on the reverse side of the board The SMT 784 occupies two slots a rack with the carrier
12. ation words to the four ADC s and clock registers inside the FPGA The behaviour of these registers is thoroughly described in the user manual for the SMT 384 The Test Register on the FPGA is then written to verify proper read write action over the X Link Comport Data is then captured from the ADC s and stored in text files relating to the ADC channel A capture txt B capture txt etc If the program is successful you should see the following screen IPETETETETETETETETIVISIETITI I I RR I I I2 2 2 2 25 System ELE E hE ERE RE RE RE ERE RE RE RE RE RE ADC and Clock registers Register 6x2 Register 6x85 Register 68 Register Register Hx3H Register x31 Register 6x32 Register 6x33 Register 6x34 Register 6x35 Register 6x36 Register 6x37 Register 4x38 Register 6x34 Register Hx3h Register Hx3B Register Bx3G Register Hx3D Register Hx3E Register Bx3F Register 6x48 Register x41 Register 6x42 Register x43 Register 44 Register 6x45 Register 6x46 Register Hx47 Register 4 amp Register 47 en Pa EI m W GS Fon 3 1 HH Writing test counter to Axi Test Register B errors status Firmware Acquiring data Check fl capture txt Acquiring data Gheck B capture txt Acquiring data Gheck G capture txt Acquiring data Ghe
13. ck D capture txt Speed Test Transfer duration 2765 ms Speed 6H677 KB s Figure 7 SMT784 exe The captured data samples can then be viewed and or manipulated through the users preferred application The provided MATLAB script file ANALYSIS m provides an easy way to load and view the captured information through MATLAB User Manual SMT 784 Page 22 of 31 Last Edited 19 03 2009 14 12 00 7 2 Host Control of 784 The provided sample program was created with Microsoft Visual C and the Sundance SMT6026 software development kit In this example the write function writeword uses the function HostWrite to write to the registers of the FPGA while readword USes HostRead to read the registers or data back through the X Link void writeword HOST LINK hostlink int value pSmt384 gt HostWrite amp value sizeof value hostlink void readword HOST LINK hostlink int ptr pSmt384 gt HostRead ptr sizeof int hostlink Using readword can return control register information or samples from the ADC s Which type of data to be read from the FPGA is selected by writing to register oxic the remaining control registers are exactly as described in the SMT384 User Manual By writing 0 0000 to regiser 0x1C readword Will return register contents information oxocoo will return raw data from channels and B and will return raw data from channels C and D It is important to remember the FIFO s are held a
14. faces The addresses of the X Link and the number of X Link are available from the X Link table of content found in the firmware The other registers available in the firmware are the following Reset register 1 0x00000000 Writing 1 to the reset register will cause the SMT70O to be reset The reset is de asserted automatically after a few milliseconds X Link table of content 1 0x00001000 Refer to the X Link documentation for details concerning the table of content and for a description of the registers in the X Link User Manual S Page 20 of 31 Last Edited 19 03 2009 14 12 00 7 Sample Host Control and Data Capture 7 1 Getting Started The sample program SMT784 exe can get the user started with the equipment by executing some of the simpler functions available from the SMT 784 system Setup e Connect the 50 ohm output of a signal generator to the ADC channel inputs 3 6 7 11 on the mezzanine module Sundance provides convenient 50 ohm terminated splitter for inputting a single source through the SMT594 e Turn on the computer Verify heartbeat signal flashing on the front panel LED s This is derived from the bus clock and indicates the FPGA is configured correctly e Execute SMT784 exe This will store a 16K sample capture from each of the ADC s to a text file in the same folder as the executable The program begins by sending control and configur
15. h address 0x0 while off selects the SMT 784 firmware flash address 0 800000 The SMT 700 default firmware is provided as a backup bit stream the event that user modified firmware at address 0x800000 in flash does not work as expected Sundance therefore suggests that when writing custom firmware to flash do not write to address OxO only write to address 0x800000 User Manual SMT784 Page 17 of 31 Last Edited 19 03 2009 14 12 00 5 15 ADC Data Flow The flow of ADC data the SMT 784 14 bit data 32 bit ASB N FIFO data amp clack 16K deep 32 bit ab samples control SMT384 registers for ADC s and clock control Xlink Comport 14 bit data amp clock a2 bit C amp D data amp clock FIFO 16K deep 32 bit cd samples Figure 5 ADC Data Flow The Control Registers contained in the FPGA control SMT384 control the complete functionality of the SMT384 Registers are written to from the PC via the X Link interface Contents of the registers or samples from the ADC s can be read back from the FPGA by choosing which output is desired By changing the default firmware samples from the ADC s can optionally be routed to the RSL links SHB SATA etc Details of the registers functions word format and a memory map of the FPGA can be found in the SMT384 User Guide Serial control signals are routed from the registers to the ADC s and to the clock distribution sys
16. itch LL 17 Table d Register 0OX1C Data Control 4 23 1 Introduction SMT784 is a Virtex 5 based PXI form factor system utilizing Sundance s SMT70O carrier board and the SMT384 quad 125MSPS ADC mezzanine board The SMT700 implements up to eight 2 5 Gigabit PCI Express lanes allowing a maximum data transfer of 2 gigabytes per second It also implements optionally a 32 bit 33 MHz PCI interface As a standard the ADCs are all AC coupled RF Transformers but can also be optionally DC coupled TI opamp THS4509 ADC configuration sampling and transferring modes are set via internal control registers stored inside the FPGA and accessible via a Comport interface The front panel interfaces make inter system capabilities extremely extensive while the ADC s and configurable clock distribution attached to the mezzanine module SMT 384 make processing raw data fast and simple to configure Together the SMT784 is a powerful system for capturing and manipulating data at high speeds Main features of system e Xilinx Virtex 5 in an FF1136 package Supports LX50T LX85T SX50T or LX110T SX95T e FPGA configuration from flash 64MB using a Xilinx Coolrunner CPLD e One 64 bit wide data bank of DDR2 memory The bank uses 4 16 bit wide devices Running this memory at 220MHz provides a maximum access speed of over 3 5Gbyte s e Sundance LVDS Bus SLB connector for interfacing the 5 700 carrier with the SM
17. n board Er 3 In ADCs vee 245 76 MHz External Clock Out ADCs Figure 4 Clock Distribution The main characteristics of the mezzanine clocks are as follows User Manual SMT784 Page 14 of 31 Last Edited 19 03 2009 14 12 00 External Trigger Inputs Input Voltage Level 1 5 3 3 Volts peak to peak DC coupled and Single ended Termination implemented at the connector Differential on option 3 3 V PECL Frequency range 62 5 MHz maximum Format Ext CIk In to Ext CIk Out 1105 between J29 and Table 1 Clock Characteristics 5 13 ADS5500 ADCs The main characteristics of the mezzanine ADC s are as follows Analogue Inputs AC coupled option 2 4 Vpp 11 5 dbm 500 Full scale AC coupled via RF transformer Input voltage range DC coupled option 1 15 Vpp Gain amplifier 6dB centred at 0 DC coupled via amplifier Gain can be adjusted to required input amplitude centred at 0 Min gain 6dBs which should allow an input swing 0 575V as full scale ADC single ended inputs to be connected to 500 source Source impedance matching implemented between RF transformers and ADC Input Impedance 50 Ohm Termination implemented at the connector External Sampling Clock Input External Trigger Inputs Input Voltage Level 1 5 3 3 Volts peak to peak User Manual SMT784 15 of 31 Last Edited 19 03 2009 14 12 00 DC coupled and single ended terminated at connecto
18. ors 4 lanes to an RSL connector two lanes to Fibre Modules and two lanes to front panel SATA connectors For FPGAs with only 12 GTPs high speed serial ports no lanes are available on the RSL connector The default firmware provides Host access straight to the RSL connectors through the RSL X Link interface User Manual SMT784 Page 12 of 31 Last Edited 19 03 2009 14 12 00 5 8 Flash This 64Mbyte memory contains the configuration bit streams for the FPGA The flash contents may be programmed via the PCI PCle interface or via USB by using the SMT6002 5 9 CPLD and FPGA Configuration This Xilinx CPLD is capable of configuring the FPGA using data provided from the flash memory The CPLD itself should not need to be re programmed but if needed it can only be accessed by JTAG using Xilinx IMPACT The CPLD also interfaces to a Cypress USB device This interface allows an easy option for upgrading the FPGA configuration stored in flash using the SMT6002 The USB mechanism to re program the flash is always present and does not rely on the FPGA being configured This can be advantageous if the FPGA configuration has been updated with a non working PCle interface 5 10 SHB Two Sundance SHB connectors are fitted as standard Each connector has the ability to carry a 32 bit data bus with a data rate of 133MHz A dual 16 bit interface option is alSo supported One SHB 15 connected directly to the FPGA To save on pin
19. portion of the system residing on the central card guides i e there will be a whole slot width for the FPGA memory etc and another slot with the SMT384 mezzanine 5 3 DDR2 Four devices are used to implement this memory A 220MHz 64 bit data bus 1 used to transfer data at over 3 5Gbyte s Xilinx provides performances of DDR2 interface as being 200MHz for a 1 part 267MHz for a 2 part and 333MHz for a 3 part Future releases of the firmware will allow for Host application access of the memory provided 5 4 Front Panel Fibre Optic Modules Two FPGA serial interfaces are presented here using Stratos Lightwave 568 LxK LT12x modules These interfaces support 2 5Gb s operation Note that only one device is fitted as standard due to the fact that the second module fits on the reverse of the SMT700 PCB Not all variations of the SMT7xx series can support two modules 5 5 Front Panel RJ45 Connector Ethernet A single RJ45 connector provides a 10 100 1000 Ethernet interface The 45 connects directly to a Marvell 88E1116 PHY which is interfaced to the FPGA 5 6 Front Panel SATA Connectors Two SATA style connectors are provided on the front panel Each connector carries a single FPGA serial interface As standard these interfaces do NOT provide SATA connectivity 5 7 RSL The LXT SXT series devices from Xilinx provide up to 16 high speed gt 3Gbps serial links The SMT784 connects 8 lanes to the PXle connect
20. r Differential an 3 3 V PECL Impedance Ohm Frequency range 62 5 MHz maximum ADCs Output 2 s Complement or offset binary Data Format Changeable via control register Table 2 ADC Characteristics 5 14 Switch 1 Flash Settings The following table represents the various switch settings for switch 1 PCB configured to FPGA can be Flash access Is boot from flash and configured via bit available for allow for serial stream uploaded on RD WR only via RD WR through the USB link the USB link using SMT 6002 Diamond Server the SMT6002 condition Table 3 Common Configurations of Switch 1 Switch 1 SW1 the front side of the SMT 784 controls flash read and write access for the carrier board as well as selecting which flash address to boot from POS 1 sends a hard reset to the CPLD instructing it to reconfigure the FPGA according to which address flash is selected The combined positions of POS 4 and POS 3 tell the CPLD how the FPGA Is to be configured at power up according to Table 3 After power up a new bit stream can be sent via USB by using Diamond Server or by first uploading the new firmware to flash with the SMT6002 then performing a reset with POS 1 POS 2 selects which address in flash the CPLD 1 going to configure the FPGA from The flash address contents can be viewed and written to by using the SMT6002 POS 2 ON boots from the backup SMT 700 firmware flas
21. rds as specified in the Specification It is also specified that a 3U PXI Express module should not dissipate more than 30 Watts of heat The following picture shows the direction of the forced air flow across a 3U PXI Express module Figure 13 3U Heat Dissipation The estimated maximum power consumption of the Virtex5 FPGA is 22W This assumes a design running at 500MHz with all DSP slices used of the devices on the SMT 784 derive their power from the 12V PXI power rails It is strongly advised as applications vary considerably to use the Xilinx power estimator tools available from this link Xilinx Power Design Solutions 10 Safety This module presents no hazard to the user when in normal use 11 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module ts protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot 12 Physical Properties Dimensions zemxixmxam wes supply Voies x a ew a ww 13 Ordering Information Several variations of this product are available Various
22. script ANALYSIS m the samples stored on the text files may be viewed The following is a zoomed in view of a test run using channels C and D with a 2MHz analogue signal sampled at 33Mhz and a 4096 point FFT 11000 10500 10000 9500 9000 8500 8000 7500 3000 3050 3100 3150 3200 3250 3300 3350 3400 400 110 221350 140 150 170 180 190 Raw data captured from ADC C FFT of ADC C data 11000 10500 10000 9500 9000 8500 8000 7500 OER Led ou ea ee ay 5050 6100 6150 6200 6250 6300 6350 6400 6450 90 100 110 120 130 14 140 150 150 170 180 190 Raw data captured fram ADC D FFT of ADC D data Figure 8 ANALYSIS m 7 4 Uploading Firmware to Flash A good guide for how Sundance firmware 1 typically modelled can be found the SMT6500 chm help files The firmware provided may be updated from time to time or can be modified as desired to implement different functionality into the FPGA For example data flow can be stored in DDR memory output to the SATA connection SHB Ethernet Fibre transceiver etc PCI PCle controller for the SMT784 is in VHDL wrapper within the Virtex5 FPGA The SMT6002 Flash Utility can access the system s flash either through this PCI PCle core or USB cable as the SMT148 FX Currently this means that change to the firmware and hard reset from SW1 will cause the FPGA to reconfigure from flash and lose the PCI PCle interface The flash can still
23. t reset while register information is being read back from the Comport This allows a quick empty of the FIFO for reading status and keeps data from being lost 0x0000 Resets all ADC sample FIFO s Reading words back returns the contents in the registers address Channel data is sent from the sample FIFO s The 14 bit sample from each channel 15 returned in a concatenated single 32 bit word as 00 14 bit B sample 00 14 bit A sample 0 0800 Channel C and D data is sent from the sample FIFO s The 14 bit sample from each channel is returned in concatenated single 32 bit word as 00 14 bit D sample 00 14 bit C sample Table 4 Register Ox1C Data Control For example writeword cp 0x101C0000 registers readable clear FIFO s for 0 k 255 readword cp amp value Empty FIFO writeword cp 0 101 0 00 Channels A amp B binary out selected User Manual S Page 23 of 31 Last Edited 19 03 2009 14 12 00 In this instance the first writeword places the ADC FIFO s in reset and configures the oxic register to return register contents information to the Host when a readword IS performed The looped readword command empties samples remaining the FIFO and the final writeword configures the SMT 784 to send samples from channels A and Bin straight binary format to the Host 7 3 Viewing the Samples By using the provided MATLAB
24. tem for desired configuration Samples and the clock output from the ADC s are then combined onto two different 32 bit buses one containing samples from channels A and B the other bus containing samples from channels C and D In order to prevent loss of data a 16K buffer is implemented to feed the samples to the control SMT384 block When control registers are programmed to be returned to the PC selected by Host application the ADC FIFO s are held in reset Upon selection of the desired channel output the buffer resumes operation 6 Software Interface 6 1 Functional Diagram The following diagram shows functionally how the SMT784 works The hashed portions will be available in future releases of the firmware The Host accesses a number of communication resources via the PCI bus All communication resources are presented as X Link software interfaces and are memory mapped in the memory space of the Host processor Figure 6 Software Interface to Firmware The firmware inside the FPGA implements the communication interfaces required to allow the data transfer between the SMT 784 and the Host PCI PCle The host transfers data with the SMT784 using the X Link There is one X Link instantiated per communication resource Flash SMT384 DDR RSL the X Link interfaces are connected to the PCI PCle core and can be accessed from the Host The default firmware currently provides two communication resources types Comport and RS
25. xu uu u a S 12 RO 12 nn u 13 59 CPLD arid FPG CODITIUP ation a a a us 13 I 5 13 LED uns sn nsn a ea 13 S42 COCK DISUHDEDPIDE u 77777777 14 5419 AD55500 BIO M O 15 5 44 SWiteh L Flash Se EI ea a x 17 5 15 ADC Data F oW 18 6 Software Interface u 19 OL F ncuosal DISOFdalEbsssensevosindmevndizen ditt pr 19 m E 20 SOW uu 20 Caa Boara REGI TE uuu 20 7 Sample Host Control and Data Capture 21 Fok AGEING S OU a ed de a de A D ete 21 1 2 OSE COMO OF SMT 794 uuu uuu u ed a nus 23 7 3 Viewing the Samples 24 7 4 Uploading Firmware to Flash lll lll l l lll ll li 24 8 SMT 784 Board uu uuu u uuu u uuu u u u aasia 26 User Manual SMT784 _ Page 3 of 31 Last Edited 19 03 2009 14 12 00 8 1 8 2 8 3 8 4 9 9 1 10 11 12 13 14 Top Side Of SMT 700 Carrier 26 Bottom Side or SMI 700 27 Top Side Of SMT384 1
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