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3807 Group USER`S MANUAL

1. Fig 2 4 12 Example of output data table 3807 GROUP USER S MANUAL 2 69 APPLICATION 2 4 Real time output port Figure 2 4 13 shows the waveforms which are output from RTPo to RTP7 as a result that the Timer A and the Timer B are operated by using the data of Figure 2 4 10 to Figure 2 4 12 This timing chart is for the case where the Timer A controls operation pattern 1 and the Timer B controls operation pattern 3 A constant motor speed Acceleration 20 steps 200 steps Deceleration 20 steps gt lt A constant motor speed Acceleration 20 steps 100 steps Deceleration 20 steps Fig 2 4 13 Timing of Real time output 2 70 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Figure 2 4 14 shows the setting method and output timing for the Timer A The same setting method is used even for the Timer B Before the count of the Timer A is started initial values t1 t2 are set in the Timer A1 latch and the Timer AO latch After the count of the Timer A is started the timer value t3 is updated in the Timer A interrupt processing routine The next latch is automatically specified each time a value is set in the timer so it is not necessary to specify a write latch in bit 7 of RTPCON1 when the timer value is updated In this application example the real time output port is switched over to the programmable I O po
2. M38073E4 XXXFP 16384 80P6N A One Time PROM version M38073E4FP 16254 One Time PROM version blank M38073E4FS 80D0 EPROM version 3807 GROUP USER S MANUAL 1 7 HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit CPU The 3807 group uses the standard 740 family instruction set Refer to the table of 740 family addressing modes and machine instruc tions or the SERIES 740 lt Software gt User s Manual for details on the instruction set Machine resident 740 family instructions are as follows The FST and SLW instructions cannot be used The MUL DIV WIT and STP instruction can be used The central processing unit CPU has the six registers Accumulator A The accumulator is an 8 bit register Data operations such as data transfer etc are executed mainly through the accumulator Index register X X Index register Y Y Both index register X and index register Y are 8 bit registers In the index addressing modes the value of the OPERAND is added to the contents of register X or register Y and specifies the real address When the T flag in the processor status register is set to 1 the value contained in index register X becomes the address for the sec ond OPERAND b7 bO PCL b7 bO NIV T BD I Z C Stack pointer S The stack pointer is an 8 bit register used during sub routine calls and interrupt
3. eesessssss 71 e The minimum instruction execution time 0 5 us at 8 MHz oscillation frequency iurc sted ROM a Een redes 8 to 60 K bytes RAM sosa lao 384 to 2048 bytes e Programmable input output ports esee 68 e Software pull up resistors Ports PO to P2 sss 24 e Input ports Ports P63 and P64 e ntermupts ici ss 20 sources 16 vectors AS A TO 16 bit X 2 e Timers A B for real time output port function 16 bit X 2 e Timers 1 9 iones teles t dee 8 bit X 3 PIN CONFIGURATION TOP VIEW RTPs RTP7 ONW RESETour CKour SYNC WR ADo AD 7 RD 4 P33 Serial 1 01 UART or Clock synchronized 8 bit X 1 Serial 1 02 Clock synchronized sssss 8 bit X 1 A D converter 8 bit X 13 channels DA CONV moins emnes 8 bit X 4 channels Watchdog ter oo ox tercera raten data 16 bit X 1 Analog comparator scere nm coe 1 channel 2 Clock generating circuit Main clock XIN XOUT Internal feedback resistor Sub clock XciN Xcour Without internal feedback resistor connect to external ceramic resonator or quartz crystal oscillator Power source voltage In high speed mode nns 4 0 to 5 5 V at 8 MHz oscillation frequency and high speed selected In middle speed mode
4. Not used returns 0 when read Timer Y mode register TYM address 002816 Timer Y operating mode bits b2 b1 bO 0 0 Timer event counter mode Pulse output mode Pulse period measurement mode Pulse width measurement mode Programmable waveform generating mode Programmable one shot generating mode PWM mode Not used 22220000 Timer Y write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Output level latch 0 L output 1 H output CNTR1 active edge switch bit 0 Event counter mode counts rising edges Pulse output mode output starts with H level Pulse period measurement mode measures between two falling edges Pulse width measurement mode measures H periodes Programmable one shot generating mode after start at L level output a H pulse interrupt request is triggered on falling edge Eevent counter mode counts falling edges Pulse output mode output starts with L level Pulse period measurement mode measures between two rising edges Pulse width measurement mode measures L periodes Programmable one shot generating mode after start at H level output a L pulse interrupt request is triggered on rising edge Timer Y count source selection bits b7 b6 0 0 f XiN 2 0 1 f Xin 16 1 0 f Xcin 1 1
5. sse 2 89 2 7 2 CD changer car audio application example 2 90 2 7 3 Hot water washing toilet seat application example ssssssseess 2 91 3807 GROUP USER S MANUAL List of figures CHAPTER 3 APPENDIX Fig 3 1 1 Circuit for measuring output switching characteristics 1 ssessssse 3 11 Fig 3 1 2 Circuit for measuring output switching characteristics 2 ssssssss 3 11 Fig 3 1 3 Timing diagram 1 in single chip mode seseHHH 3 12 Fig 3 1 4 Timing diagram 2 in memory expansion mode and microprocessor mode 3 13 Fig 3 1 5 Timing diagram 3 in memory expansion mode and microprocessor mode 3 14 Fig 3 1 6 Timing diagram 4 in memory expansion mode and microprocessor mode 3 15 Fig 3 1 7 Timing diagram 5 in memory expansion mode and microprocessor mode 3 16 Fig 3 2 1 Power source current characteristic example sssssseee 3 17 Fig 3 2 2 Power source current characteristic example in wait mode 3 17 Fig 3 2 3 Standard characteristic example of CMOS output port at P channel drive 1 Fig 3 2 4 Standard characteristic example of CMOS output port at P channel drive 2 Fig 3 2 5 Standard characteristic example of CMOS output port at N channel drive 1 Fig 3 2 6 Standard characteristic example of CMOS output port at N channel drive 2 3 19 Fig 3 2 7 Standard characterist
6. Timer A High order Address 3016 Timer A High order Address 3016 TAH A216 TAH 0316 042116 Timer A High order Address 3016 Timer A High order Address 3016 040016 TAH 4816 TAH 0416 O3EE16 03E716 27pps 488pps y e _ Fig 2 4 10 Example of timer table for acceleration and deceleration 2 68 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Figure 2 4 11 shows an example of operation pattern table to operate the motor by the operation patterns shown in Figure 2 4 9 The total number of operation patterns the direction of motor rotation and number of steps at a constant motor speed are set in this table The motor can be rotated by an arbitrary distance by changing this number of steps In this application example up to 255 steps can be set An operation pattern table is set for each of the Timer A and the Timer B Total number of operation patterns Forward rotation 200 steps at a constant motor speed Reverse rotation 9616 150 steps at a constant motor speed 0016 6446 FFie FA16 Operation pattern 1 Operation pattern 2 Operation pattern 3 Operation pattern 4 Note 0016 is defined as a forward rotation in this example FF16 is defined as a reverse rotation in this example Fig 2 4 11 Example of operation pattern table
7. Shift clock Clock control circuit P46 ScLk1O t Serial 1 01 synchronous clock selection bit BRG count source selection bit Division ratio 1 n 1 XIN O me ___________ Baud rate generator H 1 4 IS f Xcin in low speed mode Address 001C16 1 4 y P47 SrDY1O Falling edge detector Clock control circuit Shift clock Transmit shift register shift completion flag TSC Transmit interrupt source selection bit P45 TxXDO Transmit shift register 5 pe l Transmit interrupt request TI Transmit buffer register gt Transmit buffer empty flag TBE Serial 1 O1 status register Address 001916 JL Address 001816 Data bus Fig 35 Block diagram of clock synchronous serial 1 01 Transmit Receive shift clock 1 2 1 2048 of internal clock or external clock Serial output TxD X Do D1 D3 X Da X Ds De Serial input RxD X Do X DI Da X D4 X Ds X De Receive enable signal SRDY1 Write in signal to transmit receive buffer register address 001816 Y RBF 1 TSC 1 Overrun error OE detection Notes 1 The transmit interrupt TI can be selected to occur either when the transmit buffer has emptied TBE 1 or after the transmit shift operation has end
8. 1eeeeeeeeeeeneeneeeneni anaa anadan an sinn n nn nina sinn n nnn aaaea SE 1 59 Processor Status Register ea e EISE olaa abia 1 59 docte EREEETM 1 59 Decimal Calculations critt stetit ett ee eniin ate eene ee 1 59 qu Ce o v n 1 59 Multiplication and Division Instructions 1 59 A E E E E E A T 1 59 OMA OW AAA E E E T 1 59 AED CONVE EEA A T A E E se E eared e 1 59 D A Converter lonas a aaa a a a a aea 1 59 Instruction Execution TIMO Loi EEEE AAA EEEE AAT 1 59 NOTES ON USAGE 1 60 Handling of Source Pins sss nennen nennen nnns nnn nennen 1 60 3807 GROUP USER S MANUAL i Table of contents aX 1 60 AA ia eet eee cl leh eu t 1 60 EET 1 60 mr 1 61 A 1 61 FUNCTIONAL DESCRIPTION SUPPLEMEN Tlo cooccconinncccnnncnoiccccnnnnncnncncnnnnnnnnnnrnnnrrn cnc 1 62 l cngd ON 1 62 MAS AA 1 63 A Ae 1 64 Noui 2 2 2 1 1 Memory map of I O port nennen nnne nes 2 2 enm 2 3 2 1 3 Handling of unused pins sseeeeen nennen 2 5 MERERI EE 2 6 DSL adidas 2 6 2 2 2 Belated registers ir ee E tue pees rd EN eutt cnet e ou 2 7 cM E A aid 2 14 A PP E 2 29 2 3 1 Memory map of serial Ob 2 29 A A 2 30 ee
9. P80 DA3 Port P8 Input output CMOS compatible input level D A conversion output AN11 individual bits CMOS 3 state output A D conversion input P81 DA4 AN12 P82 RTPo Real time port output P87 RTP5 register Real time port control 23 Note1 For details of the functions of ports PO to P3 in modes other than single chip mode and how to use double function ports as function 1 0 ports refer to the applicable sections 2 Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction When an input level is at an intermediate potential a current will flow from Vcc to Vss through the input stage gate 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION 1 Ports PO P2 2 Ports P30 P31 Real time port output selection bit Pull up control Direction register Data bus gt Port latch Direction register Data bus 4 gt Port latch Data for real time port 3 Ports P32 P33 P35 P37 4 Port P34 Direction register X Y Direction register Clock output control Data bus Port latch Data bus
10. r Direction register Data bus gt Port latch Data bus A D conversion input o Analog input pin selection bit A D conversion input o Analog input pin selection bit Analog comparator input Fig 13 Port block diagram 2 1 18 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION 17 Port P65 18 Port P7o Direction register Direction register Data bus Port latch Data bus 4 Port latch D A conversion power source input 4 Serial 1 02 input A D conversion input Analog input pin selection bit 19 Port P71 20 Port P72 P72 Scik2 P channel output disable bit gt P71 Sour2 P channel output disable bit Serial Kee Synchronous I O Serial 1 02 transmit completion signal mE Serial 1 O2 port selection bit Serial 1 02 port selection bit 1 gt r Direction register 1 o Direction register 4 3 Y Data bus gt Port latch Data bus gt Port latch Serial 1 02 clock output 31 Serial 1 02 clock output 7 gt Serial 1 02 e
11. lOL peak L peak output current Note 1 P24 P27 in single chip mode in memory expansion mode and microprocessor mode loH avg H average output current Note 2 P00 PO7 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P62 P65 CMPouT P70 P77 P80 P87 L average output current Note 2 P00 PO7 P10 P17 P20 P23 P30 P37 P40 P47 P50 P57 P60 P62 P65 CMPouT P70 P77 P80 P87 lOL avg L average output current Note 2 P24 P27 in single chip mode in memory expansion mode and microprocessor mode f XIN Main clock input oscillation frequency Note 3 High speed mode 4 0V lt Vcc lt 5 5V High speed mode 2 7V lt Vcc lt 4 0V Middle speed mode 4 0V lt Vcc x 5 5V Middle speed mode Note 5 2 7V lt Vcc lt 4 0V Middle speed mode Note 5 2 7V VCC lt 4 0V f XCIN Sub clock input oscillation frequency Note 3 4 Note1 The peak output current is the peak current flowing in each port 2 The average output current IOL avg IOH avg in an average value measured over 100ms 3 When the oscillation frequency has a duty cyde of 50 4 When using the microcomputer in low speed mode set the sub clock input oscillation frequency on condition that f XCIN lt f XIN 3 5 When using the timer X Y timer A B real time output port timer 1 2 3 serial 1 01 serial 1 02 and A D converter set the main c
12. 3807 GROUP USER S MANUAL 1 23 HARDWARE FUNCTIONAL DESCRIPTION Precautions Set the double function port of CNTRo CNTR1 pin to output in this mode During timer operation stop The output from CNTRo CNTRa pin is initialized to the level set through CNTRo CNTRi active edge switch bit During timer operation enabled When the value of the CNTRo CNTRt active edge switch bit is writ ten over the output level of CNTRo CNTR1 pin is inverted Figure 20 shows the timing chart of the pulse output mode 3 Pulse period measurement mode Mode selection This mode can be selected by setting 010 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TYM Count source selection In high or middle speed mode f XiN 2 or f XiN 16 can be selected as the count source In low speed mode the count source is f XCIN Interrupt The interrupt generation at underflow is the same as already explained for the timer mode Bits 0 or 1 of IREQ2 is set to 1 synchronously to pulse period measurement completion Explanation of operation During timer operation stop Select the count source Next select the interval of the pulse periods to be measured When bit 5 of the TXM or TYM is set to 0 the timer counts during the interval of one falling edge of CNTRo CNTR pin input until the next falling edge of input If bits 5 are set to 1 the timer counts during the interval of one rising
13. HARDWARE FUNCTIONAL DESCRIPTION f XiN to at least 500kHz during A D conversion Use a CPU system clock dividing the main clock XIN as the internal clock 9 llNote When the A D external trigger is invalidated by the AD external trigger valid bit any interrupt request is not generated at a fall of the ADT input When the AD external trigger valid bit is set to 1 before hand A D conversion is not started by writing 0 into the AD conver sion completion bit and 0 is not written into the AD conversion completion bit Do not set 0 in the AD conversion completion bit concurrently with the timing at which the AD external trigger valid bit is rewritten Put an interval of at least 50 cycles to more of the internal clock between a start of A D conversion and the next start of A D conversion bo A D control register ADCON address 003416 Analog input pin selection bit 0000 P73 Srpy2 ADT ANo 0001 P74 AN1 0010 P75 AN2 0011 P76 AN3 0100 P77 AN4 0101 P60 ANs 0110 P61 AN6 0111 P62 AN7 1000 P63 CMPIN AN amp 1001 P64 CMPrer ANo 1010 P6s DAVREF AN10 1011 P80 DA3 AN11 1100 P81 DA4 AN12 AD conversion completion bit 0 Conversion in progress 1 Conversion completed ADVrer input switch bit 0 OFF 1 ON AD external trigger valid bit 0 A D external trigger invalid 1 A D external trigger valid Interrupt source selection bit 0 Interrupt request at A D conv
14. When this bit is read out the value is 0 of of of of of of of o X Fig 2 3 3 Structure of Serial 1 01 status register 2 30 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Serial 1 01 control register b7 b6 b5 b4 b3 b2 bi bO LLLLLLLL S Serial O1 control register SIO1CON Address 1A16 meses eps we O BRG count source A XIN Note al selection bit CSS f XiN 4 Note 24 87 Serial l O1 At BERE clock synchronous serial I O synchronous clock 0 BRG output divided by 4 selection bit SCS 1 External clock input At selecting UART 0 BRG output divided by 16 1 External clock input divided by 16 Se oda Kad S SRDY SRDY1 output pin 3 Transmit interrupt T Transmit buffer empty source selection bit 1 Transmit shift operating TIC _vombletion MES o e vem Transmit enabled Do O ES 1 Receiv enabled E REA DO g selection bit SIOM 1 Clock synchronous serial I O 7 Serial l O1 enable bit 0 Serial 1 01 disabled P44 P47 I O port 1 Serial 1 01 enabled P44 P47 Serial I O function pin Note 1 In low speed mode f Xcin is selected 2 In low speed mode f Xcin 4 is selected Fig 2 3 4 Structure of Serial 1 01 control register UART control register b7 b6 b5 b4 b3 b2 b1 b0 MAA 1111 UART control register UARTCON Address 1B16 8 nme Fon aaa Ofeina fives ALAS selection bit CHAS 1 7 bits 4 Parity enable bit O Parity checking disabled I
15. gt Port latch 1 jo 4 Clock output gt b Port P40 6 Port P41 Port Xc switch TL Port Xc switch bit r Direction register Direction registe Data bus Port latch Data bus 1 Port latch J Oscillator Port P41 Sub clock oscillating circuit input Port Xc switch bit 7 Ports P42 P43 P52 P53 8 Port P44 Direction register Serial 1 01 enable bit LL Receive enable bit Direction register Data bus f Port latch AAA Data bus 1 Port latch Interrupt i Timer X inpu i Timer Y inpu RTP trigger input P53 serial 1 01 input except P52 1 Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32 by P2 P32 input level selection bit Fig 12 Port block diagram 1 3807 GROUP USER S MANUAL 1 17 HARDWARE FUNCTIONAL DESCRIPTION 9 Port P45 10 Port P46 P45 TxD P channel output disab Serial 1 01 synchronous Serial l O1 enable bit 4 clock selection bit Transmit enable bit Serial 1 O1 enable bit 7 Direction registe Serial l O1mode selection bit 4 Serial l O1enable bit
16. 8 Jauianuoo va DHOQOOOOH 2 2626969 9699 HH H YY 8 Z J9USALOD 9 y a JeueAuoo av TELAT i Ld y 8 8 le sauanuos p sayenuoo vd wd 91 g 9w 91 v JOWLL no PBA 91 A Jeu 0d1NO JF A 91 x saw 8 z sow 8 saw 8 e saw JANO JOJereduoo L eO 1nOdWO NINO B Bojeuy nouo Burejeueb 49019 a A1noox NIOX jndino jndui 90j qns ADOJO QNS SOAdWO jndui jasoy N9d08 e6ey9ed NNVEIVIA 32018 1VNOILONn 68 4no x NIX indino indu x90 9 ule A90 9 uren Functional block diagram 2 Fig 1 3 3807 GROUP USER S MANUAL HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description 1 Pin Name Function Function except a port function Vcc Vss Power source Apply voltage of 2 7 5 5 V to Vcc and O V to Vss CMPVcc Analog comparator e Power source input pin for an analog comparator power source CNVss CNVss This pin controls the operation mode of the chip Normally connected to Vss If this pin is connected to Vcc the internal ROM is inhibited and external memory is acc
17. A Standard Mitsubishi Mark Mitsubishi IC catalog name Mitsubishi lot number 6 digit or 7 digit r Customer s parts number Note The fonts and size of characters are standard Mitsubishi type i7 Mitsubishi IC catalog name I Note3 Customer s parts number can be up to 14 char Em acters Mitsubishi lot number 6 digit or 7 digit Only 0 9 A Z t 7 amp period and comma are usable 4 If the Mitsubishi logo amp is not required check the box below Note1 The mark field should be written right aligned Mitsubishi logo is not required 2 The fonts and size of characters are standard M Mitsubishi type C Special Mark Required Note1 If the special mark is to be printed indicate the desired layout of the mark in the left figure The layout will be duplicated as close as possible Mitsubishi lot number 6 digit or 7 digit and mask ROM number 3 digit are always marked If the customer s trade mark logo must be used in the special mark check the box below Please submit a clean original of the logo For the new special character fonts a clean font original ideally logo drawing must be sub mitted N Special logo required The standard Mitsubishi font is used for all char acters except for a logo 3 58 3807 GROUP USER S MANUAL APPENDIX 3 8 Package outline 3 8 Package outline 80P6N A Plastic 80pin 14x 20mm body QFP EIAJ Pac
18. L input current P00 P07 P10 P17 P20 Pull up transistors on Vi VSS RAM hold voltage When clock stopped Note1 P45 is measured when the P45 TXD P channel output disable bit of the UART control register bit 4 of address 001B16 is 0 P71 and P12 are measured when the P71 SouT2 and P72 ScLk2 P channel output disable bit of the serial 1 02 control register 1 bit 7 of address 001Di6 3807 GROUP USER S MANUAL 2 P73 is measured when the AD external trigger valid bit of the A D control register bit 6 of address 003416 is 1 3 5 APPENDIX 3 1 Electrical characteristics Table 3 1 6 Electrical characteristics 2 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Typ Parameter Test conditions Power source current High speed mode f XIN 8MHz f XCIN 32 768kHz Output transistors off High speed mode f XIN 8MHz in WIT state f XCIN 32 768kHz Output transistors off Low speed mode f XIN 2 stopped f XCIN 32 768kHz Low power dissipation mode CM8 0 Output transistors off Low speed mode f XIN stopped f XCIN 32 768kHz in WIT state Low power dissipation mode CM8 0 Output transistors off Low speed mode VCC 3V f XIN stopped f XCIN 32 768kHz Low power dissipation mode CM8 0 Output transistors off Low speed mode VCC 3
19. P81 DA4 AN12 gt 28 e PA1 XCIN 27 RESET 33 32 31 30 29 M38073M4 XXXFP ese feles 85822 LLI T zZ gt ou gt Z X XXL e5 U LI XI ug Q gt Q 3 XI gt a no wo oOo B n P63 CMPin ANs 3 26 79 CMPouT CMPVcc 25 gt P42 INTO gt 1NI vd 4 QXu rvd lt gt X1 Svd lt gt 1110S 97d lt gt 1A0ES LYd 4 h 100 0Gd lt gt z NI dWOS Gd gt 1NI 2Gd gt v NI 5Sd gt 04 LNO Sd gt Ly 1NO SGd lt gt VdAGd gt evd 4Sd lt gt 2NIS 0 d 4 21N0S d 6 gt 2onog z d 8 gt 0NV 10V 24088 d Z gt Ny vZd 9 lt gt zNV s d LS lt gt tNV 94d y gt vNV A4d lt 4 sy y 09d 3 lt 4 9Nv I9d LH lt gt ny 9d 3807 GROUP USER S MANUAL 3 72 MITSUBISHI SEMICONDUCTORS USER S MANUAL 3807 Group Nov First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1996 MITSUBISHI ELECTRIC CORPORATION 3807 Group User s Manual ENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REVISION DESCRIPTION LIST 3807 Group User s Manual No date First
20. eene 2 710 5 5 V at 8 MHz oscillation frequency and middle speed selected Inlowsspe ed mode mnm 2 710 5 5 V at 32 kHz oscillation frequency and low speed selected Power dissipation In high speed mode eene 34mW at 8 MHz oscillation frequency at 5 V power source voltage In low speed mode eere 60 uW at 32 kHz oscillation frequency at 3 V power source voltage e Memory expansion essen possible e Operating temperature range seses 20 to 85 C APPLICATION LBP engine control PPC FAX office equipment household appli ances consumer electronics etc 0 1 2 3 4 62 a P32 60 P34 59 a P35 58 a P36 57 gt P3 56 a P0o 55 a P01 64 gt P30 63 a P31 61 48 P 46 gt P P87 RTPs P86 RTP4 P85 RTP3 P84 RTP2 P83 RTP1 P82 RTPo P81 DA4 AN12 lt q P80 DA3 AN11 O P20 DBo P21 DB1 P22 DB2 P23 DB3 P24 DB4 P25 DBs P26 DBs P27 DB7 Veo M38073M4 XXXFP Vss ADVREF 74 AVss gt P65 DAVREF AN10 a P64 CMPREF ANo
21. Fig 3 2 3 Standard characteristic example of CMOS output port at P channel drive 1 Port P87 loH VoH characteristic P channel drive Pins with same characteristic PO P1 P2 P3 P4 P5 P60 P62 P65 P7 P8 CMPoUT loH mA 100 90 80 70 60 50 40 Vcc 5 5V Ta 25 C 20 Vec 5 0V Ta 25 C Fig 3 2 4 Standard characteristic example of CMOS output port at P channel drive 2 3 18 3807 GROUP USER S MANUAL APPENDIX 3 2 Standard characteristics Port P87 loL VoL characteristic N channel drive Pins with same characteristic PO P1 P20 P23 P3 P4 P5 P60 P62 P65 P7 P8 CMPour P24 P27 except in single chip mode loL mA 100 90 80 70 ni Vec 5 5V Ta 90 C 50 Vcc 5 0V Ta 90 C 40 30 20 Vcc 3 0V Ta 90 C 10 Fig 3 2 5 Standard characteristic example of CMOS output port at N channel drive 1 Port P87 loL VoL characteristic N channel drive Pins with same characteristic PO P1 P20 P23 P3 P4 P5 P60 P62 P65 P7 P8 CMPour P24 P27 except in single chip mode loL mA 100 90 80 Vcc 55V Ta 25 C 60 Vcc 5 0V Ta 25 C 50 40 30 Vcc 23 0V Ta 25 C 20 10 Fig 3 2 6 Standard characteristic example of CMOS output port at N channel
22. Figure 2 4 12 shows an example of output data table Output data is selected in the 4 types of tables shown in Figure 2 4 12 according to the information on forward rotation and reverse rotation referenced in the operation pattern table shown in Figure 2 4 11 and then set in Real time port registers 0 to 7 For example in case the Timer B continues to control the motor in the forward direction when the data of operation pattern 2 is set after the Timer A has output operation pattern 1 the data of table 3 is set in Real time port registers 0 to 7 Table 1 Table 2 Table 3 Table 4 RTP7 RTPa Forward rotation RTP7 RTP4 Reverse rotation RTP7 RTP4 Forward rotation RTP7 RTP4 Reverse rotation RTP3 RTPo Forward rotation RTP3 RTPo Forward rotation RTP3 RTPo Reverse rotation RTP3 RTPo Reverse rotation b7 bO b7 bO b7 bO b7 bO time port register7 o oo 1 Jolo o 1 1lo10 1Jololo s olo olo 1 1 ofo 1 h loloh b7 bO b7 bO b7 bO b7 bO time port register 6 OJO 1 1 OJO 1 1 1 olo olo 111 olo 0 0 b7 bO bO bO bO ime port register 5 oloh lololol 0 1 0 0 0 b7 bO bO bO ime port register 4 0O 1 1 0 O 0 0 0 b7 bO bO bO ime port register 3 o t o o 0 0 0 b7 bO bO bO ime port register 2 111 oft 0 0 0 b7 bO bO bO ime port register 1 ilo ol 0 1 1 b7 bO bO bO ime port register 0 1 olol hi lolo 1 1 1
23. Generation of CNTRO CNTRt interrupt request Rising edge Programmable one shot generation mode 0 3807 GROUP USER S MANUAL 3 45 APPENDIX 3 5 List of registers Timer 123 mode register b7 b6 b5 b4 b3 b2 bi bO SL 123 mode register T123M Address 29 6 Name Funcion wrs R w EL output active edge switch E Start at outputting H signal bit Start at outputting L signal Tour output control bit 0 Disabled Tour output lo 1 Enabled Tour output 2 Timer 2 write control bit O To a latch and a timer at the same time ofo 1 To only latch Timer 2 count source selection s Sen signal from Timer 1 bit f Xin 16 Note 1 Timer 3 count source selection E Output signal from Timer 1 bit f Xin 16 Note 1 Timer 1 count source selection 7 P f Xin 16 bit 0 1 s 1 0 f Xcin 1 1 Not available Nothing is allocated for this bit It is a write disabled bit When this bit is read out the value is 0 Note 1 In low speed mode f Xcin 16 is selected 2 In low speed mode f Xcin 2 is selected Fig 3 5 22 Structure of Timer 123 mode register Real time port register b7 b6 b5 b4 b3 b2 b1 bO Real time port register RTP Address 2A 6 Sets the data to be output to the Real time port Makes it possible to write data into any of Real time port registers 0 to 7 by specifying the Real time port data pointer R W pointer and writing data into this register e
24. P63 CMPIN ANs CMPOUT lt CMPVcc O XOUT XIN P40 XcouT P41 XCIN RESET CNVss P42 INTo e 13 17 18 19 AN6 2 AN5 lt lt 3 AN4 gt 4 ANS gt gt 5 AN2 lt gt 6 P74 AN1 gt 7 P73 SRDY2 ADT ANO 8 P62 P61 P60 P77 P76 P75 P72 SCLK2 9 P71 SoUT2 10 P70 SiN2 lt gt 11 P57 DA2 lt 12 P56 DA1 gt P55 CNTR1 lt 14 P54 CNTRo a 15 P53 INT4 gt 16 P52 INT3 lt gt P51 ScMP2 INT2 lt gt P5o TOUT P47 SRDY1 a gt 20 P4e ScLk1 lt t 21 P45 TxD 22 P44 RxD 23 P43 INT1 t 24 Package type 80P6N A 80 pin plastic molded QFP Fig 1 Pin configuration of M38073M4 XXXFP 1 2 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL BLOCK FUNCTIONAL BLOCK 0 d uod O I L d uod O I atas Z d uod oj e d uod O y d uod O I Cc N WO E r TT il DOD OGOOOHOOSO I 8 0d 8 Ld A 8 Zd 1NODX NIOX OLNI Es d god D SSAV 9d Hed O I 334AQY 1 d uod O I 8 d uod O I r A n P m LINI 200 00 Le l EEN met 99
25. decimal arithmetic is executed when it is 1 Decimal correction is automatic in decimal mode Only the ADC and SBC instructions can be used for decimal arithmetic 5 Break flag B The B flag is used to indicate that the current interrupt was generated by the BRK instruction The BRK flag in the processor status register is always 0 When the BRK instruction is used to generate an interrupt the processor status register is pushed onto the stack with the break flag set to 1 The saved processor status is the only place where the break flag is ever set 6 Index X mode flag T When the T flag is 0 arithmetic operations are performed between accumulator and memory e g the results of an operation between two memory locations is stored in the accumulator When the T flag is 1 direct arithmetic operations and direct data transfers are enabled between memory locations i e between memory and memory memory and I O and I O and I O In this case the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1 The address of memory location 1 is specified by index register X and the address of memory location 2 is specified by normal addressing modes 7 Overflow flag V The V flag is used during the addition or subtraction of one byte of signed data It is set if the result exceeds 127 to 128 When the BIT instruction is executed bit 6 of the mem
26. routine Note Note Execute the same processing for Timer B During a constant Y A constant motor speed processing motor speed Y An acceleration processing During accelerating All number of constant motor speed steps are completed to output All number of acceleration steps i are completed to output Set the deceleration flag A deceleration processing is A deceleration processing executed next time A number of steps number of deceleration Set the constant motor speed flag Counter lt 0016 steps 1 is completed A constant motor speed processing is to output executed next time Counter lt 0016 Set the completion stop flag Counter 0016 Set a value of a timer table for deceleration in order low order to high order of Timer A Stop completely Fig 2 4 22 Control procedure 4 3807 GROUP USER S MANUAL 2 79 APPLICATION 2 5 A D converter 2 5 A D converter 2 5 1 Memory map of A D conversion 003416 A D control register ADCON 003516 A D conversion register AD _ 003D16 Interrupt request register 2 IREQ2 _ 003Fi6 Interrupt control register 2 ICON2 Fig 2 5 1 Memory map of A D conversion related registers 2 80 3807 GROUP USER S MANUAL APPLICATION 2 5 A D converter 2 5 2 Related registers A D control register b7 b6 b5 b4 b3 b2 b1 bO A D control register ADCON Address 341
27. sssssssssee 2 36 Fig 2 3 15 Serial I O connection examples Irrien 2 37 Fig 2 3 16 Serial I O connection examples 2 sse 2 38 Fig 2 3 17 Setting of Serial I O transfer data format 2 39 Fig 2 3 18 Connection diagram Communication using a clock synchronous serial 1 0 2 40 Fig 2 3 19 Timing chart Communication using a clock synchronous serial 1 O 2 40 Fig 2 3 20 Setting of related registers at a transmitting side Communication using a clock synchronous Serial I O 2 41 Fig 2 3 21 Setting of related registers at a receiving side Communication using a clock synchronous Serial I O 2 42 Fig 2 3 22 Control procedure at a transmitting side Communication using a clock synchronous serial I O 2 43 Fig 2 3 23 Control procedure at a receiving side Communication using a clock synchronous serial I O 2 44 Fig 2 3 24 Connection diagram Output of serial data sssssseeeese 2 45 Fig 2 3 25 Timing chart Output of serial data 2 45 Fig 2 3 26 Setting of serial l O1 related registers Output of serial data 2 46 Fig 2 3 27 Setting of serial l O1 transmission data Output of serial data 2 47 Fig 2 3 28 Control procedure of serial l O1 Output of serial data sssssssse 2 48 Fig
28. Details Addressing mode A BIT A ZP BIT ZP n JOP n JOP OP n BVC Note 4 Branches when the contents of overflow flag is g BVS Note 4 Branches when the contents of overflow flag is I CLB Clears the contents of the bit specified in the accumulator or memory to 0 Clears the contents of the carry flag to 0 Clears the contents of decimal mode flag to g Clears the contents of interrupt disable flag to g Clears the contents of index X mode flag to g Clears the contents overflow flag to 0 CMP Note 3 Compares the contents of accumulator and memory Compares the contents of the memory speci fied by the addressing mode with the contents of the address indicated by index register X Forms a one s complement of the contents of memory and stores it into memory Compares the contents of index register X and memory Compares the contents of index register Y and memory AA 1or M lt M 1 Decrements the contents of the accumulator or memory by 1 X X 1 Decrements the contents of index register X by 1 Ye Y 1 Decrements the contents of index register Y by 1 A M zz X 1 M zz X A M S 1 s complememt of Remainder S 8 1 Divides the 16 bit data that is the contents of M zz x 1 for high byte and the contents of M zz x
29. H when the desired number of bytes have been transmitted Figure 2 3 31 shows a control procedure of serial 1 02 RESET This bit is not used in this application Set it to O or 1 It s value can be disregarded Initialization SIO2CON1 Address 1D16 lt 010010112 Set the Serial 1 02 control register 1 SlO2CON2 Address 1E16 lt XOXXX1112 e Set the Serial 1 O2 control register 2 Address 3F 16 bit2 lt 0 Serial l O2 interrupt Disabled Address 0A 6 bit3 1 Set the CS signal output port Address 0B16 XXXX1XXX2 H level output P5 Address OAt6 bit3 0 Set the CS signal output level to L e Set the Serial 1 02 interrupt request bit to 0 IREQ2 Address 3D16 bit2 lt 0 SIO2 Address 1F16 A transmission Write a transmission data data start to transmit 1 byte data Check the completion of transmitting 1 byte data Use any of RAM area as a counter for counting the number of transmitted bytes Check that transmission of the target number of bytes has been completed Return the CS signal output level to H when transmission of the target number of bytes is completed Fig 2 3 31 Control procedure of serial 1 02 Output of serial data 3807 GROUP USER S MANUAL 2 51 APPLICATION 2 3 Serial I O 3 Cyclic transmission or reception of block data data of a specified number of bytes
30. between microcomputers without using an automatic transfer Outline When a clock synchronous serial I O is used for communication synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock Thus it is necessary to be corrected constantly This heading adjustment is carried out by using the interval between blocks in this example RxD Master unit Slave unit Note Use Sour and Sin2 instead of TxD and RxD in the serial 1 02 Fig 2 3 32 Connection diagram Cyclic transmission or reception of block data between microcomputers Specifications The serial l O1 is used clock synchronous serial I O is selected Synchronous clock frequency 125 kHz f XIN 8 MHz is divided by 64 Byte cycle 488 us Number of bytes for transmission or reception 8 byte block Block transfer cycle 16 ms Block transfer period 3 5 ms Interval between blocks 12 5 ms Heading adjustive time 8 ms Limitations of the specifications 1 Reading of the reception data and setting of the next transmission data must be completed within the time obtained from byte cycle time for transferring 1 byte data in this example the time taken from generating of the Serial l O1 receive interrupt request to generating of the next synchronizing clock is 428 p s 2 Heading adjustive time interval between blocks must be satisf
31. Fig 2 2 9 Structure of Interrupt edge selection register ssssssssseese 2 11 Fig 2 2 10 Structure of Interrupt request register 1 2 12 Fig 2 2 11 Structure of Interrupt request register 2 2 12 Fig 2 2 12 Structure of Interrupt control register 1 2 13 Fig 2 2 13 Structure of Interrupt control register 2 2 13 Fig 2 2 14 Connection of timers and setting of division ratios Clock function 2 15 Fig 2 2 15 Setting of related registers Clock function sseeese 2 16 Fig 2 2 16 Control procedure Clock function sssssseeeeeneenneens 2 17 Fig 2 2 17 Example of a peripheral circuit sesssssssseeeeeeeeee entente 2 18 Fig 2 2 18 Connection of the timer and setting of the division ratio Piezoelectric buzzer output 2 18 ii 3807 GROUP USER S MANUAL List of figures Fig 2 2 19 Setting of related registers Piezoelectric buzzer output ssse 2 19 Fig 2 2 20 Control procedure Piezoelectric buzzer output 2 20 Fig 2 2 21 A method for judging if input pulse exists ssssse m 2 21 Fig 2 2 22 Setting of related registers 1 Measurement of frequency 2 22 Fig 2 2 23 Setting of related registers 2 Measurement of frequency 2 23 Fig 2 2 24 Control procedure Measurement of frequency ssseeeeee 2 24 Fig 2 2 25
32. Pulse width measurement mode 0 Programmable waveform generating mode 0 Programmable one shot generating mode 1 PWM mode 1 Not used 22200008 Timer X write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Output level latch O L output 1 H output CNTR0 active edge switch bit 0 Event counter mode counts rising edges Pulse output mode output starts with H level Pulse period measurement mode measures between two falling edges Pulse width measurement mode measures H periodes Programmable one shot generating mode after start at L level output a H pulse interrupt request is triggered on falling edge 1 Eevent counter mode counts falling edges Pulse output mode output starts with L level Pulse period measurement mode measures between two rising edges Pulse width measurement mode measures L periodes Programmable one shot generating mode after start at H level output a L pulse interrupt request is triggered on rising edge Timer X count source selection bits b7 b6 0 0 f Xin 2 0 1 f Xin 16 1 0 f Xcin 1 1 Input signal from CNTRO pin Timer XY control register TXYCON address 001416 Timer X stop control bit 0 start counting 1 stop counting Timer Y stop control bit 0 start counting 1 stop counting
33. Serial 1 02 register S102 003A16 Interrupt edge selection register INTEDGE Fig 2 3 1 Memory map of serial I O related registers 3807 GROUP USER S MANUAL 2 29 APPLICATION 2 3 Serial I O 2 3 2 Related registers Transmit Receive buffer register b7 b6 b5 b4 b3 b2 b1 bO LTT TTT TTI Transmit Receive buffer dei TB RB Address 1816 A transmission data is written to or a receive data is read out from this buffer register At writing a data is written to the Transmit buffer register At reading a content of the Receive buffer register is read out Note A content of the Transmit buffer register cannot be read out A data cannot be written to the Receive buffer register Fig 2 3 2 Structure of Transmit Receive buffer register Serial 1 01 status register b7 b6 b5 b4 b3 b2 b1 bO WLL D 1 01 status o SIO1STS Address zm Name Function atrese R w EIN buffer empty flag H Buffer full TBE Buffer empty Receive buffer full flag RBF 3 Buffer empty 2 Transmit shift register shift 0 Transmit shift in progress completion flag TSC 1 Transmit shift completed 3 Overrun error flag OE 0 No error x 1 Overrun error X X x x x Framing error flag FE A No error Framing error Summing error flag SE OE U PE U FE 0 l OE U PE U FE 1 7 Nothing is allocated for this bit It is a write disabled bit x Parity error flag PE noes ea X
34. Use LDM or STA instruction for specifying the Real time port data pointer B when this bit is switched When this bit is read 1 is always read out 2 When these bits are read an output pointer is read out Fig 3 5 26 Structure of Real time port control register 2 3807 GROUP USER S MANUAL 3 49 APPENDIX 3 5 List of registers Real time port control register 3 b7 b6 b5 b4 b3 b2 b1 bO Real time port control register 3 RTPCON3 Address 2E16 B Name Funcio ateser R W Real time port output selection I O port bit P82 Real time output port Real time port output selection o fofo bit P83 2 Real time port output selection bit P84 3 Real time port output selection 0 fofo bit P85 4 Real time port output selection o fofo bit P86 Real time port output selection bit P87 Real time port output selection bit P30 Real time port output selection bit P31 Fig 3 5 27 Structure of Real time port control register 3 Timer A Low order Timer A High order Timer B Low order Timer B High order b7 b6 b5 b4 b3 b2 bi bO Timer A Low order TAL Timer A High order Ma Address 2Fie 3016 Timer B Low order TBL Timer B iliud TBH Address 3116 3216 Sets the real time output cycle 1 Writing is performed in the order of low order and high order There are 2 reload latches When the high order side is written the next latch is automatically specified The lat
35. value shows big changes When timer 1 output is selected as timer 2 or timer 3 count source short pulses are generated to signals output from timer 1 through writing timer 1 Due to that the count values for timer 2 and 3 may change very often Therefore when the count sources for timer 1 to 3 are set set the f XiN 16 f XciN 16 in low speed mode HARDWARE FUNCTIONAL DESCRIPTION Timer 123 mode register T123M address 002916 O start with H output 1 start with L output Tour output control bit 0 Tour output disabled 1 Tour output enabled Timer 2 write control bit O Timer 1 output Tour output active edge switch bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Timer 2 count source selection bit 1 f Xin 16 or f XciN 16 in low speed mode Timer 3 count source selection bit O Timer 1 output 1 f Xin 16 or f Xcin 16 in low speed mode Fig 26 Structure of Timer 123 mode register Timer 1 count source selection bits 00 f XiN 16 or f XciN 16 in low speed mode 01 f Xin 2 or f Xcin 2 in low speed mode 10 f Xcin 11 Not available Not used returns 0 when read Data bus Timer 1 Timer 1 count source selection bits 00 values in order starting from timer 1 Timer 1 latch 8 f Xw2 9t o f XciN 2 in low speed mode A 0 f
36. 1 01 status register 3 38 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Serial 1 01 control register b7 b6 b5 b4 b3 b2 b1 bO Serial 1 O1 control register SIO1CON Address 1416 0 f XIN Note 1 1 f XIN A Note 2 Serial 1 01 At selecting clock synchronous serial I O synchronous clock 0 BRG output divided by 4 selection bit SCS 1 External clock input At selecting UART 0 BRG output divided by 16 1 External clock input divided by 16 2 Sroyi output enable bit 0 I O port P47 SRDY 1 SRDY1 output pin 3 Transmit interrupt 0 Transmit buffer empty Source selection bit 1 Transmit shift operating TIC completion 4 Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled 5 Receive enable bit RE 0 Receive disabled 1 Receive enabled E Serial 1 01 mode 0 UART selection bit SIOM Clock synchronous serial I O 7 Serial 1 01 enable bit 0 Ou io 4 P47 I O por SIOE 1 Serial l O1 enabled P44 P47 Serial I O function pin Note 1 In low speed mode f Xcin is selected 2 In low speed mode f Xcin 4 is selected Fig 3 5 11 Structure of Serial 1 01 control register UART control register b7 b6 b5 b4 b3 b2 b1 bO UART control register UARTCON Address 1B16 selection bit CHAS 1 7 bits Parity enable bit O Parity checking disabled PARS 1 Odd parity Stop bit length selection bit STPS 1 2 stop bits In output mode 0 CMOS out
37. 2 INT2 interrupt edge 0 Falling edge active selection bit 1 Rising edge active 3 INT3 interrupt edge 0 Falling edge active selection bit 1 Rising edge active 4 INTa interrupt edge 0 Falling edge active selection bit 1 Rising edge active 5 Timer 1 INT2 interrupt 0 INT2 interrupt source bit 1 Timer 1 interrupt 6 Timer 2 INT3 interrupt 0 INTs interrupt Le ee source bit 1 Timer 2 interrupt 7 Timer 3 INT4 interrupt O INT4 interrupt ESSE source bit 1 Timer 3 interrupt Fig 3 5 33 Structure of Interrupt edge selection register CPU mode register b7 b6 b5 b4 b3 b2 bi bO CPU mode register CPUM Address 3B16 W 0 0 Single chip mode o fofo O 1 Memory expansion mode g 1 e Microprocessor KARG 1 1 Not available Note Stack page selection bit x gt page 1 page g Xcour drivability selection bit J Low High Port Xc switch bit I O port function XciN Xcour operating function Main clock Xin Xout stop bit E Operating Stopped 1 ojo Main clock division ratio f Xin 2 high speed mode l EEIBEUUII DIIS f Xin 8 middle speed mode f Xcin 2 low speed mode Not available Note An initial value of bit 1 is determined by a level of the CNVss pin Fig 3 5 34 Structure of CPU mode register 3807 GROUP USER S MANUAL 3 53 APPENDIX 3 5 List of registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi bO Interrupt request reigster 1 I
38. 2 3 29 Setting of serial 1 02 related registers Output of serial data 2 49 Fig 2 3 30 Setting of serial 1 02 transmission data Output of serial data 2 50 Fig 2 3 31 Control procedure of serial 1 02 Output of serial data ssessssse 2 51 Fig 2 3 32 Connection diagram Cyclic transmission or reception of block data between microcomputers 2 52 Fig 2 3 33 Timing chart Cyclic transmission or reception of block data between microcomputers 2 53 3807 GROUP USER S MANUAL iii List of figures Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 2 3 34 Setting of related registers Cyclic transmission or reception of block data between microcomputers 2 53 2 3 35 Control in the master unit ccccceccceeeceeeeceeeeeeeeeeeceeeeeeseaeeseeeeessaeeeeeeeeesnaeeeseneeetaas 2 54 2 39 36 Control inthe Slave ritui en pe la sad 2 55 2 3 37 Connection diagram Communication using UART esses 2 56 2 3 38 Timing chart Communication using UART ssseeeen 2 56 2 3 39 Setting of related registers at a transmitting side Communication using UART 2 58 2 3 40 Setting of related regist
39. 2 5 Table 2 2 1 Function of CNTRo CNTR1 edge switch bit ssssse 2 10 Table 2 3 1 Setting examples of Baud rate generator values and transfer bit rate values 2 57 CHAPTER 3 APPENDIX Table 3 1 1 Absolute maximum ratings ssessseeeeeeen m enne enne nnns 3 2 Table 3 1 2 Recommended operating conditions 1 sss 3 3 Table 3 1 3 Recommended operating conditions 2 sse 3 3 Table 3 1 4 Recommended operating conditions 3 oo eee eeetteeeeeeenteeeeeeeetaeeeeeeenaaeeeeeeeaees 3 4 Table 3 1 5 Electrical characteristics 1 3 5 Table 3 1 6 Electrical characteristics 2 sssssssssssssseseeeeene nennen 3 6 Table 3 1 7 A D converter characteristics sssssssssseeeenm nme 3 7 Table 3 1 8 D A converter characteristics esssssssssssssssseeeeenne entrent nnn 3 7 Table 3 1 9 Analog comparator characteristics enne eene 3 7 Table 3 1 10 Timing requirements U v cocccconncccnnnnonccccnnnnnneccnonnnnencnnnnnnnecn nn cnn cnn nnne nnne nnn 3 8 Table 3 1 11 Timing requirements 2 rerit erret hie a ht bna 3 8 Table 3 1 12 Switching characteristics 1 3 9 Table 3 1 13 Switching characteristics 2 ssssssssssssssssseseeeene eintreten 3 9 Table 3 1 14 Timing requirements in memory expansion mode and microprocessor mode 3 10 Table 3 1 15 Switching characteristics in memory expans
40. 22 Lap N Do D D2X Ds DX Ds DeX D7 No D1X D2X DsXDaX DsX DeX D7Y 2 2 4 2 ms Fig 2 3 19 Timing chart Communication using a clock synchronous serial I O 2 40 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Transmitting side Serial l O1 status register Address 1916 b7 bo L gt Transmit buffer empty flag Check to be transferred data from the Transmit buffer register to Transmit shift register Writable the next transmission data to the Transmit buffer register at being set to 1 Transmit shift register shift completion flag Check a completion of transmitting 1 byte data with this flag 1 Transmit shift completed Pa 1 01 control pus Address 1A16 SIO1 con s 1 o 1 Tofo GET 17 Le BRG counter source selection bit f XIN Serial l O1 synchronous clock selection bit BRG 4 Transmit enable bit Transmit enabled Receive enable bit Receive disabled Serial l O1 mode selection bit Clock synchronous serial I O Serial l O1 enable bit Serial 1 O1 enabled Baud rate generator Address 1C 6 b7 bo BRG Set division radio 1 Interrupt edge selection register Address 3A16 b7 bO wreocE o L INTo active edge selection bit Select INTo falling edge Fig 2 3 20 Setting of related registers at a transmitting side Communication using a clock synchronous serial I O 3807 GROUP USER S MANUAL 2 41 APPLICATION 2
41. 240 t CMOS CMOS output rising time Note 3 t CMOS CMOS output falling time Note 3 Note 1 When the P45 TxD P channel output disable bit of the UART control register bit 4 of address 001B16 is 0 2 When the P71 SouT2 P72 ScLk2 P channel output disable bit of the serial 1 02 control register bit 7 of address 001D16 is 0 3 XOUT pin is excluded 3807 GROUP USER S MANUAL APPENDIX 3 1 Electrical characteristics 3 1 9 Timing requirements in memory expansion mode and microprocessor mode Table 3 1 14 Timing requirements in memory expansion and microprocessor mode Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C in high speed mode unless otherwise noted Limits Typ Symbol Parameter tsu ONW 9 ONW input set up time th ONW ONW input hold time tsu DB Data bus set up time th DB Data bus hold time tsu ONW RD tsu ONW WR ONW input set up time th RD ONW th WR ONW ONW input hold time tsu DB RD Data bus set up time th RD DB Data bus hold time 3 1 10 Switching characteristics in memory expansion mode and microprocessor mode Table 3 1 15 Switching characteristics in memory expansion and microprocessor mode Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C in high speed mode unless otherwise noted Limits Typ Parameter Test conditions 4 clock cycle time 4 cloc
42. 4 Real time port register 5 Real time port register 6 Real time port register 7 Timer A write Specify the Timer AO latch 1 Specify the Timer A1 latch Note 1 Use LDM or STA instruction for specifying the Real time port data pointer A when this bit is switched When this bit is read 1 is always read out 2 When these bits are read an output pointer is read out o o i ur PTT Fig 3 5 25 Structure of Real time port control register 1 3 48 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Real time port control register 2 b7 b6 b5 b4 b3 b2 b1 b0 LIT IEELEE Real time port control register 2 RTPCON2 Address 2D 6 Timer B operating mode selection bits 8 repeated load mode 6 repeated load mode 5 repeated load mode One shot pulse generation mode Real time port data pointer B 0 RW pointer switch bit Note 1 Output pointer Timer B interrupt mode Interrupts occur when a Real selection bit time port output pointer value becomes 0002 1 Interrupt request occurs in spite of a Real time port output pointer value Real time port register 0 loja Real time port register 1 Real time port register 2 Real time port register 3 E Real time port register 4 Real time port register 5 Real time port register 6 Real time port register 7 Timer B write TE Specify the Timer BO latch 1 Specify the Timer B1 latch Note 1
43. Connection of the timer and setting of the division ratio Measurement of pulse width 2 25 Fig 2 2 26 Setting of related registers Measurement of pulse width 2 26 Fig 2 2 27 Control procedure 1 Measurement of pulse width ssesssssses 2 27 Fig 2 2 28 Control procedure 2 Measurement of pulse width sesssssss 2 28 Fig 2 3 1 Memory map of serial I O related registers sssssssse 2 29 Fig 2 3 2 Structure of Transmit Receive buffer register ssssssee 2 30 Fig 2 3 3 Structure of Serial l O1 status register sssssssssee 2 30 Fig 2 3 4 Structure of Serial l O1 control register ssssseee 2 31 Fig 2 3 5 Structure of UART control register sse mene 2 31 Fig 2 3 6 Structure of Baud rate generator 2 32 Fig 2 3 7 Structure of Serial 1 02 control register Tarsis roei 2 32 Fig 2 3 8 Structure of Serial 1 02 control register 2 2 33 Fig 2 3 9 Structure of Serial 1 02 register enne 2 33 Fig 2 3 10 Structure of Interrupt edge selection register ssssssssessss 2 34 Fig 2 3 11 Structure of Interrupt request register 1 sss 2 35 Fig 2 3 12 Structure of Interrupt request register 2 2 35 Fig 2 3 13 Structure of Interrupt control register 1 sssssssssee 2 36 Fig 2 3 14 Structure of Interrupt control register 2
44. DESCRIPTION On going Routine Interrupt request pee Note 1 cos S PCH Execute JSR B SU RUM ad Store Return Address M S PCH k Note 2 M PCH MG PCD on Stack Note 2 S 65 SPC 1 z Store Contents of Processor S S 1 lt Store Return Address on Stack Note 2 lt E 1 l E D o o o6 Status Register on Stack S 1 S Interrupt Service Routine Flag 0 to 1 Execute RTS Execute RTI Fetch the Jump Vector Restore Return S S 1 Add dai PCEM S Restore Contents of Processor Status Register PS lt M S S PCH EM S eos MS Restore Return Address S S 1 p 7 BR PCH M S Note 1 The condition to enable the interrupt Interrupt enable bit is 1 Interrupt disable flag is 0 2 When an interrupt occurs the address of the next instruction to be executed is stored in the stack area When a subroutine is called the address one before the next instruction to be executed is stored in the stack area Fig 6 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack PLA PLP Accumulator Processor status register 3807 GROUP USER S MANUAL 1 9 HARDWARE FUNCTIONAL DESCRIPTION Processor stat
45. Direction register t Data bus gt Port latch Data bus Port latch Serial 1 01 output Serial 1 01 clock output Serial 1 O1 external clock input 11 Port P47 12 Port P50 Serial l O1 mode selection bit gt Direction register Serial 1 01 enable bit Srbyi output enable bit r gt Direction register Data bus Port latch Data bus 7 Port latch Tour output control bit 4 Timer 2 output E Serial l O1 ready output _ gt 13 Ports P54 P55 14 Ports P56 P57 P80 P81 Direction register m Direction register Data bus t_ Port latch Data bus gt Port latch k Timer X Timer Y 100 D A conversion output amp 9 So operating mode bits DA2 output enable bit Timer ou DAs output enable bit CNTRo CNTR interrupt input f A D conversion input 4 oo i Analog input pin selection bit except P5e P57 15 Ports P60 P62 P74 P77 16 Ports P63 P64
46. Edition 971101 1 1
47. M Mask ROM version E EPROM or One Time PROM version RAM size 192 bytes 256 bytes 384 bytes 512 bytes 640 bytes 768 bytes 896 bytes 1024 bytes 1536 bytes 2048 bytes OONDOARWNM oO Fig 3 Part numbering 1 6 3807 GROUP USER S MANUAL HARDWARE GROUP EXPANSION GROUP EXPANSION Mitsubishi plans to expand the 3807 group as follows Memory Type Support for Mask ROM One Time PROM and EPROM versions Memory Size ROMPROMSIZO rir rmn emn 8K to 60K bytes RAM SIZE nicas aR 384 to 2048 bytes Package 80PO6N A enn re 0 8 mm pitch plastic molded QFP 80DO aene 0 8 mm pitch ceramic LCC EPROM version ROM size byte Being planned External f j i i i ROM U ee eee oe Under development aria 7 1 M38079E 001 1 1 0 oj Bengpames L le A M838078MC Being planned 32K M38077M8 28K 60K 24K 20K Mass product M38073M4 16 M38073E4 12K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size byte Note Products under development or planning the development schedule and specifications may be revised without notice Fig 4 Memory expansion plan Currently supported products are listed below Table 3 List of supported products As of May 1996 P ROM size bytes ROM size for User Product RAM size bytes Package Remarks M38073M4 XXXFP Mask ROM version
48. M38073M4 XXXFP MITSUBISHI ELECTRIC We recommend the use of the following pseudo command to set the start address of the assembler source program EPROM type 27256 27512 A 8000 0000 BYTE A M38073M4 BYTEA M38079M4 The pseudo command Note If the name of the product written to the EPROMs does not match the name of the mask confirmation form the ROM will not be processed 2 Mark specification Mark specification must be submitted using the correct form for the package being ordered Fill out the appropriate mark specification form 80P6N for M38073M4 XXXFP and attach it to the mask ROM confirmation form K 3 Usage conditions Please answer the following questions about usage for use in our product inspection 1 How will you use the Xin Xout oscillator Ceramic resonator Quartz crystal External clock input Other At what frequency Xin MHz 2 Which function will you use the pins P41 Xcin and P4o Xcour as P41 and P4o or Xcin and Xcout Ports P41 and P4o function L Xon and Xcour function external resonator X 4 Comments 2 2 3807 GROUP USER S MANUAL 3 57 APPENDIX 3 7 Mark specification form 3 7 Mark specification form 80P6N 80 PIN QFP MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below A B C and enter the Mitsubishi IC catalog name and the special mark if needed
49. MESE o LL interrupt enable bit Interrupt disabled Interrupt enabled CNTR1 interrupt enable bit Interrupt disabled i Interrupt enabled 2 Serial 1 02 interrupt enable bit O Interrupt disabled 1 Interrupt enabled 3 Timer 1 INT2 interrupt enable O Interrupt disabled bit 1 Interrupt enabled 4 Timer A interrupt enable bit O Interrupt disabled 1 Interrupt enabled 5 Timer B interrupt enable bit i Interrupt disabled Interrupt enabled ADT AD conversion interrupt Interrupt disabled enable bit Interrupt enabled Fix this bit to 0 o fofo Fig 3 5 38 Structure of Interrupt control register 2 3807 GROUP USER S MANUAL 3 55 APPENDIX 3 6 Mask ROM ordering method 3 6 Mask ROM ordering method GZZ SH11 00B lt 68A0 gt Mesk ROW umor 7 740 FAMILY MASK ROM CONFIRMATION FORM Date SINGLE CHIP MICROCOMPUTER M38073M4 XXXFP Section head Supervisor signature signature MITSUBISHI ELECTRIC Note Please fill in all items marked gt Submitted by Supervisor Company name Customer Issuance signature Date issued 1 Confirmation Specify the type of EPROMs submitted Three EPROMs are required for each pattern If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce
50. Operation patterns of motor 3807 GROUP USER S MANUAL 2 67 APPLICATION 2 4 Real time output port The motor is accelerated and decelerated by updating the timer value in the Timer interrupt processing routine Figure 2 4 10 shows an example of timer table for acceleration and deceleration A table common to both Timer A and Timer B is used in this application example As shown in the following figure the motor speed is controlled by setting a value in the low order side of the table first at acceleration and by setting a value the high order side of the table first at deceleration At a constant motor speed the motor operation is continued with the last timer value of acceleration Setting example for acceleration Setting example for deceleration Timer value set in Setting of Timer A for Setting of Timer A for Timer table Speed changing speed changing speed F42316 Timer A Low order Address 2F 16 Timer A Low order Address 2F 16 A2C216 TAL 2316 TAL E716 485616 28B016 Timer A High order Address 3016 Timer A High order Address 3016 1AC116 TAH F416 TAH 0316 12F616 0E4116 0B4A16 Timer A Low order Address 2F16 Timer A Low order Address 2F16 pise TAL C216 TAL EE16 07CFi6 06C216 O5F 916 056116 apps 497pps 04EB16 v Y 049B16 Timer A Low order Address 2F16 Timer A Low order Address 2F16 045216 TAL 5616 TAL 0016 l 8pps r
51. P30 RTPs O P30 latch i i Timer B interrupt 16 i request Real time output Timer B count Timer B read out latch 8 Real time port output selection bit P30 source stop bit LCE A A Real time port R W Real time port port 4 P30 direction register allocation selection bit a pointer A 3 o Real time port R W P87 RTP5 P87 latch _ pointer B 3 g boi bP LP T d Real time port Real time output i i i i i i register 0 8 Real time port output selection bit P87 Real time port register 1 8 lt E 1 1 1 i f Realtime port i f i register 2 8 P87 direction register o3 P 3 F i d Real time port i i i H register 3 8 P86 RTP4 P86 latch j Real time port i i i i NS register 4 8 Real time port Real ti tput i i i i register 5 8 eal time outpu H A Real time port output selection bit P86 i Beda Real time port i A register 7 8 P86 direction register Redi time port pet Real time port output allocation selection bit M pointer A 3 P8s RTP3 O P85 latch f Real time port output pointer B 3 Real time output Output latch 8 Real time port output selection bit P85 M P85 direction regist
52. P34 direction register P34 clock output control bit Microprocessor mode memory expansion mode P34 port latch Output clock frequency selection bits 000 P34 CKouT 9 Main clock division ratio 9 Low speed mode selection bits Note High speed or middle speed mode 444 O 010 cm Note Either high speed middle speed or low speed mode is selected by bits 7 and 6 of CPU mode register Fig 53 Block diagram of Clock output function 3807 GROUP USER S MANUAL 1 51 HARDWARE FUNCTIONAL DESCRIPTION Reset Circuit To reset the microcomputer RESET pin should be held at an L B Poweron i Z Note level for 2 us or more Then the RESET pin is returned to an H level Power source the power source voltage should be between 2 7 V and 5 5 V and voltage the oscillation should be stable reset is released After the reset is ov completed the program starts from the address contained in address Reset input FFFDt6 high order byte and address FEFC 6 low order byte Make voltage sure that the reset input voltage is less than 0 54 V for Vcc of 2 7 V RESET Internal reset Address Data SYNC ov Note Reset release voltage Vcc 2 7 V Power source d voltage detection circuit Fig 54 Reset circuit example Lin O E a 2X2 X X XK FFF X FFFD X ADH Reset address from the vector table 2 X9 X X XK AD
53. Setting time Output resistor IDAVREF Reference power source input current Note Note Using one D A converter with the value in the D A conversion register of the other D A converter being 0016 3 1 6 Analog comparator characteristics Table 3 1 9 Analog comparator characteristics Vcc 2 7 to 5 5 V Vss AVss 0 V CMPVcc 2 7 V to Vcc Ta 20 to 85 C unless otherwise noted Limits Typ Input offset voltage CMPVcc 5 0V 3 50 CMPREF 2 5V Rs 0Q Input bias current 5 Parameter Test conditions Input offset current 5 In phase input voltage range CMPVcc Voltage gain Response time CMPVcc 5 0V CMPREF 2 5V 3807 GROUP USER S MANUAL 3 7 APPENDIX 3 1 Electrical characteristics 3 1 7 Timing requirements Table 3 1 10 Timing requirements 1 Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Typ Symbol Parameter tw RESET Reset input L pulse width tc XIN External clock input cycle time tWH XIN External clock input H pulse width tWL XIN External clock input L pulse width tc CNTR CNTRo CNTR input cycle time twH CNTR CNTRo CNTR input H pulse width twL CNTR CNTRo CNTR input L pulse width twH INT INTo to INT4 input H pulse width twL INT INTo to INT4 input L pulse width tc SCLK1 Serial 1 01 clock input cycle time Note tWH SCL
54. When in serial 1 01 clock synchronous mode or in serial 1 02 an external clock is used as synchronous clock write transmission data to both the transmit buffer register and serial 1 02 register during transfer clock is H HARDWARE NOTES ON PROGRAMMING A D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low Therefore make sure that f XIN is at least on 500 kHz during an A D conversion When the ONW pin has been set to L the A D conver sion will take twice as long to match the longer bus cycle and so f XiN must be at least 1 MHz Do not execute the STP or WIT instruction during an A D conver sion D A Converter The accuracy of the D A converter becomes rapidly poor under the Vcc 4 0 V or less condition a supply voltage of Vcc 4 0 V is recommended When a D A converter is not used set all values of D Ai conversion registers i21 to 4 to 0016 Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction The number of cycles required to execute an instruction is shown in the list of machine instructions The frequency of the internal clock is half of the Xin frequency in high speed mode When the ONW function is used in modes other than single chip mode the frequency of the internal clock may be one fourth of the XIN fr
55. When the CNVss pin is connected to Vss the initial value becomes 0 When the CNVss pin is connected to Vcc the initial value becomes 1 2 Notes on STP instruction execution Make sure that the input level at each pin is either OV or to Vcc during execution of the STP instruction When an input level is at an inter mediate potential a current will flow from Vcc to Vss through the input stage gate 1 14 3807 GROUP USER S MANUAL 0 Port P2P3 control register P2P3C address 001516 P34 Clock output control bit 0 I O port 1 Clock output Output clock frequency selection bit 000 o 001 f Xcin 010 L fixed output 011 L fixed output 100 f Xin f Xcin in low speed mode 101 f Xim f Xin 2 110 f Xin f Xin 111 f Xin 16 Not used return 0 when read f Xcin 2 in low speed mode 4 f Xcin 4 in low speed mode f Xcin 16 in low speed mode P2 P32 input level selection bit 0 CMOS level input 1 TTL level input Fig 10 Structure of Port P2P3 control register Pull up control register b Kar address 001616 P0Oo P0s pull up control bit P04 P05 pull up control bit PO6 pull up control bit P07 pull up control bit P10 P13 pull up control bit P14 P17 pull up control bit P20 P23 pull up control bit P24 P27 pull up control bit Fig 11 Structure of Pull up control register 0 No pull up 1 Pull up Tab
56. XCIN Timer 1 Timer 2 count source selection bit Timer 2 write control bit y fr o Ti mer 2 latch lt interrupt request Timer 2 Timer 2 8 Ms f XiN 16 f XciN 16 in low speed mode La Tour output Tour output active control bit edge switch bit P50 TouT O D Qs q T P50 direction P50 latch Q register Tour output control bit f Xin 16 o f XciN 16 in low speed mode g Timer 3 Timer atch 8 interrupt request Timer 3 3 8 Qn Timer 3 count source selection bit Fig 27 Block diagram of Timer es 3807 GROUP USER S MANUAL interrupt request 1 33 HARDWARE FUNCTIONAL DESCRIPTION Real time output port The 3807 group has two on chip sets of real time output ports RTP The two sets of real time output ports consist of two 16 bit timers A and B and eight 8 bit real time port registers Synchronous to the reloading of timers A and B the real time port register values are output from ports P82 to P87 P30 and P31 The real time port regis ters consist of 8 bit register 0 to 7 Each port with its corresponding bits is shown in figure 26 Timer A and timer B have each two 16 bit timer latches Figure 28 shows the real time port block diagram and figure 29 and 30 show the structure of the real time port control registers 0 to 3 Ther
57. and received in the clock synchronous serial I O mode any one of data transmission and reception cannot be stopped Reason In the clock synchronous serial I O mode the same clock is used for transmission and reception If any one of transmission and reception is disabled a bit error occurs because transmission and reception cannot be synchronized In this mode the clock circuit of the transmission circuit also operates for data reception Accordingly the transmission circuit does not stop by clearing only the transmit enable bit to O transmit disabled Also the transmission circuit is not initialized by clearing the serial l O1 enable bit to 0 serial l O1 disabled refer to 1 4 The Srpy pin on a receiving side When signals are output from the SRDY pin on the reception side by using an external clock in the clock synchronous serial I O mode set all of the receive enable bit the SRDY output enable bit and the transmit enable bit to 1 transmit enabled 5 Stop of data reception in a clock synchronous serial I O mode Set the serial 1 01 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to 0 Set the bits 0 to 3 and bit 6 of the serial 1 01 control register Can be set with the LDM instruction at Set both the transmit enable the same time bit TE and the receive enable bit RE to 1 Clear b
58. b7 bo pao TT ttt P42 INTo Output mode Port P4 Address 0816 b7 bo Ps PJ fel P42 INTo Set to 1 at starting to communicate Fig 2 3 39 Setting of related registers at a transmitting side Communication using UART 2 58 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Receiving side Serial 1 O1 status register Address 1916 b7 bO SIO1STS Receive buffer full flag Check a completion of receiving 1 byte data with this flag 1 at completing to receive 0 at reading out a content of the Receive buffer register Overrun error flag 1 when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register Parity error flag 1 when parity error occurs at enabled parity Framing error flag 1 when data can not be received at the timing of setting a stop bit Summing error flag 1 when even one of the following errors occurs Overrun error Parity error Framing error Serial l O1 control register Address 1A16 b7 bO sio1con 1 ofifo Jo o BRG count source selection bit f XIN 4 Serial 1 01 synchronous clock selection bit BRG 16 SRDY1 output enable bit Not use SRDY1 out Transmit enable bit Transmit disabled Receive enable bit Receive enabled Serial 1 O1 mode selection bit Asynchronous serial l O UART Serial 1
59. bO Serial 1 02 control register 2 SIO2CON2 Address pal Serial 1 02 I O comparative P51 I O See aud Sour pin control bit P71 E Output active EXE remm T Coup gh inpesarce Fig 2 3 8 Structure of Serial 1 02 control register 2 Serial 1 02 register b7 b6 b5 b4 b3 b2 b1 bO Serial 1 O2 register SIO2 Address 1F16 A shift register for serial transmission and reception PAJE e At transmitting Set a transmission data e At receiving Store a reception data fejo KARE EARE KAGE ERG ae RAG Fig 2 3 9 Structure of Serial 1 02 register 3807 GROUP USER S MANUAL 2 33 APPLICATION 2 3 Serial I O Interrupt edge selection register b7 b6 b5 b4 b3 b2 bi bO Interrupt edge selection register INTEDGE Address 3A16 N rm interrupt edge AE Falling edge active selection bit Rising edge active INT interrupt edge T Falling edge active sa selection bit 1 Rising edge active 2 INT2 interrupt edge 0 Falling edge active selection bit 1 Rising edge active 3 INTs interrupt edge 0 Falling edge active selection bit 1 Rising edge active 4 INT24 interrupt edge 0 Falling edge active E Selection bit 1 Rising edge active 5 Timer 1 INT2 interrupt P INT2 interrupt source bit Timer 1 interrupt E Timer 2 INTs interrupt INTs interrupt MES source bit i Timer 2 interrupt Timer 3 INT4 interrupt INTA interrupt source bit E Timer 3 interrupt Fig 2 3 10 Structure of Inter
60. contents 32 Timer 1 002416 FF16 PCL FC16 contents 33 Timer 2 002516 0116 The initial values depend on level of port CNVss X Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset they must be set Fig 56 Internal status at reset 3807 GROUP USER S MANUAL 1 53 HARDWARE FUNCTIONAL DESCRIPTION Clock Generating Circuit The 3807 group has two built in oscillation circuits An oscillation circuit can be formed by connecting a resonator between XIN and XouT XCIN and Xcour Use the circuit constants in accordance with the resonator manufacturer s recommended values No external resistor is needed between Xin and Xour since a feed back resistor exists on chip However an external feed back resistor is needed between Xcin and Xcour Immediately after poweron only the XIN oscillation circuit starts oscillating and Xcin and Xcour pins function as I O ports Frequency control 1 Middle speed mode The internal clock is the frequency of Xin divided by 8 After reset this mode is selected 2 High speed mode The internal clock is half the frequency of Xin 3 Low speed mode The internal clock is half the frequency of XcIN llNote If you switch the mode between middle high speed and low speed stabilize both Xin and Xcin oscillations The sufficient time is required for the sub clock to stabilize
61. differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM I hexadecimal notation EPROM type indicate the type used 27256 27512 Md EPROM add In the address space of the microcomputer the internal ROM prada e TET doni a area is from address C08016 to FFFDie The reset vector is ASCII code ASCII code stored in addresses FFFC e and FFFDte 000F1s M38073M4 000Fis M38073M4 001016 001016 407F 6 CO7F 6 408016 C080 6 data ROM 16254 bytes 7FFDi6 FFFDie 7FFE16 FFFE e 7FFFis LLL PERE LZ 1 Set the data in the unused area the shaded area of Address Address the diagram to FF e 000016 M 4Di6 000816 2Di6 2 The ASCII codes of the product name M38073M4 000116 3 3316 000916 FFie must be entered in addresses 000016 to 000816 And 000216 8 3816 000A 6 FFi6 set the data FFie in addresses 000916 to OOOF e 000316 0 3016 000B 6 FFi6 The ASCII codes and addresses are listed to the right 000416 7 2 3716 000Ci6 FFie in hexadecimal notation 000516 3 3316 000D 6 FF e 000616 M 4D16 000E16 FFi6 000716 4 3416 O00F 16 FF 6 1 2 3 56 3807 GROUP USER S MANUAL APPENDIX 3 6 Mask ROM ordering method 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER
62. edge until the next rising edge During timer operation enabled The pulse period measurement starts by setting bit O or 1 of TXYCON to 0 and the timer counts down from the value that was set to the timer before the start of measurement When a valid edge of measurement start stop is detected the 1 s complement of the timer value is written to the timer latch and FFFF16 is set to the timer Furthermore when the timer underflows a timer X Y interrupt request occurs and FFFF16 is set to the timer The measured value is held until the next measurement completion Precautions Set the double function port of CNTRo CNTRt pin to input in this mode A read out of timer value is impossible in this mode The timer is written to only during timer stop no measurement of pulse periods Since the timer latch in this mode is specialized for the read out of measured values do not perform any write operations during measurement The timer is set to FFFF16 when the timer either underflows or a valid edge of pulse period measurement is detected Due to that the timer value at the start of measurement depends on the timer value before the start of measurement Figure 21 shows the timing chart of the pulse period measurement mode 1 24 4 Pulse width measurement mode Mode selection This mode can be selected by setting 011 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TY
63. especially immediately after poweron and at returning from stop mode When switching the mode between middle high speed and low speed set the frequency on condition that f XiN gt 3f XCIN 4 Low power consumption mode The low power consumption operation can be realized by stopping the main clock XiN in low speed mode To stop the main clock set bit 5 of the CPU mode register to 1 When the main clock Xin is re started by setting the main clock stop bit to 0 set enough time for oscillation to stabilize By clearing furthermore the Xcour drivability selection bit b3 of CPU mode register to 0 low power consumption operation of less than 55 uA Vcc 3 V Xcin 32 kHz can be realized by reducing the drivability between XciN and Xcour At reset or during STP instruc tion execution this bit is set to 1 and a reduced drivability that has an easy oscillation start is set The sub clock XciN Xcour oscillating circuit can not directly input clocks that are generated externally Ac cordingly make sure to cause an external resonator to oscillate Oscillation control 1 Stop mode If the STP instruction is executed the internal clock stops at an H level and Xin and Xcin oscillators stop Timer 1 is set to FF16 and timer 2 is set to 0116 Either XiN or XciN divided by 16 is input to timer 1 as count source and the output of timer 1 is connected to timer 2 The bits of the timer 123 mode register except timer 3 count sou
64. for controlling motor 1 This data is output at each underflow of the Timer A gt Sets the data for controlling motor 2 This data is output at each underflow of the Timer B Real time port control register 0 Address 2B16 b7 bO 1 rtecono 1 0 0 1 0 0 0 1 Timer A Timer B count source selection bit f Xin 16 Real time port port allocation selection bit 4 4 division Timer A start trigger selection bit Internal trigger gt Timer A start trigger bit Timer A is started by writing 1 gt Timer A count source stop bit Timer A is stopped by writing 1 gt Timer B start trigger selection bit Internal trigger gt Timer B start trigger bit Timer B is started by writing 1 Timer B count source stop bit Timer B is stopped by writing 1 Real time port control nearer 1 Address 2C16 b7 rtecont 1l1 ililifofolo S 00 XV Timer A operating mode selection bits 8 repeated load mode Real time port data pointer A switch bit 0 For reading the contents of the Real time port register or setting a value in the Real time port register 1 For specifying the output pointer Timer A interrupt mode selection bit Causes interrupt request at Timer A underflow Real time port data pointer A Specify Real time port register 7 Timer A write pointer Specify the Timer A1 latch Real time port control palate 2 Address 2D16 b 7 recone 1 1 1 o
65. from CNTR1 pin Timer X count and Timer Y count Stopped counting Timer X Timer mode Timer X count source selection bit f Xin 16 Set the division ratio so that the Timer X interrupt occurs every 2 ms Timer Y interrupt Disabled Timer X interrupt Enabled Set the Timer X interrupt request bit to 0 Timer X count and Timer Y count Started counting Interrupts Enabled Note 1 When using the Index X mode flag T Note 2 When using the Decimal mode flag D Push the register used in the interrupt processing routine into the stack When the count value is 256 or more the processing is performed as out of range Read the count value Store the count value in the accumulator A D616 A lt E416 Out of range Fpulse lt 0 reference value Store the comparison result in flag Fpulse Fpulse lt 1 Compare the count value read with the TYL Address 2216 FF16 TYH Address 2316 0016 Processing for a result of judgment Pop registers RTI nitialize the count value Popregisters which is pushed to stack Fig 2 2 24 Control procedure Measurement of frequency 2 24 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer 5 Timer application example 4 Measurement of pulse width of FG pulse generated by motor Outline The H level width of a pulse input to the P54 CNTRo pin is counted by Timer X An underflow is detected by Timer X in
66. group x1 Select an N channel open drain output control of TxD pin 2 Use such OUT pin of peripheral IC as an N channel open drain output in high impedance during receiving data Notes1 Port is an output port controlled by software 2 Use Sour and Sin2 instead of TxD and RxD in the Peripheral IC 2 serial 1 02 Fig 2 3 15 Serial I O connection examples 1 3807 GROUP USER S MANUAL 2 37 APPLICATION 2 3 Serial I O 2 Connection with microcomputer Figure 2 3 16 shows connection examples of the other microcomputers 1 Selecting an internal clock 2 Selecting an external clock 3807 group Microcomputer 3807 group Microcomputer 3 Using the Sroy sigan output function f A Selecting an external clock 4 Using UART 3807 group Microcomputer 3807 group Microcomputer UART can not be used in the serial 1 02 Note Use SouT2 and Sive instead of TxD and RxD in the serial 1 02 Fig 2 3 16 Serial I O connection examples 2 2 38 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O 2 3 4 Setting of serial I O transfer data format A clock synchronous or clock asynchronous UART is selected as a data format of the serial 1 01 The serial 1 02 operates in a clock synchronous Figure 2 3 17 shows a setting of serial I O transfer data format 1ST 8DATA 1SP ST LSB 1ST 7DATA 1SP ST ALSBX X X X X XMSBY sp 1ST 8DATA 1PAR 1SP ST AUSB XXX 0X 0X X088X PAR SP 1ST 7DATA 1PAR 1
67. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Re
68. interrupt edge selection bit INT2 interrupt edge selection bit 1 INT3 interrupt edge selection bit INT4 interrupt edge selection bit Timer 1 INT2 interrupt source bit bO Interrupt request register 1 b7 Interrupt request 0 Falling edge active Rising edge active Timer 2 INT3 interrupt source bit gt 0 INT interrupt selected Timer 3 INT4 interrupt source bit 1 Timer interrupt selected bO Interrupt request register 2 IREQ1 address 003C 6 INTo interrupt request bit INT interrupt request bit Serial l O1 receive interrupt request bit Serial l O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 INTs interrupt request bit Timer 3 INT4 interrupt request bit bO Interrupt control register 1 ICON1 address 003E16 IREQ2 address 003D16 CNTRo interrupt request bit CNTRt interrupt request bit Serial 1 02 interrupt request bit Timer 1 INT2 interrupt request bit Timer A interrupt request bit Timer B interrupt request bit ADT AD conversion interrupt request bit Not used returns 0 when read 0 No interrupt request issued 1 Interrupt request issued bO Interrupt control register 2 ICON2 address 003F 16 INTo interrupt enable bit INT1 interrupt enable bit Serial l O1 receive interrupt enable bit Serial l O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 INTs interrupt enabl
69. modified and the result is written in both the port latch of the port P3 and the external memory If the read enabled memory is not allocated at address 000616 the read datais undefined The undefined data is modified and written to the port latch of the port P3 The port latch data of port P3 becomes undefined 2 Overlap of an internal memory and an external memory When the internal and the external memory are overlapped in the memory expansion mode the internal memory is valid in this overlapped area When the CPU writes or reads to this area the following is performed When reading data Only the data in the internal memory is read into the CPU and the data in the external memory is not read into the CPU However as the read signal and address are still valid the external memory data of the corresponding address is output to the external data bus O When writing data Data is written in both the internal and the external memory 3807 GROUP USER S MANUAL 3 27 APPENDIX 3 3 Notes on use 3 3 7 Notes on built in PROM 1 Programming adapter To write or read data into from the internal PROM use the dedicated programming adapter and general purpose PROM programmer as shown in Table 3 3 1 Table 3 3 1 Programming adapter Programming adapter PCA4738L 80A Microcomputer M38073E4FS M38073E4FP PCA4738F 80A one time blank 2 Write and read In PROM mode operation is the same as that of the M5M27C256AK but pr
70. n is increased by 3 when T is 1 The number of cycles n is increased by 2 when T is 1 The number of cycles n is increased by 1 when T is 1 The number of cycles n is increased by 2 when branching has occurred N V and Z flags are invalid in decimal operation mode Notes akon 3 68 3807 GROUP USER S MANUAL APPENDIX 3 9 Machine instructions Addressing mode Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL 4 3 JOP OP JOP n JOP n JOP JOP JOP B D 3 9D 3 99 3 81 2 91 2 Contents Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Zero page addressing mode Shows direction of data flow Zero page bit relative addressing mode Index register X Index register Y Zero page X addressing mode Stack pointer Zero page Y addressing mode Program counter Absolute addressing mode Processor status register Absolute X addressing mode 8 high order bits of program counter Absolute Y addressing mode 8 low order bits of program counter Indirect absolute addressing mode 8 high order bits of address 8 low order bits of address Zero page indirect absolute addressing mode FF in Hexadecimal notation Immediate value Indirect X addressing mode Memory specified by address designation of any ad Indir
71. nnne 3 32 Fig 3 5 1 Structure of Port Pi 150 1 2 3 4 5b 7 Blind 3 34 Fig 3 5 2 Structure of Port Pi direction register i20 1 2 3 4 5 7 8 woes 3 34 Fig 3 5 3 Structure of Port PO eee entier etes retia er acd ede agen dad 3 35 Fig 3 5 4 Structure of Port P6 direction register sss 3 35 Fig 3 5 5 Structure of Timer XY control register 3 36 Fig 3 5 6 Structure of Port P2P3 control register susiuvu eiin 3 36 Fig 3 5 7 Structure of Pull up control register oooconccccnnncnnnncccnoccnnononnnnnncnnnnnn nn nano conan o nanann cnn 3 37 Fig 3 5 8 Structure of Watchdog timer control register mcinccnnnnnncnnnnccnnncnnnnnccccnannnananccnnnns 3 37 Fig 3 5 9 Structure of Transmit Receive buffer register sss 3 38 Fig 3 5 10 Structure of Serial l O1 status register 3 38 Fig 3 5 11 Structure of Serial 1 01 control register sessse 3 39 Fig 3 5 12 Structure of UART control register iissa arenis 3 39 Fig 3 5 13 Structure of Baud rate generator 3 40 Fig 3 5 14 Structure of Serial 1 02 control register 1 sse 3 40 Fig 3 5 15 Structure of Serial 1 02 control register 2 sss 3 41 Fig 3 5 16 Structure of Serial 1 02 register ssssssssssssssseeeneeenennn nnn 3 41 Fig 3 5 17 Structure of Timer X Low order Timer X High order Timer Y Low order Timer Y High order 3 42 3807 GROUP USER S MANUAL V List of figures Fig
72. of Real time output port related register 2 sssssssssss 1 38 31 8 repeated load mode operation ssssssseeeeenmeeneneen 1 39 32 6 repeated load mode Operation cd ete tuts toad co edu Fare dug 1 39 33 5 repeated load mode Operation eceeecccceeseeceeeeeeeeeeeeeeeeeeeeeeeaaeeeseeeeeeeeeteeeeeneeeees 1 40 34 One shot pulse generating mode operation sss 1 40 35 Block diagram of clock synchronous serial l O1 sssssseeeene 1 41 36 Operation of clock synchronous serial 1 01 function ooooooccccncccccnicncccnnnnncnananonononnnnos 1 41 37 Block diagram of UART serial l O1 ococcncnninicccninccnnnocccnonnnnnnnann nano conan rra nennen 1 42 38 Operation of UART serial 1 01 PUNCO Mascini 1 42 39 Structure of Serial 1 01 related register sssssssssssseeeenn 1 43 40 Structure of Serial 1 02 control register 1 2 oooconnoccccnnonoonncnnononnnnnnnanonnnncnnnnnnnnnncnnnns 1 44 41 Block diagramof Serial Ol iii tenet dece ip ee genter eae Tae lt 1 45 42 Timing of Serial l O2 ssseesssssssssssesesse ese ea Aaaa a eaaa nnn nannten 1 45 43 ScMP2 output OpOraltiOr ec entente ste etd rehenes ed eges tebe exu zen eR Pneu 1 46 44 Structure of A D control register nennen nnns 1 47 45 Block diagram of A D Converter ett efr e Fe oe De ka d cet 1 47 3807 GROUP USER S MANUAL i List of figures Fig 46 Structure of D A control register eee ee
73. output disable bit b7 of serial 1 02 control register 1 When the internal clock has been selected a transfer starts by a write signal to the serial 1 02 register address 001F16 After comple tion of data transfer the level of the Sour pin goes to high imped ance automatically but bit 7 of the serial 1 02 control register 2 is not set to 1 automatically When the external clock has been selected the contents of the serial 1 02 register is continuously sifted while transfer clocks are input Accordingly control the clock externally Note that the Soutz pin does not go to high impedance after completion of data trans fer To cause the Sour pin to go to high impedance in the case where the external clock is selected set bit 7 of the serial 1 02 control register 2 to 1 when ScLk2 is H after completion of data transfer After the next data transfer is started the transfer clock falls bit 7 of the serial 1 02 control register 2 is set to 0 and the Sour pin is put into the active state Regardless of the internal clock to external clock the interrupt re quest bit is set after the number of bits 1 to 8 bits selected by the optional transfer bit is transferred In case of a fractional number of bits less than 8 bits as the last data the received data to be stored in the serial 1 02 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial 1 02 control register 1 is LSB first
74. received data in the block Figure 2 3 36 shows the control in the slave unit using a serial l O1 receive interrupt and any timer interrupt for head adjustive Serial l O1 receive interrupt processing routine CLT Note 1 CLD Note 2 Push register to stack Push the register used in the interrupt processing routine into the stack Check the received byte counter to judge if a block n has been transfered ithin a block transfer period Y Read a reception data A received byte counter 1 A received byte counter 2 8 N Write a transmission data Write any data FF 6 Heading adjustive counter Initialized value Note 3 Pop registers e Pop registers which is pushed to stack Fig 2 3 36 Control in the slave unit 3807 GROUP USER S MANUAL Timer interrupt processing routine CLT Note 1 CLD Note 2 Push register to stack Heading adjustive counter 1 Heading adjustive counter 0 Push the register used in the interrupt processing routine into the stack Y Write the first transmission data first byte in a block A received byte counter lt 0 Pop registers Pop registers which is pushed to stack Notes 1 When using the Index X mode flag T 2 When using the Decimal mode flag D 3 In this example set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counte
75. register Address OF 16 P74 AN1 pin Input mode Fig 2 5 7 Setting of related registers Read for analog signal using an internal trigger 3807 GROUP USER S MANUAL 2 83 APPLICATION 2 5 A D converter Control procedure By setting the related registers as shown in Figure 2 5 8 the analog input voltage input from the sensor are converted into digital values X This bit is not used in this application Set it to 0 or 1 It s value can be disregarded e Select the P74 AN pin as an analog input pin ADCON Address y 3416 lt X0X1 00012 External trigger is invalid P7D Address OF16 XXXOXXXX2 e P74 AN1 pin Input mode ADCON Address 3416 bit4 0 Start A D conversion Check the completion of A D conversion Read out the conversion result Fig 2 5 8 Control procedure Read for analog signal using an internal trigger 2 84 3807 GROUP USER S MANUAL APPLICATION 2 5 A D converter 2 Read for analog signal using an external trigger Figure 2 5 9 shows a connection diagram and Figure 2 5 10 shows a setting of related registers ADVrer Reference voltage P74 AN1 P7s Srov2 ADT ANo External trigger E AVss Vss 3807 group Fig 2 5 9 Connection diagram Read for analog signal using an external trigger Specifications The analog input voltage input from the sensor is converted into digital values Note The P74 AN1 pin is used as an an
76. request 0 No interrupt request bit 1 Interrupt request 4 Timer A interrupt request bit 0 No interrupt request 1 Interrupt request 5 Timer B interrupt request bit 0 No interrupt request Pe 1 Interrupt request ADT AD conversion interrupt 0 No interrupt request 9 ole request bit 1 Interrupt request 7 Nothing is allocated for this bit This is a write disabled bit x When this bit is read out the value is 0 0 is set by software but not 1 Fig 2 5 4 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 bO of TT TTL Interrupt control reigster 2 ICON2 Address 3F 16 hot tot Name 1 Function latrese CNTRo interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled CNTR interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled Serial 1 02 interrupt enable 0 Interrupt disabled bi 1 Interrupt enabled Timer 1 INT2 interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled 1 1 Timer A interrupt enable bit 0 Interrupt disabled Interrupt enabled Timer B interrupt enable bit 0 Interrupt disabled Interrupt enabled ADT AD conversion interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled Fix this bit to 0 Fig 2 5 5 Structure of Interrupt control register 2 2 82 3807 GROUP USER S MANUAL APPLICATION 2 5 A D converter 2 5 3 A D conversion
77. result is stored in the accumulator Logical OR s the contents of memory indi cated by index register X and contents of memory specified by the addressing mode The result is stored in the memory specified by index register X 3807 GROUP USER S MANUAL APPENDIX 3 9 Machine instructions Addressing mode Processor status register ABS ABS X ABS Y IND ZP IND IND X IND Y REL 3 JOP JOP n JOP n JOP n JOP JOP n JOP n JOP D 4C 3 6C 5 3 B2 2 3807 GROUP USER S MANUAL 3 65 APPENDIX 3 9 Machine instructions Addressing mode Function Details A BIT A ZP BIT ZP n OP n JOP OP n M S A SeSs 1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1 M S PS c 8 1 Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1 S 8 1 A M S Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer Increments the contents of stack pointer by 1 and restores the processor status reg
78. signal of the INT4 pin The start trigger becomes a falling edge when the INT4 interrupt edge selection bit is 0 and a rising edge when this bit is 1 When the external trigger is selected in the one shot pulse genera tion mode the start trigger becomes a rising falling double edge trig ger regardless of the contents of the INT4 interrupt edge selection bit Real time port registers RTP The data to be output to real time ports is written into 8 real time port registers 0 to 7 The correspondence between each bit of real time port registers and each port output is as follows P31 bit 7 of real time port registers 7 to 0 P30 bit 6 of real time port registers 7 to O P87 bit 5 of real time port registers 7 to 0 P86 bit 4 of real time port registers 7 to O P85 bit 3 of real time port registers 7 to 0 P84 bit 2 of real time port registers 7 to O P83 bit 1 of real time port registers 7 to 0 P82 bit O of real time port registers 7 to 0 It can be selected for each bit by real time port control register 3 whether the output of each port is to be used as an ordinary I O port or a real time port output Real time port data pointer It can be optionally specified by the real time port data pointers A or B and the real time port data pointer A or B switching bit in which real time port register the output data is to be set or form which real time port register the data output is to be started When writing output data into the rea
79. the real time port register set the real time port data pointer A B switch bit to 0 select the R W pointer and also writing a value into the 3 bits of the real time port data pointer A B to specify the real time port register for reading After that the value of the HARDWARE FUNCTIONAL DESCRIPTION specified real time port register can be read by reading the real time port register address 002A16 In this care however the R W pointer value is not counted down automatically Accordingly to read an other real time port register rewrite the R W pointer beforehand To specify a read port register to be output to the real time output port set the real time port data pointer A B switch bit to 1 select an output pointer and also set a value in the 3 bits of the real time port data pointer A or B When a start trigger is generated data is output beginning with the real time port register set in the output pointer and the output pointer value is automatically decreased by 1 At each underflow of the timer A or timer B the output pointer value is automatically decreased by 1 Regarding the case of the one shot pulse generation mode however refer to the item pertaining to the one shot pulse generation mode When the real time port data pointer A to B has been read only the output pointer can be read Notes regarding all modes When the trigger is generated again during timer count operation the operation is sta
80. transmission data transmission data The Transmit buffer empty flag is set to 0 by this writing TB RB Address 1816 lt Check to be transferred data from the Transmit SIO1STS Address 1916 bit0 buffer register to the Transmit shift register Transmit buffer empty flag Write a transmission data The Transmit buffer empty flag is set to 0 by this writing Check to be transferred data from the Transmit s buffer register to the Transmit shift register SIO1STS Address 1916 bit0 Transmit buffer empty flag The second byte of TB RB Address 1816 a transmission data Check a shift completion of the Transmit shift register SIO1STS Address 1916 bit2 Transmit shift register shift completion flag 1 P4 Address 0816 bit2 0 End of communication Fig 2 3 41 Control procedure at a transmitting side Communication using UART 2 60 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O RESET X This bit is not used in this application Set it to O or 1 It s value can be disregarded Initialization SIO1CON Address 1A16 lt 1010X0012 UARTCON Address 1B16 XXXX1X002 BRG Address 1C16 8 1 PAD Address 0916 XXXXX0OXX2 SIO1STS Addr bit1 a ess 1916 Check a completion of receiving Receive buffer full flag 7 Read out a reception data Receive the first 1 byte data from RB Addres
81. 00 CHS Timer B operating mode selection bits 8 repeated load mode Real time port data pointer B switch bit 0 For reading the contents of the Real time port register or setting a value in the Real time port register 1 For specifying the output pointer Timer B interrupt mode selection bit Causes interrupt request at Timer B underflow gt Real time port data pointer B Specify Real time port register 7 gt Timer B write pointer Specify the Timer B1 latch Fig 2 4 15 Setting of related registers 1 2 72 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Real time port control poies 3 Address 2E16 b7 L gt Real time port output selection bit P82 RTPo Real time port output selection bi Real time port output selection bi gt Real time port output selection bit P85 RTP3 _ 0 I O port gt At stopping Timer A 1 Real time output port At operating Timer A gt Real time port output selection bi 0 I O port At stopping Timer B gt 1 Real time output port At operating Timer B gt Real time port output selection bi gt Real time port output selection bi gt Real time port output selection bit P31 RTP7 _ Timer A High order NUES 9016 TAH Timer A Low order Address 2F 6 A value is updated at each underflow of the Timer A b7 bo At acceleration or deceleration TA
82. 07 group one of the CMOS 8 bit microcomputer 38000 series presented in this user s manual is provided with standard functions The basic functions of the 3800 3802 3806 and 3807 groups having the same functions are shown below For the detailed functions of each group refer to the related data book and user s manual List of groups having the same functions 64 pin 64P4B 64P6N A 64P6D A Pin Package type 3802 group 3806 group 80 pin 80P6N A 80P6S A 80P6D A As of September 1996 3807 group Clock generating circuit 1 circuit 1 circuit 1 circuit 2 circuits lt 8 bit gt Prescaler 3 Timer 4 lt 8 bit gt Prescaler 3 Timer 4 lt 8 bit gt Prescaler 3 Timer 4 lt 8 bit gt Timer 3 lt 16 bit gt Timer X Y 2 Timer A B 2 UART or Clock synchronous X 1 Serial I O UART or Clock synchronous X 1 Clock synchronous X 1 UART or Clock synchronous X 1 Clock synchronous X 1 UART or Clock synchronous X 1 Clock synchronous X 1 A D converter 8 bit X 8 channel 8 bit X 8 channel 8 bit X 13 channel D A converter 8 bit X 2 channel 8 bit X 2 channel 8 bit X 4 channel Mask ROM One Time PROM 8K 16K o4 32K x Note 1 Note 1 Note 1 384 384 512 640 384 8K Note 1 16K Note 1 24K 32K Note 1 384 64 1024 i 0 4 12K 16K 24K 32K 48K Not
83. 1 Jolo 1 lolo Fig 2 2 4 Structure of Timer 1 Timer 3 Timer 2 b7 b6 b5 b4 b3 b2 b1 bO Timer 2 T2 Address 2516 BD Feeton aw o 0 e A count value of Timer 2 is set 1 Jojo l1 A value set in this register is written to both Timer 2 and a 0 Jojo corresponding Timer 2 latch at the same time or to only 0 lolol Timer 2 latch o a al e When this register is read out a value count value of a 0 folo corresponding Timer 2 is read out 0 Tolo 0 oto 0 lolo Fig 2 2 5 Structure of Timer 2 2 8 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer Timer X mode register b7 b6 b5 b4 b3 b2 bi bO Ti TT Tt Timer X mode register TXM Address 2716 Timer Event counter mode 1 Pulse output mode Pulse period measurement mode 1 Pulse width measurement mode Programmable waveform generation mode 1 Programmable one shot ME mode PWM mode Not available gene NM TIRE is To only latch 4 Output level latch a L output H output 5 CNTRo active edge switch bit i depends on the operating mode of the Timer X refer to Table 2 2 1 Timer X count source selection O 0 f Xin 2 Lo fofo bits f Xin 16 Er Lo Tela Input signal from CNTRo pin Fig 2 2 6 Structure of Timer X mode register Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register TYM Address 2816 Timer Event counter mo
84. 16 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F 16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Timer X low order TXL Timer X high order TXH Timer Y low order TYL Timer 2 T2 Timer A low order TAL Timer A high order TAH A D conversion register AD D A1 conversion register DA1 D A2 conversion register DA2 D A3 conversion register DA3 D A4 conversion register DA4 3807 GROUP USER S MANUAL 3 71 APPENDIX 3 12 Pin configuration 3 12 Pin configuration SIQV Zld lt gt vivid ELQV Sld clqv v ld lt gt LLIGV ELd OlqgVElLd lt gt 6QV Ld lt gt 8QV 0ld lt gt AV L0d lt gt 9Qv 90d lt gt sav S0d lt gt QV r0d lt gt edy 0d lt gt cQv z0d lt gt QV 0d lt gt 0Qv 00d lt gt du 4 d P UMEd lt gt ONAS SEd lt gt 9 LNOAD EA lt gt 1n0 3SdH t d MNO Ed Ldlu d lt gt 9d lu 0e d 4 P24 DB4 4 9 pP26 DBe 4 P27 DB7 Vss amp XOUT pPA4o XCOUT lt XN 4 CNVss o r aoa a a e oc N N aad o Y 38 P22 DB2 37 P23 DB3 35 P25 DB5 39 36 34 O alle oo EE oc er EOS amp d P85 RTP3 P84 RTP2 68 P83 RTP1 t 69 P82 RTPo
85. 16 Timer A high order 003016 16 Port P7 direction regis 000F 6 0016 Timer B low order 003116 17 Port P8 001016 0016 Timer B high order 003216 18 Port P8 direction register 001116 0016 D A control register 003316 19 Timer XY control register 001416 0 A D control register 003416 20 Port P2P3 control register 001516 D A1 conversion register 003616 21 Pull up control register 001616 D A2 conversion register 003716 22 Watchdog timer control register 001716 0 D A3 conversion register 003816 23 Serial 1 01 status register 001916 D A4 conversion register 003916 24 Serial 1 01 control register 001A16 Interrupt edge selection register 003A16 25 UART control register 001B16 CPU mode register 003B16 26 Serial 1 02 control register 1 001D16 6 Interrupt request register 1 003C16 27 Serial 1 02 control register 2 001E16 0 Interrupt request register 2 003D16 28 Timer X low order 002016 FF16 Interrupt control register 1 003E16 29 Timer X high order 002116 FF16 Interrupt control register 2 003Fi6 30 Timer Y low order 002216 FF16 Processor status register PS 1 31 Timer Y high order 002316 FF16 Program counter PCH FD16
86. 2016 Set FFFF e before starting measuring a pulse width TXL FF Interrupt control register 1 Address 3E16 cont app o E o o gt Timer X interrupt enable bit Interrupt enabled Interrupt request register 1 Address 3C16 b7 bo Rea fol gt Timer X interrupt request bit This bit is setto 1 at underflow of Timer X Interrupt control register 2 Address 3F 16 b7 b cone pp E CNTRo interrupt enable bit Interrupt enabled Interrupt request register 2 Address 3D16 rece C N o o TN CNTRo interrupt request bit This bit is set to 1 at completion of inputting H level signal Fon P5 direction register Address 0B16 po fo gt P54 CNTRo Input mode Fig 2 2 26 Setting of related registers Measurement of pulse width 2 26 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer Figure 2 2 27 and Figure 2 2 28 show a control procedure RESET Initialization SEI TXM Address 2716 lt 010X00112 P5D Address 0B16 XXXOXXXX2 TXYCON Address 1416 bitO 1 TXL Address 2016 255 TXH Address 2116 255 ICON1 Address 3E 6 bit4 1 IREQ1 Address 3C16 bit4 0 ICON2 Address 3F16 bitO 1 IREQ2 Address 3D16 bitO 0 TXYCON Address 1416 bitO 0 CLI Timer X interrupt processing routine Note P
87. 3 32 rada 3 32 O pU EUM MU 3 34 E 3 56 eee eee 3 58 3 59 ere 3 60 e 3 70 3 11 SFR memory Maphia suaa aaa a aHa aaa aaia daadaa a aanne Aaaa 3 71 3 12 Pin configurati on sssrinin rr 3 72 3807 GROUP USER S MANUAL iii List of figures List of figures CHAPTER 1 HARDWARE Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 1 Pin configuration of M38073M4 XXXFP ssssssssssssseseeeneeen rehenes nnne nnns nenne nen 1 2 2 Functional block diagram seiceanna aena E aae aea ia a a 1 3 3 Pait Numbering emnerne ee ee a 1 6 4 Memory expansion plan 0 eee eet cece eette eee eee non ee eee te nn eee ee nn n nc rn nana n rn r s nennen nennen nnn 1 7 5 740 Family CPU register structure c ooocnccccnnnccnonoccccncncnnnnnnnnnn cnn anna can rra nnne 1 8 6 Register push and pop at interrupt generation and subroutine call 1 9 7 Structure of CPU mode register ssssssssssssssesseeesenetn nennen tenens nnne 1 11 8 Memory Map diagtaln ecce treten nee eee te hu d De res peru rud Eu Ed cR ru 1 12 9 Memory map of special function register SFR sse 1 13 10 Structure of Port P2P
88. 3 5 18 Structure of Timer 1 Timer 3 enne ener 3 42 Fig 3 5 19 Structure of Timer Brin e veesii veda Ranes 3 43 Fig 3 5 20 Structure of Timer X mode register ssssssssssseeeene 3 44 Fig 3 5 21 Structure of Timer Y mode register sssssssssssssseeeee 3 44 Fig 3 5 22 Structure of Timer 123 mode register 3 46 Fig 3 5 23 Structure of Real time port register nccccccinnncinncccnnnonnnnnncccnnnrnnn nar n rn rra 3 46 Fig 3 5 24 Structure of Real time port control register 0 3 47 Fig 3 5 25 Structure of Real time port control register 1 3 48 Fig 3 5 26 Structure of Real time port control register 2 3 49 Fig 3 5 27 Structure of Real time port control register 3 3 50 Fig 3 5 28 Structure of Timer A Low order Timer A High order Timer B Low order Timer B High order 3 50 Fig 3 5 29 Structure of D A control register sssssseee eee 3 51 Fig 3 5 30 Structure of A D control register aussis aaan aei 3 51 Fig 3 5 31 Structure of A D conversion register ssssseseeeee 3 52 Fig 3 5 32 Structure of D Ai conversion register i 1 2 3 4 0 oooocnncccccnnccocccnnnnnnncnnncccnnnnos 3 52 Fig 3 5 33 Structure of Interrupt edge selection register ssssssssseees 3 53 Fig 3 5 34 Structure of CPU mode register eeecceeeceececeeeeeeeeseeeeeeneeenceeeeeeeeneeteeeneaeeneeees 3 53 Fig 3 5 35 Structure of Interrupt request register 1 3 54 Fig 3 5 35 Structure of Inte
89. 3 Serial I O Receiving side Serial l O1 status register Address 1916 b7 bo Receive buffer full flag Check a completion of receiving 1 byte data with this flag a At completing to receive 0 At reading out a receive buffer Overrun error flag 1 when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register Serial l O1 control register Address 1A16 Serial l O1 synchronous clock selection bit External clock SRDY1 output enable bit Use the SRDY1 output Transmit enable bit Transmit enabled Set this bit to 1 using SRDY1 output Receive enable bit Receive enabled Serial l O1 mode selection bit Clock synchronous serial I O Serial 1 O1 enable bit Serial 1 01 enabled Fig 2 3 21 Setting of related registers at a receiving side Communication using a clock synchronous serial 1 0 2 42 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Control procedure Figure 2 3 22 shows a control procedure at a transmitting side and Figure 2 3 23 shows a control procedure at a receiving side RESET X This bit is not used in this application Set it to O or 1 It s value can be disregarded Initialization SIO1CON Address 1A16 1101XX002 BRG Address 1C16 16 1 INTEDGE Address 3A16 bitO 9 IREQ1 Address 3C 16 bit0 Detect INTo falling edge 1 IREQ1 Addr
90. 3 control register 1 14 11 Structure of Pull up control register sssssssssseeeeeenenen 1 14 12 Port block diagraim 1 2 23 cere Made na cdi de 1 17 13 Port block diagram 2 coonnocccincccnnnnccconoccnononnnononcnnnnn nana cnn rca enne nnne nnne nnne nnn nnn nnn 1 18 14 Port block diagram 9 ient oneal seni 1 19 15 IMterrupticOntTO lus 1 22 16 Structure of interrupt related registers sssssssssssseeeeeeene enne 1 22 17 Block diagram of Timer X and Timer Y 1 27 18 Structure of Timer X mode register Timer Y mode register and Timer XY control register 1 28 19 Timing chart of Timer Event counter mode ssssem 1 29 20 Timing chart of Pulse output mode sssssssseeeneen nm enne nnns 1 29 21 Timing chart of Pulse period measurement mode sss 1 30 22 Timing chart of Pulse width measurement mode sse 1 30 23 Timing chart of Programmable waveform generating mode sssss 1 31 24 Timing chart of Programmable one shot generating mode ssuess 1 31 25 Timing chart of PWM mode uiridi cci tute a LASER uS 1 32 26 Structure of Timer 123 mode register sssssssssssseeeeeeeneee ne 1 33 27 Block diagram OT TIlmBl eiecti etes cee een ne eee 1 33 28 Block diagram of Real time output port 1 36 29 Structure of Real time output port related register 1 1 37 30 Structure
91. 3807 GROUP USER S MANUAL 2 11 APPLICATION 2 2 Timer Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 1 IREQ1 Address 3C16 B Name Funcion jwrese R W INTo interrupt request bit 0 No interrupt request 1 Interrupt request INT interrupt request bit 0 No interrupt request o Jo 1 Interrupt request i 2 Serial 1 01 receive interrupt 0 No interrupt request a request bit 1 Interrupt request 3 Serial 1 01 transmit interrupt O No interrupt request cs request bit 1 Interrupt request 4 Timer X interrupt request bit 0 No interrupt request o Jo 1 Interrupt request 5 Timer Y interrupt request bit 0 No interrupt request 1 Interrupt request Timer 2 INTs interrupt request O No interrupt request bit 1 Interrupt request 7 Timer 3 INT4 interrupt request 0 No interrupt request o Jo b 1 Interrupt request i it 0 is set by software but not 1 Fig 2 2 10 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 bO Biililll Interrupt request register 2 IREQ2 Address 3D16 Name Funcion atrese CNTRo interrupt request bit 0 No interrupt request 1 Interrupt request Ly CNTR interrupt request bit 0 No interrupt request 1 Interrupt request Serial 1 02 interrupt request 0 No interrupt request i 1 Interrupt request Timer A interrupt request bit 0 No int
92. 50 T out Port P5 Timer 2 output Timer 123 mode register 12 P51 ScMP2 External interrupt input Interrupt edge selection register 22 INT2 Serial 1 02 function I O Serial 1 02 control register P52 INT3 External interrupt input Interrupt edge selection register 7 P53 INT 4 Real time port trigger input INT4 P54 CNTRo Timer X Timer Y function I O Timer X mode register 13 P5s CNTR1 Timer Y mode register P56 DAt D A conversion output D A control register 14 P57 DA2 P60 ANs Port P6 A D conversion input A D control register 15 P62 AN7 P63 CMP iN Input CMOS compatible input level Analog comparator input pin A D control register 16 AN8 A D conversion input P64 CMPREF Analog comparator reference AN9 voltage input pin A D conversion input P65 DAVREF Input output CMOS compatible input level D A converter power source A D control register 17 AN10 individual bits CMOS 3 state output input A D conversion input P70 Sin2 Port P7 Serial 1 02 function I O Serial 1 02 control register 18 P71 Sout2 19 P72 ScLk2 20 P73 SrDY2 Serial 1 02 function I O Serial 1 02 control register 21 ADT ANo A D trigger input A D control register A D conversion input P74 AN1 A D conversion input A D control register 15 P77 AN4 HARDWARE FUNCTIONAL DESCRIPTION Table 7 List of I O port functions 2 Input Output 1 0 Format Non Port Function Related SFRs D A control register A D control register
93. 6 P73 Srpy2 ADT ANo P74 AN1 P75 AN2 P76 AN3 P77 AN4 P60 ANs P61 ANe P62 AN7 P63 CMPin ANs P64 CMPrer ANo9 P6s DAVrer AN10 P80 DA3 AN11 P81 DA4 AN12 4 AD conversion completion bit When A D trigger is invalid 0 Start conversion by writing to 0 1 Conversion completed 2222000000005 20000100008 O 00 00 0O O o o 0o0 0 0 0 08 When A D trigger is valid 0 Conversion in progress 1 Conversion completed 5 ADVner input switch bit 0 Connect only at A D conversion 1 Connect all time AD external trigger valid bit 0 A D external tirgger invalid 1 A D external tirgger valid 7 Interrupt source selection bit At conversion completed 1 At ADT falling input Fig 2 5 2 Structure of A D control register A D conversion register b7 b6 b5 b4 b3 b2 bi bO A D conversion register AD ai 3516 Fig 2 5 3 Structure of A D conversion register 3807 GROUP USER S MANUAL 2 81 APPLICATION 2 5 A D converter Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 bO Biilili l Interrupt request reigster 2 IREQ2 Address 3D16 B Name Fundion Atrese R w CNTRo interrupt request bit O No interrupt request 1 Interrupt request CNTR interrupt request bit 0 No interrupt request ee 1 Interrupt request 2 Serial 1 02 interrupt request 0 No interrupt request K bit 1 Interrupt request 3 Timer 1 INT2 interrupt
94. A A 2 37 2 3 4 Setting of serial I O transfer data format sse 2 39 caia 2 40 2 4 Real time output POllecccnnnnicinnnnccnrrrenrc erre 2 62 2 4 1 Memory map of real time output port 2 62 2 4 2 Related registers io dii tecto toten Leere iE ERE RE Ende 2 62 tania penca 2 67 2 5 A D CONVErterL cocino 2 80 ICON TRIP TN 2 80 FI EO 2 81 MNA MN MEN 2 83 AA OOE A 2 87 EE AE ee TEE 2 87 2 7 Application circuit example 1 esee 2 88 3807 GROUP USER S MANUAL Table of contents AAA AA CHAPTER 3 APPENDIX MEE 3 2 Alsat IAN DA mutet en Pad M aee d daa 3 2 IEEE 3 3 MI M Satin Cuhiesee 3 5 b e oU A 3 7 BC A URN 3 7 TEE 3 7 A E E E E E E EE 3 8 EEA dasa diana E EEEE EE E ANE EEA TA 3 9 ee 3 10 peas 3 10 A 3 17 T 3 17 n EE 3 18 TO 3 21 b c uu cu 3 22 e n E eat ee 3 23 3 24 ia a ci Aaa 3 24 3 3 2 Notes on the serial 1 01 ssssssssesee nnne 3 24 3 3 3 Notes on the A D converter ooocccccccoconnccccccccoococoncnononononenonononnnnnnnnnnononnnnnanononarnnanananons 3 25 323 4 Notes n the RESET pin iode reet Le dett te eere Laer ee eee roe E ansa ent dedecus 3 26 PNEU ADEM 3 26 3 27 po uU I M 3 28 M 3 29 p 3 29 een 3 30 RUM EM IM MM MM 3 31 A 3 31 tia
95. A D trigger is valid 0 Conversion in progress 1 Conversion completed 5 ADVner input switch bit 0 Connect only at A D conversion 1 Connect all time AD external trigger valid bit 0 A D external tirgger invalid 1 A D external tirgger valid 7 Interrupt source selection bit 0 At conversion completed 1 At ADT falling input ae O00oOoOoOoOooOoOGOg oOOooo oO0o0o00oR O2200 A100 002 O 20 00 00 108 Fig 3 5 30 Structure of A D control register 3807 GROUP USER S MANUAL 3 51 APPENDIX 3 5 List of registers A D conversion register b7 b6 b5 b4 b3 b2 bi bO A D conversion register AD la ahi 3516 Fig 3 5 31 Structure of A D conversion register D Ai conversion register b7 b6 b5 b4 b3 b2 bi bO D Ai conversion register DAI i 1 2 3 4 Address 3616 3716 3816 3916 1 A value which is set to this register is converted D A conversion Fig 3 5 32 Structure of D Ai conversion register i 1 2 3 4 3 52 3807 GROUP USER S MANUAL 2 The converted value is output from a corresponding DAi pin APPENDIX 3 5 List of registers Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register INTEDGE Address 3A16 n B interrupt edge De Falling edge active selection bit Rising edge active INT1 interrupt edge D Falling edge active SS selection bit 1 Rising edge active
96. A method for judging if input pulse exists 3807 GROUP USER S MANUAL 2 21 APPLICATION 2 2 Timer Timer Y mode register Address 2816 b7 bO rem afifi Jojo o Timer Y operating mode bits Timer Event counter mode Timer Y write control bit Write to a latch and a timer at the same time CNTR1 active edge switch bit Count at falling edge gt Timer Y count source selection bits Input signal from CNTR pin Timer X mode register Address 2716 0 b7 b nm oji fojojo Timer X operating mode bits Timer Event counter mode Timer X write control bit Write to a latch and a timer at the same time Timer X count source selection bits f Xin 16 Timer XY control register Address 1416 txycon fa Timer X stop control bit Stop counting set this bit to O at starting counting Timer Y stop control bit Stop counting set this bit to O at starting counting Timer Y High order Address 2316 b7 DO 00 6 Set to FF e before counting a pulse T d Y Low order ore 2216 After a certain time a number of inputted pulse is decremented from this value FFi6 Timer X High order Address 2116 b7 bo 0316 Uer X Low order Address 2016 Set division ratio 1 for making underflow every 2 ms input at inputting f Xin 8MHz E716 Fig 2 2 22 Setting of related registers 1 Measurement of frequency 2 22 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer
97. CM4 Port Xc switch bit 0 I O port function stop oscillating 1 Xcin Xcour oscillating function CMs Main clock Xin Xour stop bit 0 Operating 1 Stopped CM7 CMe Main clock division ratio selection bit b7 b6 0 f Xin 2 High speed mode f Xin 8 Middle speed mode f Xcin 2 Low speed mode available z 0 Q 1 16 2 1 Not Note 1 Switch the mode by the allows shown between the mode blocks Do not switch between the mode directly without an allow 2 The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended 3 Timer operates in the wait mode 4 When the stop mode is ended a delay of approximately 1 ms occurs by Timer 1 and Timer 2 in middle high speen mode 5 When the stop mode is ended a delay of approximately 0 25 s occurs by Timer 1 and Timer 2 in low speed mode 6 Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low speed mode to middle high speed mode 7 The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin indicates the internal clock Fig 60 State transitions of system clock 1 56 3807 GROUP USER S MANUAL Processor Mode Single chip mode memory expansion mode and microprocessor mode can be selected by changing the contents of the processor mode bits CMo and CM1 b1 and bO of address 003B16 In memory expansio
98. ES Clients cparvehesng erated PARS 1 Odd parity UL ims ON bit STPS 2 stop bits E A output mode 4 P45 TxD P channel E CMOS output output disable bit 1 N channel open drain POFF output Nothing is allocated for these bits These are write 6 disabled bits When these bits are read out the values are 1 Fig 2 3 5 Structure of UART control register 3807 GROUP USER S MANUAL 2 34 APPLICATION 2 3 Serial I O Baud rate generator b7 b6 b5 b4 b3 b2 bi b0 Baud rate generator BRG Address 1Cie Fig 2 3 6 Structure of Baud rate generator Serial 1 02 control register 1 b7 b6 b5 b4 b3 b2 b1 bO Serial l O2 control register 1 SIO2CON1 Address 1D16 B Name J Femen LEE ot Internal synchronous ESSE lock selection bits 2 f XiN XCIN C f Xin 16 XC f XiN 64 f XciN f XiN 128 f XiN 256 A ys f 8 16 f XiN 32 f XciN 32 64 f 128 256 XCIN Eine i11 5 TIN Soure ScLke MEM pin omen PP SRDV output pin 5 Transfer direction O LSB first pa ese eme ea Serial 1 02 synchronous clock A E a Soure P72 SCLK2 i output mode fossa MH N channel open drain output Note In low speed mode is selected Fig 2 3 7 Structure of Serial 1 02 control register 1 2 32 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Serial 1 02 control register 2 b7 b6 b5 b4 b3 b2 bi
99. GROUP USER S MANUAL APPENDIX 3 2 Standard characteristics 3 2 Standard characteristics 3 2 1 Power source current characteristic examples Figures 3 2 1 and Figure 3 2 2 show power source current characteristic examples Measuring condition 25 C f XCIN 32kHz A D conversion operatting in high speed mode Rectangular waveform Power source current may Vcc 5 0V Ta 25 C 9 Frequency f XiN MHz Fig 3 2 1 Power source current characteristic example Measuring condition 25 C f XCIN 32kHz A D conversion operatting in high speed mode Rectangular waveform Power source current y y e mA Vcc 5 0V Ta 25 C 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 Frequency f XiN MHz Fig 3 2 2 Power source current characteristic example in wait mode 3807 GROUP USER S MANUAL 3 17 APPENDIX 3 2 Standard characteristics 3 2 2 Port standard characteristic examples Figures 3 2 3 Figure 3 2 4 Figure 3 2 5 and Figure 3 2 6 show port standard characteristic examples Port P87 loH VoH characteristic P channel drive Pins with same characteristic PO P1 P2 P3 P4 P5 P60 P62 P65 P7 P8 CMPouT loH mA 100 90 80 70 60 50 40 Vec 5 5V Ta 90 C 20 Vcc 5 0V Ta 90 C
100. GROUP USER S MANUAL Table 8 Interrupt vector addresses and priority HARDWARE FUNCTIONAL DESCRIPTION Interrupt Source Priority Vector Addresses Note 1 Interrupt Request Remarka High Low Generating Conditions Reset Note 2 1 FFFD16 FFFC16 At reset Non maskable INTo 2 FFFB16 FFFA16 At detection of either rising or falling edge of External interrupt INTo input active edge selectable INT 3 FFF916 FFF816 At detection of either rising or falling edge of External interrupt INT input active edge selectable Serial 1 01 4 FFF716 FFF616 At completion of serial 1 01 data receive Valid when serial 1 01 is selected receive Serial 1 01 5 FFF516 FFF416 At completion of serial l O1 data transmit Valid when serial l O1 is selected transmit shift or when transmit buffer is empty Timer X 6 FFF316 FFF216 At timer X underflow Timer Y 7 FFF116 FFF016 At timer Y underflow INT3 8 FFEF16 FFEE16 At detection of either rising or falling edge of External interrupt INT3 input active edge selectable E Valid when INT3 interrupt is selected Timer 2 At timer 2 underflow Valid when timer 2 interrupt is selected INT4 9 FFED16 FFEC16 At detection of either rising or falling edge of External interrupt INT4 input active edge selectable Valid when INT4 interrupt is selected Timer 3 At timer 3 underflow Valid when timer 3 interrupt is selected CNTRo 10 FFEB16 FFEA16 At detection of either risi
101. If addressing mode is IND PCL M ADH ADL PCH M ADH ADL 1 If addressing mode is ZP IND PCL M 00 ADL PCH amp M 00 ADL 1 Jumps to the specified address M S PCH S lt S 1 M S PCL S lt S 1 After executing the above if addressing mode is ABS PCL ADL PCH lt ADH if addressing mode is SP PCL ADL PCH lt FF If addressing mode is ZP IND PCL M 00 ADL PCH M 00 ADL 1 After storing contents of program counter in stack and jumps to the specified address When T 0 AM When T 1 M X M Load accumulator with contents of memory Load memory indicated by index register X with contents of memory specified by the ad dressing mode M nn Load memory with immediate value Load index register X with contents of memory Load index register Y with contents of memory Shift the contents of accumulator or memory to the right by one bit The low order bit of accumulator or memory is stored in carry 7th bit is cleared M S A A X M zz X S lt S 1 Multiplies the accumulator with the contents of memory specified by the zero page X address ing mode and stores the high byte of the result on the stack and the low byte in the accumula tor NOP PC PC 1 No operation ORA Note 1 3 64 WhenT 0 ATAVM When T 1 M X MX VM Logical OR s the contents of memory and ac cumulator The
102. Input signal from CNTRt pin Fig 18 Structure of Timer X mode register Timer Y mode register and Timer XY control register 1 28 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION FFFF16 TL 000016 Yo y TR TR TL A value set to a timer latch TR Timer interrupt request Fig 19 Timing chart of Timer Event counter mode FFFF16 000016 Waveform output from CNTRo CNTRa pin CNTR CNTR TL A value set to a timer latch TR Timer interrupt request CNTR CNTRo ONTRt interrupt request This example s condition CNTRo CNTR active edge switch bit 0 gt output starts with H level interrupt at falling edge Fig 20 Timing chart of Pulse output mode 3807 GROUP USER S MANUAL 1 29 HARDWARE FUNCTIONAL DESCRIPTION FFFF16 FFFF16 T1 FFFF16 Signal input from CNTRo CNTR pin CNTR CNTR CNTR TR Timer interrupt request CNTR CNTRo CNTR interrupt request This example s condition CNTRo ONTR active edge switch bit set to 1 measure from rising edge to rising edge interrupt at rising edge Fig 21 Timing chart of Pulse period measurement mode 000016 TS T2 Tt FFFF16 FFFFis T2 3 T8 ia Signal inutfom4 ER CNTRo CNTRt pin CNTR CNTR CNTR TR Timer interrupt request CNTR CNTRo CNTR interrupt request This example s condition CNTRo CNTR active edge switch bit set to 1 measure L width interrup
103. Interrupt control register d Address 3E16 b7 Aii gt Timer X interrupt enable bit Interrupt enabled gt Timer Y interrupt enable bit Interrupt disabled Interrupt request register 1 Address 3C16 b7 bO gt Timer X interrupt request bit becomes 1 every 2 ms Port P5 direction register Address 0B16 eso fo TU Fig 2 2 23 Setting of related registers 2 Measurement of frequency gt P5s CNTR Input mode 3807 GROUP USER S MANUAL 2 23 APPLICATION 2 2 Timer Control procedure Figure 2 2 24 shows a control procedure RESET Initialization SEI Tym Address 28 5 111X00002 P5D TXYCON Address 2216 FF 6 TYL Address 0B16 XXOXXXXX2 1416 4 XXXXXX112 TXL Address 2016 E716 TXH Address 2116 0316 ICON1 Address 3E16 bits lt 0 ICON1 Address SE 6 bit4 lt 1 IREQ1 Address 3C 6 bit4 lt 0 TYH 2316 0016 TXM o d zm 01XX00002 TXYCON Address 1416 XXXXXX002 CLI Timer X interrupt processing routine CLT Note 1 CLD Note 2 Push register to stack TYH Address 2316 A lt TYL Address 2216 In range X This bit is not used in this application Set it to 0 or 1 It s value can be disregarded All interrupts Disabled Timer Y Timer Event counter mode Count at falling edge of pulse input
104. K1 Serial 1 01 clock input H pulse width Note twL SCLK1 Serial 1 01 clock input L pulse width Note tsu RXD SCLK1 Serial 1 01 clock input set up time th SCLK1 RXxD Serial 1 01 clock input hold time tc SCLk2 Serial 1 02 clock input cycle time twH SCLK2 Serial 1 02 clock input H pulse width twL SCLk2 Serial 1 02 clock input L pulse width tsu SIN2 SCLK2 Serial 1 02 clock input set up time th SCLK2 SIN2 Serial 1 02 clock input hold time Note When bit 6 of address 001A16 is 1 clock synchronous Divide this value by four when bit 6 of address 001416 is 0 UART Table 3 1 11 Timing requirements 2 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter tw RESET Reset input L pulse width tc XIN External clock input cycle time tWH XIN External clock input H pulse width tWL XIN External clock input L pulse width tc CNTR CNTRo CNTR input cycle time twH CNTR CNTRo CNTR input H pulse width twL CNTR CNTRo CNTR input L pulse width twH INT INTo to INT4 input H pulse width twL INT INTo to INT4 input L pulse width tc SCLK1 Serial 1 01 clock input cycle time Note tWH SCLK1 Serial 1 01 clock input H pulse width Note twL SCLK1 Serial 1 01 clock input L pulse width Note tsu RXD SCLK1 Serial 1 01 clock input set up time th SCLK1
105. L Timer B High order Address 3216 TBH A value is updated at each underflow of the Timer B Timer B Low order Address 3116 At acceleration or deceleration TBL Timer X mode register adress 2716 b7 nw ofa ojo ojo LL gt Timer X operating mode bits Timer Event counter mode gt Timer X write control bit write to a latch and a timer at the same time gt Timer X count source selection bits f Xin 16 Timer Y mode register Address 2816 bo b7 rem ofa fofojojo ______ Timer Y operating mode bits Timer Event counter mode Timer Y write control bit write to a latch and a timer at the same time gt Timer Y count source selection bits f Xin 16 Fig 2 4 16 Setting of related registers 2 3807 GROUP USER S MANUAL 2 73 APPLICATION 2 4 Real time output port Timer XY control register Address 1416 b7 TXYCON Exin 1 L gt Timer X stop control bit Stop counting Set 0 at starting counting Timer Y stop control bit Stop counting Set 0 at starting counting Timer X High order Address 2116 b7 DO TXH F416 Timer X Low order Address 2016 Set a value which need for counting the last b7 bO output period 62500 1 8pps of RTPO RTP3 TXL 2316 Timer Y High order Address 2316 b7 bo TYH F416 Timer Y Low order Addr 2246 Set a value which need for counting the last b7 e aurae dm output period 62500 1 8pps of RTP4
106. L 001216 003216 Timer B high order TBH 001316 003316 D A control register DACON 001416 Timer XY control register TXYCON 003416 A D control register ADCON 001516 Port P2P3 control register P2P3C 003516 A D conversion register AD 001616 Pull up control register PULL 003616 D A1 conversion register DA1 001716 Watchdog timer control register WDTCON 003716 D A2 conversion regis 001815 Transmit Receive buffer register TB RB 003816 D A3 conversion regis 001916 Serial 1 01 status register SIO1STS 003916 D A4 conversion regis 001A16 Serial 1 01 control register SIO1CON 003A16 Interrupt edge selection register INTEDGE 001Bie UART control register UARTCON 003B16 CPU mode register CPUM 001C16 Baud rate generator BRG 003C16 Interrupt request register 1 IREQ1 001D16 Serial 1 02 control register 1 SIO2CON1 003D16 Interrupt request register 2 IREQ2 001E16 Serial 1 02 control register 2 SIO2CON2 003E16 Interrupt control register 1 ICON1 001Fie Serial 1 02 register SIO2 003F16 Interrupt control register 2 ICON2 Fig 9 Memory map of special function register SFR 3807 GROUP USER S MANUAL 1 13 HARDWARE FUNCTIONAL DESCRIPTION 1 O Ports Direction Registers PiD The 3807 group has 68 programmable I O pins arranged in nine indi vidual I O ports PO P5 P60
107. L X ADH gt i i Xin 10 5 to 18 5 clock cycles Notes 1 The frequency relation of f Xin and f 6 is f Xin 8 f 0 2 The question marks indicate an undefined state that depends on the previous state Fig 55 Reset sequence 1 52 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Address Register contents Address Register contents Port PO 000016 0016 Timer 3 002616 FF16 Port PO direction regis 000116 0016 Timer X mode register 002716 0016 Port P1 000216 0016 Timer Y mode register 002816 0016 Port P1 direction regis 000316 0016 Timer 123 mode register 002916 0016 Port P2 000416 0016 Real time port register 0 7 002A16 0016 Port P2 direction regis 000516 0016 Real time port control register O 002B16 o 1 0 Port P3 000616 0016 Real time port control register 1 002Ci6 0 Port P3 direction regis 000716 0016 R W pointer Port P4 000816 0016 Output pointer 10 Port P4 direction regis 000916 0016 41 Real time port control register 2 002D16 11 Port P5 000A 16 0016 R W pointer 12 Port P5 direction regis 000Bt6 0016 Output pointer 13 Port P6 000C16 0016 Real time port control register 3 002E16 14 Port P6 direction regis 000D16 0016 Timer A low order 002F16 15 Port P7 000E 6 00
108. M Count source selection In high or middle speed mode f XiN 2 or f XiN 16 can be selected as the count source In low speed mode the count source is f XCIN Interrupt The interrupt generation at underflow is the same as already explained for the timer mode Bit 0 or 1 of IREQ2 is set to 1 syn chronously to pulse width measurement completion Explanation of operation During timer operation stop Select the count source Next select the interval of the pulse widths to be measured When bit 5 of TXM or TYM is set to 1 the timer counts during the interval of one falling edge of CNTRo CNTRt pin input until the next rising edge of input L interval If bit 5 is set to 0 the timer counts during the interval of one rising edge until the next falling edge H interval During timer operation enabled The pulse width measurement starts by setting bit O or 1 of TXYCON to 0 and the timer counts down from the value that was set to the timer before the start of measurement When a valid edge of measurement completion is detected the 1 s complement of the timer value is written to the timer latch and FFFF16 is set to the timer Furthermore when the timer underflows a timer X Y interrupt request occurs and FFFF16 is set to the timer The measured value is held until the next measurement completion WiPrecautions Set the double function port of CNTRo CNTRt pin to input in this mode A read out of timer value is impossible in thi
109. MPIN pin and the CMPRrer pin within the following range Vss 1 2 V to CMPVcc 0 5V HARDWARE FUNCTIONAL DESCRIPTION llNote The analog comparator circuit is separated from the MCU internal peripheral circuit in the microcomputer Accordingly even if the mi crocomputer runs away the analog comparator is still in operation For this reason the analog comparator can be used for safety circuit design CMPVcc P63 CMPin ANs P64 CMPrer ANo CMPout AVss Fig 49 Block diagram of Analog comparator 3807 GROUP USER S MANUAL 1 49 HARDWARE FUNCTIONAL DESCRIPTION Watchdog Timer The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop for example because of a software run away The watchdog timer consists of an 8 bit watchdog timer L and a 8 bit watchdog timer H Standard operation of watchdog timer When any data is not written into the watchdog timer control register address 001716 after resetting the watchdog timer is in the stop state The watchdog timer starts to count down by writing an optional value into the watchdog timer control register address 001716 and an internal resetting takes place at an underflow of the watchdog timer H Accordingly programming is usually performed so that writing to the watchdog timer control register address 001716 may be started before an underflow When the watchdog timer control register a
110. Makes it possible to read any data of Real time port registers 0 to 7 by specifying the Real time port data pointer R W pointer and reading data from this register Fig 3 5 23 Structure of Real time port register 3 46 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Real time port control register 0 b7 b6 b5 b4 b3 b2 b1 bO EE ERE Real time port control register 0 RTPCONO Address 2B16 Timer A Timer B count source 0 f Xin 2 selection bit 1 f Xin 16 4 4 division selection bit Corresponding ports to the Timer A P82 P85 Corresponding ports to the Timer B P86 P87 P3o P31 2 6 division Corresponding ports to the Timer A P82 P87 Corresponding ports to the Timer B P30 P31 Timer A start trigger selection Internal trigger bit occurs by writing 1 to bit 3 External trigger occurs by inputting trigger to the INT pin Note 3 Timer A start trigger bit No operating by writing 0 Timer A starts counting by writing 1 when bit 2 is set to 0 Timer A count source stop bit Operating is set to 0 automatically at genera ting a start trigger Stop Timer B start trigger selection Internal trigger bit occurs by writing 1 to bit 6 External trigger occurs by inputting trigger to the INT4 pin Timer B start trigger bit No operating by writing 0 Timer B starts counting by writing 1 when bit 5 is set to 0 Ti
111. NT4 peeve 0 2Vcc tw RESET RESET Nhu 0 p99 0 2Vcc TWH XIN TWL XIN tc ScLk1 tc SCLk2 gt tWL SCLK1 tWL SCLK2 tr tWH SCLK1 tWH SCLK2 J 0 2Vcc 0 8Vcc tsu RXD SCLK1 tsu SIN2 SCLK2 SOOO 0 8Vcc Y OOO OPOOOOOoO lt s 0 2Vcc td SCLK1 TXD td SCLK2 SOUT2 Fig 3 1 3 Timing diagram 1 in single chip mode th scLk1 RXD Th scLk2 SIN2 PSRRRRRRRRKREY 3807 GROUP USER S MANUAL tv SCLK1 TXD tv SCLK2 SOUT2 APPENDIX 3 1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode CMOS level input tc o E gt i TWH o ee twL 9 il 0 5Vcc td AH AD15 ADs AD7 ADo tSU ONW 4 OS CE tSU DB 9 BPE Cove gt At CPU reading ta o DB tv o DB At CPU writing Timing Diagram in Microprocessor Mode f RESET Naco Y f td RESET RESETOUT lv 6 RESETOUT RESETOUT 0 5Vcc Fig 3 1 4 Timing diagram 2 in memory expansion mode and microprocessor mode 3807 GROUP USER S MANUAL 3 13 APPENDIX 3 1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode CMOS level input tWL RD TWL WR tv RD AH tv WR AH AD1s ADs AD7 ADo tsu ONW WR ONW LOK DOOKIE SN At CPU reading RD B 0 5Vcc X I
112. NTRo CNTR1 active edge switch bit and the INTo INT1 interrupt edge selection bit The CNTRo CNTRt active edge switch bit and the INTo INT1 interrupt edge selection bit settings have an effect also on each interrupt active edge 1 26 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION CNTRO active edge Data bus switch bit Programmable one shot n generating mode RA2INTO O Programmable one shot TA generating circuit Programmable one shot generating mode PWM mode PWM generating circuit NTo interrupt request Programmable waveform generating mode Output level latch pulse output mode CNTRO active edge Switch bit A 001 1 Pulse output mode 400 o 110 Timer X operating Timer X latch low order Timer X latch high order mode bits P54 latch Timer X low order Timer X high order Timer X interrupt request P54 direction register J Pulse period measurement mode _ gt Pulse width measurement mode Edge detection circuit P54 CNTRO 2 9 gt J o f XIN 2 34 o CNTRO active tenye edge switch bit XCIN Timer X stop control bit Timer X count source selection bits gt CNTRo interrupt request CNTR1 active edge switch bit Progr
113. NUAL APPLICATION 2 4 Real time output port Il patterns for the Real time port registers 0 3 are completed to output Timer A is stopped completely Processing for updating data of RTPo RTP3 output All patterns for the Real time port registers 4 7 are completed to output Timer B is stopped completely Processing for updating data of RTP4 RTP7 output Fig 2 4 20 Control procedure 2 3807 GROUP USER S MANUAL 2 77 APPLICATION 2 4 Real time output port Processing for updating data of RTPo RTP output Note Execute the same processing for RTP4 RTP7 Timer B RTPCONO Address 2B 6 bit4 1 Timer A count is stopped TXL Address 2016 2316 Set the last output period TXH Address 2116 F446 TXYCON Address 1416 bitO lt 0 Timer X count is started IREQ1 Address 3C16 bit4 Is the last output completed TXYCON Address 1416 bitO 1 Timer X count is stopped A RTPCONS Address 2E 6 RTPo RTP5 output is switched to a port output A AJ8FO16 RTPCONS Address 2E 6 A Store the last output data to RAM A RTPCON1 Address 2C 6 A RTP data pointer value is set back the previous CLC value the last output pointer A A 1016 A lt A amp 7816 RTPCON1 Address 2C 6 A lt RTP Address 2A 6 Read out the last output data A A A amp FOte 4 low order bits of the last output dat
114. O X lo folx lo fo x lo fo x lo fo x 0 JO x Fig 2 2 2 Structure of Timer XY control register Timer X Low order Timer X High order Timer Y Low order Timer Y High order b7 b6 b5 b4 b3 b2 b1 bO Timer X Low order TXL Timer X High order TXH Address 2016 2116 Timer Y Low order TYL Timer Y High order TYH Address 2216 2316 e A count value of each timer is set e At writing eA value set in this register is written to both a Timer anda corresponding Timer latch at the same time or to only a Timer latch e A value is written to low order first e At reading When this register is read out a value count value of a corresponding Timer is read out A measurement value is read out in pulse period measure ment mode and pulse width measurement mode A value is read out from high order first Fig 2 2 3 Structure of Timer X Low order Timer X High order Timer Y Low order Timer Y High order 3807 GROUP USER S MANUAL 2 7 APPLICATION 2 2 Timer Timer 1 Timer 3 b7 b6 b5 b4 b3 b2 b1 bO Timer 1 T1 Timer 3 T3 Address 2416 2616 OBE mn a 10 e A count value of each Timer is set 1 Jojo inr A value set in this register is written to both each Timer i FOL and a corresponding Timer latch at the same time 1 Jojo e When this register is read out a value count value of a 1 olo corresponding Timer is read out 1 Tolo 1 lolol
115. O1 enable bit Serial l O1 enabled UART control register Address 1B16 bo b7 varrcoN jojo Character length selection bit 8 bits Parity enable bit Parity checking disabled Stop bit length selection bit 2 stop bits Baud rate generator Address 1C16 b7 bO f XIN Transfer bit rate X 16 X m sk when bit 0 of the Serial l O1 control register Address 1A16 is set to 0 a value of mis 1 when bit 0 of the Serial 1 01 control register Address 1A16 is set to 1 a value of m is 4 Port P4 direction register Address 0916 b7 bo pao Lt Tt fel gt P42 INTo Input mode Fig 2 3 40 Setting of related registers at a receiving side Communication using UART 3807 GROUP USER S MANUAL 2 59 APPLICATION 2 3 Serial I O Control procedure Figure 2 3 41 shows a control procedure at a transmitting side and Figure 2 3 42 shows a control procedure at a receiving side RESET X This bit is not used in this application Set it to O or 1 It s value can be disregarded Initialization SIO1CON Address 1A16 1001X0012 UARTCON Address 1B16 XXX01X002 BRG Address 1C16 8 1 P4 Address 0816 bit2 lt 0 P4D Address 0916 XXXXX1XX2 Set port P42 for a communication control An interval of 10 ms is generated by a timer Y P4 Address 0816 bit2 1 Start of communication The first byte of a Write a
116. P6 P7 P8 Set to the input mode and connect to Vcc or Vss through a resistor of 1 kO to 10 kQ Set to the output mode and open at L or H ADVREF Connect to VSS GND or open ONW Connect to Vcc through a resistor of 1 kQ to 10 kQ RESETouT Open Open SYNC Open AVss Connect to Vss GND CMPVcc Connect to Vss GND CMPouT Open XOUT Open only when using external clock 3807 GROUP USER S MANUAL 2 5 APPLICATION 2 2 Timer 2 2 Timer 2 2 1 Memory map of timer 001416 Timer XY control register TXYCON 002016 Timer X Low order TXL 002116 Timer X High order TXH 002216 Timer Y Low order TYL TYH 002316 002416 002516 002616 002716 002816 002916 003A16 Interrupt edge selection register INTEDGE 003C4e Interrupt request register 1 IREQ1 003D16 Interrupt request register 2 IREQ2 003E16 Interrupt control register 1 ICON1 003F16 Interrupt control register 2 ICON2 Fig 2 2 1 Memory map of timer related registers 2 6 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer 2 2 2 Related registers Timer XY control register b7 b6 b5 b4 b3 b2 b1 bO Timer XY control register TXYCON Address 1416 ee R Timer X stop control bit Start counting Stop counting Timer Y stop control bit 2 Start counting FADE Stop counting E Nothing is allocated for these S These are write disabled bits O
117. P62 P65 and P7 P8 The I O ports have direction registers which determine the input output direction of each individual pin Each bit in a direction register corresponds to one pin each pin can be set to be input port or output port When 0 is written to the bit corresponding to a pin that pin becomes an input pin When 1 is written to that pin that pin becomes an output pin If data is read from a pin set to output the value of the port output latch is read not the value of the pin itself Pins set to input the bit corre sponding to that pin must be set to 0 are floating and the value of that pin can be written to If a pin set to input is written to only the port output latch is written to and the pin remains floating Pull up Control Register PULL Ports PO P1 and P2 have built in programmable pull up resistors The pull up resistors are valid only in the case that the each control bit is set to 1 and the corresponding port direction registers are set to input mode 1 CMOS TTL input level selection Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32 The input level is selected by P2 P32 input level selection bit b7 of the port P2P3 control register address 001516 When the bit is set to 0 CMOS input level is selected When the bit is set to 1 the TTL input level is selected After this bit is re set its initial value depends on the state of the CNVss pin
118. PRreF Reference voltage input pin AN9 for analog comparator A D conversion input pin P65 DAVrEF I O port P6 e 1 bit CMOS I O port with the same function as port PO D A conversion power AN10 CMOS compatible input level source input pin CMOS 3 state output structure A D conversion input pin P7o SiN2 1 0 port P7 8 bit CMOS 1 O port with the same function as port PO Serial 1 02 function pins P71 S0UT2 e CMOS compatible input level P72 ScLk2 CMOS 3 state output structures P73 SRDY2 Serial 1 02 function pin ADT ANo A D conversion input pin A D trigger input pin P74 AN1 A D conversion input pin P77 AN4 P80 DA3 1 0 port P8 8 bit CMOS I O port with the same function as port PO D A conversion output AN11 CMOS compatible input level pin P81 DA4 CMOS 3 state output structures A D conversion input pin AN12 P82 RTPo Realtime port function P87 RTP5 pins 1 5 HARDWARE PART NUMBERING PART NUMBERING Product M3807 3 M 4 XXX FP Package type FP 80P6N A package FS 80D0 package ROM number Omitted in some types ROM PROM size 1 4096 bytes 8192 bytes 12288 bytes 16384 bytes 20480 bytes 24576 bytes 28672 bytes 32768 bytes 36864 bytes 40960 bytes 45056 bytes 49152 bytes 53248 bytes 57344 bytes 61440 bytes IMUON gt OO0XDOONAON The first 128 bytes and the last 2 bytes of ROM are reserved areas they cannot be used Memory type
119. Push register to stack processing routine into the stack Within a block transfer period Generate a certain block interval by using a timer or other functions Y Check the block interval counter and Read a reception data Count a block interval counter determine to start of a block transfer Complete to transfer a block Start a block transfer Y N White atranemission data Write the first transmission data first byte in a block lt e_m _ Pop registers e Pop registers which is pushed to stack Fig 2 3 35 Control in the master unit 2 54 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Control in the slave unit After a setting of the related registers is completed as shown in Figure 2 3 34 the slave unit becomes the state which is received a synchronizing clock at all times and the Serial l O1 receive interrupt request bit is set to 1 every time an 8 bit synchronous clock is received By the serial I O1 receive interrupt processing routine the data to be transmitted next is written to the Transmit buffer register after received data is read out However if no serial l O1 receive interrupt occurs for more than a certain time head adjustive time the following processing will be performed 1 The first 1 byte data of the transmission data in the block is written into the Transmission buffer register 2 The data to be received next is processed as the first 1 byte of the
120. REQ1 Address 3C e Name Fundin fies INTo interrupt request bit 0 No interrupt request Interrupt request 1 INT interrupt request bit 0 No interrupt request 1 Interrupt request 1 Serial 1 01 transmit interrupt O No interrupt request request bit 1 Interrupt request Timer X interrupt request bit 9 No interrupt request 1 Interrupt request Timer Y interrupt request bit 0 No interrupt request 1 Interrupt request Timer 2 INTs interrupt request 0 No interrupt request bit 1 Interrupt request Timer 3 INT4 interrupt request No interrupt request bit 1 Interrupt request 0 is set by software but not 1 Serial I O1 receive interrupt 0 No interrupt request request bit 1 Interrupt request of of of of of of of o pet xt x x s Fig 3 5 35 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 bO Billili Interrupt request reigster 2 IREQ2 Address 3D e hort Name Function atroset RW B CNTRo interrupt request bit 0 No interrupt request d 1 Interrupt request n CNTR interrupt request bit No interrupt request i 1 Interrupt request 2 Serial 1 02 interrupt request bit O No interrupt request l 1 Interrupt request l 3 Timer 1 INT2 interrupt 0 No interrupt request request bit 1 Interrupt request 4 Timer A interrupt request bit 0 N
121. RTP7 TYL 2316 Interrupt control register 1 Address 3E16 b7 cow ofo gt Timer X interrupt enable bit Interrupt disabled gt Timer Y interrupt enable bit Interrupt disabled Interrupt request register 1 Address 3C16 b7 bo reor fojoj gt Timer X interrupt request bit Judge a termination of the last output period of RTPO RTP3 gt Timer Y interrupt request bit Judge a termination of the last output period of RTP4 RTP7 Fig 2 4 17 Setting of related registers 3 2 74 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Interrupt control register 2 Address 3F 16 b7 bo BEEBEE gt Timer A interrupt enable bit Interrupt enabled gt Timer B interrupt enable bit Interrupt enabled Interrupt request register 2 Address 3D16 b7 0 l gt Timer A interrupt request bit gt Timer B interrupt request bit Port P3 Address 0616 b7 bo L gt P3yRTPs P31 RTP7 Output L level at stopping Timer B Port P3 direction register Address 0716 b7 0 P3o RTPe P31 RTP7 Output mode ron P8 Address 1016 bO gt P82 RTPo P85 RTPs Output L level at stopping Timer A P86 RTP4 P87 RTPs Output L level at stopping Timer B Port P8 direction register Address 1116 b7 e GELEET s Vv J gt P82 RTPo P87 RTPs Output mode Fig 2 4 18 Setting of related
122. RXxD Serial 1 01 clock input hold time tc SCLk2 Serial 1 02 clock input cycle time twH SCLK2 Serial 1 02 clock input H pulse width twL SCLk2 Serial 1 02 clock input L pulse width tsu SIN2 SCLK2 Serial 1 02 clock input set up time th SCLK2 SIN2 Serial 1 02 clock input hold time Note When bit 6 of address 001A16 is 1 clock synchronous Divide this value by four when bit 6 of address 001416 is 0 UART 3 8 3807 GROUP USER S MANUAL APPENDIX 3 1 Electrical characteristics 3 1 8 Switching characteristics Table 3 1 12 Switching characteristics 1 Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Symbol Parameter Test conditions Min tWH SCLK1 Serial 1 01 clock output H pulse width twL SCLK1 Serial 1 01 clock output L pulse width td SCLK1 TXD Serial l O1 output delay time Note 1 tv ScLK1 TXxD Serial l O1 output valid time Note 1 tr SCLK1 tr SCLK1 Serial 1 01 clock output rising time Serial 1 01 clock output falling time Fig 3 1 1 tc ScLk1 2 30 tc ScLk1 2 30 30 twH SCLK2 Serial 1 02 clock output H pulse width twL SCLK2 Serial 1 02 clock output L pulse width ta ScLk2 SOUT2 Serial 1 02 output delay time Note 2 tv SCLK2 SOUT2 Serial 1 02 output valid ti
123. SP sTXiIBX X X X X _XMSBXPAR SP 1ST 8DATA 2SP ST LSB 1ST 7DATA 2SP ST LSB 1ST 8DATA 1PAR 2SP STXLSBX X X X X X _XMSBXPAR Y 2SP 1ST 7DATA 1PAR 2SP ST LSB Clock synchronous Serial I O LSB first ST Start bit LSB first 1 to 8 bit optional transfer SP Stop bit Serial Clock synchronous 1 02 Serial I O PAR Parity bit MSB first 1 to 8 bit optional transfer Fig 2 3 17 Setting of Serial I O transfer data format 3807 GROUP USER S MANUAL 2 39 APPLICATION 2 3 Serial I O 2 3 5 Serial I O application examples 1 Communication using a clock synchronous serial I O transmit receive Outline 2 byte data is transmitted and received through the clock synchronous serial I O The Sapyi signal is used for communication control Figure 2 3 18 shows a connection diagram and Figure 2 3 19 shows a timing chart Transmitting side Receiving side 3807 group 3807 group Fig 2 3 18 Connection diagram Communication using a clock synchronous serial I O Specifications The Serial l O1 is used clock synchronous serial I O is selected Synchronous clock frequency 125 kHz f XIN 8 MHz is divided by 64 The Srov receivable signal is used e The receiving side outputs the Sarpy signal at intervals of 2 ms generated by timer and 2 byte data is transferred from the transmitting side to the receiving side m
124. SU DB RD th RD DB DBo DB7 ee p At CPU writing WR Bs 0 5Vcc X ta wR DB tvwa D8 Fig 3 1 5 Timing diagram 3 in memory expansion mode and microprocessor mode 3 14 3807 GROUP USER S MANUAL APPENDIX 3 1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode TTL level input tc o twH 9 twL o le gt kk gt oA K A td I9 9 AH AH tv o AH ADis ADo Mte AY AL lv v o AL tSU ONW 6 DOKKEN tSU DB 4 At CPU reading td o DB tv o DB oe E At CPU writing Timing Diagram in Microprocessor Mode A S RESET Nga OM OSC C S td RESET RESETOUT tv o RESETOUT DEQETA 2 0V RESETOUT 0 8V Fig 3 1 6 Timing diagram 4 in memory expansion mode and microprocessor mode 3807 GROUP USER S MANUAL 3 15 APPENDIX 3 1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode TTL level input twL RD TtWL WR RD WR 0 Nm y 0 8V td AH RD tviAD AH te ta aH WR gt e tv WR AH ADs ADs MET ta AL RD tv RD AL td AL WR iis gt gt e tv WR AL AD7 ADo Min RD tsu ONW RD th RD ONW tsu ONW WR th WR ONW ONW XOX 0 i y l At CPU reading RD tsu DB RD DBo DB7 At CPU writing WR DBo DB7 Fig 3 1 7 Timing diagram 5 in memory expansion mode and microprocessor mode 3 16 3807
125. Set to 0 before starting to transmit Port P5 direction register Address 0B16 b7 b MORONA gt P53 INT4 Output mode Fig 2 3 26 Setting of serial l O1 related registers Output of serial data 2 46 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Transmit Receive buffer register Address 1816 b7 bO Set a transmission data TB RB o Check that transmission of the previous data is completed before writing data bit 3 of the Interrupt request register 1 is set to 1 Fig 2 3 27 Setting of serial l O1 transmission data Output of serial data 3807 GROUP USER S MANUAL 2 47 APPLICATION 2 3 Serial I O Control procedure When the registers are set as shown in Fig 2 3 26 the Serial l O1 can transmit 1 byte data simply by writing data to the Transmit buffer register Thus after setting the CS signal to L write the transmission data to the Receive buffer register on a 1 byte base and return the CS signal to H when the desired number of bytes have been transmitted Figure 2 3 28 shows a control procedure of serial 1 01 RESET This bit is not used in this application Set it to 0 or 1 It s value can be disregarded Initialization SIO1CON Address 1A16 lt 110110002 e Set the Serial 1 01 UARTCON Address 1B16 bit4 lt 0 BRG Address ICON1 Address P5 Address P5D Address 1C16 lt 16 1 3E16 bits lt 0 e Serial 1 01 transm
126. Timer A start trigger bit O at read out 0 Not triggered 1 Timer A start when bit 2 0 Timer A count source stop bit 0 Count operation when a start trigger is generated 0 is set automatically 1 Count stop Timer B start trigger selection bit 0 Internal trigger trigger is generated by setting bit 6 to 1 1 External trigger trigger start by external input INT4 note Timer B start trigger bit O at read out 0 Not triggered 1 Timer B start when bit 5 0 Timer B count source stop bit 0 Count operation when a start trigger is generated 0 is set automatically 1 Count stop Note Rising or falling edge of external input can be switched by the INT4 interrupt edge selection bit of interrupt edge selection register however at one shot pulse generating mode the timer is triggered at both rising and falling edge b7 bO Real time port control register 1 RTPCON1 address 002C16 Timer A operation mode selection bit 00 8 repeated load mode 01 6 repeated load mode 10 5 repeated load mode 11 One shot pulse generating mode Real time port data pointer A switch bit 1 at read out 0 R W pointer 1 Output pointer Timer A interrupt mode selection bit O Interrupt request occurs with RTP output pointer value 0002 1 Interrupt request occurs regardless of RTP output pointer value Real time port data pointer A output pointer value at read out 000 indicates real time por
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128. V f XIN stopped f XCIN 32 768kHz in WIT state Low power dissipation mode CM8 0 Output transistors off Middle speed mode f XIN 8MHz f XCIN stopped Output transistors off Middle speed mode f XIN 8MHz in WIT state f XCIN stopped Output transistors off Increment when A D conversion is executed f XIN 8MHz All oscillation stopped in STP state Ta 25 C Output transistors off Ta 85 C Analog comparator Power source current 3 6 3807 GROUP USER S MANUAL APPENDIX 3 1 Electrical characteristics 3 1 4 A D converter characteristics Table 3 1 7 A D converter characteristics Vcc 2 7 to 5 5 V Vss AVss 0 V ADVREF 2 0 V to Vcc Ta 20 to 85 C unless otherwise noted Limits Typ Parameter Test conditions Resolution Absolute accuracy excluding quantization error VCC ADVREF 5 0V tCONV Conversion time RLADDER Ladder resistor IADVREF Reference power ADVREF on ADVREF 5 0V Source input current ADVREF gl I AD A D port input current 3 1 5 D A converter characteristics Table 3 1 8 D A converter characteristics Vcc 2 7 to 5 5 V Vss AVss 0 V DAVREF 2 7 V to Vcc Ta 20 to 85 C unless otherwise noted Limits Typ Parameter Test conditions Resolution Absolute accuracy VCC 4 0 to 5 5V VCC 2 7 to 4 0V
129. WARE FUNCTIONAL DESCRIPTION Timer 1 count source selection bits Timer 2 count source selection bit Timer 2 112 Q High speed or middle speed mode Main clock division ratio selection bits note Middle speed mode High speed or low speed mode Main clock stop bit S Timing o internal clock R STP instruction WIT instruction Reset Interrupt disable flag Interrupt request H STP instruction Note Either high speed middle speed or low speed mode is selected by bits 7 and 6 of CPU mode register When low speed mode is selected set port Xc switch bit b4 to 1 Fig 59 System clock generating circuit block diagram Single chip mode 3807 GROUP USER S MANUAL 1 55 HARDWARE FUNCTIONAL DESCRIPTION Middle speed mode f 6 21MHz CM6 CM7 0 A a CM6 1 CM5 0 8MHz oscillating CMa 0 32kHz stopped Middle speed mode 1 6 1MHz CM7 0 CMe 1 CMs 0 8MHz oscillating CMa 1 32kHz oscillating High speed mode 1 9 4MHz CM7 0 CMe 0 CMs5 0 8MHz oscillating CM4 0 32kHz stopped High speed mode f 0 4MHz CM7 0 CMe 0 CMs5 0 8MHz oscillating CMa 1 32kHz oscillating Low speed mode f 0 16kHz CM7 1 CMe 0 CMs 0 8MHz oscillating b7 CMa 1 32kHz oscillating b4 CPU mode register Low speed mode f 6 216kHz CM7 1 CMe 0 CMs 1 8MHz stopped CMa 1 32kHz oscillating CPUM address 003B16
130. Y are independent 16 bit timers which can select enable seven different operation modes each by the setting of their mode registers The related registers of timer X and Y are listed below The following register abbreviations are used e Timer XY control register TXYCON address 001416 Port P4 direction register PAD address 000916 Port P5 direction register P5D address 000B16 Timer X low order TXL address 002016 Timer X high order TXH address 002116 Timer Y low order TYL address 002216 Timer Y high order TYH address 002316 Timer X mode register TXM address 002716 Timer Y mode register TYM address 002816 Interrupt edge selection register INTEDGE address 003A16 Interrupt request register 1 IREQ1 address 003C16 Interrupt request register 2 IREQ2 address 003D16 Interrupt control register 1 ICON1 address 003E 16 Interrupt control register 2 ICON2 address 003F 16 For details refer to the structures of each register The following is an explanation of the seven modes 1 Timer event counter mode Timer mode Mode selection This mode can be selected by setting 000 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TYM Count source selection In high or middle speed mode f XIN 2 f XiN 16 or f Xcin can be Selected as the count source In low speed mode the count source is f XcIN A
131. a Read Gut reception data from A Receive buffer full flag is set to 0 by reading data TB RB Address 1816 Check a completion of receiving SIO1STS Address 1916 bit Receive byner minag Read out reception data from Receive the second byte data TB RB Address 1816 A Receive buffer full flag is set to 0 by reading data Fig 2 3 23 Control procedure at a receiving side Communication using a clock synchronous serial 1 0 2 44 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O 2 Output of serial data control of a peripheral IC Outline 4 byte data is transmitted and received through the clock synchronous serial I O The CS signal is output to a peripheral IC through the port P53 3807 group Peripheral IC 3807 group Peripheral IC 1 Example for using Serial 1 01 2 Example for using Serial 1 02 Fig 2 3 24 Connection diagram Output of serial data Specifications The Serial I O is used clock synchronous serial I O is selected Synchronous clock frequency 125 kHz f XIN 8 MHz is divided by 64 Transfer direction LSB first e The Serial I O interrupt is not used The Port P53 is connected to the CS pin L active of the peripheral IC for a transmission control the output level of the port P53 is controlled by software Figre 2 3 25 shows an output timing chart of serial data DX ed bd ex DATA j vo A pi oor A joo fos Note The Sour pin is
132. a are stored to The last data A RAM All patterns are completed Y E Judges whether real time port registers 0 to 3 output the data for forward rotation or the data for reverse rotation next in order to determine which output data table is to be used RTPCON t Address 2C16 Output pointer Sets the output pointer so that the output may be started with the last output data of the previous pattern Address Address TAL Address TAH Address TAL TBL Address TAH Initial value Initial value Set an initial value to the Timer A1 latch Initial value The next latch is specified Initial value Set an initial value to the Timer AO latch lt automatically Initial value TBH Address Initial value Set an initial value to the Timer B1 latch TBL Address J TBH Address The next latch is specified Initial value automatically Initial value Set an initial value to the Timer BO latch 11111111 o T 0 Set the Timer A interrupt request bit to 0 IREQ2 Address 3D16 HTPCONO Address 2B16 bit3 y A RTPCONS Address 2E16 Timer A Start counting A lt A or OF 16 The port output is switched to the RTP output RTPCON3 Address 2E16 lt A Set the all patterns completion flag yd Fig 2 4 21 Control procedure 3 2 78 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Timer A interrupt processing
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134. alog input pin A D conversion start with an external trigger by inputting a falling edge to the P73 SrDY2 ADT ANO pin Note Example When a reference voltage 5 12 V is input to the ADVREF pin and a voltage 4V to the P74 AN1 pin an input voltage is converted to a following value 256 5 12 V X 4 V 200 C816 A D control register Address 3416 En input pin selection bits Select the P74 AN1 pin gt AD conversion completion bit Conversion completed Note 1 AD external trigger valid bit Valid A D conversion register Address 3516 Store a result of A D conversion Note 2 Port P7 direction register Address OF 16 gt P73s Snbvz ADT ANo pin Input mode gt P74 AN pin Input mode Note 1 An external trigger becomes valid by setting this bit to 1 When bit 6 is set to 1 and bit 4 to 0 at the same time A D comversion may start at that time 2 Read out a result of A D conversion after bit 4 of the A D control register ADCON is set to 1 Fig 2 5 10 Setting of related registers Read for analog signal using an external trigger 3807 GROUP USER S MANUAL 2 85 APPLICATION 2 5 A D converter Control procedure By setting the related registers as shown in Figure 2 5 11 the analog input voltage input from the sensor are converted into digital values X This bit is not used in this application Set it to O or 1 It
135. alue can be disregarded Timer A and Timer B counts are stopped Timer A Selecting 8 repeated load mode setting R W pointer to Real time port register 7 and specification of Timer A1 latch Timer B Selecting 8 repeated load mode setting R W pointer to Real time port register 7 and specification of Timer B1 latch e P82 RTPo P87 RTPs P30 RTPs P31 RTP7 I O port Timer X Timer Event counter mode Timer Y Timer Event counter mode Initialization for ports L is output at stopping a stepping motor Each value of the table is set to the Real time port registers 0 7 A value of R W pointer is automatically decreased by 1 initial val he Timer A1 latch a e Set an initial value to the Timer A1 latc Th next latch is specified Set an initial value to the Timer AO latch d automatically e Set an initial value to the Timer B1 latch B The next latch is specified e Set an initial value to the Timer BO latch d automatically e Timer A interrupt Interrupt enabled The Timer A interrupt request bit is set to 0 Timer B interrupt Interrupt enabled The Timer B interrupt request bit is set to 0 Timer A An output pointer is set to the Real time port register 7 Timer B An output pointer is set to the Real time port register 7 Timer A Start counting Timer B Start counting The port output is switched to the RTP output 3807 GROUP USER S MA
136. ammable one shot qu generating mode P43 INT1 O 4 gt 1 gt o o Programmable one shot generating circuit Programmable one shot generating mode PWM mode PWM generating circuit INT interrupt request Programmable waveform generating mode Output level latch Pulse output mode CNTRI active edge S Switch bit D T apo Pulse output mode 001 100 101 110 Timer Y operating Timer Y latch low order Timer Y latch high order mode bits P55 latch Timer Y low order Timer Y high order Timer Y interrupt request P55 direction register J Pulse period measurement me Pulse width measurement mode Edge detection circuit CNTRI interrupt request P55 CNTR1 Q J f XIN2 34 XIN 16 XCIN CNTRt active edge switch bit Timer Y stop control bit Timer Y count source selection bits Fig 17 Block diagram of Timer X and Timer Y 3807 GROUP USER S MANUAL 1 27 HARDWARE FUNCTIONAL DESCRIPTION Timer X mode register TXM address 002716 Timer X operating mode bits bi b 0 Timer event counter mode 0 Pulse output mode 1 Pulse period measurement mode 1
137. and SE b3 to b6 respec tively Writing 0 to the serial l O1 enable bit SIOE b7 of the serial 1 01 control register also clears all the status flags including the error flags Serial 1 O1 status register SIO1STS address 001916 Transmit buffer empty flag TBE 0 Buffer full 1 Buffer empty Receive buffer full flag RBF 0 Buffer empty 1 Buffer full Transmit shift register shift completion flag TSC 0 Transmit shift in progress 1 Transmit shift completed Overrun error flag OE 0 No error 1 Overrun error Parity error flag PE 0 No error 1 Parity error Framing error flag FE 0 No error 1 Framing error Summing error flag SE 0 OE U PE U FE 1 OE U PE U FE 0 1 Not used returns 1 when read b0 UART control register UARTCON address 001B16 Character length selection bit CHAS 0 8 bits 1 7 bits Parity enable bit PARE 0 Parity cheching disabled 1 Parity checking enabled Parity selection bit PARS 0 Even parity 1 Odd parity Stop bit length selection bit STPS 0 1 stop bit 1 2 stop bits P45 TxD P channel output disable bit POFF 0 CMOS output in output mode 1 N channel open drain output in output mode Not used return 1 when read Fig 39 Structure of serial 1 01 rela
138. application example Conversion of Analog input voltage Outline The analog input voltage input from the sensor is converted into digital values Refer to the following examples for using an internal trigger or an external trigger 1 Read for analog signal using an internal trigger Figure 2 5 6 shows a connection diagram and Figure 2 5 7 shows a setting of related registers ADVREF Reference voltage P74 AN1 AVss Vss 3807 group Fig 2 5 6 Connection diagram Read for analog signal using an internal trigger Specifications The analog input voltage input from the sensor is converted into digital values Note The P74 AN1 pin is used as an analog input pin A D conversion start with an internal trigger by setting bit 4 of A D control register to 0 Note Example When a reference voltage 5 12 V is input to the ADVREF pin and a voltage 4 V to the P74 AN1 pin an input voltage is converted to a following value 256 5 12 V X 4 V 200 C816 A D control register Address 3416 a a Tom input pin selection bits Select the P74 AN1 pin AD conversion completion bit Conversion completed set to 0 at starting gt AD external trigger valid bit Invalid internal trigger A D conversion register Address 3516 Store a result of A D conversion Note Note Read out a result of A D conversion after bit 4 of the A D control register ADCON is set to 1 Port P7 direction
139. are used as control bus I O pins P35 P37 CMOS compatible input level CMOS 3 state output structure Port P32 can be switched CMOS or TTL input level P4o Xcour I O port P4 8 bit CMOS I O port with the same function as port PO e Sub clock generating I O P41 XCIN CMOS compatible input level pins connect a resonator P42 INTo CMOS 3 state output structures Interrupt input pins P43 INT1 Timer X Timer Y function pins INTO INT P44 RxD Serial 1 01 function pins P45 TxD P46 SCLK1 P47 SRDY1 P5o Tour 1 0 port P5 8 bit CMOS I O port with the same function as port PO Timer 2 output pin P51 ScMP2 CMOS compatible input level Interrupt input pin INT2 CMOS 3 state output structure Serial 1 02 function pin P52 INT3 Interrupt input pin P53 INT4 Real time port function pin INT4 P54 CNTRo Timer X Timer Y function pins P55 CNTR1 P56 DAt D A conversion output P57 DA2 pins 3807 GROUP USER S MANUAL Table 2 Pin description 2 HARDWARE PIN DESCRIPTION 3807 GROUP USER S MANUAL Pin Name Function Function except a port function P60 ANs I O port P6 3 bit CMOS I O port with the same function as port PO A D conversion output P62 AN7 CMOS compatible input level pins CMOS 3 state output structure P63 CMPin Input port P6 2 bit CMOS input port Analog comparator input pin AN8 e CMOS compatible input level A D conversion input pin P64 CM
140. area 128 byte o mE FF0016 FFDCte Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page 1 12 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION 000016 Port PO PO 002016 Timer X low order TXL 000116 Port PO direction register 002116 Timer X high order TXH 000216 Port P1 P1 002216 Timer Y low order TYL 000316 Port P1 direction register 002316 Timer Y high order TYH 000416 Port P2 P2 002416 Timer 1 T1 000516 Port P2 direction register 002516 Timer 2 T2 000616 Port P3 P3 002616 Timer 3 T3 000716 Port P3 direction register 002716 Timer X mode register TXM 000816 Port P4 P4 002816 Timer Y mode register TYM 000916 Port P4 direction register P4D 002916 Timer 123 mode register T123M 000A16 Port P5 P5 002A16 Real time port register RTP 000B16 Port P5 direction register P5D 002B 16 Real time port control register 0 RTPCONO 000C16 Port P6 P6 002C16 Real time port control register 1 RTPCON1 000D1e Port P6 direction register 002D16 Real time port control register 2 RTPCON2 000E16 Port P7 P7 002E16 Real time port control register 3 RTPCON3 000F16 Port P7 direction register 002Fie Timer A low order TAL 001016 Port P8 P8 003016 Timer A high order TAH 001116 Port P8 direction register 003116 Timer B low order TB
141. association with an alternate underflow of the corresponding timer latch 1 or 0 The real time port output pointer changes in sequence as a cycle of 5 repeated load operations as 4 3 2 1 0 4 3 2 1 0 4 3 2 1 The initial value at the generation of a start trigger can be specified by setting a value in the output pointer Figure 33 shows a timing chart of the 5 repeated load mode 4 One shot pulse generation mode The output operation for each value of real time port registers 2 to 0 is performed only once in association with trigger generation and an underflow of timer latch 1 or 0 After a trigger is generated the value of real time port register 1 is output from the real time output port and the output pointer value becomes 0002 At each underflow of the timer the each value of real time port registers 0 and 2 is output in ascending sequence then the operation is completed After completion of the operation the value of real time port register 2 is continuously output from the real time output port and the output pointer value continues to be 0012 until the next start trigger is generated In this condition the real time port function is in the wait status When this mode is selected the pointer value is not changed by writing a value into the output pointer If external trigger is specified as trigger selection when this mode is selected a rising and falling double edge trigger is generated regardless of the co
142. by specifying the Real time port data pointer R W pointer and reading data from this register Fig 2 4 2 Structure of Real time port register 2 62 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Real time port control register 0 b7 b6 b5 b4 b3 b2 b1 b0 ITITI Real time port control register 0 RTPCONO Address 2B16 Timer A Timer B count source 0 f Xin 2 selection bit 1 f Xin 16 Real time port port allocation 0 4 4 division selection bit Corresponding ports to the Timer A P82 P85 Corresponding ports to the Timer B P8s P87 P30 P31 2 6 division Corresponding ports to the Timer A P82 P87 Corresponding ports to the Timer B P3o P31 Timer A start trigger selection Internal trigger bit occurs by writing 1 to bit 3 External trigger occurs by inputting trigger to the INT4 pin Note 3 Timer A start trigger bit No operating by writing O Timer A starts counting by writing 1 when bit 2 is set to 0 Timer A count source stop bit Operating is set to 0 automatically at genera ting a start trigger Stop Timer B start trigger selection Internal trigger bit occurs by writing 1 to bit 6 External trigger occurs by inputting trigger to the INT4 pin Note 3 Timer B start trigger bit No operating by writing O Timer B starts counting by writing 1 when bit 5 is set to 0 Timer B count sour
143. c Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Preface This user s manual describes Mitsubishi s CMOS 8 bit microcomputers 3807 Group After reading this manual the user should have a through knowledge of the functions and features of the 3807 Group and should be able to fully utilize the product The manual starts with specifications and ends with application examples For details of software refer to the SERIES MELPS 740 lt SOFTWARE gt USER S MANUAL For details of development support tools refer to the DEVELOPMENT SUPPORT TOOLS FOR MICRO COMPUTERS data book BEFORE USING THIS USER S MANUAL This user s manual consists of the following three chapters Refer to the chapter appropriate to your conditions such as hardware design or software development Chapter 3 also includes necessary information for systems denelopment Be sure to refer to this chapter 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions based mainly on setting examples of related registers CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer electric characteristics a list of regis
144. ce stop bit Operating is set to 0 automatically at genera ting a start trigger Stop Note 1 In low speed mode f Xcin 2 is selected 2 In low speed mode f Xcin 16 is selected 3 The rising edge or falling edge of the external trigger is switched by the INT4 interrupt edge selection bit bit 4 of the interrupt edge selection register Address 3A16 However when the One shot pulse generation mode is selected a rising falling double edge trigger is generated in spite of the contents of the INT2 interrupt edge selection bit 4 At a read operation 0 is always read out Fig 2 4 3 Structure of Real time port control register 0 3807 GROUP USER S MANUAL 2 63 APPLICATION 2 4 Real time output port Real time port control register 1 b7 b6 b5 b4 b3 b2 b1 b0 ITITI Real time port control register 1 RTPCON1 Address 2C e Timer A operating mode 8 repeated load mode selection bits 6 repeated load mode 5 repeated load mode One shot pulse generation mode Real time port data pointer A A RW pointer switch bit Note 1 1 Output pointer Timer A interrupt mode Interrupts occur when a Real selection bit time port output pointer value becomes 0002 Interrupt request occurs in spite of a Real time port output pointer value a o a a Real time port data pointer A Real time port register 0 ola Real time port register 1 Real time port register 2 Real time port regi
145. ceive buffer full flag RBF Receive interrupt request RI P44 RxD O4 8 bit STdetector Ti 7 bit 7 Receive shift register l TPR PE FE SP detector 1 16 UART control register Clock control circuit Address 001B 6 Serial 1 01 synchronous clock P46 Scik1 O selection bit EN BRG count source selection bit Division ratio 1 n 1 f XiN Baud rate generator f XciN in low speed mode 1 4 i Address 001C 6 ST SP PA generator r Transmit shift register shift P4s TxD O e H 1 16 completion flag TSC Y Transmit interrupt source selection bit Transmit shift register Character length selection bit MEN PW interrupt request TI Transmit buffer register Transmit buffer empty flag TBE TAstress 001816 Serial l O1 status register Address 001916 ll Data bus Fig 37 Block diagram of UART serial l O1 Transmit or receive clock Write in signal to transmit buffer register Serial output TxD 1 start bit 7 or 8 data bit 1 or 0 parity bit Read out signal from 1 or 2 stop bit receive buffer register Serial input RxD Notes 1 Error flag detection occurs at the same time that the RBF flag becomes 1 at 1st
146. ch to be written first can be specified by the Timer A or B write pointer bit 7 of address 2C16 or 2D16 Reading is performed in the order of high order and low order At a read operation the value being counted is read out Fig 3 5 28 Structure of Timer A Low order Timer A High order Timer B Low order Timer B High order 3 50 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers D A control register b7 b6 b5 b4 b3 b2 b1 bO D A control register DACON Address 3316 Name Fama aves UW DA1 output enable bit 0 Output disable P56 1 Output enable DA output pi EM 1 DA2 output enable bit 0 Output disable P57 E 1 Output enable DAe output pin 1 Output enable DAs output pin 3 DA4 output enable bit 0 Output disable P8 ARES 1 Output enable DA output pin Nothing is allocated for these bits These are write disabled bits 0 O X When these bits are read out the values are 0 O0 o x 0 fo x 0 o x Fig 3 5 29 Structure of D A control register A D control register b7 b6 b5 b4 b3 b2 b1 bO A D control register ADCON Address 34 6 P73 Srpyv2 ADT ANo P74 ANi P75 AN2 P76 AN3 P77 AN4 P60 ANs P61 AN6 P62 AN7 P63 CMPiN ANs P64 CMPrer ANg P6s DAVrer AN10 P80 DA3 AN11 P81 DA4 AN12 4 AD conversion completion bit When A D trigger is invalid 1 0 Start conversion by writing to 0 1 Conversion completed When
147. count source is selected by the following bit Timer X count source selection bit bits 7 and 6 of TXM Timer Y count source selection bit bits 7 and 6 of TYM Interrupt When an underflow is generated the corresponding timer X interrupt request bit b4 or timer Y interrupt request bit b5 of IREQ1 HARDWARE FUNCTIONAL DESCRIPTION is set to 1 Explanation of operation After reset release timer X stop control bit b0 and timer Y stop control bit b1 of TXYCON are set to 1 and the timer stops During timer stop a timer value written to the timer X or timer Y is set by writing data to the corresponding timer latch and timer at the same time The timer operation is started by setting the bits O or 1 of TXYCON to 0 When the timer reaches 000016 an underflow occurs with the next count pulse Then the contents of the timer latch is reloaded into the timer and the timer continues down counting For changing a timer value during count operation a latch value must be changed by writing data only to the corresponding latch first Then the timer is reloaded with the new latch value at the next underflow GEvent counter mode Mode selection This mode can be selected by the following sequence 1 Set 000 to the timer X operating mode bit bits 2 to 0 of TXM or to the timer Y operating mode bit bits 2 to 0 of TYM 2 Select an input signal from the CNTRo pin in case of timer X set 11 to bits 7 and 6 of TXM or from th
148. d to Vcc or by setting the processor mode bits to 10 in soft ware with CNVss connected to Vss In microprocessor mode the internal ROM is no longer valid and external memory must be used HARDWARE FUNCTIONAL DESCRIPTION 000016 Mi 000816 000016 MMs 000816 SFR area SFR area 004016 004016 internal RAM reserved area internal ROM internal RAM reserved area FFFF16 Memory expansion mode FFFF16 Microprocessor mode The shaded area are external memory area YY YY 16 indicates the first address of internal ROM Fig 61 Memory maps in various processor modes bO CPU mode register CPUM address 003B16 Processor mode bits CM1 CMo b1 b0 0 0 Single chip mode O 1 Memory expansion mode 1 0 Microprocessor mode 1 1 Not available Stack page selection bit 0 0 page 1 1 page Fig 62 Structure of CPU mode register 3807 GROUP USER S MANUAL 1 57 HARDWARE FUNCTIONAL DESCRIPTION Bus control at memory expansion The 3807 group has a built in ONW function to facilitate access to external expanded memory and I O devices in memory expansion mode or microprocessor mode If an L level signal is input to port P32 ONW when the CPU is in a read or write state the corresponding read or write cycle is extended by one cycle of During this extended period the RD or WR signal remains at L This extension function is valid only for writing to and reading from addresses 000016 t
149. ddress 001716 is read the values of the 6 high order bits of the watchdog timer H STP instruction disable bit and watchdog timer H count source selection bit are read 1 Initial value of watchdog timer At reset or writing to the watchdog timer control register address 001716 each watchdog timer H and L is set to FF16 FF16 is set when watchdog timer XCIN O Iz control register is written to 10 2 Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register address 001716 permits selecting a watchdog timer H count source When this bit is set to 0 the count source becomes the underflow signal of watchdog timer L The detection time is set then to f XiN 2131 072 ms at 8 MHz frequency and f XciN 232 768 s at 32 kHz frequency When this bit is set to 1 the count source becomes the signal divided by 16 for f XiN or f XciN The detection time in this case is set to f Xin 512 us at 8 MHz frequency and f Xcin 128 ms at 32 KHz frequency This bit is cleared to 0 after resetting 3 Operation of STP instruction disable bit Bit 6 of the watchdog timer control register address 001716 permits disabling the STP instruction when the watchdog timer is in opera tion When this bit is 0 the STP instruction is enabled When this bit is 1 the STP instruction is disabled Once the STP instruction is executed an internal resetting takes place When this bit is se
150. de 1 Pulse output mode Pulse period measurement mode 1 Pulse width measurement mode Programmable waveform generation mode 1 Programmable one shot pad mode PWM mode Not available spere pomme pr 1 To only latch um fale H output It depends on the operating mode o fofo of the Timer Y refer to Table 2 2 1 Timer Y count source selection f Xin 2 bits f Xin 16 E o Jefe Input signal from CNTRt pi Fig 2 2 7 Structure of Timer Y mode register 3807 GROUP USER S MANUAL 2 9 APPLICATION 2 2 Timer Table 2 2 1 Function of CNTRo CNTR1 active edge switch bit Operating mode of Timer X Timer Y Timer mode Function of CNTRo CNTR1 edge switch bit bit 5 of each address 2716 and 2816 Generation of CNTRO ONTRt interrupt request Falling edge 9 No effect on timer count lt a Generation of CNTRo CNTR1 interrupt request Rising edge 1 No effect on timer count Event counter mode an Timer X Timer Y Count at rising edge 9 Generation of CNTRo CNTR1 interrupt request Falling edge wa Timer X Timer Y Count at falling edge Generation of CNTRo CNTR1 interrupt request Rising edge Pulse output mode g e Start of pulse output From H level e Generation of CNTRo CNTR1 interrupt request Falling edge TE Start of pulse output From L level e Generation of CNTRo CNTR1 interrupt request Risin
151. drive 2 3807 GROUP USER S MANUAL 3 19 APPENDIX 3 2 Standard characteristics Port P27 loL VOL characteristic N channel drive Pins with same characteristic P24 P27 in single chip mode loL mA 100 90 Vcc 5 5V Ta 90 C 80 Vcc 5 0V Ta 90 C 70 60 50 40 Vec 3 0V Ta 90 C 30 Fig 3 2 7 Standard characteristic example of CMOS output port at N channel drive 4 Port P27 loL VOL characteristic N channel drive Pins with same characteristic P24 P27 in single chip mode loL mA 100 Vec 5 5V Ta 25 C Vec 5 0V Ta 25 C 90 80 70 60 50 40 Vec 3 0V Ta 25 C 30 20 10 Fig 3 2 8 Standard characteristic example of CMOS output port at N channel drive 5 3 20 3807 GROUP USER S MANUAL APPENDIX 3 2 Standard characteristics 3 2 3 Input current standard characteristic examples Figure 3 2 9 and Figure 3 2 10 show input current standard characteristic examples Port P27 liL characteristic at pull up Pins with same characteristic PO P1 P2 liL mA 250 225 200 Vcc 5 5V Ta 90 C 175 150 125 Vcc 5 0V Ta 90 C Vec 3 0V Ta 90 C Fig 3 2 9 Standard characteristic example of input current at connecting pull up transistor 1 100 Port P27 liL characterist
152. e 1 Note 1 Note 3 Note 3 Note 3 384 384 512 1024 1024 Remarks PWM output Notes 1 Extended operating temperature version available 2 High speed version available 3 Extended operating temperature version and High speed version available ROM expansion Real time port output Analog comparator Watchdog timer Table of contents Table of contents CHAPTER 1 HARDWARE DESCRIPTION oo dto 1 2 FEATURES Locus 1 2 APPLICATION Loco 1 2 PIN CONFIGURATION Ae 1 2 FUNCTIONAL BLOCK 0 ta 1 3 PIN DESCRIPTION Li 1 4 PART NUMBERING Jeune uu MI ILI ILES Deed 1 6 GROUP 2st 1 7 FUNCTIONAL DESCRIPTION 1 eeeeeeeeieeeeeeeeneeeen nnne nennen nennen nnn nn sane nien nn ssim a nnn 1 8 Central Processing Unit CPU ssssseseeeneennenenennnnnenennnnnnmren nennen nnne 1 8 uuu eM dM nn ne DEM ME E 1 12 VO PONS PCT 1 14 We E E a tec 1 20 E E DU E T A E 1 23 1 41 A D Converter nie ire onte er Fe Pee pia redu ee aea Sc ge oin de ze doe Rh rix us 1 47 D A GOMVOIe rt EMEN 1 48 Analog GompatatorpBE titi lla tiles 1 49 EDS it ii 1 50 Glock output functlon Liens arit delent ts li oie ida td Eta ORE RS px 1 51 GHI MEE 1 52 Glock Generating Circuit iicet re penguin eher Ea e gen re E EX Y De xeu EE E a 1 54 o A E ML T T E 1 57 NOTES ON PROGRAMMING
153. e CNTRi pin in case of timer Y set 11 to bits 7 and 6 of TYM as a count source The valid edge for the count operation is selected by the CNTRo CNTRi active edge switch bit b5 of TXM or TYM if set to 0 counting starts with the rising edge or if set to 1 counting starts with the falling edge Interrupt The interrupt generation at underflow is the same as already explained for the timer mode Explanation of operation The operation is the same as already explained for the timer mode In this mode the double function port of CNTRo CNTR pin must be set to input Figure 19 shows the timing chart for the timer event counter mode 2 Pulse output mode Mode selection This mode can be selected by setting 001 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TYM Count source selection In high or middle speed mode f XiN 2 f XiN 16 or f XciN can be selected as the count source In low speed mode the count source is f XCIN Interrupt The interrupt generation at underflow is the same as already explained for the timer mode Explanation of operation Counting operation is the same as in timer mode Moreover the pulse which is inverted each time the timer underflows is output from CNTRo CNTR1 pin When the CNTRo CNTR1i active edge Switch bit b5 of TXM or TYM is O output starts with H level When set to 1 output starts with L level
154. e N has been set ODetects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases If the SWDT contents do not change after interrupt processing 3 32 3807 GROUP USER S MANUAL APPENDIX 3 4 Countermeasures against noise lt The interrupt processing routine gt Decrements the SWDT contents by 1 at each interrupt processing Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles at the fixed interrupt processing count ODetects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N 3807 GROUP USER S MANUAL 3 33 APPENDIX 3 5 List of registers 3 5 List of registers Port Pi b7 b6 b5 b4 b3 b2 b1 bO Port Pi Pi i 0 1 2 3 4 5 7 8 Address 0016 0216 0416 0616 0816 OA16 OE16 1016 B Name Function atroser WI pem ngage Lo fefe poet h ee ee e n input mode Gomes PP Read Value of pins TE mga mga aia mga mg Fig 3 5 1 Structure of Port Pi i 0 1 2 3 4 5 7 8 Port Pi direction register b7 b6 b5 b4 b3 b2 bi bO Port Pi direction register PiD i 0 1 2 3 4 5 7 8 Add
155. e Vcc line Connect an approximately 0 1 uF bypass capacitor across the Vss line and the Vcc line as follows G Connect a bypass capacitor across the Vss pin and the VCC pin at equal length G Connect a bypass capacitor across the Vss pin and the VCC pin with the shortest possible wiring Use lines with a larger diameter than other signal lines for Vss line and Vcc line CNVss VPP Vss 3807 group Make it the shortest possible Fig 3 4 3 Wiring for the VPP pin of the One Time PROM and the EPROM version Fig 3 4 4 Bypass capacitor across the Vss line and the Vcc line 3807 GROUP USER S MANUAL 3 4 3 Wiring to analog input pins Connect an approximately 100 Q to 1 kQ resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin Besides connect the capacitor to the Vss pin as close as possible Also connect the capacitor across the analog input pin and the Vss pin at equal length Reason Signals which is input in an analog input pin Such as an A D converter input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise in
156. e are four operating modes for real time ports which are 8 repeated load mode 6 repeated load mode 5 repeated load mode and one shot pulse generating mode Each operating mode can be set for timer A and timer B separately However switch modes dur ing timer count stop 1 8 repeated load mode The output operation for each value of the real time port registers 7 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0 The real time port output pointer changes in sequence as a cycle of 8 repeated load opera tions as 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 The initial value at the generation of a start trigger can be specified by setting a value in the output pointer Figure 31 shows a timing chart of 8 repeated load mode 2 6 repeated load mode The output operation for each value of real time port registers 5 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 to 0 The real time port output pointer changes in sequence as a cycle of 6 repeated load operations as 5 4 3 2 1 0 5 4 3 2 1 0 5 4 The initial value at the generation of a start trigger can be specified by setting a value in the output pointer Figure 32 shows a timing chart of the 6 repeated load mode 3 5 repeated load mode The output operation for each value of real time port registers 4 to 0 is performed repeatedly in
157. e bit L CNTRo interrupt enable bit CNTRt interrupt enable bit Serial 1 02 interrupt enable bit Timer 1 INT2 interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit ADT AD conversion interrupt enable bit Timer 3 INT4 interrupt enable bit Fig 16 Structure of Interrupt related registers Not used returns 0 when read Do not write 1 to this bit 0 Interrupt disabled 1 Interrupt enabled 1 22 3807 GROUP USER S MANUAL Timers The 3807 group has seven timers four 16 bit timers Timer X Timer Y Timer A and Timer B and three 8 bit timers Timer 1 Timer 2 and Timer 3 All timers are down counters When the timer reaches either 0016 or 000016 an underflow occurs with the next count pulse Then the contents of the timer latch is reloaded into the timer and the timer continues down counting When a timer underflows the interrupt request bit corresponding to that timer is set to 1 Read and write operation on 16 bit timer must be performed for both high and low order bytes When reading a 16 bit timer read from the high order byte first When writing to 16 bit timer write to the low order byte first The 16 bit timer cannot perform the correct operation when reading during write operation or when writing during read operation Timers A and B are real time output port timers For details refer to the section Real time output port Timer X Timer Y Timer X and
158. e cesee cence sees sees seeeeeaeeseeeeeeeeeeaeeesaeenaeeeaaes 1 48 Fig 47 Block diagram of D A converter enemies 1 48 Fig 48 Equivalent connection circuit of D A converter ssssem 1 48 Fig 49 Block diagram of Analog comparator susor aan nnns 1 49 Fig 50 Block diagram of Watchdog timer 1 50 Fig 51 Structure of Watchdog timer control register sss 1 50 Fig 52 Structure of Port P2P3 control register 1 51 Fig 53 Block diagram of Clock output function esssssssseeeeneenenenn 1 51 Fig 54 Reset CIFCUIL OXAIMPIS ssassn rette xui terra Se tee ge Pee ue e Eee Ge Ex Pe 1 52 FIG 55 Reset SOQUENCO ninia eer ORE ee idas 1 52 Fig 56 Internal Status at T8SOl erneut nere hene fa irae qn rd die e andas 1 53 Fig 57 Ceramic resonator circuit risiini ninnaa eaa anai e aai iaar aaa 1 54 Fig 58 External clock input GIrcult geo coc EE 1 54 Fig 59 System clock generating circuit block diagram Single chip mode 1 55 Fig 60 State transitions of system Clock nte tette e eee tene 1 56 Fig 61 Memory maps in various processor modes ssssseenee 1 57 Fig 62 Structure of CPU mode register entrent nnns 1 57 Figi 63 ONWTUNCHON TImiligsusccsecnaac der a Een netu Po dx c d Lu te gi dea 1 58 Fig 64 Programming and testing of One Time PROM version se 1 61 Fig 65 Timing chart after an interrupt OCCUIS occoocccnncccccnnnnnnnncnnnnnannnon
159. e operation Timer A operating mode selection bit in case of 6 repeated load mode 4 4 port division 3 ports out of P82 RTPO to P85 RTP3 are used Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts Timer count Source stop bit Timer A count value Port P82 RTPo Port P83 RTP1 Port P84 RTP2 Real time port output l i i i i i i pointer A L4 s a L3 IY 5 0 Data of real time port registers 5 to O Fig 32 6 repeated load mode operation 3807 GROUP USER S MANUAL 1 39 HARDWARE FUNCTIONAL DESCRIPTION Timer A operating mode selection bit in case of 5 repeated load mode 2 6 division 5 ports out of P82 RTPo to P87 RTPs are used Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts Timer count source stop bit Timer A count value Port P82 RT Port P83 RTP1 Port P84 RTP2 Port P85 RTP3 Port P86 RTP4 Real time port output pointer A 4 0 Data of real time port registers 4 to 0 Fig 33 5 repeated load mode operation Timer A operating mode selection bit in case of one shot pulse generating mode Synchronous to the start trigger the timer latch value is loaded into
160. ecial function register SFR area The special function register SFR area in the zero page contains control registers such as I O ports and timers RAM RAM is used for data storage and for stack area of subroutine calls and interrupts ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the reset is user area for storing programs Interrupt vector area The interrupt vector area contains reset and interrupt vectors RAM area byte XXXX16 Address ZZZZ16 F08016 E08016 D08016 08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 ROM capacity Address byte YYYY16 Fig 8 Memory map diagram Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area The internal RAM and the special function registers SFR are allocated to this area The zero page addressing mode can be used to specify memory and register addresses in the zero page area Access to this area with only 2 bytes is possible in the zero page addressing mode Special page The 256 bytes from addresses FF0016 to FFFF16 are called the spe cial page area The special page addressing mode can be used to specify memory addresses in the special page area Access to this area with only 2 bytes is possible in the special page addressing mode 000016 SFR area 010016 Zero page L XXXX16 Reserved area 084016 Not used YYYY 6 Reserved ROM
161. ect Y addressing mode dressing mode Relative addressing mode Memory of address indicated by contents of index Special page addressing mode register X Carry flag Memory of address indicated by contents of stack Zero flag pointer Interrupt disable flag M ADH ADL Contents of memory at address indicated by ADH and Decimal mode flag ADL in ADH is 8 high order bits and ADL is 8 low or Break flag der bits X modified arithmetic mode flag M 00 ADL Contents of address indicated by zero page ADL Overflow flag Ab 1 bit of accumulator Negative flag Mb 1 bit of memory OP Opcode n Number of cycles Number of bytes Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode lt gt l Accumulator bit relative addressing mode 3807 GROUP USER S MANUAL 3 69 APPENDIX 3 10 List of instruction codes 3 10 List of instruction codes 3 byte instruction 2 byte instruction 1 byte instruction 3 70 3807 GROUP USER S MANUAL APPENDIX 3 11 SFR memory map 3 11 SFR memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000Bt16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 A IN 002016 002116 002216 002316 0024
162. ed TSC 1 by setting transmit interrupt source selection bit TIC of the serial 1 01 control register 2 If data is written to the transmit buffer register when TSC 0 the transmit clock is generated continuously and serial data is output continuously from the TxD pin 3 The receive interrupt RI is set when the receive buffer full flag RBF becomes 1 Fig 36 Operation of clock synchronous serial 1 01 function 3807 GROUP USER S MANUAL 1 44 HARDWARE FUNCTIONAL DESCRIPTION 2 Asynchronous Serial I O UART Mode Asynchronous serial l O1 mode UART can be selected by clear ing the Serial I O1 mode selection bit b6 of the Serial 1 01 control register to 0 Eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical The transmit and receive shift registers each have a buffer the two buffers have the same address in memory Since the shift register cannot be written to or read from directly transmit data is written to the transmit buffer and receive data is read from the receive buffer The transmit buffer can also hold the next data to be transmitted and the receive buffer can hold a character while the next charac ter is being received Data bus AN Address 001816 T Serial 1 01 control register Address 001A16 OE Receive buffer register Character length selection bit Re
163. ed mode is eT 2 When CNVss pin is Cee to Vss the value is 0 When CNVss pin is connected to Vcc the value is 1 Fig 3 5 6 Structure of Port P2P3 control register 3 36 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Pull up control register b7 b6 b5 b4 b3 b2 b1 bO Pull up control register PULL Address 16 6 BB ne Funsion EA 1 Pull up Note 1 Pull up Note 2 P06 pull up control bit O No pull up 1 Pull up Note 3 P07 pull up control bit O No pull up 1 Pull up Note 4 P10 P13 pull up control bit O No pull up 1 Pull up Note 5 P14 P17 pull up control bit O No pull up 1 Pull up Note P20 P23 pull up control bit O No pull up 1 Pull up Note 7 P24 P27 pull up control bit O No pull up 1 Pull up Note Note Valid only in input mode Fig 3 5 7 Structure of Pull up control register Watchdog timer control register b7 b6 b5 b4 b3 b2 bi bO TTT Watchdog timer control register WDTCON Address 1716 Name 1 Function rest RW Watchdog timer H e After re set a watchdog timer Jol Xi operates by writting any values 1 O X in this register 1 olx After re set these bits are re set 1 jO X to 0000002 by writting any 1 o X values in this register 1 olx STP instruction disable bit 0 STP instruction enabled Note 1 STP instruction disabled 7 Watchdog timer H count 0 Watchdog timer L
164. ed only for input port Fig 2 1 4 Structure of Port P6 Port P6 direction register b7 b6 b5 b4 b3 b2 b1 bO Port P6 direction register P6D Address 0D e irecti E Port P6oinput mode 9 x ol Port P6o P66e direction registers Port P60 output mode e Port P61 input mode x Port P61 output mode T Port P62 input mode x 1 Port P62 output mode Ports P63 and P64 are input ports Accordingly these bits do not have a direction register 4 Nothing is allocated for these bits Port P6s direction register rs Port P6s input mode Port P65 output mode B Ie 6 Nothing i is allocated for these Bie These are write disabled bits When these bits are read out the values are 0 Fig 2 1 5 Structure of Port P6 direction register 2 4 3807 GROUP USER S MANUAL APPLICATION 2 1 1 0 port 2 1 3 Handling of unused pins Table 2 1 1 Handling of unused pins in single chip mode Name of Pins Ports PO P1 P2 P3 P4 P5 P6 P7 P8 Handling Set to the input mode and connect to Vcc or Vss through a resistor of 1 kO to 10 kQ Set to the output mode and open at L or H ADVREF Connect to Vss GND or open AVSS Connect to Vss GND CMPVcc Connect to Vss GND CMPoUT Open XOUT Open only when using external clock Table 2 1 2 Handling of unused pins in memory expansion mode and microprocessor mode Name of Pins Ports P30 P31 Handling Open P4 P5
165. edure Figure 2 2 16 shows a control procedure Initialization SEI 1123M Address 2916 X000XXXXe INTEDGE Address 3At6 bit7 lt 1 ICON1 Address 3E16 bit7 lt 1 T1 Address 2416 T3 Address 2616 250 1 50 1 CLI Main processing Processing for completion of setting clock Note 1 T1 Address 2416 250 1 T3 Address 2616 50 1 IREQ1 Address 3C16 bit7 lt 0 Timer 3 interrupt processing routine CLT Note 2 CLD Note 3 Push register to stack N Clock count up 1 40 second year Pop registers Fig 2 2 16 Control procedure Clock function X This bit is not used in this application Set it to 0 or 1 It s value can be disregarded All interrupts Disabled Select each count source of the Timer 1 and Timer 3 Timer 3 interrupt Enabled Set division ratio 1 to the Timer 1 and Timer 3 Interrupts Enabled When restarting the clock from zero second after completing to set the clock reset timers Set the Timer 3 interrupt request bit to 0 Note 1 This processing is performed only at completing to set the clock Note 2 When using the Index X mode flag T Note 3 When using the Decimal mode flag D Push the register used in the interrupt processing routine into the stack Check if the clock has already been set Count up the clock e Pop registers which is pushed to s
166. egister 2 b7 b6 b5 b4 b3 b2 b1 b0 E ER ed Interrupt control register 2 ICON2 Address 3F 16 i B Name Function avreser RW I CNTRo interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled CNTR interrupt enable bit 0 Interrupt disabled o fofo i 1 Interrupt enabled 2 Serial 1 02 interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled 3 Timer 1 INT2 interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled 4 Timer A interrupt enable bit 0 Interrupt disabled o fofo 1 Interrupt enabled 5 Timer B interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled ADT AD conversion interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled Fix this bit to 0 o fofo Fig 2 2 13 Structure of Interrupt control register 2 3807 GROUP USER S MANUAL 2 13 APPLICATION 2 2 Timer 2 2 3 Timer application examples 1 Basic functions and uses Function 1 Control of Event interval Timer X Timer Y Timer 1 Timer 2 Timer 3 The Timer count stop bit is set to 0 after setting a count value to a timer Then a timer interrupt request occurs after a certain period Use Generation of an output signal timing Generation of a waiting time Function 2 Control of Cyclic operation Timer X Timer Y Timer 1 Timer 2 Timer 3 The value of a timer latch is automatically written to a corresponding timer every time a timer underfl
167. eneration of CNTRO CNTRt interrupt request Rising edge No effect on timer count Event counter mode Timer X Timer Y Count at rising edge Generation of CNTRO ONTRt interrupt request Falling edge Qi Timer X Timer Y Count at falling edge e Generation of CNTRo ONTRt interrupt request Rising edge Pulse output mode g e Start of pulse output From H level Generation of CNTRo CNTR1 interrupt request Falling edge qi Start of pulse output From L level Generation of CNTRO CNTRt interrupt request Rising edge Pulse period measurement mode Timer X Timer Y Measurement of a period between a falling o edge and the next falling edge Generation of CNTRO ONTRt interrupt request Falling edge Timer X Timer Y Measurement of a period between a rising un i edge and the next rising edge Generation of CNTRO CNTRt interrupt request Rising edge Pulse width measurement mode Timer X Timer Y Measurement of H level width Generation of CNTRO ONTRt interrupt request Falling edge Timer X Timer Y Measurement of L level width Generation of CNTRO CNTRt interrupt request Rising edge Timer X Timer Y Start of a pulse output at L level and output of an one shot H level pulse Generation of CNTRO ONTRt interrupt request Falling edge Timer X Timer Y Start of a pulse output at H level and asl output of an one shot L level pulse
168. ents of the bit speci fied in the accumulator or memory is 0 Ab or Mb 1 Branches when the contents of the bit speci fied in the accumulator or memory is 1 Branches when the contents of carry flag is g Branches when the contents of carry flag is Q4 Branches when the contents of zero flag is 1 AND s the contents of accumulator and memory The results are not entered any where BMI Note 4 Branches when the contents of negative flag is oye BNE Note 4 Branches when the contents of zero flag is 0 BPL Note 4 Branches when the contents of negative flag is g BRA PC lt PC offset Jumps to address specified by adding offset to the program counter BRK 3 60 B lt 1 M S PCH S 8 1 M S PCL 8 1 M S PS e 8 1 PCL ADL PCH amp ADH Executes a software interrupt 3807 GROUP USER S MANUAL APPENDIX 3 9 Machine instructions Addressing mode Processor status register ABS ABS X ABS Y IND ZP IND IND X IND Y REL 3 JOP JOP OP JOP n JOP n JOP JOP JOP D 6D 3 7D 3 79 3 61 2 71 2 3807 GROUP USER S MANUAL 3 61 APPENDIX 3 9 Machine instructions Symbol Function
169. equency 3807 GROUP USER S MANUAL 1 59 HARDWARE NOTES ON USAGE NOTES ON USAGE Handling of Source Pins In order to avoid a latch up occurrence connect a capacitor suitable for high frequencies as bypass capacitor between power source pin Vcc pin and GND pin Vss pin and between power source pin Vcc pin and analog power source input pin AVss pin Besides connect the capacitor to as close as possible For bypass capacitor which should not be located too far from the pins to be connected a ce ramic capacitor of 0 01 uF 0 1 uF is recommended P34 clock output function In the case of using an I O port P34 as a clock output function note the following when an output clock frequency is changed during outputting a clock the port may feed a noise having a shorter pulse width than the standard at the switch timing Besides it also may happen at the timing for switching the low speed mode to the middle high speed mode Timer X and timer Y In the pulse period measurement mode or the pulse width measure ment mode for timers X and Y set the L or H pulse width of input signal from CNTRo CNTR1 pin to 2 cycles or more of a timer count source EPROM version One Time PROM version The CNVss pin is connected to the internal memory circuit block by a low ohmic resistance since it has the multiplexed function to be a programmable power source pin VPP pin as well To improve the noise reduction connect a track betwee
170. er P84 RTP2 O P84 latch Real time output Real time port output selection bit P84 P84 direction register When a start trigger bit is set to 1 ___________ A timer latch value is loaded into the timer internal trigger is selected P83 RTP1 O P83 latch When an external start trigger is generated A timer latch value is loaded into the timer external trigger is selected operation 0 1 stop P83 direction register x P82 RTPO P82 latch at reset Timer count source stop bit is set to 1 Real time output Real time port output selection bit P83 Real time output E Real time port output selection bit P82 State transition of timer count source stop bit P82 direction register Fig 28 Block diagram of Real time output port 1 36 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION b7 bO Real time port control register 0 RTPCONO address 002B16 Timer A B count source selection bit 0 f XIN 2 or f XCIN 2 1 f XIN 16 or f XCIN 16 Real time port port allocation selection bit 0 4 4 port division P82 to P85 correspond to timer A P86 P87 P30 P31 correspond to timer B 1 2 6 port division P82 to P87 correspond to timer A P30 P31 correspond to timer B Timer A start trigger selection bit 0 Internal trigger trigger is generated by setting bit 3 to 1 1 External trigger trigger start by external input INT4 note
171. er 2 Address 003F 6 to 0 Figure 3 3 1 shows the structure of the interrupt control register 2 3 3 2 Notes on the serial 1 01 1 Stop of data transmission Clear an interrupt enable bit to 0 interrupt disabled Switch the detection edge Clear an interrupt request bit to 0 no interrupt requ est issued Set the interrupt enable bit to 1 interrupt enabled Interrupt control register 2 Address 003F16 Interrupt enable bits Not used Fix this bit to 0 Fig 3 3 1 Structure of interrupt control register 2 As for the serial l O1 that can be used as either a clock synchronous or an asynchronous UART serial I O clear the transmit enable bit to 0 transmit disabled and clear the serial I O enable bit to 0 serial l O1 disabled in the following cases when stopping data transmission during transmitting data in the clock synchronous serial I O mode O when stopping data transmission during transmitting data in the UART mode when stopping only data transmission during transmitting and receiving data in the UART mode Reason Since transmission is not stopped and the transmission circuit is not initialized even if the serial l O1 enable bit is cleared to 0 serial l O1 disabled the internal transmission is running in this case since pins TxD RxD SCLK1 and SRDY1 function as I O ports the transmission data is not output When data is written to the transmit bu
172. errupt request 1 Interrupt request Timer B interrupt request bit 0 No interrupt request 1 Interrupt request ADT AD conversion interrupt 0 No interrupt request request bit 1 Interrupt request Nothing is allocated for this bit It is a write disabled bit When this bit is read out the value is 0 fr fee lt l Timer 1 INT2 interrupt request 0 No interrupt request i 1 Interrupt request x x x E 0 is set by software but not 1 Fig 2 2 11 Structure of Interrupt request register 2 2 12 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 uA control register 1 ICON1 Address ols e m interrupt enable bit 0 Interrupt disabled Interrupt enabled INT interrupt enable bit Interrupt disabled o Jolo i Interrupt enabled 2 Serial l O1 receive interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 3 Serial O1 transmit interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 4 Timer X interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer Y interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled Timer 2 INTs interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled 7 Timer 3 INT interrupt enable O Interrupt disabled bit 1 Interrupt enabled Fig 2 2 12 Structure of Interrupt control register 1 Interrupt control r
173. ers 9 reticere itae cer ee 2 74 2 4 18 Setting of related registers 4 nennen 2 75 2 4 19 Control Procedure 1 irn tn tiir interiit aT 2 76 2 4 20 Control procedute 2 uut ere ana cdd eth egere nag e oe E exp exce rx Du exe and 2 77 2 4 21 Control procedure 3J esince eene enne nennen trn 2 78 2 4 22 Control Procedure 4 eiie dera rrr eem eed eg tue e ra Bu eR LR ut dae 2 79 2 5 1 Memory map of A D conversion related registers ssseeseeees 2 80 2 5 2 Structure of A D control register nenne 2 81 2 5 3 Structure of A D conversion register 2 81 2 5 4 Structure of Interrupt request register 2 sssssssssseeee 2 82 2 5 5 Structure of Interrupt control register 2ni aE 2 82 2 5 6 Connection diagram Read for analog signal using an internal trigger 2 83 2 5 7 Setting of related registers Read for analog signal using an internal trigger 2 83 2 5 8 Control procedure Read for analog signal using an internal trigger 2 84 2 5 9 Connection diagram Read for analog signal using an external trigger 2 85 2 5 10 Setting of related registers Read for analog signal using an external trigger 2 85 2 5 11 Control procedure Read for analog signal using an external trigger 2 86 2 6 1 Example of Poweron reset circuit 2 87 2 0 2 HAM back up systetm x uec ues e oc Irae nein ei 2 87 2 7 1 Hot water supply system application example
174. ers at a receiving side Communication using UART 2 59 2 3 41 Control procedure at a transmitting side Communication using UARTY 2 60 2 3 42 Control procedure at a receiving side Communication using UART 2 61 2 4 1 Memory map of real time output port related registers s 2 62 2 4 2 Structure of Real time port register sessassriisiiiniinin iana 2 62 2 4 3 Structure of Real time port control register 0 2 63 2 4 4 Structure of Real time port control register 1 2 64 2 4 5 Structure of Real time port control register 2 2 65 2 4 6 Structure of Real time port control register 3 2 66 2 4 7 Structure of Timer A Low order Timer A High order Timer B Low order Timer B High order 2 66 2 4 8 Connection diagram veiessin aaia a nnne nennen ns 2 67 2 4 9 Operation patterns of motor ssssssssssesesesse entree enne nennen tense nnns 2 67 2 4 10 Example of timer table for acceleration and deceleration 2 68 2 4 11 Example of operation pattern table sssssssssseeeeeeenenen 2 69 2 4 12 Example of output data table nennen 2 69 2 4 13 Timing of Real time oUtpUut uui coii itte ii 2 70 2 4 14 Setting method and output timing oooccincccnnnnicnnnccccnnnnnnononnnnnnc nana nn anno canaria naar cnn 2 71 2 4 15 Setting of related registers ocsi nennen 2 72 2 4 16 Setting of related registers 2 nennen 2 73 2 4 17 Setting of related regist
175. ersion completed 1 Interrupt request at ADT input falling Fig 44 Structure of A D control register A D control register P73 SRDY2 ADT ANo O P74 AN1 O P75 AN2 O P76 AN3 O Comparator A D control circuit A D conversion register ADT A D interrupt request P77 AN4 O P60 AN5 O P61 AN6 O P62 AN7 O P63 CMPIN ANg O P64 CMPREF AN9 O P65 DAVREF AN10 O P80 DA3 AN11 O P81 DA4 AN120 Channel selector Fig 45 Block diagram of A D converter Resistor ladder a AVss ADVREF 3807 GROUP USER S MANUAL 1 47 HARDWARE FUNCTIONAL DESCRIPTION D A Converter The 3807 group has an on chip D A converter with 8 bit resolution and 4 channels DAI i 1 4 The D A converter is performed by setting the value in the D A conversion register The result of D A converter is output from DAi pin by setting the DAi output enable bits to 1 When using the D A converter the corresponding port direc tion register bit P65 DAVREF AN10 P56 DA1 P57 DA2 P80 DA3 AN11 P81 DA4 AN12 should be set to 0 input status The output analog voltage V is determined by the value n base 10 in the D A conversion register as follows V DAVREF x n 256 n 0 to 255 Where DAVREr is the reference voltage At reset the D A conversion registers are cleared to 0016 the DAi output enable bits are cleared to 0 and DAi pin is set to input high impedance The DA output is not buffered so connect an e
176. es 0 By repeating the above operations up to the lowest order bit of the A D conversion register an analog value converts into a digital value A D conversion completes at 50 clock cycles 12 5 us at f XIN 8 0 MHz after it is started and the result of the conversion is stored into the A D con version register Concurrently with the completion of A D conversion A D conversion interrupt request occurs so that the AD conversion interrupt request bit is set to 1 Relative formula for a reference voltage VREF of A D converter and Vref When n 0 When n 1 to 255 Vref 0 VREF Vref X n 0 re 256 n 0 5 n the value of A D converter decimal numeral Table 12 Change of A D conversion register during A D conversion Change of A D conversion register Value of comparison voltage Vref At start of conversion ololololofolo o 0 First s 1 Ta ae VREF VREF irst comparison 0 2 5i VREF VREF VREF Second comparison 1 1 0 010 olo _ 2 4 512 VREF VREF VREF VREF Third comparison 4 iE p Polio Toe To Ta o cR e ae ee a e o l After completion of eighth comparison A result of A D conversion 1 A result of the first comparison 3 A result of the third comparison 5 A result of the fifth comparison 7 A result of the seventh comparison 2 A result of the second comparison 4 A result of the f
177. ess 3C16 bitO O TB RB Address 1816 The first byte of a Write a transmission data transmission data The Transmit buffer empty flag is set to 0 by this writing Check to be transfered data from the Transmit buffer register to the Transmit shift register Transmit buffer empty flag The second byte of Write a transmission data a transmission data The Transmit buffer empty flag is set to 0 by this writing TB RB Address 181 Check to be transfered data from the Transmit buffer register to the Transmit shift register Transmit buffer empty flag Check a shift completion of the Transmit shift register Transmit shift register shift completion flag Fig 2 3 22 Control procedure at a transmitting side Communication using a clock synchronous serial 1 0 3807 GROUP USER S MANUAL 2 43 APPLICATION 2 3 Serial I O X This bit is not used in this application Set it to 0 or 1 It s value can be disregarded Initialization SIO1CON Address 1A16 1111X11X2 An interval of 2 ms is generated by a timer Y TB RB Address 1816 lt Dummy data SRDY1 output SRDY1 signal is output by writing data to the TB RB Using the SrDY1 the transmit enabled bit bit4 of the SIO1CON address 1A16 is set to 1 SIO1STS Address 1916 bit1 Check a completion of receiving Receive buffer full flag Receive the first byte dat
178. essed ADVREF Analog reference Reference voltage input pin for A D converter voltage AVss Analog power Analog power source input pin for A D and D A converter and an analog comparator source Connect to Vss CMPour Analog comparator e Output pin for an analog comparator output RESET Reset input Reset input pin for active L XIN Clock input Input and output signals for the internal clock generating circuit Connect a ceramic resonator or quartz crystal oscillator between the XiN and Xour pins to set the oscillation frequency XOUT Clock output If an external clock is used connect the clock source to the XIN pin and leave the Xour pin open The clock is used as the oscillating source of system clock POo P07 I O port PO 8 bit CMOS I O port P10 P17 1 0 port P1 I O direction register allows each pin to be individually programmed as either input or output P20 P27 1 0 port P2 At reset this port is set to input mode In modes other than single chip these pins are used as address data bus l O pins CMOS compatible input level CMOS 3 state output structure Port P2 can be switched CMOS or TTL input level P3o RTPe I O port P3 8 bit CMOS I O port Real time port function P31 RTP7 1 0 direction register allows each pin to be individually programmed as either input or output pins P34 CKour At reset this port is set to input mode Clock output function pin P32 P33 In modes other than single chip these pins
179. f the timer the count value at that point of time is read Read the high order side first and then the low order side The low order side value is read with the same timing as that for the high order side value and held at the timer read latch The data held state is released by reading the low order side At a reload operation of the timer A or the timer B Timer latch 1 is reloaded as the initial value after a trigger is generated After that the timer latch is reloaded in sequence as 0 1 0 1 The timer latch value cannot be read out Start trigger The operation of the real time port is started by a start trigger When a start trigger is generated the value of the real time port register specified by the output pointer the value of real time port register 1 in the one shot pulse generation mode is output from the real time output port The value of timer latch 1 is reloaded into the timer A or the timer B and the timer count A B source stop bit is released so that the timer count is started After that when the timer underflows data is transferred from the real port register to the real time output port As a Start trigger either internal trigger or external trigger can be selected by the timer A start trigger selection bit b2 or timer B start trigger selection bit 65 of real time port control register 0 1 34 3807 GROUP USER S MANUAL When the internal trigger is selected a start trigger is generated by an input
180. ffer register in this state the data is transferred to the transmit shift register and start to be shifted When the serial 1 01 enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and it may cause an operation failure to a microcomputer 2 Stop of data reception As for the serial l O1 that can be used as either a clock synchronous or an asynchronous UART serial I O clear the receive enable bit to 0 receive disabled or clear the serial I O enable bit to 0 serial I O disabled in the following case when stopping data reception during receiving data in the clock synchronous serial I O mode Clear the receive enable bit to 0 receive disabled in the following cases when stopping data reception during receiving data in the UART mode O when stopping only data reception during transmitting and receiving data in the UART mode 3 24 3807 GROUP USER S MANUAL APPENDIX 3 3 Notes on use 3 Stop of data transmission and reception in a clock synchronous serial I O mode As for the serial l O1 that can be used as either a clock synchronous or an asynchronous UART serial I O clear both the transmit enable bit and receive enable bit to 0 transmit and receive disabled at the same time in the following case when stopping data transmission and reception during transmitting and receiving data in the clock synchronous mode when data is transmitted
181. first measurement value happen to be invalid at a start timing of the Timer X count as shown a following figure Process it by software in accordance with the necessity Example 1 Be started the Timer X count at L level of the CNTRo input signal A level of the CNTRo input signal is judged by reading a content of the Port P54 register 2 Be invalid the first CNTRo interrupt after starting the Timer X count When the Timer X count is started at L level of the CNTRo input signal 000016 T2 T1 FFFF16 A value of T1 Valid A value of T2 Valid gt pp al CNTRo OP E x CNTRo interrupt CNTRo interrupt At starting counting the Timer X When the Timer X count is started at H level of the CNTRo input signal PERIG A value of T1 Invalid A value of T2 Vali o all i onmin Ed Ld CNTRo interrupt CNTRo interrupt At starting counting the Timer X Fig 2 2 28 Control procedure 2 Measurement of pulse width 2 28 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O 2 3 Serial I O 2 3 1 Memory map of serial I O 001816 Transmit Receive buffer register TB RB 001916 Serial 1 01 status register SIO1STS 001A16 Serial 1 01 control register SIO1CON 001C1e Baud rate generator BRG 001B16 UART control register UARTCON 001D16 Serial 1 02 control register 1 SIO2CON1 i 001E16 Serial 1 O2 control register 2 SIO2CON2 001F16
182. fofo 1 To only latch 3 Timer 2 count source selection H Me signal from Timer 1 bit f XiN 16 Note 1 4 Timer 3 count source selection TOT signal from Timer 1 bit f XiN 16 Note 1 Timer 1 count source selection s Pa f Xin 16 o fofo bit 0 1 f Xm 2 1 0 f Xcin 1 1 Not available Nothing is allocated for this bit It is a write disabled bit When this bit is read out the value is 0 Note 1 In low speed mode f Xcin 16 is selected 2 In low speed mode f Xcin 2 is selected Fig 2 2 8 Structure of Timer 123 mode register Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 bO Interrupt edge selection register INTEDGE Address 3A e B Nam Funon ww RW INTo interrupt edge selection Falling edge active bit Rising edge active INT interrupt edge selection a Falling edge active o fofo bit Rising edge active 2 INT2 interrupt edge selection TE Falling edge active bit 1 Rising edge active 3 INTs interrupt edge selection gt Falling edge active bit Rising edge active 4 INT4 interrupt edge selection o Falling edge active bit Rising edge active 5 Timer 1 INT2 interrupt sources T INT2 interrupt bit 1 Timer 1 interrupt Timer 2 INTs interrupt sources 0 INTs interrupt bit 1 Timer 2 interrupt 7 Timer S INT interrupt sources 0 INT4 interrupt bit 1 Timer 3 interrupt Fig 2 2 9 Structure of Interrupt edge selection register
183. for low byte by the accumulator Stores the quotient in the accumulator and the 1 s complement of the remainder on the stack When T 0 A lt A M When T 1 M X M X VM Exclusive ORs the contents of accumulator and memory The results are stored in the ac cumulator Exclusive ORs the contents of the memory specified by the addressing mode and the contents of the memory at the address indi cated by index register X The results are stored into the memory at the address indi cated by index register X AS A 1or MeM 1 Increments the contents of accumulator or memory by 1 XX 1 Increments the contents of index register X by 1 Y Y 1 3 62 Increments the contents of index register Y by C8 3807 GROUP USER S MANUAL Addressing mode APPENDIX 3 9 Machine instructions Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL 3 OP n JOP n JOP n JOP n JOP n JOP n JOP 50 70 3807 GROUP USER S MANUAL 3 63 APPENDIX 3 9 Machine instructions Function Details Addressing mode A BIT A ZP BIT ZP n JOP n OP OP n If addressing mode is ABS PCL ADL PCH lt ADH
184. g edge Pulse period measurement mode Timer X Timer Y Measurement of a period between a falling Q edge and the next falling edge Generation of CNTRO ONTRt interrupt request Falling edge Timer X Timer Y Measurement of a period between a rising aa edge and the next rising edge Generation of CNTRo CNTR1 interrupt request Rising edge Pulse width measurement mode uy Timer X Timer Y Measurement of H level width Generation of CNTRO ONTRt interrupt request Falling edge aa Timer X Timer Y Measurement of L level width Generation of CNTRo CNTR1 interrupt request Rising edge Programmable one shot generation Timer X Timer Y Start of a pulse output at L level and mode o output of an one shot H level pulse 2 10 Generation of CNTRO ONTRt interrupt request Falling edge Timer X Timer Y Start of a pulse output at H level and output of an one shot L level pulse Generation of CNTRo CNTR1 interrupt request Rising edge 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 mL Timer 123 mode register T123M Address 2916 B Name Funcion faesafR W Tour output active edge switch 0 Start at outputting H signal bit 1 Start at outputting L signal Tout output control bit 0 Disabled Tour output 1 Enabled Tour output 2 Timer 2 write control bit O To a latch and a timer at the same time o
185. g the Real time port data pointer B when this bit is switched When this bit is read 1 is always read out 2 When these bits are read an output pointer is read out Fig 2 4 5 Structure of Real time port control register 2 3807 GROUP USER S MANUAL 2 65 APPLICATION 2 4 Real time output port Real time port control register 3 b7 b6 b5 b4 b3 b2 bi b0 Real time port control register 3 RTPCONS Address 2E16 B Name Function Atrese R W Real time port output selection a I O port bit P82 Real time output port Real time port output selection bit P83 Real time port output selection bit P84 Real time port output selection bit P85 B Real time port output selection bit P86 Real time port output selection 5 bit P87 Real time port output selection bit P30 Real time port output selection bit P31 Fig 2 4 6 Structure of Real time port control register 3 Timer A Low order Timer A High order Timer B Low order Timer B High order b7 b6 b5 b4 b3 b2 b1 bO Timer A Low order TAL Timer A High order TAH Address 2F16 3016 Timer B Low order TBL Timer B dio TBH Address 3116 3216 Sets the real time output cycle 1 e Writing is performed in the order of low order and high order There are 2 reload latches When the high order side is written the next latch is automatically specified The latch to be written first can be specified by the Time
186. have a direction register 4 Nothing is allocated for these bits Port P65 direction register A Port P65 input mode Port P6s output mode els T Port P62 input mode x 1 Port P62 output mode 6 Nothing i is allocated for these BE These are write disabled bits When these bits are read out the values are 0 Fig 3 5 4 Structure of Port P6 direction register 3807 GROUP USER S MANUAL 3 35 APPENDIX 3 5 List of registers Timer XY control register b7 b6 b5 b4 b3 b2 b1 bO EM X aL control register TXYCON Address re Name Function ars r w m X stop control bit E Start counting SUB eounbng a Tat E L1 Stop counting 0 ol x 0 o x 0 olx 0 olx 0 folx o0 Jo x Fig 3 5 5 Structure of Timer XY control reigster Port P2P3 control register b7 b6 b5 b4 b3 b2 b1 bO Port P2P32 control register P2P3C Address 1516 Name B CI M clock output control bit 0 I O port P34 MAS 1 Clock output CKour output pin ie Output clock frequency selection bits F XIN L fixed output L fixed output XIN f XCIN f Xin 2 f XCIN f XiN 4 f XCIiN 4 f Xin 16 f Xcin 16 Note 1 4 Nothing is allocated for these bits These are write disabled bits ma lla these bits are read out the values are 0 9 fo x O0 o x E P3 input level selection bit x CMOS level Note 2 TTL level Note 1 In low spe
187. i i 0 1 2 3 4 5 7 8 Address 0016 0216 0416 0616 0816 OA16 OE16 1016 B Name Function arreser R w Write e n input mode Read Value of pins gem Fig 2 1 2 Structure of Port Pi i 0 1 2 3 4 5 7 8 Port Pi direction register b7 b6 b5 b4 b3 b2 b1 bO Port Pi direction register PiD i 0 1 2 3 4 5 7 8 Address 0116 0316 0516 0716 0916 OBis OF 16 1116 0 Port Pio input mode 1 Port Pio output mode el Port Pi input mode Port Pit output mode s Port Piz input mode x Port Piz output mode E Port Pis input mode x 1 Port Pis output mode O Port Pia input mode x 1 Port Pia output mode 0 Port Pis input mode x 1 Port Pis output mode 0 Port Pieinput mode x 1 Port Pie output mode 0 Port Piz input mode x 1 Port Piz output mode Fig 2 1 3 Structure of Port Pi direction register i 0 1 2 3 4 5 7 8 3807 GROUP USER S MANUAL 2 3 APPLICATION 2 1 1 0 port Port P6 b7 b6 b5 b4 b3 b2 bi bO Port P6 P6 Address 0C16 B Name Function At reset o Port P6o e In output mode Write Port P61 Read rortatel e n input mode Port P62 Write Port latch Read Value of pins Port P6 Note Port P64 Note Port P6s 6 Nothing i is allocated for these bits These are write disabled bits When these bits are read out the values are 0 Note These bits are us
188. ial 1 02 register 8 La P51 latch P51 Sowez INTa AS gt AE nym Serial 1 02 I O comparison signal control bit Note Either high speed middle speed or low speed mode is selected by bits 6 and 7 of CPU mode register Fig 41 Block diagram of Serial 1 02 Transfer clock Note 1 Write in signal to serial 1 02 register Serial 1 02 output Sout2 Serial 1 02 input Sinz Receive enable signal SRDY2 y Serial 1 02 interrupt request bit set Notes 1 When the internal clock is selected as a transfer clock the f XIN clock division f XCIN in low speed mode can be selected by setting bits O to 2 of serial 1 02 control register 1 2 When the internal clock is selected as a transfer clock the ScouT2 pin has high impedance after transfer completion Fig 42 Timing chart of Serial 1 02 3807 GROUP USER S MANUAL 1 45 HARDWARE FUNCTIONAL DESCRIPTION Judgement of I O data comparison Fig 43 Scmp2 output operation 1 46 3807 GROUP USER S MANUAL A D Converter A D Conversion Register AD address 003516 The A D conversion register is a read only register that contains the result of an A D conversion When reading this register during an A D conversion the previous conversion result is read A D Control Register ADCON The A D cont
189. ic at pull up Pins with same characteristic PO P1 P2 liL mA 250 225 Vcc 5 5V Ta 25 C 200 175 150 Vcc 5 0V Ta 25 C 125 100 Vec 3 0V Ta 25 C Fig 3 2 10 Standard characteristic example of input current at connecting pull up transistor 2 3807 GROUP USER S MANUAL 3 21 APPENDIX 3 2 Standard characteristics 3 2 4 A D conversion standard characteristics Figure 3 2 11 shows the A D conversion standard characteristics The lower side line on the graph indicates the absolute precision error It represents the deviation from the ideal value For example the conversion of output code from O to 1 occurs ideally at the point of ANo 10 mV but the measured value is 0 mV Accordingly the measured point of conversion is represented as 10 0 10 mV The upper side line on the graph indicates the width of input voltages equivalent to output codes For example the measured width of the input voltage for output code 13 is 22 mV so the differential nonlinear error is represented as 22 20 2 mV 0 1 LSB M38073E4FS A D CONVERTER STEP WIDTH MEASUREMENT Voc 5 12 V VREF 5 12 V Xin 8 0 MHz Temp 25 deg ANALOG INPUT P60 AN5 i o mo E z 3 ERROR mv Measured when a power source voltage is stable in the single chip mode and the high speed mode Fig 3 2 11 A D conversion standard character
190. ic example of CMOS output port at N channel drive 3 4 Fig 3 2 8 Standard characteristic example of CMOS output port at N channel drive 3 20 Fig 3 2 9 Standard characteristic example of input current at connecting pull up transistor 1 3 21 Fig 3 2 10 Standard characteristic example of input current at connecting pull up transistor 2 3 21 Fig 3 2 11 A D conversion standard characteristics sssssssssssseene 3 22 Fig 3 2 12 D A conversion standard characteristics ssssseee 3 23 Fig 3 3 1 Structure of interrupt control register 2 ssssssssssseeeeeeee 3 24 Fig 3 4 1 Wiring for the RESET IUe tr tree parete Exe Papeete n centes acu lute rope na e 3 29 Fig 3 4 2 Wiring for clock I O pins ssssssssssssseseneeeenenen enne nnne nnns nnns 3 30 Fig 3 4 3 Wiring for the VPP pin of the One Time PROM and the EPROM version 3 30 Fig 3 4 4 Bypass capacitor across the Vss line and the VCC line seeeesssssss 3 30 Fig 3 4 5 Analog signal line and a resistor and a capacitor ssseeeeees 3 31 Fig 3 4 6 Wiring for a large current signal line sssssssneen e 3 31 Fig 3 4 7 Wiring to a signal line where potential levels change frequently 3 31 Fig 3 4 9 Setup for VO Ports uie tae ed recedat dud dd ead cse tte sea ER Rae 3 32 Fig 3 4 9 Watchdog timer by software nennen nennen
191. ied 2 52 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O The communication is performed according to the timing shown below In the slave unit when a synchronizing clock is not input within a certain time heading adjustive time the next clock input is processed as the beginning heading of a block When a clock is input again after one block 8 byte is received the clock is ignored Figure 2 3 34 shows a setting of related registers Do I Byte cycl l D1 Da D7 EM Do e Block transfer period interval between blocks Block transfer cycle q _ _ _ _ _ _ _ __ A A q lt I l S de MET I T Heading adjustive time l o Master side Read a receive data l Write a transmit data S lave side Read a receive data Processing for heading adjustment Write a transmit data Fig 2 3 33 Timing chart Cyclic transmission or reception of block data between microcomputers Master unit Slave unit Serial l O1 control register Address 1A 6 Serial 1 01 control register Address 1A16 bO bO b7 b7 sio1con a a fa a r fofofo siorcon t rit ofl b BRG count source f XIN b Not be effected by Synchronous external clock clock BRG 4 Synchronous clock External clock Not use the Srov output Not use the Sabv output Transmit interrupt source Not use the serial O1 transmit interrupt Transmit shift operating completion Transmit enabled gt Receive e
192. imum ratings Table 3 1 1 Absolute maximum ratings Symbol Parameter Conditions Ratings 0 3 to 7 0 0 3 to 7 0 0 3 to Vcc 0 3 Vcc Power source voltage CMPVcc VI Input voltage Analog comparator power source voltage P00 PO7 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P65 P70 P77 P80 P87 ADVREF RESET XIN CNVss ROM version CNVss PROM version CMPIN CMPREF Differential input voltage CMPIN CMPREF Output voltage POo P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P62 P65 P70 P77 P80 P87 XOUT CMPour Input voltage Input voltage Input voltage In phase input voltage 0 3 to Vcc 0 3 0 3 to 7 0 3 to 13 0 3 to CMPVcc 0 3 CMPVcc 0 3 to Vcc 0 3 All voltages are based on Vss Output transistors are cut off 0 3 to CMPVcc 0 3 Output voltage Power dissipation Ta 25 C 500 Operating temperature 3 2 Storage temperature 3807 GROUP USER S MANUAL 20 to 85 40 to 125 APPENDIX 3 1 Electrical characteristics 3 1 2 Recommended operating conditions Table 3 1 2 Recommended operating conditions 1 Vcc 2 7 to 5 5 V Ta 20 to 85 C unless otherwise noted Limits Typ Vcc Power source voltage f XIN lt 4 1MHz 5 0 f XIN 8MHz 5 0 Vss Power source voltage 0 Symbol Parameter ADVREF A D comparato
193. in high impedance after completing to transfer data using the serial 1 02 as an internal clock Fig 2 3 25 Timing chart Output of serial data 3807 GROUP USER S MANUAL 2 45 APPLICATION 2 3 Serial I O Figure 2 3 26 shows a setting of serial l O1 related registers and Figure 2 3 27 shows a setting of serial l O1 transmission data Serial 1 01 control register Address 1A16 bO b7 siorcon 1 Jo o 0 fo Ls BRG count source selection bit f Xin Serial l O1 synchronous clock selection bit BRG 4 SRDY1 output enable bit Not use the Srov signal output function gt Transmit interrupt source selection bit Transmit shift operating completion Transmit enable bit Transmit enabled gt Receive enable bit Receive disabled gt Serial l O1 mode selection bit Clock synchronous serial I O gt Serial l O1 enable bit Serial l O1 enabled UART control register Address 1B16 7 bO b uartoon Jol ps P45 TxD P channel output disable bit CMOS output Baud rate generator Address 1C16 b7 bO Interrupt control register 1 Address 3E16 b7 b gt Serial l O1 transmit interrupt enable bit Interrupt disabled Interrupt request register 1 Address 3C16 b7 bO poy Serial 1 01 transmit interrupt request bit Using this bit check the completion of transmitting 1 byte base data 1 Transmit shift completion Port P5 Address 0A16 b7 b ERNMEEEB m
194. in the output unit is requested Output unit TXYCON Address 1416 bito 1 TXYCON Address 1416 bit 0 During stopping outputting a piezoelectric buzzer During outputting a piezoelectric buzzer Fig 2 2 20 Control procedure Piezoelectric buzzer output 2 20 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer 4 Timer application example 3 Measurement of frequency Outline The following two values are compared for judging if the frequency is within a certain range A value counted a pulse which is input to P55 CNTRi1 pin by a timer A referance value Specifications The pulse is input to the P55 CNTR1 pin and counted by the Timer Y A count value is read out at the interval of about 2 ms Timer X interrupt interval When the count value is 28 to 40 it is regarded the input pulse as a valid Because the timer is a down counter the count value is compared with 227 to 215 227 to 215 255 initialized value of counter 28 to 40 the number of valid value Figure 2 2 21 shows a method for judging if input pulse exists and Figure 2 2 22 and Figure 2 2 23 show a setting of related registers i i I 1 I 1 gt Input pulse en AU m on D D 1 1 ie 50 us or less 20 kHz or more A 71 4 us or more 71 4 us 50 us B 14 kHz or less 14 kHz Invalid gt lt Invalid 2ms 2ms 714 us 28 counts 50 us 40 counts Fig 2 2 21
195. ion mode and microprocessor mode L total peak output current Note P40 P47 P50 P57 P60 P62 P65 CMPour P70 P77 H total average output current Note P00 P07 P10 P17 P20 P27 P30 P37 P80 P87 H total average output current Note P40 P47 P50 P57 P60 P62 P65 CMPour P70 P77 L total average output current Note P00 PO07 P10 P17 P20 P23 P30 P37 P80 P87 L total average output current Note in single chip mode P24 P27 in memory expansion mode and microprocessor mode L total average output current Note P40 P47 P50 P57 P60 P62 P65 CMPour P70 P77 Note The total output current is the sum of all the currents flowing through all the applicable ports The total average current is an average value measured over 100ms The total peak current is the peak value of all the currents 3807 GROUP USER S MANUAL 3 3 APPENDIX 3 1 Electrical characteristics Table 3 1 4 Recommended operating conditions 3 lOH peak Vcc 2 7 to 5 5 V Ta 20 to 85 C unless otherwise noted Parameter H peak output current Note 1 P00 PO7 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P62 P65 CMPouT P70 P77 P80 P87 Limits Typ lOL peak L peak output current Note 1 P00 PO7 P10 P17 P20 P23 P30 P37 P40 P47 P50 P57 P60 P62 P65 CMPouT P70 P77 P80 P87
196. ion mode and microprocessor mode 3 10 Table 3 31 Programming adapter iare iced erret react etu d reas 3 28 Table 3 3 2 Setting of programming adapter switch sssssseee 3 28 Table 3 3 3 Setting of PROM programmer address sse 3 28 Table 3 5 1 Function of CNTRo CNTR1 edge switch bit ssssse 3 45 3807 GROUP USER S MANUAL i CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATIONS PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT HARDWARE DESCRIPTION FEATURES APPLICATIONS PIN CONFIGURATION DESCRIPTION The 3807 group is a 8 bit microcomputer based on the 740 family core technology The 3807 group has two serial I Os an A D converter a D A converter a real time output port function a watchdog timer and an analog comparator which are available for a system controller which controls motors of office equipment and household appliances The various microcomputers in the 3807 group include variations of internal memory size and packaging For details refer to the section on part numbering For details on availability of microcomputers in the 3807 group refer to the section on group expansion FEATURES e Basic machine language instructions
197. is detected H is output and at underflow L is output from CNTRo CNTR a pin For a L one shot pulse set bit 5 of TXM TYM to 1 During timer operation stop The output level of CNTRo CNTRt pin is initialized to H at mode selection Set the one shot pulse width to TXH TXL TYH TYL A trigger generation during timer stop input signal to INTo INT1 pin is invalid During timer operation enabled When a trigger generation is detected L is output and at underflow H is output from CNTRo CNTRa pin WiPrecautions Set the double function port of CNTRo CNTRt pin to output and the double function port of INTo INT1 pin to input in this mode This mode is unused in low speed mode 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION During one shot generation permission or one shot generation the output level from CNTRo CNTRt pin changes if the value of the CNTRo CNTR1 active edge switch bit is inverted Figure 24 shows the timing chart of the programmable one shot generating mode 7 PWM mode Mode selection This mode can be selected by setting 110 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TYM Count source selection In high or middle speed mode f XiN 2 or f XiN 16 can be selected as the count source Interrupt With a rising edge of CNTRo CNTRt output the timer X interrupt request bit b4 and timer Y interrupt request bi
198. ister from the memory at the address indicated by the stack pointer Shifts the contents of the memory or accumu lator to the left by one bit The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit Shifts the contents of the memory or accumu lator to the right by one bit The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit Rotates the contents of memory to the right by 4 bits S 8 41 PS M S S 8 41 PCL M S S lt S 1 PCH lt M S Returns from an interrupt routine to the main routine S lt S 1 PCL M S St S91 PCH M S Returns from a subroutine to the main routine SBC Note 1 Note 5 When T 0 ACcCA M C When T 1 E M X E MX M C Subtracts the contents of memory and complement of carry flag from the contents of accumulator The results are stored into the accumulator Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the ad dress indicated by index register X The results are stored into the memory of the ad dress indicated by index register X Ab or Mb 1 Sets the specified bit in the accumulator or memory to 1 Sets the contents of the carry flag to 1 Sets the contents of the decimal mode flag to I Sets the c
199. ister 2 b7 b6 b5 b4 b3 b2 b1 bO oJI EI control reigster 2 ICON2 Address uc EMEN Cocos Gp MN ea ELI interrupt enable bit 0 Interrupt disabled Interrupt enabled CNTR interrupt enable bit Interrupt disabled i Interrupt enabled 2 Serial 1 02 interrupt enable bit O Interrupt disabled 1 Interrupt enabled 3 Timer 1 INT2 interrupt enable 0 Interrupt disabled Eee bit 1 Interrupt enabled 4 Timer A interrupt enable bit O Interrupt disabled 1 Interrupt enabled 5 Timer B interrupt enable bit O Interrupt disabled 1 Interrupt enabled ADT AD conversion interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 7 Fix this bit to 0 9 fofo Fig 2 3 14 Structure of Interrupt control register 2 2 36 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O 2 3 3 Serial I O connection examples 1 Control of peripheral IC equipped with CS pin There are connection examples using a clock synchronous serial I O mode Figure 2 3 15 shows connection examples of a peripheral IC equipped with the CS pin 1 Only transmission 2 Transmission and reception using the RxD pin as an I O port 3807 group Peripheral IC 3807 group Peripheral IC OSD controller etc E PROM etc 3 Transmission and reception Pins RxD and TxD are connected 4 Connecting ICs Pins IN and OUT in peripheral IC are connected 3807 group Peripheral IC E PROM etc 3807
200. istics 3 22 3807 GROUP USER S MANUAL APPENDIX 3 2 Standard characteristics 3 2 5 D A conversion standard characteristics Figure 3 2 12 shows the D A conversion standard characteristics The lower side line on the graph indi cates the absolute precision error In this case it represents the difference between the ideal analog output value for an input code and the measured value The upper side line on the graph indicates the change width of output analog value to a one bit change of input code M38073E4FS D A CONVERTER STEP WIDTH MEASUREMENT Voc 5 12 V VREF 5 12 V Xin 8 0 MHz Temp 25 deg ANALOG OUTPUT P5e DA1 ERROR mv E soo uii due ind a SEEIGuE purum ccc MIDI QUE US VUES ee UVP rn YE Ae TN ne AAA APA 204118 ERROR mv Measured when a power source voltage is stable in the single chip mode and the high speed mode Fig 3 2 12 D A conversion standard characteristics 3807 GROUP USER S MANUAL 3 23 APPENDIX 3 3 Notes on use 3 3 Notes on use 3 3 1 Notes on interrupts 1 Sequence for switching an external interrupt detection edge When the external interrupt detection edge must be switched make sure the following sequence Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals This may cause an unnecessary interrupt 2 Bit 7 of the interrupt control register 2 Fix the bit 7 of the interrupt control regist
201. it board can be as an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less the possibility of noise insertion into a microcomputer 1 Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible Especially connect a capacitor across the RESET pin and the Vss pin with the shortest possible wiring within 20mm Reason The reset works to initialize a microcomputer The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise having a shorter pulse width than the standard is input to the RESET pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway Reset A f Reset circuit E circuit N G 3807 group Fig 3 4 1 Wiring for the RESET pin 2 Wiring for clock input output pins Make the length of wiring which is connected to clock I O pins as short as possible eMake the length of wiring within 20mm across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible G Separate the Vss pattern only for oscillation from other Vss patterns Reason A microcomputer s operation synchronizes with a clock generated by the oscillator circuit If noise enters clock I O pins clock waveforms may be deformed This may cause a malfunction or program
202. it interrupt Disabled OA 6 bit3 1 Set the CS signal output port 0B16 lt XXXX1XXX2 H level output Set the CS signal output level to L P5 Address 0A 6 bit3 1 e Set the Serial 1 01 transmit interrupt request bit to 0 Write a transmission data start to transmit 1 byte data e Check the completion of transmitting 1 byte data Use any of RAM area as a counter for counting the number of transmitted bytes Check that transmission of the target number of bytes has been completed Return the CS signal output level to H when transmission of the target number of bytes is completed Fig 2 3 28 Control procedure of serial l O1 Output of serial data 2 48 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Figure 2 3 29 shows a setting of serial 1 02 related registers and Figure 2 3 30 shows a setting of serial 1 02 transmission data Serial l O2 control register 1 Address 1D16 bO 1 b7 siozcon1 o 1 o o 1 0 1 1 E Internal synchronous clock selection bits f Xin 64 gt Serial 1 02 port selection bit Use the Serial 1 02 gt SRDY2 output enable bit Not use the SRDy2 signal output function Transfer direction selection bit LSB first Serial 1 02 synchronous clock selection bit Internal clock P71 SouT2 P72 ScLk2 P channel output disable bit CMOS output Serial 1 02 control register 2 Address 1E16 b7 bO sio
203. k H pulse width 4 clock L pulse width AD15 ADs delay time AD7 ADo delay time AD15 ADg valid time AD7 ADo valid time SYNC delay time SYNC valid time Data bus delay time Data bus valid time 10 tw RD tw WR RD pulse width WR pulse width tc XIN 10 RD pulse width WR pulse width 3tc XIN 10 When one wait is valid td AH RD td AH WR AD15 ADs delay time tc XIN 35 td AL RD td AL WR AD7 ADo delay time tc XIN 40 tv RD AH tv WR AH AD15 ADg valid time tv RD AL tv WR AL AD7 ADo valid time Data bus delay time Data bus valid time RESETOUT output delay time tv RESETouT RESETOUT output valid time Note Note The RESETovr output goes H in sync with the fall of the o clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes H 3 10 3807 GROUP USER S MANUAL APPENDIX 3 1 Electrical characteristics Measurement output pin Measurement output pin Jr 100pF CMOS output N channel open drain output Fig 3 1 1 Circuit for measuring output switching Fig 3 1 2 Circuit for measuring output switching characteristics 1 characteristics 2 3807 GROUP USER S MANUAL 3 11 APPENDIX 3 1 Electrical characteristics Timing Diagram tWH CNTR tWL CNTR CNTR o CNTR 1 tWH INT tWL INT al 8V INTo I
204. k output Output clock frequency selection bits 1 1 O ports or clock output function selection The P34 clock output control bit b0 of port P2P3 control register selects the I O port or clock output function When clock output function is selected the clock is output regardless of the port P34 direction register settings 000 Directly after bit O is written to the port or clock output is switched Dn bd Esau synchronous to a falling edge of clock frequency selected by the 011 L fixed for output output clock frequency selection bit When memory expansion mode 100 f XIN f XCIN in low speed mode or microprocessor mode is selected in CPU mode register b1 bO 101 f XIN2 f XcIN 2 in low speed mode 110 f XiN 4 f XCIN 4 in low speed mode clock output is selected on regardless of P34 clock output control bit 111 f XIN 16 F XCIN 16 in low speed mode settings or port P34 direction register settings Not used return 0 when read P2 P32 input level selection bit 2 Selection of output clock frequency 0 CMOS level input The output clock frequency selection bits b3 b2 b1 of port P2P3 1 TTL level input control register select the output clock frequency The output waveform when f XIN or f Xcin is selected depends on Xin or Xcin input waveform however all other output waveform settings have a duty cycle of 50 Fig 52 Structure of Port P2P3 control register
205. kage Code JEDEC Cod SEDEC Code _Weight z Lead Material QFP80 P 1420 0 80 158 Alloy 42 Scale 2 1 O LJ i e E30 Recommended Mount Pad Dimension in Millimeters Ei I CN 3807 GROUP USER S MANUAL 3 59 APPENDIX 3 9 Machine instructions 3 9 Machine instructions Symbol Function Details Addressing mode A BIT A ZP BIT ZP n JOP n JOP OP n ADC Note 1 Note 5 When T 0 ASA M C When T 1 M X E MX M C Adds the carry accumulator and memory con tents The results are entered into the accumulator Adds the contents of the memory in the ad dress indicated by index register X the contents of the memory specified by the ad dressing mode and the carry The results are entered into the memory at the address indi cated by index register X AND Note 1 AND s the accumulator and memory con tents The results are entered into the accumulator AND s the contents of the memory of the ad dress indicated by index register X and the contents of the memory specified by the ad dressing mode The results are entered into the memory at the address indicated by index register X Shifts the contents of accumulator or contents of memory one bit to the left The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag Ab or Mb 0 Branches when the cont
206. l time port register set the real time port data pointer A B switch bit to 0 select the R W pointer and also write a value into the 3 bits of the real time port data pointers A B With this the real time port register for writing will be specified After that when a value is written into the real time port register address 002416 the data is written into the specified real time port register and also the R W pointer value is automatically decreased by 1 Then writing data is enabled into the next real time port register A value of 0002 to 1112 can be set int the R W pointer regardless of the operating mode specified by the timer A B operating mode selection bit and the R W pointer value is automatically decreased by 1 by writing data into the real time port register However when a value becomes 0002 the R W pointer value is decreased by 1 in the numeral range of stages to be used in each operating mode un less the R W pointer is set again at the subsequent write operation to the real time port register When 1112 7 is set in the R W pointer the R W pointer operation in each selected mode is as follows During 8 repeated load mode 7 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 gt 0 gt 7 gt 6 gt 5 During 6 repeated load mode 7 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 gt 0 gt 5 gt 4 gt 3 During 5 repeated load mode 75654 32104 3 2 During one shot pulse generation mode 7 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 gt 0 gt 2 gt 1 gt 0 When reading
207. latch WiPrecautions Set the double function port of CNTRo CNTRt pin to output in this mode Figure 23 shows the timing chart of the programmable waveform generation mode 6 Programmable one shot generating mode Mode selection This mode can be selected by setting 101 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TYM Count source selection In high or middle speed mode f XiN 2 or f XiN 16 can be selected as the count source Interrupt The interrupt generation at underflow is the same as already explained for the timer mode The one shot generating trigger condition must be set to the INTo interrupt edge selection bit bO and INT interrupt edge selection bit b1 of INTEDGE Setting these bits to 0 causes the interrupt request being triggered by a falling edge setting them to 1 causes the interrupt request being triggered by a rising edge The INTo interrupt request bit 60 and INT interrupt request bit b1 of IREQ1 are set to 1 by detecting the active edge of the INT pin Explanation of operation For a H one shot pulse set bit 5 of TXM TYM to 0 During timer operation stop The output level of CNTRo CNTRt pin is initialized to L at mode selection Set the one shot pulse width to TXH TXL TYH TYL A trigger generation during timer stop input signal to INTo INT1 pin is invalid During timer operation enabled When a trigger generation
208. le 6 List of I O port functions 1 HARDWARE FUNCTIONAL DESCRIPTION 3807 GROUP USER S MANUAL Pin Name Input Output 1 0 Format Non Port Function Related SFRs Ref No POo P07 Port PO Input output CMOS compatible input level Address low order byte output CPU mode register 1 P10 P17 Port P1 jindividual bits CMOS 3 state output Address high order byte output Pull up control register P20 P27 Port P2 CMOS TTL input level Data bus I O CPU mode register CMOS 3 state output Pull up control register Port P2P3 control register P3o RTPe Port P3 CMOS compatible input level Real time port output CPU mode register 2 P31 RTP7 CMOS 3 state output Real time port control register P32 CMOS TTL input level Control signal input CPU mode register 3 CMOS 3 state output Port P2P3 control register P33 CMOS compatible input level Control signal output CPU mode register CMOS 3 state output P34 CKouT Clock output output CPU mode register 4 Port P2P3 control register P35 P37 Control signal I O CPU mode register 3 P40 XcouT Port P4 Sub clock generating circuit CPU mode register 5 P41 XCIN 6 P42 INTo External interrupt input Interrupt edge selection register 7 P43 INT1 Timer X Timer Y function input P44 RxD Serial 1 01 function I O Serial l O1 control register 8 P45 TxD UART control register 9 P46 ScLK1 10 P47 SRDY1 11 P
209. lication circuit example 91 10594 Buij o4ju09 104 LGM Z Jejouoo ejouiaH uq 8 1eu Iq JOU 19 01JUO9 3J0WIY Ey 1q 8 z 19W11 uq 8 sour Josues xn J epoui 4ejunoo juo 3 991 A PWLL Ny 28 JO SIWIS8U Jnod Jajem 10H pow juewenseau poned es ng 113 91 x JOWLL Jojsiuueu Ajddns Jayem JOH JO OW UB Y dino uod awy e9y 10 SI19y sunyessdwa 197E M 1q 91 g Jar yndjno uod aun eay JOSUSS 9A9 JSIEM SAJBA uosueduioo a 1a 91 y 18w11 di TTD c SMA 9SUBLUIONO9 3 a 0d JOYUB eAjeA oneubeuo oa 3 20d 00d dnoJ6 08 39 autx3a uohel 2 89 3807 GROUP USER S MANUAL Fig 2 7 1 Hot water supply system application example APPLICATION 2 7 Application circuit example 91193138 09 4 J3INALVUOIOJDILU J9 01JUu0O9 Wa SAS dnojJ6 08 3JdWEX3 uonediy 3 pow peeds uDiu e ppiuu 104 490 09 3 apou peeds Mo JO 420 2 jun wslueyoow JeBueuo Gd woy 10sueg SJB9 JO J9 01 U09 WYT ueuo GA oipne 1e5 Fig 2 7 2 CD changer car audio application example 3807 GROUP USER S MANUAL 2 90 APPLICATION t example Ion circul 2 7 Applicat indino duing indino 101u09 uonezuopoaq indino ugy 11e 10H jndino q31 indino 041u09 SALA oneuDeuiloJ29 43 indino Jazzng Z Jo41u09 Jojow Buiddeis 101 U09 Jojow Buiddeis indino jeyesy yeas 1910 indino Jajea
210. lock input oscillation frequency to the max 3 Vcc 4 MHz 3 4 3807 GROUP USER S MANUAL APPENDIX 3 1 Electrical characteristics 3 1 3 Electrical characteristics Table 3 1 5 Electrical characteristics 1 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions H output voltage P00 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P62 P65 P70 P77 P80 P87 CMPour Note 1 loH 10mA Vcc 4 0 to 5 5V loH 1 0mA Vcc 2 7 to 5 5V loL 10mA VCC 4 0 to 5 5V L output voltage P00 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P62 P65 P70 P77 P80 P87 CMPouT loL 1 6mA VCC 2 7 to 5 5V Hysteresis P42 P43 P51 P55 P73 Note 2 CNTRo CNTR1 INTo INT4 ADT Hysteresis RxD SCLK1 SIN2 SCLK2 Hysteresis RESET H input current POo P07 P10 P17 P20 P30 P37 P40 P47 P50 P60 P65 P70 P77 P80 Vi Vcc Pin floating Pull up transistors off H input current RESET CNVss Vi Voc H input current XIN Vi VCC L input current POo P07 P10 P17 P20 P30 P37 P40 P47 P50 P60 P65 P70 P77 P80 Vi VSS Pin floating Pull up transistors off L input current RESET CNVss VI VSS L input current XIN VI VSS
211. logy Corp C T D m 0 ay 5 E 2 ENESAS 3807 Group User s Manual MITSUBISHI 8 BIT SINGLE CHIP MICROCOMPUTER 740 FAMILY 38000 SERIES Renesas Electronics www renesas com keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party O Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials All information contained in these materials including product data diagrams and cha
212. m runaway APPENDIX 3 4 Countermeasures against noise Note Microcompute Thermistor Note The resistor is used for dividing resistance with a thermistor Fig 3 4 5 Analog signal line and a resistor and a capacitor J Microcomputer Mutual inductance UN M Large current Fig 3 4 6 Wiring for a large current signal line N G Fig 3 4 7 Wiring to a signal line where potential levels change frequently 3807 GROUP USER S MANUAL 3 31 APPENDIX 3 4 Countermeasures against noise 3 4 5 Setup for I O ports Setup I O ports using hardware and software as follows lt Hardware gt Connect a resistor of 100 Q or more to an I O port inseries TATUS Software As for an input port read data several times by a gt program for checking whether input levels are I O port equal or not pins As for an output port since the output data may reverse because of noise rewrite data to its port latch at fixed periods Rewirte data to direction registers and pull up control registers only the product having it at fixed periods When a direction register is set for input port again at fixed periods a several nanosecond short pulse may be output from this port If this is undesirable connect a capacitor to this port to remove the noise pulse Fig 3 4 8 Setup for I O ports 3 4 6 Providing of watchdog timer function by software If a microcomputer runs away because of n
213. me Note 2 tr SCLK2 tr CMOS Serial 1 02 clock output falling time CMOS output rising time Note 3 t CMOS CMOS output falling time Note 3 tc ScLk2 2 160 tc ScLk2 2 160 Note 1 When the P45 TxD P channel output disable bit of the UART control register bit 4 of address 001B16 is 0 2 When the P71 SouT2 P72 ScLk2 P channel output disable bit of the serial 1 02 control register1 bit 7 of address 001D16 is 0 3 XOUT pin is excluded Table 3 1 13 Switching characteristics 2 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter Test conditions Limits Min Typ twH SCLK1 twL SCLK1 Serial 1 01 clock output H pulse width Serial 1 01 clock output L pulse width ta ScLk1 TXD Serial l O1 output delay time Note 1 tv ScLK1 TXD Serial l O1 output valid time Note 1 tr SCLK1 Serial 1 01 clock output rising time tr SCLK1 Serial 1 01 clock output falling time Fig 3 1 1 tc ScLk1 2 50 tc ScLk1 2 50 30 twH SCLK2 twL SCLK2 Serial 1 02 clock output H pulse width Serial 1 02 clock output L pulse width td SCLK2 SOUT2 Serial 1 02 output delay time Note 2 tv SCLK2 SOUT2 Serial 1 02 output valid time Note 2 tr SCLK2 Serial 1 02 clock output falling time tc ScLK2 2 240 tc ScLK2 2
214. mer B count source stop bit Operating is set to 0 automatically at genera ting a start trigger Stop Note 1 In low speed mode f Xcin 2 is selected 2 In low speed mode f Xcin 16 is selected 3 The rising edge or falling edge of the external trigger is switched by the INT4 interrupt edge selection bit bit 4 of the interrupt edge selection register Address 3A16 However when the One shot pulse generation mode is selected a rising falling double edge trigger is generated in spite of the contents of the INT2 interrupt edge selection bit 4 At a read operation 0 is always read out Fig 3 5 24 Structure of Real time port control register 0 3807 GROUP USER S MANUAL 3 47 APPENDIX 3 5 List of registers Real time port control register 1 b7 b6 b5 b4 b3 b2 b1 bO ITITI Real time port control register 1 RTPCON1 Address 2C16 Timer A operating mode 8 repeated load mode selection bits 6 repeated load mode 5 repeated load mode One shot pulse generation mode Real time port data pointer A RW pointer switch bit Note 1 1 Output pointer Timer A interrupt mode Interrupts occur when a Real selection bit time port output pointer value becomes 0002 1 Interrupt request occurs in spite of a Real time port output pointer value Real time port register 0 ola Real time port register 1 Real time port register 2 Real time port register 3 pe Real time port register
215. n 16 Timer XY control register Address 1416 veros TTT TLL E Timer X stop control bit Stop counting set this bit to 0 at starting counting Timer X High order Address 2116 b7 bo Timer X Low order Address 2016 gt Set division ratio 1 122 1 Port P5 direction register Address 0B16 A a gt P54 CNTRo Output mode ran P5 Address ae T gt H is output at stopping a piezoelectric buzzer output Fig 2 2 19 Setting of related registers Piezoelectric buzzer output 3807 GROUP USER S MANUAL 2 19 APPLICATION 2 2 Timer Control procedure Figure 2 2 20 shows a control procedure RESET Initialization eX This bit is not used in this application Set it to O or 1 It s value can be disregarded P5 Address 0A 6 bit4 lt 1 Set the port state at stopping a piezoelectric buzzer P5D Address OB16 lt XXX1XXXX2 output H level output ICON1 Address 3E 6 bit4 0 Timer X interrupts Disabled TXYCON Address 1416 bito lt 1 Timer X count Stopped TXM Address 2716 lt 010X00012 stop outputting a piezoelectric buzzer TXL Address 2016 122 1 Timer X Pulse output mode TXH Address 2116 9 Set division ratio 1 to the Timer X Main processing The piezoelectric buzzer request occured in the A piezoelectric buzzer main processing is processed
216. n CNVss pin and Vss pin or Vcc pin with 1 to 10 kQ resistance The mask ROM version track of port CNVss has no operational inter ference even if it is connected via a resistor 1 60 3807 GROUP USER S MANUAL HARDWARE DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc tion 1 Mask ROM Order Confirmation Form 2 Mark Specification Form 3 Data to be written to ROM in EPROM form three identical cop ies ROM PROGRAMMING METHOD The built in PROM of the blank One Time PROM version and built in EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter Set the address of PROM programmer in the user ROM area Table 10 Special programming adapter Package Name of Programming Adapter 80P6N A PCA4738F 80A 80D0 PCA4738L 80A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes To en sure proper operation after programming the procedure shown in Figure 64 is recommended to verify programming Programming with PROM programmer Screening Caution 150 C for 40 hours Verification with PROM programmer Functional check in target device Caution The screening temperature is far higher than the storage temperature Never expose to 150 C exceeding 100 hours Fig 64 Programming and te
217. n mode and microprocessor mode memory can be ex panded externally through ports PO to P3 In these modes ports PO to P3 lose their I O port functions and become bus pins Table 9 Port functions in memory expansion mode and microprocessor mode Port Name Function Port PO Outputs 8 bits low order byte of address Port P1 Outputs 8 bits high order byte of address Port P2 Operates as I O pins for data D7 to Do including instruction code Port P3 P30 and P31 function only as output pins except that the port latch cannot be read P32 is the ONW input pin P33 is the RESTour output pin Note P34 is the output pin P35 is the SYNC output pin P3e is the WR output pin and P37 is the RD output pin Note If CNVss is connected to Vss the microcomputer goes to single chip mode after a reset so this pin cannot be used as the RESETour output pin 1 Single chip mode Select this mode by resetting the microcomputer with CNVss connected to Vss 2 Memory expansion mode Select this mode by setting the processor mode bits b1 bO to 01 in software with CNVss connected to Vss This mode enables external memory expansion while maintaining the validity of the internal ROM However some I O devices will not support the memory expansion mode Internal ROM will take precedence over external memory if addresses conflict 3 Microprocessor mode Select this mode by resetting the microcomputer with CNVss con necte
218. n to the Vss line of the analog circuit 3 A clock frequency during an A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D conversion O f XIN is 500 kHz or more When the ONW pin is L f XIN is 1 MHz or more Do not execute the STP instruction and WIT instruction 3 3 4 Notes on the RESET pin When a rising time of the reset signal is long connect a ceramic capacitor or others across the RESET pin and the Vss pin And use a 1000 pF or more capacitor for high frequency use When connecting the capacitor make sure the following eMake the length of the wiring which is connected to a capacitor the shortest possible eMake sure to check the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin a microcomputer may malfunction 3 3 5 Notes on input and output pins 1 Fix of a port input level in stand by state Fix input levels of an input and an I O port for getting effect of low power dissipation in stand by state especially for the I O ports of the N channel open drain Pull up connect the port to Vcc or pull down connect the port to Vss these ports through a resistor When determining a resistance value make sure the following e External circuit e Variation of output levels during the ordinary
219. nabled gt Receive enabled gt Clock synchronous serial I O gt Clock synchronous serial I O gt Serial l O1 enabled AAA Serial 1 01 enabled Transmit enabled Both of units UART control register Address 1B 6 b7 b uamrcoN fol P45 TXD pin CMOS output Baud rate generator Address 1C 6 b Set division ratio 1 Fig 2 3 34 Setting of related registers Cyclic transmission or reception of block data between microcomputers 3807 GROUP USER S MANUAL 2 53 APPLICATION 2 3 Serial I O Control procedure D Control in the master unit After a setting of the related registers is completed as shown in Figure 2 3 34 in the master unit transmission or reception of 1 byte data is started simply by writing transmission data to the Transmit buffer register To perform the communication in the timing shown in Figure 2 3 33 therefore take the timing into account and write transmission data Read out the reception data when the Serial 1 01 transmit interrupt request bit is set to 1 or before the next transmission data is written to the Transmit buffer register A processing example in the master unit using timer interrupts is shown below Interrupt processing routine executed every 488 us Note 1 When using the Index X mode flag T CLT Note 1 Note 2 When using the Decimal mode flag D CLD Note 2 Push the register used in the interrupt
220. nesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office eq
221. ng or falling edge of External interrupt CNTRo input active edge selectable CNTRi1 11 FFE916 FFE816 At detection of either rising or falling edge of External interrupt CNTRt input active edge selectable Serial 1 02 12 FFE716 FFE616 At completion of serial I O2 data transmit Valid when serial 1 02 is selected and receive INT2 13 FFE516 FFE416 At detection of either rising or falling edge of External interrupt INT2 input active edge selectable Valid when INT2 interrupt is selected Timert At timer 1 underflow Valid when timer 1 interrupt is selected Timer A 14 FFE316 FFE216 At timer A underflow Timer B 15 FFE116 FFEO016 At timer B underflow A D conversion 16 FFDF16 FFDEt6 At completion of A D conversion Valid when A D interrupt is selected ADT At falling edge of ADT input External interrupt valid at falling Valid when ADT interrupt is selected and when A D external trigger is selected BRK instruction 17 FFDD16 FFDCi6 At BRK instruction execution Non maskable software interrupt Note1 Vector addresses contain interrupt jump destination addresses 2 Reset function in the same way as an interrupt with the highest priority 3807 GROUP USER S MANUAL 1 21 HARDWARE FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag BRK instruction Reset Fig 15 Interrupt control bO Interrupt edge selection register INTEDGE address 003A 6 INTo interrupt edge selection bit INT1
222. nnnnn anan aiaa aaa cnn 1 63 Fig 66 Time up to execution of the interrupt processing routine seeeeeess 1 63 Fig 67 A D conversion equivalent ClrCUll es esiis ianiai rasian treada ania a anii iania aaide 1 65 Fig 68 A D conversion timing liar etcetera terree a ra ttes aE 1 65 CHAPTER 2 APPLICATION Fig 2 1 1 Memory map of I O port related registers ooccccinninicinccccnnonnncnnccnonannnnnno no nannnn nana nnnns 2 2 Fig 2 1 2 Structure of Port Pi i 0 1 2 3 4 5 7 8 2 3 Fig 2 1 3 Structure of Port Pi direction register i20 1 2 3 4 5 7 8 cconnicccninininanicinnns 2 3 IQs 2 WA Struct r of Port PG uini etr ett Fen DR eere Rt dede dea aed a et edd ee dd 2 4 Fig 2 1 5 Structure of Port P6 direction register ssssssssssssseeeeeenne 2 4 Fig 2 2 1 Memory map of timer related registers 2 6 Fig 2 2 2 Structure of Timer XY control register 2 7 Fig 2 2 3 Structure of Timer X Low order Timer X High order Timer Y Low order Timer Y High order 2 7 Fig 2 2 4 Structure of Timer 1 Timer 3 ou ccccccccccccssssscceecssceuececssseeeccecsceeeeesecseeeecesssssaeeesessnees 2 8 Fig 2 2 5 Structure of Timer 2 nennen nennen nn trnnr ennt nennt 2 8 Fig 2 2 6 Structure of Timer X mode register ansasinen ii cnn 2 9 Fig 2 2 7 Structure of Timer Y mode register ccceeeccecseeeeeeeeeeeeeeeeeeeeeeceaeeeeeaaeesseeeseaeeesaes 2 9 Fig 2 2 8 Structure of Timer 123 mode register 2 11
223. ntents of the INT4 interrupt source bit b7 of the interrupt edge selection register Figure 34 shows a timing chart of the one shot pulse generation mode 5 Selection of timer interrupt mode The timer is a count down system The contents of the timer latch are reloaded by the count pulse subsequent to the moment when the contents of the counter becomes 000016 At the same time the interrupt request bit corresponding to each timer is set to 1 The interrupt request corresponding to the value of the real time port output pointer can also be controlled For controlling the interrupt request bit refer to the item pertaining to the timer interrupt mode selection bit of the real time port control register 1 2 shown in figure 29 and 30 6 Switch of timer count source The timer A and the timer B can select the system clock 6 divided by 2 or 16 as a count source with the timer A B count source selection bit b0 of real time port control register 0 Timer latches Each of the timer A and the timer B has two 16 bit timer latches Data is written into the 8 low order bits and the 8 high order bits in this order When the high order side has been written the next latch is automatically specified The writing pointer changes in sequence as 1 0 1 0 1 The timer latch to be written first can be specified by setting the timer writing pointer Data is not written directly into the timer A and the timer B When reading the contents o
224. o 000716 and 084016 to FFFF 16 and only read and write cycles are extended Read cycle Dummy cycle Write cycle Read cycle Dummy cycle Write cycle e ef 9 AD15 ADo RD WR ONW Period during which ONW input signal is received During this period the ONW signal must be fixed at either H or L At all other times the input level of the ONW signal has no affect on operations The bus cycles is not extended for an address in the area 000816 to 083F 16 regardless of whether the ONW signal is received Fig 63 ONW function timing 1 58 3807 GROUP USER S MANUAL NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register PS after a reset are undefined except for the interrupt disable flag I which is 1 After a reset initialize flags which affect program execution In particular it is essential to initialize the index X mode T and the decimal mode D flags because of their effect on calculations Interrupts The contents of the interrupt request bits do not change immediately after they have been written After writing to an interrupt request reg ister execute at least one instruction before performing a BBC or BBS instruction Decimal Calculations To calculate in decimal notation set the decimal mode flag D to 1 then execute an ADC or SBC instruction Only the ADC and SBC instructions yield proper decimal results After executing an ADC or SBC instruc
225. o interrupt request 1 Interrupt request 5 Timer B interrupt request bit 0 No interrupt request 1 Interrupt request ADT AD conversion 0 No interrupt request interrupt request bit 1 Interrupt request 7 Nothing is allocated for this bit This is a write disabled bit x When this bit is read out the value is 0 0 is set by software but not 1 Fig 3 5 36 Structure of Interrupt request register 2 3 54 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Interrupt control register 1 b7 b6 b5 b4 b3 b2 bi bO CI control register 1 ICON1 Address 2g ENT a ee mm interrupt enable bit Interrupt disabled Interrupt enabled INT interrupt enable bit Interrupt disabled 1 Interrupt enabled 2 Serial 1 01 receive interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 3 Serial 1 01 transmit interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 4 Timer X interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer Y interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled Timer 2 INTs interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled 7 Timer 3 INTa interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled Fig 3 5 37 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 of TT Tt tt rd control reigster 2 ICON2 Address uu Cosme
226. ogramming conditions of PROM programmer are not set automatically because there are no internal device ID codes Accurately set the following conditions for data write read Take care not to apply 21 V to Vpp pin is also used as the CNVSs pin or the product may be permanently damaged O Programming voltage 12 5 V O Setting of programming adapter switch refer to table 3 3 2 O Setting of PROM programmer address refer to table 3 3 3 Table 3 3 2 Setting of programming adapter switch Programming adapter PCA4738F 80A OFF PCA4738L 80A Table 3 3 3 Setting of PROM programmer address Microcomputer PROM programmer start address PROM programmer completion address M38073E4FS M38073E4FP Address 408016 Note 1 Address 7FFD16 Note 1 Note Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD16 in the ROM programmer 3 Erasing Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537 Angstrom At least 15 W sec cm are required to erase EPROM contents 3 28 3807 GROUP USER S MANUAL APPENDIX 3 4 Countermeasures against noise 3 4 Countermeasures against noise Countermeasures against noise are described below The following countermeasures are effective against noise in theory however it is necessary not only to take measures as follows but to evaluate before actual use 3 4 1 Shortest wiring length The wiring on a printed circu
227. oise or others it can be detected by a software watchdog Main routine interrupt processing routine timer and the microcomputer can be reset to normal operation This is equal to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the following example to reset a microcomputer to normal operation the main routine detects errors of Main processing the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is SWDT SWDT 1 Interrupt processing repeated multiple times in a single main routine Return processing Interrupt processing Main routine The main routine routine errors errors Assigns asingle byte of RAM to a software watchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following Fig 3 4 9 Watchdog timer by software condition N 1 gt Counts of interrupt processing executed in each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin e Waiches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial valu
228. on that is currently in execution Address bus PC X S sPS Xs t SPSKS 2 SPSX BL X BH XAL AH Data bus SYNC CPU operation code fetch cycle BL BH Vector address of each interrupt AL AH Jump destination address of each interrupt SPS 0016 or 0116 Fig 65 Timing chart after an interrupt occurs Generation of interrupt request Start of interrupt processing Y Waiting time for Main routine post processing of pipeline Stack push and Vector fetch Interrupt processing routine O to 16 cycles 2 cycles i 5 cycles 7 to 23 cycles At performing 8 0 MHz 1 75 usto 5 75 us gt gt at execution of DIV instruction 16 cycles Fig 66 Time up to execution of the interrupt processing routine 3807 GROUP USER S MANUAL 1 63 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT A D Converter A D conversion is started by setting AD conversion completion bit to 0 During A D conversion inter nal operations are performed as follows 1 After the start of A D conversion A D conversion register goes to 0016 2 The highest order bit of A D conversion register is set to 1 and the comparison voltage Vref is input to the comparator Then Vref is compared with analog input voltage VIN 3 As a result of comparison when Vref lt VIN the highest order bit of A D conversion register be comes 1 When Vref gt VIN the highest order bit becom
229. ontents of the interrupt disable flag to 1 3 66 Sets the contents of the index X mode flag to I 3807 GROUP USER S MANUAL APPENDIX 3 9 Machine instructions Addressing mode Processor status register ABS X ABS Y ND ZP IND IND X IND Y REL 3 OP n JOP n OP n OP n JOP n JOP n JOP D 3807 GROUP USER S MANUAL 3 67 APPENDIX 3 9 Machine instructions Addressing mode Function Details A BIT A ZP BIT ZP n OP n JOP H OP n Stores the contents of accumulator in memory Stops the oscillator Stores the contents of index register X in memory Stores the contents of index register Y in memory Transfers the contents of the accumulator to index register X Transfers the contents of the accumulator to index register Y ests whether the contents of memory are 0 or not Transfers the contents of the stack pointer to index register X Transfers the contents of index register X to he accumulator ransfers the contents of index register X to the stack pointer Transfers the contents of index register Y to the accumulator Stops the internal clock m The number of cycles
230. operation stand by state the stop mode by executing the STP instruction the wait mode by executing the WIT instruction Reason Even when setting as an output port with its direction register in the following state e N channel when the content of the port latch is 1 the transistor becomes the OFF state which causes the ports to be the high impedance state Make sure that the level becomes undefined depending on external circuits Accordingly the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I O port are undefined This may cause power source current 2 Modify of the content of I O port latch When the content of the port latch of an I O port is modified with the bit managing instruction the value of the unspecified bit may be changed Reason The bit managing instruction is read modify write instruction for reading and writing data by a byte unit Accordingly when this instruction is executed on one bit of the port latch of an I O port the following is executed to all bits of the port latch As for a bit which is set as an input port The pin state is read in the CPU and is written to this bit after bit managing As for a bit which is set as an output port The bit value is read in the CPU and is written to this bit after bit managing 3 26 3807 GROUP USER S MANUAL APPENDIX 3 3 Notes on use Make sure the following Even
231. or a fractional number of bits close to LSB if the said bit is MSB first For the remaining bits the previously re ceived data is shifted At transmit operation using the clock synchronous serial I O the Scmpz2 signal can be output by comparing the state of the transmit pin Sour with the state of the receive pin Sin2 in synchronization with a rise of the transfer clock If the output level of the Sour pin is equal to the input level to the Sinz pin L is output from the ScMP2 pin If not H is output At this time an INT2 interrupt request can also be generated Select a valid edge by bit 2 of the interrupt edge selection register address 003A16 Serial 1 02 Control Registers 1 2 SIO2CON1 SIO2CON2 The serial 1 02 control registers 1 and 2 are containing various se lection bits for serial l O2 control as shown in Figure 40 1 44 3 Serial 1 02 control register 1 SIO2CON1 address 001D16 Internal synchronous clock selection bit 1 bO b2 b 0 0 0 f XiN 8 f XcIN 8 in low speed mode 1 f XiN 16 f XciN 16 in low speed mode f XiN 32 f XciN 32 in low speed mode f XiN 64 f XciN 64 in low speed mode f XiN 128 f XciN 128 in low speed mode f XiN 256 f XciN 256 in low speed mode 0 0 0 1 1 0 1 1 1 1 Serial 1 02 port selection bit 0 I O port 1 Sout2 ScLk2 output pin Srpy2 output enable bit 0 P73 pin is normal I O pin 1 P73
232. ory location operated on by the BIT instruction is stored in the overflow flag 8 Negative flag N The N flag is set if the result of an arithmetic operation or data transfer is negative When the BIT instruction is executed bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction 1 10 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION CPU Mode Register The CPU mode register contains the stack page selection bit and processor mode bits The CPU mode register is allocated at address 003B16 CPU mode register CPUM address 003B16 Processor mode bits b1 bO 0 0 Single chip mode O 1 Memory expansion mode 1 0 Microprocessor mode 1 1 Not available Stack page selection bit 0 0 page 1 1 page XCOUT drivability selection bit 0 Low drive 1 High drive Port Xc switch bit 0 1 O port function stop oscillating 1 XCIN XCOUT oscillating function Main clock XIN XOUT stop bit 0 oscillating 1 stopped Main clock division ratio selection bits b7 b6 0 0 o f XIN 2 high speed mode O 1 62f XIN 8 middle speed mode 1 0 f XCIN 2 low speed mode 1 1 Not available Fig 7 Structure of CPU mode register 3807 GROUP USER S MANUAL 1 11 HARDWARE FUNCTIONAL DESCRIPTION Memory Sp
233. oth the transmit enable bit TE and the receive enable bit RE to 0 6 Control of data transmission using the transmit shift completion flag The transmit shift completion flag changes from 1 to O with a delay of 0 5 to 1 5 shift clocks When checking the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data transmission note this delay 7 Control of data transmission using an external clock When an external clock is used as the synchronous clock for data transmission set the transmit enable bit to 1 at H level of the SCLK input signal Also write data to the transmit buffer register at H level of the SCLK input signal 3 3 3 Notes on the A D converter 1 Input of signals from signal source with high impedance to an analog input pin Make the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01 uF to 1 uF Further make sure to check the operation of application products on the user side Reason The A D converter builds in the capacitor for analog voltage comparison Accordingly when signals from signal source with high impedance are input to an analog input pin a charge and discharge noise generates This may cause the A D conversion precision to be worse 3807 GROUP USER S MANUAL 3 25 APPENDIX 3 3 Notes on use 2 AVss pin Connect a power source for the A D converter AVSS pi
234. ourth comparison 6 A result of the sixth comparison 8 A result of the eighth comparison 1 64 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Figures 67 shows A D conversion equivalent cir cuit and Figure 68 shows A D conversion timing chart Vcc Vss Sampling clock Chopper amplifier Mi NV NN ANV NNN i ANV WAY WAY ANV WE ANN A D conversion register Doo ADT A D conversion interrupt request A D control register ADVREF O Vref Reference D A converter clock o Fig 67 A D conversion equivalent circuit Write signal for A D control register g 3 50 cycles AD conversion completion bit Sampling clock Fig 68 A D conversion timing chart 3807 GROUP USER S MANUAL 1 65 CHAPTER 2 APPLICATION 2 1 I O port 2 2 Timer 2 3 Serial I O 2 4 Real time output port 2 5 A D converter 2 6 Reset 2 7 Application circuit example APPLICATION 2 1 1 0 port 2 1 1 0 port 2 1 1 Memory map of I O port 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000818 000616 000D16 000E 16 000F 16 001016 001116 Fig 2 1 1 Memory map of I O port related registers 2 2 3807 GROUP USER S MANUAL APPLICATION 2 1 1 0 port 2 1 2 Related registers Port Pi b7 b6 b5 b4 b3 b2 b1 bO Port Pi P
235. ows and each cyclic timer interrupt request occurs Use Generation of cyclic interrupts Clock function measurement of 25m second gt Application example 1 Control of a main routine cycle Function 3 Output of Rectangular waveform Timer X Timer Y Timer 2 The output level of the CNTR pin is inverted every time a timer underflows Pulse output mode Use A piezoelectric buzzer output gt Application example 2 Generation of the remote control carrier waveforms Function 4 Count of External pulse Timer X Timer Y External pulses input to the CNTR pin are selected as a timer count source Event counter mode Use Measurement of frequency gt Application example 3 Division of external pulses Generation of interrupts in a cycle based on an external pulse count of a reel pulse Function 5 Measurement of External pulse width Timer X Timer Y The H or L level width of external pulses input to CNTR pin is measured Pulse width measurement mode Use Measurement of external pulse frequency Measurement of pulse width of FG pulse gener ated by motor Application example 4 Measurement of external pulse duty when the frequency is fixed FG pulse Pulse used for detecting the motor speed to control the motor speed 2 14 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer 2 Timer application example 1 Clock function measurement of 25 ms Outline The input clock is divided by a
236. pin is SRDY2 output pin Transfer direction selection bit 0 LSB first 1 MSB first Serial 1 O2 synchronous clock selection bit 0 External clock 1 Internal clock P71 Soure P72 ScLk2 P channel output disable bit 0 CMOS output in output mode 1 N channel open drain output in output mode b0 Serial 1 02 control register 2 SIO2CON2 address 001E16 Optional transfer bits b2 b1 b0 8 bit 4 bit 5 bit 6 bit 7 bit 8 bit Not used returns 0 when read Serial 1 02 I O comparison signal control bit 0 P51 VO 1 Scmp2 output Sour pin control bit P71 0 Output active 1 Output high impedance Fig 40 Structure of Serial 1 02 control registers 1 2 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Internal synchronous clock selection bit Xen O 22 40 Data bus Main clock division ratio ve selection bits Note 00 XIN Q ZZ 01 atch Serial 1 02 synchronous clock selection bit o lt q O lt 802 Synchronous circuit SRDY output enable bit External clock P72 latch Optional transfer bits 3 Q 1 P72 ScLk2 Serial 1 02 vo gt Serial I O counter 2 3 Serial 1 02 port selection bit P71 latch d P71 Soure oe O interrupt request Serial 1 02 port selection bit Y P7o Sie O Ser
237. put output disable bit 1 N channel open drain POFF output Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 1 pu gt gt o eo Fig 3 5 12 Structure of UART control register 3807 GROUP USER S MANUAL 3 39 APPENDIX 3 5 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 bO Baud rate generator BRG Address 1C16 By Function faesfR w A count value of Baud rate generator is set ES m Y Fig 3 5 13 Structure of Baud rate generator Serial 1 02 control register 1 b7 b6 b5 b4 b3 b2 bi bO Serial 1 02 control register 1 SIO2CON1 Address 1D16 Internal synchronous doc clock selection bits XT fXCIN f Xmy 32 f XciN f XiNJ 64 F XcIN 64 f XiN 128 XI 128 1 f XiN 256 f XciN 256 3 Serial 1 02 port selection bit 0 VO port P71 P72 E SouT2 SCLK2 output pin SRDY output enable bit 1 O port P73 SRDY output pin 5 Transfer direction selection bit LSB first MSB first Serial 1 02 synchronous clock o External clock selection bit Internal clock P71 SouT2 P72 ScLk2 T output mode P channel output disable bit gt CMOS output l N channel open drain output Note In low speed mode is selected Fig 3 5 14 Structure of Serial 1 02 control register 1 3 40 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Serial 1 02 cont
238. quest request bit 1 Interrupt request 4 Timer A interrupt request bit 0 No interrupt request 1 Interrupt request sb s 5 Timer B interrupt request bit 0 No interrupt request 1 Interrupt request ADT AD conversion 0 No interrupt request interrupt request bit 1 Interrupt request 7 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 Pot of of of of of of om xr rfp 0 is set by software but not 1 Fig 2 3 12 Structure of Interrupt request register 2 3807 GROUP USER S MANUAL 2 35 APPLICATION 2 3 Serial I O Interrupt control register 1 b7 b6 b5 b4 b3 b2 bi bO CI control register 1 ICON1 Address SEE MA A O M interrupt enable bit Interrupt disabled Interrupt enabled INT interrupt enable bit Interrupt disabled i Interrupt enabled 2 Serial l O1 receive interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 3 Serial 1 01 transmit interrupt O Interrupt disabled enable bit 1 Interrupt enabled 4 Timer X interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer Y interrupt enable bit Interrupt disabled 1 Interrupt enabled Timer 2 INTs interrupt enable 0 Interrupt disabled bit 1 Interrupt enabled UT 3 INTa interrupt enable 0 Interrupt disabled 1 Interrupt enabled Fig 2 3 13 Structure of Interrupt control register 1 Interrupt control reg
239. r For example When the heading adjustive time is 8 ms and the timer interrupt cycle is 1 ms set 8 as the initialized value 2 55 APPLICATION 2 3 Serial I O 4 Communication transmit receive using an asynchronous serial I O UART Point 2 byte data is transmitted and received through an asynchronous serial I O The port P42 is used for communication control Figure 2 3 37 shows a connection diagram and Figure 2 3 38 shows a timing chart Transmitting side Receiving side gt P42 3807 group 3807 group Fig 2 3 37 Connection diagram Communication using UART Specifications The Serial l O1 is used UART is selected Transfer bit rate 9600 bps f XIN 4 9152 MHz is divided by 512 Communication control using port P42 The output level of the port P42 is controlled by softoware 2 byte data is transferred from the transmitting side to the receiving side at inter vals of 10 ms generated by timer a TxD N STENE NENEA Fa ST DoXD XD2XDs X DaX Ds XDs XD7Y SP 2 e STADoX 10 ms Fig 2 3 38 Timing chart Communication using UART 2 56 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Table 2 3 1 shows setting examples of Baud rate generator BRG values and transfer bit rate values Figure 2 3 39 shows a setting of related registers at a transmitting side and Figure 2 3 40 shows a setting of related registers at a receiving side Table 2 3 1 Se
240. r A or B write pointer bit 7 of address 2Cie or 2Die Reading is performed in the order of high order and low order At a read operation the value being counted is read out Fig 2 4 7 Structure of Timer A Low order Timer A High order Timer B Low order Timer B High order 2 66 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port 2 4 3 Real time output port application examples Control of stepping motor Outline The rotation of the stepping motor is controlled by using Real time output ports Figure 2 4 8 shows a connection diagram P82 RTPo P83 RTP1 P84 RTP2 Motor 1 P85 RTPs P86 RTP4 P87 RTP5 P3o RTPe P31 RTP7 3807 group Motor 2 Fig 2 4 8 Connection diagram Specifications Each of two motors is controlled by using four Real time output ports Clock f XIN 8 MHz The same data table is used for acceleration and deceleration 20 steps 500 pps max The value of the Timer A and B are updated by each interrupt processing routine When the Timer A and or B stops the L level is output Figure 2 4 9 shows the operation patterns of the motor to be controlled in this application example The Timer A and the Timer B can control the motor independently with different operation patterns Pattern 1 Pattern 2 Pattern 3 P4 A 200 steps at a constant motor speed Forward t rotation Reverse rotation 150 steps at a constant motor speed M Speed Fig 2 4 9
241. r reference voltage DAVREF D A comparator reference voltage CMPVcc Analog comparator power source voltage AVSS Analog power source voltage VIA A D comparator input voltage ANo AN12 VIH H input voltage P0o PO07 P10 P17 P30 P31 P33 P37 P40 P47 P50 P5 P60 P65 P70 P77 P80 P87 H input voltage CMOS input level selected P20 P27 P32 H input voltage TTL input level selected P20 P27 P32 Note H input voltage RESET XiN CNVss L input voltage POo P07 P10 P17 P30 P31 P33 P37 P40 P47 P50 P57 P60 P65 P70 P77 P80 P87 L input voltage CMOS input level selected P20 P27 P32 0 2Vcc L input voltage TTL input level selected P20 P27 P32 Note 0 8 L input voltage RESET CNVss 0 2Vcc L input voltage XIN 0 16Vcc Note When Vcc is 4 0 to 5 5 V KILES ESS Table 3 1 3 Recommended operating conditions 2 Vcc 2 7 to 5 5 V Ta 20 to 85 C unless otherwise noted Limits Typ Parameter H total peak output current Note P00 PO7 P10 P17 P20 P27 P30 P37 P80 P87 H total peak output current Note P40 P47 P50 P57 P60 P62 P65 CMPour P70 P77 L total peak output current Note P00 PO7 P10 P17 P20 P23 P30 P37 P80 P87 L total peak output current Note in single chip mode P24 P27 in memory expans
242. rce selection bit b4 are cleared to 0 Set the timer 2 INT3 interrupt source bit to 1 and timer 1 INT2 as well as timer 2 INT3 interrupt enable bit to disabled 0 before executing the STP instruction Oscillator restarts when an external interrupt is received but the internal clock is not sup plied to the CPU remains at H until timer 2 underflows This al lows time for the clock circuit oscillation to stabilize The internal clock is supplied for the first time when timer 2 underflows Therefore make sure not to set the timer 2 INT3 interrupt request bit to 1 be fore the STP instruction stops the oscillator When the oscillator is restarted by reset apply L level to port RESET until the oscillation is stable since a wait time will not be generated 2 Wait mode If the WIT instruction is executed the internal clock stops at an H level The states of Xin and XciN are the same as the state before executing the WIT instruction The internal clock restarts at reset or when an interrupt is received Since the oscillator does not stop nor mal operation can be started immediately after the clock is restarted XCIN XCOUT XIN Fig 57 Ceramic resonator circuit XCIN XCOUT XIN External oscillation circuit CCOUT Vcc Fig 58 External clock input circuit 1 54 3807 GROUP USER S MANUAL O Port Xc switch bit XQUT Main clock division ratio selection bits note Low speed mode HARD
243. registers 4 3807 GROUP USER S MANUAL 2 75 APPLICATION 2 4 Real time output port Control procedure Figure 2 4 19 Figure 2 4 22 show control procedures Initialization SEI RTPCONO Address RTPCON1 Address 2B16 lt 9116 2C16 lt F816 RTPCON 2 Address 2D16 lt F816 RTPCON3 Address 2E16 0016 TXM Address Address Address Address Address Address 01XX00002 01XX00002 XXXXXX002 XXXXXX112 000000XX2 111111XX2 RTP Address 2416 Initial value TAL TAH TAL TAH TBL TBH TBL TBH ICON2 IREQ2 ICON2 IREQ2 A setting of Real time po registers 0 7 is completed Address Address Address Address Address Address Address Address Address Address Address 3216 9116 Address 2F16 Initial value 9016 2F16 3016 320 lt Initial value Initial value Initial value lt Initial value lt Initial value Initial value 3216 Initial value 3F16 bit4 1 3D16 bit4 0 3F16 bit5 1 3D16 bits 0 RTPCON1 Address RTPCON2 Address RTPCONO Address RTPCONO Address RTPCONS Address 2D16 2C16 lt FCie lt FCte 2B16 bit3 lt 1 2B16 bit6 lt 1 2E16 FFie Fig 2 4 19 Control procedure 1 e X This bit is not used in this application Set it to 0 or 1 It s v
244. ress 0116 0316 0516 0716 0916 0B16 OF 16 1116 Port Pio input mode Port Pio output mode E Port Pi input mode x Port Pi output mode gt Port Piz input mode x 1 Port Piz output mode Port Pis input mode Port Pis output mode s Port Pia input mode Port Pia output mode 0 Port Pisinput mode 1 Port Pis output mode 0 Port Pieinput mode 1 Port Pie output mode 0 Port Pizinput mode 1 Port Piz output mode Fig 3 5 2 Structure of Port Pi direction register i 0 1 2 3 4 5 7 8 3 34 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Port P6 b7 b6 b5 b4 b3 b2 b1 bO Port P6 P6 Address 0C16 B Nam Function atrs R w o Port P6o e n output mode o ofol Write emm Read J Port latch o polo e n input mode Port P62 Write Port latch o fofo Read Value of pins Port P6 Note Edd Port P64 Port P65 6 Nothing i is allocated for these bits These are write disabled bits When these bits are read out the values are 0 Note These bits are used only for input port Fig 3 5 3 Structure of Port P6 Port P6 direction register b7 b6 b5 b4 b3 b2 b1 bO Port P6 direction register P6D Address 0D16 irecti Port P60 input mode o bo Port P6o P6e direction registers Port P6o output mode E Port P6 input mode x Port P61 output mode Ports P63 and P64 are input ports Accordingly these bits do not
245. rocessing for error O X This bit is not used in this application Set it to O or 1 It s value can be disregarded All interrupts Disabled Timer X Pulse width measurement mode Count H level width of pulse input from CNTRo pin e Timer X count Stopped counting Set the initial value of the Timer X Timer X interrupt Enabled CNTRo interrupt Enabled Timer X count Start Interrupts Enabled Error occurs Note The Timer X interrupt occurs at a level except a measurement level when it is L level in this applicaion example Process by software in accordance with the necessity like as a processing for errors is performed only at a measurement level The CNTRo input level is judged by reading a content of the Port P54 register Fig 2 2 27 Control procedure 1 Measurement of pulse width 3807 GROUP USER S MANUAL 2 27 APPLICATION 2 2 Timer CNTRo interrupt processing routine Note 1 CLT Note 2 Note 2 When using the Index X mode flag T CLD Note 3 Note 3 When using the Decimal mode flag D Push register to stack Push the register used in the interrupt processing routine into the stack A TXH A count value is read out and stored to RAM Result of pulse width measurement A high order 8 bit A TXL Result of pulse width measurement A low order 8 bit lt A Pop registers Pop registers which is pushed to stack Note 1 The
246. rol register 2 b7 b6 b5 b4 b3 b2 b1 bO Serial 1 02 control register 2 SIO2CON2 Address ini EINE NER d L7 Optional transfer bits 2k b2 0 0 0 0 1 1 1 1 lx LEX ce ee a000 0 0 0 08 Serial 1 02 I O comparative 7 P51 1 0 ree eee pum Sour pin control bit P71 E O active E Fig 3 5 15 Structure of Serial 1 02 control register 2 Serial 1 02 register b7 b6 b5 b4 b3 b2 bi bO Serial 1 02 register SIO2 Address 1F 6 A shift register for serial transmission and reception fofo e At transmitting Set a transmission data e At receiving Store a reception data eje EXER ME MI Bage ee ES Fig 3 5 16 Structure of Serial 1 02 register 3807 GROUP USER S MANUAL 3 41 APPENDIX 3 5 List of registers Timer X Low order Timer X High order Timer Y Low order Timer Y High order b7 b6 b5 b4 b3 b2 b1 bO Timer X Low order TXL Timer X High order TXH Address 2016 2116 Timer Y Low order TYL Timer Y High order TYH Address 2216 2316 W e A count value of each timer is set 4 e At writing e A value set in this register is written to both a Timer and a corresponding Timer latch at the same time or to only a 1 Jojo Timer latch e A value is written to low order first 1 fofo e At reading When this register is read out a value count value of a 1 lolo corresponding Timer is read out A measurement value is read out in pulse period meas
247. rol register controls the A D conversion process Bits 0 to 3 of this register select specific analog input pins Bit 4 signals the completion of an A D conversion The value of this bit remains at 0 during an A D conversion then changes to 1 when the A D conver sion is completed Writing 0 to this bit starts the A D conversion When bit 6 which is the AD external trigger valid bit is set to 1 this bit enables A D conversion at a falling edge of an ADT input Set ports which is also used as ADT pins to input when using an A D external trigger Bit 5 is the ADVREF input switch bit Writing 1 to this bit this bit always causes ADVREF connection Writing 0 to this bit causes ADVREF connection only during A D conversion and cut off when A D conversion is completed Comparison Voltage Generator The comparison voltage generator divides the voltage between AVss and ADVREF by 256 and outputs the divided voltages Channel Selector The channel selector selects one of the input ports AN12 to ANo and inputs it to the comparator Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A D conversion register When an A D conversion is completed the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to 1 Note that the comparator is constructed linked to a capacitor so set Data bus
248. rrupt request register 2 3 54 Fig 3 5 36 Structure of Interrupt control register 1 3 55 Fig 3 5 36 Structure of Interrupt control register 2 3 55 vi 3807 GROUP USER S MANUAL List of tables List of tables CHAPTER 1 HARDWARE Table 1 Pin description T iek asea ads usa se ze deed 1 4 Table 2 Pin description 2 ssissssssssssseseeee eene enne nnn nnte nennen insta senten sens senes 1 5 Table S List of Supported products miii 1 7 Table 4 Push and pop instructions of accumulator or processor status register 1 9 Table 5 Set and clear instructions of each bit of processor status register 1 10 Table 6 List of 1 O port TUNCIUONS 1 siii as e rte LE et ded A En tex 1 15 Table 7 List of I O port functions 2 eene enn nnne 1 16 Table 8 Interrupt vector addresses and priority sssm nana 1 21 Table 9 Port functions in memory expansion mode and microprocessor mode 1 57 Table 10 Special programming adapter sse nnne nennen nnne 1 61 Table 11 Interrupt sources vector addresses and interrupt priority sssssse 1 62 Table 12 Change of A D conversion register during A D conversion ssses 1 64 CHAPTER 2 APPLICATION Table 2 1 1 Handling of unused pins in single chip mode 2 5 Table 2 1 2 Handling of unused pins in memory expansion mode and microprocessor mode
249. rt after termination of the last output because the L level is output from RTPo to RTP7 when the timer stops as a matter of specification However when the count of the Timer A is stopped and the real time output port is switched over to the programmable I O port after termination of the last output the next RTP data is output in a short period from an underflow of the Timer A till a count stop of the Timer A To avoid outputting the next RTP data in the short period the count of the Timer A is stopped at a start of the last output though the last output data is output and the last output period is counted by using different timers Timer X for the Timer A and timer Y for the Timer B in this case After that counting when the Timer X underflows the real time output port is switched over to the programmable 1 O port and the L level is output To continue to output the last output data after the timer stops just stop the count of the Timer A after termination of the last output Figure 2 4 14 shows the setting method and output timing and Figure 2 4 15 to Figure 2 4 18 show the control procedures for related registers Acceleration A constant motor speed Deceleration 20 steps 200 steps 20 steps RTPo RTP3 Note 1 7 1 6 85 Output pointer value 9 9 Note 2 i i i Timer A count source stop bit Note4 Note 4 AS E E ou n Timer A count value ti
250. rted from the beginning In this case put an interval of 3 cycles or more between the generation of a trigger and the generation of the next trigger If the generation of the next trig ger occurs almost concurrently with the underflow timing of the timer the next real time output may not be performed normally To stop the timer count after generation of a start trigger write 1 in the timer A B count source stop bit of real time port control register 0 at an interval of 3 cycles or more of the timer count source To change the contents of the real time port data pointer A B switch bit the real time port data pointer must be specified simultaneously Therefore use the LDM STA instruction instead of the SEB CLB instruction lf the timer A B count source stop bit is changed 1 0 by a start trigger between the read operation and the write operation of a read modify write instruction such as the SEB instruction which is used in real time port control register 0 the timer count will stop having an effect on the real time output An maximum interval of 2 cycles of the count source is required before the timer A B count source stop bit is cleared to 0 which indicates the count operation state after a start trigger is generated regardless of whether the start trigger is an internal trigger or an external trigger Accordingly do not use the read modify write instruction for real time port control register O in this period If a wri
251. rts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein O Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use O The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials O l these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electri
252. runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer 3807 GROUP USER S MANUAL 3 29 APPENDIX 3 4 Countermeasures against noise An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example Fig 3 4 2 Wiring for clock I O pins 3 Wiring for the VPP pin of the One Time PROM version and the EPROM version In this microcomputer the VPP pin is also used as the CNVss pin Connect an approximately 5 kQ resistor to the VPP pin the shortest possible in series and also to the Vss pin When not connecting the resistor make the length of wiring between the VPP pin and the Vss pin the shortest possible Note Even when a circuit which included an approxi mately 5 kQ resistor is used in the Mask ROM version the maicrocomputer operates correctly Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built in PROM When programming in the built in PROM the impedance of the VPP pin is low to allow the electric current for wiring flow into the PROM Be cause of this noise can enter easily If noise enters the VPP pin abnormal instruction codes or data are read from the built in PROM which may cause a program runaway 3 4 2 Connection of a bypass capacitor across the 3 30 Vss line and th
253. rupt Valid when timer 2 interrupt is selected 9 INT4 interrupt FFED16 FFEC16 External interrupt active edge selectable Valid when INT4 interrupt is selected Timer 3 interrupt J 7 j l Valid when timer 3 interrupt is selected 10 CNTRo interrupt FFEB16 FFEA16 External interrupt active edge selectable 11 CNTR1 interrupt FFE916 FFE816 External interrupt active edge selectable 12 Serial 1 02 interrupt FFE716 FFE616 Valid when serial 1 02 is selected 13 INT2 interrupt FFE516 FFE416 External interrupt active edge selectable Valid when INT2 interrupt is selected Timer 1 interrupt g i Valid when timer 1 interrupt is selected 14 Timer A interrupt FFES316 FFE216 15 Timer B interrupt FFE116 FFEO16 16 A D conversion interrupt FFDFi6 FFDE16 Valid when A D interrupt is selected ADT interrupt p E g External interrupt only at falling edge Valid when ADT interrupt and A D external trigger valid are selected 17 BRK instruction interrupt FFDD1e FFDC16 Non maskable software interrupt Note Reset functions in the same way as an interrupt with the highest priority 1 62 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt Figure 65 shows a timing chart after an interrupt occurs and Figure 66 shows the time up to execu The interrupt processing routine begins with the tion of the interrupt processing routine machine cycle following the completion of the in structi
254. rupt edge selection register 2 34 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi b0 Interrupt request reigster 1 IREQ1 Address 3C e B Name Function Arese R w INTo interrupt request bit 0 No interrupt request 1 Interrupt request 1 INT interrupt request bit 0 No interrupt request 1 Interrupt request 2 Serial 1 O1 receive interrupt 9 No interrupt request request bit 1 Interrupt request 3 Serial 1 O1 transmit interrupt O No interrupt request request bit 1 Interrupt request 4 Timer X interrupt request bit 0 No interrupt request 1 Interrupt request 5 Timer Y interrupt request bit No interrupt request 1 Interrupt request Timer 2 INTs interrupt request 0 No interrupt request bit 1 Interrupt request 7 Timer 3 INTa interrupt request 0 No interrupt request bit 1 Interrupt request x 0 is set by software but not 1 Fig 2 3 11 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 bO Interrupt request reigster 2 IREQ2 Address 3D16 B Name Function Atrese CNTRo interrupt request bit 0 No interrupt request 1 Interrupt request CNTR interrupt request bit 0 No interrupt request 1 Interrupt request 2 Serial 1 02 interrupt request bit 0 No interrupt request 1 Interrupt request g Timer 1 INT2 interrupt 0 No interrupt re
255. s 1816 A Receive buffer full flag is set to O by reading data Check an error flag SIO1STS Address 1916 bite SIO1STS Address 1916 bit1 Check a completion of receiving Receive buffer full flag 1 Receive the second byte data A Receive buffer full flag is set to O by reading data Read out a reception data from RB Address 1816 Check an error flag Processing for error SIO1STS Address 1916 bite P4 Address 0816 bit2 0 SIO1CON Address 1A16 lt 0000X0012 SIO1CON Address 1A16 1010X0012 Countermeasure for a bit slippage Fig 2 3 42 Control procedure at a receiving side Communication using UART 3807 GROUP USER S MANUAL 2 61 APPLICATION 2 4 Real time output port 2 4 Real time output port RTP 2 4 1 Memory map of real time output port 00216 002818 002616 002Di6 002E6 002F16 003016 003116 003216 Fig 2 4 1 Memory map of real time output port related registers 2 4 2 Related registers Real time port register b7 b6 b5 b4 b3 b2 b1 bO Real time port register RTP Address 2A 6 Sets the data to be output to the Real time port m2 Makes it possible to write data into any of Real time port JO o registers 0 to 7 by specifying the Real time port data pointer R W pointer and writing data into this register e Makes it possible to read any data of Real time port registers 0 0 O O to 7
256. s The stack is used to store the current address data and processor status when branching to subroutines or interrupt rou tines The lower eight bits of the stack address are determined by the con tents of the stack pointer The upper eight bits of the stack address are determined by the Stack Page Selection Bit If the Stack Page Selection Bit is 0 then the RAM in the zero page is used as the stack area If the Stack Page Selection Bit is 1 then RAM in page 1 is used as the stack area The Stack Page Selection Bit is located in the SFR area in the zero page Note that the initial value of the Stack Page Selection Bit var ies with each microcomputer type Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig 6 Program counter PC The program counter is a 16 bit counter consisting of two 8 bit registers PCH and PCL It is used to indicate the address of the next instruction to be executed Accumulator Index Register X Index Register Y Stack Pointer Program Counter Processor Status Register PS Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Fig 5 740 Family CPU register structure Negative Flag 1 8 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL
257. s mode The timer is written to only during timer stop no measurement of pulse widths Since the timer latch in this mode is specialized for the read out of measured values do not perform any write operations during mea surement The timer value is set to FFFF 16 when the timer either underflows or a valid edge of pulse widths measurement is detected Due to that the timer value at the start of measurement depends on the timer value before the start of measurement Figure 22 shows the timing chart of the pulse width measurement mode 5 Programmable waveform generation mode Mode selection This mode can be selected by setting 100 to the following bits Timer X operating mode bit bits 2 to 0 of TXM Timer Y operating mode bit bits 2 to 0 of TYM Count source selection In high or middle speed mode f XiN 2 f XiN 16 or f Xcin can be Selected as the count source In low speed mode the count source is f XcIN Interrupt The interrupt generation at underflow is the same as already 3807 GROUP USER S MANUAL explained for the timer mode Explanation of operation Counting operation is the same as in timer mode Moreover the timer outputs the data set in the corresponding output level latch bit 4 of TXM or TYM to CNTRo CNTR1 pin each time the timer underflows After the timer underflows the generation of optional waveform from CNTROo CNTRt pin is possible through a change of values in the output level latch and timer
258. s products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMs etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 424 N SAS Renesas Techno
259. s timer B1 latch b7 bO EE Jer A Real time port control register 3 RTPCONS address 002E16 Real time port output selection bit P82 0 1 O port 1 Real time output port Real time port output selection bit P83 0 1 O port 1 Real time output port Real time port output selection bit P84 0 1 O port 1 Real time output port Real time port output selection bit P85 0 1 O port 1 Real time output port Real time port output selection bit P86 0 I O port 1 Real time output port Real time port output selection bit P87 0 I O port 1 Real time output port Real time port output selection bit P30 0 1 O port 1 Real time output port Real time port output selection bit P31 0 I O port 1 Real time output port Fig 30 Structure of Real time output port related register 2 1 38 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Timer A operating mode selection bit in case of 8 repeated load mode 4 4 port division Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts Timer count source stop bit Timer A count value Port P82 RTPo Port P83 RTP1 Port P84 RTP2 Port P85 RTP3 Hi i H i i i H i H H H Realtime poar pipin ex 2 Y 1 o 7 6 5 7 0 Data of real time port registers 7 to 0 Fig 31 8 repeated load mod
260. s value can be disregarded Select the P74 AN pin as an analog input pin ADCON Address 3416 lt X1X100012 External trigger is valid P7D Address OF 6 XXX00XXX P73 Srpy2 ADT ANo pin Input mode Check the start of A D conversion Check the completion of A D conversion Read out AD Address 3516 Read out the conversion result Fig 2 5 11 Control procedure Read for analog signal using an external trigger 2 86 3807 GROUP USER S MANUAL APPLICATION 2 6 Reset 2 6 Reset 2 6 1 Connection example of reset IC Power source M62022L 3807 group Fig 2 6 1 Example of Poweron reset circuit Figure 2 6 2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt System power source voltage 5 M62009L M62009P M62009FP Fig 2 6 2 RAM back up system 3807 GROUP USER S MANUAL 2 87 APPLICATION 2 7 Application circuit example 2 7 Application circuit example Refer to the following applicaion circuit examples using the 3807 group microcomputer Hot water supply system application example e Figure 2 7 1 CD changer car audio application example sse Figure 2 7 2 e Hot water washing toilet seat applicaiton example ssseeeeeeene Figure 2 7 3 2 88 3807 GROUP USER S MANUAL APPLICATION 2 7 App
261. set to 0016 at least for a short time timer X timer Y interrupt request does not occur When the value set to the timer latch is 0016 the value is unde fined since the timer counts down by dummy count operation Figure 25 shows the timing chart of the PWM mode 1 25 HARDWARE FUNCTIONAL DESCRIPTION Precautions regarding all modes Timer X timer Y writing control One of the following operation is selected by bit 3 of TXM or TYM for timer X or timer Y Writing data to the corresponding latch and timer at the same time Writing data to only corresponding latch When the operation writing data to only corresponding latch is selected the value is set to the timer latch by writing a value to timer X Y address and a timer is renewed at the next underflow After releasing a reset writing the corresponding latch and timer at the same time is selected When a value is written to timer X Y address a value is set to a timer and a timer latch at the same time When writing data to only corresponding latch is selected if writ ing to a reload latch and an underflow are performed at the same timing the timer value is undefined Timer X timer Y read control In pulse period measurement mode and pulse width measurement mode the timer value cannot be read out In all other modes read out operations without effect to count operations stops are possible However the timer latch value cannot be read out Precautions regarding the C
262. ster 3 ele Real time port register 4 Real time port register 5 Real time port register 6 Real time port register 7 res Td 1 Specify the Timer A1 latch Note 1 Use LDM or STA instruction for specifying the Real time port data pointer A when this bit is switched When this bit is read 1 is always read out 2 When these bits are read an output pointer is read out 20000 c oOunoOaooaot Fig 2 4 4 Structure of Real time port control register 1 2 64 3807 GROUP USER S MANUAL APPLICATION 2 4 Real time output port Real time port control register 2 b7 b6 b5 b4 b3 b2 b1 bO ITITI Real time port control register 2 RTPCON2 Address 2D16 Timer B operating mode 8 repeated load mode selection bits 6 repeated load mode 5 repeated load mode One shot pulse generation mode Real time port data pointer B 0 R W pointer switch bit Note 1 Output pointer Timer B interrupt mode Interrupts occur when a Real selection bit time port output pointer value becomes 0002 1 Interrupt request occurs in spite of a Real time port output pointer value Real time port register 0 ola Real time port register 1 Real time port register 2 Real time port register 3 s loja Real time port register 4 Real time port register 5 Real time port register 6 Real time port register 7 res Td 1 Specify the Timer B1 latch Note 1 Use LDM or STA instruction for specifyin
263. sting of One Time PROM version 3807 GROUP USER S MANUAL 1 61 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt 3807 group permits interrupts on the basis of 16 requests occur during the same sampling the higher priority interrupt is accepted first This priority is determined by hardware but variety of priority processing can be performed by software using an sources It is vector interrupts with a fixed priority system Accordingly when two or more interrupt interrupt enable bit and an interrupt disable flag For interrupt sources vector addresses and inter rupt priority refer to Table 11 Table 11 Interrupt sources vector addresses and interrupt priority Vector addresses Priority Interrupt sources Remarks High order Low order 1 Reset Note FFFD16 FFFC16 Non maskable 2 INTO interrupt FFFB16 FFFA16 External interrupt active edge selectable 3 INT1 interrupt FFF916 FFF816 External interrupt active edge selectable 4 Serial l O1 receive interrupt FFF716 FFF616 Valid when serial 1 01 is selected 5 Serial 1 01 transmit interrupt FFF516 FFF416 Valid when serial l O1 is selected 6 Timer X interrupt FFF316 FFF216 7 Timer Y interrupt FFF 116 FFFO16 8 INT3 interrupt FFEFie FFEE16 External interrupt active edge selectable E p E 7 Valid when INTs interrupt is selected Timer 2 inter
264. stop bit during reception 2 The transmit interrupt TI can be selected to occur when either the TBE or TSC flag becomes 1 depending on the setting of the transmit interrupt source selection bit TIC of the serial 1 01 control register 3 The receive interrupt RI is set when the RBF flag becomes 1 4 After data is written to the transmit buffer register when TSC 1 0 5 to 1 5 cycles of the data shift cycle is necessary until changing to TSC 0 Fig 38 Operation of UART serial 1 01 function 1 42 3807 GROUP USER S MANUAL Transmit Buffer Register Receive Buffer Register TB RB 001816 The transmit buffer and the receive buffer are located in the same address The transmit buffer is write only and the receive buffer is read only If a character bit length is 7 bits the MSB of data stored in the receive buffer is 0 Serial I O 1 Status Register SIO1STS 001916 The read only serial 1 O1 status register consists of seven flags b0 to b6 which indicate the operating status of the serial 1 O1 function and various errors Three of the flags b4 to b6 are only valid in UART mode The receive buffer full flag b1 is cleared to 0 when the receive buffer is read The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register and the receive buffer full flag is set A writing to the serial I O1 status regis ter clears all the error flags OE PE FE
265. surement mode Programmable waveform generation mode 1 Programmable one shot M oia mode PWM mode Not available sperme pem e dz To only latch H output 7 depende on the operating mode of the Timer X refer to Table 3 5 1 Timer X count source selection 0 0 f Xmy 2 bits f Xin 16 f Xcin Input signal from CNTRo pin Fig 3 5 20 Structure of Timer X mode register Timer Y mode register b7 b6 b5 b4 b3 b2 b1 bO LITT Tt TI Timer Y mode register TYM Address 2816 Timer Event counter mode Pulse output mode Pulse period measurement mode Pulse width measurement mode Programmable waveform generation mode Programmable one shot generation mode PWM mode Not available Old c CR To only latch 4 Output level latch L output i H output 5 CNTR1 active edge switch bit lt depends on the operating mode of the Timer Y refer to Table 3 5 1 lo Timer Y count source selection O 0 f Xin 2 o fofo bits f XiN 16 Et e Tele Input signal from CNTRt pi Fig 3 5 21 Structure of Timer Y mode register 3 44 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Table 3 5 1 Function of CNTRo CNTR1 edge switch bit Operating mode of Function of CNTRo CNTR1 edge switch bit Timer X Timer Y bit 5 of each address 2716 and 2816 Timer mode ql Generation of CNTRo CNTR1 interrupt request Falling edge No effect on timer count e G
266. synchronous serial I O is selected External clock input 16 UART is selected SnDv1 output enable bit SRDY 0 P47 pin operates as ordinaly I O pin 1 P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit TIC 0 Interrupt when transmit buffer has emptied 1 Interrupt when transmit shift operation is completed Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled Receive enable bit RE 0 Receive disabled 1 Receive enabled Serial l O1 mode selection bit SIOM 0 Asynchronous serial I O UART 1 Clock synchronous serial I O Serial l O1 enable bit SIOE 0 Serial 1 01 disabled pins P44 to P47 operate as ordinary I O pins 1 Serial 1 01 enabled pins P44 to P47 operate as serial I O pins 3807 GROUP USER S MANUAL 1 43 HARDWARE FUNCTIONAL DESCRIPTION Serial 1 02 The serial 1 02 can be operated only as the clock synchronous type As a synchronous clock for serial transfer either internal clock or external clock can be selected by the serial 1 02 synchronous clock selection bit b6 of serial 1 02 control register 1 The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selec tion bit b2 b1 bO of serial 1 02 control register 1 Regarding Sour and ScLk2 being output pins either CMOS output format or N channel open drain output format can be selected by the P71 Soure P72 ScLk2 P channel
267. t b5 of IREQ1 are set to 1 Explanation of operation PWM waveform is output from CNTRo pin in case of timer X or from CNTRt pin in case of timer Y The H interval of PWM waveform is determined by the setting value m m 0 to 255 of TXH and TYH and the L interval of PWM waveform is determined by the setting value n n 0 to 255 of TXL and TYL The PWM cycles are PWM cycle time m n ts PWM duty m m n where ts period of timer X timer Y count source During count operation stop When a timer value is set to TXL TXH TYL TYH by writing data to timer and timer latch at the same time When setting this value the output of CNTRo ONTRt pin is initialized to the H level During count operation enabled By setting the bit O or 1 of TXYCON to 0 an H interval of TXH or TYH is output first and after that a L level interval of TXL or TYL are output next These operations are repeated continuously The PWM output is changed after the underflow by setting a timer value which is set by writing data to the timer latch only to TXL TXH TYL TYH Precautions Set the double function port of CNTRo CNTRt pin to output in this mode This mode is unused in low speed mode e When the PWM H interval is set to 0016 PWM output is L When the PWM L interval is set to 0016 PWM output is H e When the PWM H interval and L interval are set to 0016 PWM output is L When a PWM H interval or L interval is
268. t at rising edge Fig 22 Timing chart of Pulse width measurement mode 1 30 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION FFFF16 T3 L T2 T1 w Pere A Signal output from T1 T3 T2 CNTR L Initial value of timer TR Timer interrupt request CNTR CNTRo CNTR1 interrupt request This example s condition CNTRo CNTR1 active edge switch bit set to O gt output starts with L level interrupt at falling edge Fig 23 Timing chart of Programmable waveform generating mode FFFF16 Signal input from INTo INT pin Signal output from MU Ll oo CNTRo CNTRt pin L L L CNTR CNTR L One shot pulse width timer latch value TR timer interrupt request CNTR CNTRo ONTR interrupt request This example s condition CNTRo CNTRi active edge switch bit set to 0 gt output a H pulse interrupt at falling edge Fig 24 Timing chart of Programmable one shot generating mode 3807 GROUP USER S MANUAL 1 31 HARDWARE FUNCTIONAL DESCRIPTION t Timer X Timer Y gt count source Timer X Timer Y PWM output signal TR CNTR CNTRo ONTRt interrupt request TR Timer interrupt request PWM waveform duty m m n and period m n X ts is output m the setting value of TXH TYH m 0 to 255 n the setting value of TXL TYL n 0 to 255 ts the period of timer X timer Y count source This example s condition CNTRo CNTRi active edge switch bit set to 0 o
269. t register O 001 indicates real time port register 1 010 indicates real time port register 2 011 indicates real time port register 3 100 indicates real time port register 4 101 indicates real time port register 5 110 indicates real time port register 6 111 indicates real time port register 7 Timer A write pointer 0 indicates timer AO latch 1 indicates timer A1 latch Fig 29 Structure of Real time output port related register 1 3807 GROUP USER S MANUAL 1 37 HARDWARE FUNCTIONAL DESCRIPTION Real time port control register 2 RTPCONe address 002D16 Timer B operating mode selection bit 00 8 repeated load mode 01 6 repeated load mode 10 5 repeated load mode 11 One shot pulse generating mode Real time port data pointer B switch bit 1 at read out 0 R W pointer 1 Output pointer Timer B interrupt mode selection bit 0 Interrupt request occurs with RTP output pointer value 0002 1 Interrupt request occurs regardless of RTP output pointer value Real time port data pointer B output pointer value at read out 000 indicates real time port register 0 001 indicates real time port register 1 010 indicates real time port register 2 011 indicates real time port register 3 100 indicates real time port register 4 101 indicates real time port register 5 110 indicates real time port register 6 111 indicates real time port register 7 Timer B write pointer 0 indicates timer BO latch 1 indicate
270. t to 1 it cannot be rewritten to 0 by program This bit is cleared to 0 after resetting Zi Data bus FF16 is set when watchdog timer control register is Main clock division Watchdog timer L 8 written to Watchdog timer H 8 ratio selection bits lt 1 16 Note 00 r o Watchdog timer H count p gt o1 STP instruction disable bit STP instruction source selection bit Reset internal reset J circuit ss O dz Note Either high speed middle speed or low speed mode is selected by bits 7 and 6 of CPU mode register Fig 50 Block diagram of Watchdog timer Watchdog timer control register WDTCON address 001716 Watchdog timer H for read out of high order 6 bit STP instruction disable bit 0 STP instruction enabled 1 STP instruction disabled Watchdog timer H count source selection bit 0 Watchdog timer L underflow 1 f XiN 16 or f XciN 16 Fig 51 Structure of Watchdog timer control register 1 50 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Clock output function The internal clock can be output from I O port P34 Control of I O ports and clock output function can be performed by port P2P3 control register address 001516 bO _ Port P2P3 control register eee address 001516 P34 clock output control bit 0 I O port 1 Cloc
271. t2 t20 t20 t20 1120 Timer A interrupt request i j i j j i j Timer A setting value t3 t4 t20 t20 t20 t20 t19 t18 A Timer A count Stop Timer X count Start B Timer X count Stop RTP output Port output Use the same setting method for RTP4 RTP7 Timer B Numbers 0 to 7 indicate Real time port registers 0 to 7 The output pointer value bits 6 to 4 of real time port control register 1 is decreased by 1 at each underflow of the Timer A Thus the current output pointer value which is read out indicates the next Real time port register to be output The L level is output after the timer stops Thus the last output is executed by creating time by software Timer X after the stop of the timer and switching over the real time output port to the programmable I O port For the reason that if the Timer A is stopped during or after an interrupt caused at the termination of the last output the next data data of Real time port register 7 is output in a short period from the underflow of the Timer A to the count stop of the Timer A To continue to output the last output data after the timer stops just stop the count of the timer after termination of the last output Set the timer values t1 and t2 before an RTP output Fig 2 4 14 Setting method and output timing 3807 GROUP USER S MANUAL 2 71 APPLICATION 2 4 Real time output port Real time port register Address 2A16 b7 bo RTP ____ Sets the data
272. tack 3807 GROUP USER S MANUAL 2 17 APPLICATION 2 2 Timer 3 Timer application example 2 Piezoelectric buzzer output Outline The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output Specifications The rectangular waveform resulting from dividing clock f XIN 8 MHz into about 2 kHz 2049 Hz is output from the P54 CNTRo pin The level of the P54 CNTRo pin fixes to H while a piezoelectric buzzer output is stopped Figure 2 2 17 shows an example of a peripheral circuit and Figure 2 2 18 shows a connection of the timer and setting of the division ratio NE Lu H level is output while a piezoelectric buzzer output is stopped CNTRo output 3807 group P54 CNTRo 244 V 244 us N a division ratio so that the underflow output cycle of the Timer X becomes this value Fig 2 2 17 Example of a peripheral circuit Timer X count source selection bit Timer X f Xin 8 MHz 1 16 1 122 Fig 2 2 18 Connection of the timer and setting of the division ratio Piezoelectric buzzer output 2 18 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer Timer X mode register Address 2716 b7 bO nw ofifo fo ofo 1 Timer X operating mode bits Pulse output mode gt Timer X write control bit Write to a latch and a timer at the same time gt CNTRo active edge switch bit Output from the H level gt Timer X count source selection bits f Xi
273. te operation for real time port control register O with any purpose other than stopping the timer count is performed concurrently with the generation of a start trigger be sure to use such an instruction for writing 0 into the timer A B count source stop bit as the LDM STA instruction Even if 0 is written into the timer A B count source stop bit the timer count remains in the stop state without change When the timing for writing to the high order side reload latch is almost equal to the underflow timing an undesirable value may be set in the timer A or timer B lf the real time output port is selected by real time port control regis ter 3 after resetting L is output from this pin until a start trigger is generated 3807 GROUP USER S MANUAL 1 35 HARDWARE FUNCTIONAL DESCRIPTION Timer A write CIN H pointer 1 Z Timer A B poimer t count source 3 0 selection bit Timer A 1H latch 8 Timer A 1L latch 8 Main clock division ratio selection bits 7 o Timer A OH latch 8 Timer A OL latch 8 qe i of Timer A interrupt oe Di Timer A 16 Timer A interrup H request Timer A count i F P31 RTP7 O P31 latch source stop bit Timer A read out latch 8 Real time output Timer B write Real time port output selection bit P31 z XE pointer 1 HCE Timer B 1H latch 8 Timer B 1L latch 8 P31 direction register Timer B OH latch 8 Timer B OL latch 8
274. ted register HARDWARE FUNCTIONAL DESCRIPTION All bits of the serial l O1 status register are initialized to 0 at reset but if the transmit enable bit b4 of the serial 1 01 control register has been set to 1 the transmit shift register shift completion flag b2 and the transmit buffer empty flag b0 become 1 Serial 1 01 Control Register SIO1CON 001416 The serial 1 O1 control register contains eight control bits for serial 1 01 functions UART Control Register UARTCON 001B16 The UART control register consists of four control bits bO to b3 which are valid when asynchronous serial I O is selected and set the data format of an data transfer One bit in this register b4 is always valid and sets the output structure of the P45 TxD pin Baud Rate Generator BRG 001C16 The baud rate generator determines the baud rate for serial transfer With the 8 bit counter having a reload register the baud rate genera tor divides the frequency of the count source by 1 n 1 where n is the value written to the baud rate generator Serial 1 01 control register SIO1CON address 001A16 L BRG count source selection bit CSS 0 f XiN f XciN in low peed mode 1 f XiN 4 Xcin 4 in low speed mode Serial l O1 synchronous clock selection bit SCS 0 BRG 4 when clock synchronous serial I O is selected BRG 16 UART is selected 1 External clock input when clock
275. ter rupt request bits can be cleared by software but cannot be set by software The BRK instruction interrupt and reset cannot be disabled with any flag or bit The flag disables all interrupts except the BRK instruction interrupt and reset If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first 2 Interrupt Operation Upon acceptance of an interrupt the following operations are auto matically performed 1 The processing being executed is stopped 2 The contents of the program counter and processor status reg ister are automatically pushed onto the stack 3 Concurrently with the push operation the interrupt jump desti nation address is read from the vector table into the program counter 4 The interrupt disable flag is set and the corresponding inter rupt request bit is cleared Notes on Use When the active edge of an external interrupt INTo INT4 CNTRo or CNTR1 is set or the timer INT interrupt source and the ADT A D conversion interrupt source are changed the corresponding interrupt request bit may also be set Therefore please take follow ing sequence 1 Disable the external interrupt which is selected 2 Change the active edge in interrupt edge selection register in case of CNTRo Timer X mode register in case of CNTR1 Timer Y mode register 3 Clear the set interrupt request bit to 0 4 Enable the external interrupt which is selected 1 20 3807
276. terrupt and an end of the input pulse H level is detected by CNTRo interrupt Specifications The H level width of FG pulse input to the P54 CNTRo pin is counted by Timer X Example When the clock frequency is 8 MHz the count source would be 2 us that is obtained by dividing the clock frequency by 16 Measurement can be made up to 131 072 ms in the range of FFFF16 to 000016 Figure 2 2 25 shows a connection of the timer and setting of the division ratio and Figure 2 2 26 shows a setting of related registers Timer X count source Timer X Timer X interrupt selection bit request bit 9 8 Me 1118 1165536 131 072 ms 0 No interrupt request 1 Interrupt request Fig 2 2 25 Connection of the timer and setting of the division ratio Measurement of pulse width 3807 GROUP USER S MANUAL 2 25 APPLICATION 2 2 Timer Timer X mode register Address 2716 b7 b0 rem o vjo Jojo El y Timer X operating mode bits Pulse width measurement mode gt Timer X write control bit Write to a latch and a timer at the same time gt CNTRo active edge switch bit Measure the H level width gt Timer X count source selection bits f Xin 16 Timer XY control register Address 1416 txycon EM Timer X stop control bit Stop counting set this bit to 0 at starting counting Timer X High order Address 2116 b7 bo l TXH FFi6 Md X Low order Address
277. ters the masking confirmation mask ROM version and mark specifications which are to be submitted when ordering 2 Structure of register The figure of each register structure describes its functions contents at reset and attributes as follows Note 2 Bits Bit attributes Note 1 b7 b6 b5 b4 b3 b2 bi bO Contents immediately after reset release AO CPU mode register CPUM Address 3B e 0 Single eie mode Stack page selection bit TENE a fats 3 Nothing arranged for these bits These are write disabled MN TES 4 bits When these bits are read out the contents are 0 Fix this bit to 0 6 Main clock Xw Xour stop bit V S pes OO Xww Xour selected Internal system clock selection bit BR Xcour selected oio m Bit in which nothing is arranged Bit that is not used for control of the corresponding function Note 1 Contents immediately after reset release Q 0 at reset release 1279941 at reset release Undefined Undefined or reset release zk Contents determined by option at reset release Note 2 Bit attributes The attributes of control register bits are classified into 3 bytes read only write only and read and write In the figure these attributes are represented as follows Resesee Read WeeeeesWrite OveeeeeRead enabled O Write enabled XeeeeesRead disabled X eseeeeWrite disabled LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS 38
278. the timer and timer count operation starts External start trigger input l INT4 Timer count source stop bit Counting stops when timer i Counting stops when timer 4 AO latch has underflow H 4 AO latch has underflow Timer A count value Port P82 RTPo Port P83 RTP1 Real time port output pointer A 2 0 Data of real time port registers 2 to 0 Fig 34 One shot pulse generating mode operation 1 40 3807 GROUP USER S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Serial I O 1 Clock Synchronous Serial I O Mode OSerial 1 01 Clock synchronous serial l O1 mode can be selected by setting the Serial l O1 can be used as either clock synchronous or asynchro serial l O1 mode selection bit b6 of the serial 1 01 control register nous UART serial I O A dedicated timer baud rate generator is to 1 For clock synchronous serial I O the transmitter and the also provided for baud rate generation during Serial 1 01 opera receiver must use the same clock for serial l O1 operation If an tion internal clock is used transmit receive is started by a write signal to the Transmit Receive buffer register TB RB address 001816 Data bus Serial I O 1 control register Address 001A16 Address 001816 Receive buffer register EE ci full flag RBF P44 RxDO Receive shift register Receive interrupt request RI A
279. timer so that the clock counts up every 25 ms Specifications e The clock f XIN 8 MHz is divided by a timer The clock is counted at intervals of 25 ms by the Timer 3 interrupt Figure 2 2 14 shows a connection of timers and a setting of division ratios Figures 2 2 15 show a setting of related registers and Figure 2 2 16 shows a control procedure Timer 1 Timer 3 Timer 3 interrupt request bit The clock is divided by 40 by software 25 ms 1 second 0 No interrupt request 1 Interrupt request Fig 2 2 14 Connection of timers and setting of division ratios Clock function 3807 GROUP USER S MANUAL 2 15 APPLICATION 2 2 Timer INTEDGE IREQ1 Timer 123 mode register Address 2916 bo b7 gt Timer 3 count source selection bit Output signal from Timer 1 Timer 1 count source selection bits f Xin 16 Timer 1 Address 2416 b7 bo Timer 3 Address 2616 b7 bo Set division ratio 1 Interrupt edge selection register Address 3A16 PET TT ETT Timer 3 INT4 interrupt sources bit Timer 3 interrupt Interrupt control register d Address 3E16 b7 APO Interrupt request di Address 3C16 b7 gt Timer 3 INT4 interrupt enable bit Interrupt enabled gt Timer 3 INT4 interrupt request bit becomes 1 every 25 ms Fig 2 2 15 Setting of related registers Clock function 2 16 3807 GROUP USER S MANUAL APPLICATION 2 2 Timer Control proc
280. tion execute at least one instruction before ex ecuting a SEC CLC or CLD instruction In decimal mode the values of the negative N overflow V and zero Z flags are invalid Timers If a value n between 0 and 255 is written to a timer latch the fre quency division ratio is 1 n 1 Multiplication and Division Instructions The index X mode T and the decimal mode D flags do not affect the MUL and DIV instruction The execution of these instructions does not change the contents of the processor status register Ports The contents of the port direction registers cannot be read The following cannot be used The data transfer instruction LDA etc The operation instruction when the index X mode flag T is 1 The addressing mode which uses the value of a direction register as an index The bit test instruction BBC or BBS etc to a direction register The read modify write instructions ROR CLB or SEB etc to a direction register Use instructions such as LDM and STA etc to set the port direction registers Serial I O In clock synchronous serial I O if the receive side is using an external clock and it is to output the SRDY1 signal set the transmit enable bit the receive enable bit and the SRDY1 output enable bit to my Serial 1 01 continues to output the final bit from the TxD pin after transmission is completed Soure pin for serial l O2 goes to high im pedance after transfer is completed
281. to the microcomputer which causes noise to an analog input pin If a capacitor between an analog input pin and the Vss pin is grounded at a position far away from the Vss pin noise on the GND line may enter a micro computer through the capacitor 3 4 4 Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals 1 Keeping an oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance 2 Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin line may affect other lines at signal rising or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a progra
282. tting examples of Baud rate generator values and transfer bit rate values at f XIN 7 3728 MHz Transfer bit BRG count at f XIN 4 9152 MHz at f XIN 8 MHz b 1 ue 2 BRG setting value Actual time bps BRG setting value Actual time bps BRG setting value Actual time bps 600 f XIN 4 127 7F 16 600 00 191 BF16 600 00 207 CF16 600 96 1200 f XIN 4 63 3F16 1200 00 95 5F16 1200 00 103 6716 1201 92 2400 f XIN 4 31 1F16 2400 00 47 2F16 2400 00 51 3316 2403 85 4800 f XIN 4 15 0F16 4800 00 23 1716 4800 00 25 1916 4807 69 9600 f XIN 4 7 0716 9600 00 11 0B16 9600 00 12 0C16 9615 38 19200 f XIN 4 3 0316 19200 00 5 0516 19200 00 5 0516 20833 33 38400 f XIN 4 1 0116 38400 00 2 02 16 38400 00 2 0216 41666 67 76800 f XIN 3 0316 76800 00 5 0516 76800 00 5 0516 83333 33 31250 f XIN 15 0F16 31250 00 62500 f XIN 7 0716 62500 00 Notes 1 Equation of transfer bit rate f XIN Transfer bit rate bps m when bit O of the Serial l O1 control register Address of m is 1 when bit O of the Serial l O1 control register Address of m is 4 BRG setting value 1 X 16 X m 1A16 is set to 0 a value 1A16 is set to 1 a value 2 A BRG count source is selected by bit O of the Serial lI O1 control register Address 1A16 3807 GROUP USER S MANUAL 2 57 APPLICATION 2 3 Serial I O Transmitting side Serial 1 O1 sta
283. tus register Address 1916 SIO1STS L Transmit buffer empty flag Check to be transferred data from the Transmit buffer register to the Transmit shift register Writable the next transmission data to the Transmit buffer register at being setto 1 gt Transmit shift register shift completion flag Check a completion of transmitting 1 byte data with this flag 4 Transmit shift completed Serial 1 O1 control register Address 1A16 b7 bo SIO1CON 1 polo 1 0 0 1 BRG count source selection bit f XIN 4 Serial l O1 synchronous clock selection bit BRG 16 SRDY1 output enable bit Not use SRDY1 output Transmit enable bit Transmit enabled gt Receive enable bit Receive disabled Serial l O1 mode selection bit Asynchronous serial I O UART Serial l O1 enable bit Serial l O1 enabled UART control register Address 1B16 bo b7 uartcon ols jojo Character length selection bit 8 bits Parity enable bit Parity checking disabled Stop bit length selection bit 2 stop bits P45 TxD P channel output disable bit CMOS output Baud rate generator Address 1C16 b7 b0 f XIN 7 BRG 7 O SRI Transfer bit rate X 16 X m when bit 0 of the Serial 1 01 control register Address 1A16 is set to 0 a value of m is 1 when bit 0 of the Serial 1 01 control register Address 1A16 is set to 1 a value of m is 4 Port P4 direction register Address 0916
284. uipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under cert
285. underflow loto Source selection bit 1 f Xin 16 or f Xcin 16 Note When this bit is set to 1 it is not rewritten to 0 by software Fig 3 5 8 Structure of Watchdog timer control register 3807 GROUP USER S MANUAL 3 37 APPENDIX 3 5 List of registers Transmit Receive buffer register b7 b6 b5 b4 b3 b2 b1 bO LITT TTT Transmit Receive buffer register TB RB Address 1816 A transmission data is written to or a receive data is read out from this buffer register At writing a data is written to the Transmit buffer register At reading a content of the Receive buffer register is read out Note A content of the Transmit buffer register cannot be read out A data cannot be written to the Receive buffer register Fig 3 5 9 Structure of Transmit Receive buffer register Serial 1 01 status register b7 b6 b5 b4 b3 b2 bi b0 Serial 1 01 status reigster SIO1STS Address 1916 Ww Eee B Name Function atreset R W Transmit buffer empty flag 0 Buffer full x TBE 1 Buffer empty Receive buffer full flag RBF e Buffer empty x o Transmit shift register shift o Transmit shift in progress completion flag a Transmit shift completed Overrun error Parity error Framing IPETU Summing error flag SE 0 ee DIE 1 7 Nothing is allocated for this bit It is a write disabled bit When this bit is read out the value is 0 Fig 3 5 10 Structure of Serial
286. ure ment mode and pulse width measurement mode 1 A value is read out from high order first 1 Jojo ojo efe Fig 3 5 17 Structure of Timer X Low order Timer X High order Timer Y Low order Timer Y High order Timer 1 Timer 3 b7 b6 b5 b4 b3 b2 b1 bO Timer 1 T1 Timer 3 T3 E 2416 2616 O e A count value of each Timer is set A value set in this register is written to both each Timer and a corresponding Timer latch at the same time 3 When this register is read out a value count value of a corresponding Timer is read out Fig 3 5 18 Structure of Timer 1 Timer 3 3 42 3807 GROUP USER S MANUAL APPENDIX 3 5 List of registers Timer 2 b7 b6 b5 b4 b3 b2 bi bO Timer 2 T2 Address 2516 Ojea count value of Timer 2 is set toto e A value set in this register is written to both Timer 2 and a 0 lolol corresponding Timer 2 latch at the same time or to only 0 lolol Timer 2 latch 0 olo When this register is read out a value count value of a 0 Tolo corresponding Timer 2 is read out 0 Tolo ENSE 0 o o Fig 3 5 19 Structure of Timer 2 3807 GROUP USER S MANUAL 3 43 APPENDIX 3 5 List of registers Timer X mode register b7 b6 b5 b4 b3 b2 b1 bO LEE IET Timer X mode register TXM Address 2716 Timer Event counter mode 1 Pulse output mode Pulse period measurement mode 1 Pulse width mea
287. us register PS The processor status register is an 8 bit register consisting of flags which indicate the status of the processor after an arithmetic opera tion Branch operations can be performed by testing the Carry C flag Zero Z flag Overflow V flag or the Negative N flag In deci mal mode the Z V N flags are not valid After reset the Interrupt disable lI flag is set to 1 but all other flags are undefined Since the Index X mode T and Decimal mode D flags directly affect arithmetic operations they should be initialized in the beginning of a program 1 Carry flag C The C flag contains a carry or borrow generated by the arithmetic logic unit ALU immediately after an arithmetic operation It can also be changed by a shift or rotate instruction 2 Zero flag Z The Z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 and cleared if the result is anything other than 0 3 Interrupt disable flag I The flag disables all interrupts except for the interrupt generated by the BRK instruction Interrupts are disabled when the flag is 1 When an interrupt occurs this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced 4 Decimal mode flag D The D flag determines whether additions and subtractions are executed in binary or decimal Binary arithmetic is executed when this flag is 0
288. utput starts with H level interrupt at falling edge Fig 25 Timing chart of PWM mode 1 32 3807 GROUP USER S MANUAL Timer 1 Timer 2 Timer 3 Timer 1 to 3 are 8 bit timers for which the count source can be se lected through timer 123 mode register 1 Timer 2 write control Timer 2 write control bit b2 of timer 123 mode register allows to select whether a value written to timer 2 is written to timer latch and timer synchronously or to the timer latch only If only the timer latch is written to the value is set only to the reload latch by writing a value to the timer address at that time The content of timer is reloaded with the next underflow Usually writing operation to the timer latch and timer synchronously is selected And a value is written to the timer latch and timer synchronously when a value is written to the timer address If only the timer latch is written to it may occur that the value set to the counter is not constant when the timing with which the reload latch is written to and the underflow timing is nearly the same 2 Timer 2 output control When timer 2 output Tour is enabled inverted signals are output from Tour pin each time timer 2 has underflow For this reason set the double function port of Tour pin to output mode WiPrecautions on timers 1 to 3 When the count source for timer 1 to 3 is switched it may occur that short pulses are generated in count signals and that the timer count
289. when a port which is set as an output port is changed for an input port its port latch holds the output data Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction its value may be changed in case where content of the pin differs from a content of the port latch bit managing instructions SEB and CLB instruction 3 The AVss pin when not using the A D converter When not using the A D converter handle a power source pin for the A D converter AVSS pin as follows O AVss Connect to the Vss pin Reason If the AVSs pin is opened the microcomputer may malfunction by effect of noise or others 3 3 6 Notes on memory expansion mode and microprocessor mode 1 Writing data to the port latch of port P3 In the memory expansion or the microprocessor mode ports P30 and P31 can be used as the output port Use the LDM or STA instruction for writing data to the port latch address 000616 of port P3 When using a read modify write instruction the SEB or the CLB instruction allocate the read and the write enabled memory at address 000616 Reason In the memory expansion or microprocessor mode address 000616 is allocated in the external area Accordingly O Data is read from the external memory O Data is written to both the port latch of the port P3 and the external memory Accordingly when executing a read modify write instruction for address 000616 external memory data is read and
290. xternal buffer when driving a low impedance load DA i output enable bit Note P56 DA P57 DA2 R P80 DA3 AN11 O o P81 DA4 AN12 1 D A i conversion register Note AVSS P65 DAVREF AN10 Note i 1 to 4 Fig 48 Equivalent connection circuit of D A converter 1 48 D A control register DACON address 003316 DA1 output enable bit DA output enable bit DAs output enable bit DA4 output enable bit Not used return 0 when read 0 Output disabled 1 Output enabled Fig 46 Structure of D A control register Data bus A1 conversion register 003616 D D A2 conversion register 003716 D A3 conversion register 003816 D A4 conversion register 003916 D A i conversion register 8 R 2R resistor ladder DA i output enable bit O P5e DA1 P57 DA2 P80 DA3 AN11 P81 DA4 AN12 Fig 47 Block diagram of D A converter 3807 GROUP USER S MANUAL Analog Comparator An analog comparator circuit which is independent of peripheral cir cuits in the microcomputer is incorporated Note An analog comparator outputs the result of comparison with an input voltage of CMPRrer pin which is specified as a reference voltage and an input voltage of CMPIN pin to CMPour pin The result is 1 when the input voltage to port CMP in is higher than the voltage applied to port CMPREF and 0 when the voltage is lower Because the analog comparator consists of an analog MOS circuit set the input voltage to the C
291. xternal clock input GA 21 Port P73 22 Port P51 Srbyz output enable bit Serial 1 02 I O comparison signal control bit Direction register r gt Direction register Data bus 4 gt Port latch zu Data bus Port latch 81 MW j Serial 1 02 I O comparison Serial 1 02 ready outpu signal output AD external trigger valid bit Interrrupt input A D trigger interrupt input A D conversion input o Analog input pin selection bit 23 Ports P82 P87 Real time port output selection bit Direction register Data bus gt Port latch Data for real time port Fig 14 Port block diagram 3 3807 GROUP USER S MANUAL 1 19 HARDWARE FUNCTIONAL DESCRIPTION Interrupts Interrupts occur by twenty sources eight external eleven internal and one software 1 Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit and is controlled by the interrupt disable flag An interrupt occurs if the corresponding interrupt request and enable bits are 1 and the interrupt disable flag is 0 Interrupt enable bits can be set or cleared by software In
292. y 11e 10H indio Jajeay JaJem WIEM INOX uonoojep emeuny 10 8 HLAM 119 8 1LAM su 09z uonnjoseJ apow jueuieinseeui ponad asing 19 91 A 43W L epouu indino asing 1a 91 X JWI su QGZ uonnjosae1 apow peo pejeedeu g 19 91 g saw su OGZ uonnjosei epouu peo peyeedai g 1q 91 v Jeu L 1 8 49w L 0o4Juo9 eseud uq 8 z seu 19 01JU09 3 0U9Y U01 9919P XN 19J2M WIEM uonoejep aBeyjon eoinos Jamod uonoalep aunyesedwe wooy uonoeljep eJnjeJeduiej 1ees 9110 y uoioejep eunje1eduuel JaJem uonoa p eunje1eduie 191 M z uoioejep eunje1eduuel 198M uonoejep eunjeJeduue JejeM q 8 3w L dnos6 08 jawe ex UO CO uonoejep uoriisod ajzzoN indui 9ounos J3MOA eroJeuluJ0 2 1895 19 101 DUIYSEM J9JEM WIEN Fig 2 7 3 Hot water washing toilet seat applicaiton example 2 91 3807 GROUP USER S MANUAL CHAPTER 3 APPENDIX 3 1 Electrical characteristics 3 2 Standard characteristics 3 3 Notes on use 3 4 Countermeasures against noise 3 5 List of registers 3 6 Mask ROM ordering method 3 7 Mark specification form 3 8 Package outline 3 9 Machine instructions 3 10 List of instruction codes 3 11 SFR memory map 3 12 Pin configuration APPENDIX 3 1 Electrical characteristics 3 1 Electrical characteristics 3 1 1 Absolute max
293. zcon2 o 1 t 1 L Optional transfer bits 8 bit transfer Serial 1 02 I O comparative signal control bit Not use Scmr2 output Interrupt control register 2 Address 3F 16 b7 bO Serial 1 02 interrupt enable bit Interrupt disabled Interrupt request register 2 Address 3D16 b7 bO Serial 1 02 interrupt request bit Using this bit check the completion of transmitting 1 byte base data 1 Transmit completion Port P5 Address 0A16 b7 b RENTER gt Set to 0 before starting to transmit Port P5 direction register Address 0B16 b7 bO PEt Ey gt P53 INT4 Output mode Fig 2 3 29 Setting of serial 1 02 related registers Output of serial data 3807 GROUP USER S MANUAL 2 49 APPLICATION 2 3 Serial I O Serial l O2 register Address 1F 16 b7 bO Set a transmission data Check that transmission of the previous data is completed before writing data bit 2 of the Interrupt request register 2 is set to 1 Fig 2 3 30 Setting of serial 1 02 transmission data Output of serial data 2 50 3807 GROUP USER S MANUAL APPLICATION 2 3 Serial I O Control procedure When the registers are set as shown in Fig 2 3 29 the Serial 1 02 can transmit 1 byte data simply by writing data to the Serial 1 02 register Thus after setting the CS signal to L write the transmission data to the Serial 1 01 register on a 1 byte base and return the CS signal to

3807 Group USER`S MANUAL

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